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open-power/snap | hardware/hdl/core/mmio_register.vhd | 1 | 4,835 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- True dual port, single clocked register
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mmio_register_2w2r IS
GENERIC (
WIDTH : integer := 16;
SIZE : integer := 512;
ADDR_WIDTH : integer := 9
);
PORT (
clk : IN std_logic;
we_a : IN std_logic;
addr_a : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
din_a : IN std_logic_vector(WIDTH-1 DOWNTO 0);
dout_a : OUT std_logic_vector(WIDTH-1 DOWNTO 0);
we_b : IN std_logic;
addr_b : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
din_b : IN std_logic_vector(WIDTH-1 DOWNTO 0);
dout_b : OUT std_logic_vector(WIDTH-1 DOWNTO 0)
);
END mmio_register_2w2r;
ARCHITECTURE mmio_register_2w2r OF mmio_register_2w2r IS
TYPE ram_t IS ARRAY (SIZE-1 DOWNTO 0) OF std_logic_vector(WIDTH-1 DOWNTO 0);
SHARED VARIABLE ram_v : ram_t;
BEGIN
mmio_register_2w2r_b: PROCESS (clk)
BEGIN -- PROCESS mmio_register
IF (rising_edge(clk)) THEN
IF (we_b = '1') THEN
ram_v(to_integer(unsigned(addr_b))) := din_b;
END IF;
dout_b <= ram_v(to_integer(unsigned(addr_b)));
END IF;
END PROCESS mmio_register_2w2r_b;
mmio_register_2w2r_a: PROCESS (clk)
BEGIN -- PROCESS mmio_register
IF (rising_edge(clk)) THEN
IF (we_a = '1') THEN
ram_v(to_integer(unsigned(addr_a))) := din_a;
END IF;
dout_a <= ram_v(to_integer(unsigned(addr_a)));
END IF;
END PROCESS mmio_register_2w2r_a;
END ARCHITECTURE;
-- Single write / dual read port, single clocked register
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mmio_register_1w2r IS
GENERIC (
WIDTH : integer := 16;
SIZE : integer := 512;
ADDR_WIDTH : integer := 9
);
PORT (
clk : IN std_logic;
we_a : IN std_logic;
addr_a : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
din_a : IN std_logic_vector(WIDTH-1 DOWNTO 0);
dout_a : OUT std_logic_vector(WIDTH-1 DOWNTO 0);
addr_b : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
dout_b : OUT std_logic_vector(WIDTH-1 DOWNTO 0)
);
END mmio_register_1w2r;
ARCHITECTURE mmio_register_1w2r OF mmio_register_1w2r IS
TYPE mem_t IS ARRAY (SIZE DOWNTO 0) OF std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL mem : mem_t;
BEGIN
mmio_register_1w2r: PROCESS (clk)
BEGIN -- PROCESS mmio_register
IF (rising_edge(clk)) THEN
IF (we_a = '1') THEN
mem(to_integer(unsigned(addr_a))) <= din_a;
END IF;
dout_a <= mem(to_integer(unsigned(addr_a)));
dout_b <= mem(to_integer(unsigned(addr_b)));
END IF;
END PROCESS mmio_register_1w2r;
END ARCHITECTURE;
-- Single port register
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mmio_register_1w1r IS
GENERIC (
WIDTH : integer := 16;
SIZE : integer := 512;
ADDR_WIDTH : integer := 9
);
PORT (
clk : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
din : IN std_logic_vector(WIDTH-1 DOWNTO 0);
dout : OUT std_logic_vector(WIDTH-1 DOWNTO 0)
);
END mmio_register_1w1r;
ARCHITECTURE mmio_register_1w1r OF mmio_register_1w1r IS
TYPE mem_t IS ARRAY (SIZE DOWNTO 0) OF std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL mem : mem_t;
BEGIN
mmio_register_1w1r: PROCESS (clk)
BEGIN -- PROCESS mmio_register
IF (rising_edge(clk)) THEN
IF (we = '1') THEN
mem(to_integer(unsigned(addr))) <= din;
END IF;
dout <= mem(to_integer(unsigned(addr)));
END IF;
END PROCESS mmio_register_1w1r;
END ARCHITECTURE;
| apache-2.0 | 11142e0a2fcd46c7a99a59d620ad32d9 | 0.596484 | 3.309377 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_8_0_0/RAT_Mux2x1_8_0_0_sim_netlist.vhdl | 2 | 4,463 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:46:24 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux2x1_8_0_0/RAT_Mux2x1_8_0_0_sim_netlist.vhdl
-- Design : RAT_Mux2x1_8_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux2x1_8_0_0_Mux2x1_8 is
port (
X : out STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Mux2x1_8_0_0_Mux2x1_8 : entity is "Mux2x1_8";
end RAT_Mux2x1_8_0_0_Mux2x1_8;
architecture STRUCTURE of RAT_Mux2x1_8_0_0_Mux2x1_8 is
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \X[0]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \X[1]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \X[2]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \X[3]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \X[4]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \X[5]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \X[6]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \X[7]_INST_0\ : label is "soft_lutpair3";
begin
\X[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(0),
I1 => A(0),
I2 => SEL,
O => X(0)
);
\X[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(1),
I1 => A(1),
I2 => SEL,
O => X(1)
);
\X[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(2),
I1 => A(2),
I2 => SEL,
O => X(2)
);
\X[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(3),
I1 => A(3),
I2 => SEL,
O => X(3)
);
\X[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(4),
I1 => A(4),
I2 => SEL,
O => X(4)
);
\X[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(5),
I1 => A(5),
I2 => SEL,
O => X(5)
);
\X[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(6),
I1 => A(6),
I2 => SEL,
O => X(6)
);
\X[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => B(7),
I1 => A(7),
I2 => SEL,
O => X(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux2x1_8_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC;
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Mux2x1_8_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Mux2x1_8_0_0 : entity is "RAT_Mux2x1_8_0_0,Mux2x1_8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Mux2x1_8_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Mux2x1_8_0_0 : entity is "Mux2x1_8,Vivado 2016.4";
end RAT_Mux2x1_8_0_0;
architecture STRUCTURE of RAT_Mux2x1_8_0_0 is
begin
U0: entity work.RAT_Mux2x1_8_0_0_Mux2x1_8
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
SEL => SEL,
X(7 downto 0) => X(7 downto 0)
);
end STRUCTURE;
| mit | 423ee6ce72a73de0864800ff2242dc85 | 0.56173 | 2.969395 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment3-Program_Counter/Testbenches/Exp_3_Prog-ROM_TB.vhd | 1 | 2,982 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 09/19/2017 11:39:07 PM
-- Design Name:
-- Module Name: Exp_3_Prog-ROM_TB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Program Counter & Program ROM integration Test Bench
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Exp_3_Prog_ROM_TB is
end Exp_3_Prog_ROM_TB;
architecture Behavioral of Exp_3_Prog_ROM_TB is
COMPONENT Program_Counter
PORT(
FROM_IMMED : IN std_logic_vector(9 downto 0);
FROM_STACK : IN std_logic_vector(9 downto 0);
PC_MUX_SEL : IN std_logic_vector(1 downto 0);
PC_LD : IN std_logic;
PC_INC : IN std_logic;
RST : IN std_logic;
CLK : IN std_logic;
PC_COUNT : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
COMPONENT prog_rom
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
END COMPONENT;
--Inputs
signal PC_MUX_SEL_tb : std_logic_vector(1 downto 0) := "00";
signal PC_LD_tb : std_logic := '0';
signal PC_INC_tb : std_logic := '1';
signal RST_tb : std_logic := '0';
signal CLK_tb : std_logic := '0';
--Internal
signal FROM_IMMED_tb : std_logic_vector(9 downto 0) := "0011001100"; --x0CC
signal FROM_STACK_tb : std_logic_vector(9 downto 0) := "0110101010"; --x1AA
signal PC_COUNT_tb : std_logic_vector(9 downto 0);
--Outputs
signal ROM_INSTRUCTION_tb : std_logic_vector(17 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
Program_Counter_0: Program_Counter PORT MAP (
FROM_IMMED => FROM_IMMED_tb,
FROM_STACK => FROM_STACK_tb,
PC_MUX_SEL => PC_MUX_SEL_tb,
PC_LD => PC_LD_tb,
PC_INC => PC_INC_tb,
RST => RST_tb,
CLK => CLK_tb,
PC_COUNT => PC_COUNT_tb
);
Program_ROM_0: prog_rom PORT MAP (
ADDRESS => PC_COUNT_tb,
INSTRUCTION => ROM_INSTRUCTION_tb,
CLK => CLK_tb
);
-- Clock process definitions
CLK_process: process begin
CLK_tb <= '0';
wait for CLK_period / 2;
CLK_tb <= '1';
wait for CLK_period / 2;
end process;
-- Stimulus process
stim_proc: process begin
RST_tb <= '1';
wait for 5 ns;
RST_tb <= '0';
wait;
end process;
end Behavioral;
| mit | 76cc6b7066cc301770f0f022578af5f7 | 0.502683 | 3.732165 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/mem/sdram/memtest_s3esk.vhdl | 1 | 9,991 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory Controller Test for Spartan-3E Starter Kit
--
-- Description:
-- ------------------------------------
-- Top-Level of Memory Controller Test for Altera DE0 Board
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.fifo.all;
entity memtest_s3esk is
port (
clk_in : in std_logic;
sd_ck_fb : in std_logic;
btn_south : in std_logic;
led : out std_logic_vector(7 downto 0);
sd_ck_p : out std_logic;
sd_ck_n : out std_logic;
sd_cke : out std_logic;
sd_cs : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sd_we : out std_logic;
sd_ba : out std_logic_vector(1 downto 0);
sd_a : out std_logic_vector(12 downto 0);
sd_ldm : out std_logic;
sd_udm : out std_logic;
sd_ldqs : out std_logic;
sd_udqs : out std_logic;
sd_dq : inout std_logic_vector(15 downto 0));
end memtest_s3esk;
architecture rtl of memtest_s3esk is
signal clk_sys : std_logic;
signal clk_mem : std_logic;
signal clk_mem_n : std_logic;
signal clk_mem90 : std_logic;
signal clk_mem90_n : std_logic;
signal clk_memfb90 : std_logic;
signal clk_memfb90_n : std_logic;
signal rst_sys : std_logic;
signal rst_mem : std_logic;
signal rst_mem90 : std_logic;
signal rst_mem180 : std_logic;
signal rst_mem270 : std_logic;
signal rst_memfb90 : std_logic;
signal rst_memfb270 : std_logic;
signal locked : std_logic;
signal clk_tb : std_logic;
signal rst_tb : std_logic;
signal cf_put : std_logic;
signal cf_full : std_logic;
signal cf_din : std_logic_vector(25 downto 0);
signal cf_dout : std_logic_vector(25 downto 0);
signal cf_valid : std_logic;
signal cf_got : std_logic;
signal wf_put : std_logic;
signal wf_full : std_logic;
signal wf_din : std_logic_vector(31 downto 0);
signal wf_dout : std_logic_vector(31 downto 0);
signal wf_valid : std_logic;
signal wf_got : std_logic;
signal mem_rdy : std_logic;
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(31 downto 0);
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(23 downto 0);
signal mem_wdata : std_logic_vector(31 downto 0);
signal fsm_status : std_logic_vector(2 downto 0);
signal rf_put : std_logic;
signal rf_din : std_logic_vector(31 downto 0);
-- Component declaration in case a netlist is used.
component sdram_ctrl_s3esk is
generic (
CLK_PERIOD : real;
BL : positive);
port (
clk : in std_logic;
clk_n : in std_logic;
clk90 : in std_logic;
clk90_n : in std_logic;
rst : in std_logic;
rst90 : in std_logic;
rst180 : in std_logic;
rst270 : in std_logic;
clk_fb90 : in std_logic;
clk_fb90_n : in std_logic;
rst_fb90 : in std_logic;
rst_fb270 : in std_logic;
user_cmd_valid : in std_logic;
user_wdata_valid : in std_logic;
user_write : in std_logic;
user_addr : in std_logic_vector(24 downto 0);
user_wdata : in std_logic_vector(31 downto 0);
user_got_cmd : out std_logic;
user_got_wdata : out std_logic;
user_rdata : out std_logic_vector(31 downto 0);
user_rstb : out std_logic;
sd_ck_p : out std_logic;
sd_ck_n : out std_logic;
sd_cke : out std_logic;
sd_cs : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sd_we : out std_logic;
sd_ba : out std_logic_vector(1 downto 0);
sd_a : out std_logic_vector(12 downto 0);
sd_ldqs : out std_logic;
sd_udqs : out std_logic;
sd_dq : inout std_logic_vector(15 downto 0));
end component sdram_ctrl_s3esk;
begin -- rtl
clockgen: entity work.memtest_s3esk_clockgen
port map (
clk_in => clk_in,
sd_ck_fb => sd_ck_fb,
user_rst => btn_south,
clk_sys => clk_sys,
clk_mem => clk_mem,
clk_mem_n => clk_mem_n,
clk_mem90 => clk_mem90,
clk_mem90_n => clk_mem90_n,
clk_memfb90 => clk_memfb90,
clk_memfb90_n => clk_memfb90_n,
rst_sys => rst_sys,
rst_mem => rst_mem,
rst_mem90 => rst_mem90,
rst_mem180 => rst_mem180,
rst_mem270 => rst_mem270,
rst_memfb90 => rst_memfb90,
rst_memfb270 => rst_memfb270,
locked => locked);
-- Testbench clock selection
-- Also update chipscope configuration.
-- clk_tb <= clk_mem;
-- rst_tb <= rst_mem;
clk_tb <= clk_sys;
rst_tb <= rst_sys;
-- uses default configuration, see entity declaration
mem_ctrl: sdram_ctrl_s3esk
generic map (
CLK_PERIOD => 10.0,
BL => 2)
port map (
clk => clk_mem,
clk_n => clk_mem_n,
clk90 => clk_mem90,
clk90_n => clk_mem90_n,
rst => rst_mem,
rst90 => rst_mem90,
rst180 => rst_mem180,
rst270 => rst_mem270,
clk_fb90 => clk_memfb90,
clk_fb90_n => clk_memfb90_n,
rst_fb90 => rst_memfb90,
rst_fb270 => rst_memfb270,
user_cmd_valid => cf_valid,
user_wdata_valid => wf_valid,
user_write => cf_dout(25),
user_addr => cf_dout(24 downto 0),
user_wdata => wf_dout,
user_got_cmd => cf_got,
user_got_wdata => wf_got,
user_rdata => rf_din,
user_rstb => rf_put,
sd_ck_p => sd_ck_p,
sd_ck_n => sd_ck_n,
sd_cke => sd_cke,
sd_cs => sd_cs,
sd_ras => sd_ras,
sd_cas => sd_cas,
sd_we => sd_we,
sd_ba => sd_ba,
sd_a => sd_a,
sd_ldqs => sd_ldqs,
sd_udqs => sd_udqs,
sd_dq => sd_dq);
sd_ldm <= '0';
sd_udm <= '0';
cmd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 26,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => cf_put,
din => cf_din,
full => cf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => cf_got,
valid => cf_valid,
dout => cf_dout);
wr_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 32,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => wf_put,
din => wf_din,
full => wf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => wf_got,
valid => wf_valid,
dout => wf_dout);
-- The size fo this FIFO depends on the latency between write and read
-- clock domain
rd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 32,
MIN_DEPTH => 8)
port map (
clk_wr => clk_memfb90_n,
rst_wr => rst_memfb270,
put => rf_put,
din => rf_din,
full => open, -- can't stall
clk_rd => clk_tb,
rst_rd => rst_tb,
got => mem_rstb,
valid => mem_rstb,
dout => mem_rdata);
fsm: entity work.memtest_fsm
generic map (
A_BITS => 24,
D_BITS => 32)
port map (
clk => clk_tb,
rst => rst_tb,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
status => fsm_status);
-- Signal mem_ctrl ready only if both FIFOs are not full.
mem_rdy <= cf_full nor wf_full;
-- Word aligned access to memory.
-- Parallel "put" to both FIFOs.
cf_put <= mem_req and mem_rdy;
wf_put <= mem_req and mem_write and mem_rdy;
cf_din <= mem_write & std_logic_vector(mem_addr) & '0';
wf_din <= mem_wdata;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
led(7) <= locked;
led(6 downto 3) <= (others => '0');
led(2 downto 0) <= fsm_status;
end rtl;
| apache-2.0 | 118a232a2c05aa3de4c1e5bb32445167 | 0.496147 | 3.374198 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/synth/RAT_Mux4x1_10_0_0.vhd | 2 | 3,989 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_10:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_10_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RAT_Mux4x1_10_0_0;
ARCHITECTURE RAT_Mux4x1_10_0_0_arch OF RAT_Mux4x1_10_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_10 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "Mux4x1_10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux4x1_10_0_0_arch : ARCHITECTURE IS "RAT_Mux4x1_10_0_0,Mux4x1_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux4x1_10_0_0_arch: ARCHITECTURE IS "RAT_Mux4x1_10_0_0,Mux4x1_10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux4x1_10,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux4x1_10
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_10_0_0_arch;
| mit | 15c65a1050d09060f8e860d46f8dd360 | 0.720481 | 3.548932 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/hdl/RAT_wrapper.vhd | 1 | 1,534 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Fri Oct 27 00:01:59 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target RAT_wrapper.bd
--Design : RAT_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_wrapper is
port (
CLK : in STD_LOGIC;
INT_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
IN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC
);
end RAT_wrapper;
architecture STRUCTURE of RAT_wrapper is
component RAT is
port (
PORT_ID : out STD_LOGIC_VECTOR ( 7 downto 0 );
IN_PORT : in STD_LOGIC_VECTOR ( 7 downto 0 );
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
OUT_PORT : out STD_LOGIC_VECTOR ( 7 downto 0 );
INT_IN : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component RAT;
begin
RAT_i: component RAT
port map (
CLK => CLK,
INT_IN(0) => INT_IN(0),
IN_PORT(7 downto 0) => IN_PORT(7 downto 0),
OUT_PORT(7 downto 0) => OUT_PORT(7 downto 0),
PORT_ID(7 downto 0) => PORT_ID(7 downto 0),
RST => RST
);
end STRUCTURE;
| mit | 8c5748ba1de2f7ea8ced5ddff843aa84 | 0.556714 | 3.567442 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/RegisterFile.vhd | 1 | 955 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RegisterFile is
Port ( D_IN : in STD_LOGIC_VECTOR (7 downto 0);
DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
ADRX : in STD_LOGIC_VECTOR (4 downto 0);
ADRY : in STD_LOGIC_VECTOR (4 downto 0);
DX_OE : in STD_LOGIC;
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end RegisterFile;
architecture Behavioral of RegisterFile is
TYPE memory is array (0 to 31) of std_logic_vector(7 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
begin
process(clk)
begin
if (rising_edge(clk)) then
if (WE = '1') then
REG(conv_integer(ADRX)) <= D_IN;
end if;
end if;
end process;
DX_OUT <= REG(conv_integer(ADRX)) when DX_OE='1' else (others=>'Z');
DY_OUT <= REG(conv_integer(ADRY));
end Behavioral;
| mit | 57132c292ce79601330d3e22c68ecbea | 0.586387 | 3.141447 | false | false | false | false |
stefanct/aua | hw/alu/sim/alu_tb.vhd | 1 | 16,171 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity alu_tb is
end alu_tb;
architecture alu_test of alu_tb is
component alu is
port (
clk : in std_logic;
reset : in std_logic;
opcode : in opcode_t;
opa : in word_t;
opb : in word_t;
result : out word_t
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal opa: word_t;
signal opb: word_t;
signal result: word_t;
signal opcode: opcode_t;
begin
alu1: alu port map(clk, reset, opcode, opa, opb, result);
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
-- ldi
opcode <= "000000";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = opb report "ldi: load failed - 1";
icwait(5);
opcode <= "000111";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = opb report "ldi: load failed - 2";
icwait(5);
--jmpl
opcode <= "001101";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = x"0000" report "jmpl: jmpl not ignored";
icwait(5);
--brez
opcode <= "001110";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = x"0000" report "brez: brez not ignored - 1";
icwait(5);
--brnez
opcode <= "001111";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = x"0000" report "brnez: brnez not ignored - 2";
icwait(5);
--brezi
opcode <= "010000";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = x"0000" report "brezi: brezi not ignored";
icwait(5);
--brnezi
opcode <= "010100";
opb <= std_logic_vector(to_unsigned(12,word_t'length));
icwait(1);
assert result = x"0000" report "brnezi: brnezi not ignored";
icwait(5);
--addi
opcode <="011000";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(23,word_t'length) report "addi: (+) + (+), (12 + 11 != 23)";
icwait(5);
--addi
opcode <="011001";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-1,word_t'length) report "addi: (-) + (+), (-12 + 11 != -1)";
icwait(5);
--addi
opcode <="011010";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(1,word_t'length) report "addi: (+) + (-), (12 + -11 != 1)";
icwait(5);
--addi
opcode <="011011";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-23,word_t'length) report "addi: (-) + (-), (-12 + -11 != -23)";
icwait(5);
--muli
opcode <= "011100";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(132,word_t'length) report "muli: (+) * (+), (12 * 11 != 132)";
icwait(5);
--muli
opcode <= "011100";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-132,word_t'length) report "muli: (-) * (+), (-12 * 11 != -132)";
icwait(5);
--muli
opcode <= "011100";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-132,word_t'length) report "muli: (+) * (-), (12 * -11 != -132)";
icwait(5);
--muli
opcode <= "011100";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(132,word_t'length) report "muli: (-) * (-), (-12 * -11 != 132)";
icwait(5);
--add
opcode <="100000";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(23,word_t'length) report "add: (+) + (+), (12 + 11 != 23)";
icwait(5);
--add
opcode <="100000";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-1,word_t'length) report "add: (-) + (+), (-12 + 11 != -1)";
icwait(5);
--add
opcode <="100000";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(1,word_t'length) report "add: (+) + (-), (12 + -11 != 1)";
icwait(5);
--add
opcode <="100000";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-23,word_t'length) report "add: (-) + (-), (-12 + -11 != -23)";
icwait(5);
--addc
opcode <= "100000";
opa <= std_logic_vector(to_unsigned(2**16-1,word_t'length));
opb <= std_logic_vector(to_unsigned(2,word_t'length));
icwait(1);
assert unsigned(result) = to_unsigned(1,word_t'length) report "add: (+) + (+), (FFFF + 2 != 0001,c=1)";
opcode <= "100001";
opa <= std_logic_vector(to_unsigned(0,word_t'length));
opb <= std_logic_vector(to_unsigned(2,word_t'length));
icwait(1);
assert unsigned(result) = to_unsigned(3,word_t'length) report "addc: (+) + (+), (0 + 2 + c(=1) != 3)";
icwait(5);
--sub
opcode <="100010";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(1,word_t'length) report "sub: (+) - (+), (12 - 11 != 1)";
icwait(5);
--sub
opcode <="100010";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-23,word_t'length) report "sub: (-) - (+), (-12 - 11 != -23)";
icwait(5);
--sub
opcode <="100010";
opa <= std_logic_vector(to_signed(12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(23,word_t'length) report "sub: (+) - (-), (12 - -11 != 23)";
icwait(5);
--sub
opcode <="100010";
opa <= std_logic_vector(to_signed(-12,word_t'length));
opb <= std_logic_vector(to_signed(-11,word_t'length));
icwait(1);
assert signed(result) = to_signed(-1,word_t'length) report "sub: (-) - (-), (-12 - -11 != -1)";
icwait(5);
--subc
opcode <= "100010";
opa <= std_logic_vector(to_signed(1,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert signed(result) = to_signed(-2,word_t'length) report "subc: (+) - (+), (1 - 3 != -2,c=1)";
opcode <= "100011";
opa <= std_logic_vector(to_signed(6,word_t'length));
opb <= std_logic_vector(to_signed(2,word_t'length));
icwait(1);
assert signed(result) = to_signed(3,word_t'length) report "subc: (+) - (+), (6 - 2 - c(=1) != 3)";
icwait(5);
--mul
opcode <= "100100";
opa <= x"FFFF";
opb <= x"FFFF";
icwait(1);
assert result = x"0001" report "mul: -1 * -1 != 1";
icwait(5);
--mulu
opcode <= "100101";
opa <= x"FFFF";
opb <= x"FFFF";
icwait(1);
assert result = x"0001" report "mulu: 65535 * 65535 != 4294836225 (FFFF * FFFF != FFFE0001)";
icwait(5);
--mulh
opcode <= "100110";
opa <= x"FFFF";
opb <= x"FFFF";
icwait(1);
assert result = x"0000" report "mulh: -1 * -1 != 1";
icwait(5);
--mulhu
opcode <= "100111";
opa <= x"FFFF";
opb <= x"FFFF";
icwait(1);
assert result = x"FFFE" report "mulhu: 65535 * 65535 != 4294836225 (FFFF * FFFF != FFFE0001)";
icwait(5);
--or
opcode <= "101000";
opa <= x"FF00";
opb <= x"00FF";
icwait(1);
assert result = x"FFFF" report "or: FF00 or 00FF != FFFF";
icwait(5);
--and
opcode <= "101001";
opa <= x"FF00";
opb <= x"00FF";
icwait(1);
assert result = x"0000" report "and: FF00 and 00FF != 0000";
icwait(5);
--xor
opcode <= "101010";
opa <= x"F0F0";
opb <= x"FF00";
icwait(1);
assert result = x"0FF0" report "or: F0F0 or FF00 != 0FF0";
icwait(5);
--not
opcode <= "101011";
opb <= x"F0F0";
icwait(1);
assert result = x"0F0F" report "not: not F0F0 != 0F0F";
icwait(5);
--neg
opcode <= "101100";
opb <= x"00FF";
icwait(1);
assert result = x"FF01" report "neg: (+) -> (-), 255 !-> -255";
icwait(5);
--neg
opcode <= "101100";
opb <= x"FF01";
icwait(1);
assert result = x"00FF" report "neg: (-) -> (+), -255 !-> +255";
icwait(5);
--asr
opcode <= "101101";
opb <= x"9999";
icwait(1);
assert result = x"CCCC" report "asr: 1 shift, 1001100110011001 !=> 1100110011001100";
icwait(5);
--asr
opcode <= "101101";
opb <= x"6666";
icwait(1);
assert result = x"3333" report "asr: 0 shift, 0110011001100110 !=> 0011001100110011";
icwait(5);
--lsl
opcode <= "101110";
opb <= x"F0F0";
icwait(1);
assert result = x"E1E0" report "lsl: 0 shift, 1111000011110000 !=> 1110000111100000";
icwait(5);
--lsr
opcode <= "101111";
opb <= x"F0F0";
icwait(1);
assert result = x"7878" report "lsr: 0 shift, 1111000011110000 !=> 0111100001111000";
icwait(5);
--lsli
opcode <= "110000";
opa <= x"0001";
opb <= std_logic_vector(to_unsigned(3,word_t'length));
icwait(1);
assert result = x"0008" report "lsli: shift right about 3, 0001 !=> 0008";
icwait(5);
--lsri
opcode <= "110001";
opa <= x"8000";
opb <= std_logic_vector(to_unsigned(3,word_t'length));
icwait(1);
assert result = x"1000" report "asri: shift right about 3, 8000 !=> 1000";
icwait(5);
--scb
opcode <= "110010";
opa <= x"FFFF";
opb <= std_logic_vector(to_unsigned(0,word_t'length));
icwait(1);
assert result = x"FFFE" report "scb: clear bit 0 error";
icwait(5);
--scb
opcode <= "110010";
opa <= x"FFFE";
opb <= std_logic_vector(to_unsigned(16,word_t'length));
icwait(1);
assert result = x"FFFF" report "scb: set bit 0 error";
icwait(5);
--roti -- 0 = links
opcode <= "110011";
opa <= x"0001";
opb <= std_logic_vector(to_unsigned(17,word_t'length));
icwait(1);
assert result = x"8000" report "roti: roll 1 bit right, 0001 !=> 8000";
icwait(5);
--roti
opcode <= "110011";
opa <= x"8000";
opb <= std_logic_vector(to_unsigned(1,word_t'length));
icwait(1);
assert result = x"0001" report "roti: roll 1 bit left, 0001 !=> 8000";
icwait(5);
--cmpv out of isa
--opcode <= "110100"
--cmplt
opcode <= "110101";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert result = x"0000" report "cmplt: 3 < 3";
icwait(5);
--cmplt
opcode <= "110101";
opa <= std_logic_vector(to_signed(4,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert result = x"0000" report "cmplt: 4 !< 3";
icwait(5);
--cmplt
opcode <= "110101";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(4,word_t'length));
icwait(1);
assert result = x"0001" report "cmplt: 3 !< 4";
icwait(5);
--cmplt
opcode <= "110101";
opa <= std_logic_vector(to_signed(-3,word_t'length));
opb <= std_logic_vector(to_signed(-4,word_t'length));
icwait(1);
assert result = x"0000" report "cmplt: -3 < -4";
icwait(5);
--cmplt
opcode <= "110101";
opa <= std_logic_vector(to_signed(-4,word_t'length));
opb <= std_logic_vector(to_signed(-3,word_t'length));
icwait(1);
assert result = x"0001" report "cmplt: -4 !< -3";
icwait(5);
--cmpltu
opcode <= "110110";
opa <= std_logic_vector(to_unsigned(3,word_t'length));
opb <= std_logic_vector(to_unsigned(4,word_t'length));
icwait(1);
assert result = x"0001" report "cmplt: 3 !< 4";
icwait(5);
--cmpltu
opcode <= "110110";
opa <= std_logic_vector(to_unsigned(4,word_t'length));
opb <= std_logic_vector(to_unsigned(3,word_t'length));
icwait(1);
assert result = x"0000" report "cmpltu: 4 < 3";
icwait(5);
--cmpltu
opcode <= "110110";
opa <= std_logic_vector(to_unsigned(3,word_t'length));
opb <= std_logic_vector(to_unsigned(3,word_t'length));
icwait(1);
assert result = x"0000" report "cmpltu: 3 < 3";
icwait(5);
--cmplte
opcode <= "110111";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert result = x"0001" report "cmplte: 3 !<= 3";
icwait(5);
--cmplte
opcode <= "110111";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(4,word_t'length));
icwait(1);
assert result = x"0001" report "cmplte: 3 !<= 4";
icwait(5);
--cmplte
opcode <= "110111";
opa <= std_logic_vector(to_signed(4,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert result = x"0000" report "cmplte: 4 <= 3";
icwait(5);
--cmplte
opcode <= "110111";
opa <= std_logic_vector(to_signed(-3,word_t'length));
opb <= std_logic_vector(to_signed(4,word_t'length));
icwait(1);
assert result = x"0001" report "cmplte: -3 !<= 4";
icwait(5);
--cmplteu
opcode <= "111000";
opa <= std_logic_vector(to_unsigned(3,word_t'length));
opb <= std_logic_vector(to_unsigned(4,word_t'length));
icwait(1);
assert result = x"0001" report "cmplteu: 3 !<= 4";
icwait(5);
--cmplteu
opcode <= "111000";
opa <= std_logic_vector(to_unsigned(4,word_t'length));
opb <= std_logic_vector(to_unsigned(3,word_t'length));
icwait(1);
assert result = x"0000" report "cmplteu: 4 <= 3";
icwait(5);
--cmpe
opcode <= "111001";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert result = x"0001" report "cmpe: 3 != 3";
icwait(5);
--cmpe
opcode <= "111001";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(4,word_t'length));
icwait(1);
assert result = x"0000" report "cmpe: 3 = 4";
icwait(5);
--cmpe
opcode <= "111001";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(-4,word_t'length));
icwait(1);
assert result = x"0000" report "cmpe: 3 = -4";
icwait(5);
--cmpei
opcode <= "111010";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(3,word_t'length));
icwait(1);
assert result = x"0001" report "cmpei: 3 != 3";
icwait(5);
--cmpei
opcode <= "111010";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(4,word_t'length));
icwait(1);
assert result = x"0000" report "cmpei: 3 = 4";
icwait(5);
--cmpei
opcode <= "111010";
opa <= std_logic_vector(to_signed(3,word_t'length));
opb <= std_logic_vector(to_signed(-4,word_t'length));
icwait(1);
assert result = x"0000" report "cmpei: 3 = -4";
icwait(5);
--mov
opcode <= "111011";
opb <= x"FFFF";
icwait(1);
assert result = x"FFFF" report "mov: FFFF !=> FFFF";
icwait(5);
--ld
opcode <= "111100";
opb <= x"FFFF";
icwait(1);
assert result = x"0000" report "ld: load not ignored";
icwait(5);
--ldb
opcode <= "111101";
opb <= x"FFFF";
icwait(1);
assert result = x"0000" report "ld: load not ignored";
icwait(5);
--st
opcode <= "111110";
opb <= x"FFFF";
icwait(1);
assert result = x"0000" report "st: store not ignored";
icwait(5);
--stb
opcode <= "111111";
opb <= x"FFFF";
icwait(1);
assert result = x"0000" report "st: store not ignored";
assert false report "sim finish" SEVERITY failure;
end process TEST;
end alu_test; | gpl-3.0 | 1d0406c8e7a174132d521e4385beb341 | 0.598108 | 2.672009 | false | false | false | false |
David-Estevez/spaceinvaders | src/bullet.vhd | 1 | 2,861 | ----------------------------------------------------------------------------------
-- Invaders
-- Sergio Vilches
-- David Estévez Fernández
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bullet is
port (clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
enable : in std_logic;
hit : in std_logic; -- '1' when an invader has been hit
shoot : in std_logic; -- pushbutton
posH : in std_logic_vector(4 downto 0); -- h position of ship
flying : out std_logic;-- '1' if there is a bullet moving
bullX : out std_logic_vector(4 downto 0);
bullY : out std_logic_vector(3 downto 0)
);
end bullet;
architecture behavioral of bullet is
signal tick : std_logic; -- Signal from timer
signal intbullX: std_logic_vector( 4 downto 0);
signal intbullY: std_logic_vector( 3 downto 0);
component timer is
generic ( t: integer);
port (clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
en : in std_logic;
q : out std_logic);
end component;
begin
speedTimer: timer
generic map (50) -- Period of movement in ms (5 for a faster simulation)
port map (
clk => clk,
reset => reset,
clear => clear,
en => '1',
q => tick
);
process (reset, clk,intbullX,intbullY)
variable intflying: std_logic;
begin
if reset = '1' then
intbullX <= std_logic_vector(to_unsigned(0,5));
intbullY <= std_logic_vector(to_unsigned(14,4));
intflying := '0';
elsif clk'event and clk = '1' then
-- Sequential behaviors:
if clear = '1' then
intbullX <= std_logic_vector(to_unsigned(0,5));
intbullY <= std_logic_vector(to_unsigned(14,4));
intflying := '0';
elsif enable = '1' then
-- Shoot the bullet
if ((intflying = '0') and (shoot = '1')) then
intflying := '1'; -- bullet moving
intbullX <= posH; -- starting just over the ship
intbullY <= std_logic_vector(to_unsigned(13,4));
end if;
-- Check if we have killed any invader
if (hit = '1') then
intflying := '0';
intbullY <= std_logic_vector(to_unsigned(14,4));
end if;
-- Moving up!
if (tick = '1') and (intflying = '1') then
if intbullY = std_logic_vector(to_unsigned(0,4)) then
-- We have reached the top of the screen
intflying := '0';
intbullY <= std_logic_vector(to_unsigned(14,4));
else
intbullY <= std_logic_vector(unsigned(intbullY) - to_unsigned(1,4));
end if;
end if;
end if;
end if;
bullX <= intBullX;
bullY <= intBullY;
flying <= intFlying;
end process;
end behavioral; | gpl-3.0 | 7829b5da498b5b6be674fb439af93084 | 0.546695 | 3.387441 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_MUX4_0/sim/design_1_MUX4_0.vhd | 2 | 6,083 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX4_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX4_0;
ARCHITECTURE design_1_MUX4_0_arch OF design_1_MUX4_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX4_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data2xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid2xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready2xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI2 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 3
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => Data2xDI,
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => Valid2xSI,
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
Ready2xSO => Ready2xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX4_0_arch;
| mit | 3820c9ad2c9da706408634846e01d4d2 | 0.71034 | 3.691141 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/dds_compiler_v6_0/hdl/dds_compiler_v6_0.vhd | 4 | 25,746 | `protect begin_protected
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`protect end_protected
| mit | 4b92dc63ae05be9a0c108c0c45978003 | 0.941428 | 1.864031 | false | false | false | false |
marcoep/MusicBoxNano | ip/SongROM.vhd | 1 | 5,889 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: SongROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY SongROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END SongROM;
ARCHITECTURE SYN OF songrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (16 DOWNTO 0);
BEGIN
q <= sub_wire0(16 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../../GITROOT/MusicBoxNano/matlab/for_elise_by_beethoven.mid-musicbox.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1068,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 11,
width_a => 17,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../../GITROOT/MusicBoxNano/matlab/for_elise_by_beethoven.mid-musicbox.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1068"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "17"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../../GITROOT/MusicBoxNano/matlab/for_elise_by_beethoven.mid-musicbox.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1068"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 17 0 OUTPUT NODEFVAL "q[16..0]"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 17 0 @q_a 0 0 17 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SongROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SongROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SongROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SongROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SongROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | f9be75665114272791663ac885e53142 | 0.676855 | 3.727215 | false | false | false | false |
blytkerchan/BrainF | SPISlave.vhdl | 1 | 9,365 | -- Generic SPI Slave
-- sets the output data bit on the rising edge of the clock, reads the
-- data input bit on the falling edge.
-- To use, read the data_O output on the rising edge of
-- (data_ready_O and new_data_byte_O), set data_I to something you want to send and
-- wait for a rising edge on data_ack_O before putting another one in.
-- Data sent by the slave will be aligned to 8-bit boundaries, so if you don't
-- have any data ready to send (data_ready_I is set) when a byte starts to be sent,
-- the slave will pull its output low for the duration of the byte. You have between
-- the rising edge of the SPI clock for the last bit of a byte and the next rising
-- edge to provide new data.
-- the spi_clock_I, spi_slave_select_NI and spi_mosi_I signals should be debounced
-- before being fed to this component -- you know better how much noise to expect
-- than I do.
-- Version: 20141019
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPISlave is
port(
clock : in std_logic
; resetN : in std_logic
-- bus to the outside
; spi_clock_I : in std_logic
; spi_slave_select_NI : in std_logic
; spi_mosi_I : in std_logic
; spi_miso_O : out std_logic
-- internal bus:
-- signal to this component that data_I contains something
; data_ready_I : in std_logic
-- data to send
; data_I : in std_logic_vector(7 downto 0)
-- acknowledge we've copied the byte, so you can provide another one
; data_ack_O : out std_logic
-- indicate data_O contains valid data from the master
; data_ready_O : out std_logic
-- signal that we've changed the byte (can be used to push into a FIFO or set an SR flip-flop or something)
; new_data_byte_O : out std_logic
-- byte from the master
; data_O : out std_logic_vector(7 downto 0)
);
end entity;
architecture behavior of SPISlave is
type BitCounter is range 0 to 7;
-- driven by a SR flip-flop
signal internal_data_ready_O : std_logic := '0';
signal internal_data_ready_NO : std_logic := '1';
-- driven by p_decoder
signal set_internal_data_ready_O : std_logic := '0';
signal clear_internal_data_ready_O : std_logic := '1';
signal prev_spi_clock_I : std_logic := 'X';
signal prev_spi_slave_select_NI : std_logic := 'X';
signal internal_spi_miso_O : std_logic := 'Z';
signal input_bit_count : BitCounter := 0;
signal output_bit_count : BitCounter := 7;
signal current_input_byte : std_logic_vector(7 downto 0) := (others => 'X');
signal outputting_data : std_logic := '0';
signal current_output_byte : std_logic_vector(7 downto 0) := (others => '0');
signal current_output_byte_valid : std_logic := '0';
signal prev_data_ready_I : std_logic := 'X';
signal data_ack_on_first_seen : std_logic := '0';
signal data_ack_on_byte_change : std_logic := '0';
signal read_select : std_logic := '0';
begin
-- flip-flop for the data-ready output signal
internal_data_ready_O <= not internal_data_ready_NO or set_internal_data_ready_O;
internal_data_ready_NO <= not internal_data_ready_O or clear_internal_data_ready_O;
data_ready_O <= internal_data_ready_O;
-- let the client code know we produced a new byte
new_data_byte_O <= set_internal_data_ready_O;
-- wire-through for the MISO output
spi_miso_O <= internal_spi_miso_O;
-- acknowledge consuming a byte
data_ack_O <= data_ack_on_byte_change or data_ack_on_first_seen;
p_decoder : process(clock, resetN)
begin
if resetN = '0' then
prev_spi_clock_I <= 'X';
prev_spi_slave_select_NI <= 'X';
clear_internal_data_ready_O <= '1';
data_O <= (others => 'X');
internal_spi_miso_O <= 'Z';
set_internal_data_ready_O <= '0';
current_input_byte <= (others => 'X');
input_bit_count <= 0;
output_bit_count <= 7;
outputting_data <= '0';
current_output_byte <= (others => '0');
current_output_byte_valid <= '0';
prev_data_ready_I <= 'X';
data_ack_on_first_seen <= '0';
data_ack_on_byte_change <= '0';
read_select <= '0';
else
if rising_edge(clock) then
-- detect a falling edge of the spi_slave_select_NI input
if prev_spi_slave_select_NI = '1' and spi_slave_select_NI = '0' then
clear_internal_data_ready_O <= '1';
-- counters should already be OK at this point: either because we're coming out of a complete reset or because we have previously been deselected
-- on a rising edge (when we're deselected) reset the counters so we can't get desynchronized if we get deselected in the middle of a byte
elsif prev_spi_slave_select_NI = '0' and spi_slave_select_NI = '1' then
output_bit_count <= 7;
input_bit_count <= 0;
read_select <= '0';
else
clear_internal_data_ready_O <= '0';
end if;
prev_spi_slave_select_NI <= spi_slave_select_NI;
-- detect new output data
if prev_data_ready_I = '0'and data_ready_I = '1' then
current_output_byte <= data_I;
current_output_byte_valid <= '1';
data_ack_on_first_seen <= '1';
else
data_ack_on_first_seen <= '0';
end if;
prev_data_ready_I <= data_ready_I;
-- detect edges of the input clock
if spi_slave_select_NI = '0' then -- we are selected
if prev_spi_clock_I = '0' and spi_clock_I = '1' then -- rising edge of the clock - write a bit if we have any
-- start outputting data if we are at the start of a byte boundary, or if we were already outputting a byte
if current_output_byte_valid = '1' and (outputting_data = '1' or output_bit_count = 7) then
internal_spi_miso_O <= current_output_byte(7);
outputting_data <= '1';
else
internal_spi_miso_O <= '0';
outputting_data <= '0';
end if;
-- if we just decided to output the last bit of the byte, load the next byte if we have one, or invalidate the current byte if we don't.
-- if we do load a new byte, we should acknowledge it.
-- if we're not at the last bit, just shift a bit out of the register
if (output_bit_count = 0) then
-- we should, of course, only take the byte if we've output the current one. Otherwise, we should leave it there until we do.
if outputting_data = '1' then
current_output_byte <= data_I;
current_output_byte_valid <= data_ready_I;
data_ack_on_byte_change <= '1';
else
data_ack_on_byte_change <= '0';
end if;
output_bit_count <= 7;
else
-- shift out a bit
data_ack_on_byte_change <= '0';
output_bit_count <= output_bit_count - 1;
current_output_byte <= current_output_byte(6 downto 0) & '0';
end if;
set_internal_data_ready_O <= '0';
read_select <= '1';
elsif read_select = '1' and prev_spi_clock_I = '1' and spi_clock_I = '0' then -- falling edge of the clock - read a bit
if input_bit_count = 7 then
set_internal_data_ready_O <= '1';
data_O <= current_input_byte(6 downto 0) & spi_mosi_I;
input_bit_count <= 0;
else
set_internal_data_ready_O <= '0';
input_bit_count <= input_bit_count + 1;
end if;
current_input_byte <= current_input_byte(6 downto 0) & spi_mosi_I;
else
set_internal_data_ready_O <= '0';
end if;
else
internal_spi_miso_O <= 'Z';
set_internal_data_ready_O <= '0';
end if;
prev_spi_clock_I <= spi_clock_I;
end if;
end if;
end process;
end architecture;
| lgpl-3.0 | aa6caf5027b31fd17f6cc594b70e0ca3 | 0.514042 | 4.047105 | false | false | false | false |
open-power/snap | actions/hdl_nvme_example/hw/action_wrapper.vhd | 1 | 35,038 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016,2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
USE work.action_types.ALL;
ENTITY action_wrapper IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
interrupt_src : OUT STD_LOGIC_VECTOR(INT_BITS-2 DOWNTO 0);
interrupt_ctx : OUT STD_LOGIC_VECTOR(CONTEXT_BITS-1 DOWNTO 0);
interrupt_ack : IN STD_LOGIC;
--
-- AXI SDRAM Interface
m_axi_card_mem0_araddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_arburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_card_mem0_arcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_card_mem0_arid : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_arlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_card_mem0_arlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_card_mem0_arprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_card_mem0_arqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_card_mem0_arready : IN STD_LOGIC;
m_axi_card_mem0_arregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_card_mem0_arsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_card_mem0_aruser : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ARUSER_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_arvalid : OUT STD_LOGIC;
m_axi_card_mem0_awaddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_awburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_card_mem0_awcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_card_mem0_awid : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_awlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_card_mem0_awlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_card_mem0_awprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_card_mem0_awqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_card_mem0_awready : IN STD_LOGIC;
m_axi_card_mem0_awregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_card_mem0_awsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_card_mem0_awuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_AWUSER_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_awvalid : OUT STD_LOGIC;
m_axi_card_mem0_bid : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_bready : OUT STD_LOGIC;
m_axi_card_mem0_bresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_card_mem0_buser : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_BUSER_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_bvalid : IN STD_LOGIC;
m_axi_card_mem0_rdata : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_rid : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_rlast : IN STD_LOGIC;
m_axi_card_mem0_rready : OUT STD_LOGIC;
m_axi_card_mem0_rresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_card_mem0_ruser : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_RUSER_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_rvalid : IN STD_LOGIC;
m_axi_card_mem0_wdata : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_wlast : OUT STD_LOGIC;
m_axi_card_mem0_wready : IN STD_LOGIC;
m_axi_card_mem0_wstrb : OUT STD_LOGIC_VECTOR ( (C_M_AXI_CARD_MEM0_DATA_WIDTH/8)-1 DOWNTO 0 );
m_axi_card_mem0_wuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_WUSER_WIDTH-1 DOWNTO 0 );
m_axi_card_mem0_wvalid : OUT STD_LOGIC;
--
-- AXI NVME Interface
m_axi_nvme_araddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ADDR_WIDTH -1 DOWNTO 0 );
m_axi_nvme_arburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_nvme_arcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_nvme_arid : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 );
m_axi_nvme_arlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_nvme_arlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_nvme_arprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_nvme_arqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_nvme_arready : IN STD_LOGIC;
m_axi_nvme_arregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_nvme_arsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_nvme_aruser : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ARUSER_WIDTH -1 DOWNTO 0 );
m_axi_nvme_arvalid : OUT STD_LOGIC;
m_axi_nvme_awaddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ADDR_WIDTH -1 DOWNTO 0 );
m_axi_nvme_awburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_nvme_awcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_nvme_awid : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 );
m_axi_nvme_awlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_nvme_awlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_nvme_awprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_nvme_awqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_nvme_awready : IN STD_LOGIC;
m_axi_nvme_awregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_nvme_awsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_nvme_awuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_AWUSER_WIDTH -1 DOWNTO 0 );
m_axi_nvme_awvalid : OUT STD_LOGIC;
m_axi_nvme_bid : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 );
m_axi_nvme_bready : OUT STD_LOGIC;
m_axi_nvme_bresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_nvme_buser : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_BUSER_WIDTH -1 downto 0 );
m_axi_nvme_bvalid : IN STD_LOGIC;
m_axi_nvme_rdata : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_DATA_WIDTH -1 DOWNTO 0 );
m_axi_nvme_rid : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 );
m_axi_nvme_rlast : IN STD_LOGIC;
m_axi_nvme_rready : OUT STD_LOGIC;
m_axi_nvme_rresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_nvme_ruser : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_RUSER_WIDTH -1 DOWNTO 0 );
m_axi_nvme_rvalid : IN STD_LOGIC;
m_axi_nvme_wdata : OUT STD_LOGIC_VECTOR (C_M_AXI_NVME_DATA_WIDTH -1 DOWNTO 0 );
m_axi_nvme_wlast : OUT STD_LOGIC;
m_axi_nvme_wready : IN STD_LOGIC;
m_axi_nvme_wstrb : OUT STD_LOGIC_VECTOR ((C_M_AXI_NVME_DATA_WIDTH/8) -1 DOWNTO 0 );
m_axi_nvme_wuser : OUT STD_LOGIC_VECTOR (C_M_AXI_NVME_WUSER_WIDTH -1 DOWNTO 0 );
m_axi_nvme_wvalid : OUT STD_LOGIC;
--
-- AXI Control Register Interface
s_axi_ctrl_reg_araddr : IN STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_arready : OUT STD_LOGIC;
s_axi_ctrl_reg_arvalid : IN STD_LOGIC;
s_axi_ctrl_reg_awaddr : IN STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_awready : OUT STD_LOGIC;
s_axi_ctrl_reg_awvalid : IN STD_LOGIC;
s_axi_ctrl_reg_bready : IN STD_LOGIC;
s_axi_ctrl_reg_bresp : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
s_axi_ctrl_reg_bvalid : OUT STD_LOGIC;
s_axi_ctrl_reg_rdata : OUT STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_rready : IN STD_LOGIC;
s_axi_ctrl_reg_rresp : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
s_axi_ctrl_reg_rvalid : OUT STD_LOGIC;
s_axi_ctrl_reg_wdata : IN STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_wready : OUT STD_LOGIC;
s_axi_ctrl_reg_wstrb : IN STD_LOGIC_VECTOR ( (C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 DOWNTO 0 );
s_axi_ctrl_reg_wvalid : IN STD_LOGIC;
--
-- AXI Host Memory Interface
m_axi_host_mem_araddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_arburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_arcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_arid : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_arlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_host_mem_arlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_arprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_arqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_arready : IN STD_LOGIC;
m_axi_host_mem_arregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_arsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_aruser : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_arvalid : OUT STD_LOGIC;
m_axi_host_mem_awaddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_awburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_awcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_awid : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_awlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_host_mem_awlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_awprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_awqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_awready : IN STD_LOGIC;
m_axi_host_mem_awregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_awsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_awuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_awvalid : OUT STD_LOGIC;
m_axi_host_mem_bid : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_bready : OUT STD_LOGIC;
m_axi_host_mem_bresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_buser : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_BUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_bvalid : IN STD_LOGIC;
m_axi_host_mem_rdata : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_rid : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_rlast : IN STD_LOGIC;
m_axi_host_mem_rready : OUT STD_LOGIC;
m_axi_host_mem_rresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_ruser : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_RUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_rvalid : IN STD_LOGIC;
m_axi_host_mem_wdata : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_wlast : OUT STD_LOGIC;
m_axi_host_mem_wready : IN STD_LOGIC;
m_axi_host_mem_wstrb : OUT STD_LOGIC_VECTOR ( (C_M_AXI_HOST_MEM_DATA_WIDTH/8)-1 DOWNTO 0 );
m_axi_host_mem_wuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_WUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_wvalid : OUT STD_LOGIC
);
END action_wrapper;
ARCHITECTURE STRUCTURE OF action_wrapper IS
COMPONENT action_nvme_example IS
GENERIC (
-- Parameters for Axi Master Bus Interface AXI_CARD_MEM0 : to on-card SDRAM
C_AXI_CARD_MEM0_ID_WIDTH : integer;
C_AXI_CARD_MEM0_ADDR_WIDTH : integer;
C_AXI_CARD_MEM0_DATA_WIDTH : integer;
C_AXI_CARD_MEM0_AWUSER_WIDTH : integer;
C_AXI_CARD_MEM0_ARUSER_WIDTH : integer;
C_AXI_CARD_MEM0_WUSER_WIDTH : integer;
C_AXI_CARD_MEM0_RUSER_WIDTH : integer;
C_AXI_CARD_MEM0_BUSER_WIDTH : integer;
-- Parameters for Axi Slave Bus Interface AXI_CTRL_REG
C_AXI_CTRL_REG_DATA_WIDTH : integer;
C_AXI_CTRL_REG_ADDR_WIDTH : integer;
-- Parameters for Axi Master Bus Interface AXI_HOST_MEM : to Host memory
C_AXI_HOST_MEM_ID_WIDTH : integer;
C_AXI_HOST_MEM_ADDR_WIDTH : integer;
C_AXI_HOST_MEM_DATA_WIDTH : integer;
C_AXI_HOST_MEM_AWUSER_WIDTH : integer;
C_AXI_HOST_MEM_ARUSER_WIDTH : integer;
C_AXI_HOST_MEM_WUSER_WIDTH : integer;
C_AXI_HOST_MEM_RUSER_WIDTH : integer;
C_AXI_HOST_MEM_BUSER_WIDTH : integer;
INT_BITS : integer;
CONTEXT_BITS : integer
);
PORT (
action_clk : IN STD_LOGIC;
action_rst_n : IN STD_LOGIC;
int_req : OUT STD_LOGIC;
int_src : OUT STD_LOGIC_VECTOR(INT_BITS-2 DOWNTO 0);
int_ctx : OUT STD_LOGIC_VECTOR(CONTEXT_BITS-1 DOWNTO 0);
int_req_ack : IN STD_LOGIC;
-- Ports of Axi Master Bus Interface AXI_CARD_MEM0
-- to on-card SDRAM
axi_card_mem0_awaddr : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0);
axi_card_mem0_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_card_mem0_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_awvalid : OUT STD_LOGIC;
axi_card_mem0_awready : IN STD_LOGIC;
axi_card_mem0_wdata : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0);
axi_card_mem0_wstrb : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_DATA_WIDTH/8-1 DOWNTO 0);
axi_card_mem0_wlast : OUT STD_LOGIC;
axi_card_mem0_wvalid : OUT STD_LOGIC;
axi_card_mem0_wready : IN STD_LOGIC;
axi_card_mem0_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_bvalid : IN STD_LOGIC;
axi_card_mem0_bready : OUT STD_LOGIC;
axi_card_mem0_araddr : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0);
axi_card_mem0_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_card_mem0_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_card_mem0_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_card_mem0_arvalid : OUT STD_LOGIC;
axi_card_mem0_arready : IN STD_LOGIC;
axi_card_mem0_rdata : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0);
axi_card_mem0_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_card_mem0_rlast : IN STD_LOGIC;
axi_card_mem0_rvalid : IN STD_LOGIC;
axi_card_mem0_rready : OUT STD_LOGIC;
axi_card_mem0_arid : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_aruser : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ARUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_awid : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_awuser : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_AWUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_bid : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_buser : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_BUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_rid : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0);
axi_card_mem0_ruser : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_RUSER_WIDTH-1 DOWNTO 0);
axi_card_mem0_wuser : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_WUSER_WIDTH-1 DOWNTO 0);
--
-- Ports of Axi Master Bus Interface AXI_NVME
-- to NVME
axi_nvme_awaddr : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ADDR_WIDTH-1 DOWNTO 0);
axi_nvme_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_nvme_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_awvalid : OUT STD_LOGIC;
axi_nvme_awready : IN STD_LOGIC;
axi_nvme_wdata : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_DATA_WIDTH-1 downto 0);
axi_nvme_wstrb : OUT STD_LOGIC_VECTOR((C_M_AXI_NVME_DATA_WIDTH/8)-1 DOWNTO 0);
axi_nvme_wlast : OUT STD_LOGIC;
axi_nvme_wvalid : OUT STD_LOGIC;
axi_nvme_wready : IN STD_LOGIC;
axi_nvme_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_bvalid : IN STD_LOGIC;
axi_nvme_bready : OUT STD_LOGIC;
axi_nvme_araddr : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ADDR_WIDTH-1 downto 0);
axi_nvme_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_nvme_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_nvme_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_nvme_arvalid : OUT STD_LOGIC;
axi_nvme_arready : IN STD_LOGIC;
axi_nvme_rdata : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_DATA_WIDTH-1 DOWNTO 0);
axi_nvme_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_nvme_rlast : IN STD_LOGIC;
axi_nvme_rvalid : IN STD_LOGIC;
axi_nvme_rready : OUT STD_LOGIC;
axi_nvme_arid : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0);
axi_nvme_aruser : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ARUSER_WIDTH-1 DOWNTO 0);
axi_nvme_awid : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0);
axi_nvme_awuser : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_AWUSER_WIDTH-1 DOWNTO 0);
axi_nvme_bid : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0);
axi_nvme_buser : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_BUSER_WIDTH-1 DOWNTO 0);
axi_nvme_rid : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0);
axi_nvme_ruser : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_RUSER_WIDTH-1 DOWNTO 0);
axi_nvme_wuser : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_WUSER_WIDTH-1 DOWNTO 0);
--
-- Ports of Axi Slave Bus Interface AXI_CTRL_REG
axi_ctrl_reg_awaddr : IN STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_awvalid : IN STD_LOGIC;
axi_ctrl_reg_awready : OUT STD_LOGIC;
axi_ctrl_reg_wdata : IN STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_wstrb : IN STD_LOGIC_VECTOR((C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 DOWNTO 0);
axi_ctrl_reg_wvalid : IN STD_LOGIC;
axi_ctrl_reg_wready : OUT STD_LOGIC;
axi_ctrl_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_ctrl_reg_bvalid : OUT STD_LOGIC;
axi_ctrl_reg_bready : IN STD_LOGIC;
axi_ctrl_reg_araddr : IN STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_arvalid : IN STD_LOGIC;
axi_ctrl_reg_arready : OUT STD_LOGIC;
axi_ctrl_reg_rdata : OUT STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_ctrl_reg_rvalid : OUT STD_LOGIC;
axi_ctrl_reg_rready : IN STD_LOGIC;
--
-- Ports of Axi Master Bus Interface AXI_HOST_MEM
-- to HOST memory
axi_host_mem_awaddr : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0);
axi_host_mem_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_host_mem_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awvalid : OUT STD_LOGIC;
axi_host_mem_awready : IN STD_LOGIC;
axi_host_mem_wdata : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0);
axi_host_mem_wstrb : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_DATA_WIDTH/8-1 DOWNTO 0);
axi_host_mem_wlast : OUT STD_LOGIC;
axi_host_mem_wvalid : OUT STD_LOGIC;
axi_host_mem_wready : IN STD_LOGIC;
axi_host_mem_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_bvalid : IN STD_LOGIC;
axi_host_mem_bready : OUT STD_LOGIC;
axi_host_mem_araddr : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0);
axi_host_mem_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_host_mem_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arvalid : OUT STD_LOGIC;
axi_host_mem_arready : IN STD_LOGIC;
axi_host_mem_rdata : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0);
axi_host_mem_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_rlast : IN STD_LOGIC;
axi_host_mem_rvalid : IN STD_LOGIC;
axi_host_mem_rready : OUT STD_LOGIC;
axi_host_mem_arid : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_aruser : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_awid : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_awuser : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_bid : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_buser : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_BUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_rid : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_ruser : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_RUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_wuser : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_WUSER_WIDTH-1 DOWNTO 0)
);
END COMPONENT action_nvme_example;
BEGIN
action_0: COMPONENT action_nvme_example
GENERIC MAP (
-- Parameters for Axi Master Bus Interface AXI_CARD_MEM0 : to on-card SDRAM
C_AXI_CARD_MEM0_ID_WIDTH => C_M_AXI_CARD_MEM0_ID_WIDTH,
C_AXI_CARD_MEM0_ADDR_WIDTH => C_M_AXI_CARD_MEM0_ADDR_WIDTH,
C_AXI_CARD_MEM0_DATA_WIDTH => C_M_AXI_CARD_MEM0_DATA_WIDTH,
C_AXI_CARD_MEM0_AWUSER_WIDTH => C_M_AXI_CARD_MEM0_AWUSER_WIDTH,
C_AXI_CARD_MEM0_ARUSER_WIDTH => C_M_AXI_CARD_MEM0_ARUSER_WIDTH,
C_AXI_CARD_MEM0_WUSER_WIDTH => C_M_AXI_CARD_MEM0_WUSER_WIDTH,
C_AXI_CARD_MEM0_RUSER_WIDTH => C_M_AXI_CARD_MEM0_RUSER_WIDTH,
C_AXI_CARD_MEM0_BUSER_WIDTH => C_M_AXI_CARD_MEM0_BUSER_WIDTH,
-- Parameters for Axi Slave Bus Interface AXI_CTRL_REG
C_AXI_CTRL_REG_DATA_WIDTH => C_S_AXI_CTRL_REG_DATA_WIDTH,
C_AXI_CTRL_REG_ADDR_WIDTH => C_S_AXI_CTRL_REG_ADDR_WIDTH,
-- Parameters for Axi Master Bus Interface AXI_HOST_MEM : to Host memory
C_AXI_HOST_MEM_ID_WIDTH => C_M_AXI_HOST_MEM_ID_WIDTH,
C_AXI_HOST_MEM_ADDR_WIDTH => C_M_AXI_HOST_MEM_ADDR_WIDTH,
C_AXI_HOST_MEM_DATA_WIDTH => C_M_AXI_HOST_MEM_DATA_WIDTH,
C_AXI_HOST_MEM_AWUSER_WIDTH => C_M_AXI_HOST_MEM_AWUSER_WIDTH,
C_AXI_HOST_MEM_ARUSER_WIDTH => C_M_AXI_HOST_MEM_ARUSER_WIDTH,
C_AXI_HOST_MEM_WUSER_WIDTH => C_M_AXI_HOST_MEM_WUSER_WIDTH,
C_AXI_HOST_MEM_RUSER_WIDTH => C_M_AXI_HOST_MEM_RUSER_WIDTH,
C_AXI_HOST_MEM_BUSER_WIDTH => C_M_AXI_HOST_MEM_BUSER_WIDTH,
INT_BITS => INT_BITS,
CONTEXT_BITS => CONTEXT_BITS
)
PORT MAP (
action_clk => ap_clk,
action_rst_n => ap_rst_n,
int_req => interrupt,
int_src => interrupt_src,
int_ctx => interrupt_ctx,
int_req_ack => interrupt_ack,
axi_card_mem0_araddr => m_axi_card_mem0_araddr,
axi_card_mem0_arburst => m_axi_card_mem0_arburst,
axi_card_mem0_arcache => m_axi_card_mem0_arcache,
axi_card_mem0_arid => m_axi_card_mem0_arid,
axi_card_mem0_arlen => m_axi_card_mem0_arlen,
axi_card_mem0_arlock => m_axi_card_mem0_arlock,
axi_card_mem0_arprot => m_axi_card_mem0_arprot,
axi_card_mem0_arqos => m_axi_card_mem0_arqos,
axi_card_mem0_arready => m_axi_card_mem0_arready,
axi_card_mem0_arregion => m_axi_card_mem0_arregion,
axi_card_mem0_arsize => m_axi_card_mem0_arsize,
axi_card_mem0_aruser => m_axi_card_mem0_aruser,
axi_card_mem0_arvalid => m_axi_card_mem0_arvalid,
axi_card_mem0_awaddr => m_axi_card_mem0_awaddr,
axi_card_mem0_awburst => m_axi_card_mem0_awburst,
axi_card_mem0_awcache => m_axi_card_mem0_awcache,
axi_card_mem0_awid => m_axi_card_mem0_awid,
axi_card_mem0_awlen => m_axi_card_mem0_awlen,
axi_card_mem0_awlock => m_axi_card_mem0_awlock,
axi_card_mem0_awprot => m_axi_card_mem0_awprot,
axi_card_mem0_awqos => m_axi_card_mem0_awqos,
axi_card_mem0_awready => m_axi_card_mem0_awready,
axi_card_mem0_awregion => m_axi_card_mem0_awregion,
axi_card_mem0_awsize => m_axi_card_mem0_awsize,
axi_card_mem0_awuser => m_axi_card_mem0_awuser,
axi_card_mem0_awvalid => m_axi_card_mem0_awvalid,
axi_card_mem0_bid => m_axi_card_mem0_bid,
axi_card_mem0_bready => m_axi_card_mem0_bready,
axi_card_mem0_bresp => m_axi_card_mem0_bresp,
axi_card_mem0_buser => m_axi_card_mem0_buser,
axi_card_mem0_bvalid => m_axi_card_mem0_bvalid,
axi_card_mem0_rdata => m_axi_card_mem0_rdata,
axi_card_mem0_rid => m_axi_card_mem0_rid,
axi_card_mem0_rlast => m_axi_card_mem0_rlast,
axi_card_mem0_rready => m_axi_card_mem0_rready,
axi_card_mem0_rresp => m_axi_card_mem0_rresp,
axi_card_mem0_ruser => m_axi_card_mem0_ruser,
axi_card_mem0_rvalid => m_axi_card_mem0_rvalid,
axi_card_mem0_wdata => m_axi_card_mem0_wdata,
axi_card_mem0_wlast => m_axi_card_mem0_wlast,
axi_card_mem0_wready => m_axi_card_mem0_wready,
axi_card_mem0_wstrb => m_axi_card_mem0_wstrb,
axi_card_mem0_wuser => m_axi_card_mem0_wuser,
axi_card_mem0_wvalid => m_axi_card_mem0_wvalid,
axi_nvme_araddr => m_axi_nvme_araddr,
axi_nvme_arburst => m_axi_nvme_arburst,
axi_nvme_arcache => m_axi_nvme_arcache,
axi_nvme_arid => m_axi_nvme_arid,
axi_nvme_arlen => m_axi_nvme_arlen,
axi_nvme_arlock => m_axi_nvme_arlock,
axi_nvme_arprot => m_axi_nvme_arprot,
axi_nvme_arqos => m_axi_nvme_arqos,
axi_nvme_arready => m_axi_nvme_arready,
axi_nvme_arregion => m_axi_nvme_arregion,
axi_nvme_arsize => m_axi_nvme_arsize,
axi_nvme_aruser => m_axi_nvme_aruser,
axi_nvme_arvalid => m_axi_nvme_arvalid,
axi_nvme_awaddr => m_axi_nvme_awaddr,
axi_nvme_awburst => m_axi_nvme_awburst,
axi_nvme_awcache => m_axi_nvme_awcache,
axi_nvme_awid => m_axi_nvme_awid,
axi_nvme_awlen => m_axi_nvme_awlen,
axi_nvme_awlock => m_axi_nvme_awlock,
axi_nvme_awprot => m_axi_nvme_awprot,
axi_nvme_awqos => m_axi_nvme_awqos,
axi_nvme_awready => m_axi_nvme_awready,
axi_nvme_awregion => m_axi_nvme_awregion,
axi_nvme_awsize => m_axi_nvme_awsize,
axi_nvme_awuser => m_axi_nvme_awuser,
axi_nvme_awvalid => m_axi_nvme_awvalid,
axi_nvme_bid => m_axi_nvme_bid,
axi_nvme_bready => m_axi_nvme_bready,
axi_nvme_bresp => m_axi_nvme_bresp,
axi_nvme_buser => m_axi_nvme_buser,
axi_nvme_bvalid => m_axi_nvme_bvalid,
axi_nvme_rdata => m_axi_nvme_rdata,
axi_nvme_rid => m_axi_nvme_rid,
axi_nvme_rlast => m_axi_nvme_rlast,
axi_nvme_rready => m_axi_nvme_rready,
axi_nvme_rresp => m_axi_nvme_rresp,
axi_nvme_ruser => m_axi_nvme_ruser,
axi_nvme_rvalid => m_axi_nvme_rvalid,
axi_nvme_wdata => m_axi_nvme_wdata,
axi_nvme_wlast => m_axi_nvme_wlast,
axi_nvme_wready => m_axi_nvme_wready,
axi_nvme_wstrb => m_axi_nvme_wstrb,
axi_nvme_wuser => m_axi_nvme_wuser,
axi_nvme_wvalid => m_axi_nvme_wvalid,
axi_ctrl_reg_araddr => s_axi_ctrl_reg_araddr,
axi_ctrl_reg_arready => s_axi_ctrl_reg_arready,
axi_ctrl_reg_arvalid => s_axi_ctrl_reg_arvalid,
axi_ctrl_reg_awaddr => s_axi_ctrl_reg_awaddr,
axi_ctrl_reg_awready => s_axi_ctrl_reg_awready,
axi_ctrl_reg_awvalid => s_axi_ctrl_reg_awvalid,
axi_ctrl_reg_bready => s_axi_ctrl_reg_bready,
axi_ctrl_reg_bresp => s_axi_ctrl_reg_bresp,
axi_ctrl_reg_bvalid => s_axi_ctrl_reg_bvalid,
axi_ctrl_reg_rdata => s_axi_ctrl_reg_rdata,
axi_ctrl_reg_rready => s_axi_ctrl_reg_rready,
axi_ctrl_reg_rresp => s_axi_ctrl_reg_rresp,
axi_ctrl_reg_rvalid => s_axi_ctrl_reg_rvalid,
axi_ctrl_reg_wdata => s_axi_ctrl_reg_wdata,
axi_ctrl_reg_wready => s_axi_ctrl_reg_wready,
axi_ctrl_reg_wstrb => s_axi_ctrl_reg_wstrb,
axi_ctrl_reg_wvalid => s_axi_ctrl_reg_wvalid,
axi_host_mem_araddr => m_axi_host_mem_araddr,
axi_host_mem_arburst => m_axi_host_mem_arburst,
axi_host_mem_arcache => m_axi_host_mem_arcache,
axi_host_mem_arid => m_axi_host_mem_arid,
axi_host_mem_arlen => m_axi_host_mem_arlen,
axi_host_mem_arlock => m_axi_host_mem_arlock,
axi_host_mem_arprot => m_axi_host_mem_arprot,
axi_host_mem_arqos => m_axi_host_mem_arqos,
axi_host_mem_arready => m_axi_host_mem_arready,
axi_host_mem_arregion => m_axi_host_mem_arregion,
axi_host_mem_arsize => m_axi_host_mem_arsize,
axi_host_mem_aruser => m_axi_host_mem_aruser,
axi_host_mem_arvalid => m_axi_host_mem_arvalid,
axi_host_mem_awaddr => m_axi_host_mem_awaddr,
axi_host_mem_awburst => m_axi_host_mem_awburst,
axi_host_mem_awcache => m_axi_host_mem_awcache,
axi_host_mem_awid => m_axi_host_mem_awid,
axi_host_mem_awlen => m_axi_host_mem_awlen,
axi_host_mem_awlock => m_axi_host_mem_awlock,
axi_host_mem_awprot => m_axi_host_mem_awprot,
axi_host_mem_awqos => m_axi_host_mem_awqos,
axi_host_mem_awready => m_axi_host_mem_awready,
axi_host_mem_awregion => m_axi_host_mem_awregion,
axi_host_mem_awsize => m_axi_host_mem_awsize,
axi_host_mem_awuser => m_axi_host_mem_awuser,
axi_host_mem_awvalid => m_axi_host_mem_awvalid,
axi_host_mem_bid => m_axi_host_mem_bid,
axi_host_mem_bready => m_axi_host_mem_bready,
axi_host_mem_bresp => m_axi_host_mem_bresp,
axi_host_mem_buser => m_axi_host_mem_buser,
axi_host_mem_bvalid => m_axi_host_mem_bvalid,
axi_host_mem_rdata => m_axi_host_mem_rdata,
axi_host_mem_rid => m_axi_host_mem_rid,
axi_host_mem_rlast => m_axi_host_mem_rlast,
axi_host_mem_rready => m_axi_host_mem_rready,
axi_host_mem_rresp => m_axi_host_mem_rresp,
axi_host_mem_ruser => m_axi_host_mem_ruser,
axi_host_mem_rvalid => m_axi_host_mem_rvalid,
axi_host_mem_wdata => m_axi_host_mem_wdata,
axi_host_mem_wlast => m_axi_host_mem_wlast,
axi_host_mem_wready => m_axi_host_mem_wready,
axi_host_mem_wstrb => m_axi_host_mem_wstrb,
axi_host_mem_wuser => m_axi_host_mem_wuser,
axi_host_mem_wvalid => m_axi_host_mem_wvalid
);
END STRUCTURE;
| apache-2.0 | fcd02c4ff16c77ca1b7728d858fa62c8 | 0.584651 | 2.964799 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/mem/ddr2/memtest_Nexys4DDR.vhdl | 1 | 9,406 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory tester for Nexys4 DDR board using Xilinx MIG.
--
-- Description:
-- ------------------------------------
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
-- Copyrigth 2018 Martin Zabel
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library poc;
use poc.utils.all;
entity memtest_Nexys4DDR is
generic (
-- Must match configuration of generated mig_Nexys4DDR
ADDR_WIDTH : integer := 27;
BANK_WIDTH : integer := 3;
CK_WIDTH : integer := 1;
nCK_PER_CLK : integer := 4;
CS_WIDTH : integer := 1;
nCS_PER_RANK : integer := 1;
CKE_WIDTH : integer := 1;
DM_WIDTH : integer := 2;
DQ_WIDTH : integer := 16;
DQS_WIDTH : integer := 2;
PAYLOAD_WIDTH : integer := 16;
ROW_WIDTH : integer := 13;
ODT_WIDTH : integer := 1);
port (
sys_clk_i : in std_logic;
led : out std_logic_vector(7 downto 0);
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0));
end entity memtest_Nexys4DDR;
architecture rtl of memtest_Nexys4DDR is
signal sys_clk_unbuf : std_logic;
signal clk_ref : std_logic;
signal ref_clk_locked : std_logic;
signal memtest0_status : std_logic_vector(2 downto 0);
-- Memory Controller signals
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal ui_clk : std_logic;
signal ui_clk_sync_rst : std_logic;
signal init_calib_complete : std_logic;
begin -- architecture rtl
----------------------------------------------------------------------------
-- Clocking
----------------------------------------------------------------------------
-- This system clock is used two-fold:
--
-- 1) It is used as the system clock for the memory controllers
-- (MIG). There it feeds only PLLs, so that, dedicated routing can be
-- used and no BUFG is required.
--
-- 2) It is also used to generate a 200 MHz reference clock used for the
-- IDELAYCTRL and temperature monitor logic.
-- This requires a BUFG, but could also be driven by another 200 MHz
-- clock source. If this other clock is not free-runnning, then
-- IDELAYCTRL and the temperature monitor must be hold in reset until
-- this other clock is stable.
sys_clk_ibufg : IBUFG port map (
I => sys_clk_i,
O => sys_clk_unbuf);
ref_clk_pll : entity work.pll_ref_clk
port map (
CLK_IN1 => sys_clk_unbuf,
CLK_OUT1 => clk_ref, -- 200 MHz reference clock driven by BUFG
LOCKED => ref_clk_locked); -- will hold IDELAYCTRL in reset by
-- by driving sys_rst of 'mig'
-----------------------------------------------------------------------------
-- MemoryTester for Port 0
-----------------------------------------------------------------------------
MemoryTester0 : block
constant BYTE_ADDR_BITS : natural := 4; -- 16 Byte / Word
constant WORD_ADDR_BITS : natural := ite(SIMULATION,
15, -- 32 KByte = 2 rows
27) -- 128 MB = 1 GBit
-BYTE_ADDR_BITS;
signal mem_rdy : std_logic;
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(WORD_ADDR_BITS-1 downto 0);
signal mem_wdata : std_logic_vector(127 downto 0);
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(127 downto 0);
begin -- block MemoryTester0
fsm: entity work.memtest_fsm
generic map (
A_BITS => WORD_ADDR_BITS,
D_BITS => 128)
port map (
clk => ui_clk,
rst => ui_clk_sync_rst,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
status => memtest0_status);
adapter : entity poc.ddr3_mem2mig_adapter_Series7
generic map (
D_BITS => 128,
DQ_BITS => DQ_WIDTH,
MEM_A_BITS => WORD_ADDR_BITS,
APP_A_BITS => app_addr'length)
port map (
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
init_calib_complete => init_calib_complete,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren);
end block MemoryTester0;
-----------------------------------------------------------------------------
-- Memory Controller Instantiation
-----------------------------------------------------------------------------
mig : entity work.mig_Nexys4DDR
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
sys_clk_i => sys_clk_unbuf,
clk_ref_i => clk_ref,
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => init_calib_complete,
sys_rst => ref_clk_locked); -- active low
-----------------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------------
led(7) <= ui_clk_sync_rst;
led(6) <= ref_clk_locked;
led(5) <= '0';
led(4) <= '0';
led(3) <= init_calib_complete;
led(2 downto 0) <= memtest0_status;
end architecture rtl;
| apache-2.0 | c8db683e59513314f96b50d5b7ec21bb | 0.520838 | 3.416636 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/slice_number.vhd | 1 | 2,229 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity slice_number is
Generic(n :natural := 7);
Port ( integerNumber : in std_logic_vector(n downto 0); -- recebe um vetor de bits da interface
receives_input : in std_logic;
MDDreset : in std_logic;
clk : in std_logic;
finish : out std_logic;
unity : out STD_LOGIC_vector(9 downto 0); --retorna o codigo do display do digito presente na unidade
dicker : out STD_LOGIC_vector(9 downto 0); -- retorna o codigo do display do digito presente na dezena
hundred : out STD_LOGIC_vector(9 downto 0) -- retorna o codigo do display do digito presente na centena
);
end slice_number;
architecture Behavioral of slice_number is
----------- #### SINAIS #### --------
signal dividendo : std_logic_vector(n downto 0);
signal dez,cem : std_logic_vector(n downto 0);
signal enable : std_logic;
signal finishDez, finishCem : std_logic;
signal quocienteCem, quocienteDez : std_logic_vector(n downto 0);
signal restoCem, restoDez : std_logic_vector(n downto 0);
----------- #### COMPONENTES #### --------
begin
dividendo <= integerNumber;
enable <= receives_input;
MaquinaDeDividirCentena: entity work.MaquinaDeDividir port map
(clk, dividendo, cem, restoCem, quocienteCem, enable, finishDez, MDDreset);
MaquinaDeDividirDezena : entity work.MaquinaDeDividir port map
(clk, restoCem, dez, restoDez, quocienteDez, finishDez, finishCem, MDDreset);
Dez <= "00001010";
Cem <= "01100100";
finish <= (finishCem and finishDez);
-- quocienteCem <= std_logic_vector(unsigned(quocienteDez)-unsigned(quocienteDez)*10);
process(clk,quocienteCem, quocienteDez, restoDez)
begin
if (rising_edge(clk) and receives_input = '1') then
hundred(9 downto 4) <= "100011";
hundred(3 downto 0) <= quocienteCem(3 downto 0);
dicker(9 downto 4) <= "100011";
dicker(3 downto 0) <= quocienteDez(3 downto 0);
unity(9 downto 4) <= "100011";
unity(3 downto 0) <= restoDez(3 downto 0);
-- hundred <= "100011" & quocienteCem(3 downto 0);
-- dicker <= "100011" & quocienteDez(3 downto 0);
-- unity <= "100011" & restoDez(3 downto 0);
end if;
end process;
end Behavioral;
| gpl-3.0 | db1c0ce5290d0eba72781263fba22446 | 0.666667 | 3.249271 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/sim/RAT_ScratchRam_0_0.vhd | 1 | 3,423 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:ScratchRam:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_ScratchRam_0_0 IS
PORT (
DATA_IN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WE : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END RAT_ScratchRam_0_0;
ARCHITECTURE RAT_ScratchRam_0_0_arch OF RAT_ScratchRam_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ScratchRam_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ScratchRam IS
PORT (
DATA_IN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WE : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END COMPONENT ScratchRam;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : ScratchRam
PORT MAP (
DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT,
ADDR => ADDR,
WE => WE,
CLK => CLK
);
END RAT_ScratchRam_0_0_arch;
| mit | 4c0032c5ad42f30bf2c8e7ca41c95b2f | 0.726264 | 4.046099 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_ML605.vhdl | 1 | 12,618 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_ML605 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 200 MHz
);
port (
ClockIn_200MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_200MHz : out STD_LOGIC;
Clock_250MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_250MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- DCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 200.000 0.000 50.0
-- CLK_OUT1 100.000 0.000 50.0
-- CLK_OUT2 125.000 0.000 50.0
-- CLK_OUT3 250.000 0.000 50.0
-- CLK_OUT4 10.000 0.000 50.0
--
architecture rtl of clknet_ClockNetwork_ML605 is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 200 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (200 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal MMCM_Reset : STD_LOGIC;
signal MMCM_Reset_clr : STD_LOGIC;
signal MMCM_ResetState : STD_LOGIC := '0';
signal MMCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal MMCM_Locked_async : STD_LOGIC;
signal MMCM_Locked : STD_LOGIC;
signal MMCM_Locked_d : STD_LOGIC := '0';
signal MMCM_Locked_re : STD_LOGIC;
signal MMCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal MMCM_Clock_10MHz : STD_LOGIC;
signal MMCM_Clock_100MHz : STD_LOGIC;
signal MMCM_Clock_125MHz : STD_LOGIC;
signal MMCM_Clock_200MHz : STD_LOGIC;
signal MMCM_Clock_250MHz : STD_LOGIC;
signal MMCM_Clock_10MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_100MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_125MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_200MHz_BUFG : STD_LOGIC;
signal MMCM_Clock_250MHz_BUFG : STD_LOGIC;
attribute KEEP of MMCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_200MHz_BUFG : signal is DEBUG;
attribute KEEP of MMCM_Clock_250MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) MMCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => MMCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => MMCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
MMCM_Reset_clr <= ClkNet_Reset nor MMCM_Locked;
-- detect rising edge on CMB locked signals
MMCM_Locked_d <= MMCM_Locked when rising_edge(Control_Clock);
MMCM_Locked_re <= not MMCM_Locked_d and MMCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
MMCM_ResetState <= ffrs(q => MMCM_ResetState, rst => MMCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
MMCM_LockedState <= ffrs(q => MMCM_LockedState, rst => MMCM_Reset, set => MMCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
MMCM_Reset_delayed <= shreg_left(MMCM_Reset_delayed, MMCM_ResetState) when rising_edge(Control_Clock);
MMCM_Reset <= MMCM_Reset_delayed(MMCM_Reset_delayed'high);
Locked <= MMCM_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
generic map (
SIM_DEVICE => "VIRTEX6"
)
port map (
CE => '1',
CLR => '0',
I => ClockIn_200MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 10 MHz BUFG
BUFG_Clock_10MHz : BUFG
port map (
I => MMCM_Clock_10MHz,
O => MMCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => MMCM_Clock_100MHz,
O => MMCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_Clock_125MHz : BUFG
port map (
I => MMCM_Clock_125MHz,
O => MMCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => MMCM_Clock_200MHz,
O => MMCM_Clock_200MHz_BUFG
);
-- 250 MHz BUFG
BUFG_Clock_250MHz : BUFG
port map (
I => MMCM_Clock_250MHz,
O => MMCM_Clock_250MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (MMCM)
-- ==================================================================
System_MMCM : MMCM_ADV
generic map (
CLOCK_HOLD => FALSE,
STARTUP_WAIT => FALSE,
BANDWIDTH => "LOW", -- LOW = Jitter Filter
COMPENSATION => "BUF_IN", --"ZHOLD",
CLKIN1_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKIN2_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz), -- Not used
REF_JITTER1 => 0.00048,
REF_JITTER2 => 0.00048, -- Not used
CLKFBOUT_MULT_F => 5.0,
CLKFBOUT_PHASE => 0.0,
CLKFBOUT_USE_FINE_PS => FALSE,
DIVCLK_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 5.0,
CLKOUT0_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.0,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_DIVIDE => 4,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 100,
CLKOUT4_PHASE => 0.0,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => FALSE
)
port map (
RST => MMCM_Reset,
CLKIN1 => ClockIn_200MHz,
CLKIN2 => ClockIn_200MHz,
CLKINSEL => '1',
CLKINSTOPPED => open,
CLKFBOUT => open,
CLKFBOUTB => open,
CLKFBIN => MMCM_Clock_200MHz_BUFG,
CLKFBSTOPPED => open,
CLKOUT0 => MMCM_Clock_200MHz,
CLKOUT0B => open,
CLKOUT1 => MMCM_Clock_100MHz,
CLKOUT1B => open,
CLKOUT2 => MMCM_Clock_125MHz,
CLKOUT2B => open,
CLKOUT3 => MMCM_Clock_250MHz,
CLKOUT3B => open,
CLKOUT4 => MMCM_Clock_10MHz,
CLKOUT5 => open,
CLKOUT6 => open,
-- Dynamic Reconfiguration Port
DO => open,
DRDY => open,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PWRDWN => '0',
LOCKED => MMCM_Locked_async,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open
);
Control_Clock_200MHz <= Control_Clock_BUFR;
Clock_250MHz <= MMCM_Clock_250MHz_BUFG;
Clock_200MHz <= MMCM_Clock_200MHz_BUFG;
Clock_125MHz <= MMCM_Clock_125MHz_BUFG;
Clock_100MHz <= MMCM_Clock_100MHz_BUFG;
Clock_10MHz <= MMCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to ouput clock domains
syncLocked250MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_250MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_250MHz -- synchronized data
);
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => MMCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | e0a0bd0791309ff5436f8a118d9e5ef3 | 0.522032 | 3.589758 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/Somador1bit.vhd | 1 | 1,256 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:31:38 03/28/2017
-- Design Name:
-- Module Name: Somador1bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Somador1bit is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
z : out STD_LOGIC;
p : out STD_LOGIC;
g : out STD_LOGIC);
end Somador1bit;
architecture Behavioral of Somador1bit is
signal a: std_logic;
signal b: std_logic;
begin
a <= x and y;
b <= x xor y;
z <= x xor y xor cin;
cout <= a or (b and cin);
p <= b;
g <= a;
end Behavioral;
| gpl-3.0 | 894646021a76db403df5b3d80a5f4454 | 0.557325 | 3.64058 | false | false | false | false |
BBN-Q/VHDL-Components | src/DownCounter.vhd | 1 | 881 | ----
-- Original author: Blake Johnson
-- Copyright 2015,2016 Raytheon BBN Technologies
--
-- A basic down counter.
----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DownCounter is
generic ( nbits : natural := 8 );
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
load_value : in std_logic_vector(nbits-1 downto 0);
load : in std_logic;
Q : out std_logic_vector(nbits-1 downto 0)
);
end DownCounter;
architecture arch of DownCounter is
signal value : std_logic_vector(nbits-1 downto 0) := (others => '0');
begin
Q <= value;
main: process ( clk )
begin
if rising_edge(clk) then
if rst = '1' then
value <= (others => '0');
else
if load = '1' then
value <= load_value;
elsif en = '1' then
value <= std_logic_vector(unsigned(value) - 1);
end if;
end if;
end if;
end process;
end arch;
| mpl-2.0 | fb7955b84065215e0121593919e7a670 | 0.643587 | 2.823718 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_8_0_0/synth/RAT_Mux2x1_8_0_0.vhd | 2 | 3,736 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux2x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux2x1_8_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux2x1_8_0_0;
ARCHITECTURE RAT_Mux2x1_8_0_0_arch OF RAT_Mux2x1_8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT Mux2x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC;
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux2x1_8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "Mux2x1_8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux2x1_8_0_0_arch : ARCHITECTURE IS "RAT_Mux2x1_8_0_0,Mux2x1_8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux2x1_8_0_0_arch: ARCHITECTURE IS "RAT_Mux2x1_8_0_0,Mux2x1_8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux2x1_8,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : Mux2x1_8
PORT MAP (
A => A,
B => B,
SEL => SEL,
X => X
);
END RAT_Mux2x1_8_0_0_arch;
| mit | f16364e7996b398b92c1d343c8727f58 | 0.728854 | 3.571702 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/io/FanControl/top_FanControl_ML605.vhdl | 1 | 7,206 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Top-Module: FanControl example design for a ML605 board
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library PoC;
use PoC.physical.all;
entity top_FanControl_ML605 is
port (
ML605_SystemClock_200MHz_p : in STD_LOGIC;
ML605_SystemClock_200MHz_n : in STD_LOGIC;
ML605_GPIO_LED : out STD_LOGIC_VECTOR(7 downto 0);
ML605_FanControl_PWM : out STD_LOGIC;
ML605_FanControl_Tacho : in STD_LOGIC
);
end entity;
architecture top of top_FanControl_ML605 is
attribute KEEP : BOOLEAN;
-- ===========================================================================
-- configurations
-- ===========================================================================
-- common configuration
constant DEBUG : BOOLEAN := TRUE;
constant SYS_CLOCK_FREQ : FREQ := 200 MHz;
-- ClockNetwork configuration
-- ===========================================================================
constant SYSTEM_CLOCK_FREQ : FREQ := SYS_CLOCK_FREQ / 2;
-- ===========================================================================
-- signal declarations
-- ===========================================================================
-- clock and reset signals
signal System_RefClock_200MHz : STD_LOGIC;
signal ClkNet_Reset : STD_LOGIC;
signal ClkNet_ResetDone : STD_LOGIC;
signal SystemClock_200MHz : STD_LOGIC;
signal SystemClock_100MHz : STD_LOGIC;
signal SystemClock_Stable_200MHz : STD_LOGIC;
signal SystemClock_Stable_100MHz : STD_LOGIC;
signal System_Clock : STD_LOGIC;
signal System_Reset : STD_LOGIC;
attribute KEEP of System_Clock : signal is TRUE;
attribute KEEP of System_Reset : signal is TRUE;
begin
-- ===========================================================================
-- assert statements
-- ===========================================================================
assert FALSE report "FanControl configuration:" severity NOTE;
assert FALSE report " SYS_CLOCK_FREQ: " & to_string(SYS_CLOCK_FREQ, 3) severity note;
-- ===========================================================================
-- Input/output buffers
-- ===========================================================================
IBUFGDS_SystemClock : IBUFGDS
port map (
I => ML605_SystemClock_200MHz_p,
IB => ML605_SystemClock_200MHz_n,
O => System_RefClock_200MHz
);
-- ==========================================================================================================================================================
-- ClockNetwork
-- ==========================================================================================================================================================
ClkNet_Reset <= '0';
ClkNet : entity PoC.clknet_ClockNetwork_ML605
generic map (
CLOCK_IN_FREQ => SYS_CLOCK_FREQ
)
port map (
ClockIn_200MHz => System_RefClock_200MHz,
ClockNetwork_Reset => ClkNet_Reset,
ClockNetwork_ResetDone => ClkNet_ResetDone,
Control_Clock_200MHz => open,
Clock_250MHz => open,
Clock_200MHz => SystemClock_200MHz,
Clock_125MHz => open,
Clock_100MHz => SystemClock_100MHz,
Clock_10MHz => open,
Clock_Stable_250MHz => open,
Clock_Stable_200MHz => SystemClock_Stable_200MHz,
Clock_Stable_125MHz => open,
Clock_Stable_100MHz => SystemClock_Stable_100MHz,
Clock_Stable_10MHz => open
);
-- system signals
System_Clock <= SystemClock_100MHz;
System_Reset <= not SystemClock_Stable_100MHz;
-- ==========================================================================================================================================================
-- General Purpose I/O
-- ==========================================================================================================================================================
blkGPIO : block
signal GPIO_LED : STD_LOGIC_VECTOR(7 downto 0);
signal GPIO_LED_d : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
GPIO_LED <= "0000000" & ClkNet_ResetDone;
GPIO_LED_d <= GPIO_LED when rising_edge(System_Clock);
ML605_GPIO_LED <= GPIO_LED_d;
end block;
-- ==========================================================================================================================================================
-- Fan Control
-- ==========================================================================================================================================================
blkFanControl : block
signal FanControl_PWM : STD_LOGIC;
signal FanControl_PWM_d : STD_LOGIC := '0';
signal FanControl_Tacho_async : STD_LOGIC;
signal FanControl_Tacho_sync : STD_LOGIC;
begin
FanControl_Tacho_async <= ML605_FanControl_Tacho;
sync : entity PoC.sync_Bits
port map (
Clock => System_Clock, -- Clock to be synchronized to
Input(0) => FanControl_Tacho_async, -- Data to be synchronized
Output(0) => FanControl_Tacho_sync -- synchronized data
);
Fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => SYSTEM_CLOCK_FREQ -- 100 MHz
)
port map (
Clock => System_Clock,
Reset => System_Reset,
Fan_PWM => FanControl_PWM,
Fan_Tacho => FanControl_Tacho_sync,
TachoFrequency => open
);
-- IOB-FF
FanControl_PWM_d <= FanControl_PWM when rising_edge(System_Clock);
ML605_FanControl_PWM <= FanControl_PWM_d;
end block;
end architecture;
| apache-2.0 | 5659fa89a44e5261df532bfdf2029d2c | 0.451568 | 4.706728 | false | false | false | false |
stefanct/aua | hw/io/sc_uart/src/fifo.vhd | 1 | 3,525 | --
--
-- This file is a part of JOP, the Java Optimized Processor
--
-- Copyright (C) 2001-2008, Martin Schoeberl ([email protected])
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- fifo.vhd
--
-- simple fifo
--
-- uses FF and every rd or wr has to 'bubble' through the hole fifo.
--
-- Author: Martin Schoeberl [email protected]
--
--
-- resources on ACEX1K
--
-- (width+2)*depth-1 LCs
--
--
-- 2002-01-06 first working version
-- 2002-11-03 a signal for reaching threshold
-- 2005-02-20 change entity order for modelsim vcom
--
library ieee;
use ieee.std_logic_1164.all;
entity fifo_elem is
generic (width : integer);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
rd_prev : out std_logic;
full : out std_logic
);
end fifo_elem;
architecture rtl of fifo_elem is
signal buf : std_logic_vector(width-1 downto 0);
signal f : std_logic;
begin
dout <= buf;
process(clk, reset, f)
begin
full <= f;
if (reset='1') then
buf <= (others => '0');
f <= '0';
rd_prev <= '0';
elsif rising_edge(clk) then
rd_prev <= '0';
if f='0' then
if wr='1' then
rd_prev <= '1';
buf <= din;
f <= '1';
end if;
else
if rd='1' then
f <= '0';
end if;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic (width : integer := 8; depth : integer := 4; thres : integer := 2);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
half : out std_logic
);
end fifo ;
architecture rtl of fifo is
component fifo_elem is
generic (width : integer);
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(width-1 downto 0);
dout : out std_logic_vector(width-1 downto 0);
rd : in std_logic;
wr : in std_logic;
rd_prev : out std_logic;
full : out std_logic
);
end component;
signal r, w, rp, f : std_logic_vector(depth-1 downto 0);
type d_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal di, do : d_array;
begin
g1: for i in 0 to depth-1 generate
f1: fifo_elem generic map (width)
port map (clk, reset, di(i), do(i), r(i), w(i), rp(i), f(i));
x: if i<depth-1 generate
r(i) <= rp(i+1);
w(i+1) <= f(i);
di(i+1) <= do(i);
end generate;
end generate;
di(0) <= din;
dout <= do(depth-1);
w(0) <= wr;
r(depth-1) <= rd;
full <= f(0);
half <= f(depth-thres);
empty <= not f(depth-1);
end rtl;
| gpl-3.0 | 7e38832d7150452b107cb93edf3dbc31 | 0.605957 | 2.709454 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Principal/MultBcd_1xNDig.vhd | 2 | 1,994 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity MultBcd_1xNDig is
Port ( A : in unsigned (3 downto 0);
B : in unsigned (19 downto 0);
Z : out unsigned (23 downto 0));
end MultBcd_1xNDig;
architecture Behavioral of MultBcd_1xNDig is
component MultBcd_1Dig is
port (
a_bcd_1dig : in unsigned (3 downto 0);
b_bcd_1dig : in unsigned (3 downto 0);
cin_bcd_1dig : in unsigned (3 downto 0);
z_bcd_1dig : out unsigned (3 downto 0);
cout_bcd_1dig : out unsigned (3 downto 0)
);
end component;
signal Zaux: unsigned(19 downto 0) := (others => '0');
signal CarryOut: unsigned(19 downto 0);
begin
MULT1: MultBcd_1Dig port map (
a_bcd_1dig => A,
b_bcd_1dig => B(3 downto 0),
cin_bcd_1dig => "0000",
z_bcd_1dig => Zaux(3 downto 0),
cout_bcd_1dig => CarryOut(3 downto 0)
);
MULT2: MultBcd_1Dig port map (
a_bcd_1dig => A,
b_bcd_1dig => B(7 downto 4),
cin_bcd_1dig => CarryOut(3 downto 0),
z_bcd_1dig => Zaux(7 downto 4),
cout_bcd_1dig => CarryOut(7 downto 4)
);
MULT3: MultBcd_1Dig port map (
a_bcd_1dig => A,
b_bcd_1dig => B(11 downto 8),
cin_bcd_1dig => CarryOut(7 downto 4),
z_bcd_1dig => Zaux(11 downto 8),
cout_bcd_1dig => CarryOut(11 downto 8)
);
MULT4: MultBcd_1Dig port map (
a_bcd_1dig => A,
b_bcd_1dig => B(15 downto 12),
cin_bcd_1dig => CarryOut(11 downto 8),
z_bcd_1dig => Zaux(15 downto 12),
cout_bcd_1dig => CarryOut(15 downto 12)
);
MULT5: MultBcd_1Dig port map (
a_bcd_1dig => A,
b_bcd_1dig => B(19 downto 16),
cin_bcd_1dig => CarryOut(15 downto 12),
z_bcd_1dig => Zaux(19 downto 16),
cout_bcd_1dig => CarryOut(19 downto 16)
);
Z(23 downto 20) <= CarryOut(19 downto 16);
Z(19 downto 0) <= Zaux(19 downto 0);
end Behavioral;
| gpl-3.0 | 92c2c0de334e909f964a90c6396df5e7 | 0.561184 | 2.954074 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/ALU.vhd | 1 | 2,746 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01/25/2016 10:40:54 AM
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (3 downto 0);
SUM : out STD_LOGIC_VECTOR (7 downto 0);
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC);
end alu;
architecture Behavioral of alu is
signal temp_s : STD_LOGIC_VECTOR (8 downto 0);
begin
process (A, B, C_IN, SEL)
begin
case SEL is
when "0000" => temp_s <= ('0' & A) + B; -- add
when "0001" => temp_s <= ('0' & A) + B + C_IN; -- addc
when "0010" => temp_s <= ('0' & A) - B; -- sub
when "0011" => temp_s <= ('0' & A) - B - C_IN; -- subc
when "0100" => temp_s <= ('0' & A) - B; -- cmp
when "0101" => temp_s <= ('0' & A) and ('0' & B); -- and
when "0110" => temp_s <= ('0' & A) or ('0' & B); -- or
when "0111" => temp_s <= ('0' & A) xor ('0' & B); -- exor
when "1000" => temp_s <= ('0' & A) and ('0' & B); -- test
when "1001" => temp_s <= A & C_IN; -- lsl
when "1010" => temp_s <= A(0) & C_IN & A (7 downto 1); -- lsr
when "1011" => temp_s <= A(7 downto 0) & A(7); -- rol
when "1100" => temp_s <= A(0) & A(0) & A(7 downto 1); -- ror
when "1101" => temp_s <= A(0) & A(7) & A(7 downto 1); -- asr
when "1110" => temp_s <= '0' & B; -- mov
when "1111" => temp_s <= "000000000"; -- unused
when others => temp_s <= "000000000";
end case;
end process;
-- account for overflow during subtraction
SUM <= not(temp_s (7 downto 0)) + 1 when ((SEL = "0010" or SEL = "0011") and temp_s(8) = '1')
else temp_s(7 downto 0);
Z_FLAG <= '1' when (temp_s = "000000000" or temp_s = "100000000") else '0';
C_FLAG <= temp_s(8);
end Behavioral;
| mit | 99146c6f55041540c028d983cc121b46 | 0.482156 | 3.312425 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/ControlUnit.vhd | 1 | 19,313 | ----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer:
-- -------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ControlUnit is
Port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OPY_SEL : out STD_LOGIC; -- DOESN'T DO ANYTHING RIGHT NOW!! CHECK ME!!
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC);
end ControlUnit;
architecture Behavioral of ControlUnit is
-- State machine signals
type state_type is (ST_init, ST_fet, ST_exec, ST_int);
signal PS,NS : state_type;
-- Opcode
signal sig_OPCODE_7: std_logic_vector (6 downto 0);
begin
-- Assign next state
sync_p: process (CLK, NS, RST)
begin
if (RST = '1') then
PS <= ST_init;
elsif (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_p;
-- Translate instruction to signals
comb_p: process (OPCODE_HI_5, OPCODE_LO_2, sig_OPCODE_7, C, Z, PS, NS, INT) begin
sig_OPCODE_7 <= OPCODE_HI_5 & OPCODE_LO_2;
case PS is
-- STATE: the init cycle ------------------------------------
when ST_init =>
NS <= ST_fet;
-- Initialize all control outputs to non-active states and reset the PC and SP to all zeros.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '1'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '1';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the fetch cycle -----------------------------------
when ST_fet =>
NS <= ST_exec;
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '1';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the execute cycle ---------------------------------
when ST_exec =>
if (INT = '1') then
NS <= ST_int;
else
NS <= ST_fet;
end if;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
if (sig_OPCODE_7 = "0000100") then -- ADD reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0000";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10100" ) then -- ADD reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0000";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000101") then -- ADDC reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10101" ) then -- ADDC reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000000") then -- AND reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0101";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10000" ) then -- AND reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0101";
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100100") then -- ASR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1101";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0010101") then -- BRCC
if (c = '0') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010100") then -- BRCS
if (c = '1') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010010") then -- BREQ
if (Z = '1') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010000") then -- BRN
PC_LD <= '1';
elsif (sig_OPCODE_7 = "0010011") then -- BRNE
if (Z = '0') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010001") then -- CALL
PC_LD <= '1';
PC_OE <= '1';
SP_LD <= '1';
SP_MUX_SEL <= "10";
SCR_ADDR_SEL <= "11";
SCR_WR <= '1';
elsif (sig_OPCODE_7 = "0110000") then -- CLC
C_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0110101") then -- CLI (INT)
I_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0001000") then -- CMP reg-reg
RF_OE <= '1';
ALU_SEL <= "0100";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11000" ) then -- CMP reg-immed
RF_OE <= '1';
ALU_SEL <= "0100";
REG_IMMED_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000010") then -- EXOR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0111";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10010" ) then -- EXOR reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0111";
REG_IMMED_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11001" ) then -- IN
RF_WR <= '1';
RF_WR_SEL <= "11";
elsif (sig_OPCODE_7 = "0001010") then -- LD reg-reg
SCR_OE <= '1';
SCR_ADDR_SEL <= "00";
RF_WR <= '1';
RF_WR_SEL <= "01";
elsif (OPCODE_HI_5 = "11100" ) then -- LD reg-immed
SCR_OE <= '1';
SCR_ADDR_SEL <= "01";
RF_WR <= '1';
RF_WR_SEL <= "01";
elsif (sig_OPCODE_7 = "0100000") then -- LSL
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100001") then -- LSR
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1010";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0001001") then -- MOV reg-reg
RF_WR <= '1';
RF_OE <= '0';
ALU_SEL <= "1110";
elsif (OPCODE_HI_5 = "11011" ) then -- MOV reg-immed
RF_WR <= '1';
ALU_SEL <= "1110";
REG_IMMED_SEL <= '1';
elsif (sig_OPCODE_7 = "0000001") then -- OR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0110";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10001" ) then -- OR reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0110";
REG_IMMED_SEL <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11010" ) then -- OUT
RF_OE <= '1';
IO_OE <= '1';
elsif (sig_OPCODE_7 = "0100110") then -- POP
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
RF_WR <= '1';
RF_WR_SEL <= "01";
SP_MUX_SEL <= "11";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0100101") then -- PUSH
RF_OE <= '1';
SCR_WR <= '1';
SCR_ADDR_SEL <= "11";
SP_MUX_SEL <= "10";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0110010") then -- RET
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
PC_MUX_SEL <= "01";
PC_LD <= '1';
SP_MUX_SEL <= "11";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0110110") then -- RETID (INT)
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
PC_MUX_SEL <= "01";
PC_LD <= '1';
SP_MUX_SEL <= "11";
SP_LD <= '1';
I_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0110111") then -- RETIE (INT)
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
PC_MUX_SEL <= "01";
PC_LD <= '1';
SP_MUX_SEL <= "11";
SP_LD <= '1';
I_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0100010") then -- ROL
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1011";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100011") then -- ROR
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1100";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0110001") then -- SEC
C_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0110100") then -- SEI (INT)
I_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0001011") then -- ST reg-reg
RF_OE <= '1';
SCR_WR <= '1';
elsif (OPCODE_HI_5 = "11101" ) then -- ST reg-immed
RF_OE <= '1';
SCR_WR <= '1';
SCR_ADDR_SEL <= "01";
elsif (sig_OPCODE_7 = "0000110") then -- SUB reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0010";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10110" ) then -- SUB reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0010";
REG_IMMED_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000111") then -- SUBC reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0011";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10111" ) then -- SUBC reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0011";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000011") then -- TEST reg-reg
RF_OE <= '1';
ALU_SEL <= "1000";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10011" ) then -- TEST reg-immed
REG_IMMED_SEL <= '1';
RF_OE <= '1';
ALU_SEL <= "1000";
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0101000") then -- WSP
RF_OE <= '1';
SP_MUX_SEL <= "00";
SP_LD <= '1';
else
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end if;
when ST_int =>
NS <= ST_fet;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '1'; PC_MUX_SEL <= "10"; PC_RESET <= '0'; PC_OE <= '1'; PC_INC <= '0';
SP_LD <= '1'; SP_MUX_SEL <= "10"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '1'; SCR_OE <= '0'; SCR_ADDR_SEL <= "11";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '1'; IO_OE <= '0';
when others =>
NS <= ST_fet;
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end case;
end process comb_p;
end Behavioral; | mit | 246bc9678e9fd1d660deb6211a7417cd | 0.353544 | 3.51465 | false | false | false | false |
open-power/snap | hardware/hdl/core/job_manager.vhd | 1 | 32,743 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
USE work.snap_core_types.all;
ENTITY job_manager IS
PORT (
--
-- pervasive
ha_pclock : IN std_logic;
afu_reset : IN std_logic;
--
-- MMIO Interface
mmj_c_i : IN MMJ_C_T;
mmj_d_i : IN MMJ_D_T;
jmm_c_o : OUT JMM_C_T;
jmm_d_o : OUT JMM_D_T;
--
-- DMA Interface (via AXI-DMA shim)
sj_c_i : IN SJ_C_T;
js_c_o : OUT JS_C_T;
--
-- AXI MASTER Interface
xj_c_i : IN XJ_C_T;
jx_c_o : OUT JX_C_T
);
END job_manager;
ARCHITECTURE job_manager OF job_manager IS
--
-- CONSTANT
--
-- TYPE
TYPE ASSIGN_ACTION_FSM_T IS (ST_RESET, ST_WAIT_FREE_ACTION, ST_WAIT_CONTEXT, ST_REQUEST_MMIO, ST_WAIT_MMIO_GRANT, ST_RETURN_MMIO_LOCK);
TYPE COMPLETE_ACTION_FSM_T IS (ST_WAIT_COMPLETION, ST_REQUEST_MMIO, ST_WAIT_MMIO_GRANT, ST_PUSH_CTX, ST_RETURN_MMIO_LOCK, ST_INIT_ACTIONS);
TYPE REQUEST_MMIO_INTERFACE_FSM_T IS (ST_WAIT_GRANT, ST_ASSIGN_MMIO_GRANTED, ST_COMPLETE_MMIO_GRANTED, ST_RETURN_GRANT);
TYPE INTERRUPTS_FSM_T IS (ST_IDLE, ST_REQUEST_INT, ST_WAIT_ACK);
--
-- ATTRIBUTE
ATTRIBUTE syn_encoding : string;
ATTRIBUTE syn_encoding OF ASSIGN_ACTION_FSM_T : TYPE IS "safe";
ATTRIBUTE syn_encoding OF COMPLETE_ACTION_FSM_T : TYPE IS "safe";
ATTRIBUTE syn_encoding OF REQUEST_MMIO_INTERFACE_FSM_T : TYPE IS "safe";
ATTRIBUTE syn_encoding OF INTERRUPTS_FSM_T : TYPE IS "safe";
--
-- SIGNAL
SIGNAL grant_mmio_interface_q : integer RANGE 0 TO NUM_OF_ACTION_TYPES-1;
SIGNAL wait_lock_q : std_logic;
SIGNAL lock_mmio_interface_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL mmio_ctx_q : CONTEXT_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL assign_grant_mmio_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL assign_action_id_q : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL assign_context_active_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL assign_status_we_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL complete_grant_mmio_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL complete_next_seqno_q : SEQNO_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL complete_next_jqidx_q : JQIDX_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL complete_seqno_we_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL complete_context_active_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL complete_status_we_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL check_for_idle_q : std_logic_vector(ACTION_BITS-1 DOWNTO 0);
SIGNAL enable_check_for_idle_q : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL job_queue_mode_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_active_q : std_logic_vector(NUM_OF_ACTIONS-1 DOWNTO 0);
SIGNAL ctx_fifo_we : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_re : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_empty : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_full : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_din : CONTEXT_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_dout : CONTEXT_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_wrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_fifo_rrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_we : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_re : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_empty : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_full : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_din : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_dout : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_wrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_fifo_rrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_attach_q : ACTION_MASK_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_we : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_re : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_empty : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_full : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_din : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_dout : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_wrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_completed_fifo_rrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL action_detach_q : ACTION_MASK_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_we : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_re : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_empty : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_full : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_din : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_dout : ACTION_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_wrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_rrb : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL int_fifo_we_q : std_logic;
SIGNAL int_fifo_re_q : std_logic;
SIGNAL int_fifo_empty : std_logic;
SIGNAL int_fifo_full : std_logic;
SIGNAL int_fifo_din_q : std_logic_vector(CONTEXT_BITS + INT_BITS - 2 DOWNTO 0);
SIGNAL int_fifo_dout : std_logic_vector(CONTEXT_BITS + INT_BITS - 2 DOWNTO 0);
SIGNAL int_fifo_wrb : std_logic;
SIGNAL int_fifo_rrb : std_logic;
SIGNAL int_src_id_array_q : INTSRC_ID_ARRAY(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL int_fifo_assign_we_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL int_fifo_complete_we_q : std_logic_vector(NUM_OF_ACTION_TYPES-1 DOWNTO 0);
SIGNAL int_req_q : std_logic;
SIGNAL interrupts_fsm_q : INTERRUPTS_FSM_T;
--
-- COMPONENT
COMPONENT fifo_10x512
PORT (
clk : IN std_logic;
srst : IN std_logic;
din : IN std_logic_vector(CONTEXT_BITS+INT_BITS-2 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(CONTEXT_BITS+INT_BITS-2 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_rst_busy : OUT std_logic;
rd_rst_busy : OUT std_logic
);
END COMPONENT;
--
-- COMPONENT
COMPONENT fifo_8x512
PORT (
clk : IN std_logic;
srst : IN std_logic;
din : IN std_logic_vector(CONTEXT_BITS-1 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(CONTEXT_BITS-1 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_rst_busy : OUT std_logic;
rd_rst_busy : OUT std_logic
);
END COMPONENT;
--
-- COMPONENT
COMPONENT fifo_4x512
PORT (
clk : IN std_logic;
srst : IN std_logic;
din : IN std_logic_vector(ACTION_BITS-1 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(ACTION_BITS-1 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic;
wr_rst_busy : OUT std_logic;
rd_rst_busy : OUT std_logic
);
END COMPONENT;
BEGIN
int_fifo: fifo_10x512
PORT MAP (
clk => ha_pclock,
srst => afu_reset,
din => int_fifo_din_q,
wr_en => int_fifo_we_q,
rd_en => int_fifo_re_q,
dout => int_fifo_dout,
full => int_fifo_full,
empty => int_fifo_empty,
wr_rst_busy => int_fifo_wrb,
rd_rst_busy => int_fifo_rrb
);
action_type_handling: FOR sat_id IN 0 TO NUM_OF_ACTION_TYPES-1 GENERATE
SIGNAL assign_action_fsm_q : ASSIGN_ACTION_FSM_T;
SIGNAL complete_action_fsm_q : COMPLETE_ACTION_FSM_T;
SIGNAL request_mmio_interface_fsm_q : REQUEST_MMIO_INTERFACE_FSM_T;
SIGNAL assign_require_mmio_q : std_logic;
SIGNAL complete_ctx_q : std_logic_vector(CONTEXT_BITS-1 DOWNTO 0);
SIGNAL ctx_completed_fifo_busy_q : std_logic;
SIGNAL complete_require_mmio_q : std_logic;
SIGNAL current_contexts_q : CONTEXT_ID_ARRAY(NUM_OF_ACTIONS-1 DOWNTO 0); -- Keeping the current context for each action
SIGNAL exploration_done_q : std_logic;
SIGNAL init_action_counter_q : std_logic_vector(ACTION_BITS-1 DOWNTO 0);
BEGIN
ctx_fifo: fifo_8x512
PORT MAP (
clk => ha_pclock,
srst => afu_reset,
din => ctx_fifo_din(sat_id),
wr_en => ctx_fifo_we(sat_id),
rd_en => ctx_fifo_re(sat_id),
dout => ctx_fifo_dout(sat_id),
full => ctx_fifo_full(sat_id),
empty => ctx_fifo_empty(sat_id),
wr_rst_busy => ctx_fifo_wrb(sat_id),
rd_rst_busy => ctx_fifo_rrb(sat_id)
);
action_fifo: fifo_4x512
PORT MAP (
clk => ha_pclock,
srst => afu_reset,
din => action_fifo_din(sat_id),
wr_en => action_fifo_we(sat_id),
rd_en => action_fifo_re(sat_id),
dout => action_fifo_dout(sat_id),
full => action_fifo_full(sat_id),
empty => action_fifo_empty(sat_id),
wr_rst_busy => action_fifo_wrb(sat_id),
rd_rst_busy => action_fifo_rrb(sat_id)
);
action_completed_fifo: fifo_4x512
PORT MAP (
clk => ha_pclock,
srst => afu_reset,
din => action_completed_fifo_din(sat_id),
wr_en => action_completed_fifo_we(sat_id),
rd_en => action_completed_fifo_re(sat_id),
dout => action_completed_fifo_dout(sat_id),
full => action_completed_fifo_full(sat_id),
empty => action_completed_fifo_empty(sat_id),
wr_rst_busy => action_completed_fifo_wrb(sat_id),
rd_rst_busy => action_completed_fifo_rrb(sat_id)
);
ctx_completed_fifo: fifo_4x512
PORT MAP (
clk => ha_pclock,
srst => afu_reset,
din => ctx_completed_fifo_din(sat_id),
wr_en => ctx_completed_fifo_we(sat_id),
rd_en => ctx_completed_fifo_re(sat_id),
dout => ctx_completed_fifo_dout(sat_id),
full => ctx_completed_fifo_full(sat_id),
empty => ctx_completed_fifo_empty(sat_id),
wr_rst_busy => ctx_completed_fifo_wrb(sat_id),
rd_rst_busy => ctx_completed_fifo_rrb(sat_id)
);
assign_action_fsm : PROCESS (ha_pclock)
BEGIN -- PROCESS
IF rising_edge(ha_pclock) THEN
-- defaults
ctx_fifo_re(sat_id) <= '0';
action_fifo_re(sat_id) <= '0';
action_attach_q(sat_id) <= (OTHERS => '0');
assign_action_id_q(sat_id) <= assign_action_id_q(sat_id);
assign_context_active_q(sat_id) <= '0';
assign_status_we_q(sat_id) <= '0';
assign_require_mmio_q <= assign_require_mmio_q;
assign_action_fsm_q <= assign_action_fsm_q;
current_contexts_q <= current_contexts_q;
enable_check_for_idle_q(sat_id) <= (OTHERS => '0');
job_queue_mode_q(sat_id) <= job_queue_mode_q(sat_id);
int_fifo_assign_we_q(sat_id) <= '0';
--
-- F S M
--
CASE assign_action_fsm_q IS
WHEN ST_RESET =>
IF NOT (ctx_fifo_wrb(sat_id) OR ctx_fifo_rrb(sat_id) OR action_fifo_wrb(sat_id) OR action_fifo_rrb(sat_id) OR
ctx_completed_fifo_wrb(sat_id) OR ctx_completed_fifo_rrb(sat_id) OR action_completed_fifo_wrb(sat_id) OR action_completed_fifo_rrb(sat_id) OR
int_fifo_wrb OR int_fifo_rrb) = '1' THEN
assign_action_fsm_q <= ST_WAIT_FREE_ACTION;
END IF;
WHEN ST_WAIT_FREE_ACTION =>
IF action_fifo_empty(sat_id) = '0' THEN
action_fifo_re(sat_id) <= '1';
IF ctx_fifo_empty(sat_id) = '1' THEN
assign_action_fsm_q <= ST_WAIT_CONTEXT;
ELSE
ctx_fifo_re(sat_id) <= '1';
assign_action_fsm_q <= ST_REQUEST_MMIO;
END IF;
END IF;
WHEN ST_WAIT_CONTEXT =>
IF ctx_fifo_empty(sat_id) = '0' THEN
ctx_fifo_re(sat_id) <= '1';
assign_action_fsm_q <= ST_REQUEST_MMIO;
END IF;
WHEN ST_REQUEST_MMIO =>
assign_require_mmio_q <= '1';
assign_action_fsm_q <= ST_WAIT_MMIO_GRANT;
WHEN ST_WAIT_MMIO_GRANT =>
current_contexts_q(to_integer(unsigned(assign_action_id_q(sat_id)))) <= ctx_fifo_dout(sat_id);
assign_action_id_q(sat_id) <= action_fifo_dout(sat_id);
IF assign_grant_mmio_q(sat_id) = '1' THEN
assign_context_active_q(sat_id) <= '1';
assign_status_we_q(sat_id) <= '1';
action_attach_q(sat_id)(to_integer(unsigned(action_fifo_dout(sat_id)))) <= '1';
int_fifo_assign_we_q(sat_id) <= mmj_d_i.assign_int_enable;
assign_action_fsm_q <= ST_RETURN_MMIO_LOCK;
END IF;
WHEN ST_RETURN_MMIO_LOCK =>
enable_check_for_idle_q(sat_id)(to_integer(unsigned(assign_action_id_q(sat_id)))) <= mmj_d_i.job_queue_mode OR mmj_d_i.cpl_int_enable;
job_queue_mode_q(sat_id) <= mmj_d_i.job_queue_mode;
IF mmj_c_i.action_ack = '1' THEN
assign_require_mmio_q <= '0';
assign_action_fsm_q <= ST_WAIT_FREE_ACTION;
END IF;
WHEN OTHERS => NULL;
END CASE; -- assign_action_fsm_q
IF afu_reset = '1' THEN
ctx_fifo_re(sat_id) <= '0';
action_fifo_re(sat_id) <= '0';
assign_action_id_q(sat_id) <= (OTHERS => '0');
assign_status_we_q(sat_id) <= '0';
assign_require_mmio_q <= '0';
assign_action_fsm_q <= ST_RESET;
current_contexts_q <= (OTHERS => (OTHERS => '0'));
job_queue_mode_q(sat_id) <= '0';
int_fifo_assign_we_q(sat_id) <= '0';
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS assign_action_fsm;
complete_action_fsm : PROCESS (ha_pclock)
VARIABLE action_completed_v : std_logic;
BEGIN -- PROCESS
IF rising_edge(ha_pclock) THEN
-- defaults
complete_require_mmio_q <= complete_require_mmio_q;
ctx_fifo_we(sat_id) <= mmj_c_i.ctx_fifo_we(sat_id);
ctx_fifo_din(sat_id) <= mmj_d_i.context_id;
action_fifo_we(sat_id) <= '0';
action_fifo_din(sat_id) <= action_completed_fifo_dout(sat_id);
action_completed_fifo_re(sat_id) <= '0';
action_completed_fifo_we(sat_id) <= '0';
action_completed_v := '0';
IF (job_queue_mode_q(sat_id) = '1') AND (unsigned(mmj_d_i.sat(to_integer(unsigned(xj_c_i.action)))) = to_unsigned(sat_id, ACTION_BITS)) THEN
action_completed_fifo_we(sat_id) <= xj_c_i.valid;
action_completed_fifo_din(sat_id) <= xj_c_i.action;
action_completed_v := xj_c_i.valid;
END IF;
action_detach_q(sat_id) <= (OTHERS => '0');
ctx_completed_fifo_re(sat_id) <= '0';
ctx_completed_fifo_we(sat_id) <= '0';
ctx_completed_fifo_busy_q <= ctx_completed_fifo_busy_q;
IF mmj_c_i.ctx_stop(sat_id) = '1' THEN
ctx_completed_fifo_we(sat_id) <= '1';
ctx_completed_fifo_din(sat_id) <= mmj_d_i.action_id;
END IF;
IF (ctx_completed_fifo_busy_q OR ctx_completed_fifo_empty(sat_id)) = '0' THEN
ctx_completed_fifo_re(sat_id) <= '1';
ctx_completed_fifo_busy_q <= '1';
END IF;
IF (ctx_completed_fifo_busy_q AND NOT (ctx_completed_fifo_re(sat_id) OR action_completed_v)) = '1' THEN
-- Wait until action reset is completed
IF mmj_c_i.action_reset_vector(to_integer(unsigned(ctx_completed_fifo_dout(sat_id)))) = '0' THEN
action_completed_fifo_we(sat_id) <= '1';
action_completed_fifo_din(sat_id) <= ctx_completed_fifo_dout(sat_id);
ctx_completed_fifo_busy_q <= '0';
END IF;
END IF;
complete_ctx_q <= complete_ctx_q;
complete_next_seqno_q(sat_id) <= complete_next_seqno_q(sat_id);
complete_next_jqidx_q(sat_id) <= complete_next_jqidx_q(sat_id);
complete_seqno_we_q(sat_id) <= '0';
complete_context_active_q(sat_id) <= '0';
complete_status_we_q(sat_id) <= '0';
complete_action_fsm_q <= complete_action_fsm_q;
int_fifo_complete_we_q(sat_id) <= '0';
exploration_done_q <= exploration_done_q OR mmj_c_i.exploration_done;
init_action_counter_q <= init_action_counter_q;
--
-- F S M
--
CASE complete_action_fsm_q IS
WHEN ST_WAIT_COMPLETION =>
IF action_completed_fifo_empty(sat_id) = '0' THEN
action_completed_fifo_re(sat_id) <= '1';
complete_action_fsm_q <= ST_REQUEST_MMIO;
ELSIF (exploration_done_q AND action_fifo_empty(sat_id)) = '1' THEN
exploration_done_q <= '0';
init_action_counter_q <= (OTHERS => '0');
complete_action_fsm_q <= ST_INIT_ACTIONS;
END IF;
WHEN ST_REQUEST_MMIO =>
complete_require_mmio_q <= '1';
complete_action_fsm_q <= ST_WAIT_MMIO_GRANT;
WHEN ST_WAIT_MMIO_GRANT =>
complete_ctx_q <= current_contexts_q(to_integer(unsigned(action_completed_fifo_dout(sat_id))));
IF complete_grant_mmio_q(sat_id) = '1' THEN
action_fifo_we(sat_id) <= '1';
complete_next_seqno_q(sat_id) <= mmj_d_i.current_seqno + 1;
complete_next_jqidx_q(sat_id) <= mmj_d_i.current_jqidx + 1;
complete_seqno_we_q(sat_id) <= '1';
complete_status_we_q(sat_id) <= '1';
int_fifo_complete_we_q(sat_id) <= mmj_d_i.cpl_int_enable;
action_detach_q(sat_id)(to_integer(unsigned(action_completed_fifo_dout(sat_id)))) <= '1';
IF mmj_c_i.last_seqno = '0' THEN
complete_context_active_q(sat_id) <= '1';
complete_action_fsm_q <= ST_PUSH_CTX;
ELSE
complete_action_fsm_q <= ST_RETURN_MMIO_LOCK;
END IF;
END IF;
WHEN ST_PUSH_CTX =>
complete_require_mmio_q <= '0';
IF mmj_c_i.ctx_fifo_we(sat_id) = '0' THEN
ctx_fifo_we(sat_id) <= '1';
ctx_fifo_din(sat_id) <= complete_ctx_q;
complete_action_fsm_q <= ST_WAIT_COMPLETION;
END IF;
WHEN ST_RETURN_MMIO_LOCK =>
complete_require_mmio_q <= '0';
complete_action_fsm_q <= ST_WAIT_COMPLETION;
WHEN ST_INIT_ACTIONS =>
IF unsigned(mmj_d_i.sat(to_integer(unsigned(init_action_counter_q)))) = to_unsigned(sat_id, ACTION_BITS) THEN
action_fifo_we(sat_id) <= '1';
action_fifo_din(sat_id) <= init_action_counter_q;
END IF;
IF to_integer(unsigned(init_action_counter_q)) = NUM_OF_ACTIONS-1 THEN
complete_action_fsm_q <= ST_WAIT_COMPLETION;
ELSE
init_action_counter_q <= init_action_counter_q + 1;
END IF;
WHEN OTHERS => NULL;
END CASE; -- complete_action_fsm_q
IF afu_reset = '1' THEN
complete_require_mmio_q <= '0';
ctx_fifo_we(sat_id) <= '0';
action_fifo_we(sat_id) <= '0';
action_completed_fifo_re(sat_id) <= '0';
action_completed_fifo_we(sat_id) <= '0';
ctx_completed_fifo_re(sat_id) <= '0';
ctx_completed_fifo_we(sat_id) <= '0';
ctx_completed_fifo_busy_q <= '0';
complete_ctx_q <= (OTHERS => '0');
complete_next_seqno_q(sat_id) <= (OTHERS => '0');
complete_next_jqidx_q(sat_id) <= (OTHERS => '0');
complete_seqno_we_q(sat_id) <= '0';
complete_status_we_q(sat_id) <= '0';
int_fifo_complete_we_q(sat_id) <= '0';
exploration_done_q <= '0';
init_action_counter_q <= (OTHERS => '0');
complete_action_fsm_q <= ST_WAIT_COMPLETION;
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS complete_action_fsm;
request_mmio_interface_fsm : PROCESS (ha_pclock)
BEGIN -- PROCESS
IF rising_edge(ha_pclock) THEN
-- defaults
lock_mmio_interface_q(sat_id) <= lock_mmio_interface_q(sat_id);
mmio_ctx_q(sat_id) <= mmio_ctx_q(sat_id);
int_src_id_array_q(sat_id) <= int_src_id_array_q(sat_id);
assign_grant_mmio_q(sat_id) <= assign_grant_mmio_q(sat_id);
complete_grant_mmio_q(sat_id) <= complete_grant_mmio_q(sat_id);
request_mmio_interface_fsm_q <= request_mmio_interface_fsm_q;
--
-- F S M
--
CASE request_mmio_interface_fsm_q IS
WHEN ST_WAIT_GRANT =>
IF grant_mmio_interface_q = sat_id THEN
IF assign_require_mmio_q = '1' THEN
lock_mmio_interface_q(sat_id) <= '1';
mmio_ctx_q(sat_id) <= ctx_fifo_dout(sat_id);
int_src_id_array_q(sat_id) <= CTX_ASSIGN_INT_SRC_ID;
assign_grant_mmio_q(sat_id) <= '1';
request_mmio_interface_fsm_q <= ST_ASSIGN_MMIO_GRANTED;
ELSIF complete_require_mmio_q = '1' THEN
lock_mmio_interface_q(sat_id) <= '1';
mmio_ctx_q(sat_id) <= current_contexts_q(to_integer(unsigned(action_completed_fifo_dout(sat_id))));
int_src_id_array_q(sat_id) <= CTX_COMPLETE_INT_SRC_ID;
complete_grant_mmio_q(sat_id) <= '1';
request_mmio_interface_fsm_q <= ST_COMPLETE_MMIO_GRANTED;
ELSE
request_mmio_interface_fsm_q <= ST_RETURN_GRANT;
END IF;
END IF;
WHEN ST_ASSIGN_MMIO_GRANTED =>
IF assign_require_mmio_q = '0' THEN
assign_grant_mmio_q(sat_id) <= '0';
IF complete_require_mmio_q = '1' THEN
lock_mmio_interface_q(sat_id) <= '1';
mmio_ctx_q(sat_id) <= current_contexts_q(to_integer(unsigned(action_completed_fifo_dout(sat_id))));
int_src_id_array_q(sat_id) <= CTX_COMPLETE_INT_SRC_ID;
complete_grant_mmio_q(sat_id) <= '1';
request_mmio_interface_fsm_q <= ST_COMPLETE_MMIO_GRANTED;
ELSE
lock_mmio_interface_q(sat_id) <= '0';
request_mmio_interface_fsm_q <= ST_RETURN_GRANT;
END IF;
END IF;
WHEN ST_COMPLETE_MMIO_GRANTED =>
IF complete_require_mmio_q = '0' THEN
complete_grant_mmio_q(sat_id) <= '0';
lock_mmio_interface_q(sat_id) <= '0';
request_mmio_interface_fsm_q <= ST_RETURN_GRANT;
END IF;
WHEN ST_RETURN_GRANT =>
request_mmio_interface_fsm_q <= ST_WAIT_GRANT;
WHEN OTHERS => NULL;
END CASE; -- request_mmio_interface_fsm_q
IF afu_reset = '1' THEN
lock_mmio_interface_q(sat_id) <= '0';
mmio_ctx_q(sat_id) <= (OTHERS => '0');
int_src_id_array_q(sat_id) <= (OTHERS => '0');
assign_grant_mmio_q(sat_id) <= '0';
complete_grant_mmio_q(sat_id) <= '0';
request_mmio_interface_fsm_q <= ST_WAIT_GRANT;
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS request_mmio_interface_fsm;
END GENERATE action_type_handling;
grant_mmio_access: PROCESS (ha_pclock)
VARIABLE sat_v : integer RANGE 0 TO NUM_OF_ACTION_TYPES-1;
BEGIN -- PROCESS grant_mmio_access
IF rising_edge(ha_pclock) THEN
sat_v := grant_mmio_interface_q;
wait_lock_q <= '0';
IF (lock_mmio_interface_q(sat_v) OR wait_lock_q) = '0' THEN
wait_lock_q <= '1';
IF sat_v = mmj_c_i.max_sat THEN
sat_v := 0;
ELSE
sat_v := sat_v + 1;
END IF;
END IF;
grant_mmio_interface_q <= sat_v;
IF afu_reset = '1' THEN
grant_mmio_interface_q <= 0;
wait_lock_q <= '1';
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS grant_mmio_access;
action_active: PROCESS (ha_pclock)
VARIABLE action_active_v : std_logic_vector(NUM_OF_ACTIONS-1 DOWNTO 0);
BEGIN -- PROCESS action_active
IF rising_edge(ha_pclock) THEN
action_active_v := action_active_q;
FOR sat_id IN 0 TO NUM_OF_ACTION_TYPES-1 LOOP
action_active_v := (action_active_v OR action_attach_q(sat_id)) AND NOT action_detach_q(sat_id);
END LOOP; -- sat_id
action_active_q <= action_active_v;
IF afu_reset = '1' THEN
action_active_q <= (OTHERS => '0');
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS action_active;
set_check_for_idle: PROCESS (ha_pclock)
VARIABLE check_for_idle_v : std_logic_vector(ACTION_BITS-1 DOWNTO 0);
BEGIN -- PROCESS check_for_idle
IF rising_edge(ha_pclock) THEN
check_for_idle_v := check_for_idle_q;
FOR sat_id IN 0 TO NUM_OF_ACTION_TYPES-1 LOOP
check_for_idle_v := check_for_idle_v OR enable_check_for_idle_q(sat_id);
END LOOP; -- sat_id
check_for_idle_v(to_integer(unsigned(xj_c_i.action))) := check_for_idle_v(to_integer(unsigned(xj_c_i.action))) AND NOT xj_c_i.valid;
check_for_idle_q <= check_for_idle_v;
IF afu_reset = '1' THEN
check_for_idle_q <= (OTHERS => '0');
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS set_check_for_idle;
interrupts: PROCESS (ha_pclock)
BEGIN -- PROCESS int_fifo
IF rising_edge(ha_pclock) THEN
-- defaults
int_fifo_we_q <= int_fifo_assign_we_q(grant_mmio_interface_q) OR int_fifo_complete_we_q(grant_mmio_interface_q);
int_fifo_din_q <= mmio_ctx_q(grant_mmio_interface_q) & int_src_id_array_q(grant_mmio_interface_q);
int_fifo_re_q <= '0';
int_req_q <= '0';
interrupts_fsm_q <= interrupts_fsm_q;
--
-- F S M
--
CASE interrupts_fsm_q IS
WHEN ST_IDLE =>
IF int_fifo_empty = '0' THEN
int_fifo_re_q <= '1';
interrupts_fsm_q <= ST_REQUEST_INT;
END IF;
WHEN ST_REQUEST_INT =>
int_req_q <= '1';
interrupts_fsm_q <= ST_WAIT_ACK;
WHEN ST_WAIT_ACK =>
IF sj_c_i.int_ack = '1' THEN
interrupts_fsm_q <= ST_IDLE;
END IF;
WHEN OTHERS => NULL;
END CASE;
IF afu_reset = '1' THEN
int_fifo_we_q <= '0';
int_fifo_re_q <= '0';
int_req_q <= '0';
interrupts_fsm_q <= ST_IDLE;
END IF; -- afu_reset
END IF; -- rising_edge(ha_pclock)
END PROCESS interrupts;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Interfaces
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- to MMIO
jmm_c_o.seqno_we <= complete_seqno_we_q(grant_mmio_interface_q);
jmm_c_o.status_we <= assign_status_we_q(grant_mmio_interface_q) OR complete_status_we_q(grant_mmio_interface_q);
jmm_c_o.assign_action <= assign_status_we_q(grant_mmio_interface_q);
jmm_d_o.seqno <= complete_next_seqno_q(grant_mmio_interface_q);
jmm_d_o.jqidx <= complete_next_jqidx_q(grant_mmio_interface_q);
jmm_d_o.action_id <= assign_action_id_q(grant_mmio_interface_q) WHEN (assign_grant_mmio_q(grant_mmio_interface_q) = '1') ELSE action_completed_fifo_dout(grant_mmio_interface_q);
jmm_d_o.action_active <= action_active_q;
jmm_d_o.attached_to_action <= assign_status_we_q(grant_mmio_interface_q);
jmm_d_o.context_id <= mmio_ctx_q(grant_mmio_interface_q);
jmm_d_o.context_active <= assign_context_active_q(grant_mmio_interface_q) WHEN (assign_grant_mmio_q(grant_mmio_interface_q) = '1') ELSE complete_context_active_q(grant_mmio_interface_q);
-- to AXI MASTER
jx_c_o.check_for_idle <= check_for_idle_q;
-- to AXI-DMA shim
js_c_o.int_req <= int_req_q;
js_c_o.int_src <= int_fifo_dout(INT_BITS-2 DOWNTO 0);
js_c_o.int_ctx <= int_fifo_dout(CONTEXT_BITS + INT_BITS - 2 DOWNTO INT_BITS - 1);
END ARCHITECTURE;
| apache-2.0 | 2b2ca85c3ba011539b38dc5e1a67edda | 0.52741 | 3.358601 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_1/synth/RAT_xlslice_0_1.vhd | 1 | 3,804 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_xlslice_0_1 IS
PORT (
Din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_xlslice_0_1;
ARCHITECTURE RAT_xlslice_0_1_arch OF RAT_xlslice_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_xlslice_0_1_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_xlslice_0_1_arch : ARCHITECTURE IS "RAT_xlslice_0_1,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_xlslice_0_1_arch: ARCHITECTURE IS "RAT_xlslice_0_1,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=10,DIN_FROM=7,DIN_TO=0}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 10,
DIN_FROM => 7,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_xlslice_0_1_arch;
| mit | 6c353909f39729422801af9896ea40a3 | 0.729758 | 3.909558 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/Testbenches/prog_rom.vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "44098BA154403401806B030A0310430962AA610F6B016A0074005E817E010000";
attribute INIT_01 of ram_1024_x_18 : label is "06004A5846098BA15440340480DB05A5051245098BA15440340280A304AF0411";
attribute INIT_02 of ram_1024_x_18 : label is "8C01544034E08BA154403410815B078707014A5847098BA154403408811B061F";
attribute INIT_03 of ram_1024_x_18 : label is "6AAB8BA15F403F0281EB0AFF2AAA6A558BA15F403F0181B30A110ADB6A357F00";
attribute INIT_04 of ram_1024_x_18 : label is "0A7F0A036AFE8BA15F403F08825B0AFE0A026A7F8BA15F403F0482230AFF4A54";
attribute INIT_05 of ram_1024_x_18 : label is "047764778BA1810161008C015F403FE082CB0ADF2A006ABE8BA15F403F108293";
attribute INIT_06 of ram_1024_x_18 : label is "8380C10483808BA1810441408350C102835304668BA1810241408318C101831A";
attribute INIT_07 of ram_1024_x_18 : label is "8400C110A401841164778BA18110414083C0C108A3C0845564FF8BA181084140";
attribute INIT_08 of ram_1024_x_18 : label is "8480C140A4808001C4118BA1814041408440C120A441800084FF8BA181204140";
attribute INIT_09 of ram_1024_x_18 : label is "6011410061D18BA15F403F0184DB015081FF200160505F407F008C0141408180";
attribute INIT_0A of ram_1024_x_18 : label is "5F403F04857B01222102A0FF6022410061FF8BA15F403F02852B011181D02001";
attribute INIT_0B of ram_1024_x_18 : label is "603320016022200160118BA15F403F0885CB0142210220016042410061008BA1";
attribute INIT_0C of ram_1024_x_18 : label is "0122210286AB0133210286AB0144210286AB0155210220016055200160442001";
attribute INIT_0D of ram_1024_x_18 : label is "870B01888B118BA15F403F2086DB01778B018BA15F403F1086AB0111210286AB";
attribute INIT_0E of ram_1024_x_18 : label is "8BA15440340187730A016A0174008C015F403F80873B00598B398BA15F403F40";
attribute INIT_0F of ram_1024_x_18 : label is "4DAA7502AA028BA15440340487DB0C014C5A4A5B8BA15440340287A30B014B51";
attribute INIT_10 of ram_1024_x_18 : label is "0C018F04AA048BA154403410885B0E018E034AB376038BA154403408881B0D01";
attribute INIT_11 of ram_1024_x_18 : label is "800124028BA14140012188E30203820262012401640061008C01544034E08893";
attribute INIT_12 of ram_1024_x_18 : label is "E203800124088BA141400121895B0205C20224048BA14140012189230207A203";
attribute INIT_13 of ram_1024_x_18 : label is "80018BA14F402F0189EB4C506C092A586B046A058C01414021F0012189A30201";
attribute INIT_14 of ram_1024_x_18 : label is "2F048A834C506C012A5A6B046A058BA14F402F028A3B4C506C0A2A596B046A05";
attribute INIT_15 of ram_1024_x_18 : label is "8AF84F402F802F402F202F102F088AF34C506C022A5B6B026A0580018BA14F40";
attribute INIT_16 of ram_1024_x_18 : label is "402141014409200880028B61630A610160018002618880028B29613080026177";
attribute INIT_17 of ram_1024_x_18 : label is "80028BAB3D008BBB3C008BCBDB017B5EDC017CFFDD017DFF80028B618B9AC301";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000080028BA15E819E015F407F008BA18BA1";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "22CB22CB20B232C8F2CE3738DCE3738ECE3B38EF38E340E340E3038C0E30FFFC";
attribute INITP_01 of ram_1024_x_18 : label is "3CE3038C38FCE30E30E30E34D34D35DDDDCE35DCE37DCE3DDCE3DFCE218B218B";
attribute INITP_02 of ram_1024_x_18 : label is "488BBB42004FDD373AA833D3833CE0CF4E0CF38398C3A30E630EEF38FCE3CCE3";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000004EF0";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"44098BA154403401806B030A0310430962AA610F6B016A0074005E817E010000",
INIT_01 => X"06004A5846098BA15440340480DB05A5051245098BA15440340280A304AF0411",
INIT_02 => X"8C01544034E08BA154403410815B078707014A5847098BA154403408811B061F",
INIT_03 => X"6AAB8BA15F403F0281EB0AFF2AAA6A558BA15F403F0181B30A110ADB6A357F00",
INIT_04 => X"0A7F0A036AFE8BA15F403F08825B0AFE0A026A7F8BA15F403F0482230AFF4A54",
INIT_05 => X"047764778BA1810161008C015F403FE082CB0ADF2A006ABE8BA15F403F108293",
INIT_06 => X"8380C10483808BA1810441408350C102835304668BA1810241408318C101831A",
INIT_07 => X"8400C110A401841164778BA18110414083C0C108A3C0845564FF8BA181084140",
INIT_08 => X"8480C140A4808001C4118BA1814041408440C120A441800084FF8BA181204140",
INIT_09 => X"6011410061D18BA15F403F0184DB015081FF200160505F407F008C0141408180",
INIT_0A => X"5F403F04857B01222102A0FF6022410061FF8BA15F403F02852B011181D02001",
INIT_0B => X"603320016022200160118BA15F403F0885CB0142210220016042410061008BA1",
INIT_0C => X"0122210286AB0133210286AB0144210286AB0155210220016055200160442001",
INIT_0D => X"870B01888B118BA15F403F2086DB01778B018BA15F403F1086AB0111210286AB",
INIT_0E => X"8BA15440340187730A016A0174008C015F403F80873B00598B398BA15F403F40",
INIT_0F => X"4DAA7502AA028BA15440340487DB0C014C5A4A5B8BA15440340287A30B014B51",
INIT_10 => X"0C018F04AA048BA154403410885B0E018E034AB376038BA154403408881B0D01",
INIT_11 => X"800124028BA14140012188E30203820262012401640061008C01544034E08893",
INIT_12 => X"E203800124088BA141400121895B0205C20224048BA14140012189230207A203",
INIT_13 => X"80018BA14F402F0189EB4C506C092A586B046A058C01414021F0012189A30201",
INIT_14 => X"2F048A834C506C012A5A6B046A058BA14F402F028A3B4C506C0A2A596B046A05",
INIT_15 => X"8AF84F402F802F402F202F102F088AF34C506C022A5B6B026A0580018BA14F40",
INIT_16 => X"402141014409200880028B61630A610160018002618880028B29613080026177",
INIT_17 => X"80028BAB3D008BBB3C008BCBDB017B5EDC017CFFDD017DFF80028B618B9AC301",
INIT_18 => X"0000000000000000000000000000000080028BA15E819E015F407F008BA18BA1",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"22CB22CB20B232C8F2CE3738DCE3738ECE3B38EF38E340E340E3038C0E30FFFC",
INITP_01 => X"3CE3038C38FCE30E30E30E34D34D35DDDDCE35DCE37DCE3DDCE3DFCE218B218B",
INITP_02 => X"488BBB42004FDD373AA833D3833CE0CF4E0CF38398C3A30E630EEF38FCE3CCE3",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000004EF0",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | 2dc5f9a7efb3183fb6ab83024487fd85 | 0.735725 | 4.419075 | false | false | false | false |
stefanct/aua | hw/alu/src/Mux4to1.vhd | 1 | 658 | library ieee;
use ieee.std_logic_1164.all;
entity Mux4to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(1 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end Mux4to1;
architecture rtl of Mux4to1 is
begin
process(sel, i01, i02, i03, i04)
begin
case sel is
when "00" => mux_out <= i01;
when "01" => mux_out <= i02;
when "10" => mux_out <= i03;
when "11" => mux_out <= i04;
when others => mux_out <= x"0000";
end case;
end process;
end rtl; | gpl-3.0 | 078b6e9b0b27a24f6adc611433644ff3 | 0.613982 | 2.550388 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_0_1/sim/RAT_FlagReg_0_1.vhd | 2 | 3,343 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_0_1 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_0_1;
ARCHITECTURE RAT_FlagReg_0_1_arch OF RAT_FlagReg_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_0_1_arch;
| mit | 4ecb5b437c1b5bebc755188e6ac8ec00 | 0.717918 | 4.022864 | false | false | false | false |
stefanct/aua | hw/reg/src/ram.vhd | 1 | 9,565 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 5,
widthad_b => 5,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL rdaddress[4..0]
-- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
-- Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 7885dffbf9652b73c60eecfe0e2afc38 | 0.666702 | 3.402704 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/DivisorDeClock.vhd | 1 | 1,221 | ----------------------------------------------------------------------------------
-- Create Date: 14:56:26 05/01/2017
-- Module Name: DivisorDeClock - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DivisorDeClock is
Port ( clockIn : in STD_LOGIC; -- clock gerado pela FPGA na frequência de 50 MHz
counter : buffer integer; -- contador para dividir o clock
clockOut : out STD_LOGIC); -- clock de 3 em 3 segundos
end DivisorDeClock;
architecture Behavioral of DivisorDeClock is
begin
-- A cada 3 segundos tem-se uma contagem de 100 milhões no contador.
-- Então a cada 3 segundos dá-se um clock.
clockOut <= '1' when counter = 10000000 else '0';
ClockCounter: process(clockIn, counter) -- Processo para que os 'if' possam ocorrer
begin
if(clockIn'event and clockIn = '1') then
counter <= counter + 1;
end if;
-- Se o contador alcançar 100 milhões + l, volta para a contagem 1
-- e passa a contar novamente até o momento de gerar um novo pulso de clock.
if(counter = 10000001) then
counter <= 0;
end if;
end process ClockCounter;
end Behavioral;
| gpl-3.0 | b4bee6108f8464ad7117195116b7b91e | 0.595414 | 4.016447 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/BANCADA_TESTE.vhd | 1 | 3,776 | ----------------------------------------------------------------------------------
-- Create Date: 16:31:16 04/25/2017
-- Module Name: BANCADA_TESTE - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BANCADA_TESTE is
Port ( Controle : in STD_LOGIC_VECTOR (2 downto 0);
clockFPGA : in STD_LOGIC;
LedSaida : out STD_LOGIC_VECTOR (7 downto 0));
end BANCADA_TESTE;
architecture Behavioral of BANCADA_TESTE is
signal EntradaA, EntradaB: STD_LOGIC_VECTOR(3 downto 0); --sinal auxiliar
signal VetorAB, Saida: STD_LOGIC_VECTOR(7 downto 0); --sinal auxiliar
signal contadorClock: integer; --sinal auxiliar
signal clockAux: STD_LOGIC ; --sinal auxiliar
-- 0 component Divisor de Clocks é chamado para ditar o tempo em que as entradas
-- são geradas e tamhém o tempo que cada um dos operandos e que o resultado são impressos nos LEDs adequados.
component DivisorDeClock is
port(clockIn: in std_LOGIC ;
counter : buffer integer range 0 to 100000001;
clockOut : out std_LOGIC );
end component;
-- O componente Gerador de entrada é chamado para gerar as entradas conforme o sinal de clock que é recebido
-- são gerados vetores de 8 bits de 0000 0000 até 1111 1111, onde será assumido que os 4 bits mais significativos
-- representam o vetor A e os 4 bits menos significativos representam o vetor B. Dessa forma, podemos mapear todas as
-- possíveis entradas de 4 bits.
component GeradorDeEntradas is
Port ( Saida : out STD_LOGIC_VECTOR (7 downto 0);
clock : in STD_LOGIC );
end component;
component ULA_MODULO is
port ( A: in STD_LOGIC_VECTOR (3 downto 0); -- EntradaA
B: in STD_LOGIC_VECTOR (3 downto 0); -- EntradaB
Controle : in STD_LOGIC_VECTOR (2 downto 0); -- Vetor de Controle(S2S1S0)
Z: out STD_LOGIC_VECTOR(7 downto 0) -- Saída
);
end component;
begin
divisorClock: DivisorDeClock port map(clockIn => clockFPGA, --Chamada dos componentes
counter => contadorClock,
clockOut => clockAux);
escolherEntradas: GeradorDeEntradas port map(VetorAB, clockAux); --Chamada dos componentes
EntradaA <= VetorAB(3 downto 0);
EntradaB <= VetorAB(7 downto 4);
saidas: ULA_MODULO port map(A => EntradaA, --Chamada dos componentes
B => EntradaB,
Controle => Controle,
Z => Saida);
imprimir: process(EntradaA, EntradaB, Saida, clockAux) -- lnício do processo de impressão nos LEDs
variable processCounter: integer := 2; --variável auxiliar
variable contadorA: integer; --variável auxiliar
--Primeiro é impresso nos LEDs o operando A, depois o opcrand B e, por ultimo, o resultado.
begin
if (clockAux'event and clockAux = '1') then
if processCounter = 1 then
LedSaida(0) <= EntradaA(0);
LedSaida(1) <= EntradaA(1);
LedSaida(2) <= EntradaA(2);
LedSaida(3) <= EntradaA(3);
LedSaida(4) <= '0';
LedSaida(5) <= '0';
LedSaida(6) <= '0';
LedSaida(7) <= '1';
processCounter := 2;
elsif (processCounter = 2) then
LedSaida(0) <= EntradaB(0);
LedSaida(1) <= EntradaB(1);
LedSaida(2) <= EntradaB(2);
LedSaida(3) <= EntradaB(3);
LedSaida(4) <= '0';
LedSaida(5) <= '0';
LedSaida(6) <= '1';
LedSaida(7) <= '0';
processCounter := 3;
elsif processCounter= 3 then
LedSaida(0) <= Saida(0);
LedSaida(1) <= Saida(1);
LedSaida(2) <= Saida(2);
LedSaida(3) <= Saida(3);
LedSaida(4) <= '0';
LedSaida(5) <= '1';
LedSaida(6) <= '1';
LedSaida(7 )<= '1';
end if;
end if;
end process imprimir;
end Behavioral; | gpl-3.0 | 561ded978248240029f98083a1cf0c94 | 0.612818 | 3.509294 | false | false | false | false |
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| mit | 513dde0f3fc30134b3dddb8b63022884 | 0.920693 | 1.942841 | false | false | false | false |
MiddleMan5/233 | Experiments/IP_Repo/Program Counter/src/Counter10bit.vhd | 3 | 1,391 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 09/19/2017 12:16:57 AM
-- Design Name:
-- Module Name: Counter10bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter10bit is
Port ( Din : in STD_LOGIC_VECTOR (0 to 9);
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (0 to 9) );
end Counter10bit;
architecture Behavioral of Counter10bit is
signal s_COUNT : STD_LOGIC_VECTOR (0 to 9);
begin
process (CLK, RESET) begin
if (RESET = '1') then
s_COUNT <= ( others => '0' );
elsif (rising_edge(CLK)) then
if (LOAD = '1') then
s_COUNT <= Din;
else
if (INC = '1') then
s_COUNT <= s_COUNT + 1;
end if;
end if;
end if;
end process;
COUNT <= s_COUNT;
end Behavioral;
| mit | 54a00afe641ce50f94b68998c4746458 | 0.469446 | 3.962963 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_Atlys.vhdl | 1 | 10,333 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_Atlys is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
-- DCM - clock wizard report
--
-- Output Output Phase Duty Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)
-------------------------------------------------------------------------------
-- CLK_OUT0 100.000 0.000 50.0 200.000 150.000
-- CLK_OUT1 200.000 0.000 50.0 300.000 150.000
-- CLK_OUT2 125.000 0.000 50.0 360.000 150.000
-- CLK_OUT3 10.000 0.000 50.0 300.000 150.000
--
architecture rtl of clknet_ClockNetwork_Atlys is
attribute KEEP : BOOLEAN;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 24 (100 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal DCM_Reset : STD_LOGIC;
signal DCM_Reset_clr : STD_LOGIC;
signal DCM_ResetState : STD_LOGIC := '0';
signal DCM_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 DOWNTO 0);
signal DCM_Locked_async : STD_LOGIC;
signal DCM_Locked : STD_LOGIC;
signal DCM_Locked_d : STD_LOGIC := '0';
signal DCM_Locked_re : STD_LOGIC;
signal DCM_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFG : STD_LOGIC;
signal DCM_Clock_10MHz : STD_LOGIC;
signal DCM_Clock_100MHz : STD_LOGIC;
signal DCM_Clock_125MHz : STD_LOGIC;
signal DCM_Clock_200MHz : STD_LOGIC;
signal DCM_Clock_10MHz_BUFG : STD_LOGIC;
signal DCM_Clock_100MHz_BUFG : STD_LOGIC;
signal DCM_Clock_125MHz_BUFG : STD_LOGIC;
signal DCM_Clock_200MHz_BUFG : STD_LOGIC;
attribute KEEP of DCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_200MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) DCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => DCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => DCM_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
DCM_Reset_clr <= ClkNet_Reset nor DCM_Locked;
-- detect rising edge on CMB locked signals
DCM_Locked_d <= DCM_Locked when rising_edge(Control_Clock);
DCM_Locked_re <= not DCM_Locked_d and DCM_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
DCM_ResetState <= ffrs(q => DCM_ResetState, rst => DCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
DCM_LockedState <= ffrs(q => DCM_LockedState, rst => DCM_Reset, set => DCM_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
DCM_Reset_delayed <= sr_left(DCM_Reset_delayed, DCM_ResetState) when rising_edge(Control_Clock);
DCM_Reset <= DCM_Reset_delayed(DCM_Reset_delayed'high);
Locked <= DCM_LockedState and '1'; --PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFG
port map (
I => ClockIn_100MHz,
O => Control_Clock_BUFG
);
Control_Clock <= Control_Clock_BUFG;
-- 10 MHz BUFG
BUFG_DCM_Clock_10MHz : BUFG
port map (
I => DCM_Clock_10MHz,
O => DCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_DCM_Clock_100MHz : BUFG
port map (
I => DCM_Clock_100MHz,
O => DCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_DCM_Clock_125MHz : BUFG
port map (
I => DCM_Clock_125MHz,
O => DCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_DCM_Clock_200MHz : BUFG
port map (
I => DCM_Clock_200MHz,
O => DCM_Clock_200MHz_BUFG
);
-- ==================================================================
-- Mixed-Mode Clock Manager (DCM)
-- ==================================================================
System_DCM : DCM_SP
generic map (
STARTUP_WAIT => false,
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS"
PHASE_SHIFT => 0,
CLKIN_PERIOD => to_real(to_time(CLOCK_IN_FREQ), 1.0 ns),
CLKIN_DIVIDE_BY_2 => FALSE,
CLK_FEEDBACK => "1X",
CLKOUT_PHASE_SHIFT => "NONE",
CLKDV_DIVIDE => 10.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5
)
port map (
RST => DCM_Reset,
CLKIN => ClockIn_100MHz,
CLKFB => DCM_Clock_100MHz_BUFG,
CLK0 => DCM_Clock_100MHz,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => DCM_Clock_200MHz,
CLK2X180 => open,
CLKFX => DCM_Clock_125MHz,
CLKFX180 => open,
CLKDV => DCM_Clock_10MHz,
-- DCM status
LOCKED => DCM_Locked_async,
STATUS => open,
-- Dynamic Phase Shift Port
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
DSSEN => '0'
);
Control_Clock_100MHz <= Control_Clock_BUFG;
Clock_200MHz <= DCM_Clock_200MHz_BUFG;
Clock_125MHz <= DCM_Clock_125MHz_BUFG;
Clock_100MHz <= DCM_Clock_100MHz_BUFG;
Clock_10MHz <= DCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to output clock domains
syncLocked200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | cbd4fd160640073d4d5a06540c985c64 | 0.534017 | 3.625614 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_util_vector_logic_0_0/sim/RAT_util_vector_logic_0_0.vhd | 2 | 3,409 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY RAT_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END RAT_util_vector_logic_0_0;
ARCHITECTURE RAT_util_vector_logic_0_0_arch OF RAT_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "and",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END RAT_util_vector_logic_0_0_arch;
| mit | ce7640535deafb97113d8a887927b551 | 0.724259 | 3.918391 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment5-Ram_Reg/RTL/RegisterFile.vhd | 1 | 1,639 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 09/29/2017 12:31:58 AM
-- Design Name: RegisterFile
-- Module Name: RegisterFile - Behavioral
-- Project Name: RAT CPU
-- Target Devices: xc7a50tcsg324-1
-- Tool Versions:
-- Description: This is the register component for our RAT CPU. The function of the register is to:
-- - Provide register space for the RAT instructions
-- The RAM is 32x8 memory module with asyc read and synchronous write.
--
-- Dependencies: N/A
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RegisterFile is
Port ( D_IN : in STD_LOGIC_VECTOR (7 downto 0);
DX_OUT : out STD_LOGIC_VECTOR (7 downto 0);
DY_OUT : out STD_LOGIC_VECTOR (7 downto 0);
ADRX : in STD_LOGIC_VECTOR (4 downto 0);
ADRY : in STD_LOGIC_VECTOR (4 downto 0);
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end RegisterFile;
architecture Behavioral of RegisterFile is
TYPE memory is array (0 to 31) of std_logic_vector(7 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
begin
process(clk) begin
if (rising_edge(clk)) then
if (WE = '1') then
REG(conv_integer(ADRX)) <= D_IN;
end if;
end if;
end process;
DX_OUT <= REG(conv_integer(ADRX));
DY_OUT <= REG(conv_integer(ADRY));
end Behavioral;
| mit | 393d55fc11661215ed75ba6f1e4342a7 | 0.57169 | 3.708145 | false | false | false | false |
stefanct/aua | hw/alu/src/Mux16to1.vhd | 1 | 2,053 | library ieee;
use ieee.std_logic_1164.all;
entity Mux16to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
i05: in std_logic_vector(15 downto 0);
i06: in std_logic_vector(15 downto 0);
i07: in std_logic_vector(15 downto 0);
i08: in std_logic_vector(15 downto 0);
i09: in std_logic_vector(15 downto 0);
i10: in std_logic_vector(15 downto 0);
i11: in std_logic_vector(15 downto 0);
i12: in std_logic_vector(15 downto 0);
i13: in std_logic_vector(15 downto 0);
i14: in std_logic_vector(15 downto 0);
i15: in std_logic_vector(15 downto 0);
i16: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Mux16to1 is
component Mux4to1 is
port( i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(1 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end component;
signal mux_sel: std_logic_vector(1 downto 0);
signal mux1_o: std_logic_vector(15 downto 0);
signal mux2_o: std_logic_vector(15 downto 0);
signal mux3_o: std_logic_vector(15 downto 0);
signal mux4_o: std_logic_vector(15 downto 0);
begin
mux1: Mux4to1 port map(i01, i02, i03, i04, mux_sel, mux1_o);
mux2: Mux4to1 port map(i05, i06, i07, i08, mux_sel, mux2_o);
mux3: Mux4to1 port map(i09, i10, i11, i12, mux_sel, mux3_o);
mux4: Mux4to1 port map(i13, i14, i15, i16, mux_sel, mux4_o);
process(sel, mux1_o, mux2_o, mux3_o, mux4_o)
begin
mux_sel <= sel(1 downto 0);
case sel(3 downto 2) is
when "00" => mux_out <= mux1_o;
when "01" => mux_out <= mux2_o;
when "10" => mux_out <= mux3_o;
when "11" => mux_out <= mux4_o;
when others => mux_out <= x"0000";
end case;
end process;
end rtl; | gpl-3.0 | 81aac7ed358c7001e7337532cdb7bf8e | 0.643449 | 2.497567 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_prog_rom_0_0/synth/RAT_prog_rom_0_0.vhd | 2 | 3,829 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:prog_rom:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_prog_rom_0_0 IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END RAT_prog_rom_0_0;
ARCHITECTURE RAT_prog_rom_0_0_arch OF RAT_prog_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT prog_rom IS
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
INSTRUCTION : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
CLK : IN STD_LOGIC
);
END COMPONENT prog_rom;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "prog_rom,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_prog_rom_0_0_arch : ARCHITECTURE IS "RAT_prog_rom_0_0,prog_rom,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_prog_rom_0_0_arch: ARCHITECTURE IS "RAT_prog_rom_0_0,prog_rom,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=prog_rom,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : prog_rom
PORT MAP (
ADDRESS => ADDRESS,
INSTRUCTION => INSTRUCTION,
CLK => CLK
);
END RAT_prog_rom_0_0_arch;
| mit | 253d8a9ddb5484e50722cf54278a71c8 | 0.739096 | 3.863774 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/RAT_RegisterFile_0_0_sim_netlist.vhdl | 2 | 6,533 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:46:57 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/RAT_RegisterFile_0_0_sim_netlist.vhdl
-- Design : RAT_RegisterFile_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_RegisterFile_0_0_RegisterFile is
port (
DY_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
DX_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
CLK : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR ( 7 downto 0 );
WE : in STD_LOGIC;
ADRX : in STD_LOGIC_VECTOR ( 4 downto 0 );
ADRY : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_RegisterFile_0_0_RegisterFile : entity is "RegisterFile";
end RAT_RegisterFile_0_0_RegisterFile;
architecture STRUCTURE of RAT_RegisterFile_0_0_RegisterFile is
begin
REG_reg_0_31_0_0: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(0),
DPO => DY_OUT(0),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(0),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_1_1: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(1),
DPO => DY_OUT(1),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(1),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_2_2: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(2),
DPO => DY_OUT(2),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(2),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_3_3: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(3),
DPO => DY_OUT(3),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(3),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_4_4: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(4),
DPO => DY_OUT(4),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(4),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_5_5: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(5),
DPO => DY_OUT(5),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(5),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_6_6: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(6),
DPO => DY_OUT(6),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(6),
WCLK => CLK,
WE => WE
);
REG_reg_0_31_7_7: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => ADRX(0),
A1 => ADRX(1),
A2 => ADRX(2),
A3 => ADRX(3),
A4 => ADRX(4),
D => D_IN(7),
DPO => DY_OUT(7),
DPRA0 => ADRY(0),
DPRA1 => ADRY(1),
DPRA2 => ADRY(2),
DPRA3 => ADRY(3),
DPRA4 => ADRY(4),
SPO => DX_OUT(7),
WCLK => CLK,
WE => WE
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_RegisterFile_0_0 is
port (
D_IN : in STD_LOGIC_VECTOR ( 7 downto 0 );
DX_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
DY_OUT : out STD_LOGIC_VECTOR ( 7 downto 0 );
ADRX : in STD_LOGIC_VECTOR ( 4 downto 0 );
ADRY : in STD_LOGIC_VECTOR ( 4 downto 0 );
WE : in STD_LOGIC;
CLK : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_RegisterFile_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_RegisterFile_0_0 : entity is "RAT_RegisterFile_0_0,RegisterFile,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_RegisterFile_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_RegisterFile_0_0 : entity is "RegisterFile,Vivado 2016.4";
end RAT_RegisterFile_0_0;
architecture STRUCTURE of RAT_RegisterFile_0_0 is
begin
U0: entity work.RAT_RegisterFile_0_0_RegisterFile
port map (
ADRX(4 downto 0) => ADRX(4 downto 0),
ADRY(4 downto 0) => ADRY(4 downto 0),
CLK => CLK,
DX_OUT(7 downto 0) => DX_OUT(7 downto 0),
DY_OUT(7 downto 0) => DY_OUT(7 downto 0),
D_IN(7 downto 0) => D_IN(7 downto 0),
WE => WE
);
end STRUCTURE;
| mit | b52fbc737846693861294abb86dd7e39 | 0.51921 | 3.179075 | false | false | false | false |
qynvi/rtl-adders | rcadder_tb.vhd | 1 | 906 | -- William Fan
-- 2/19/2011
-- RCAdder Testbench
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
generic (N: integer := 8);
end testbench;
architecture tb of testbench is
signal input1,input2,sum: std_logic_vector((N-1) downto 0);
signal c_in,c_out: std_logic := '0';
begin
rcatb: entity work.rcadder port map (input1,input2,c_in,sum,c_out);
tb: process
begin
input1 <= "01111000"; -- =120d
wait;
input2 <= "00000000"; -- =0d
wait for 120 ns;
input2 <= "00101000"; -- =40d
wait for 140 ns;
input2 <= "01011010"; -- =90d
wait for 120 ns;
input2 <= "01111000"; -- =120d
wait for 120 ns;
input2 <= "10010110"; -- =150d
wait for 120 ns;
input2 <= "10110100"; -- =180d
wait for 120 ns;
input2 <= "11010010"; -- =210d
wait for 120 ns;
c_in <= '0';
wait for 200 ns;
c_in <= '1';
wait for 80 ns;
c_in <= '0';
wait;
end process tb;
end;
| mit | 0dab1872c5e81cea3a5e038a92ea8fcb | 0.613687 | 2.633721 | false | true | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_StackPointer_0_0/RAT_StackPointer_0_0_sim_netlist.vhdl | 1 | 9,544 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 10:19:57 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_StackPointer_0_0/RAT_StackPointer_0_0_sim_netlist.vhdl
-- Design : RAT_StackPointer_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_StackPointer_0_0_StackPointer is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DECR : in STD_LOGIC;
INCR : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
LD : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_StackPointer_0_0_StackPointer : entity is "StackPointer";
end RAT_StackPointer_0_0_StackPointer;
architecture STRUCTURE of RAT_StackPointer_0_0_StackPointer is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \SP[3]_i_2_n_0\ : STD_LOGIC;
signal \SP[4]_i_2_n_0\ : STD_LOGIC;
signal \SP[4]_i_3_n_0\ : STD_LOGIC;
signal \SP[5]_i_2_n_0\ : STD_LOGIC;
signal \SP[5]_i_3_n_0\ : STD_LOGIC;
signal \SP[6]_i_2_n_0\ : STD_LOGIC;
signal \SP[6]_i_3_n_0\ : STD_LOGIC;
signal \SP[7]_i_1_n_0\ : STD_LOGIC;
signal \SP[7]_i_3_n_0\ : STD_LOGIC;
signal \SP[7]_i_4_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \SP[4]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \SP[4]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \SP[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \SP[5]_i_3\ : label is "soft_lutpair0";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\SP[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5754"
)
port map (
I0 => \^q\(0),
I1 => DECR,
I2 => INCR,
I3 => DATA(0),
O => p_0_in(0)
);
\SP[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CE3232CE"
)
port map (
I0 => DATA(1),
I1 => DECR,
I2 => INCR,
I3 => \^q\(0),
I4 => \^q\(1),
O => p_0_in(1)
);
\SP[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9CC6DDD79CC68882"
)
port map (
I0 => DECR,
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => INCR,
I5 => DATA(2),
O => p_0_in(2)
);
\SP[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9FFFFAAA90000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => DECR,
I5 => \SP[3]_i_2_n_0\,
O => p_0_in(3)
);
\SP[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => INCR,
I5 => DATA(3),
O => \SP[3]_i_2_n_0\
);
\SP[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B487B7B7B4878484"
)
port map (
I0 => \SP[4]_i_2_n_0\,
I1 => DECR,
I2 => \^q\(4),
I3 => \SP[4]_i_3_n_0\,
I4 => INCR,
I5 => DATA(4),
O => p_0_in(4)
);
\SP[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => \SP[4]_i_2_n_0\
);
\SP[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(3),
O => \SP[4]_i_3_n_0\
);
\SP[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"784B7B7B784B4848"
)
port map (
I0 => \SP[5]_i_2_n_0\,
I1 => DECR,
I2 => \^q\(5),
I3 => \SP[5]_i_3_n_0\,
I4 => INCR,
I5 => DATA(5),
O => p_0_in(5)
);
\SP[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \^q\(3),
O => \SP[5]_i_2_n_0\
);
\SP[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(4),
O => \SP[5]_i_3_n_0\
);
\SP[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B787B7B4B784848"
)
port map (
I0 => \SP[6]_i_2_n_0\,
I1 => DECR,
I2 => \^q\(6),
I3 => \SP[6]_i_3_n_0\,
I4 => INCR,
I5 => DATA(6),
O => p_0_in(6)
);
\SP[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \SP[6]_i_2_n_0\
);
\SP[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(4),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(3),
O => \SP[6]_i_3_n_0\
);
\SP[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => LD,
I1 => INCR,
I2 => DECR,
O => \SP[7]_i_1_n_0\
);
\SP[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \^q\(7),
I1 => \SP[6]_i_3_n_0\,
I2 => \^q\(6),
I3 => INCR,
I4 => DATA(7),
O => \SP[7]_i_3_n_0\
);
\SP[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(7),
I1 => \^q\(6),
I2 => \SP[6]_i_2_n_0\,
O => \SP[7]_i_4_n_0\
);
\SP_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(0),
Q => \^q\(0)
);
\SP_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(1),
Q => \^q\(1)
);
\SP_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(2),
Q => \^q\(2)
);
\SP_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(3),
Q => \^q\(3)
);
\SP_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(4),
Q => \^q\(4)
);
\SP_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(5),
Q => \^q\(5)
);
\SP_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(6),
Q => \^q\(6)
);
\SP_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => \SP[7]_i_1_n_0\,
CLR => RST,
D => p_0_in(7),
Q => \^q\(7)
);
\SP_reg[7]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \SP[7]_i_3_n_0\,
I1 => \SP[7]_i_4_n_0\,
O => p_0_in(7),
S => DECR
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_StackPointer_0_0 is
port (
DATA : in STD_LOGIC_VECTOR ( 7 downto 0 );
RST : in STD_LOGIC;
LD : in STD_LOGIC;
INCR : in STD_LOGIC;
DECR : in STD_LOGIC;
CLK : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_StackPointer_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_StackPointer_0_0 : entity is "RAT_StackPointer_0_0,StackPointer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_StackPointer_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_StackPointer_0_0 : entity is "StackPointer,Vivado 2016.4";
end RAT_StackPointer_0_0;
architecture STRUCTURE of RAT_StackPointer_0_0 is
begin
U0: entity work.RAT_StackPointer_0_0_StackPointer
port map (
CLK => CLK,
DATA(7 downto 0) => DATA(7 downto 0),
DECR => DECR,
INCR => INCR,
LD => LD,
Q(7 downto 0) => DOUT(7 downto 0),
RST => RST
);
end STRUCTURE;
| mit | 07a306ff03a7c9f182bfbdfdcd5c0e83 | 0.47171 | 2.798827 | false | false | false | false |
stefanct/aua | hw/alu/src/alu_opt.vhd | 1 | 10,502 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
architecture opt of alu is
component Mux32to1 is
port(
i01: in std_logic_vector(15 downto 0);
i02: in std_logic_vector(15 downto 0);
i03: in std_logic_vector(15 downto 0);
i04: in std_logic_vector(15 downto 0);
i05: in std_logic_vector(15 downto 0);
i06: in std_logic_vector(15 downto 0);
i07: in std_logic_vector(15 downto 0);
i08: in std_logic_vector(15 downto 0);
i09: in std_logic_vector(15 downto 0);
i10: in std_logic_vector(15 downto 0);
i11: in std_logic_vector(15 downto 0);
i12: in std_logic_vector(15 downto 0);
i13: in std_logic_vector(15 downto 0);
i14: in std_logic_vector(15 downto 0);
i15: in std_logic_vector(15 downto 0);
i16: in std_logic_vector(15 downto 0);
i17: in std_logic_vector(15 downto 0);
i18: in std_logic_vector(15 downto 0);
i19: in std_logic_vector(15 downto 0);
i20: in std_logic_vector(15 downto 0);
i21: in std_logic_vector(15 downto 0);
i22: in std_logic_vector(15 downto 0);
i23: in std_logic_vector(15 downto 0);
i24: in std_logic_vector(15 downto 0);
i25: in std_logic_vector(15 downto 0);
i26: in std_logic_vector(15 downto 0);
i27: in std_logic_vector(15 downto 0);
i28: in std_logic_vector(15 downto 0);
i29: in std_logic_vector(15 downto 0);
i30: in std_logic_vector(15 downto 0);
i31: in std_logic_vector(15 downto 0);
i32: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(4 downto 0);
mux_out: out std_logic_vector(15 downto 0)
);
end component;
signal carry: std_logic;
signal carry_nxt: std_logic;
signal mux_sel: std_logic_vector(4 downto 0);
signal mux1_o: word_t;
signal res_ldi: word_t;
signal res_addi: word_t;
signal res_muli: word_t;
signal res_add: word_t;
signal res_addc: word_t;
signal res_sub: word_t;
signal res_subc: word_t;
signal res_mul: word_t;
signal res_mulu: word_t;
signal res_mulh: word_t;
signal res_mulhu: word_t;
signal res_or: word_t;
signal res_and: word_t;
signal res_xor: word_t;
signal res_not: word_t;
signal res_neg: word_t;
signal res_asr: word_t;
signal res_lsl: word_t;
signal res_lsr: word_t;
signal res_lsli: word_t;
signal res_lsri: word_t;
signal res_scb: word_t;
signal res_roti: word_t;
signal res_cmplt: word_t;
signal res_cmpltu: word_t;
signal res_cmplte: word_t;
signal res_cmplteu: word_t;
signal res_cmpe: word_t;
signal res_cmpei: word_t;
signal res_mov: word_t;
signal res_ignore: word_t;
begin
mux1: Mux32to1 port map
( res_ldi,
res_add,
res_mul,
res_add,
res_addc,
res_sub,
res_subc,
res_mul,
res_mulu,
res_mulh,
res_mulhu,
res_or,
res_and,
res_xor,
res_not,
res_neg,
res_asr,
res_lsl,
res_lsr,
res_lsli,
res_lsri,
res_scb,
res_roti,
res_cmplt,
res_cmpltu,
res_cmplte,
res_cmplteu,
res_cmpe,
res_cmpei,
res_mov,
res_ignore,
res_ignore,
mux_sel,
mux1_o
);
sync_carry: process (clk, reset)
begin
if reset = '1' then
carry <= '0';
elsif rising_edge(clk) then
carry <= carry_nxt;
end if;
end process;
process(opcode, opa, opb, carry, mux1_o)
variable tmp_sel: std_logic_vector(4 downto 0);
variable tmp_opa: std_logic_vector(16 downto 0);
variable tmp_opb: std_logic_vector(16 downto 0);
variable tmp_addc: std_logic_vector(16 downto 0);
variable tmp_subc: std_logic_vector(16 downto 0);
variable tmp_carry: std_logic_vector(16 downto 0);
variable carry_addc:std_logic;
variable carry_subc:std_logic;
variable tmp_muls: std_logic_vector(31 downto 0);
variable tmp_mulu: std_logic_vector(31 downto 0);
variable tmp_scb: word_t;
variable tmp_sll: word_t;
variable tmp_srl: word_t;
begin
res_ldi <= opa(15 downto 8) & opb(7 downto 0);
--------------------------------------------------------------------------------------------------
tmp_opa := std_logic_vector(('0' & opa));
tmp_opb := std_logic_vector(('0' & opb));
if (opcode = "100001") or (opcode = "100011") then
tmp_carry := (x"0000"&carry);
else
tmp_carry := (16 downto 0 => '0');
end if;
tmp_addc := std_logic_vector(unsigned(tmp_opa) + unsigned(tmp_opb) + unsigned(tmp_carry));
tmp_subc := std_logic_vector(unsigned(tmp_opa) - unsigned(tmp_opb) - unsigned(tmp_carry));
carry_addc := tmp_addc(16);
carry_subc := tmp_subc(16);
res_add <= tmp_addc(15 downto 0);
res_addc <= tmp_addc(15 downto 0);
res_sub <= tmp_subc(15 downto 0);
res_subc <= tmp_subc(15 downto 0);
if opcode = "100001" or opcode = "011000" or opcode = "100000" then
carry_nxt <= carry_addc;
elsif opcode = "100011" or opcode = "100010" then
carry_nxt <= carry_subc;
else
carry_nxt <= '0';
end if;
--------------------------------------------------------------------------------------------------
-- tmp_add := std_logic_vector(('0' & unsigned(opa)) + ('0' & unsigned(opb)));
-- tmp_addc := std_logic_vector(('0' & unsigned(opa)) + ('0' & unsigned(opb)) + (x"0000"&carry));
-- carry_add := tmp_add(16);
-- carry_addc := tmp_addc(16);
--
-- res_add <= tmp_add(15 downto 0);
-- res_addc <= tmp_addc(15 downto 0);
--
-- tmp_sub := std_logic_vector(('0' & unsigned(opa)) - ('0' & unsigned(opb)));
-- tmp_subc := std_logic_vector(('0' & unsigned(opa)) - ('0' & unsigned(opb)) - (x"0000"&carry));
-- carry_sub := tmp_sub(16);
-- carry_subc := tmp_subc(16);
--
-- res_sub <= tmp_sub(15 downto 0);
-- res_subc <= tmp_subc(15 downto 0);
--------------------------------------------------------------------------------------------------
tmp_muls := std_logic_vector(signed(opa) * signed(opb));
tmp_mulu := std_logic_vector(unsigned(opa) * unsigned(opb));
res_mul <= tmp_muls(15 downto 0);
res_mulu <= tmp_mulu(15 downto 0);
res_mulh <= tmp_muls(31 downto 16);
res_mulhu <= tmp_mulu(31 downto 16);
res_or <= opa or opb;
res_and <= opa and opb;
res_xor <= opa xor opb;
res_not <= not opb;
res_neg <= std_logic_vector(unsigned(not opb) + 1);
res_asr <= to_stdlogicvector(to_bitvector(opb) sra 1);
res_lsl <= std_logic_vector(unsigned(opb) sll 1);
res_lsr <= std_logic_vector(unsigned(opb) srl 1);
res_lsli <= std_logic_vector(unsigned(opa) sll to_integer(unsigned(opb(3 downto 0))));
res_lsri <= std_logic_vector(unsigned(opa) srl to_integer(unsigned(opb(3 downto 0))));
tmp_scb := opa;
tmp_scb(to_integer(unsigned(opb(3 downto 0)))) := opb(4);
res_scb <= tmp_scb;
if opb(4) = '0' then -- rotl
res_roti <= std_logic_vector(unsigned(opa) rol to_integer(unsigned(opb(3 downto 0))));
else -- rotr
res_roti <= std_logic_vector(unsigned(opa) ror to_integer(unsigned(opb(3 downto 0))));
end if;
if signed(opa) < signed(opb) then
res_cmplt <= x"0001";
else
res_cmplt <= x"0000";
end if;
if unsigned(opa) < unsigned(opb) then
res_cmpltu <= x"0001";
else
res_cmpltu <= x"0000";
end if;
if signed(opa) <= signed(opb) then
res_cmplte <= x"0001";
else
res_cmplte <= x"0000";
end if;
if unsigned(opa) <= unsigned(opb) then
res_cmplteu <= x"0001";
else
res_cmplteu <= x"0000";
end if;
if opa = opb then
res_cmpe <= x"0001";
else
res_cmpe <= x"0000";
end if;
if opa = ((15 downto 5 => '0')&opb(4 downto 0)) then
res_cmpei <= x"0001";
else
res_cmpei <= x"0000";
end if;
res_mov <= opb;
res_ignore <= x"0000";
case opcode(5 downto 3) is
when "000" => tmp_sel := "00000"; --ldi
--when "001" => tmp_sel := "11110"; branches--ignore
--when "010" => tmp_sel := "11110"; --ignore
when "011" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "00001"; --addi
when "001" => tmp_sel := "00001"; --addi
when "010" => tmp_sel := "00001"; --addi
when "011" => tmp_sel := "00001"; --addi
when "100" => tmp_sel := "00010"; --muli
when "101" => tmp_sel := "00010"; --muli
when "110" => tmp_sel := "00010"; --muli
when "111" => tmp_sel := "00010"; --muli
when others => tmp_sel := "11110"; --ignore
end case;
when "100" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "00011"; --add
when "001" => tmp_sel := "00100"; --addc
when "010" => tmp_sel := "00101"; --sub
when "011" => tmp_sel := "00110"; --subc
when "100" => tmp_sel := "00111"; --mul
when "101" => tmp_sel := "01000"; --mulu
when "110" => tmp_sel := "01001"; --mulh
when "111" => tmp_sel := "01010"; --mulhu
when others => tmp_sel := "11110"; --ignore
end case;
when "101" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "01011"; --or
when "001" => tmp_sel := "01100"; --and
when "010" => tmp_sel := "01101"; --xor
when "011" => tmp_sel := "01110"; --not
when "100" => tmp_sel := "01111"; --neg
when "101" => tmp_sel := "10000"; --asr
when "110" => tmp_sel := "10001"; --lsl
when "111" => tmp_sel := "10010"; --lsr
when others => tmp_sel := "11110"; --ignore
end case;
when "110" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "10011"; --lsli
when "001" => tmp_sel := "10100"; --lsri
when "010" => tmp_sel := "10101"; --scb
when "011" => tmp_sel := "10110"; --roti
when "100" => tmp_sel := "10111"; --cmplt
when "101" => tmp_sel := "11000"; --cmpltu
when "110" => tmp_sel := "11001"; --cmplte
when "111" => tmp_sel := "11010"; --cmplteu
when others => tmp_sel := "11110"; --ignore
end case;
when "111" =>
case opcode(2 downto 0) is
when "000" => tmp_sel := "11011"; --cmpe
when "001" => tmp_sel := "11100"; --cmpei
when "010" => tmp_sel := "11110"; --ignore
when "011" => tmp_sel := "11101"; --mov
when "100" => tmp_sel := "11110"; --ld, ignore
when "101" => tmp_sel := "11110"; --ldb, ignore
when "110" => tmp_sel := "11110"; --st, ignore
when "111" => tmp_sel := "11110"; --stb, ignore
when others => tmp_sel := "11110"; --ignore
end case;
when others => tmp_sel := "11110"; --ignore
end case;
mux_sel <= tmp_sel;
result <= mux1_o;
end process;
end opt;
| gpl-3.0 | f457def0ac1e1942ab821d88b0fc6016 | 0.561036 | 2.781987 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_17_13_0/synth/RAT_slice_17_13_0.vhd | 2 | 3,828 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_17_13_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END RAT_slice_17_13_0;
ARCHITECTURE RAT_slice_17_13_0_arch OF RAT_slice_17_13_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_17_13_0_arch : ARCHITECTURE IS "RAT_slice_17_13_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "RAT_slice_17_13_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=1,DIN_TO=0}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 1,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_17_13_0_arch;
| mit | 5d569c1bb8008b48bc6b96ce79527199 | 0.728579 | 3.847236 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_cic_compiler_0_0/sim/design_1_cic_compiler_0_0.vhd | 2 | 7,234 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 16,
C_OUTPUT_WIDTH => 35,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 35,
C_C2 => 35,
C_C3 => 35,
C_C4 => 35,
C_C5 => 0,
C_C6 => 0,
C_I1 => 35,
C_I2 => 35,
C_I3 => 35,
C_I4 => 35,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
| mit | 51f4290a82c6e722ffccb6fe0b670ec8 | 0.651092 | 3.325977 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_ML505.vhdl | 1 | 8,033 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.io.all;
entity clknet_ClockNetwork_ML505 is
generic (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
architecture trl of clknet_ClockNetwork_ML505 is
attribute KEEP : BOOLEAN;
attribute ASYNC_REG : STRING;
attribute SHREG_EXTRACT : STRING;
signal ClkNet_Reset : STD_LOGIC;
signal DCM_Reset : STD_LOGIC;
signal DCM_Reset_clr : STD_LOGIC;
signal DCM_Locked : STD_LOGIC;
signal DCM_Locked_async : STD_LOGIC;
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal Control_Clock_BUFR : STD_LOGIC;
signal DCM_Clock_10MHz : STD_LOGIC;
signal DCM_Clock_100MHz : STD_LOGIC;
signal DCM_Clock_125MHz : STD_LOGIC;
signal DCM_Clock_200MHz : STD_LOGIC;
signal DCM_Clock_10MHz_BUFG : STD_LOGIC;
signal DCM_Clock_100MHz_BUFG : STD_LOGIC;
signal DCM_Clock_125MHz_BUFG : STD_LOGIC;
signal DCM_Clock_200MHz_BUFG : STD_LOGIC;
attribute KEEP of DCM_Clock_10MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_100MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_125MHz_BUFG : signal is DEBUG;
attribute KEEP of DCM_Clock_200MHz_BUFG : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) DCM_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Xilinx
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => DCM_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => DCM_Locked --
);
DCM_Reset_clr <= ClkNet_Reset NOR DCM_Locked;
-- RS-FF Q RST SET CLK
DCM_Reset <= ffrs(q => ClkNet_Reset, rst => DCM_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
Locked <= DCM_Locked;
Reset <= NOT Locked;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
BUFR_Control_Clock : BUFR
-- GENERIC MAP (
-- SIM_DEVICE => "7SERIES"
-- )
port map (
CE => '1',
CLR => '0',
I => ClockIn_100MHz,
O => Control_Clock_BUFR
);
Control_Clock <= Control_Clock_BUFR;
-- 10 MHz BUFG
BUFG_Clock_10MHz : BUFG
port map (
I => DCM_Clock_10MHz,
O => DCM_Clock_10MHz_BUFG
);
-- 100 MHz BUFG
BUFG_Clock_100MHz : BUFG
port map (
I => DCM_Clock_100MHz,
O => DCM_Clock_100MHz_BUFG
);
-- 125 MHz BUFG
BUFG_Clock_125MHz : BUFG
port map (
I => DCM_Clock_125MHz,
O => DCM_Clock_125MHz_BUFG
);
-- 200 MHz BUFG
BUFG_Clock_200MHz : BUFG
port map (
I => DCM_Clock_200MHz,
O => DCM_Clock_200MHz_BUFG
);
-- ==================================================================
-- Digital Clock Manager (DCM)
-- ==================================================================
System_DCM : DCM_BASE
generic map (
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
CLKIN_PERIOD => 1.0e9 / real(CLOCK_IN_FREQ / 1 Hz),
CLKDV_DIVIDE => 10.0,
CLKFX_MULTIPLY => 5,
CLKFX_DIVIDE => 4
)
port map (
CLKIN => ClockIn_100MHz,
CLKFB => DCM_Clock_100MHz_BUFG,
RST => DCM_Reset,
CLKDV => DCM_Clock_10MHz,
CLK0 => DCM_Clock_100MHz,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => DCM_Clock_200MHz,
CLK2X180 => open,
CLKFX => DCM_Clock_125MHz,
CLKFX180 => open,
LOCKED => DCM_Locked_async
);
Control_Clock_100MHz <= Control_Clock_BUFR;
Clock_200MHz <= DCM_Clock_200MHz_BUFG;
Clock_125MHz <= DCM_Clock_125MHz_BUFG;
Clock_100MHz <= DCM_Clock_100MHz_BUFG;
Clock_10MHz <= DCM_Clock_10MHz_BUFG;
-- synchronize internal Locked signal to ouput clock domains
syncReset200MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_200MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncReset125MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_125MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncReset100MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_100MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncReset10MHz: entity PoC.sync_Bits_Xilinx
port map (
Clock => DCM_Clock_10MHz_BUFG, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | ae8b71380ac386a5a56882dfebfcf16e | 0.518362 | 3.70355 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/common/my_config_KC705.vhdl | 1 | 1,790 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Xilinx KC705 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "KC705"; -- KC705 - Xilinx Kintex 7 reference design board: XC7K325T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
--
constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures
end package;
| apache-2.0 | 7dcf96f3a573c9b32d6e8e9cb2ae7dee | 0.570391 | 4.685864 | false | true | false | false |
stefanct/aua | hw/src/aua_top.vhd | 1 | 16,083 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity aua is
port (
clk_in : in std_logic;
reset_pin : in std_logic;
switch_pins : in std_logic_vector(15 downto 0);
led_pins : out std_logic_vector(15 downto 0);
digit0_pins : out std_logic_vector(6 downto 0);
digit1_pins : out std_logic_vector(6 downto 0);
digit2_pins : out std_logic_vector(6 downto 0);
digit3_pins : out std_logic_vector(6 downto 0);
digit4_pins : out std_logic_vector(6 downto 0);
digit5_pins : out std_logic_vector(6 downto 0);
sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
sram_dq : inout word_t;
sram_we : out std_logic;
-- sram_oe : out std_logic;
sram_ub : out std_logic;
sram_lb : out std_logic;
-- sram_ce : out std_logic
txd : out std_logic;
rxd : in std_logic
--~ ncts : in std_logic;
--~ nrts : out std_logic
);
end aua;
architecture sat1 of aua is
component aua_pll is
port(
areset : in std_logic;
inclk0 : in std_logic;
c0 : out std_logic
);
end component;
component ent_if is
generic (
INIT_VECTOR : pc_t
);
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register outputs
opcode_out : out opcode_t;
dest_out : out reg_t;
pc_out : out pc_t;
pcnxt_out : out pc_t;
rega_out : out reg_t;
regb_out : out reg_t;
imm_out : out std_logic_vector(7 downto 0);
-- asynchron register outputs
async_rega : out reg_t;
async_regb : out reg_t;
-- branches (from ID)
pc_in : in pc_t;
branch : in std_logic;
-- cache
instr_addr : out word_t;
instr_valid : in std_logic;
instr_data : in word_t;
-- interlock
lock : in std_logic
);
end component;
component id is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register inputs
opcode_in : in opcode_t;
dest_in : in reg_t;
pc_in : in pc_t;
pcnxt_in : in pc_t;
rega_in : in reg_t;
regb_in : in reg_t;
imm_in : in std_logic_vector(7 downto 0);
-- asynchron register inputs
async_rega : in reg_t;
async_regb : in reg_t;
-- results from wb to reg file
regr : in reg_t;
valr : in word_t;
-- pipeline register outputs
opcode_out : out opcode_t;
dest_out : out reg_t;
opa_out : out word_t;
opb_out : out word_t;
-- needed for EX forwarding
rega_out : out reg_t;
regb_out : out reg_t;
opb_isfrom_regb : out boolean;
-- branch decision
pc_out : out pc_t;
branch_out : out std_logic;
-- interlock
lock : in std_logic;
id_locks : out std_logic
);
end component;
component ex is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register inputs
opcode : in opcode_t;
dest_in : in reg_t;
opa : in word_t;
opb : in word_t;
-- pipeline register outputs
dest_out : out reg_t;
result_out : out word_t;
-- interface to MMU
mmu_address : out word_t;
mmu_result : in word_t;
mmu_st_data : out word_t;
mmu_enable : out std_logic;
mmu_opcode : out std_logic_vector(1 downto 0);
mmu_done : in std_logic;
-- pipeline interlock
ex_locks : out std_ulogic;
ex_locks_async : out std_ulogic
);
end component;
component instr_cache is
port (
clk : in std_logic;
reset : in std_logic;
-- cache/if
id_instr_addr : in word_t;
id_instr_valid : out std_logic;
id_instr : out word_t;
-- cache/mmu
mmu_instr_addr : out word_t;
mmu_enable : out std_logic;
mmu_instr_valid : in std_logic;
mmu_instr : in word_t
);
end component;
component mmu is
generic (
CLK_FREQ : natural;
SRAM_RD_FREQ : natural;
SRAM_WR_FREQ : natural
);
port (
clk : in std_logic;
reset : in std_logic;
-- IF stage
instr_addr : in word_t;
instr_enable: in std_logic;
instr_data : out word_t;
instr_valid : out std_logic;
-- interface to EX stage
ex_address : in word_t;
ex_rd_data : out word_t;
ex_wr_data : in word_t;
ex_enable : in std_logic;
ex_opcode : in std_logic_vector(1 downto 0);
ex_done : out std_logic;
-- SimpCon interface to IO devices
sc_io_in : in sc_in_t;
sc_io_out : out sc_out_t;
-- interface to SRAM
sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0);
sram_dq : inout word_t;
sram_we : out std_logic; -- write enable, low active, 0=enable, 1=disable
-- sram_oe : out std_logic; -- output enable, low active
sram_ub : out std_logic; -- upper byte, low active
sram_lb : out std_logic -- lower byte, low active
-- sram_ce : out std_logic -- chip enable, low active
);
end component;
component sc_de2_switches is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t;
-- pins
switch_pins : in std_logic_vector(15 downto 0);
led_pins : out std_logic_vector(15 downto 0)
);
end component;
component sc_de2_digits is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t;
-- pins
digit0_pins : out std_logic_vector(6 downto 0);
digit1_pins : out std_logic_vector(6 downto 0);
digit2_pins : out std_logic_vector(6 downto 0);
digit3_pins : out std_logic_vector(6 downto 0);
digit4_pins : out std_logic_vector(6 downto 0);
digit5_pins : out std_logic_vector(6 downto 0)
);
end component;
component sc_uart is
generic(
clk_freq : integer;
baud_rate : integer;
txf_depth : integer;
txf_thres : integer;
rxf_depth : integer;
rxf_thres : integer
);
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t;
-- pins
txd : out std_logic;
rxd : in std_logic;
ncts : in std_logic;
nrts : out std_logic
);
end component;
component sc_test_slave is
port (
clk : in std_logic;
reset : in std_logic;
-- SimpCon slave interface to IO ctrl
address : in sc_addr_t;
wr_data : in sc_data_t;
rd : in std_logic;
wr : in std_logic;
rd_data : out sc_data_t;
rdy_cnt : out sc_rdy_cnt_t
);
end component;
signal reset : std_logic;
-- clk Signal aus PLL
signal clk : std_logic;
-- pipeline registers (written by top)
-- IF/ID
signal ifid_opcode_out : opcode_t;
signal ifid_dest_out : reg_t;
signal ifid_pc_out : pc_t;
signal ifid_pcnxt_out : pc_t;
signal ifid_rega_out : reg_t;
signal ifid_regb_out : reg_t;
signal ifid_async_rega_out : reg_t;
signal ifid_async_regb_out : reg_t;
signal ifid_imm_out : std_logic_vector(7 downto 0);
-- ID/IF
signal idif_pc_out : pc_t;
signal idif_branch_out : std_logic;
-- ID/EX
signal idex_opcode_out : opcode_t;
signal idex_dest_out : reg_t;
signal idex_opa_out : word_t;
signal idex_opb_out : word_t;
-- EX/ID (for WB)
signal exid_dest_out : reg_t;
signal exid_result_out : word_t;
-- pipeline registers (read by top)
-- IF/ID
signal ifid_opcode_in : opcode_t;
signal ifid_dest_in : reg_t;
signal ifid_pc_in : pc_t;
signal ifid_pcnxt_in : pc_t;
signal ifid_rega_in : reg_t;
signal ifid_regb_in : reg_t;
signal ifid_async_rega_in : reg_t;
signal ifid_async_regb_in : reg_t;
signal ifid_imm_in : std_logic_vector(7 downto 0);
-- ID/IF
signal idif_pc_in : pc_t;
signal idif_branch_in : std_logic;
-- ID/EX
signal idex_opcode_in : opcode_t;
signal idex_dest_in : reg_t;
signal idex_opa_in : word_t;
signal idex_opb_in : word_t;
-- EX/ID (for WB)
signal exid_dest_in : reg_t;
signal exid_result_in : word_t;
-- IF/CACHE/MMU
signal ifcache_addr : word_t;
signal ifcache_data : word_t;
signal ifcache_valid : std_logic;
signal cachemmu_addr : word_t;
signal cachemmu_data : word_t;
signal cachemmu_valid : std_logic;
signal cachemmu_enable : std_logic;
-- MMU interfaces
-- EX/MMU
signal exmmu_address : word_t;
signal exmmu_result_mmu : word_t;
signal exmmu_wr_data : word_t;
signal exmmu_enable : std_logic;
signal exmmu_mmu_opcode : std_logic_vector(1 downto 0);
signal exmmu_valid : std_logic;
-- MMU/IO
signal mmuio_out : sc_out_t;
signal mmuio_outa : sc_out_at;
signal mmuio_in : sc_in_t;
signal mmuio_ina : sc_in_at;
--forwarding
signal id_rega_in : reg_t;
signal id_regb_in : reg_t;
signal id_opb_isfrom_regb : boolean;
signal exid_dest : reg_t;
signal exid_result : word_t;
--interlocks
signal ex_locks : std_logic;
signal ex_locks_async : std_logic;
signal lock_if : std_logic;
signal lock_id : std_logic;
signal id_locks_async : std_logic;
-- IO helpers
signal sc_sel, sc_sel_reg : integer range 0 to 2**SC_ADDR_BITS; -- one more than needed (for NC)
signal sc_addr : sc_addr_t;
signal reset_sync : std_logic; -- reset pin is async! so we synchronize it: see sync_reset
signal reset_pll : std_logic;
begin
cmp_pll: aua_pll
port map(reset_pll, clk_in, clk);
cmp_if: ent_if
generic map(RST_VECTOR)
port map(clk, reset, ifid_opcode_in, ifid_dest_in, ifid_pc_in, ifid_pcnxt_in, ifid_rega_in, ifid_regb_in, ifid_imm_in, ifid_async_rega_in, ifid_async_regb_in, idif_pc_out, idif_branch_out, ifcache_addr, ifcache_valid, ifcache_data, lock_if);
cmp_id: id
port map(clk, reset, ifid_opcode_out, ifid_dest_out, ifid_pc_out, ifid_pcnxt_out, ifid_rega_out, ifid_regb_out, ifid_imm_out, ifid_async_rega_out, ifid_async_regb_out, exid_dest_out, exid_result_out, idex_opcode_in, idex_dest_in, idex_opa_in, idex_opb_in, id_rega_in, id_regb_in, id_opb_isfrom_regb, idif_pc_in, idif_branch_in, lock_id, id_locks_async);
cmp_ex: ex
port map(clk, reset, idex_opcode_out, idex_dest_out, idex_opa_out, idex_opb_out, exid_dest_in, exid_result_in, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid, ex_locks, ex_locks_async);
cmp_icache: instr_cache
port map(clk, reset, ifcache_addr, ifcache_valid, ifcache_data, cachemmu_addr, cachemmu_enable, cachemmu_valid, cachemmu_data);
cmp_mmu: mmu
generic map(CLK_FREQ, SRAM_RD_FREQ, SRAM_WR_FREQ)
port map(clk, reset, cachemmu_addr, cachemmu_enable, cachemmu_data, cachemmu_valid,
exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid,
mmuio_in, mmuio_out,
sram_addr, sram_dq, sram_we, sram_ub, sram_lb);
-- taken from http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
sync_reset: process (clk, reset_pin)
begin
if (reset_pin = '0') then
reset_sync <= '1';
reset <= '1';
elsif rising_edge(clk) then
reset_sync <= '0';
reset <= reset_sync;
end if;
end process;
reset_pll <= not reset_pin; -- needs to be async (think about it. :)
ifid_opcode_out <= ifid_opcode_in;
ifid_dest_out <= ifid_dest_in;
ifid_pc_out <= ifid_pc_in;
ifid_pcnxt_out <= ifid_pcnxt_in;
ifid_rega_out <= ifid_rega_in;
ifid_regb_out <= ifid_regb_in;
ifid_async_rega_out <= ifid_async_rega_in;
ifid_async_regb_out <= ifid_async_regb_in;
ifid_imm_out <= ifid_imm_in;
idif_pc_out <= idif_pc_in;
idif_branch_out <= idif_branch_in;
idex_opcode_out <= idex_opcode_in;
idex_dest_out <= idex_dest_in;
exid_dest_out <= exid_dest_in;
exid_result_out <= exid_result_in;
lock_if <= ex_locks_async or id_locks_async;
lock_id <= ex_locks_async;
ex_fw: process(id_rega_in, id_regb_in, exid_dest, exid_result, idex_opa_in, idex_opb_in, id_opb_isfrom_regb, ex_locks)
begin
if id_rega_in = exid_dest and ex_locks = '0' then
idex_opa_out <= exid_result;
else
idex_opa_out <= idex_opa_in;
end if;
if id_regb_in = exid_dest and id_opb_isfrom_regb and ex_locks = '0' then
idex_opb_out <= exid_result;
else
idex_opb_out <= idex_opb_in;
end if;
end process;
sync: process (clk, reset)
begin
if reset = '1' then
exid_dest <= (others => '0');
exid_result <= (others => '0');
elsif rising_edge(clk) then
exid_dest <= exid_dest_in;
exid_result <= exid_result_in;
end if;
end process;
sc_sync: process(clk, reset)
begin
if (reset='1') then
sc_sel_reg <= 0;
-- sc_sel_reg <= SC_SLAVE_CNT; -- would be correct, but does not work on all devices; procudes warning
elsif rising_edge(clk) then
sc_sel_reg <= sc_sel;
end if;
end process;
sc_in_mux: process (mmuio_ina, sc_sel_reg)
begin
if sc_sel_reg /= SC_SLAVE_CNT then
mmuio_in.rd_data <= mmuio_ina(sc_sel_reg).rd_data;
mmuio_in.rdy_cnt <= mmuio_ina(sc_sel_reg).rdy_cnt;
else
mmuio_in.rd_data <= (others => '0');
mmuio_in.rdy_cnt <= (others => '0');
end if;
end process;
sc_rdwr_mux: for i in 0 to SC_SLAVE_CNT-1 generate
mmuio_outa(i).rd <= mmuio_out.rd when i=sc_sel else '0';
mmuio_outa(i).wr <= mmuio_out.wr when i=sc_sel else '0';
end generate;
-- 0* --> ram
-- 10* --> rom
-- 11* --> simcon...
-- 1111* --> Blöcke 0xF000/4
-- 11111111 * --> Blöcke 0xFF00/8 (I/O Devices)
-- 11111111 0000* --> Switches 0xFF00/12
-- 11111111 0001* --> Digits 0xFF10/12
-- 11111111 0002* --> uart 0XFF20/12
--
-- 11111111 1111111* --> Test 0xFFFE/15
-- FEDCBA98 76543210
sc_addr <= mmuio_out.address;
sc_sc_selector: process (mmuio_out, sc_addr)
begin
if((sc_addr and x"FFF0") = x"FF00") then
sc_sel <= 0;
elsif((sc_addr and x"FFF0") = x"FF10") then
sc_sel <= 1;
elsif((sc_addr and x"FFF0") = x"FF20") then
sc_sel <= 2;
elsif((sc_addr and x"FFFE") = x"FFFE") then
sc_sel <= 3;
else
sc_sel <= SC_SLAVE_CNT;
end if;
end process;
--IO devices below
cmp_switches: sc_de2_switches
port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(0).rd, mmuio_outa(0).wr, mmuio_ina(0).rd_data, mmuio_ina(0).rdy_cnt, switch_pins, led_pins);
cmp_digits: sc_de2_digits
port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(1).rd, mmuio_outa(1).wr, mmuio_ina(1).rd_data, mmuio_ina(1).rdy_cnt,
digit0_pins, digit1_pins, digit2_pins, digit3_pins, digit4_pins, digit5_pins);
cmp_uart: sc_uart
generic map(CLK_FREQ, UART_RATE, 4, 2, 4, 2)
port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(2).rd, mmuio_outa(2).wr, mmuio_ina(2).rd_data, mmuio_ina(2).rdy_cnt,
txd, rxd, '0', open);
cmp_test: sc_test_slave
port map(clk, reset, mmuio_out.address, mmuio_out.wr_data, mmuio_outa(3).rd, mmuio_outa(3).wr, mmuio_ina(3).rd_data, mmuio_ina(3).rdy_cnt);
end sat1;
use WORK.all;
configuration aua_cache of aua is
for sat1
for cmp_icache : instr_cache
use entity work.instr_cache(cache_null);
--~ use entity work.instr_cache(cache_direct);
end for;
for cmp_ex: ex
use entity work.ex(sat1);
for sat1
for cmp_alu: alu
use entity work.alu(old);
--~ use entity work.alu(opt);
end for;
end for;
end for;
-- does not work... why?
--~ for cmp_mmu: mmu
--~ use entity work.mmu(sat1)
--~ generic map(1) -- irq_cnt
--~ port map(clk, reset, cachemmu_addr, cachemmu_data, cachemmu_valid, exmmu_address, exmmu_result_mmu, exmmu_wr_data, exmmu_enable, exmmu_mmu_opcode, exmmu_valid,
--~ mmuio_address, mmuio_wr_data, mmuio_rd, mmuio_wr, mmuio_rd_data, mmuio_rdy_cnt,
--~ sram_addr, sram_dq, sram_we, sram_oe, sram_ub, sram_lb, sram_ce);
--~ end for;
end for;
end aua_cache;
| gpl-3.0 | 387732af4ee39a097262195ae1864dc6 | 0.620484 | 2.59371 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/synth/RAT_ControlUnit_0_0.vhd | 1 | 7,370 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:ControlUnit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_ControlUnit_0_0 IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_OE : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_RESET : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RF_OE : OUT STD_LOGIC;
REG_IMMED_SEL : OUT STD_LOGIC;
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_OE : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END RAT_ControlUnit_0_0;
ARCHITECTURE RAT_ControlUnit_0_0_arch OF RAT_ControlUnit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ControlUnit IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_OE : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_RESET : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RF_OE : OUT STD_LOGIC;
REG_IMMED_SEL : OUT STD_LOGIC;
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_OE : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END COMPONENT ControlUnit;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "ControlUnit,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_ControlUnit_0_0_arch : ARCHITECTURE IS "RAT_ControlUnit_0_0,ControlUnit,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "RAT_ControlUnit_0_0,ControlUnit,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=ControlUnit,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF PC_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 PC_RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF SP_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 SP_RESET RST";
BEGIN
U0 : ControlUnit
PORT MAP (
CLK => CLK,
C => C,
Z => Z,
INT => INT,
RST => RST,
OPCODE_HI_5 => OPCODE_HI_5,
OPCODE_LO_2 => OPCODE_LO_2,
PC_LD => PC_LD,
PC_INC => PC_INC,
PC_RESET => PC_RESET,
PC_OE => PC_OE,
PC_MUX_SEL => PC_MUX_SEL,
SP_LD => SP_LD,
SP_MUX_SEL => SP_MUX_SEL,
SP_RESET => SP_RESET,
RF_WR => RF_WR,
RF_WR_SEL => RF_WR_SEL,
RF_OE => RF_OE,
REG_IMMED_SEL => REG_IMMED_SEL,
ALU_SEL => ALU_SEL,
ALU_OPY_SEL => ALU_OPY_SEL,
SCR_WR => SCR_WR,
SCR_OE => SCR_OE,
SCR_ADDR_SEL => SCR_ADDR_SEL,
C_FLAG_SEL => C_FLAG_SEL,
C_FLAG_LD => C_FLAG_LD,
C_FLAG_SET => C_FLAG_SET,
C_FLAG_CLR => C_FLAG_CLR,
SHAD_C_LD => SHAD_C_LD,
Z_FLAG_SEL => Z_FLAG_SEL,
Z_FLAG_LD => Z_FLAG_LD,
Z_FLAG_SET => Z_FLAG_SET,
Z_FLAG_CLR => Z_FLAG_CLR,
SHAD_Z_LD => SHAD_Z_LD,
I_FLAG_SET => I_FLAG_SET,
I_FLAG_CLR => I_FLAG_CLR,
IO_OE => IO_OE
);
END RAT_ControlUnit_0_0_arch;
| mit | 7576b445362316810df91b84572a8ee2 | 0.656445 | 3.301971 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/RTL/StackPointer.vhd | 1 | 925 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity StackPointer is
port (
DATA : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
LD : in STD_LOGIC;
INCR : in STD_LOGIC;
DECR : in STD_LOGIC;
CLK : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (7 downto 0)
);
end StackPointer;
architecture Stack of StackPointer is
signal SP : STD_LOGIC_VECTOR (7 downto 0) := x"00";
begin
-- Load new value if needed
LOAD : process (CLK, LD, SP, INCR, DECR) begin
if (rising_edge(CLK)) then
if (DECR = '1') then
SP <= SP - 1;
elsif (INCR = '1') then
SP <= SP + 1;
elsif ((LD = '1')) then
SP <= DATA;
end if;
end if;
if (RST = '1') then
SP <= (others => '0');
end if;
end process LOAD;
-- Output resulting stack pointers
DOUT <= SP;
end Stack;
| mit | 1c6128ada1c45f94a89658ec409aeccb | 0.545946 | 3.167808 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/AND_BitABit.vhd | 1 | 721 | ----------------------------------------------------------------------------------
-- Create Date: 21:44:50 04/10/2017
-- Module Name: AND_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end AND_BitABit;
architecture Behavioral of AND_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) AND B(0);
Zout(1) <= A(1) AND B(1);
Zout(2) <= A(2) AND B(2);
Zout(3) <= A(3) AND B(3);
Z <= Zout;
end Behavioral;
| gpl-3.0 | 6d6163face99fe0caa0be270c1c0f988 | 0.467406 | 3.433333 | false | false | false | false |
marcoep/MusicBoxNano | hdl/MusicBoxDDS.vhd | 1 | 8,481 | -------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis
-- Project :
-------------------------------------------------------------------------------
-- File : MusicBoxDDS.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-08-01
-- Last update: 2016-08-01
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Direct Digital Synthesis for the Music Box Project. Takes
-- frequency increments and distributes it to DDS address generators. The
-- addresses get translated to the waveform one by one, multiplied with the
-- envelope, added up, and put out. 16-fold parallelism
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Marco Eppenberger
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-08-01 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.Helpers_Pkg.all;
entity MusicBoxDDS is
port (
Clk_CI : in std_logic;
Reset_SI : in std_logic;
FreqTick_SI : in std_logic;
FreqIncrement_D : in std_logic_vector(28 downto 0);
FreqIncrValid_SI : in std_logic;
Waveform_DO : out std_logic_vector(9 downto 0));
end entity MusicBoxDDS;
architecture RTL of MusicBoxDDS is
-- distribution
signal EnableShift_S : std_logic_vector(15 downto 0) := (0 => '1', others => '0');
-- collection
type wave_addr_gen_t is array(0 to 15) of std_logic_vector(11 downto 0);
signal WaveAddrGen_D : wave_addr_gen_t := (others => (others => '0'));
signal WaveAddr_D : std_logic_vector(11 downto 0) := (others => '0');
type env_addr_gen_t is array(0 to 15) of std_logic_vector(7 downto 0);
signal EnvAddrGen_D : env_addr_gen_t := (others => (others => '0'));
signal EnvAddr_D : std_logic_vector(7 downto 0) := (others => '0');
signal CollectionCnt_S : unsigned(3 downto 0) := (others => '0');
signal ColCntZero_S : std_logic := '0';
-- multiply accumulate
signal WaveformROM_D : std_logic_vector(7 downto 0) := (others => '0');
signal WaveformToMul_D : signed(8 downto 0) := (others => '0');
signal EnvelopeROM_D : std_logic_vector(7 downto 0) := (others => '0');
signal EnvelopeToMul_D : signed(8 downto 0) := (others => '0');
signal WaveformPostMul_D : signed(21 downto 0) := (others => '0');
signal WaveformSum_D : signed(21 downto 0) := (others => '0');
signal WaveformUnsigned_D : signed(21 downto 0) := (others => '0');
begin -- architecture RTL
-----------------------------------------------------------------------------
-- Distribute the Enable
-----------------------------------------------------------------------------
shift_ena_reg : process (Clk_CI) is
begin
if Clk_CI'event and Clk_CI = '1' then
if Reset_SI = '1' then
EnableShift_S <= ("0000000000000001");
else
if FreqIncrValid_SI = '1' then
EnableShift_S <= EnableShift_S(14 downto 0) & EnableShift_S(15);
end if;
end if;
end if;
end process shift_ena_reg;
-----------------------------------------------------------------------------
-- Generate the wave address generators
-----------------------------------------------------------------------------
wave_addr_gens : for i in 0 to 15 generate
DDSAddressGenerator_i : entity work.DDSAddressGenerator
generic map (
ENV_DECAY_SPEED => 8192,
DDS_COUNTER_WIDTH => 29)
port map (
Clk_CI => Clk_CI,
Reset_SI => Reset_SI,
Increment_DI => FreqIncrement_D,
IncrementValid_SI => (FreqIncrValid_SI and EnableShift_S(i)),
FreqTick_SI => FreqTick_SI,
DDSAddr_DO => WaveAddrGen_D(i),
EnvAddr_DO => EnvAddrGen_D(i));
end generate wave_addr_gens;
-----------------------------------------------------------------------------
-- Put Outputs through Env and Wave ROM
-----------------------------------------------------------------------------
-- counter for collection
output_cnt : process (Clk_CI) is
begin
if Clk_CI'event and Clk_CI = '1' then
if Reset_SI = '1' then
CollectionCnt_S <= (others => '0');
else
CollectionCnt_S <= CollectionCnt_S + 1;
end if;
end if;
end process output_cnt;
-- Mux (each latency 2)
WaveAddrMux_i : entity work.WaveAddrMux
port map (
clock => Clk_CI,
data0x => WaveAddrGen_D(0),
data1x => WaveAddrGen_D(1),
data2x => WaveAddrGen_D(2),
data3x => WaveAddrGen_D(3),
data4x => WaveAddrGen_D(4),
data5x => WaveAddrGen_D(5),
data6x => WaveAddrGen_D(6),
data7x => WaveAddrGen_D(7),
data8x => WaveAddrGen_D(8),
data9x => WaveAddrGen_D(9),
data10x => WaveAddrGen_D(10),
data11x => WaveAddrGen_D(11),
data12x => WaveAddrGen_D(12),
data13x => WaveAddrGen_D(13),
data14x => WaveAddrGen_D(14),
data15x => WaveAddrGen_D(15),
sel => std_logic_vector(CollectionCnt_S),
result => WaveAddr_D);
EnvAddrMux_i : entity work.EnvAddrMux
port map (
clock => Clk_CI,
data0x => EnvAddrGen_D(0),
data1x => EnvAddrGen_D(1),
data2x => EnvAddrGen_D(2),
data3x => EnvAddrGen_D(3),
data4x => EnvAddrGen_D(4),
data5x => EnvAddrGen_D(5),
data6x => EnvAddrGen_D(6),
data7x => EnvAddrGen_D(7),
data8x => EnvAddrGen_D(8),
data9x => EnvAddrGen_D(9),
data10x => EnvAddrGen_D(10),
data11x => EnvAddrGen_D(11),
data12x => EnvAddrGen_D(12),
data13x => EnvAddrGen_D(13),
data14x => EnvAddrGen_D(14),
data15x => EnvAddrGen_D(15),
sel => std_logic_vector(CollectionCnt_S),
result => EnvAddr_D);
-- Wave and Env ROM (each latency 2)
WaveformROM_i : entity work.WaveformROM
port map (
address => WaveAddr_D,
clock => Clk_CI,
q => WaveformROM_D);
EnvelopeROM_i : entity work.EnvelopeROM
port map (
address => EnvAddr_D,
clock => Clk_CI,
q => EnvelopeROM_D);
-----------------------------------------------------------------------------
-- Multiply and Accumulate
-----------------------------------------------------------------------------
-- resize words
premul_reg : process (Clk_CI) is
begin -- process premul_reg
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
WaveformToMul_D <= resize(signed(WaveformROM_D), 9);
EnvelopeToMul_D <= signed('0' & EnvelopeROM_D);
end if;
end process premul_reg;
-- multiply and resize for accumulation
WaveformPostMul_D <= resize(WaveformToMul_D * EnvelopeToMul_D, 22);
-- accumulate
ColCntZero_S <= bool2sl(CollectionCnt_S = "0000");
accumulate_reg : process (Clk_CI) is
begin -- process accumulate_reg
if Clk_CI'event and Clk_CI = '1' then
if Reset_SI = '1' then
WaveformSum_D <= (others => '0');
else
if ColCntZero_S = '1' then
WaveformSum_D <= WaveformPostMul_D;
else
WaveformSum_D <= WaveformSum_D + WaveformPostMul_D;
end if;
end if;
end if;
end process accumulate_reg;
-- calculate unsigned
unsigned_reg : process (Clk_CI) is
begin -- process unsigned_reg
if Clk_CI'event and Clk_CI = '1' then
if Reset_SI = '1' then
WaveformUnsigned_D <= (others => '0');
else
if ColCntZero_S = '1' then
WaveformUnsigned_D <= WaveformSum_D + to_signed(2**20, 22);
end if;
end if;
end if;
end process unsigned_reg;
-- output register
output_reg : process (Clk_CI) is
begin -- process output_reg
if Clk_CI'event and Clk_CI = '1' then
if Reset_SI = '1' then
Waveform_DO <= (others => '0');
else
Waveform_DO <= std_logic_vector(WaveformUnsigned_D(20 downto 11));
end if;
end if;
end process output_reg;
end architecture RTL;
| gpl-3.0 | 69657241e427d2336030a780dd12187e | 0.512675 | 3.877915 | false | false | false | false |
marcoep/MusicBoxNano | ip/WaveAddrMux.vhd | 1 | 15,362 | -- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: WaveAddrMux.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY WaveAddrMux IS
PORT
(
clock : IN STD_LOGIC ;
data0x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data15x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END WaveAddrMux;
ARCHITECTURE SYN OF waveaddrmux IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_2D (15 DOWNTO 0, 11 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire14 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire15 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire16 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL sub_wire17 : STD_LOGIC_VECTOR (11 DOWNTO 0);
BEGIN
sub_wire16 <= data0x(11 DOWNTO 0);
sub_wire15 <= data1x(11 DOWNTO 0);
sub_wire14 <= data2x(11 DOWNTO 0);
sub_wire13 <= data3x(11 DOWNTO 0);
sub_wire12 <= data4x(11 DOWNTO 0);
sub_wire11 <= data5x(11 DOWNTO 0);
sub_wire10 <= data6x(11 DOWNTO 0);
sub_wire9 <= data7x(11 DOWNTO 0);
sub_wire8 <= data8x(11 DOWNTO 0);
sub_wire7 <= data9x(11 DOWNTO 0);
sub_wire6 <= data10x(11 DOWNTO 0);
sub_wire5 <= data11x(11 DOWNTO 0);
sub_wire4 <= data12x(11 DOWNTO 0);
sub_wire3 <= data13x(11 DOWNTO 0);
sub_wire2 <= data14x(11 DOWNTO 0);
sub_wire0 <= data15x(11 DOWNTO 0);
sub_wire1(15, 0) <= sub_wire0(0);
sub_wire1(15, 1) <= sub_wire0(1);
sub_wire1(15, 2) <= sub_wire0(2);
sub_wire1(15, 3) <= sub_wire0(3);
sub_wire1(15, 4) <= sub_wire0(4);
sub_wire1(15, 5) <= sub_wire0(5);
sub_wire1(15, 6) <= sub_wire0(6);
sub_wire1(15, 7) <= sub_wire0(7);
sub_wire1(15, 8) <= sub_wire0(8);
sub_wire1(15, 9) <= sub_wire0(9);
sub_wire1(15, 10) <= sub_wire0(10);
sub_wire1(15, 11) <= sub_wire0(11);
sub_wire1(14, 0) <= sub_wire2(0);
sub_wire1(14, 1) <= sub_wire2(1);
sub_wire1(14, 2) <= sub_wire2(2);
sub_wire1(14, 3) <= sub_wire2(3);
sub_wire1(14, 4) <= sub_wire2(4);
sub_wire1(14, 5) <= sub_wire2(5);
sub_wire1(14, 6) <= sub_wire2(6);
sub_wire1(14, 7) <= sub_wire2(7);
sub_wire1(14, 8) <= sub_wire2(8);
sub_wire1(14, 9) <= sub_wire2(9);
sub_wire1(14, 10) <= sub_wire2(10);
sub_wire1(14, 11) <= sub_wire2(11);
sub_wire1(13, 0) <= sub_wire3(0);
sub_wire1(13, 1) <= sub_wire3(1);
sub_wire1(13, 2) <= sub_wire3(2);
sub_wire1(13, 3) <= sub_wire3(3);
sub_wire1(13, 4) <= sub_wire3(4);
sub_wire1(13, 5) <= sub_wire3(5);
sub_wire1(13, 6) <= sub_wire3(6);
sub_wire1(13, 7) <= sub_wire3(7);
sub_wire1(13, 8) <= sub_wire3(8);
sub_wire1(13, 9) <= sub_wire3(9);
sub_wire1(13, 10) <= sub_wire3(10);
sub_wire1(13, 11) <= sub_wire3(11);
sub_wire1(12, 0) <= sub_wire4(0);
sub_wire1(12, 1) <= sub_wire4(1);
sub_wire1(12, 2) <= sub_wire4(2);
sub_wire1(12, 3) <= sub_wire4(3);
sub_wire1(12, 4) <= sub_wire4(4);
sub_wire1(12, 5) <= sub_wire4(5);
sub_wire1(12, 6) <= sub_wire4(6);
sub_wire1(12, 7) <= sub_wire4(7);
sub_wire1(12, 8) <= sub_wire4(8);
sub_wire1(12, 9) <= sub_wire4(9);
sub_wire1(12, 10) <= sub_wire4(10);
sub_wire1(12, 11) <= sub_wire4(11);
sub_wire1(11, 0) <= sub_wire5(0);
sub_wire1(11, 1) <= sub_wire5(1);
sub_wire1(11, 2) <= sub_wire5(2);
sub_wire1(11, 3) <= sub_wire5(3);
sub_wire1(11, 4) <= sub_wire5(4);
sub_wire1(11, 5) <= sub_wire5(5);
sub_wire1(11, 6) <= sub_wire5(6);
sub_wire1(11, 7) <= sub_wire5(7);
sub_wire1(11, 8) <= sub_wire5(8);
sub_wire1(11, 9) <= sub_wire5(9);
sub_wire1(11, 10) <= sub_wire5(10);
sub_wire1(11, 11) <= sub_wire5(11);
sub_wire1(10, 0) <= sub_wire6(0);
sub_wire1(10, 1) <= sub_wire6(1);
sub_wire1(10, 2) <= sub_wire6(2);
sub_wire1(10, 3) <= sub_wire6(3);
sub_wire1(10, 4) <= sub_wire6(4);
sub_wire1(10, 5) <= sub_wire6(5);
sub_wire1(10, 6) <= sub_wire6(6);
sub_wire1(10, 7) <= sub_wire6(7);
sub_wire1(10, 8) <= sub_wire6(8);
sub_wire1(10, 9) <= sub_wire6(9);
sub_wire1(10, 10) <= sub_wire6(10);
sub_wire1(10, 11) <= sub_wire6(11);
sub_wire1(9, 0) <= sub_wire7(0);
sub_wire1(9, 1) <= sub_wire7(1);
sub_wire1(9, 2) <= sub_wire7(2);
sub_wire1(9, 3) <= sub_wire7(3);
sub_wire1(9, 4) <= sub_wire7(4);
sub_wire1(9, 5) <= sub_wire7(5);
sub_wire1(9, 6) <= sub_wire7(6);
sub_wire1(9, 7) <= sub_wire7(7);
sub_wire1(9, 8) <= sub_wire7(8);
sub_wire1(9, 9) <= sub_wire7(9);
sub_wire1(9, 10) <= sub_wire7(10);
sub_wire1(9, 11) <= sub_wire7(11);
sub_wire1(8, 0) <= sub_wire8(0);
sub_wire1(8, 1) <= sub_wire8(1);
sub_wire1(8, 2) <= sub_wire8(2);
sub_wire1(8, 3) <= sub_wire8(3);
sub_wire1(8, 4) <= sub_wire8(4);
sub_wire1(8, 5) <= sub_wire8(5);
sub_wire1(8, 6) <= sub_wire8(6);
sub_wire1(8, 7) <= sub_wire8(7);
sub_wire1(8, 8) <= sub_wire8(8);
sub_wire1(8, 9) <= sub_wire8(9);
sub_wire1(8, 10) <= sub_wire8(10);
sub_wire1(8, 11) <= sub_wire8(11);
sub_wire1(7, 0) <= sub_wire9(0);
sub_wire1(7, 1) <= sub_wire9(1);
sub_wire1(7, 2) <= sub_wire9(2);
sub_wire1(7, 3) <= sub_wire9(3);
sub_wire1(7, 4) <= sub_wire9(4);
sub_wire1(7, 5) <= sub_wire9(5);
sub_wire1(7, 6) <= sub_wire9(6);
sub_wire1(7, 7) <= sub_wire9(7);
sub_wire1(7, 8) <= sub_wire9(8);
sub_wire1(7, 9) <= sub_wire9(9);
sub_wire1(7, 10) <= sub_wire9(10);
sub_wire1(7, 11) <= sub_wire9(11);
sub_wire1(6, 0) <= sub_wire10(0);
sub_wire1(6, 1) <= sub_wire10(1);
sub_wire1(6, 2) <= sub_wire10(2);
sub_wire1(6, 3) <= sub_wire10(3);
sub_wire1(6, 4) <= sub_wire10(4);
sub_wire1(6, 5) <= sub_wire10(5);
sub_wire1(6, 6) <= sub_wire10(6);
sub_wire1(6, 7) <= sub_wire10(7);
sub_wire1(6, 8) <= sub_wire10(8);
sub_wire1(6, 9) <= sub_wire10(9);
sub_wire1(6, 10) <= sub_wire10(10);
sub_wire1(6, 11) <= sub_wire10(11);
sub_wire1(5, 0) <= sub_wire11(0);
sub_wire1(5, 1) <= sub_wire11(1);
sub_wire1(5, 2) <= sub_wire11(2);
sub_wire1(5, 3) <= sub_wire11(3);
sub_wire1(5, 4) <= sub_wire11(4);
sub_wire1(5, 5) <= sub_wire11(5);
sub_wire1(5, 6) <= sub_wire11(6);
sub_wire1(5, 7) <= sub_wire11(7);
sub_wire1(5, 8) <= sub_wire11(8);
sub_wire1(5, 9) <= sub_wire11(9);
sub_wire1(5, 10) <= sub_wire11(10);
sub_wire1(5, 11) <= sub_wire11(11);
sub_wire1(4, 0) <= sub_wire12(0);
sub_wire1(4, 1) <= sub_wire12(1);
sub_wire1(4, 2) <= sub_wire12(2);
sub_wire1(4, 3) <= sub_wire12(3);
sub_wire1(4, 4) <= sub_wire12(4);
sub_wire1(4, 5) <= sub_wire12(5);
sub_wire1(4, 6) <= sub_wire12(6);
sub_wire1(4, 7) <= sub_wire12(7);
sub_wire1(4, 8) <= sub_wire12(8);
sub_wire1(4, 9) <= sub_wire12(9);
sub_wire1(4, 10) <= sub_wire12(10);
sub_wire1(4, 11) <= sub_wire12(11);
sub_wire1(3, 0) <= sub_wire13(0);
sub_wire1(3, 1) <= sub_wire13(1);
sub_wire1(3, 2) <= sub_wire13(2);
sub_wire1(3, 3) <= sub_wire13(3);
sub_wire1(3, 4) <= sub_wire13(4);
sub_wire1(3, 5) <= sub_wire13(5);
sub_wire1(3, 6) <= sub_wire13(6);
sub_wire1(3, 7) <= sub_wire13(7);
sub_wire1(3, 8) <= sub_wire13(8);
sub_wire1(3, 9) <= sub_wire13(9);
sub_wire1(3, 10) <= sub_wire13(10);
sub_wire1(3, 11) <= sub_wire13(11);
sub_wire1(2, 0) <= sub_wire14(0);
sub_wire1(2, 1) <= sub_wire14(1);
sub_wire1(2, 2) <= sub_wire14(2);
sub_wire1(2, 3) <= sub_wire14(3);
sub_wire1(2, 4) <= sub_wire14(4);
sub_wire1(2, 5) <= sub_wire14(5);
sub_wire1(2, 6) <= sub_wire14(6);
sub_wire1(2, 7) <= sub_wire14(7);
sub_wire1(2, 8) <= sub_wire14(8);
sub_wire1(2, 9) <= sub_wire14(9);
sub_wire1(2, 10) <= sub_wire14(10);
sub_wire1(2, 11) <= sub_wire14(11);
sub_wire1(1, 0) <= sub_wire15(0);
sub_wire1(1, 1) <= sub_wire15(1);
sub_wire1(1, 2) <= sub_wire15(2);
sub_wire1(1, 3) <= sub_wire15(3);
sub_wire1(1, 4) <= sub_wire15(4);
sub_wire1(1, 5) <= sub_wire15(5);
sub_wire1(1, 6) <= sub_wire15(6);
sub_wire1(1, 7) <= sub_wire15(7);
sub_wire1(1, 8) <= sub_wire15(8);
sub_wire1(1, 9) <= sub_wire15(9);
sub_wire1(1, 10) <= sub_wire15(10);
sub_wire1(1, 11) <= sub_wire15(11);
sub_wire1(0, 0) <= sub_wire16(0);
sub_wire1(0, 1) <= sub_wire16(1);
sub_wire1(0, 2) <= sub_wire16(2);
sub_wire1(0, 3) <= sub_wire16(3);
sub_wire1(0, 4) <= sub_wire16(4);
sub_wire1(0, 5) <= sub_wire16(5);
sub_wire1(0, 6) <= sub_wire16(6);
sub_wire1(0, 7) <= sub_wire16(7);
sub_wire1(0, 8) <= sub_wire16(8);
sub_wire1(0, 9) <= sub_wire16(9);
sub_wire1(0, 10) <= sub_wire16(10);
sub_wire1(0, 11) <= sub_wire16(11);
result <= sub_wire17(11 DOWNTO 0);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_pipeline => 2,
lpm_size => 16,
lpm_type => "LPM_MUX",
lpm_width => 12,
lpm_widths => 4
)
PORT MAP (
clock => clock,
data => sub_wire1,
sel => sel,
result => sub_wire17
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data0x 0 0 12 0 INPUT NODEFVAL "data0x[11..0]"
-- Retrieval info: USED_PORT: data10x 0 0 12 0 INPUT NODEFVAL "data10x[11..0]"
-- Retrieval info: USED_PORT: data11x 0 0 12 0 INPUT NODEFVAL "data11x[11..0]"
-- Retrieval info: USED_PORT: data12x 0 0 12 0 INPUT NODEFVAL "data12x[11..0]"
-- Retrieval info: USED_PORT: data13x 0 0 12 0 INPUT NODEFVAL "data13x[11..0]"
-- Retrieval info: USED_PORT: data14x 0 0 12 0 INPUT NODEFVAL "data14x[11..0]"
-- Retrieval info: USED_PORT: data15x 0 0 12 0 INPUT NODEFVAL "data15x[11..0]"
-- Retrieval info: USED_PORT: data1x 0 0 12 0 INPUT NODEFVAL "data1x[11..0]"
-- Retrieval info: USED_PORT: data2x 0 0 12 0 INPUT NODEFVAL "data2x[11..0]"
-- Retrieval info: USED_PORT: data3x 0 0 12 0 INPUT NODEFVAL "data3x[11..0]"
-- Retrieval info: USED_PORT: data4x 0 0 12 0 INPUT NODEFVAL "data4x[11..0]"
-- Retrieval info: USED_PORT: data5x 0 0 12 0 INPUT NODEFVAL "data5x[11..0]"
-- Retrieval info: USED_PORT: data6x 0 0 12 0 INPUT NODEFVAL "data6x[11..0]"
-- Retrieval info: USED_PORT: data7x 0 0 12 0 INPUT NODEFVAL "data7x[11..0]"
-- Retrieval info: USED_PORT: data8x 0 0 12 0 INPUT NODEFVAL "data8x[11..0]"
-- Retrieval info: USED_PORT: data9x 0 0 12 0 INPUT NODEFVAL "data9x[11..0]"
-- Retrieval info: USED_PORT: result 0 0 12 0 OUTPUT NODEFVAL "result[11..0]"
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 1 0 12 0 data0x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 10 12 0 data10x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 11 12 0 data11x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 12 12 0 data12x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 13 12 0 data13x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 14 12 0 data14x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 15 12 0 data15x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 1 12 0 data1x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 2 12 0 data2x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 3 12 0 data3x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 4 12 0 data4x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 5 12 0 data5x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 6 12 0 data6x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 7 12 0 data7x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 8 12 0 data8x 0 0 12 0
-- Retrieval info: CONNECT: @data 1 9 12 0 data9x 0 0 12 0
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 12 0 @result 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL WaveAddrMux_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | 736e0d69688c68e1d5a4322540e8afd0 | 0.599401 | 2.400688 | false | false | false | false |
David-Estevez/spaceinvaders | src/spaceship_tb.vhd | 1 | 2,195 | ----------------------------------------------------------------------------------
--
-- Lab session #2: ship control testbench
--
-- Control the user spaceship
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY spaceship_tb IS
END spaceship_tb;
ARCHITECTURE behavior OF spaceship_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spaceship
PORT(
clk : IN std_logic;
reset : IN std_logic;
left : IN std_logic;
right : IN std_logic;
enable : IN std_logic;
posH : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal left : std_logic := '0';
signal right : std_logic := '0';
signal enable : std_logic := '0';
--Outputs
signal posH : std_logic_vector(4 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: spaceship PORT MAP (
clk => clk,
reset => reset,
left => left,
right => right,
enable => enable,
posH => posH
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '0';
wait for 100 ns;
reset <= '1';
enable <= '1'; -- without this enabled obviously it doesn't work
wait for clk_period*2;
left <= '1';
wait for clk_period*10;
left <= '0';
right <= '1';
wait for clk_period*20;
left <= '1';
right <= '0';
wait for clk_period*10;
left <= '0';
wait;
end process;
END;
| gpl-3.0 | a366e4f27b2fe7c4facc9dbff0151e6a | 0.507755 | 4.036832 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment6-ALU/Testbenches/ALU_TB.vhd | 1 | 3,923 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_alu IS
END tb_alu;
ARCHITECTURE tb OF tb_alu IS
constant data_width : integer := 8;
constant sel_width : integer := 4;
COMPONENT alu
PORT (
A : IN std_logic_vector (data_width - 1 DOWNTO 0);
B : IN std_logic_vector (data_width - 1 DOWNTO 0);
C_IN : IN std_logic;
Sel : IN std_logic_vector (sel_width - 1 DOWNTO 0);
SUM : OUT std_logic_vector (data_width - 1 DOWNTO 0);
C_FLAG : OUT std_logic;
Z_FLAG : OUT std_logic
);
END COMPONENT;
SIGNAL A_tb : std_logic_vector (data_width - 1 DOWNTO 0);
SIGNAL B_tb : std_logic_vector (data_width - 1 DOWNTO 0);
SIGNAL C_IN_tb : std_logic;
SIGNAL Sel_tb : std_logic_vector (sel_width - 1 DOWNTO 0);
SIGNAL SUM_tb : std_logic_vector (data_width - 1 DOWNTO 0);
SIGNAL C_FLAG_tb : std_logic;
SIGNAL Z_FLAG_tb : std_logic;
CONSTANT TbPeriod : TIME := 1000 ns; -- EDIT Put right period here
SIGNAL TbClock : std_logic := '0';
SIGNAL TbSimEnded : std_logic := '0';
BEGIN
dut : alu
PORT MAP(
A => A_tb,
B => B_tb,
C_IN => C_IN_tb,
Sel => Sel_tb,
SUM => SUM_tb,
C_FLAG => C_FLAG_tb,
Z_FLAG => Z_FLAG_tb
);
-- Clock generation
TbClock <= NOT TbClock AFTER TbPeriod/2 WHEN TbSimEnded /= '1' ELSE '0';
-- EDIT: Replace YOURCLOCKSIGNAL below by the name of your clock as I haven't guessed it
-- YOURCLOCKSIGNAL <= TbClock;
stimuli : PROCESS
BEGIN
-- EDIT Adapt initialization as needed
A_tb <= (OTHERS => '0');
B_tb <= (OTHERS => '0');
C_IN_tb <= '0';
Sel_tb <= (OTHERS => '0');
--Test Case #1: add
WAIT FOR 10ns;
Sel_tb <= x"0";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #2: addc
WAIT FOR 10ns;
Sel_tb <= x"1";
A_tb <= x"C8";
B_tb <= x"37";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #3: sub
WAIT FOR 10ns;
Sel_tb <= x"2";
A_tb <= x"C8";
B_tb <= x"64";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #4: subc
WAIT FOR 10ns;
Sel_tb <= x"3";
A_tb <= x"C8";
B_tb <= x"C8";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #5: COMP
WAIT FOR 10ns;
Sel_tb <= x"4";
A_tb <= x"AA";
B_tb <= x"FF";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #6: COMP
WAIT FOR 10ns;
Sel_tb <= x"4";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #7: AND
WAIT FOR 10ns;
Sel_tb <= x"5";
A_tb <= x"AA";
B_tb <= x"CC";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #7: OR
WAIT FOR 10ns;
Sel_tb <= x"6";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #8: XOR
WAIT FOR 10ns;
Sel_tb <= x"7";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #9: TEST
WAIT FOR 10ns;
Sel_tb <= x"8";
A_tb <= x"AA";
B_tb <= x"55";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #10: LSL
WAIT FOR 10ns;
Sel_tb <= x"9";
A_tb <= x"01";
B_tb <= x"12";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #11: LSR
WAIT FOR 10ns;
Sel_tb <= x"A";
A_tb <= x"81";
B_tb <= x"33";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #12: ROL
WAIT FOR 10ns;
Sel_tb <= x"B";
A_tb <= x"01";
B_tb <= x"AB";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #13: ROR
WAIT FOR 10ns;
Sel_tb <= x"C";
A_tb <= x"81";
B_tb <= x"3C";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #14: ASR
WAIT FOR 10ns;
Sel_tb <= x"D";
A_tb <= x"81";
B_tb <= x"81";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #15: MOV
WAIT FOR 10ns;
Sel_tb <= x"E";
A_tb <= x"50";
B_tb <= x"30";
C_IN_tb <= '0';
WAIT FOR 10ns;
WAIT FOR 100 * TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
WAIT;
END PROCESS;
END tb;
| mit | 914198e2813ba6b3b976a1b6811219d6 | 0.515167 | 2.30088 | false | true | false | false |
David-Estevez/spaceinvaders | src/spaceship.vhd | 1 | 1,572 | ----------------------------------------------------------------------------------
--
-- Lab session #2: spaceship control
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spaceship is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
left : in STD_LOGIC;
right : in STD_LOGIC;
enable : in STD_LOGIC;
posH : out STD_LOGIC_VECTOR (4 downto 0));
end spaceship;
architecture Behavioral of spaceship is
begin
process( reset, clk )
variable posHAux: integer range 0 to 19; -- To be able to update the ship position
begin
-- High level reset
if reset = '1' then
posHAux := 9;
posH <= std_logic_vector( to_unsigned( posHAux, 5) ); --"00111"; -- Center the ship
-- Synchronous behaviour
elsif clk'Event and clk = '1' then
-- Clear
if Clear = '1' then
posHAux := 9;
posH <= std_logic_vector( to_unsigned( posHAux, 5) ); --"00111"; -- Center the ship
-- When enabled...
elsif enable = '1' then
-- Move left/right if possible
if left = '1' and posHAux /= 0 then
posHAux := posHAux - 1;
elsif right = '1' and posHAux /= 19 then
posHAux := posHAux + 1;
end if;
end if;
end if;
-- Update the position
posH <= std_logic_vector( to_unsigned( posHAux, 5) );
end process;
end Behavioral;
| gpl-3.0 | cc36222eac2ed2c493c55d9c48a5fe24 | 0.530911 | 3.718009 | false | false | false | false |
odeke-em/hdl-class | learning/gTestBenches-Sequential.vhd | 1 | 711 | entity TestAnd2
end entity TestAnd2
architecture test2 of TestAnd2 is
signal a, b, c: BIT;
begin
g1: entity WORK.And2(arch2) port map (x => a, y => b, z => c);
process is
begin
a <= '0';
b <= '0';
wait for 100ns;
a <= '1';
wait for 150ns;
b <= '1';
wait; -- Suspend the process forever
end process;
end architecture test2;
-- A process without "wait" and without sensitivity list will run forever at time 0;
-- process(a) is: (a) a sensitivity list;
-- The process is evaluated only when the signals in the sensitivity list change.
-- A process can have a sensitivity list or "wait" statements, but not both (and not neither).
| mit | 7575ff47f632692dba1f1eb9b64e08a9 | 0.62166 | 3.664948 | false | true | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_utils_v2_0/hdl/axi_utils_v2_0_vh_rfs.vhd | 5 | 292,074 | `protect begin_protected
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VSVE5z/g4qBzG4/jxr3/vLn8GEhQEWw2ahuZUlnPaOJySyL23cVBaqj3SSwZMGnqluoQWEAKU0tw
a4tuga2WXl9Q9dArQN+bNnqNt9NwAZ3JQNmq7LE2Y6zW7Ssr8WtY2ehmOc/OccvJyarHLp0y2XxD
0bao0oeblNk91Gee4x4NCDUkbJHRCazz07IN51HEw5kEOgLqVqsJE99C+jonIrM4QeKXNlCP8htm
J9kVj+IYF3jnLANlpsyt9MR0UlIsRER5zn4Kkqfj7O8NBs8Yqm3GE9R8QR2s
`protect end_protected
| mit | 7cab57d1c9719259ab44235f52812be5 | 0.955056 | 1.831105 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_0_0/sim/RAT_FlagReg_0_0.vhd | 2 | 3,343 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_0_0 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_0_0;
ARCHITECTURE RAT_FlagReg_0_0_arch OF RAT_FlagReg_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_0_0_arch;
| mit | 6fdafc046c3c109951a05ce3fb48ad6c | 0.717918 | 4.022864 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 2/Multiplicador/test_mult_BCD_comb.vhd | 1 | 1,375 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
ENTITY MultBcd_1Dig_TEST IS
END MultBcd_1Dig_TEST;
ARCHITECTURE behavior OF MultBcd_1Dig_TEST IS
component MultBcd_1Dig is
port (
a_bcd_1dig : in unsigned (3 downto 0);
b_bcd_1dig : in unsigned (3 downto 0);
cin_bcd_1dig : in unsigned (3 downto 0);
z_bcd_1dig : out unsigned (3 downto 0);
cout_bcd_1dig : out unsigned (3 downto 0)
);
end component;
signal a, b, c: unsigned(3 downto 0) := (others => '0');
signal z, cout: unsigned(3 downto 0) := (others => '0');
BEGIN
uut: MultBcd_1Dig PORT MAP (
a_bcd_1dig => a,
b_bcd_1dig => b,
cin_bcd_1dig => c,
z_bcd_1dig => z,
cout_bcd_1dig => cout
);
stim_proc: process
begin
-- Teste 1
wait for 100 ns;
c <= "0000";
-- Entrada 1 = 50
--------------------------------- MSB
-- a(19 downto 16) <= "0000";
-- a(15 downto 12) <= "0010";
-- a(11 downto 8) <= "0000";
-- a(7 downto 4) <= "0000";
a(3 downto 0) <= "0111";
--------------------------------- LSB
-- Entrada 2 = 50
--------------------------------- MSB
-- b(19 downto 16) <= "0000";
-- b(15 downto 12) <= "0000";
-- b(11 downto 8) <= "0010";
-- b(7 downto 4) <= "0000";
b(3 downto 0) <= "0111";
--------------------------------- LSB
wait;
end process;
END behavior;
| gpl-3.0 | 7126651e91d97726fdde39e5e5586164 | 0.504 | 2.888655 | false | true | false | false |
VLSI-EDA/PoC-Examples | src/xil/clknet/clknet_ClockNetwork_DE4.vhdl | 1 | 10,650 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library altera_mf;
use altera_mf.Altera_MF_Components.all;
library PoC;
use PoC.physical.all;
use PoC.components.all;
entity clknet_ClockNetwork_DE4 is
GENERIC (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_250MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_250MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
architecture rtl of clknet_ClockNetwork_DE4 is
attribute PRESERVE : BOOLEAN;
-- component altpll
-- generic (
-- bandwidth_type : STRING;
-- clk0_divide_by : NATURAL;
-- clk0_duty_cycle : NATURAL;
-- clk0_multiply_by : NATURAL;
-- clk0_phase_shift : STRING;
-- inclk0_input_frequency : NATURAL;
-- intended_device_family : STRING;
-- lpm_hint : STRING;
-- lpm_type : STRING;
-- operation_mode : STRING;
-- pll_type : STRING;
-- port_activeclock : STRING;
-- port_areset : STRING;
-- port_clkbad0 : STRING;
-- port_clkbad1 : STRING;
-- port_clkloss : STRING;
-- port_clkswitch : STRING;
-- port_configupdate : STRING;
-- port_fbin : STRING;
-- port_fbout : STRING;
-- port_inclk0 : STRING;
-- port_inclk1 : STRING;
-- port_locked : STRING;
-- port_pfdena : STRING;
-- port_phasecounterselect : STRING;
-- port_phasedone : STRING;
-- port_phasestep : STRING;
-- port_phaseupdown : STRING;
-- port_pllena : STRING;
-- port_scanaclr : STRING;
-- port_scanclk : STRING;
-- port_scanclkena : STRING;
-- port_scandata : STRING;
-- port_scandataout : STRING;
-- port_scandone : STRING;
-- port_scanread : STRING;
-- port_scanwrite : STRING;
-- port_clk0 : STRING;
-- port_clk1 : STRING;
-- port_clk2 : STRING;
-- port_clk3 : STRING;
-- port_clk4 : STRING;
-- port_clk5 : STRING;
-- port_clk6 : STRING;
-- port_clk7 : STRING;
-- port_clk8 : STRING;
-- port_clk9 : STRING;
-- port_clkena0 : STRING;
-- port_clkena1 : STRING;
-- port_clkena2 : STRING;
-- port_clkena3 : STRING;
-- port_clkena4 : STRING;
-- port_clkena5 : STRING;
-- using_fbmimicbidir_port : STRING;
-- width_clock : NATURAL
-- );
-- port (
-- clk : out STD_LOGIC_VECTOR (9 downto 0);
-- inclk : in STD_LOGIC_VECTOR (1 downto 0)
-- );
-- end component;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (100 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal PLL_Reset : STD_LOGIC;
signal PLL_Reset_clr : STD_LOGIC;
signal PLL_ResetState : STD_LOGIC := '0';
signal PLL_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal PLL_Locked_async : STD_LOGIC;
signal PLL_Locked : STD_LOGIC;
signal PLL_Locked_d : STD_LOGIC := '0';
signal PLL_Locked_re : STD_LOGIC;
signal PLL_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal PLL_Clock_250MHz : STD_LOGIC;
signal PLL_Clock_200MHz : STD_LOGIC;
signal PLL_Clock_125MHz : STD_LOGIC;
signal PLL_Clock_100MHz : STD_LOGIC;
signal PLL_Clock_10MHz : STD_LOGIC;
attribute PRESERVE of PLL_Clock_10MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_100MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_125MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_200MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_250MHz : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) PLL_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Altera
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => PLL_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => PLL_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
PLL_Reset_clr <= ClkNet_Reset nor PLL_Locked;
-- detect rising edge on CMB locked signals
PLL_Locked_d <= PLL_Locked when rising_edge(Control_Clock);
PLL_Locked_re <= not PLL_Locked_d and PLL_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
PLL_ResetState <= ffrs(q => PLL_ResetState, rst => PLL_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
PLL_LockedState <= ffrs(q => PLL_LockedState, rst => ClkNet_Reset, set => PLL_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
PLL_Reset_delayed <= sr_left(PLL_Reset_delayed, PLL_ResetState) when rising_edge(Control_Clock);
PLL_Reset <= PLL_Reset_delayed(PLL_Reset_delayed'high);
Locked <= PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
Control_Clock <= ClockIn_100MHz;
Control_Clock_100MHz <= Control_Clock;
Clock_250MHz <= PLL_Clock_250MHz;
Clock_200MHz <= PLL_Clock_200MHz;
Clock_125MHz <= PLL_Clock_125MHz;
Clock_100MHz <= PLL_Clock_100MHz;
Clock_10MHz <= PLL_Clock_10MHz;
PLL: entity work.mypll
port map (
AReset => PLL_Reset,
inclk0 => ClockIn_100MHz,
Locked => PLL_Locked_async,
c0 => PLL_Clock_100MHz,
c1 => PLL_Clock_200MHz,
c2 => PLL_Clock_250MHz,
c3 => PLL_Clock_125MHz,
c4 => PLL_Clock_10MHz
);
-- synchronize internal Locked signal to output clock domains
syncLocked250MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_250MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_250MHz -- synchronized data
);
syncLocked200MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_200MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_125MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_100MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_10MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
| apache-2.0 | 1cba9fb0e560ad198cc9617cfa547c2a | 0.537746 | 3.651011 | false | false | false | false |
MiddleMan5/233 | Experiments/RTL_Components/CPE233-master/vgaDriverBuffer.vhd | 1 | 3,916 | --
-- The interface to the VGA driver module. Extended to both read and write
-- to the framebuffer (to check the color values of a particular pixel).
--
-- Original author: unknown
--
-- Modified by: Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaDriverBuffer is
Port ( CLK, we : in std_logic;
wa : in std_logic_vector (10 downto 0);
wd : in std_logic_vector (7 downto 0);
Rout : out std_logic_vector(2 downto 0);
Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
HS : out std_logic;
VS : out std_logic;
pixelData : out std_logic_vector(7 downto 0)
);
end vgaDriverBuffer;
architecture Behavioral of vgaDriverBuffer is
-- vga driver signals
signal rgbout : std_logic_vector(7 downto 0);
signal ra : std_logic_vector(10 downto 0);
signal vgaData : std_logic_vector(7 downto 0);
signal fb_wr, vgaclk : std_logic;
signal red, green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal row, column : std_logic_vector(9 downto 0);
-- Added to read the pixel data at address 'wa' -- pfh, 3/1/2012
signal pixelVal : std_logic_vector(7 downto 0);
-- Declare VGA driver components
component VGAdrive is
port( clock : in std_logic; -- 25.175 Mhz clock
red, green : in std_logic_vector(2 downto 0);
blue : in std_logic_vector(1 downto 0);
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
H, V : out std_logic); -- VGA drive signals
end component;
component ram2k_8 is
port(clk: in STD_LOGIC;
we: in STD_LOGIC;
ra, wa: in STD_LOGIC_VECTOR(10 downto 0);
wd: in STD_LOGIC_VECTOR(7 downto 0);
rd: out STD_LOGIC_VECTOR(7 downto 0);
pixelVal: out STD_LOGIC_VECTOR(7 downto 0));
end component;
component vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end component;
begin
frameBuffer : ram2k_8 port map ( clk => clk, --CLK
we => we,
ra => ra,
wa => wa,
wd => wd,
rd => vgaData,
pixelVal => pixelVal);
vga_out : VGAdrive port map ( clock => vgaclk,
red => red,
green => green,
blue => blue,
row => row,
column => column,
Rout => Rout,
Gout => Gout,
Bout => Bout,
H => HS,
V => VS );
-- read signals from fb
ra <= row (8 downto 4) & column(9 downto 4);
red <= vgaData(7 downto 5);
green <= vgaData(4 downto 2);
blue <= vgaData(1 downto 0);
pixelData <= pixelVal; -- returns the pixel data in the framebuffer at address 'wa'
vga_clk : vga_clk_div port map ( clk => CLK, clkout => vgaclk);
end Behavioral;
| mit | d8560bbe1396b6c5b0dae842198410c5 | 0.466037 | 4.40991 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_MUX5_0/sim/design_1_MUX5_0.vhd | 2 | 5,676 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: raphael-frey:user:axis_multiplexer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_MUX5_0 IS
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END design_1_MUX5_0;
ARCHITECTURE design_1_MUX5_0_arch OF design_1_MUX5_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX5_0_arch: ARCHITECTURE IS "yes";
COMPONENT multiplexer IS
GENERIC (
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_NUM_SI_SLOTS : INTEGER
);
PORT (
ClkxCI : IN STD_LOGIC;
RstxRBI : IN STD_LOGIC;
SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
Valid0xSI : IN STD_LOGIC;
Valid1xSI : IN STD_LOGIC;
Valid2xSI : IN STD_LOGIC;
Valid3xSI : IN STD_LOGIC;
Ready0xSO : OUT STD_LOGIC;
Ready1xSO : OUT STD_LOGIC;
Ready2xSO : OUT STD_LOGIC;
Ready3xSO : OUT STD_LOGIC;
DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
ValidxSO : OUT STD_LOGIC;
ReadyxSI : IN STD_LOGIC
);
END COMPONENT multiplexer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY";
BEGIN
U0 : multiplexer
GENERIC MAP (
C_AXIS_TDATA_WIDTH => 24,
C_AXIS_NUM_SI_SLOTS => 2
)
PORT MAP (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
SelectxDI => SelectxDI,
Data0xDI => Data0xDI,
Data1xDI => Data1xDI,
Data2xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
Valid0xSI => Valid0xSI,
Valid1xSI => Valid1xSI,
Valid2xSI => '0',
Valid3xSI => '0',
Ready0xSO => Ready0xSO,
Ready1xSO => Ready1xSO,
DataxDO => DataxDO,
ValidxSO => ValidxSO,
ReadyxSI => ReadyxSI
);
END design_1_MUX5_0_arch;
| mit | b652d1c84c2ff7c64886917eed3bc617 | 0.708069 | 3.729304 | false | false | false | false |
ErikAndren/SG90-PWM | PWM.vhd | 1 | 3,481 | -- Simple POC that tests the control of the SG90-motors
-- Copyright [email protected] 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity PWM is
generic (
Displays : positive := 8
);
port (
RstN : in bit1;
Clk : in bit1;
--
Button0 : in bit1;
Button1 : in bit1;
--
Display : out word(Displays-1 downto 0);
Segments : out word(8-1 downto 0);
--
ServoPitch : out bit1;
ServoYaw : out bit1
);
end entity;
architecture rtl of PWM is
signal Btn0Deb : bit1;
signal Btn1Deb : bit1;
constant Freq : positive := 50000000;
constant PwmRes : positive := 128;
constant PwmResW : positive := bits(PwmRes);
constant MaxPitch : positive := 40;
signal Pos_N, Pos_D : word(PwmResW-1 downto 0);
signal Data : word(27-1 downto 0);
signal Button0_N, Button0_D : bit1;
signal Button1_N, Button1_D : bit1;
signal Clk64kHz : bit1;
signal Clk1Hz : bit1;
signal OldClk1Hz_D, OldClk1Hz_N : bit1;
signal Rising_N, Rising_D : bit1;
begin
Btn0Debouncer : entity work.Debounce
port map (
Clk => Clk,
x => Button0,
DBx => Btn0Deb
);
Btn1Debouncer : entity work.Debounce
port map (
Clk => Clk,
x => Button1,
DBx => Btn1Deb
);
process (Clk, RstN)
begin
if RstN = '0' then
Pos_D <= (others => '0');
Button0_D <= '0';
Button1_D <= '0';
OldClk1Hz_D <= '0';
Rising_D <= '1';
elsif rising_edge(Clk) then
Pos_D <= Pos_N;
Button0_D <= Button0_N;
Button1_D <= Button1_N;
OldClk1Hz_D <= OldClk1Hz_N;
Rising_D <= Rising_N;
end if;
end process;
Button0_N <= Btn0Deb;
Button1_N <= Btn1Deb;
OldClk1Hz_N <= Clk1Hz;
process (Clk1Hz, Pos_D, OldClk1Hz_D)
begin
Pos_N <= Pos_D;
Rising_N <= Rising_D;
if Pos_D = MaxPitch then
Rising_N <= '0';
Pos_N <= Pos_D - 1;
elsif Pos_D = 0 then
Rising_N <= '1';
Pos_N <= Pos_D + 1;
elsif (Clk1Hz = '1' and OldClk1Hz_D = '0') then
if Rising_D = '1' then
Pos_N <= Pos_D + 1;
--Pos_N <= conv_word(MaxPitch, Pos_N'length);
else
Pos_N <= Pos_D - 1;
--Pos_N <= (others => '0');
end if;
end if;
end process;
Clk1HzGen : entity work.ClkDiv
generic map (
SourceFreq => Freq,
SinkFreq => 1
)
port map (
clk => Clk,
Reset => RstN,
Clk_out => Clk1Hz
);
Data <= xt0(Pos_D, Data'length);
BcdDispay : entity work.BcdDisp
generic map (
Displays => 8,
Freq => Freq
)
port map (
Clk => Clk,
RstN => RstN,
Data => Data,
--
Segments => Segments,
Display => Display
);
Clk64kHzGen : entity work.ClkDiv
generic map (
SourceFreq => Freq,
SinkFreq => 32000
)
port map (
clk => Clk,
Reset => RstN,
Clk_out => Clk64kHz
);
PitchServo : entity work.Servo_pwm
port map (
Clk => Clk64kHz,
RstN => RstN,
Pos => Pos_D,
servo => ServoPitch
);
YawServo : entity work.Servo_pwm
port map (
Clk => Clk64kHz,
RstN => RstN,
Pos => Pos_D,
servo => ServoYaw
);
end architecture rtl;
| gpl-2.0 | 49b84635ebdc1609b597d5c3244ee4c9 | 0.521976 | 3.220167 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 5 | 142,613 | `protect begin_protected
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`protect end_protected
| mit | a0679db8b32be3dbeab74c3ee2c0489b | 0.952837 | 1.831659 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/cache/cachetest_KC705_Vivado.vhdl | 1 | 13,007 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Martin Zabel
--
-- Module: Test cache_mem on Xilinx KC705 board.
--
-- Description:
-- ------------------------------------
-- Test cache_mem on Xilinx KC705 board using the Xilinx Memory Controller
-- (MIG).
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library poc;
use poc.utils.all;
entity cachetest_KC705 is
port (
KC705_SystemClock_200MHz_p : in std_logic;
KC705_SystemClock_200MHz_n : in std_logic;
KC705_GPIO_LED : out std_logic_vector(7 downto 0);
ddr3_dq : inout std_logic_vector(64-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(8-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(8-1 downto 0);
ddr3_addr : out std_logic_vector(14-1 downto 0);
ddr3_ba : out std_logic_vector(3-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(1-1 downto 0);
ddr3_ck_n : out std_logic_vector(1-1 downto 0);
ddr3_cke : out std_logic_vector(1-1 downto 0);
ddr3_cs_n : out std_logic_vector(1*1-1 downto 0);
ddr3_dm : out std_logic_vector(8-1 downto 0);
ddr3_odt : out std_logic_vector(1-1 downto 0));
end entity cachetest_KC705;
architecture rtl of cachetest_KC705 is
signal sysclk_unbuf : std_logic;
signal refclk : std_logic;
signal memtest_status : std_logic_vector(2 downto 0);
-- Inputs / Outputs of MIG core
signal sys_rst : std_logic;
signal app_addr : std_logic_vector(28-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector((4*2*64)-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector((4*2*64)/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector((4*2*64)-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal ui_clk : std_logic;
signal ui_clk_sync_rst : std_logic;
signal init_calib_complete : std_logic;
-- component declaration required for Xilinx Vivado
component mig_KC705_MT8JTF12864HZ_1G6
port (
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(511 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(63 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(511 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
-- Reference Clock Ports
clk_ref_i : in std_logic;
sys_rst : in std_logic
);
end component mig_KC705_MT8JTF12864HZ_1G6;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Clock Buffer
-----------------------------------------------------------------------------
-- This system clock is used two-fold:
--
-- 1) It is used as the reference / system clock for the memory controllers
-- (MIG). There it feeds only PLLs, so that, dedicated routing can be
-- used and no BUFG is required.
--
-- 2) It is also used for the IDELAYCTRL and temperature monitor logic.
-- This requires a BUFG, but could also be driven by another 200 MHz
-- clock source. If this other clock is not free-runnning, then
-- IDELAYCTRL and the temperature monitor must be hold in reset until
-- this other clock is stable.
sysclk_ibuf : ibufds
port map (
I => KC705_SystemClock_200MHz_p,
IB => KC705_SystemClock_200MHz_n,
O => sysclk_unbuf); -- sufficient for memory controllers only.
refclk_bufg : bufg
port map (
I => sysclk_unbuf,
O => refclk); -- buffered 200 MHz reference clock
-----------------------------------------------------------------------------
-- MemoryTester
-----------------------------------------------------------------------------
MemoryTester : block
-- The smallest addressable unit of the "app" interface has DQ_BITS bits.
-- The smallest addressable unit of the "mem" interface has MEM_DATA_BITS bits.
-- The burst length is then MEM_DATA_BITS / DQ_BITS.
constant MEM_DATA_BITS : positive := 512;
constant DQ_BITS : positive := 64;
constant BL_BITS : natural := log2ceil(MEM_DATA_BITS / DQ_BITS);
constant MEM_ADDR_BITS : natural :=
ite(SIMULATION,
17-3, -- 128 KByte / 8 = 16 KByte per chip (on SoDIMM)
30-3) -- 1 GB / 8 = 128 MB per chip (on SoDIMM)
-BL_BITS;
constant CPU_DATA_BITS : positive := 32; -- supported values: 8, 16, 32, 64, 128
constant CPU_ADDR_BITS : positive := log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS;
signal cpu_rdy : std_logic;
signal cpu_req : std_logic;
signal cpu_write : std_logic;
signal cpu_addr : unsigned(CPU_ADDR_BITS-1 downto 0);
signal cpu_wdata : std_logic_vector(CPU_DATA_BITS-1 downto 0);
signal cpu_rstb : std_logic;
signal cpu_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0);
signal mem_rdy : std_logic;
signal mem_rstb : std_logic;
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(MEM_ADDR_BITS-1 downto 0);
signal mem_wdata : std_logic_vector(MEM_DATA_BITS-1 downto 0);
signal mem_wmask : std_logic_vector(MEM_DATA_BITS/8-1 downto 0);
signal mem_rdata : std_logic_vector(MEM_DATA_BITS-1 downto 0);
begin -- block MemoryTester
fsm : entity work.memtest_fsm
generic map (
A_BITS => CPU_ADDR_BITS,
D_BITS => CPU_DATA_BITS)
port map (
clk => ui_clk,
rst => ui_clk_sync_rst,
mem_rdy => cpu_rdy,
mem_rstb => cpu_rstb,
mem_rdata => cpu_rdata,
mem_req => cpu_req,
mem_write => cpu_write,
mem_addr => cpu_addr,
mem_wdata => cpu_wdata,
status => memtest_status(2 downto 0));
cache : entity poc.cache_mem
generic map (
REPLACEMENT_POLICY => "LRU",
CACHE_LINES => 1024, -- 64 KiB cache / 512 bit per cache line
ASSOCIATIVITY => 1,
CPU_DATA_BITS => CPU_DATA_BITS,
MEM_ADDR_BITS => MEM_ADDR_BITS,
MEM_DATA_BITS => MEM_DATA_BITS,
OUTSTANDING_REQ => 2)
port map (
clk => ui_clk,
rst => ui_clk_sync_rst,
cpu_req => cpu_req,
cpu_write => cpu_write,
cpu_addr => cpu_addr,
cpu_wdata => cpu_wdata,
cpu_rdy => cpu_rdy,
cpu_rstb => cpu_rstb,
cpu_rdata => cpu_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
mem_wmask => mem_wmask,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata);
adapter : entity poc.ddr3_mem2mig_adapter_Series7
generic map (
D_BITS => MEM_DATA_BITS,
DQ_BITS => DQ_BITS,
MEM_A_BITS => MEM_ADDR_BITS,
APP_A_BITS => app_addr'length)
port map (
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
mem_wmask => mem_wmask,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
init_calib_complete => init_calib_complete,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren);
end block MemoryTester;
-----------------------------------------------------------------------------
-- Memory Controller Instantiation
-----------------------------------------------------------------------------
-- Apply an initial reset pulse. Required for IDELAYCTRL.
sys_rst_pulse : FD
generic map (
INIT => '1')
port map (
D => '0',
C => refclk,
Q => sys_rst);
mig : mig_KC705_MT8JTF12864HZ_1G6
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
sys_clk_i => sysclk_unbuf,
clk_ref_i => refclk,
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0', -- reserved
app_sr_active => open,
app_ref_req => '0', -- unused
app_ref_ack => open,
app_zq_req => '0', -- unused
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => init_calib_complete,
sys_rst => sys_rst); -- active high
-----------------------------------------------------------------------------
-- Status Output
-----------------------------------------------------------------------------
KC705_GPIO_LED(7) <= ui_clk_sync_rst;
KC705_GPIO_LED(6) <= '0';
KC705_GPIO_LED(5) <= '0';
KC705_GPIO_LED(4) <= '0';
KC705_GPIO_LED(3) <= init_calib_complete;
KC705_GPIO_LED(2 downto 0) <= memtest_status;
end architecture rtl;
| apache-2.0 | 59375060ed2e5609c433104c40a7ff13 | 0.534251 | 3.137241 | false | false | false | false |
marcoep/MusicBoxNano | hdl/MusicBoxClocking.vhd | 1 | 4,468 | -------------------------------------------------------------------------------
-- Title : Music Box Nano - Clocking
-- Project :
-------------------------------------------------------------------------------
-- File : MusicBoxClocking.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-28
-- Last update: 2016-07-28
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Gathers all clocking and reset resources for the Music Box Nano
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-28 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MusicBoxClocking is
port (
CLOCK_50 : in std_logic;
RESET_RI : in std_logic;
ClkSystem_CO : out std_logic;
ClkPWM_CO : out std_logic;
ResetSystem_SO : out std_logic;
ResetPWM_SO : out std_logic;
FreqInt_SO : out std_logic;
KeyInt_SO : out std_logic);
end entity MusicBoxClocking;
architecture RTL of MusicBoxClocking is
constant KEYFREQDIV : integer := 9; -- divides the frequency wave to the
-- key-speed wave
signal Clk5M_C : std_logic := '0';
signal Clk64M_C : std_logic := '0';
signal Clk128k_C : std_logic := '0';
signal ResetSystem_S : std_logic := '0';
signal ResetPWM_S : std_logic := '0';
signal PLLLocked_S : std_logic := '0';
signal FreqWave_SN, FreqWave_SP : std_logic := '0';
signal FreqEdgeDet_S : std_logic;
signal ClkDivider_D : unsigned(KEYFREQDIV-1 downto 0) := (others => '0');
signal KeyWave_SN, KeyWave_SP : std_logic := '0';
signal KeyEdgeDet_S : std_logic := '0';
begin -- architecture RTL
-- clock generator PLL from 50MHz input clock
ClocksPLL_i : entity work.ClocksPLL
port map (
areset => RESET_RI,
inclk0 => CLOCK_50,
c0 => Clk5M_C,
c1 => Clk64M_C,
c2 => Clk128k_C,
locked => PLLLocked_S);
-- clock outputs
ClkSystem_CO <= Clk5M_C;
ClkPWM_CO <= Clk64M_C;
-- reset synchronizer for System Clock
ResetSync_Sys_i : entity work.ResetSync
port map (
Clk_CI => Clk5M_C,
ClkStable_RI => PLLLocked_S,
OtherReset_RI => RESET_RI,
SyncReset_SO => ResetSystem_S);
ResetSystem_SO <= ResetSystem_S;
-- reset sync for pwm clock
ResetSync_pwm_i : entity work.ResetSync
port map (
Clk_CI => Clk64M_C,
ClkStable_RI => PLLLocked_S,
OtherReset_RI => RESET_RI,
SyncReset_SO => ResetPWM_S);
ResetPWM_SO <= ResetPWM_S;
-----------------------------------------------------------------------------
-- Generation of Interrupts
-----------------------------------------------------------------------------
-- frequency wave generator
CrossClockDomain_Freq_i : entity work.CrossClockDomain
port map (
Clk_CI => Clk5M_C,
AsyncIn_SI => Clk128k_C,
SyncOut_SO => FreqWave_SN);
clk_divider : process (Clk128k_C) is
begin -- process clk_divider
if Clk128k_C'event and Clk128k_C = '1' then -- rising clock edge
ClkDivider_D <= ClkDivider_D + 1;
end if;
end process clk_divider;
CrossClockDomain_Key_i : entity work.CrossClockDomain
port map (
Clk_CI => Clk5M_C,
AsyncIn_SI => ClkDivider_D(KEYFREQDIV-1),
SyncOut_SO => KeyWave_SN);
-- edge detector flipflops
edge_det : process (Clk5M_C) is
begin -- process freq_edge_det
if Clk5M_C'event and Clk5M_C = '1' then -- rising clock edge
if ResetSystem_S = '1' then -- synchronous reset (active high)
FreqWave_SP <= '0';
FreqInt_SO <= '0';
KeyWave_SP <= '0';
KeyInt_SO <= '0';
else
FreqWave_SP <= FreqWave_SN;
FreqInt_SO <= FreqWave_SN and not(FreqWave_SP);
KeyWave_SP <= KeyWave_SN;
KeyInt_SO <= KeyWave_SN and not(KeyWave_SP);
end if;
end if;
end process edge_det;
end architecture RTL;
| gpl-3.0 | c5036ee3da0175a24a712dd7a3537082 | 0.506043 | 3.845095 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/cache/cachetest_de0.vhdl | 1 | 8,052 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory Controller Test for Altera DE0 Board
--
-- Description:
-- ------------------------------------
-- Top-Level of Memory Controller Test for Altera DE0 Board
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.fifo.all;
entity cachetest_de0 is
port (
clk_in : in std_logic;
btn : in std_logic_vector(2 downto 2);
led : out std_logic_vector(9 downto 0);
sd_ck : out std_logic;
sd_cke : out std_logic;
sd_cs : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sd_we : out std_logic;
sd_ba : out std_logic_vector(1 downto 0);
sd_a : out std_logic_vector(11 downto 0);
sd_ldm : out std_logic;
sd_udm : out std_logic;
sd_dq : inout std_logic_vector(15 downto 0));
end cachetest_de0;
architecture rtl of cachetest_de0 is
signal clk_sys : std_logic;
signal clk_mem : std_logic;
signal clk_memout : std_logic;
signal rst_sys : std_logic;
signal rst_mem : std_logic;
signal locked : std_logic;
signal clk_tb : std_logic;
signal rst_tb : std_logic;
signal cf_put : std_logic;
signal cf_full : std_logic;
signal cf_din : std_logic_vector(22 downto 0);
signal cf_dout : std_logic_vector(22 downto 0);
signal cf_valid : std_logic;
signal cf_got : std_logic;
signal wf_put : std_logic;
signal wf_full : std_logic;
signal wf_din : std_logic_vector(15 downto 0);
signal wf_dout : std_logic_vector(15 downto 0);
signal wf_valid : std_logic;
signal wf_got : std_logic;
signal cpu_rdy : std_logic;
signal cpu_rstb : std_logic;
signal cpu_rdata : std_logic_vector(15 downto 0);
signal cpu_req : std_logic;
signal cpu_write : std_logic;
signal cpu_addr : unsigned(21 downto 0);
signal cpu_wdata : std_logic_vector(15 downto 0);
signal mem_rdy : std_logic;
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(15 downto 0);
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(21 downto 0);
signal mem_wdata : std_logic_vector(15 downto 0);
signal fsm_status : std_logic_vector(2 downto 0);
signal rf_put : std_logic;
signal rf_din : std_logic_vector(15 downto 0);
begin -- rtl
pll: entity work.memtest_de0_pll
port map (
inclk0 => clk_in,
c0 => clk_sys,
c1 => clk_mem,
c2 => clk_memout,
locked => locked);
rst_sync : block
signal do_rst : std_logic;
signal rst_sys_r : std_logic_vector(4 downto 0);
signal rst_mem_r : std_logic_vector(4 downto 0);
begin -- block clockgen
-- reset synchronizer
do_rst <= not locked or not btn(2);
rst_sys_r <= rst_sys_r(rst_sys_r'left-1 downto 0) & do_rst
when rising_edge(clk_sys);
rst_mem_r <= rst_mem_r(rst_mem_r'left-1 downto 0) & do_rst
when rising_edge(clk_mem);
rst_sys <= rst_sys_r(rst_sys_r'left);
rst_mem <= rst_mem_r(rst_mem_r'left);
end block rst_sync;
-- Testbench clock selection
-- Also update chipscope configuration.
-- clk_tb <= clk_mem;
-- rst_tb <= rst_mem;
clk_tb <= clk_sys;
rst_tb <= rst_sys;
-- uses default configuration, see entity declaration
mem_ctrl: entity poc.sdram_ctrl_de0
generic map (
CLK_PERIOD => 7.5,
CL => 2,
BL => 1)
port map (
clk => clk_mem,
clkout => clk_memout,
rst => rst_mem,
user_cmd_valid => cf_valid,
user_wdata_valid => wf_valid,
user_write => cf_dout(cf_dout'left),
user_addr => cf_dout(cf_dout'left-1 downto 0),
user_wdata => wf_dout,
user_got_cmd => cf_got,
user_got_wdata => wf_got,
user_rdata => rf_din,
user_rstb => rf_put,
sd_ck => sd_ck,
sd_cke => sd_cke,
sd_cs => sd_cs,
sd_ras => sd_ras,
sd_cas => sd_cas,
sd_we => sd_we,
sd_ba => sd_ba,
sd_a => sd_a,
sd_dq => sd_dq);
sd_ldm <= '0';
sd_udm <= '0';
cmd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 23,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => cf_put,
din => cf_din,
full => cf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => cf_got,
valid => cf_valid,
dout => cf_dout);
wr_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 16,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => wf_put,
din => wf_din,
full => wf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => wf_got,
valid => wf_valid,
dout => wf_dout);
-- The size fo this FIFO depends on the latency between write and read
-- clock domain
rd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 16,
MIN_DEPTH => 8)
port map (
clk_wr => clk_mem,
rst_wr => rst_mem,
put => rf_put,
din => rf_din,
full => open, -- can't stall
clk_rd => clk_tb,
rst_rd => rst_tb,
got => mem_rstb,
valid => mem_rstb,
dout => mem_rdata);
cache: entity poc.cache_mem
generic map (
REPLACEMENT_POLICY => "LRU",
CACHE_LINES => 512, -- 1 KiB cache / 16 bit per cache line
ASSOCIATIVITY => 1,
CPU_DATA_BITS => 16, -- must match MEM_DATA_BITS because memory
-- controller has no write-mask
MEM_ADDR_BITS => 22,
MEM_DATA_BITS => 16,
OUTSTANDING_REQ => 2)
port map (
clk => clk_tb,
rst => rst_tb,
cpu_req => cpu_req,
cpu_write => cpu_write,
cpu_addr => cpu_addr,
cpu_wdata => cpu_wdata,
cpu_rdy => cpu_rdy,
cpu_rstb => cpu_rstb,
cpu_rdata => cpu_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
mem_wmask => open,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata);
fsm: entity work.memtest_fsm
generic map (
A_BITS => 22,
D_BITS => 16)
port map (
clk => clk_tb,
rst => rst_tb,
mem_rdy => cpu_rdy,
mem_rstb => cpu_rstb,
mem_rdata => cpu_rdata,
mem_req => cpu_req,
mem_write => cpu_write,
mem_addr => cpu_addr,
mem_wdata => cpu_wdata,
status => fsm_status);
-- Signal mem_ctrl ready only if both FIFOs are not full.
mem_rdy <= cf_full nor wf_full;
-- Word aligned access to memory.
-- Parallel "put" to both FIFOs.
cf_put <= mem_req and mem_rdy;
wf_put <= mem_req and mem_write and mem_rdy;
cf_din <= mem_write & std_logic_vector(mem_addr);
wf_din <= mem_wdata;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
led(9) <= locked;
led(8 downto 3) <= (others => '0');
led(2 downto 0) <= fsm_status;
end rtl;
| apache-2.0 | 3bc3ddcd2064fca9dca87a4718a7b139 | 0.556508 | 2.924809 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_alu_0_0/RAT_alu_0_0_sim_netlist.vhdl | 2 | 37,199 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:46:25 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_alu_0_0/RAT_alu_0_0_sim_netlist.vhdl
-- Design : RAT_alu_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_alu_0_0_alu is
port (
SUM : out STD_LOGIC_VECTOR ( 7 downto 0 );
Z_FLAG : out STD_LOGIC;
C_FLAG : out STD_LOGIC;
\SUM[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
Sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
\B_6__s_port_]\ : in STD_LOGIC;
\A_0__s_port_\ : in STD_LOGIC;
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
\B_5__s_port_\ : in STD_LOGIC;
\B_4__s_port_\ : in STD_LOGIC;
\B_0__s_port_\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
C_IN : in STD_LOGIC;
\A_7__s_port_\ : in STD_LOGIC;
\B_3__s_port_\ : in STD_LOGIC;
\B_2__s_port_\ : in STD_LOGIC;
\B_1__s_port_\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_alu_0_0_alu : entity is "alu";
end RAT_alu_0_0_alu;
architecture STRUCTURE of RAT_alu_0_0_alu is
signal \A_0__s_net_1\ : STD_LOGIC;
signal \A_7__s_net_1\ : STD_LOGIC;
signal \B_0__s_net_1\ : STD_LOGIC;
signal \B_1__s_net_1\ : STD_LOGIC;
signal \B_2__s_net_1\ : STD_LOGIC;
signal \B_3__s_net_1\ : STD_LOGIC;
signal \B_4__s_net_1\ : STD_LOGIC;
signal \B_5__s_net_1\ : STD_LOGIC;
signal \B_6__s_net_1\ : STD_LOGIC;
signal \^c_flag\ : STD_LOGIC;
signal C_FLAG_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sum\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \SUM[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_5_n_1\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal Z_FLAG_INST_0_i_1_n_0 : STD_LOGIC;
signal Z_FLAG_INST_0_i_2_n_0 : STD_LOGIC;
signal \__0_carry__0_n_0\ : STD_LOGIC;
signal \__0_carry__0_n_1\ : STD_LOGIC;
signal \__0_carry__0_n_2\ : STD_LOGIC;
signal \__0_carry__0_n_3\ : STD_LOGIC;
signal \__0_carry_i_10_n_0\ : STD_LOGIC;
signal \__0_carry_i_11_n_0\ : STD_LOGIC;
signal \__0_carry_i_12_n_0\ : STD_LOGIC;
signal \__0_carry_i_13_n_0\ : STD_LOGIC;
signal \__0_carry_i_1__1_n_0\ : STD_LOGIC;
signal \__0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \__0_carry_i_3_n_0\ : STD_LOGIC;
signal \__0_carry_i_4__0_n_0\ : STD_LOGIC;
signal \__0_carry_i_5__0_n_0\ : STD_LOGIC;
signal \__0_carry_i_5_n_0\ : STD_LOGIC;
signal \__0_carry_i_6__0_n_0\ : STD_LOGIC;
signal \__0_carry_i_6_n_0\ : STD_LOGIC;
signal \__0_carry_i_7__0_n_0\ : STD_LOGIC;
signal \__0_carry_i_7_n_0\ : STD_LOGIC;
signal \__0_carry_i_8_n_0\ : STD_LOGIC;
signal \__0_carry_i_9_n_1\ : STD_LOGIC;
signal \__0_carry_i_9_n_2\ : STD_LOGIC;
signal \__0_carry_i_9_n_3\ : STD_LOGIC;
signal \__0_carry_n_0\ : STD_LOGIC;
signal \__0_carry_n_1\ : STD_LOGIC;
signal \__0_carry_n_2\ : STD_LOGIC;
signal \__0_carry_n_3\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data1 : STD_LOGIC_VECTOR ( 8 downto 0 );
signal data2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \data2__0\ : STD_LOGIC_VECTOR ( 8 to 8 );
signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal minusOp_carry_i_1_n_0 : STD_LOGIC;
signal minusOp_carry_i_2_n_0 : STD_LOGIC;
signal minusOp_carry_i_3_n_0 : STD_LOGIC;
signal minusOp_carry_i_4_n_0 : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 2 );
signal \temp_s__125\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \NLW___0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW___0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \SUM[2]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \SUM[3]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \SUM[4]_INST_0_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \SUM[4]_INST_0_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \SUM[5]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \SUM[6]_INST_0\ : label is "soft_lutpair0";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \__0_carry\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \__0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \__0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
\A_0__s_net_1\ <= \A_0__s_port_\;
\A_7__s_net_1\ <= \A_7__s_port_\;
\B_0__s_net_1\ <= \B_0__s_port_\;
\B_1__s_net_1\ <= \B_1__s_port_\;
\B_2__s_net_1\ <= \B_2__s_port_\;
\B_3__s_net_1\ <= \B_3__s_port_\;
\B_4__s_net_1\ <= \B_4__s_port_\;
\B_5__s_net_1\ <= \B_5__s_port_\;
\B_6__s_net_1\ <= \B_6__s_port_]\;
C_FLAG <= \^c_flag\;
SUM(7 downto 0) <= \^sum\(7 downto 0);
C_FLAG_INST_0: unisim.vcomponents.MUXF7
port map (
I0 => C_FLAG_INST_0_i_1_n_0,
I1 => \A_7__s_net_1\,
O => \^c_flag\,
S => Sel(3)
);
C_FLAG_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"55004D4D55004848"
)
port map (
I0 => Sel(2),
I1 => \data2__0\(8),
I2 => Sel(1),
I3 => data1(8),
I4 => Sel(0),
I5 => CO(0),
O => C_FLAG_INST_0_i_1_n_0
);
\SUM[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \B_0__s_net_1\,
I1 => Sel(3),
I2 => \SUM[0]_INST_0_i_2_n_0\,
I3 => Sel(2),
I4 => \SUM[0]_INST_0_i_3_n_0\,
O => \^sum\(0)
);
\SUM[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(0),
I1 => B(0),
O => \SUM[0]_INST_0_i_10_n_0\
);
\SUM[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(0),
I2 => B(0),
I3 => Sel(0),
I4 => data2(0),
O => \SUM[0]_INST_0_i_2_n_0\
);
\SUM[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(0),
I1 => Sel(1),
I2 => data1(0),
I3 => Sel(0),
I4 => data0(0),
O => \SUM[0]_INST_0_i_3_n_0\
);
\SUM[0]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \SUM[0]_INST_0_i_5_n_0\,
CO(2) => \SUM[0]_INST_0_i_5_n_1\,
CO(1) => \SUM[0]_INST_0_i_5_n_2\,
CO(0) => \SUM[0]_INST_0_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => A(3 downto 0),
O(3 downto 0) => data0(3 downto 0),
S(3) => \SUM[0]_INST_0_i_7_n_0\,
S(2) => \SUM[0]_INST_0_i_8_n_0\,
S(1) => \SUM[0]_INST_0_i_9_n_0\,
S(0) => \SUM[0]_INST_0_i_10_n_0\
);
\SUM[0]_INST_0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(3),
I1 => B(3),
O => \SUM[0]_INST_0_i_7_n_0\
);
\SUM[0]_INST_0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(2),
I1 => B(2),
O => \SUM[0]_INST_0_i_8_n_0\
);
\SUM[0]_INST_0_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(1),
I1 => B(1),
O => \SUM[0]_INST_0_i_9_n_0\
);
\SUM[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => \^sum\(0),
I1 => \temp_s__125\(1),
I2 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(1)
);
\SUM[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EF0"
)
port map (
I0 => \^sum\(0),
I1 => \temp_s__125\(1),
I2 => \temp_s__125\(2),
I3 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(2)
);
\SUM[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FEFF00"
)
port map (
I0 => \temp_s__125\(2),
I1 => \temp_s__125\(1),
I2 => \^sum\(0),
I3 => \temp_s__125\(3),
I4 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(3)
);
\SUM[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001FFFEFFFF0000"
)
port map (
I0 => \temp_s__125\(3),
I1 => \^sum\(0),
I2 => \temp_s__125\(1),
I3 => \temp_s__125\(2),
I4 => \temp_s__125\(4),
I5 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(4)
);
\SUM[4]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => Sel(3),
I1 => \SUM[4]_INST_0_i_4_n_0\,
I2 => \B_3__s_net_1\,
O => \temp_s__125\(3)
);
\SUM[4]_INST_0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(3),
I1 => Sel(1),
I2 => data1(3),
I3 => Sel(0),
I4 => data0(3),
O => \SUM[4]_INST_0_i_10_n_0\
);
\SUM[4]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(3),
I2 => B(3),
I3 => Sel(0),
I4 => data2(3),
O => \SUM[4]_INST_0_i_11_n_0\
);
\SUM[4]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(1),
I1 => Sel(1),
I2 => data1(1),
I3 => Sel(0),
I4 => data0(1),
O => \SUM[4]_INST_0_i_13_n_0\
);
\SUM[4]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(1),
I2 => B(1),
I3 => Sel(0),
I4 => data2(1),
O => \SUM[4]_INST_0_i_14_n_0\
);
\SUM[4]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(2),
I1 => Sel(1),
I2 => data1(2),
I3 => Sel(0),
I4 => data0(2),
O => \SUM[4]_INST_0_i_16_n_0\
);
\SUM[4]_INST_0_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(2),
I2 => B(2),
I3 => Sel(0),
I4 => data2(2),
O => \SUM[4]_INST_0_i_17_n_0\
);
\SUM[4]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => Sel(3),
I1 => \SUM[4]_INST_0_i_6_n_0\,
I2 => \B_1__s_net_1\,
O => \temp_s__125\(1)
);
\SUM[4]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => Sel(3),
I1 => \SUM[4]_INST_0_i_8_n_0\,
I2 => \B_2__s_net_1\,
O => \temp_s__125\(2)
);
\SUM[4]_INST_0_i_4\: unisim.vcomponents.MUXF7
port map (
I0 => \SUM[4]_INST_0_i_10_n_0\,
I1 => \SUM[4]_INST_0_i_11_n_0\,
O => \SUM[4]_INST_0_i_4_n_0\,
S => Sel(2)
);
\SUM[4]_INST_0_i_6\: unisim.vcomponents.MUXF7
port map (
I0 => \SUM[4]_INST_0_i_13_n_0\,
I1 => \SUM[4]_INST_0_i_14_n_0\,
O => \SUM[4]_INST_0_i_6_n_0\,
S => Sel(2)
);
\SUM[4]_INST_0_i_8\: unisim.vcomponents.MUXF7
port map (
I0 => \SUM[4]_INST_0_i_16_n_0\,
I1 => \SUM[4]_INST_0_i_17_n_0\,
O => \SUM[4]_INST_0_i_8_n_0\,
S => Sel(2)
);
\SUM[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4BF0"
)
port map (
I0 => \temp_s__125\(4),
I1 => \SUM[7]_INST_0_i_3_n_0\,
I2 => \temp_s__125\(5),
I3 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(5)
);
\SUM[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FBFF00"
)
port map (
I0 => \temp_s__125\(5),
I1 => \SUM[7]_INST_0_i_3_n_0\,
I2 => \temp_s__125\(4),
I3 => \temp_s__125\(6),
I4 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(6)
);
\SUM[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010FFEFFFFF0000"
)
port map (
I0 => \temp_s__125\(6),
I1 => \temp_s__125\(4),
I2 => \SUM[7]_INST_0_i_3_n_0\,
I3 => \temp_s__125\(5),
I4 => \temp_s__125\(7),
I5 => \SUM[7]_INST_0_i_6_n_0\,
O => \^sum\(7)
);
\SUM[7]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \B_6__s_net_1\,
I1 => Sel(3),
I2 => \SUM[7]_INST_0_i_8_n_0\,
I3 => Sel(2),
I4 => \SUM[7]_INST_0_i_9_n_0\,
O => \temp_s__125\(6)
);
\SUM[7]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(4),
I2 => B(4),
I3 => Sel(0),
I4 => data2(4),
O => \SUM[7]_INST_0_i_11_n_0\
);
\SUM[7]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(4),
I1 => Sel(1),
I2 => data1(4),
I3 => Sel(0),
I4 => data0(4),
O => \SUM[7]_INST_0_i_12_n_0\
);
\SUM[7]_INST_0_i_13\: unisim.vcomponents.MUXF7
port map (
I0 => \SUM[0]_INST_0_i_3_n_0\,
I1 => \SUM[0]_INST_0_i_2_n_0\,
O => \SUM[7]_INST_0_i_13_n_0\,
S => Sel(2)
);
\SUM[7]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(5),
I2 => B(5),
I3 => Sel(0),
I4 => data2(5),
O => \SUM[7]_INST_0_i_15_n_0\
);
\SUM[7]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(5),
I1 => Sel(1),
I2 => data1(5),
I3 => Sel(0),
I4 => data0(5),
O => \SUM[7]_INST_0_i_16_n_0\
);
\SUM[7]_INST_0_i_17\: unisim.vcomponents.MUXF7
port map (
I0 => \SUM[7]_INST_0_i_22_n_0\,
I1 => \SUM[7]_INST_0_i_23_n_0\,
O => \SUM[7]_INST_0_i_17_n_0\,
S => Sel(2)
);
\SUM[7]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \B_4__s_net_1\,
I1 => Sel(3),
I2 => \SUM[7]_INST_0_i_11_n_0\,
I3 => Sel(2),
I4 => \SUM[7]_INST_0_i_12_n_0\,
O => \temp_s__125\(4)
);
\SUM[7]_INST_0_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(7),
I1 => Sel(1),
I2 => data1(7),
I3 => Sel(0),
I4 => data0(7),
O => \SUM[7]_INST_0_i_22_n_0\
);
\SUM[7]_INST_0_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(7),
I2 => B(7),
I3 => Sel(0),
I4 => data2(7),
O => \SUM[7]_INST_0_i_23_n_0\
);
\SUM[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000011101"
)
port map (
I0 => \temp_s__125\(2),
I1 => \temp_s__125\(1),
I2 => \SUM[7]_INST_0_i_13_n_0\,
I3 => Sel(3),
I4 => \B_0__s_net_1\,
I5 => \temp_s__125\(3),
O => \SUM[7]_INST_0_i_3_n_0\
);
\SUM[7]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \B_5__s_net_1\,
I1 => Sel(3),
I2 => \SUM[7]_INST_0_i_15_n_0\,
I3 => Sel(2),
I4 => \SUM[7]_INST_0_i_16_n_0\,
O => \temp_s__125\(5)
);
\SUM[7]_INST_0_i_5\: unisim.vcomponents.MUXF8
port map (
I0 => \SUM[7]_INST_0_i_17_n_0\,
I1 => \A_0__s_net_1\,
O => \temp_s__125\(7),
S => Sel(3)
);
\SUM[7]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => Sel(2),
I1 => Sel(3),
I2 => Sel(1),
I3 => \^c_flag\,
O => \SUM[7]_INST_0_i_6_n_0\
);
\SUM[7]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"68FD68A8"
)
port map (
I0 => Sel(1),
I1 => A(6),
I2 => B(6),
I3 => Sel(0),
I4 => data2(6),
O => \SUM[7]_INST_0_i_8_n_0\
);
\SUM[7]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => data2(6),
I1 => Sel(1),
I2 => data1(6),
I3 => Sel(0),
I4 => data0(6),
O => \SUM[7]_INST_0_i_9_n_0\
);
Z_FLAG_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \temp_s__125\(4),
I1 => \temp_s__125\(5),
I2 => Z_FLAG_INST_0_i_1_n_0,
I3 => Z_FLAG_INST_0_i_2_n_0,
I4 => \^sum\(0),
I5 => \temp_s__125\(1),
O => Z_FLAG
);
Z_FLAG_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000015155550151"
)
port map (
I0 => \temp_s__125\(7),
I1 => \SUM[7]_INST_0_i_9_n_0\,
I2 => Sel(2),
I3 => \SUM[7]_INST_0_i_8_n_0\,
I4 => Sel(3),
I5 => \B_6__s_net_1\,
O => Z_FLAG_INST_0_i_1_n_0
);
Z_FLAG_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \temp_s__125\(2),
I1 => \temp_s__125\(3),
O => Z_FLAG_INST_0_i_2_n_0
);
\__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \__0_carry_n_0\,
CO(2) => \__0_carry_n_1\,
CO(1) => \__0_carry_n_2\,
CO(0) => \__0_carry_n_3\,
CYINIT => '1',
DI(3) => p_0_in(2),
DI(2) => \__0_carry_i_2__0_n_0\,
DI(1) => \__0_carry_i_3_n_0\,
DI(0) => '1',
O(3 downto 0) => data1(3 downto 0),
S(3) => \__0_carry_i_4__0_n_0\,
S(2) => \__0_carry_i_5__0_n_0\,
S(1) => \__0_carry_i_6_n_0\,
S(0) => \__0_carry_i_7_n_0\
);
\__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \__0_carry_n_0\,
CO(3) => \__0_carry__0_n_0\,
CO(2) => \__0_carry__0_n_1\,
CO(1) => \__0_carry__0_n_2\,
CO(0) => \__0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_0_in(6 downto 3),
O(3 downto 0) => data1(7 downto 4),
S(3) => \__0_carry_i_5_n_0\,
S(2) => \__0_carry_i_6__0_n_0\,
S(1) => \__0_carry_i_7__0_n_0\,
S(0) => \__0_carry_i_8_n_0\
);
\__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \__0_carry__0_n_0\,
CO(3 downto 0) => \NLW___0_carry__1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW___0_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => data1(8),
S(3 downto 1) => B"000",
S(0) => \__0_carry_i_1__1_n_0\
);
\__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => data2(2),
I1 => data0(2),
I2 => Sel(1),
O => p_0_in(2)
);
\__0_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(7),
I1 => B(7),
O => \__0_carry_i_10_n_0\
);
\__0_carry_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(6),
I1 => B(6),
O => \__0_carry_i_11_n_0\
);
\__0_carry_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(5),
I1 => B(5),
O => \__0_carry_i_12_n_0\
);
\__0_carry_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => A(4),
I1 => B(4),
O => \__0_carry_i_13_n_0\
);
\__0_carry_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => data2(6),
I1 => data0(6),
I2 => Sel(1),
O => p_0_in(6)
);
\__0_carry_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAC53A35"
)
port map (
I0 => data0(7),
I1 => data2(7),
I2 => Sel(1),
I3 => CO(0),
I4 => \data2__0\(8),
O => \__0_carry_i_1__1_n_0\
);
\__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => data2(5),
I1 => data0(5),
I2 => Sel(1),
O => p_0_in(5)
);
\__0_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => data0(1),
I1 => Sel(1),
O => \__0_carry_i_2__0_n_0\
);
\__0_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"CFA0"
)
port map (
I0 => data0(0),
I1 => data2(0),
I2 => C_IN,
I3 => Sel(1),
O => \__0_carry_i_3_n_0\
);
\__0_carry_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => data2(4),
I1 => data0(4),
I2 => Sel(1),
O => p_0_in(4)
);
\__0_carry_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => data2(3),
I1 => data0(3),
I2 => Sel(1),
O => p_0_in(3)
);
\__0_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAC53A35"
)
port map (
I0 => data0(2),
I1 => data2(2),
I2 => Sel(1),
I3 => data0(3),
I4 => data2(3),
O => \__0_carry_i_4__0_n_0\
);
\__0_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAC53A35"
)
port map (
I0 => data0(6),
I1 => data2(6),
I2 => Sel(1),
I3 => data0(7),
I4 => data2(7),
O => \__0_carry_i_5_n_0\
);
\__0_carry_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"21ED"
)
port map (
I0 => data0(1),
I1 => Sel(1),
I2 => data0(2),
I3 => data2(2),
O => \__0_carry_i_5__0_n_0\
);
\__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"22DD22DDA0A05F5F"
)
port map (
I0 => C_IN,
I1 => data2(0),
I2 => data0(0),
I3 => data2(1),
I4 => data0(1),
I5 => Sel(1),
O => \__0_carry_i_6_n_0\
);
\__0_carry_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAC53A35"
)
port map (
I0 => data0(5),
I1 => data2(5),
I2 => Sel(1),
I3 => data0(6),
I4 => data2(6),
O => \__0_carry_i_6__0_n_0\
);
\__0_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"AC53"
)
port map (
I0 => data2(0),
I1 => data0(0),
I2 => Sel(1),
I3 => C_IN,
O => \__0_carry_i_7_n_0\
);
\__0_carry_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAC53A35"
)
port map (
I0 => data0(4),
I1 => data2(4),
I2 => Sel(1),
I3 => data0(5),
I4 => data2(5),
O => \__0_carry_i_7__0_n_0\
);
\__0_carry_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"CAC53A35"
)
port map (
I0 => data0(3),
I1 => data2(3),
I2 => Sel(1),
I3 => data0(4),
I4 => data2(4),
O => \__0_carry_i_8_n_0\
);
\__0_carry_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \SUM[0]_INST_0_i_5_n_0\,
CO(3) => \SUM[7]\(0),
CO(2) => \__0_carry_i_9_n_1\,
CO(1) => \__0_carry_i_9_n_2\,
CO(0) => \__0_carry_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => A(7 downto 4),
O(3 downto 0) => data0(7 downto 4),
S(3) => \__0_carry_i_10_n_0\,
S(2) => \__0_carry_i_11_n_0\,
S(1) => \__0_carry_i_12_n_0\,
S(0) => \__0_carry_i_13_n_0\
);
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => A(3 downto 0),
O(3 downto 0) => data2(3 downto 0),
S(3) => minusOp_carry_i_1_n_0,
S(2) => minusOp_carry_i_2_n_0,
S(1) => minusOp_carry_i_3_n_0,
S(0) => minusOp_carry_i_4_n_0
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => A(7 downto 4),
O(3 downto 0) => data2(7 downto 4),
S(3) => \minusOp_carry__0_i_1_n_0\,
S(2) => \minusOp_carry__0_i_2_n_0\,
S(1) => \minusOp_carry__0_i_3_n_0\,
S(0) => \minusOp_carry__0_i_4_n_0\
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(7),
I1 => A(7),
O => \minusOp_carry__0_i_1_n_0\
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(6),
I1 => A(6),
O => \minusOp_carry__0_i_2_n_0\
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(5),
I1 => A(5),
O => \minusOp_carry__0_i_3_n_0\
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(4),
I1 => A(4),
O => \minusOp_carry__0_i_4_n_0\
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 0) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \data2__0\(8),
S(3 downto 0) => B"0001"
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(3),
I1 => A(3),
O => minusOp_carry_i_1_n_0
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(2),
I1 => A(2),
O => minusOp_carry_i_2_n_0
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(1),
I1 => A(1),
O => minusOp_carry_i_3_n_0
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => B(0),
I1 => A(0),
O => minusOp_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_alu_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C_IN : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
SUM : out STD_LOGIC_VECTOR ( 7 downto 0 );
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_alu_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_alu_0_0 : entity is "RAT_alu_0_0,alu,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_alu_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_alu_0_0 : entity is "alu,Vivado 2016.4";
end RAT_alu_0_0;
architecture STRUCTURE of RAT_alu_0_0 is
signal C_FLAG_INST_0_i_2_n_0 : STD_LOGIC;
signal \SUM[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \SUM[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \SUM[4]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \SUM[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 8 to 8 );
signal NLW_C_FLAG_INST_0_i_3_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_C_FLAG_INST_0_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
C_FLAG_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"5D480848"
)
port map (
I0 => Sel(2),
I1 => A(0),
I2 => Sel(1),
I3 => Sel(0),
I4 => A(7),
O => C_FLAG_INST_0_i_2_n_0
);
C_FLAG_INST_0_i_3: unisim.vcomponents.CARRY4
port map (
CI => U0_n_10,
CO(3 downto 1) => NLW_C_FLAG_INST_0_i_3_CO_UNCONNECTED(3 downto 1),
CO(0) => data0(8),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_C_FLAG_INST_0_i_3_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => B"0001"
);
\SUM[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(0),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(1),
I4 => Sel(2),
I5 => \SUM[0]_INST_0_i_4_n_0\,
O => \SUM[0]_INST_0_i_1_n_0\
);
\SUM[0]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => A(7),
I1 => A(1),
I2 => Sel(1),
I3 => C_IN,
I4 => Sel(0),
I5 => \SUM[0]_INST_0_i_6_n_0\,
O => \SUM[0]_INST_0_i_4_n_0\
);
\SUM[0]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => A(0),
I1 => B(0),
O => \SUM[0]_INST_0_i_6_n_0\
);
\SUM[4]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => A(4),
I1 => Sel(1),
I2 => A(2),
I3 => Sel(0),
I4 => A(3),
I5 => B(3),
O => \SUM[4]_INST_0_i_12_n_0\
);
\SUM[4]_INST_0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => A(2),
I1 => Sel(1),
I2 => A(0),
I3 => Sel(0),
I4 => A(1),
I5 => B(1),
O => \SUM[4]_INST_0_i_15_n_0\
);
\SUM[4]_INST_0_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => A(3),
I1 => Sel(1),
I2 => A(1),
I3 => Sel(0),
I4 => A(2),
I5 => B(2),
O => \SUM[4]_INST_0_i_18_n_0\
);
\SUM[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(3),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(4),
I4 => Sel(2),
I5 => \SUM[4]_INST_0_i_12_n_0\,
O => \SUM[4]_INST_0_i_5_n_0\
);
\SUM[4]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(1),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(2),
I4 => Sel(2),
I5 => \SUM[4]_INST_0_i_15_n_0\,
O => \SUM[4]_INST_0_i_7_n_0\
);
\SUM[4]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(2),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(3),
I4 => Sel(2),
I5 => \SUM[4]_INST_0_i_18_n_0\,
O => \SUM[4]_INST_0_i_9_n_0\
);
\SUM[7]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(4),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(5),
I4 => Sel(2),
I5 => \SUM[7]_INST_0_i_20_n_0\,
O => \SUM[7]_INST_0_i_10_n_0\
);
\SUM[7]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(5),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(6),
I4 => Sel(2),
I5 => \SUM[7]_INST_0_i_21_n_0\,
O => \SUM[7]_INST_0_i_14_n_0\
);
\SUM[7]_INST_0_i_18\: unisim.vcomponents.MUXF7
port map (
I0 => \SUM[7]_INST_0_i_24_n_0\,
I1 => \SUM[7]_INST_0_i_25_n_0\,
O => \SUM[7]_INST_0_i_18_n_0\,
S => Sel(2)
);
\SUM[7]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => A(7),
I1 => Sel(1),
I2 => A(5),
I3 => Sel(0),
I4 => A(6),
I5 => B(6),
O => \SUM[7]_INST_0_i_19_n_0\
);
\SUM[7]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => A(5),
I1 => Sel(1),
I2 => A(3),
I3 => Sel(0),
I4 => A(4),
I5 => B(4),
O => \SUM[7]_INST_0_i_20_n_0\
);
\SUM[7]_INST_0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => A(6),
I1 => Sel(1),
I2 => A(4),
I3 => Sel(0),
I4 => A(5),
I5 => B(5),
O => \SUM[7]_INST_0_i_21_n_0\
);
\SUM[7]_INST_0_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0BBF088F088F088"
)
port map (
I0 => C_IN,
I1 => Sel(1),
I2 => A(6),
I3 => Sel(0),
I4 => A(7),
I5 => B(7),
O => \SUM[7]_INST_0_i_24_n_0\
);
\SUM[7]_INST_0_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => B(7),
I1 => Sel(1),
I2 => A(7),
I3 => Sel(0),
I4 => A(0),
O => \SUM[7]_INST_0_i_25_n_0\
);
\SUM[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F20FFFF2F200000"
)
port map (
I0 => B(6),
I1 => Sel(0),
I2 => Sel(1),
I3 => A(7),
I4 => Sel(2),
I5 => \SUM[7]_INST_0_i_19_n_0\,
O => \SUM[7]_INST_0_i_7_n_0\
);
U0: entity work.RAT_alu_0_0_alu
port map (
A(7 downto 0) => A(7 downto 0),
\A_0__s_port_\ => \SUM[7]_INST_0_i_18_n_0\,
\A_7__s_port_\ => C_FLAG_INST_0_i_2_n_0,
B(7 downto 0) => B(7 downto 0),
\B_0__s_port_\ => \SUM[0]_INST_0_i_1_n_0\,
\B_1__s_port_\ => \SUM[4]_INST_0_i_7_n_0\,
\B_2__s_port_\ => \SUM[4]_INST_0_i_9_n_0\,
\B_3__s_port_\ => \SUM[4]_INST_0_i_5_n_0\,
\B_4__s_port_\ => \SUM[7]_INST_0_i_10_n_0\,
\B_5__s_port_\ => \SUM[7]_INST_0_i_14_n_0\,
\B_6__s_port_]\ => \SUM[7]_INST_0_i_7_n_0\,
CO(0) => data0(8),
C_FLAG => C_FLAG,
C_IN => C_IN,
SUM(7 downto 0) => SUM(7 downto 0),
\SUM[7]\(0) => U0_n_10,
Sel(3 downto 0) => Sel(3 downto 0),
Z_FLAG => Z_FLAG
);
end STRUCTURE;
| mit | a2ce5a82f87809e640c894130eb11e50 | 0.475658 | 2.430831 | false | false | false | false |
stefanct/aua | hw/if/src/if.vhd | 1 | 3,243 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.aua_types.all;
entity ent_if is
generic (
INIT_VECTOR : pc_t
);
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register outputs
opcode_out : out opcode_t;
dest_out : out reg_t;
pc_out : out pc_t;
pcnxt_out : out pc_t;
rega_out : out reg_t;
regb_out : out reg_t;
imm_out : out std_logic_vector(7 downto 0);
-- asynchron register outputs
async_rega : out reg_t;
async_regb : out reg_t;
-- branches (from ID)
pc_in : in pc_t;
branch : in std_logic;
-- cache
instr_addr : out word_t;
instr_valid : in std_logic;
instr_data : in word_t;
-- interlock
lock : in std_logic
);
end ent_if;
architecture sat1 of ent_if is
signal opcode_nxt : opcode_t;
signal dest_nxt : reg_t;
signal rega_nxt : reg_t;
signal regb_nxt : reg_t;
signal imm_nxt : std_logic_vector(7 downto 0);
signal pc_nxt : pc_t;
signal opcode : opcode_t;
signal dest : reg_t;
signal rega : reg_t;
signal regb : reg_t;
signal imm : std_logic_vector(7 downto 0);
signal pc : pc_t;
signal pc_id : pc_t;
begin
instr_addr <= word_t(pc);
opcode_out <= opcode;
dest_out <= dest;
rega_out <= rega;
regb_out <= regb;
imm_out <= imm;
pc_out <= pc_id;
pcnxt_out <= pc;
instr_dec: process(reset, instr_data, branch, instr_valid)
begin
if branch = '0' and instr_valid = '1' then
opcode_nxt <= instr_data(15 downto 10);
dest_nxt <= instr_data(4 downto 0);
rega_nxt <= instr_data(4 downto 0);
regb_nxt <= instr_data(9 downto 5);
imm_nxt <= instr_data(12 downto 5);
else -- schedule nop, we wait for a (re)fetch
opcode_nxt <= (others => '0');
dest_nxt <= (others => '0');
rega_nxt <= (others => '0');
regb_nxt <= (others => '0');
imm_nxt <= (others => '0');
end if;
end process;
calc_pc_nxt: process(reset, pc, pc_in, branch, instr_valid)
begin
if reset = '1' then
pc_nxt <= (others => '0');
elsif branch='1' then
pc_nxt <= pc_in;
elsif instr_valid /= '1' then
pc_nxt <= pc;
else
pc_nxt <= pc + 2;
end if;
end process;
reg_async_when_locked: process (lock, rega_nxt, regb_nxt, rega, regb)
begin
if lock = '1' then
async_rega <= rega;
async_regb <= regb;
else
async_rega <= rega_nxt;
async_regb <= regb_nxt;
end if;
end process;
sync: process(clk, reset)
begin
if reset = '1' then
opcode <= (others => '0');
dest <= (others => '0');
rega <= (others => '0');
regb <= (others => '0');
imm <= (others => '0');
--~ pc <= (others => '0');
pc <= INIT_VECTOR;
--~ pc <= x"7FFE";
--~ pc <= pc_nxt;
--~ instr_addr <= (others => '0');
pc_id <= (others => '0');
elsif rising_edge(clk) then
if lock='1' then
opcode <= opcode;
dest <= dest;
rega <= rega;
regb <= regb;
imm <= imm;
pc <= pc;
pc_id <= pc_id;
else
opcode <= opcode_nxt;
dest <= dest_nxt;
rega <= rega_nxt;
regb <= regb_nxt;
imm <= imm_nxt;
pc <= pc_nxt;
pc_id <= pc;
end if;
end if;
end process;
end sat1;
| gpl-3.0 | c67dcc2dd3aefbbf027f5e5ada972cc7 | 0.547333 | 2.640879 | false | false | false | false |
marcoep/MusicBoxNano | ip/EnvAddrMux.vhd | 1 | 12,747 | -- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: EnvAddrMux.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY EnvAddrMux IS
PORT
(
clock : IN STD_LOGIC ;
data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END EnvAddrMux;
ARCHITECTURE SYN OF envaddrmux IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire14 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire16 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire17 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
sub_wire16 <= data0x(7 DOWNTO 0);
sub_wire15 <= data1x(7 DOWNTO 0);
sub_wire14 <= data2x(7 DOWNTO 0);
sub_wire13 <= data3x(7 DOWNTO 0);
sub_wire12 <= data4x(7 DOWNTO 0);
sub_wire11 <= data5x(7 DOWNTO 0);
sub_wire10 <= data6x(7 DOWNTO 0);
sub_wire9 <= data7x(7 DOWNTO 0);
sub_wire8 <= data8x(7 DOWNTO 0);
sub_wire7 <= data9x(7 DOWNTO 0);
sub_wire6 <= data10x(7 DOWNTO 0);
sub_wire5 <= data11x(7 DOWNTO 0);
sub_wire4 <= data12x(7 DOWNTO 0);
sub_wire3 <= data13x(7 DOWNTO 0);
sub_wire2 <= data14x(7 DOWNTO 0);
sub_wire0 <= data15x(7 DOWNTO 0);
sub_wire1(15, 0) <= sub_wire0(0);
sub_wire1(15, 1) <= sub_wire0(1);
sub_wire1(15, 2) <= sub_wire0(2);
sub_wire1(15, 3) <= sub_wire0(3);
sub_wire1(15, 4) <= sub_wire0(4);
sub_wire1(15, 5) <= sub_wire0(5);
sub_wire1(15, 6) <= sub_wire0(6);
sub_wire1(15, 7) <= sub_wire0(7);
sub_wire1(14, 0) <= sub_wire2(0);
sub_wire1(14, 1) <= sub_wire2(1);
sub_wire1(14, 2) <= sub_wire2(2);
sub_wire1(14, 3) <= sub_wire2(3);
sub_wire1(14, 4) <= sub_wire2(4);
sub_wire1(14, 5) <= sub_wire2(5);
sub_wire1(14, 6) <= sub_wire2(6);
sub_wire1(14, 7) <= sub_wire2(7);
sub_wire1(13, 0) <= sub_wire3(0);
sub_wire1(13, 1) <= sub_wire3(1);
sub_wire1(13, 2) <= sub_wire3(2);
sub_wire1(13, 3) <= sub_wire3(3);
sub_wire1(13, 4) <= sub_wire3(4);
sub_wire1(13, 5) <= sub_wire3(5);
sub_wire1(13, 6) <= sub_wire3(6);
sub_wire1(13, 7) <= sub_wire3(7);
sub_wire1(12, 0) <= sub_wire4(0);
sub_wire1(12, 1) <= sub_wire4(1);
sub_wire1(12, 2) <= sub_wire4(2);
sub_wire1(12, 3) <= sub_wire4(3);
sub_wire1(12, 4) <= sub_wire4(4);
sub_wire1(12, 5) <= sub_wire4(5);
sub_wire1(12, 6) <= sub_wire4(6);
sub_wire1(12, 7) <= sub_wire4(7);
sub_wire1(11, 0) <= sub_wire5(0);
sub_wire1(11, 1) <= sub_wire5(1);
sub_wire1(11, 2) <= sub_wire5(2);
sub_wire1(11, 3) <= sub_wire5(3);
sub_wire1(11, 4) <= sub_wire5(4);
sub_wire1(11, 5) <= sub_wire5(5);
sub_wire1(11, 6) <= sub_wire5(6);
sub_wire1(11, 7) <= sub_wire5(7);
sub_wire1(10, 0) <= sub_wire6(0);
sub_wire1(10, 1) <= sub_wire6(1);
sub_wire1(10, 2) <= sub_wire6(2);
sub_wire1(10, 3) <= sub_wire6(3);
sub_wire1(10, 4) <= sub_wire6(4);
sub_wire1(10, 5) <= sub_wire6(5);
sub_wire1(10, 6) <= sub_wire6(6);
sub_wire1(10, 7) <= sub_wire6(7);
sub_wire1(9, 0) <= sub_wire7(0);
sub_wire1(9, 1) <= sub_wire7(1);
sub_wire1(9, 2) <= sub_wire7(2);
sub_wire1(9, 3) <= sub_wire7(3);
sub_wire1(9, 4) <= sub_wire7(4);
sub_wire1(9, 5) <= sub_wire7(5);
sub_wire1(9, 6) <= sub_wire7(6);
sub_wire1(9, 7) <= sub_wire7(7);
sub_wire1(8, 0) <= sub_wire8(0);
sub_wire1(8, 1) <= sub_wire8(1);
sub_wire1(8, 2) <= sub_wire8(2);
sub_wire1(8, 3) <= sub_wire8(3);
sub_wire1(8, 4) <= sub_wire8(4);
sub_wire1(8, 5) <= sub_wire8(5);
sub_wire1(8, 6) <= sub_wire8(6);
sub_wire1(8, 7) <= sub_wire8(7);
sub_wire1(7, 0) <= sub_wire9(0);
sub_wire1(7, 1) <= sub_wire9(1);
sub_wire1(7, 2) <= sub_wire9(2);
sub_wire1(7, 3) <= sub_wire9(3);
sub_wire1(7, 4) <= sub_wire9(4);
sub_wire1(7, 5) <= sub_wire9(5);
sub_wire1(7, 6) <= sub_wire9(6);
sub_wire1(7, 7) <= sub_wire9(7);
sub_wire1(6, 0) <= sub_wire10(0);
sub_wire1(6, 1) <= sub_wire10(1);
sub_wire1(6, 2) <= sub_wire10(2);
sub_wire1(6, 3) <= sub_wire10(3);
sub_wire1(6, 4) <= sub_wire10(4);
sub_wire1(6, 5) <= sub_wire10(5);
sub_wire1(6, 6) <= sub_wire10(6);
sub_wire1(6, 7) <= sub_wire10(7);
sub_wire1(5, 0) <= sub_wire11(0);
sub_wire1(5, 1) <= sub_wire11(1);
sub_wire1(5, 2) <= sub_wire11(2);
sub_wire1(5, 3) <= sub_wire11(3);
sub_wire1(5, 4) <= sub_wire11(4);
sub_wire1(5, 5) <= sub_wire11(5);
sub_wire1(5, 6) <= sub_wire11(6);
sub_wire1(5, 7) <= sub_wire11(7);
sub_wire1(4, 0) <= sub_wire12(0);
sub_wire1(4, 1) <= sub_wire12(1);
sub_wire1(4, 2) <= sub_wire12(2);
sub_wire1(4, 3) <= sub_wire12(3);
sub_wire1(4, 4) <= sub_wire12(4);
sub_wire1(4, 5) <= sub_wire12(5);
sub_wire1(4, 6) <= sub_wire12(6);
sub_wire1(4, 7) <= sub_wire12(7);
sub_wire1(3, 0) <= sub_wire13(0);
sub_wire1(3, 1) <= sub_wire13(1);
sub_wire1(3, 2) <= sub_wire13(2);
sub_wire1(3, 3) <= sub_wire13(3);
sub_wire1(3, 4) <= sub_wire13(4);
sub_wire1(3, 5) <= sub_wire13(5);
sub_wire1(3, 6) <= sub_wire13(6);
sub_wire1(3, 7) <= sub_wire13(7);
sub_wire1(2, 0) <= sub_wire14(0);
sub_wire1(2, 1) <= sub_wire14(1);
sub_wire1(2, 2) <= sub_wire14(2);
sub_wire1(2, 3) <= sub_wire14(3);
sub_wire1(2, 4) <= sub_wire14(4);
sub_wire1(2, 5) <= sub_wire14(5);
sub_wire1(2, 6) <= sub_wire14(6);
sub_wire1(2, 7) <= sub_wire14(7);
sub_wire1(1, 0) <= sub_wire15(0);
sub_wire1(1, 1) <= sub_wire15(1);
sub_wire1(1, 2) <= sub_wire15(2);
sub_wire1(1, 3) <= sub_wire15(3);
sub_wire1(1, 4) <= sub_wire15(4);
sub_wire1(1, 5) <= sub_wire15(5);
sub_wire1(1, 6) <= sub_wire15(6);
sub_wire1(1, 7) <= sub_wire15(7);
sub_wire1(0, 0) <= sub_wire16(0);
sub_wire1(0, 1) <= sub_wire16(1);
sub_wire1(0, 2) <= sub_wire16(2);
sub_wire1(0, 3) <= sub_wire16(3);
sub_wire1(0, 4) <= sub_wire16(4);
sub_wire1(0, 5) <= sub_wire16(5);
sub_wire1(0, 6) <= sub_wire16(6);
sub_wire1(0, 7) <= sub_wire16(7);
result <= sub_wire17(7 DOWNTO 0);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_pipeline => 2,
lpm_size => 16,
lpm_type => "LPM_MUX",
lpm_width => 8,
lpm_widths => 4
)
PORT MAP (
clock => clock,
data => sub_wire1,
sel => sel,
result => sub_wire17
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL "data10x[7..0]"
-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL "data11x[7..0]"
-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL "data12x[7..0]"
-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL "data13x[7..0]"
-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL "data14x[7..0]"
-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL "data15x[7..0]"
-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL "data4x[7..0]"
-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL "data5x[7..0]"
-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL "data6x[7..0]"
-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL "data7x[7..0]"
-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL "data8x[7..0]"
-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL "data9x[7..0]"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvAddrMux.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvAddrMux.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvAddrMux.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvAddrMux.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL EnvAddrMux_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-3.0 | febf2a6971488b9b28065e8160da1faf | 0.607594 | 2.490135 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_0_1/RAT_FlagReg_0_1_sim_netlist.vhdl | 2 | 2,920 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 00:02:33 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_0_1/RAT_FlagReg_0_1_sim_netlist.vhdl
-- Design : RAT_FlagReg_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_FlagReg_0_1_FlagReg is
port (
OUT_FLAG : out STD_LOGIC;
IN_FLAG : in STD_LOGIC;
SET : in STD_LOGIC;
LD : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_FlagReg_0_1_FlagReg : entity is "FlagReg";
end RAT_FlagReg_0_1_FlagReg;
architecture STRUCTURE of RAT_FlagReg_0_1_FlagReg is
signal \^out_flag\ : STD_LOGIC;
signal OUT_FLAG_i_1_n_0 : STD_LOGIC;
begin
OUT_FLAG <= \^out_flag\;
OUT_FLAG_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ACAFACAC"
)
port map (
I0 => IN_FLAG,
I1 => SET,
I2 => LD,
I3 => CLR,
I4 => \^out_flag\,
O => OUT_FLAG_i_1_n_0
);
OUT_FLAG_reg: unisim.vcomponents.FDRE
port map (
C => CLK,
CE => '1',
D => OUT_FLAG_i_1_n_0,
Q => \^out_flag\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_FlagReg_0_1 is
port (
IN_FLAG : in STD_LOGIC;
LD : in STD_LOGIC;
SET : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_FLAG : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_FlagReg_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_FlagReg_0_1 : entity is "RAT_FlagReg_0_1,FlagReg,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_FlagReg_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_FlagReg_0_1 : entity is "FlagReg,Vivado 2016.4";
end RAT_FlagReg_0_1;
architecture STRUCTURE of RAT_FlagReg_0_1 is
begin
U0: entity work.RAT_FlagReg_0_1_FlagReg
port map (
CLK => CLK,
CLR => CLR,
IN_FLAG => IN_FLAG,
LD => LD,
OUT_FLAG => OUT_FLAG,
SET => SET
);
end STRUCTURE;
| mit | a49de82b6792ea7a0cb553a84c638438 | 0.606849 | 3.447462 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment3-Program_Counter/RTL/Counter10bit.vhd | 1 | 1,333 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 09/19/2017 12:16:57 AM
-- Design Name:
-- Module Name: Counter10bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter10bit is
Port ( Din : in STD_LOGIC_VECTOR (0 to 9);
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR (0 to 9) );
end Counter10bit;
architecture Behavioral of Counter10bit is
signal s_COUNT : STD_LOGIC_VECTOR (0 to 9);
begin
process (CLK, RESET) begin
if (RESET = '1') then
s_COUNT <= ( others => '0' );
elsif (rising_edge(CLK)) then
if (LOAD = '1') then
s_COUNT <= Din;
elsif (INC = '1') then
s_COUNT <= s_COUNT + 1;
end if;
end if;
end process;
COUNT <= s_COUNT;
end Behavioral;
| mit | 02a31ea2891e9738072b68b06c315610 | 0.485371 | 3.852601 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/mem/ddr2/memtest_Atlys_1x128.vhdl | 1 | 8,380 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory tester for Atlys board using Xilinx MIG with one
-- 128-bit port.
--
-- Description:
-- ------------------------------------
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.utils.all;
entity memtest_Atlys_1x128 is
generic (
C3_SIMULATION : string := "FALSE");
port (
Atlys_SystemClock_100MHz : in std_logic;
Atlys_GPIO_LED : out std_logic_vector(7 downto 0);
-- Memory Controller Bank 3
mcb3_dram_dq : inout std_logic_vector(16-1 downto 0);
mcb3_dram_a : out std_logic_vector(13-1 downto 0);
mcb3_dram_ba : out std_logic_vector(3-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic);
end entity memtest_Atlys_1x128;
architecture rtl of memtest_Atlys_1x128 is
signal memtest0_status : std_logic_vector(2 downto 0);
-- Memory Controller signals
-- signal c3_sys_rst_i : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic; -- output from IP core
signal c3_rst0 : std_logic; -- output from IP core, asynchronously asserted!
-- signal c3_p0_cmd_clk : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
-- signal c3_p0_wr_clk : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(16-1 downto 0);
signal c3_p0_wr_data : std_logic_vector(128-1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
-- signal c3_p0_rd_clk : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(128-1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- MemoryTester for Port 0
-----------------------------------------------------------------------------
MemoryTester0 : block
constant BYTE_ADDR_BITS : natural := 4; -- 16 Byte / Word
constant WORD_ADDR_BITS : natural := ite(SIMULATION,
15, -- 32 KByte = 2 rows
27) -- 128 MB = 1 GBit
-BYTE_ADDR_BITS;
signal mem_rdy : std_logic;
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(WORD_ADDR_BITS-1 downto 0);
signal mem_wdata : std_logic_vector(127 downto 0);
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(127 downto 0);
begin -- block MemoryTester0
fsm: entity work.memtest_fsm
generic map (
A_BITS => WORD_ADDR_BITS,
D_BITS => 128)
port map (
clk => c3_clk0,
rst => c3_rst0,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
status => memtest0_status);
adapter: entity poc.ddr2_mem2mig_adapter_Spartan6
generic map (
D_BITS => 128,
MEM_A_BITS => WORD_ADDR_BITS,
APP_A_BITS => c3_p0_cmd_byte_addr'length)
port map (
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mig_calib_done => c3_calib_done,
mig_cmd_full => c3_p0_cmd_full,
mig_wr_full => c3_p0_wr_full,
mig_rd_empty => c3_p0_rd_empty,
mig_rd_data => c3_p0_rd_data,
mig_cmd_instr => c3_p0_cmd_instr,
mig_cmd_en => c3_p0_cmd_en,
mig_cmd_bl => c3_p0_cmd_bl,
mig_cmd_byte_addr => c3_p0_cmd_byte_addr,
mig_wr_data => c3_p0_wr_data,
mig_wr_mask => c3_p0_wr_mask,
mig_wr_en => c3_p0_wr_en,
mig_rd_en => c3_p0_rd_en);
end block MemoryTester0;
-----------------------------------------------------------------------------
-- Memory Controller Instantiation
-----------------------------------------------------------------------------
mig : entity poc.mig_Atlys_1x128
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk => Atlys_SystemClock_100MHz,
c3_sys_rst_i => '0', -- active high
c3_calib_done => c3_calib_done,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => c3_clk0,
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => c3_clk0,
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => c3_clk0,
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error);
-----------------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------------
Atlys_GPIO_LED(7) <= c3_rst0;
Atlys_GPIO_LED(6) <= '0';
Atlys_GPIO_LED(5) <= '0';
Atlys_GPIO_LED(4) <= '0';
Atlys_GPIO_LED(3) <= c3_calib_done;
Atlys_GPIO_LED(2 downto 0) <= memtest0_status;
end architecture rtl;
| apache-2.0 | 1a0c7861cd91c6ebea9641a8d5f11b11 | 0.552029 | 2.650221 | false | true | false | false |
VLSI-EDA/PoC-Examples | src/mem/memtest_fsm.vhdl | 1 | 9,203 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Generic FSM for Memory Controller Test Modules
--
-- Description:
-- ------------------------------------
-- Check read/write by blocked and random memory accesses.
--
-- Output status(0) indicates if an read error has occured (high-active).
-- Output status(2 downto 1) are progress indicators, these should toogle with
-- a visible frequency. Otherwise the memory controller does not except new
-- commands.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
-------------------------------------------------------------------------------
-- Naming Conventions:
-- (Based on: Keating and Bricaud: "Reuse Methodology Manual")
--
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: all UPPERCASE
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- output of a register: "*_r"
-- asynchronous signal: "*_a"
-- pipelined or register delay signals: "*_p#"
-- data before being registered into register with the same name: "*_nxt"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- tristate internal signal "*_z"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.arith.all;
use poc.utils.all;
entity memtest_fsm is
generic (
A_BITS : positive;
D_BITS : positive
);
port (
clk : in std_logic;
rst : in std_logic;
mem_rdy : in std_logic;
mem_rstb : in std_logic;
mem_rdata : in std_logic_vector(D_BITS-1 downto 0);
mem_req : out std_logic;
mem_write : out std_logic;
mem_addr : out unsigned(A_BITS-1 downto 0);
mem_wdata : out std_logic_vector(D_BITS-1 downto 0);
status : out std_logic_vector(2 downto 0));
end memtest_fsm;
architecture rtl of memtest_fsm is
-- Main FSM
type FSM_TYPE is (INIT, WRITE_BLOCK, READ_BLOCK,
WRITE_READ1, WRITE_READ2, FINISHED);
signal fsm_cs : FSM_TYPE;
signal fsm_ns : FSM_TYPE;
-- Read Check FSM
type CHKFSM_TYPE is (CHK_INIT, CHK_RUN);
signal chkfsm_cs : CHKFSM_TYPE;
signal chkfsm_ns : CHKFSM_TYPE;
-- Address register
signal addr_r : unsigned(A_BITS downto 0);
signal addr_rst : std_logic;
signal addr_inc : std_logic;
-- Write Data register
signal wdata_r : std_logic_vector(D_BITS-1 downto 0);
signal wdata_rst : std_logic;
signal wdata_got : std_logic;
-- Expected Read Data Register
signal exp_rdata_r : std_logic_vector(D_BITS-1 downto 0);
signal exp_rdata_rst : std_logic;
signal exp_rdata_got : std_logic;
-- End of block has been reached.
signal block_finished : std_logic;
-- Read data / strobe register
signal rdata_r : std_logic_vector(D_BITS-1 downto 0);
signal rstb_r : std_logic;
-- Read data equals expected value.
signal rdata_eq_exp : std_logic;
-- Read fail indicator
signal rd_failed_r : std_logic;
signal rd_failed_rst : std_logic;
signal rd_failed_set : std_logic;
-- Run counter
signal run_r : unsigned(1 downto 0) := (others => '0');
signal run_inc : std_logic;
begin -- rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
exp_rdata_prng: arith_prng
generic map (
BITS => D_BITS)
port map (
clk => clk,
rst => exp_rdata_rst,
got => exp_rdata_got,
val => exp_rdata_r);
wdata_prng: arith_prng
generic map (
BITS => D_BITS)
port map (
clk => clk,
rst => wdata_rst,
got => wdata_got,
val => wdata_r);
-----------------------------------------------------------------------------
-- Datapath not depending on FSM
-----------------------------------------------------------------------------
block_finished <= addr_r(A_BITS);
rdata_eq_exp <= '1' when rdata_r = std_logic_vector(exp_rdata_r) else '0';
-----------------------------------------------------------------------------
-- Main FSM
-----------------------------------------------------------------------------
process (fsm_cs, mem_rdy, block_finished)
begin -- process
fsm_ns <= fsm_cs;
mem_req <= '0';
mem_write <= '-';
run_inc <= '0';
addr_rst <= '0';
addr_inc <= '0';
wdata_rst <= '0';
wdata_got <= '0';
case fsm_cs is
when INIT =>
wdata_rst <= '1';
addr_rst <= '1';
fsm_ns <= WRITE_BLOCK;
when WRITE_BLOCK =>
if block_finished = '1' then
addr_rst <= '1';
fsm_ns <= READ_BLOCK;
else
mem_req <= '1';
mem_write <= '1';
if mem_rdy = '1' then
wdata_got <= '1';
addr_inc <= '1';
end if;
end if;
when READ_BLOCK =>
if block_finished = '1' then
addr_rst <= '1';
fsm_ns <= WRITE_READ1;
else
-- Note: Read data is checked concurrently.
mem_req <= '1';
mem_write <= '0';
if mem_rdy = '1' then
addr_inc <= '1';
end if;
end if;
when WRITE_READ1 =>
if block_finished = '1' then
addr_rst <= '1';
if SIMULATION then
fsm_ns <= FINISHED;
else
run_inc <= '1';
fsm_ns <= WRITE_BLOCK;
end if;
else
mem_req <= '1';
mem_write <= '1';
if mem_rdy = '1' then
wdata_got <= '1';
-- do not increment address
fsm_ns <= WRITE_READ2;
end if;
end if;
when WRITE_READ2 =>
-- Note: Read data is checked concurrently.
mem_req <= '1';
mem_write <= '0';
if mem_rdy = '1' then
addr_inc <= '1';
fsm_ns <= WRITE_READ1;
end if;
when FINISHED =>
null;
end case;
end process;
-----------------------------------------------------------------------------
-- Read Check FSM
-----------------------------------------------------------------------------
process (chkfsm_cs, rstb_r, rdata_eq_exp)
begin -- process
chkfsm_ns <= chkfsm_cs;
exp_rdata_rst <= '0';
exp_rdata_got <= '0';
rd_failed_rst <= '0';
rd_failed_set <= '0';
case chkfsm_cs is
when CHK_INIT =>
exp_rdata_rst <= '1';
rd_failed_rst <= '1';
chkfsm_ns <= CHK_RUN;
when CHK_RUN =>
if rstb_r = '1' then
exp_rdata_got <= '1';
if rdata_eq_exp = '0' then
rd_failed_set <= '1';
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
process (clk)
begin -- process
if rising_edge(clk) then
if rst = '1' then
fsm_cs <= INIT;
chkfsm_cs <= CHK_INIT;
run_r <= (others => '0');
else
fsm_cs <= fsm_ns;
chkfsm_cs <= chkfsm_ns;
if run_inc = '1' then
run_r <= run_r + 1;
end if;
end if;
if addr_rst = '1' then
addr_r <= (others => '0');
elsif addr_inc = '1' then
addr_r <= addr_r + 1;
end if;
if rd_failed_rst = '1' then
rd_failed_r <= '0';
elsif rd_failed_set = '1' then
rd_failed_r <= '1';
end if;
if rst = '1' then
rstb_r <= '0';
else
rstb_r <= mem_rstb;
end if;
if mem_rstb = '1' then
rdata_r <= mem_rdata;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
mem_addr <= addr_r(A_BITS-1 downto 0);
mem_wdata <= std_logic_vector(wdata_r);
status(0) <= rd_failed_r;
status(2 downto 1) <= std_logic_vector(run_r);
end rtl;
| apache-2.0 | 744a68152b45a24e6d9d3c08254da5bc | 0.478214 | 3.899576 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_StackPointer_0_0/synth/RAT_StackPointer_0_0.vhd | 1 | 4,225 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:StackPointer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_StackPointer_0_0 IS
PORT (
DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RST : IN STD_LOGIC;
LD : IN STD_LOGIC;
INCR : IN STD_LOGIC;
DECR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_StackPointer_0_0;
ARCHITECTURE RAT_StackPointer_0_0_arch OF RAT_StackPointer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT StackPointer IS
PORT (
DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RST : IN STD_LOGIC;
LD : IN STD_LOGIC;
INCR : IN STD_LOGIC;
DECR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT StackPointer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "StackPointer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_StackPointer_0_0_arch : ARCHITECTURE IS "RAT_StackPointer_0_0,StackPointer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "RAT_StackPointer_0_0,StackPointer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=StackPointer,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : StackPointer
PORT MAP (
DATA => DATA,
RST => RST,
LD => LD,
INCR => INCR,
DECR => DECR,
CLK => CLK,
DOUT => DOUT
);
END RAT_StackPointer_0_0_arch;
| mit | b5d6b1e98d1dd025c3b7400f23c4d6f6 | 0.728757 | 3.963415 | false | false | false | false |
VLSI-EDA/PoC-Examples | src/mem/sdram/memtest_de0.vhdl | 1 | 7,478 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Memory Controller Test for Altera DE0 Board
--
-- Description:
-- ------------------------------------
-- Top-Level of Memory Controller Test for Altera DE0 Board
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
use poc.fifo.all;
entity memtest_de0 is
port (
clk_in : in std_logic;
btn : in std_logic_vector(2 downto 2);
led : out std_logic_vector(9 downto 0);
sd_ck : out std_logic;
sd_cke : out std_logic;
sd_cs : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sd_we : out std_logic;
sd_ba : out std_logic_vector(1 downto 0);
sd_a : out std_logic_vector(11 downto 0);
sd_ldm : out std_logic;
sd_udm : out std_logic;
sd_dq : inout std_logic_vector(15 downto 0));
end memtest_de0;
architecture rtl of memtest_de0 is
signal clk_sys : std_logic;
signal clk_mem : std_logic;
signal clk_memout : std_logic;
signal rst_sys : std_logic;
signal rst_mem : std_logic;
signal locked : std_logic;
signal clk_tb : std_logic;
signal rst_tb : std_logic;
signal cf_put : std_logic;
signal cf_full : std_logic;
signal cf_din : std_logic_vector(22 downto 0);
signal cf_dout : std_logic_vector(22 downto 0);
signal cf_valid : std_logic;
signal cf_got : std_logic;
signal wf_put : std_logic;
signal wf_full : std_logic;
signal wf_din : std_logic_vector(15 downto 0);
signal wf_dout : std_logic_vector(15 downto 0);
signal wf_valid : std_logic;
signal wf_got : std_logic;
signal mem_rdy : std_logic;
signal mem_rstb : std_logic;
signal mem_rdata : std_logic_vector(15 downto 0);
signal mem_req : std_logic;
signal mem_write : std_logic;
signal mem_addr : unsigned(21 downto 0);
signal mem_wdata : std_logic_vector(15 downto 0);
signal fsm_status : std_logic_vector(2 downto 0);
signal rf_put : std_logic;
signal rf_din : std_logic_vector(15 downto 0);
begin -- rtl
pll: entity work.memtest_de0_pll
port map (
inclk0 => clk_in,
c0 => clk_sys,
c1 => clk_mem,
c2 => clk_memout,
locked => locked);
rst_sync : block
signal do_rst : std_logic;
signal rst_sys_r : std_logic_vector(4 downto 0);
signal rst_mem_r : std_logic_vector(4 downto 0);
begin -- block clockgen
-- reset synchronizer
do_rst <= not locked or not btn(2);
rst_sys_r <= rst_sys_r(rst_sys_r'left-1 downto 0) & do_rst
when rising_edge(clk_sys);
rst_mem_r <= rst_mem_r(rst_mem_r'left-1 downto 0) & do_rst
when rising_edge(clk_mem);
rst_sys <= rst_sys_r(rst_sys_r'left);
rst_mem <= rst_mem_r(rst_mem_r'left);
end block rst_sync;
-- Testbench clock selection
-- Also update chipscope configuration.
-- clk_tb <= clk_mem;
-- rst_tb <= rst_mem;
clk_tb <= clk_sys;
rst_tb <= rst_sys;
-- uses default configuration, see entity declaration
mem_ctrl: entity poc.sdram_ctrl_de0
generic map (
CLK_PERIOD => 7.5,
CL => 2,
BL => 1)
port map (
clk => clk_mem,
clkout => clk_memout,
rst => rst_mem,
user_cmd_valid => cf_valid,
user_wdata_valid => wf_valid,
user_write => cf_dout(cf_dout'left),
user_addr => cf_dout(cf_dout'left-1 downto 0),
user_wdata => wf_dout,
user_got_cmd => cf_got,
user_got_wdata => wf_got,
user_rdata => rf_din,
user_rstb => rf_put,
sd_ck => sd_ck,
sd_cke => sd_cke,
sd_cs => sd_cs,
sd_ras => sd_ras,
sd_cas => sd_cas,
sd_we => sd_we,
sd_ba => sd_ba,
sd_a => sd_a,
sd_dq => sd_dq);
sd_ldm <= '0';
sd_udm <= '0';
cmd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 23,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => cf_put,
din => cf_din,
full => cf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => cf_got,
valid => cf_valid,
dout => cf_dout);
wr_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 16,
MIN_DEPTH => 8)
port map (
clk_wr => clk_tb,
rst_wr => rst_tb,
put => wf_put,
din => wf_din,
full => wf_full,
clk_rd => clk_mem,
rst_rd => rst_mem,
got => wf_got,
valid => wf_valid,
dout => wf_dout);
-- The size fo this FIFO depends on the latency between write and read
-- clock domain
rd_fifo: fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => 16,
MIN_DEPTH => 8)
port map (
clk_wr => clk_mem,
rst_wr => rst_mem,
put => rf_put,
din => rf_din,
full => open, -- can't stall
clk_rd => clk_tb,
rst_rd => rst_tb,
got => mem_rstb,
valid => mem_rstb,
dout => mem_rdata);
fsm: entity work.memtest_fsm
generic map (
A_BITS => 22,
D_BITS => 16)
port map (
clk => clk_tb,
rst => rst_tb,
mem_rdy => mem_rdy,
mem_rstb => mem_rstb,
mem_rdata => mem_rdata,
mem_req => mem_req,
mem_write => mem_write,
mem_addr => mem_addr,
mem_wdata => mem_wdata,
status => fsm_status);
-- Signal mem_ctrl ready only if both FIFOs are not full.
mem_rdy <= cf_full nor wf_full;
-- Word aligned access to memory.
-- Parallel "put" to both FIFOs.
cf_put <= mem_req and mem_rdy;
wf_put <= mem_req and mem_write and mem_rdy;
cf_din <= mem_write & std_logic_vector(mem_addr);
wf_din <= mem_wdata;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
led(9) <= locked;
led(8 downto 3) <= (others => '0');
led(2 downto 0) <= fsm_status;
end rtl;
| apache-2.0 | 3552097f6f76976e6ef5d116613b71a5 | 0.513105 | 3.409941 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment5-Ram_Reg/RTL/ScratchRam.vhd | 1 | 1,531 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 09/29/2017 12:31:58 AM
-- Design Name: ScratchRam
-- Module Name: ScratchRam - Behavioral
-- Project Name: RAT CPU
-- Target Devices: xc7a50tcsg324-1
-- Tool Versions:
-- Description: This is the RAM domponent for our RAT CPU. The function of the RAM is to:
-- - Provide temporary storage that is accessile using the RAT instruction set
-- - Provide storage for the stack
-- The RAM is 256x10 memory module with asyc read and synchronous write.
--
-- Dependencies: N/A
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ScratchRam is
Port ( DATA_IN : in STD_LOGIC_VECTOR (9 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (9 downto 0);
ADDR : in STD_LOGIC_VECTOR (7 downto 0);
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end ScratchRam;
architecture Behavioral of ScratchRam is
TYPE memory is array (0 to 255) of std_logic_vector(9 downto 0);
SIGNAL RAM: memory := (others=>(others=>'0'));
begin
process(clk) begin
if (rising_edge(clk)) then
if (WE = '1') then
RAM(conv_integer(ADDR)) <= DATA_IN;
end if;
end if;
end process;
DATA_OUT <= RAM(conv_integer(ADDR));
end Behavioral;
| mit | f06521183171785cb475cb109bd6b7ad | 0.585238 | 3.680288 | false | false | false | false |
viniciussmello/SistemasDigitais | Trabalho 1/GeradorDeEntradas.vhd | 1 | 996 | ----------------------------------------------------------------------------------
-- Create Date: 15:48:51 04/18/2017
-- Module Name: GeradorDeEntradas - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity GeradorDeEntradas is
Port ( Saida : out STD_LOGIC_VECTOR (7 downto 0);
clock : in STD_LOGIC);
end GeradorDeEntradas;
architecture Behavioral of GeradorDeEntradas is
signal counter: integer := 0;
signal VectorAB: STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
ClockCounter: process(clock, counter) -- Processo para que os 'if' possam ocorrer
begin
saida <= VectorAB;
if(clock'event and clock = '1') then
counter <= counter + 1;
VectorAB <= conv_std_logic_vector(counter, VectorAB'length);
end if;
if(counter = 256) then
counter <= 0;
end if;
end process ClockCounter;
end Behavioral;
| gpl-3.0 | 969173cda24acf30ccdc30f55ff38d85 | 0.563253 | 4.065306 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_FIR_resized2_2/synth/design_1_FIR_resized2_2.vhd | 1 | 12,514 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized2_2 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized2_2;
ARCHITECTURE design_1_FIR_resized2_2_arch OF design_1_FIR_resized2_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized2_2_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_FIR_resized2_2_arch: ARCHITECTURE IS "fir_compiler_v7_2_6,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_FIR_resized2_2_arch : ARCHITECTURE IS "design_1_FIR_resized2_2,fir_compiler_v7_2_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_FIR_resized2_2_arch: ARCHITECTURE IS "design_1_FIR_resized2_2,fir_compiler_v7_2_6,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=design_1_FIR_resized2_2,C_COEF_FILE=design_1_FIR_resized2_2.mif,C_COEF_FILE_LINES=105,C_FILTER_TYPE=1,C_INTERP_RATE=1,C_DECIM_RATE=5,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=204,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN" &
"=fixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=21,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=24,C_DATA_IP_PATH_WIDTHS=24,C_DATA_PX_PATH_WIDTHS=24,C_DATA_WIDTH=24,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=43,C_OUTPUT_WIDTH=32,C_OUTPUT_PATH_WIDTHS=32,C_ACCUM_OP_PATH_WIDTHS=43,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NU" &
"M_MADDS=21,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=1,C_INPUT_RATE=1,C_OUTPUT_RATE=5,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=28,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_TUSER_WIDTH=1,C_HAS_" &
"CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized2_2",
C_COEF_FILE => "design_1_FIR_resized2_2.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized2_2_arch;
| mit | 31f77a1ef3bdfdb5dccf982eaacaded0 | 0.654307 | 3.051451 | false | true | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/sim/RAT_Mux4x1_8_0_1.vhd | 1 | 3,384 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:Mux4x1_8:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_Mux4x1_8_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END RAT_Mux4x1_8_0_1;
ARCHITECTURE RAT_Mux4x1_8_0_1_arch OF RAT_Mux4x1_8_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux4x1_8_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1_8 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT Mux4x1_8;
BEGIN
U0 : Mux4x1_8
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END RAT_Mux4x1_8_0_1_arch;
| mit | d2533a97fba6e44c59e7b0a3d03a6e9a | 0.71247 | 3.751663 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_alu_0_0/synth/RAT_alu_0_0.vhd | 2 | 4,091 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:alu:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_alu_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END RAT_alu_0_0;
ARCHITECTURE RAT_alu_0_0_arch OF RAT_alu_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_alu_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT alu IS
GENERIC (
data_width : INTEGER;
sel_width : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END COMPONENT alu;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_alu_0_0_arch: ARCHITECTURE IS "alu,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_alu_0_0_arch : ARCHITECTURE IS "RAT_alu_0_0,alu,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_alu_0_0_arch: ARCHITECTURE IS "RAT_alu_0_0,alu,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=alu,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,data_width=8,sel_width=4}";
BEGIN
U0 : alu
GENERIC MAP (
data_width => 8,
sel_width => 4
)
PORT MAP (
A => A,
B => B,
C_IN => C_IN,
Sel => Sel,
SUM => SUM,
C_FLAG => C_FLAG,
Z_FLAG => Z_FLAG
);
END RAT_alu_0_0_arch;
| mit | ad5e9c9bda543c87daefd832cacfd449 | 0.705207 | 3.729262 | false | false | false | false |
ayueha/infomatic-pj | src/ALU/alu-original-error-include.vhd | 2 | 2,377 | library ieee;
use ieee.std_logic_1164.all;
entity alu is
port (
n : in std_logic_vector (3 downto 0);
m : in std_logic_vector (3 downto 0);
opcode : in std_logic_vector (1 downto 0);
d : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end alu;
architecture behavioral of alu is
component carry_ripple_adder
port (
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector (3 downto 0);
ci : in std_logic;
s : out std_logic_vector (3 downto 0);
co : out std_logic
);
end component;
signal m_inverted : std_logic_vector (3 downto 0);
signal nand_result : std_logic_vector (3 downto 0);
signal nor_result : std_logic_vector (3 downto 0);
signal adder_result : std_logic_vector (3 downto 0);
signal adder_carry_out : std_logic;
signal operation_type : std_logic;
signal sub : std_logic;
begin
-- Make sense from control bits
operation_type <= opcode(1); -- Are we doing logical or arithmetic operation?
sub <= opcode(0); -- Are we doing addition/NAND or subtraction/NOR?
-- Here we calculate inverted bits for subtraction if necessary
m_inverted(0) <= not m(0);
m_inverted(1) <= not m(1);
m_inverted(2) <= not m(2);
m_inverted(3) <= not m(3);
-- Addition
adder_instance: carry_ripple_adder
port map(
a => n,
b => m_inverted,
ci => '1',
s => adder_result,
co => adder_carry_out
);
-- Logical NAND operation
nand_result(0) <= not m(0) and n(0);
nand_result(1) <= not m(1) and n(1);
nand_result(2) <= not m(2) and n(2);
nand_result(3) <= not m(3) and n(3);
-- Logical NOR operation
nor_result(0) <= not m(0) or n(0);
nor_result(1) <= not m(1) or n(1);
nor_result(2) <= not m(2) or n(2);
nor_result(3) <= not m(3) or n(3);
-- Select output based on which operation was requested
d <= nand_result when opcode ="10" else
nor_result when opcode ="11" else
adder_result;
-- Carry out bit
cout <= (adder_carry_out xor sub) when operation_type = '0' else
'0';
end;
| mit | ef4d4757fa3cbb4fa9b0ea9d60d7b4d5 | 0.533446 | 3.480234 | false | false | false | false |
MiddleMan5/233 | Experiments/IP_Repo/Program Counter/src/Program_Counter.vhd | 2 | 4,167 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Oct 16 23:04:57 2017
--Host : Juice-Laptop running 64-bit major release (build 9200)
--Command : generate_target Program_Counter.bd
--Design : Program_Counter
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Program_Counter is
port (
CLK : in STD_LOGIC;
FROM_IMMED : in STD_LOGIC_VECTOR ( 9 downto 0 );
FROM_STACK : in STD_LOGIC_VECTOR ( 9 downto 0 );
PC_COUNT : out STD_LOGIC_VECTOR ( 0 to 9 );
PC_INC : in STD_LOGIC;
PC_LD : in STD_LOGIC;
PC_MUX_SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
RST : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of Program_Counter : entity is "Program_Counter,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Program_Counter,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=3,numReposBlks=3,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of Program_Counter : entity is "Program_Counter.hwdef";
end Program_Counter;
architecture STRUCTURE of Program_Counter is
component Program_Counter_Constant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component Program_Counter_Constant_0_0;
component Program_Counter_Mux4x1_0_1 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
C : in STD_LOGIC_VECTOR ( 9 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component Program_Counter_Mux4x1_0_1;
component Program_Counter_Counter10bit_0_1 is
port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
end component Program_Counter_Counter10bit_0_1;
signal CLK_1 : STD_LOGIC;
signal Constant_0_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal Counter10bit_0_COUNT : STD_LOGIC_VECTOR ( 0 to 9 );
signal FROM_IMMED_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal FROM_STACK_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal Mux4x1_0_X : STD_LOGIC_VECTOR ( 9 downto 0 );
signal PC_INC_1 : STD_LOGIC;
signal PC_LD_1 : STD_LOGIC;
signal PC_MUX_SEL_1 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal RST_1 : STD_LOGIC;
begin
CLK_1 <= CLK;
FROM_IMMED_1(9 downto 0) <= FROM_IMMED(9 downto 0);
FROM_STACK_1(9 downto 0) <= FROM_STACK(9 downto 0);
PC_COUNT(0 to 9) <= Counter10bit_0_COUNT(0 to 9);
PC_INC_1 <= PC_INC;
PC_LD_1 <= PC_LD;
PC_MUX_SEL_1(1 downto 0) <= PC_MUX_SEL(1 downto 0);
RST_1 <= RST;
Constant_0: component Program_Counter_Constant_0_0
port map (
dout(9 downto 0) => Constant_0_dout(9 downto 0)
);
Counter10bit_0: component Program_Counter_Counter10bit_0_1
port map (
CLK => CLK_1,
COUNT(0 to 9) => Counter10bit_0_COUNT(0 to 9),
Din(0) => Mux4x1_0_X(9),
Din(1) => Mux4x1_0_X(8),
Din(2) => Mux4x1_0_X(7),
Din(3) => Mux4x1_0_X(6),
Din(4) => Mux4x1_0_X(5),
Din(5) => Mux4x1_0_X(4),
Din(6) => Mux4x1_0_X(3),
Din(7) => Mux4x1_0_X(2),
Din(8) => Mux4x1_0_X(1),
Din(9) => Mux4x1_0_X(0),
INC => PC_INC_1,
LOAD => PC_LD_1,
RESET => RST_1
);
Mux4x1_0: component Program_Counter_Mux4x1_0_1
port map (
A(9 downto 0) => FROM_IMMED_1(9 downto 0),
B(9 downto 0) => FROM_STACK_1(9 downto 0),
C(9 downto 0) => Constant_0_dout(9 downto 0),
D(9 downto 0) => B"0000000000",
SEL(1 downto 0) => PC_MUX_SEL_1(1 downto 0),
X(9 downto 0) => Mux4x1_0_X(9 downto 0)
);
end STRUCTURE;
| mit | 62a3c11c0df6a5389cd0998d7f3815a9 | 0.613391 | 3.032751 | false | false | false | false |
BBN-Q/VHDL-Components | test/FakeOSERDES.vhd | 1 | 1,203 | -- Fake testing module that mocks a 4:1 DDR OSERDES module
--
-- Original authors Diego Riste and Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FakeOSERDES is
generic (
SAMPLE_WIDTH : natural := 16;
CLK_PERIOD : time := 2 ns
);
port (
reset : in std_logic;
data_in : in std_logic_vector(4*SAMPLE_WIDTH-1 downto 0);
clk_in : in std_logic;
data_out : out std_logic_vector(SAMPLE_WIDTH-1 downto 0)
);
end entity ; -- FakeOSERDES
architecture arch of FakeOSERDES is
begin
serialize : process
variable registered_data : std_logic_vector(4*SAMPLE_WIDTH-1 downto 0);
begin
wait until rising_edge(clk_in);
while true loop
--register the input data as a crude clock crosser
registered_data := data_in;
if reset = '1' then
data_out <= (others => '0');
wait for CLK_PERIOD;
else
for ct in 0 to 3 loop
data_out <= registered_data((ct+1)*SAMPLE_WIDTH-1 downto ct*SAMPLE_WIDTH);
if ct = 3 then
wait until rising_edge(clk_in);
else
wait for CLK_PERIOD/2;
end if;
end loop; --
end if;
end loop ; --
end process; -- serialize
end architecture ; -- arch
| mpl-2.0 | f31b42e1d89bbc9c95096348efa5c185 | 0.67581 | 3.076726 | false | false | false | false |
open-power/snap | actions/hdl_example/hw/action_axi_nvme.vhd | 1 | 10,881 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.numeric_std.all;
entity action_axi_nvme is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Thread ID Width
C_M_AXI_ID_WIDTH : integer := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : integer := 32;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : integer := 32;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : integer := 1;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : integer := 1;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : integer := 1;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : integer := 1;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : integer := 1
);
port (
-- Users to add ports here
nvme_cmd_valid_i : in std_logic;
nvme_cmd_i : in std_logic_vector(11 downto 0);
nvme_mem_addr_i : in std_logic_vector(63 downto 0);
nvme_lba_addr_i : in std_logic_vector(63 downto 0);
nvme_lba_count_i : in std_logic_vector(31 downto 0);
nvme_status : out std_logic_vector(31 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end action_axi_nvme;
architecture action_axi_nvme of action_axi_nvme is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
function or_reduce (signal arg : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for i in arg'low to arg'high loop
result := result or arg(i);
end loop; -- i
return result;
end or_reduce;
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_wstrb : std_logic_vector(3 downto 0);
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arvalid : std_logic;
signal axi_rready : std_logic;
signal axi_awlen : std_logic_vector(7 downto 0);
signal axi_arlen : std_logic_vector(7 downto 0);
signal continue_polling : std_logic;
signal start_polling : std_logic;
signal cmd_complete : std_logic_vector(1 downto 0);
signal wr_count : std_logic_vector(3 downto 0);
begin
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= axi_awaddr;
M_AXI_AWLEN <= axi_awlen;
M_AXI_AWSIZE <= std_logic_vector( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= (others => '0');
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= (others => '0');
M_AXI_AWVALID <= axi_awvalid;
M_AXI_WDATA <= axi_wdata;
M_AXI_WSTRB <= (others => '1');
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (others => '0');
M_AXI_WVALID <= axi_wvalid;
M_AXI_BREADY <= axi_bready;
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= axi_araddr;
M_AXI_ARLEN <= axi_arlen;
M_AXI_ARSIZE <= std_logic_vector( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= (others => '0');
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= (others => '0');
M_AXI_ARVALID <= axi_arvalid;
M_AXI_RREADY <= axi_rready;
-- data for NVMe host write burst
with wr_count select
axi_wdata <=
nvme_mem_addr_i(31 downto 0) when x"5",
nvme_mem_addr_i(63 downto 32) when x"4",
nvme_lba_addr_i(31 downto 0) when x"3",
nvme_lba_addr_i(63 downto 32) when x"2",
nvme_lba_count_i(31 downto 0) when x"1",
(31 downto 12 => '0') & nvme_cmd_i when others ;
axi_wlast <= '1' when wr_count = x"0" else '0';
axi_awaddr <= (others => '0');
axi_awlen <= x"05";
axi_w: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
nvme_status(8) <= '0';
if M_AXI_ARESETN = '0' then
axi_awvalid <= '0';
axi_bready <= '0';
axi_wvalid <= '0';
nvme_status <= (others => '0');
else
-- wait for valid command
if nvme_cmd_valid_i = '1' then
-- send command to NVMe host
nvme_status <= (others => '0');
axi_awvalid <= '1';
wr_count <= x"5";
axi_wvalid <= '1';
end if;
-- wait for NVMe host poll completion
if cmd_complete /= "00" then
nvme_status(2 downto 1) <= cmd_complete;
nvme_status(8) <= '1';
end if;
if axi_awvalid = '1' and M_AXI_AWREADY = '1' then
axi_awvalid <= '0';
axi_bready <= '1';
end if;
start_polling <= '0';
-- wait until command has been send to NVMe host
-- and then start polling for completion
if M_AXI_BVALID = '1' and axi_bready = '1' then
axi_bready <= '0';
nvme_status(0) <= '1';
if wr_count = x"f" then
start_polling <= '1';
end if;
end if;
if axi_wvalid = '1' and M_AXI_WREADY = '1' then
wr_count <= wr_count - '1';
if wr_count = x"0" then
axi_wvalid <= '0';
end if;
end if;
end if;
end if;
end process;
axi_araddr <= x"0000_0004";
axi_arlen <= x"00";
-- poll NVMe host Action Track register until
-- bit 0 (command complete) or
-- bit 1 (error) is set
axi_r: process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
continue_polling <= '0';
cmd_complete <= (others => '0');
if (M_AXI_ARESETN = '0' ) then
axi_arvalid <= '0';
axi_rready <= '0';
else
if start_polling = '1' or continue_polling = '1' then
axi_arvalid <= '1';
end if;
if axi_arvalid = '1' and M_AXI_ARREADY = '1' then
axi_arvalid <= '0';
axi_rready <= '1';
end if;
if M_AXI_RVALID = '1' and axi_rready = '1' then
axi_rready <= '0';
if M_AXI_RDATA(1 downto 0) = "00" then
continue_polling <= '1';
else
cmd_complete <= M_AXI_RDATA(1 downto 0);
end if;
end if;
end if;
end if;
end process;
end action_axi_nvme;
| apache-2.0 | ca73caab8695ef9e5658c3078c1ee312 | 0.534877 | 3.210682 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/cores/axis_multiplexer_v1_0/tb/full_tb.vhd | 1 | 2,120 | ----------------------------------------------------------------------------------
--
-- full_tb.vhd
--
-- (c) 2017
-- N. Huesser
-- R. Frey
--
----------------------------------------------------------------------------------
--
-- A testbench to test the multiplexer with real inputs.
--
----------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library UNIMACRO;
use UNIMACRO.VCOMPONENTS.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
entity full_tb is
end full_tb;
architecture Behavioral of full_tb is
signal tbClkxC: std_logic := '0';
signal tbRstxRB: std_logic := '0';
signal tbSelectxDI: std_logic_vector(1 downto 0) := (others => '0');
signal tbData1xDI: std_logic_vector(31 downto 0) := (0 => '1', others => '0');
signal tbData2xDI: std_logic_vector(31 downto 0) := (1 => '1', others => '0');
signal tbDataxDO: std_logic_vector(31 downto 0);
begin
-- generate clock
tbClkxC <= not tbClkxC after 1ns;
DUT : entity work.multiplexer
port map (
ClkxCI => tbClkxC,
RstxRBI => tbRstxRB,
SelectxDI => tbSelectxDI,
Data1xDI => tbData1xDI,
Data2xDI => tbData2xDI,
DataxDO => tbDataxDO
);
process
begin
-- write chain of events here
tbRstxRB <= '0';
wait until rising_edge(tbClkxC);
wait until rising_edge(tbClkxC);
tbRstxRB <= '1';
-- wait 3 clk cycles
for i in 0 to 3 loop
wait until rising_edge(tbClkxC);
end loop;
tbSelectxDI <= (0 => '1', others => '0');
-- wait 3 clk cycles
for i in 0 to 3 loop
wait until rising_edge(tbClkxC);
end loop;
tbSelectxDI <= (1 => '1', 0 => '0', others => '0');
-- wait 3 clk cycles
for i in 0 to 3 loop
wait until rising_edge(tbClkxC);
end loop;
tbSelectxDI <= (1 => '1', 0 => '1', others => '0');
wait;
end process;
end Behavioral;
| mit | afc4dcd46aaa60ace4f843ef0dc67080 | 0.495283 | 4.124514 | false | false | false | false |
open-power/snap | hardware/hdl/core/mmio_to_axi_master.vhd | 1 | 13,299 | ----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
USE work.snap_core_types.all;
entity mmio_to_axi_master is
generic (
NUM_OF_ACTIONS : integer range 1 to 8 := 1
);
port (
clk : IN std_logic;
rst : IN std_logic;
mmx_d_i : IN MMX_D_T;
xmm_d_o : OUT XMM_D_T;
xk_d_o : out XK_D_T;
kx_d_i : in KX_D_T;
xj_c_o : out XJ_C_T;
jx_c_i : in JX_C_T;
xn_d_o : out XN_D_T;
nx_d_i : in NX_D_T
);
end mmio_to_axi_master;
architecture implementation of mmio_to_axi_master is
type fsm_t is ( AXI_IDLE, AXI_WR_DATA, AXI_WR_RESP, AXI_RD_REQ, AXI_RD_DATA );
signal axi_master_fsm_q : fsm_t ;
-- AXI4LITE signals
--write address valid
signal axi_awvalid_q : std_logic;
--write data valid
signal axi_wvalid_q : std_logic;
--read address valid
signal axi_arvalid_q : std_logic;
--read data acceptance
signal axi_rready_q : std_logic;
--write response acceptance
signal axi_bready_q : std_logic;
--write address
signal axi_address_q : std_logic_vector(31 downto 0);
signal saved_address_q : std_logic_vector(31 downto 0);
signal axi_wr_data_q : std_logic_vector(31 downto 0);
signal mmio_ack_q : std_logic;
signal mmio_rd_data_q : std_logic_vector(31 downto 0);
signal mmio_error_q : std_logic_vector( 1 downto 0);
signal poll_addr_q : std_logic_vector( 3 downto 0);
signal idle_vector_q : std_logic_vector( 4 downto 0);
signal poll_active_q : boolean;
signal poll_done_q : std_logic;
signal addr_32b_q : boolean;
signal wr_pending_q : std_logic;
signal rd_pending_q : std_logic;
signal max_actions : std_logic_vector(3 downto 0);
signal running_status_q : std_logic_vector(15 downto 0);
signal wr_pulse_q : std_logic;
signal wr_addr_q : std_logic_vector(17 downto 0);
signal start_bit_q : std_logic;
signal rvalid_q : std_logic;
signal nvme_q : std_logic;
begin
xk_d_o.M_AXI_AWADDR <= x"0000" & axi_address_q(15 downto 0);
xn_d_o.M_AXI_AWADDR <= axi_address_q;
--AXI 4 write data
xk_d_o.M_AXI_WDATA <= axi_wr_data_q;
xn_d_o.M_AXI_WDATA <= axi_wr_data_q;
xk_d_o.M_AXI_AWPROT <= "000";
xn_d_o.M_AXI_AWPROT <= "000";
xk_d_o.M_AXI_AWVALID <= axi_awvalid_q and not nvme_q;
xn_d_o.M_AXI_AWVALID <= axi_awvalid_q and nvme_q;
--Write Data(W)
xk_d_o.M_AXI_WVALID <= axi_wvalid_q and not nvme_q;
xn_d_o.M_AXI_WVALID <= axi_wvalid_q and nvme_q;
--Set all byte strobes in this example
xk_d_o.M_AXI_WSTRB <= "1111";
xn_d_o.M_AXI_WSTRB <= "1111";
--Write Response (B)
xk_d_o.M_AXI_BREADY <= axi_bready_q and not nvme_q;
xn_d_o.M_AXI_BREADY <= axi_bready_q and nvme_q;
--Read Address (AR)
xk_d_o.M_AXI_ARADDR <= x"0000" & axi_address_q(15 downto 0);
xn_d_o.M_AXI_ARADDR <= axi_address_q;
xk_d_o.M_AXI_ARVALID <= axi_arvalid_q and not nvme_q;
xn_d_o.M_AXI_ARVALID <= axi_arvalid_q and nvme_q;
xk_d_o.M_AXI_ARPROT <= "001";
xn_d_o.M_AXI_ARPROT <= "001";
--Read and Read Response (R)
xk_d_o.M_AXI_RREADY <= axi_rready_q and not nvme_q;
xn_d_o.M_AXI_RREADY <= axi_rready_q and nvme_q;
--Example design I/O
xmm_d_o.ack <= mmio_ack_q;
xmm_d_o.data <= mmio_rd_data_q;
xmm_d_o.error <= mmio_error_q;
max_actions <= std_logic_vector(to_unsigned(NUM_OF_ACTIONS - 1,4));
xj_c_o.valid <= idle_vector_q(4);
xj_c_o.action <= idle_vector_q(3 downto 0);
process(clk)
begin
if rising_edge(clk) then
rvalid_q <= '0';
mmio_ack_q <= '0';
if nvme_q = '0' then
mmio_rd_data_q <= kx_d_i.M_AXI_RDATA;
else
mmio_rd_data_q <= nx_d_i.M_AXI_RDATA;
end if;
if rst = '1' then
axi_master_fsm_q <= AXI_IDLE;
axi_awvalid_q <= '0';
axi_wvalid_q <= '0';
axi_bready_q <= '0';
axi_arvalid_q <= '0';
mmio_ack_q <= '0';
axi_rready_q <= '0';
poll_active_q <= false;
addr_32b_q <= false;
poll_addr_q <= (others => '0');
poll_done_q <= '0';
wr_pending_q <= '0';
rd_pending_q <= '0';
nvme_q <= '0';
else
if mmx_d_i.wr_strobe = '1' then
if mmx_d_i.addr(17 downto 16 ) = "11" then
-- indirect write
if mmx_d_i.addr(2) = '0' then
saved_address_q <= std_logic_vector(mmx_d_i.data);
mmio_ack_q <= '1';
else
wr_pending_q <= '1';
end if;
-- write address register
addr_32b_q <= true;
else
-- direct write
wr_pending_q <= '1';
addr_32b_q <= false;
end if;
end if;
if mmx_d_i.rd_strobe = '1' then
rd_pending_q <= '1';
if mmx_d_i.addr(17 downto 16 ) = "11" then
addr_32b_q <= true;
else
addr_32b_q <= false;
end if;
end if;
case axi_master_fsm_q is
when AXI_IDLE =>
if addr_32b_q then
axi_address_q <= saved_address_q;
-- 32 bit request goes always to the NVMe port
nvme_q <= '1';
else
axi_address_q <= std_logic_vector(mmx_d_i.addr);
if mmx_d_i.addr(29 downto 28) = "00" then
axi_address_q(17) <= '0';
end if;
-- address is eq or gt than 0x20000 --> is NVMe access
nvme_q <= mmx_d_i.addr(17);
end if;
axi_wr_data_q <= std_logic_vector(mmx_d_i.data);
axi_awvalid_q <= '0';
axi_wvalid_q <= '0';
axi_bready_q <= '0';
axi_arvalid_q <= '0';
axi_rready_q <= '0';
if wr_pending_q = '1' then
-- mmio write
axi_master_fsm_q <= AXI_WR_DATA;
axi_awvalid_q <= '1';
axi_wvalid_q <= '1';
elsif rd_pending_q = '1' then
-- mmio read
axi_master_fsm_q <= AXI_RD_REQ;
axi_arvalid_q <= '1';
elsif (running_status_q /= x"0000") and (jx_c_i.check_for_idle(to_integer(unsigned(poll_addr_q))) = '1') then
-- poll idle bit when no rd request is pending
axi_master_fsm_q <= AXI_RD_REQ;
axi_arvalid_q <= '1';
poll_active_q <= true;
axi_address_q <= x"0000" & poll_addr_q & x"000";
end if;
when AXI_RD_REQ =>
if(kx_d_i.M_AXI_ARREADY = '1' and nvme_q = '0') or (nx_d_i.M_AXI_ARREADY = '1' and nvme_q = '1') then
axi_master_fsm_q <= AXI_RD_DATA;
axi_arvalid_q <= '0';
axi_rready_q <= '1';
end if;
when AXI_RD_DATA =>
if (kx_d_i.M_AXI_RVALID = '1' and nvme_q = '0') or (nx_d_i.M_AXI_RVALID = '1' and nvme_q = '1') then
rvalid_q <= '1';
axi_master_fsm_q <= AXI_IDLE;
axi_rready_q <= '0';
if poll_active_q then
poll_active_q <= false;
if poll_addr_q = max_actions then
poll_addr_q <= (others => '0');
else
poll_addr_q <= poll_addr_q + '1';
end if;
else
mmio_ack_q <= '1';
rd_pending_q <= '0';
end if;
if nvme_q = '0' then
mmio_error_q <= kx_d_i.M_AXI_BRESP;
else
mmio_error_q <= nx_d_i.M_AXI_BRESP;
end if;
end if;
when AXI_WR_DATA =>
if (kx_d_i.M_AXI_AWREADY = '1' and nvme_q = '0') or (nx_d_i.M_AXI_AWREADY = '1' and nvme_q = '1') then
axi_awvalid_q <= '0';
end if;
if (kx_d_i.M_AXI_WREADY = '1' and nvme_q = '0') or (nx_d_i.M_AXI_WREADY = '1' and nvme_q = '1') then
axi_wvalid_q <= '0';
end if;
if axi_awvalid_q = '0' and axi_wvalid_q = '0' then
axi_master_fsm_q <= AXI_WR_RESP;
axi_bready_q <= '1';
end if;
when AXI_WR_RESP =>
if (kx_d_i.M_AXI_BVALID = '1' and nvme_q = '0') or (nx_d_i.M_AXI_BVALID = '1' and nvme_q = '1') then
axi_master_fsm_q <= AXI_IDLE;
axi_bready_q <= '0';
mmio_ack_q <= '1';
if nvme_q = '0' then
mmio_error_q <= kx_d_i.M_AXI_BRESP;
else
mmio_error_q <= nx_d_i.M_AXI_BRESP;
end if;
wr_pending_q <= '0';
end if;
when others => null;
end case;
if jx_c_i.check_for_idle(to_integer(unsigned(poll_addr_q))) = '0' then
if poll_addr_q = max_actions then
poll_addr_q <= (others => '0');
else
poll_addr_q <= poll_addr_q + '1';
end if;
end if;
end if; -- rst
end if; -- clk
end process;
-- process to observe which action is running
-- if an action goes to idle, notify job manager
process(clk)
begin
if rising_edge(clk) then
idle_vector_q(4) <= '0';
if rst = '1' then
running_status_q <= (others => '0');
else
wr_pulse_q <= mmx_d_i.wr_strobe;
wr_addr_q <= std_logic_vector(mmx_d_i.addr(17 downto 0));
start_bit_q <= std_logic(mmx_d_i.data(0));
if wr_pulse_q = '1' and wr_addr_q(11 downto 0) = x"000" and
wr_addr_q(17 downto 16) = "01" then
-- capture which action was started
running_status_q(to_integer(unsigned(wr_addr_q(15 downto 12)))) <= start_bit_q;
end if;
if mmio_rd_data_q(2) = '1' and axi_address_q(11 downto 0 ) = x"000" and
rvalid_q = '1' and
running_status_q(to_integer(unsigned(axi_address_q(15 downto 12)))) = '1' then
-- turn off the running bit
running_status_q(to_integer(unsigned(axi_address_q(15 downto 12)))) <= '0';
-- valid pulse
idle_vector_q(4) <= jx_c_i.check_for_idle(to_integer(unsigned(axi_address_q(15 downto 19))));
idle_vector_q(3 downto 0) <= axi_address_q(15 downto 12);
end if;
end if;
end if;
end process;
end implementation;
| apache-2.0 | 55f93dec144632409ab30de040620980 | 0.429431 | 3.502502 | false | false | false | false |
VLSI-EDA/PoC-Examples | projects/mem/sdram/memtest_s3esk/my_project.vhdl | 3 | 1,661 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This files bases on template lib/PoC/src/common/my_project.vhdl.template
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_project is
-- Change these lines to setup configuration.
constant MY_PROJECT_DIR : string := "CHANGE THIS"; -- e.g. "d:/vhdl/myproject/", "/home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. "WINDOWS", "LINUX"
end package;
| apache-2.0 | 65d719b66d8d2bb999f4ac4e838bbb78 | 0.584588 | 4.280928 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/cores/dec_to_fir_mux_v1_0/tb/full_tb.vhd | 2 | 2,476 | ----------------------------------------------------------------------------------
--
-- full_tb.vhd
--
-- (c) 2015
-- L. Schrittwieser
-- N. Huesser
--
----------------------------------------------------------------------------------
--
-- A testbench to test the logger core with real inputs.
--
----------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library UNIMACRO;
use UNIMACRO.VCOMPONENTS.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
entity full_tb is
end full_tb;
architecture Behavioral of full_tb is
-- TODO:
-- create testsignals here
signal tbClkxC : std_logic := '0';
signal tbRstxRB : std_logic := '0';
signal tbDataxD : std_logic_vector(31 downto 0) := (others => '0');
signal tbCntxD: signed(15 downto 0) := to_signed(-430, 16);
signal tbValidxS : std_logic := '0';
signal tbReadyxS: std_logic := '0';
signal tbData0xDO: std_logic_vector(15 downto 0) := (others => '0');
signal tbData1xDO: std_logic_vector(15 downto 0) := (others => '0');
signal tbStrobexS: std_logic := '0';
begin
-- generate clock
tbClkxC <= not tbClkxC after 1ns;
tbDataxD <= std_logic_vector(tbCntxD) & std_logic_vector(tbCntxD);
DUT : entity work.axis_to_data_lanes
generic map (
Decimation => 3
)
port map (
ClkxCI => tbClkxC,
RstxRBI => tbRstxRB,
AxiTDataxDI=> tbDataxD,
AxiTValid => tbValidxS,
AxiTReady => tbReadyxS,
Data0xDO => tbData0xDO,
Data1xDO => tbData1xDO,
DataStrobexDO => tbStrobexS
);
process
begin
-- TODO:
-- write chain of events here
tbRstxRB <= '0';
wait until rising_edge(tbClkxC);
wait until rising_edge(tbClkxC);
tbRstxRB <= '1';
wait until rising_edge(tbClkxC);
tbValidxS <= '0';
for i in 0 to 30 loop
wait until rising_edge(tbClkxC);
end loop;
tbValidxS <= '1';
for i in 0 to 30 loop
wait until rising_edge(tbClkxC);
end loop;
wait;
end process;
process(tbClkxC, tbRstxRB, tbCntxD)
begin
if rising_edge(tbClkxC) then
tbCntxD <= to_signed(-430, 16);
if tbRstxRB = '1' then
tbCntxD <= tbCntxD + 1;
end if;
end if;
end process;
end Behavioral;
| mit | 594d091af21e095ff45acf3cd0658699 | 0.523425 | 4.026016 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_0/RAT_Mux4x1_8_0_0_sim_netlist.vhdl | 2 | 4,781 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:46:24 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_0/RAT_Mux4x1_8_0_0_sim_netlist.vhdl
-- Design : RAT_Mux4x1_8_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_8_0_0_Mux4x1_8 is
port (
X : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
A : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of RAT_Mux4x1_8_0_0_Mux4x1_8 : entity is "Mux4x1_8";
end RAT_Mux4x1_8_0_0_Mux4x1_8;
architecture STRUCTURE of RAT_Mux4x1_8_0_0_Mux4x1_8 is
begin
\X[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(0),
I1 => B(0),
I2 => C(0),
I3 => SEL(1),
I4 => A(0),
I5 => SEL(0),
O => X(0)
);
\X[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(1),
I1 => B(1),
I2 => C(1),
I3 => SEL(1),
I4 => A(1),
I5 => SEL(0),
O => X(1)
);
\X[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(2),
I1 => B(2),
I2 => C(2),
I3 => SEL(1),
I4 => A(2),
I5 => SEL(0),
O => X(2)
);
\X[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(3),
I1 => B(3),
I2 => C(3),
I3 => SEL(1),
I4 => A(3),
I5 => SEL(0),
O => X(3)
);
\X[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(4),
I1 => B(4),
I2 => C(4),
I3 => SEL(1),
I4 => A(4),
I5 => SEL(0),
O => X(4)
);
\X[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(5),
I1 => B(5),
I2 => C(5),
I3 => SEL(1),
I4 => A(5),
I5 => SEL(0),
O => X(5)
);
\X[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(6),
I1 => B(6),
I2 => C(6),
I3 => SEL(1),
I4 => A(6),
I5 => SEL(0),
O => X(6)
);
\X[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => D(7),
I1 => B(7),
I2 => C(7),
I3 => SEL(1),
I4 => A(7),
I5 => SEL(0),
O => X(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_Mux4x1_8_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
C : in STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
SEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
X : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_Mux4x1_8_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_Mux4x1_8_0_0 : entity is "RAT_Mux4x1_8_0_0,Mux4x1_8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_Mux4x1_8_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_Mux4x1_8_0_0 : entity is "Mux4x1_8,Vivado 2016.4";
end RAT_Mux4x1_8_0_0;
architecture STRUCTURE of RAT_Mux4x1_8_0_0 is
begin
U0: entity work.RAT_Mux4x1_8_0_0_Mux4x1_8
port map (
A(7 downto 0) => A(7 downto 0),
B(7 downto 0) => B(7 downto 0),
C(7 downto 0) => C(7 downto 0),
D(7 downto 0) => D(7 downto 0),
SEL(1 downto 0) => SEL(1 downto 0),
X(7 downto 0) => X(7 downto 0)
);
end STRUCTURE;
| mit | b2d9c572ab50e013e15e630393a651b7 | 0.526668 | 2.913467 | false | false | false | false |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/synth/RAT_ControlUnit_0_0.vhd | 1 | 7,164 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:ControlUnit:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_ControlUnit_0_0 IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_RESET : OUT STD_LOGIC;
SP_INCR : OUT STD_LOGIC;
SP_DECR : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SCR_DATA_SEL : OUT STD_LOGIC;
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END RAT_ControlUnit_0_0;
ARCHITECTURE RAT_ControlUnit_0_0_arch OF RAT_ControlUnit_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ControlUnit IS
PORT (
CLK : IN STD_LOGIC;
C : IN STD_LOGIC;
Z : IN STD_LOGIC;
INT : IN STD_LOGIC;
RST : IN STD_LOGIC;
OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
PC_LD : OUT STD_LOGIC;
PC_INC : OUT STD_LOGIC;
PC_RESET : OUT STD_LOGIC;
PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SP_LD : OUT STD_LOGIC;
SP_RESET : OUT STD_LOGIC;
SP_INCR : OUT STD_LOGIC;
SP_DECR : OUT STD_LOGIC;
RF_WR : OUT STD_LOGIC;
RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ALU_OPY_SEL : OUT STD_LOGIC;
SCR_WR : OUT STD_LOGIC;
SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SCR_DATA_SEL : OUT STD_LOGIC;
C_FLAG_SEL : OUT STD_LOGIC;
C_FLAG_LD : OUT STD_LOGIC;
C_FLAG_SET : OUT STD_LOGIC;
C_FLAG_CLR : OUT STD_LOGIC;
SHAD_C_LD : OUT STD_LOGIC;
Z_FLAG_SEL : OUT STD_LOGIC;
Z_FLAG_LD : OUT STD_LOGIC;
Z_FLAG_SET : OUT STD_LOGIC;
Z_FLAG_CLR : OUT STD_LOGIC;
SHAD_Z_LD : OUT STD_LOGIC;
I_FLAG_SET : OUT STD_LOGIC;
I_FLAG_CLR : OUT STD_LOGIC;
IO_OE : OUT STD_LOGIC
);
END COMPONENT ControlUnit;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "ControlUnit,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_ControlUnit_0_0_arch : ARCHITECTURE IS "RAT_ControlUnit_0_0,ControlUnit,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "RAT_ControlUnit_0_0,ControlUnit,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=ControlUnit,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST";
ATTRIBUTE X_INTERFACE_INFO OF PC_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 PC_RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF SP_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 SP_RESET RST";
BEGIN
U0 : ControlUnit
PORT MAP (
CLK => CLK,
C => C,
Z => Z,
INT => INT,
RST => RST,
OPCODE_HI_5 => OPCODE_HI_5,
OPCODE_LO_2 => OPCODE_LO_2,
PC_LD => PC_LD,
PC_INC => PC_INC,
PC_RESET => PC_RESET,
PC_MUX_SEL => PC_MUX_SEL,
SP_LD => SP_LD,
SP_RESET => SP_RESET,
SP_INCR => SP_INCR,
SP_DECR => SP_DECR,
RF_WR => RF_WR,
RF_WR_SEL => RF_WR_SEL,
ALU_SEL => ALU_SEL,
ALU_OPY_SEL => ALU_OPY_SEL,
SCR_WR => SCR_WR,
SCR_ADDR_SEL => SCR_ADDR_SEL,
SCR_DATA_SEL => SCR_DATA_SEL,
C_FLAG_SEL => C_FLAG_SEL,
C_FLAG_LD => C_FLAG_LD,
C_FLAG_SET => C_FLAG_SET,
C_FLAG_CLR => C_FLAG_CLR,
SHAD_C_LD => SHAD_C_LD,
Z_FLAG_SEL => Z_FLAG_SEL,
Z_FLAG_LD => Z_FLAG_LD,
Z_FLAG_SET => Z_FLAG_SET,
Z_FLAG_CLR => Z_FLAG_CLR,
SHAD_Z_LD => SHAD_Z_LD,
I_FLAG_SET => I_FLAG_SET,
I_FLAG_CLR => I_FLAG_CLR,
IO_OE => IO_OE
);
END RAT_ControlUnit_0_0_arch;
| mit | ca688dc15027b202e52891e1abfb2828 | 0.659687 | 3.325905 | false | false | false | false |
MiddleMan5/233 | Experiments/IP_Repo/Program Counter/sim/Program_Counter_Mux4x1_0_1.vhd | 2 | 3,425 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Mux4x1:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Mux4x1_0_1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END Program_Counter_Mux4x1_0_1;
ARCHITECTURE Program_Counter_Mux4x1_0_1_arch OF Program_Counter_Mux4x1_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Mux4x1_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Mux4x1 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
D : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT Mux4x1;
BEGIN
U0 : Mux4x1
PORT MAP (
A => A,
B => B,
C => C,
D => D,
SEL => SEL,
X => X
);
END Program_Counter_Mux4x1_0_1_arch;
| mit | be689db3016393a305f666dcec4f9fcf | 0.717664 | 3.839686 | false | false | false | false |
alpenwasser/pitaya | firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_dds_compiler_0_1/sim/design_1_dds_compiler_0_1.vhd | 2 | 8,862 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_1 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_dds_compiler_0_1;
ARCHITECTURE design_1_dds_compiler_0_1_arch OF design_1_dds_compiler_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 29,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 1,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "10100111110001011,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 1,
C_M_PHASE_TDATA_WIDTH => 32,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tvalid => m_axis_phase_tvalid,
m_axis_phase_tready => '0',
m_axis_phase_tdata => m_axis_phase_tdata
);
END design_1_dds_compiler_0_1_arch;
| mit | 7f4dff872cbf55c2c27bcd1caee8c2e0 | 0.647371 | 3.279793 | false | true | false | false |
David-Estevez/spaceinvaders | src/toneGenerator_tb.vhd | 1 | 1,759 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY toneGenerator_tb IS
END toneGenerator_tb;
ARCHITECTURE behavior OF toneGenerator_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toneGenerator
PORT(
clk : IN std_logic;
reset : IN std_logic;
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
q : INOUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
--BiDirs
signal q : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toneGenerator PORT MAP (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
d => d,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
a <= '1';
wait for clk_period;
a <= '0';
wait for 500 ms;
b <= '1';
wait for clk_period;
b <= '0';
wait;
end process;
END;
| gpl-3.0 | ca0f12a138d50be4f4ac468ffd7f3ada | 0.520182 | 3.718816 | false | false | false | false |
David-Estevez/spaceinvaders | src/edgeDetector.vhd | 1 | 1,252 | ----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity edgeDetector is
port( clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC );
end edgeDetector;
architecture Behavioral of edgeDetector is
begin
process( clk, reset)
variable currentState: STD_LOGIC;
variable previousState: STD_LOGIC;
begin
-- Reset
if reset = '1' then
currentState := '0';
previousState := '0';
detected <= '0';
-- Synchronous behaviour
elsif clk'Event and clk = '1' then
if enable = '1' then
-- Update states
previousState := currentState;
currentState := input;
-- If the current state is high, and the previous state was low,
-- an edge has arrived:
detected <= currentState and not previousState;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7d13c9da3948692f6394ab04171aa309 | 0.548439 | 4.108553 | false | false | false | false |
MiddleMan5/233 | Experiments/IP_Repo/Program Counter/src/Program_Counter_Counter10bit_0_1.vhd | 2 | 3,921 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: CPE233:F17:Counter10bit:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Program_Counter_Counter10bit_0_1 IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END Program_Counter_Counter10bit_0_1;
ARCHITECTURE Program_Counter_Counter10bit_0_1_arch OF Program_Counter_Counter10bit_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Program_Counter_Counter10bit_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT Counter10bit IS
PORT (
Din : IN STD_LOGIC_VECTOR(0 TO 9);
LOAD : IN STD_LOGIC;
INC : IN STD_LOGIC;
RESET : IN STD_LOGIC;
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(0 TO 9)
);
END COMPONENT Counter10bit;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Program_Counter_Counter10bit_0_1_arch: ARCHITECTURE IS "Counter10bit,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Program_Counter_Counter10bit_0_1_arch : ARCHITECTURE IS "Program_Counter_Counter10bit_0_1,Counter10bit,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : Counter10bit
PORT MAP (
Din => Din,
LOAD => LOAD,
INC => INC,
RESET => RESET,
CLK => CLK,
COUNT => COUNT
);
END Program_Counter_Counter10bit_0_1_arch;
| mit | b9c71d8601005d3e2f7bef5eceadbc08 | 0.731446 | 3.94864 | false | false | false | false |
marcoep/MusicBoxNano | hdl/ResetSync.vhd | 1 | 3,130 |
-------------------------------------------------------------------------------
-- Title : Reset Synchronizer Circuit with 4 FFs
-- Project :
-------------------------------------------------------------------------------
-- File : ResetSync.vhd
-- Author : <marcoep@ITET-IEF-W03>
-- Company : Institute of Electromagnetic Fields, ETH Zurich
-- Created : 2016-01-09
-- Last update: 2016-01-09
-- Platform : Mentor Graphics ModelSim (simulation), Xilinx Vivado (synthesis, implementation)
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- The Reset is asynchronously asserted logic high. The reset pulse is
-- guaranteed to last at least 4 Clk_CI cycles. Then, the reset is desasserted
-- synchronously with Clk_CI.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Marco Eppenberger <[email protected]>
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-01-09 1.0 marcoep Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ResetSync is
port (
---------------------------------------------------------------------------
-- Clock to synchronize reset to
---------------------------------------------------------------------------
Clk_CI : in std_logic;
---------------------------------------------------------------------------
-- Reset Inputs
-- As long as ClkStable_RI is low, reset is asserted
-- As long as OtherReset_RI is high, reset is asserted
---------------------------------------------------------------------------
ClkStable_RI : in std_logic;
OtherReset_RI : in std_logic;
---------------------------------------------------------------------------
-- Syncronized Reset Out
-- Active high synchronized reset.
-- SyncReset_SO is desasserted 4 cycles after reset condition is lifted
---------------------------------------------------------------------------
SyncReset_SO : out std_logic);
end entity ResetSync;
architecture RTL of ResetSync is
signal AsyncReset_R : std_logic := '0';
signal ShiftRst_SN, ShiftRst_SP : std_logic_vector(3 downto 0) := (others => '1');
begin -- architecture RTL
-- reset condition
AsyncReset_R <= OtherReset_RI or not(ClkStable_RI);
-- Feed 0 to first FF
ShiftRst_SN(0) <= '0';
-- connect FFs
ShiftRst_SN(3 downto 1) <= ShiftRst_SP(2 downto 0);
-- FF chain
ResetFFs : process (Clk_CI, AsyncReset_R) is
begin -- process ResetFFs
if AsyncReset_R = '1' then -- asynchronous active high reset
ShiftRst_SP <= (others => '1');
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
ShiftRst_SP <= ShiftRst_SN;
end if;
end process ResetFFs;
-- assign output
SyncReset_SO <= ShiftRst_SP(3);
end architecture RTL;
| gpl-3.0 | 0e048b1e72e1350cb4a780d0b43fb9ba | 0.450799 | 5.008 | false | false | false | false |
Subsets and Splits