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wifidar/wifidar_fpga | src/dac_section/dac_controller.vhd | 1 | 2,747 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_controller is
generic(
sine_length_bits: integer := 10;
num_channels: integer := 1
);
port(
-- sine wave control related
freq_mult: out std_logic_vector((num_channels * 10) - 1 downto 0) := (others => '0');
offset_adjust: out std_logic_vector((num_channels * 12) - 1 downto 0);
amplitude_adjust: out std_logic_vector((num_channels * 6) - 1 downto 0);
-- control related
current_mode: in std_logic_vector (1 downto 0); -- 00 = freq, 01 = phase, 10 = amplitude
current_channel: in std_logic_vector(1 downto 0);
adjust: in std_logic_vector(1 downto 0); -- pulses for adjustment of values, 0 up, 1 down
clk: in std_logic
);
end dac_controller;
architecture Behavioral of dac_controller is
type freq_array_t is array (0 to num_channels - 1) of std_logic_vector(9 downto 0);
type offset_array_t is array (0 to num_channels - 1) of std_logic_vector(11 downto 0);
type amplitude_array_t is array (0 to num_channels - 1) of std_logic_vector(5 downto 0);
signal freq_array: freq_array_t := (others => ("0000000100")); -- :- 4
signal offset_array: offset_array_t := (others => ("101001111000"));
signal amplitude_array: amplitude_array_t := (others => ("010000")); -- := 16
begin
mode_handle: process(clk)
begin
if(rising_edge(clk)) then
for I in 0 to num_channels - 1 loop
if(I = to_integer(unsigned(current_channel))) then
if(current_mode = "00") then -- freq adjust
if(adjust(0) = '1') then
freq_array(I) <= std_logic_vector(unsigned(freq_array(I)) + 1);
elsif(adjust(1) = '1') then
freq_array(I) <= std_logic_vector(unsigned(freq_array(I)) - 1);
end if;
elsif(current_mode = "01") then -- offset adjust
if(adjust(0) = '1') then
offset_array(I) <= std_logic_vector(unsigned(offset_array(I)) + 10);
elsif(adjust(1) = '1') then
offset_array(I) <= std_logic_vector(unsigned(offset_array(I)) - 10);
end if;
elsif(current_mode= "10") then -- amplitude adjust
if(adjust(0) = '1') then
amplitude_array(I) <= std_logic_vector(unsigned(amplitude_array(I)) + 1);
elsif(adjust(1) = '1') then
amplitude_array(I) <= std_logic_vector(unsigned(amplitude_array(I)) - 1);
end if;
end if;
end if;
end loop;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
for I in 0 to num_channels - 1 loop
freq_mult((10 + (I * 10)) - 1 downto (I * 10)) <= freq_array(I);
offset_adjust((12 + (I * 8)) - 1 downto (I * 8)) <= offset_array(I);
amplitude_adjust((6 + (I * 6)) - 1 downto (I * 6)) <= amplitude_array(I);
end loop;
end if;
end process;
end Behavioral;
| mit | c066338a82a1972e81728766ab58e3c3 | 0.626138 | 2.989119 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/process_lifting_test_conditional.vhd | 2 | 836 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fnord : block
constant f : natural := 11;
begin
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result(n);
foo : block
constant i : natural := 10;
begin
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result(n);
end block foo;
end block fnord;
end beh;
| gpl-3.0 | 5e40190dd7aa14444a656f0da200a3fd | 0.539474 | 3.24031 | false | false | false | false |
db-electronics/SDRAMController | src/SDRAMcontroller.vhd | 1 | 13,798 | -- Title: SDRAMController.vhd
-- Original Author: Matthew Hagerty
-- Modified by: René Richard
-- Description:
--
-- LICENSE
--
-- This file is part of SDRAMController.
-- TDSN76489 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- Foobar is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with SDRAMController. If not, see <http://www.gnu.org/licenses/>.
--
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity SDRAMController is
port(
-- Host side
clk_100m0_i : in std_logic; -- Master clock
reset_i : in std_logic := '0'; -- Reset, active high
refresh_i : in std_logic := '0'; -- Initiate a refresh cycle, active high
rw_i : in std_logic := '0'; -- Initiate a read or write operation, active high
we_i : in std_logic := '0'; -- Write enable, active low
addr_i : in std_logic_vector(23 downto 0) := (others => '0'); -- Address from host to SDRAM
data_i : in std_logic_vector(15 downto 0) := (others => '0'); -- Data from host to SDRAM
ub_i : in std_logic; -- Data upper byte enable, active low
lb_i : in std_logic; -- Data lower byte enable, active low
ready_o : out std_logic := '0'; -- Set to '1' when the memory is ready
done_o : out std_logic := '0'; -- Read, write, or refresh, operation is done
data_o : out std_logic_vector(15 downto 0); -- Data from SDRAM to host
-- SDRAM side
sdCke_o : out std_logic; -- Clock-enable to SDRAM
sdCe_bo : out std_logic; -- Chip-select to SDRAM
sdRas_bo : out std_logic; -- SDRAM row address strobe
sdCas_bo : out std_logic; -- SDRAM column address strobe
sdWe_bo : out std_logic; -- SDRAM write enable
sdBs_o : out std_logic_vector(1 downto 0); -- SDRAM bank address
sdAddr_o : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sdData_io : inout std_logic_vector(15 downto 0); -- Data to/from SDRAM
sdDqmh_o : out std_logic; -- Enable upper-byte of SDRAM databus if true
sdDqml_o : out std_logic -- Enable lower-byte of SDRAM databus if true
);
end entity;
architecture SDRAMController_a of SDRAMController is
-- SDRAM controller states.
type fsm_state_type is (
ST_INIT_WAIT, ST_INIT_PRECHARGE, ST_INIT_REFRESH1, ST_INIT_MODE, ST_INIT_REFRESH2,
ST_IDLE, ST_REFRESH, ST_ACTIVATE, ST_RCD, ST_RW, ST_RAS1, ST_RAS2, ST_PRECHARGE);
signal state_r, state_x : fsm_state_type := ST_INIT_WAIT;
-- SDRAM mode register data sent on the address bus.
--
-- | A12-A10 | A9 | A8 A7 | A6 A5 A4 | A3 | A2 A1 A0 |
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
-- 0 0 0 0 0 0 0 1 0 0 0 0 0
constant MODE_REG : std_logic_vector(12 downto 0) := "000" & "0" & "00" & "010" & "0" & "000";
-- SDRAM commands combine SDRAM inputs: cs, ras, cas, we.
subtype cmd_type is unsigned(3 downto 0);
constant CMD_ACTIVATE : cmd_type := "0011";
constant CMD_PRECHARGE : cmd_type := "0010";
constant CMD_WRITE : cmd_type := "0100";
constant CMD_READ : cmd_type := "0101";
constant CMD_MODE : cmd_type := "0000";
constant CMD_NOP : cmd_type := "0111";
constant CMD_REFRESH : cmd_type := "0001";
signal cmd_r : cmd_type;
signal cmd_x : cmd_type;
signal bank_s : std_logic_vector(1 downto 0);
signal row_s : std_logic_vector(12 downto 0);
signal col_s : std_logic_vector(8 downto 0);
signal addr_r : std_logic_vector(12 downto 0);
signal addr_x : std_logic_vector(12 downto 0); -- SDRAM row/column address.
signal sd_dout_r : std_logic_vector(15 downto 0);
signal sd_dout_x : std_logic_vector(15 downto 0);
signal sd_busdir_r : std_logic;
signal sd_busdir_x : std_logic;
signal timer_r, timer_x : natural range 0 to 20000 := 0;
signal refcnt_r, refcnt_x : natural range 0 to 7 := 0;
signal bank_r, bank_x : std_logic_vector(1 downto 0);
signal cke_r, cke_x : std_logic;
signal sd_dqmu_r, sd_dqmu_x : std_logic;
signal sd_dqml_r, sd_dqml_x : std_logic;
signal ready_r, ready_x : std_logic;
begin
-- SDRAM signals.
(sdCe_bo, sdRas_bo, sdCas_bo, sdWe_bo) <= cmd_r; -- SDRAM operation control bits
sdCke_o <= cke_r; -- SDRAM clock enable
sdBs_o <= bank_r; -- SDRAM bank address
sdAddr_o <= addr_r; -- SDRAM address
sdData_io <= sd_dout_r when sd_busdir_r = '1' else (others => 'Z'); -- SDRAM data bus.
sdDqmh_o <= sd_dqmu_r; -- SDRAM high data byte enable, active low
sdDqml_o <= sd_dqml_r; -- SDRAM low date byte enable, active low
ready_o <= ready_r;
-- Data back to host, not buffered and must be latched when done_o == '1'.
data_o <= sdData_io;
-- 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 09 | 08 07 06 05 04 03 02 01 00 |
-- BS0 BS1 | ROW (A12-A0) 8192 rows | COL (A8-A0) 512 cols |
bank_s <= addr_i(23 downto 22);
row_s <= addr_i(21 downto 9);
col_s <= addr_i(8 downto 0);
-- When rw_i activates:
-- hold_i | active_r
-- 0 | 0 -> 0 activate the row, issue read/write, precharge all rows when done
-- 1 | 0 -> 1 activate the row, issue read/write, do not precharage when done
-- 1 | 1 -> 1 issue read/write, do not precharge when done
-- 0 | 1 -> 0 issue read/write, precharge all rows when done
--
-- Thus, for a "one time" read / write, hold_i should be low. For a series of reads / writes
-- to the same bank, hold_i should be held high for all reads / writes, but then brought
-- low for the final read / write.
process (
state_r, timer_r, refcnt_r, cke_r, addr_r, sd_dout_r, sd_busdir_r, sd_dqmu_r, sd_dqml_r, ready_r,
bank_s, row_s, col_s,
rw_i, refresh_i, addr_i, data_i, we_i, ub_i, lb_i )
begin
state_x <= state_r; -- Stay in the same state unless changed.
timer_x <= timer_r; -- Hold the cycle timer by default.
refcnt_x <= refcnt_r; -- Hold the refresh timer by default.
cke_x <= cke_r; -- Stay in the same clock mode unless changed.
cmd_x <= CMD_NOP; -- Default to NOP unless changed.
bank_x <= bank_r; -- Register the SDRAM bank.
addr_x <= addr_r; -- Register the SDRAM address.
sd_dout_x <= sd_dout_r; -- Register the SDRAM write data.
sd_busdir_x <= sd_busdir_r; -- Register the SDRAM bus tristate control.
sd_dqmu_x <= sd_dqmu_r;
sd_dqml_x <= sd_dqml_r;
ready_x <= ready_r; -- Always ready unless performing initialization.
done_o <= '0'; -- Done tick, single cycle.
if timer_r /= 0 then
timer_x <= timer_r - 1;
else
cke_x <= '1';
bank_x <= bank_s;
addr_x <= "0000" & col_s; -- A10 low for rd/wr commands to suppress auto-precharge.
sd_dqmu_x <= '0';
sd_dqml_x <= '0';
case state_r is
when ST_INIT_WAIT =>
-- 1. Wait 200us with DQM signals high, cmd NOP.
-- 2. Precharge all banks.
-- 3. Eight refresh cycles.
-- 4. Set mode register.
-- 5. Eight refresh cycles.
state_x <= ST_INIT_PRECHARGE;
timer_x <= 20000; -- Wait 200us (20,000 cycles).
-- timer_x <= 2; -- for simulation
sd_dqmu_x <= '1';
sd_dqml_x <= '1';
when ST_INIT_PRECHARGE =>
state_x <= ST_INIT_REFRESH1;
refcnt_x <= 7; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
cmd_x <= CMD_PRECHARGE;
timer_x <= 1; -- Wait 1 cycles plus state overhead for 20ns Trp.
addr_x(10) <= '1'; -- Precharge all banks.
when ST_INIT_REFRESH1 =>
if refcnt_r = 0 then
state_x <= ST_INIT_MODE;
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 6; -- Wait 6 cycles plus state overhead for 70ns refresh.
end if;
when ST_INIT_MODE =>
state_x <= ST_INIT_REFRESH2;
refcnt_x <= 7; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
bank_x <= "00";
addr_x <= MODE_REG;
cmd_x <= CMD_MODE;
timer_x <= 1; -- Trsc == 2 cycles after issuing MODE command.
when ST_INIT_REFRESH2 =>
if refcnt_r = 0 then
state_x <= ST_IDLE;
ready_x <= '1';
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 6; -- Wait 6 cycles plus state overhead for 70ns refresh.
end if;
--
-- Normal Operation
--
when ST_IDLE =>
-- 60ns since activate when coming from PRECHARGE state.
-- 10ns since PRECHARGE. Trp == 20ns min.
if rw_i = '1' then
state_x <= ST_ACTIVATE;
cmd_x <= CMD_ACTIVATE;
addr_x <= row_s; -- Set bank select and row on activate command.
elsif refresh_i = '1' then
state_x <= ST_REFRESH;
cmd_x <= CMD_REFRESH;
timer_x <= 5; -- Wait 5 cycles plus state overhead for 70ns refresh.
end if;
when ST_REFRESH =>
state_x <= ST_IDLE;
done_o <= '1';
when ST_ACTIVATE =>
-- Trc (Active to Active Command Period) is 65ns min.
-- 70ns since activate when coming from PRECHARGE -> IDLE states.
-- 20ns since PRECHARGE.
-- ACTIVATE command is presented to the SDRAM. The command out of this
-- state will be NOP for one cycle.
state_x <= ST_RCD;
sd_dout_x <= data_i; -- Register any write data, even if not used.
when ST_RCD =>
-- 10ns since activate.
-- Trcd == 20ns min. The clock is 10ns, so the requirement is satisfied by this state.
-- READ or WRITE command will be active in the next cycle.
state_x <= ST_RW;
if we_i = '0' then
cmd_x <= CMD_WRITE;
sd_busdir_x <= '1'; -- The SDRAM latches the input data with the command.
sd_dqmu_x <= ub_i;
sd_dqml_x <= lb_i;
else
cmd_x <= CMD_READ;
end if;
when ST_RW =>
-- 20ns since activate.
-- READ or WRITE command presented to SDRAM.
state_x <= ST_RAS1;
sd_busdir_x <= '0';
when ST_RAS1 =>
-- 30ns since activate.
state_x <= ST_RAS2;
when ST_RAS2 =>
-- 40ns since activate.
-- Tras (Active to precharge Command Period) 45ns min.
-- PRECHARGE command will be active in the next cycle.
state_x <= ST_PRECHARGE;
cmd_x <= CMD_PRECHARGE;
addr_x(10) <= '1'; -- Precharge all banks.
when ST_PRECHARGE =>
-- 50ns since activate.
-- PRECHARGE presented to SDRAM.
state_x <= ST_IDLE;
done_o <= '1'; -- Read data is ready and should be latched by the host.
end case;
end if;
end process;
process (clk_100m0_i)
begin
if falling_edge(clk_100m0_i) then
if reset_i = '1' then
state_r <= ST_INIT_WAIT;
timer_r <= 0;
cmd_r <= CMD_NOP;
cke_r <= '0';
ready_r <= '0';
else
state_r <= state_x;
timer_r <= timer_x;
refcnt_r <= refcnt_x;
cke_r <= cke_x; -- CKE to SDRAM.
cmd_r <= cmd_x; -- Command to SDRAM.
bank_r <= bank_x; -- Bank to SDRAM.
addr_r <= addr_x; -- Address to SDRAM.
sd_dout_r <= sd_dout_x; -- Data to SDRAM.
sd_busdir_r <= sd_busdir_x; -- SDRAM bus direction.
sd_dqmu_r <= sd_dqmu_x; -- Upper byte enable to SDRAM.
sd_dqml_r <= sd_dqml_x; -- Lower byte enable to SDRAM.
ready_r <= ready_x;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 37773d6b62eaaad12c3fe9bfea153e7b | 0.512213 | 3.65 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_zc706/gtx/testbench/top_tb.vhdl | 1 | 1,365 | --
-- Xilinx ml605 Minimal Transceiver Testbench
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Top_tb is
end entity Top_tb;
architecture Structural of Top_tb is
constant GTXPERIOD : time := 5 ns;
constant SYSPERIOD : time := 6.25 ns;
signal gtxclkn, gtxclkp : std_logic;
signal sysclkn, sysclkp : std_logic;
signal stop : boolean;
signal dips, leds : std_logic_vector(3 downto 0);
signal txp, txn, rxn, rxp : std_logic;
begin
gtxclk_i : Clock
generic map(PERIOD => GTXPERIOD, RESET_CLKS => 15.0)
port map(clk_o => gtxclkp, rst_o => open, stop_i => stop);
sysclk_i : Clock
generic map(PERIOD => SYSPERIOD, RESET_CLKS => 15.0)
port map(clk_o => sysclkp, rst_o => open, stop_i => stop);
gtxclkn <= not(gtxclkp);
sysclkn <= not(sysclkp);
dut: entity work.top
port map(
sysclk_p_i => sysclkp,
sysclk_n_i => sysclkn,
gtxclk_p_i => gtxclkp,
gtxclk_n_i => gtxclkn,
rx_p_i => '0',
rx_n_i => '0',
tx_p_o => open,
tx_n_o => open,
pbc_i => '0',
dips_i => "1010",
leds_o => open
);
end architecture Structural;
| bsd-3-clause | 9ec606b6b46dd166f928de2e386c5dc4 | 0.572894 | 3.196721 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_serial_input/hdl/industrial_serial_input.vhd | 1 | 11,612 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 30/04/2009
-- File : industrial_serial_input.vhd
--
-- Abstract : This IP manage input serialized by the
-- industrial 8-digital-input serializer : SN65HVS882
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity industrial_serial_input is
---------------------------------------------------------------------------
generic(
id : natural := 1; -- identification register value
wb_size : natural := 16; -- Data port size for wishbone
clk_freq : natural := 133000 -- fpga clock speed
);
port
(
-- Syscon signals
reset : in std_logic ; -- reset
clk : in std_logic ; -- general clock
-- Wishbone signals
wbs_add : in std_logic_vector( 1 downto 0) ; -- address bus
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- interrupt
interrupt : out std_logic ; -- interrupt signal
-- SN65HVS882 controls signals
spi_sip : out std_logic ;
spi_ld_n : out std_logic ;
spi_clk : out std_logic ; -- SPI clock
spi_sop : in std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture industrial_serial_input_1 of industrial_serial_input is
---------------------------------------------------------------------------
-- usefull constants
constant ZERO : std_logic_vector( 31 downto 0) := (others => '0');
-- states type
type state is (spi_init_state,spi_load_state,spi_read7_state,spi_read_state,spi_end_state);
signal state_reg : state;
signal next_state_reg : state;
-- registers addresses
constant REG_DATA : std_logic_vector( 1 downto 0) := "00"; -- |x[15:9]|int_en|data[7:0]
constant REG_READ_PER : std_logic_vector( 1 downto 0) := "01"; -- read period = reg x bus period
constant REG_BUS_PER : std_logic_vector( 1 downto 0) := "10"; -- bus period = reg x clock period
constant REG_ID : std_logic_vector( 1 downto 0) := "11"; -- identification register
constant BUS_PER_DFLT : std_logic_vector(15 downto 0) := x"010A";
constant READ_PER_DFLT: std_logic_vector(15 downto 0) := x"0020";
constant COUNT_SIZE : natural := 13;
-- registers
signal data_reg : std_logic_vector( 7 downto 0):= x"00";
signal int_en : std_logic ;
signal read_per : std_logic_vector( wb_size-1 downto 0);
signal bus_per : std_logic_vector( wb_size-1 downto 0);
signal data : std_logic_vector( 7 downto 0):= x"00";
-- local clocks signals
signal local_clk : std_logic ;
signal clock_rise_pulse : std_logic ;
signal clock_fall_pulse : std_logic ;
-- spi signals
signal spi_read_pulse : std_logic ;
signal spi_read_count : natural range 0 to 8;
-- wisbone acks
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
-- read process
read_p : process (clk,reset)
begin
if reset = '1' then
wbs_readdata <= (others => '0');
elsif rising_edge(clk) then
if (wbs_strobe and (not wbs_write) and wbs_cycle) = '1' then
read_ack <= '1';
case wbs_add is
when REG_DATA =>
-- change data_reg bits order to match card route
wbs_readdata <=
ZERO(6 downto 0)&int_en&
data_reg(5)&
data_reg(6)&
data_reg(7)&
data_reg(4 downto 0);
when REG_READ_PER =>
wbs_readdata <= read_per;
when REG_BUS_PER =>
wbs_readdata <= bus_per;
when REG_ID =>
wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
when others =>
wbs_readdata <= (others => '0');
end case;
else
read_ack <= '0';
wbs_readdata <= (others => '0');
end if;
end if;
end process read_p;
-- write process
write_p : process (clk, reset)
begin
if reset = '1' then
int_en <= '0';
-- defaut values
bus_per <= BUS_PER_DFLT; -- 266 x 3.759 = 1MHz
read_per <= READ_PER_DFLT;
elsif rising_edge(clk) then
if (wbs_strobe and wbs_write and wbs_cycle) = '1' then
case wbs_add is
when REG_DATA =>
int_en <= wbs_writedata(8);
write_ack <= '1';
when REG_READ_PER =>
read_per <= wbs_writedata;
write_ack <= '1';
when REG_BUS_PER =>
if wbs_writedata = x"0000" then
bus_Per <= x"0001";
else
bus_per <= wbs_writedata;
end if;
write_ack <= '1';
when others =>
write_ack <= '1';
end case;
else
write_ack <= '0';
end if;
end if;
end process write_p;
wbs_ack <= read_ack or write_ack;
-- SPI clock generator
clock_divider : process (clk,reset)
variable count : natural range 0 to (2**COUNT_SIZE)-1;
begin
if reset = '1' then
count := 0;
local_clk <= '0';
clock_rise_pulse <= '0';
clock_fall_pulse <= '0';
elsif rising_edge(clk) then
if (count < to_integer(unsigned(bus_per))) then
count := count + 1;
local_clk <= local_clk;
clock_rise_pulse <= '0';
clock_fall_pulse <= '0';
else
clock_fall_pulse <= local_clk;
clock_rise_pulse <= not local_clk;
local_clk <= not local_clk;
count := 0;
end if;
end if;
end process clock_divider;
-- read_pulse generator
read_pulse_p : process (clk,reset)
variable count : natural range 0 to (2**COUNT_SIZE)-1;
begin
if reset = '1' then
count := 0;
spi_read_pulse <= '0';
elsif rising_edge(clk) then
if (count <= to_integer(unsigned(read_per))) then
if clock_rise_pulse = '1' then
count := count + 1;
spi_read_pulse <= spi_read_pulse;
elsif clock_fall_pulse = '1' then
spi_read_pulse <= '0';
end if;
elsif clock_rise_pulse = '1' then
count := 0;
spi_read_pulse <= '1';
end if;
end if;
end process read_pulse_p;
-- interrupt management process
interrupt_p : process (clk,reset)
begin
if reset = '1' then
interrupt <= '0';
elsif rising_edge(clk) then
if data_reg /= data and (state_reg = spi_end_state) then
interrupt <= int_en; -- rise interrupt if data reg is changed
elsif (read_ack = '1') and (wbs_add = REG_DATA) then
interrupt <= '0'; -- reset interrupt when data register is read
end if;
end if;
end process interrupt_p;
----------------------------
-- spi read state machine --
----------------------------
-- state register
spi_state_register_p : process (clk,reset)
begin
if reset = '1' then
state_reg <= spi_init_state;
elsif rising_edge(clk) then
state_reg <= next_state_reg;
end if;
end process spi_state_register_p;
-- next-state logic
nstate_p : process (state_reg,spi_read_pulse,clock_rise_pulse,spi_read_count)
begin
case state_reg is
when spi_init_state =>
if spi_read_pulse = '1' then
next_state_reg <= spi_load_state;
else
next_state_reg <= spi_init_state;
end if;
when spi_load_state =>
if spi_read_pulse = '0' and clock_rise_pulse = '1' then
next_state_reg <= spi_read7_state;
else
next_state_reg <= spi_load_state;
end if;
when spi_read7_state =>
if clock_rise_pulse = '1' then
next_state_reg <= spi_read_state;
else
next_state_reg <= spi_read7_state;
end if;
when spi_read_state =>
if spi_read_count > 6 then
next_state_reg <= spi_end_state;
else
next_state_reg <= spi_read_state;
end if;
when spi_end_state =>
next_state_reg <= spi_init_state;
when others =>
next_state_reg <= spi_init_state;
end case;
end process nstate_p;
-- output logic
--output_p : process (state_reg,spi_sop,data,local_clk)
output_p : process (clk,reset)
begin
if reset = '1' then
data <= (others => '0');
spi_clk <= '0';
elsif rising_edge(clk) then
case state_reg is
when spi_init_state =>
data <= (others => '0');
spi_clk <= '0';
when spi_load_state =>
spi_clk <= '0';
when spi_read7_state =>
spi_clk <= '0';
data(0) <= spi_sop;
when spi_read_state =>
spi_clk <= local_clk;
if clock_fall_pulse = '1' then
data <= data(6 downto 0)&spi_sop;
end if;
when spi_end_state =>
data_reg <= data;
spi_clk <= '0';
when others =>
spi_clk <= local_clk;
end case;
end if;
end process output_p;
spi_ld_n <= '0' when state_reg = spi_load_state else '1' ;
spi_sip <= '1';
-- read count
read_count_p : process (clk, reset)
begin
if reset = '1' then
spi_read_count <= 0;
elsif rising_edge(clk) then
if state_reg = spi_read_state then
if clock_rise_pulse = '1' then
spi_read_count <= spi_read_count + 1;
else
spi_read_count <= spi_read_count;
end if;
else
spi_read_count <= 0;
end if;
end if;
end process read_count_p;
end architecture industrial_serial_input_1;
| lgpl-2.1 | f4d46d46808a6984aebf97fe5471c9df | 0.450482 | 4.244152 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/lcd.vhd | 3 | 1,538 | -------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity lcd is
port(rst : in std_logic;
clk : in std_logic;
-- LCD bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LCD control/data interface
lcd_out : out std_logic_vector(LCD_PW-1 downto 0)
);
end lcd;
architecture rtl of lcd is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
lcd_out <= (others => '0');
elsif rising_edge(clk) then
if bus_in.we = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
lcd_out <= bus_in.addr & bus_in.data(3);
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 7a3ed1d4a468ea16d31a1a58b44bcb00 | 0.392718 | 4.457971 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_case_dff_nested.vhd | 1 | 1,080 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
baz : out std_logic_vector(7 downto 0);
clock : in std_logic;
clock2 : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
baz <= "00101100";
case "100" is
when "000" =>
if rising_edge(clock) then
if rising_edge(clock2) then
A <= '0';
end if;
end if;
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
| gpl-3.0 | d5f07d306c5d0d173cd6f60b93959d51 | 0.473148 | 3.396226 | false | false | false | false |
alexkernphysiker/JPET-FPGA-parser | packet_simulation/packet_simulation.vhd | 1 | 2,257 | -- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;
entity packet_simulation is
Port (
clock : in STD_LOGIC;
data_valid : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
start_packet : out STD_LOGIC;
end_packet : out STD_LOGIC
);
end packet_simulation;
architecture Behavioral of packet_simulation is
begin
reading: process(clock)
file source : text is in "test_data";
variable L : line;
variable K : STD_LOGIC_VECTOR (7 downto 0);
variable N : STD_LOGIC_VECTOR (7 downto 0);
variable goodnumber: boolean;
variable started: boolean:=false;
variable inside:boolean:=false;
variable maybenext:boolean:=false;
variable wait_cnt:integer:=0;
variable data_v: std_logic := '0';
variable start_p: std_logic := '0';
variable end_p: std_logic := '0';
begin
if falling_edge(clock)then
if(wait_cnt>0)then
wait_cnt:=wait_cnt-1;
end_p:='0';
if(wait_cnt=0)then
start_p:='1';
end if;
else
hread(L,N,goodnumber);
if not goodnumber then
if not endfile(source)then
readline(source,L);
hread(L,N,goodnumber);
case N is
when "00000000" => maybenext:=true;
when others => maybenext:=false;
end case;
hread(L,N,goodnumber);
case N is
when "00000000" => inside:=not maybenext;
when others => inside:=true;
end case;
if not inside then
wait_cnt:=3;
inside:=false;
if started then
end_p:='1';
start_p:='0';
else
started:=true;
end_p:='0';
end if;
else
end_p:='0';
start_p:='0';
end if;
else
if inside then
inside:=false;
start_p:='0';
end_p:='1';
else
start_p:='0';
end_p:='0';
end if;
end if;
data_v:='0';
else
if not inside then
inside:=true;
start_p:='0';
end_p:='0';
else
end_p:='0';
start_p:='0';
end if;
data_v:='1';
data_out<=N;
end if;
end if;
end if;
start_packet<=start_p;
end_packet<=end_p;
data_valid<=data_v;
end process reading;
end Behavioral;
| gpl-3.0 | 5c7ddd723513c2ee1202cf7ff3e540cb | 0.615419 | 2.938802 | false | false | false | false |
B-George/ECEGR_4220_MIPS_PROC | registers.vhd | 1 | 9,220 | --------------------------------------------------------------------------------
--
-- LAB #3
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bitstorage IS
PORT(bitin : IN STD_LOGIC;
enout : IN STD_LOGIC;
writein : IN STD_LOGIC;
bitout : OUT STD_LOGIC);
END ENTITY bitstorage;
ARCHITECTURE memlike OF bitstorage IS
SIGNAL q: STD_LOGIC;
BEGIN
PROCESS(writein) IS
BEGIN
IF (RISING_EDGE(writein)) THEN
q <= bitin;
END IF;
END PROCESS;
-- Note that data IS OUTput only WHEN enout = 0
bitout <= q WHEN enout = '0' ELSE 'Z';
END ARCHITECTURE memlike;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fulladder IS
PORT (a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC;
carry : OUT STD_LOGIC);
END fulladder;
ARCHITECTURE addlike OF fulladder IS
BEGIN
sum <= a xor b xor cIN;
carry <= (a AND b) OR (a AND cIN) OR (b AND cIN);
END ARCHITECTURE addlike;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY register8 IS
PORT(datain : IN STD_LOGIC_vector(7 DOWNTO 0);
enout : IN STD_LOGIC;
writein : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(7 DOWNTO 0));
END ENTITY register8;
ARCHITECTURE memmy OF register8 IS
COMPONENT bitstorage
PORT(bitin : IN STD_LOGIC;
enout : IN STD_LOGIC;
writein : IN STD_LOGIC;
bitout : OUT STD_LOGIC);
END COMPONENT;
BEGIN
R0: bitstorage PORT MAP(datain(0),enout,writein,dataout(0));
R1: bitstorage PORT MAP(datain(1),enout,writein,dataout(1));
R2: bitstorage PORT MAP(datain(2),enout,writein,dataout(2));
R3: bitstorage PORT MAP(datain(3),enout,writein,dataout(3));
R4: bitstorage PORT MAP(datain(4),enout,writein,dataout(4));
R5: bitstorage PORT MAP(datain(5),enout,writein,dataout(5));
R6: bitstorage PORT MAP(datain(6),enout,writein,dataout(6));
R7: bitstorage PORT MAP(datain(7),enout,writein,dataout(7));
END ARCHITECTURE memmy;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY register16 IS
PORT(datain : IN STD_LOGIC_vector(15 DOWNTO 0);
enout16,
enout8 : IN STD_LOGIC;
writein16,
writein8 : IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(15 DOWNTO 0));
END ENTITY register16;
ARCHITECTURE biggermem OF register16 IS
SIGNAL writeit8, writeit16: STD_LOGIC;
SIGNAL enit8, enit16: STD_LOGIC;
COMPONENT register8 IS
PORT(datain: IN STD_LOGIC_vector(7 DOWNTO 0);
enout: IN STD_LOGIC;
writein: IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(7 DOWNTO 0));
END COMPONENT;
BEGIN
writeit8 <= writein8 OR writein16;
writeit16 <= writein16;
enit8 <= enOUT8 AND enOUT16;
enit16 <= enOUT16;
Q0: register8 PORT MAP(datain(7 DOWNTO 0),enit8,writeit8,dataout(7 DOWNTO 0));
Q1: register8 PORT MAP(datain(15 DOWNTO 8),enit16,writeit16,dataout(15 DOWNTO 8));
END ARCHITECTURE biggermem;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY register32 IS
PORT(datain: IN STD_LOGIC_vector(31 DOWNTO 0);
enOUT32,enOUT16,enOUT8: IN STD_LOGIC;
writein32, writein16, writein8: IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(31 DOWNTO 0));
END ENTITY register32;
ARCHITECTURE biggermem OF register32 IS
SIGNAL writeit8, writeit16, writeit32: STD_LOGIC;
SIGNAL enit8, enit16, enit32: STD_LOGIC;
COMPONENT register8 IS
PORT(datain: IN STD_LOGIC_vector(7 DOWNTO 0);
enout: IN STD_LOGIC;
writein: IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(7 DOWNTO 0));
END COMPONENT;
BEGIN
writeit8 <= writein8 OR writein16 OR writein32;
writeit16 <= writein16 OR writein32;
writeit32 <= writein32;
enit8 <= enOUT8 AND enOUT16 AND enOUT32;
enit16 <= enOUT16 AND enOUT32;
enit32 <= enOUT32;
Q0: register8 PORT MAP(datain(7 DOWNTO 0),enit8,writeit8,dataout(7 DOWNTO 0));
Q1: register8 PORT MAP(datain(15 DOWNTO 8),enit16,writeit16,dataout(15 DOWNTO 8));
Q2: register8 PORT MAP(datain(23 DOWNTO 16),enit32,writeit32,dataout(23 DOWNTO 16));
Q3: register8 PORT MAP(datain(31 DOWNTO 24),enit32,writeit32,dataout(31 DOWNTO 24));
END ARCHITECTURE biggermem;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder_subtracter IS
PORT( datain_a: IN STD_LOGIC_vector(31 DOWNTO 0);
datain_b: IN STD_LOGIC_vector(31 DOWNTO 0);
add_sub : IN STD_LOGIC; -- add when == '0'
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0);
co : OUT STD_LOGIC);
END ENTITY adder_subtracter;
ARCHITECTURE calc OF adder_subtracter IS
SIGNAL used_b: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL carryit: STD_LOGIC_vector(31 DOWNTO 0);
COMPONENT fulladder IS
PORT (a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC;
carry : OUT STD_LOGIC);
END COMPONENT;
BEGIN
used_b <= dataIN_b WHEN add_sub = '0' ELSE
not(dataIN_b)+1;
F1: fulladder PORT MAP(dataIN_a(0),used_b(0),'0',dataout(0),carryit(0));
ADDVAL:
FOR i IN 1 to 31 GENERATE
FA: fulladder PORT MAP(dataIN_a(i),used_b(i),carryit(i-1),dataout(i),carryit(i));
END GENERATE ADDVAL;
co <= carryit(31);
END ARCHITECTURE calc;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shift_register IS
PORT( datain: IN STD_LOGIC_vector(31 DOWNTO 0);
dir: IN STD_LOGIC;
shamt: IN STD_LOGIC_vector(4 DOWNTO 0);
dataout: OUT STD_LOGIC_vector(31 DOWNTO 0));
END ENTITY shift_register;
ARCHITECTURE shifter OF shift_register IS
SIGNAL shammy: STD_LOGIC_vector(1 DOWNTO 0);
BEGIN
shammy <= shamt(1 DOWNTO 0);
dataout <= datain(30 DOWNTO 0) & "0" WHEN dir & shammy = "001" ELSE
datain(29 DOWNTO 0) & "00" WHEN dir & shammy = "010" ELSE
datain(28 DOWNTO 0) & "000" WHEN dir & shammy = "011" ELSE
"0" & datain(31 DOWNTO 1) WHEN dir & shammy = "101" ELSE
"00" & datain(31 DOWNTO 2) WHEN dir & shammy = "110" ELSE
"000" & datain(31 DOWNTO 3) WHEN dir & shammy = "111" ELSE
datain;
END ARCHITECTURE shifter;
------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALU IS
PORT( datain1: IN STD_LOGIC_vector(31 DOWNTO 0);
datain2: IN STD_LOGIC_vector(31 DOWNTO 0);
Control: IN STD_LOGIC_vector(4 DOWNTO 0);
Zero: OUT STD_LOGIC;
ALUResult: OUT STD_LOGIC_vector(31 DOWNTO 0));
END ENTITY ALU;
ARCHITECTURE logic OF ALU IS
--SIGNALS GO HERE
SIGNAL excarry1: STD_LOGIC;
SIGNAL excarry2: STD_LOGIC;
SIGNAL addres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL subres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL orres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL andres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL sllres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL srlres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL result: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL nores: STD_LOGIC_vector(31 DOWNTO 0):= (OTHERS=>'0');
--COMPONENTS
COMPONENT adder_subtracter IS
PORT( datain_a : IN STD_LOGIC_vector(31 DOWNTO 0);
datain_b : IN STD_LOGIC_vector(31 DOWNTO 0);
add_sub : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0);
co : OUT STD_LOGIC);
END COMPONENT;
COMPONENT shift_register IS
PORT( datain : IN STD_LOGIC_vector(31 DOWNTO 0);
dir : IN STD_LOGIC;
shamt : IN STD_LOGIC_vector(4 DOWNTO 0);
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0));
END COMPONENT;
BEGIN
A: adder_subtracter PORT MAP(datain1,datain2,'0',addres,excarry1);
S: adder_subtracter PORT MAP(datain1,datain2,'1',subres,excarry2);
andres <= datain1 AND datain2;
orres <= datain1 OR datain2;
L: shift_register PORT MAP(datain1,'0',datain2(4 DOWNTO 0),sllres);
R: shift_register PORT MAP(datain1,'1',datain2(4 DOWNTO 0),srlres);
WITH Control SELECT result <=
addres WHEN "00000",
subres WHEN "00001",
andres WHEN "00010",
orres WHEN "00011",
sllres WHEN "00100",
srlres WHEN "00101",
nores WHEN OTHERS;
WITH result SELECT Zero <=
'1' WHEN x"00000000",
'0' WHEN OTHERS;
ALUResult <= result;
END ARCHITECTURE logic;
| mit | 1db6b10512e098c8f06886c0122acf83 | 0.636117 | 3.194733 | false | false | false | false |
xcthulhu/periphondemand | src/library/test/clock_measurement/hdl/clockmeasurement.vhd | 1 | 3,029 | ---------------------------------------------------------------------------
-- Company : ARMadeus Systems
-- Author(s) : Fabien Marteau
--
-- Creation Date : 05/03/2008
-- File : clockmeasurement.vhd
--
-- Abstract : measure clock frequency of low_clock
--
-- mapping:
-- 0x0 : Id
-- 0x1 : counter
--
-- frequency is FpgaClock/counter
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-----------------------------------------------------------------------
Entity clockmeas is
-----------------------------------------------------------------------
generic(
id : natural := 1;
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_add : in std_logic ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- input clock signal
low_clock : in std_logic
);
end entity clockmeas;
-----------------------------------------------------------------------
Architecture clockmeas_1 of clockmeas is
-----------------------------------------------------------------------
signal wb_reg : std_logic_vector( wb_size-1 downto 0);
signal reset_counter : std_logic ;
begin
wbs_ack <= wbs_strobe;
-- read wb_register
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
wbs_readdata <= (others => '0');
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
if wbs_add = '0' then
wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
else
wbs_readdata <= wb_reg;
end if;
else
wbs_readdata <= (others => '0');
end if;
end if;
end process read_bloc;
-- the counter
count : process(gls_clk,gls_reset)
variable counter : natural range 0 to 65535;
begin
if gls_reset = '1' then
counter := 0;
elsif rising_edge(gls_clk) then
counter := counter + 1;
if reset_counter = '1' then
wb_reg <=std_logic_vector(to_unsigned(counter,wb_size));
counter := 0;
end if;
end if;
end process count;
-- edge detection
edge : process(gls_clk,gls_reset)
variable old_low_clock : std_logic ;
begin
if gls_reset = '1' then
old_low_clock := '1';
reset_counter <= '0';
elsif rising_edge(gls_clk) then
if (old_low_clock = '0') and (low_clock = '1') then
reset_counter <= '1';
else
reset_counter <= '0';
end if;
old_low_clock := low_clock;
end if;
end process edge;
end architecture clockmeas_1;
| lgpl-2.1 | a7c3f8c012737b94a299da156028e605 | 0.48894 | 3.898327 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tx/tx_add_preamble.vhd | 1 | 3,574 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tx_add_preamble - Behavioral
--
-- Description: Add the required 16 nibbles of preamble to the data packet.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_add_preamble is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end tx_add_preamble;
architecture Behavioral of tx_add_preamble is
signal delay_data : std_logic_vector(8*8-1 downto 0) := (others => '0');
signal delay_data_valid : std_logic_vector(8-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
if delay_data_valid(delay_data_valid'high)= '1' then
-- Passing through data
data_out <= delay_data(delay_data'high downto delay_data'high-7);
data_valid_out <= '1';
elsif delay_data_valid(delay_data_valid'high-1)= '1' then
-- Start Frame Delimiter
data_out <= "11010101";
data_valid_out <= '1';
elsif data_valid_in = '1' then
-- Preamble nibbles
data_out <= "01010101";
data_valid_out <= '1';
else
-- Link idle
data_out <= "00000000";
data_valid_out <= '0';
end if;
-- Move the data through the delay line
delay_data <= delay_data(delay_data'high-8 downto 0) & data_in;
delay_data_valid <= delay_data_valid(delay_data_valid'high-1 downto 0) & data_valid_in;
end if;
end process;
end Behavioral; | mit | af384ee5742eaae793d3d85f3c0c765b | 0.539172 | 4.347932 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/transport/transport_commit_buffer.vhd | 1 | 7,231 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: transport_commit_buffer - Behavioral
--
-- Description: Somewhere to hold the data outbound packet while waiting to
-- be granted access to the TX interface.
-- If the buffer gets over-run with data (e.g. if the TX interface is
-- busy) then it drops the packet.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity transport_commit_buffer is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end transport_commit_buffer;
architecture Behavioral of transport_commit_buffer is
type a_data_buffer is array(0 to 2047) of std_logic_vector(8 downto 0);
signal data_buffer : a_data_buffer := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of data_buffer : signal is "block";
signal read_addr : unsigned(10 downto 0) := (others => '1');
signal write_addr : unsigned(10 downto 0) := (others => '0');
signal committed_addr : unsigned(10 downto 0) := (others => '1');
type s_read_state is (read_idle, read_reading1, read_reading, read_waiting);
signal read_state : s_read_state := read_idle;
type s_write_state is (write_idle, write_writing, write_aborted);
signal write_state : s_write_state := write_idle;
signal i_packet_out_valid : std_logic := '0';
signal i_packet_out_valid_last : std_logic := '0';
signal i_packet_out_data : std_logic_vector(7 downto 0) := (others => '0');
constant fcs_length : integer := 4;
constant interpacket_gap : integer := 12;
constant for_next_preamble : integer := 8;
-- counter for the delay between packets
signal read_pause : unsigned(5 downto 0) := to_unsigned(fcs_length + interpacket_gap + for_next_preamble-1,6);
signal write_data : std_logic_vector(8 downto 0);
signal read_data : std_logic_vector(8 downto 0);
begin
with data_valid_in select write_data <= data_valid_in & data_in when '1',
(others => '0') when others;
i_packet_out_valid <= read_data(8);
i_packet_out_data <= read_data(7 downto 0);
packet_out_valid <= i_packet_out_valid;
packet_out_data <= i_packet_out_data;
infer_dp_mem_process: process(clk)
variable this_read_addr : unsigned(10 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if write_state = write_writing or data_valid_in = '1' then
data_buffer(to_integer(write_addr)) <= write_data;
end if;
this_read_addr := read_addr;
if i_packet_out_valid = '0' then
if read_addr = committed_addr or i_packet_out_valid_last = '1' then
packet_out_request <= '0';
else
packet_out_request <= '1';
if packet_out_granted = '1' then
this_read_addr := read_addr + 1;
end if;
end if;
else
this_read_addr := read_addr + 1;
end if;
i_packet_out_valid_last <= i_packet_out_valid;
read_data <= data_buffer(to_integer(this_read_addr));
read_addr <= this_read_addr;
end if;
end process;
process(clk)
variable write_data : std_logic_vector(8 downto 0);
begin
if rising_edge(clk) then
-------------------------------------------------
-- Writing the data into the buffer. If the buffer
-- would overrun the then packet is dropped (i.e.
-- committed_addr will not be updated).
------------------------------------------------
case write_state is
when write_writing =>
if write_addr+1 = read_addr then
-------------------------------------------------------
-- If we would wrap around? Is so then abort the packet
-------------------------------------------------------
write_addr <= committed_addr;
write_state <= write_aborted;
else
write_addr <= write_addr + 1;
if data_valid_in = '0' then
committed_addr <= write_addr;
write_state <= write_idle;
end if;
end if;
when write_aborted =>
---------------------------------------------------------
-- Wait until the data_valid_in drop at the end of packet
---------------------------------------------------------
if data_valid_in = '0' then
write_state <= write_idle;
end if;
when others => -- write_idle state
if data_valid_in = '1' then
write_addr <= write_addr + 1;
write_state <= write_writing;
end if;
end case;
end if;
end process;
end Behavioral; | mit | ce3cfb04088532fc0a762d57099609e1 | 0.509611 | 4.471861 | false | false | false | false |
alexkernphysiker/JPET-FPGA-parser | packet_simulation/parser.vhd | 1 | 6,381 | -- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity parser is
Port (
clk_read : in STD_LOGIC;
reset : in STD_LOGIC;
start_packet : in STD_LOGIC;
end_packet : in STD_LOGIC;
data_valid : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
eventID: out std_logic_vector(31 downto 0);
triggerID: out std_logic_vector(31 downto 0);
deviceID: out std_logic_vector(15 downto 0);
dataWORD: out std_logic_vector(31 downto 0);
out_data: out std_logic
);
end parser;
architecture Behavioral of parser is
type data_state is(IDLE,PACKET);
signal current_data_state:data_state:=IDLE;
type queue_state is(IDLE,QUEUE_HEADER,QUEUE_BODY,QUEUE_TAIL);
signal current_queue_state,next_queue_state:queue_state:=IDLE;
type subqueue_state is(IDLE,SUBHEADER,SUBQUEUE);
signal current_subqueue_state,next_subqueue_state:subqueue_state:=IDLE;
type dataitem_state is (IDLE,ITEMHEADER,ITEMBODY);
signal current_item_state,next_item_state:dataitem_state:=IDLE;
begin
packet_state_proc:process(clk_read)
begin
if rising_edge(clk_read)then
if start_packet='1' then
current_data_state<=PACKET;
elsif end_packet='1' then
current_data_state<=IDLE;
elsif reset='1' then
current_data_state<=IDLE;
end if;
end if;
end process packet_state_proc;
parcer_state_proc:process(clk_read,reset)
begin
if falling_edge(clk_read) then
current_queue_state<=next_queue_state;
current_subqueue_state<=next_subqueue_state;
current_item_state<=next_item_state;
if reset='1' then
current_queue_state<=IDLE;
current_subqueue_state<=IDLE;
current_item_state<=IDLE;
end if;
end if;
end process parcer_state_proc;
parcer_queue:process(clk_read)
variable queue_cnt,queue_size:integer:=0;
begin
if rising_edge(clk_read)then
if reset='1' then
next_queue_state<=IDLE;
elsif (data_valid='1')and(current_data_state=PACKET)then
queue_cnt:=queue_cnt+1;
case current_queue_state is
when IDLE =>
next_queue_state<=QUEUE_HEADER;
queue_cnt:=0;
queue_size:=0;
for i in 7 downto 0 loop
queue_size:=queue_size*2;
if data_in(i)='1' then
queue_size:=queue_size+1;
end if;
end loop;
when QUEUE_HEADER =>
if queue_cnt<4 then
for i in 7 downto 0 loop
queue_size:=queue_size*2;
if data_in(i)='1' then
queue_size:=queue_size+1;
end if;
end loop;
end if;
if queue_cnt=7 then
next_queue_state<=QUEUE_BODY;
end if;
when QUEUE_BODY =>
if queue_cnt>=(queue_size-1)then
next_queue_state<=QUEUE_TAIL;
queue_cnt:=0;
end if;
when QUEUE_TAIL =>
if queue_cnt=32 then
next_queue_state<=IDLE;
end if;
end case;
end if;
end if;
end process parcer_queue;
parcer_subqueue:process(clk_read)
variable subqueue_cnt,subqueue_size:integer:=0;
variable event_id,trigger_id:std_logic_vector(31 downto 0);
begin
if rising_edge(clk_read)then
if reset='1' then
next_subqueue_state<=IDLE;
elsif (data_valid='1')and(current_data_state=PACKET)then
if not(current_queue_state=QUEUE_BODY) then
next_subqueue_state<=IDLE;
else
subqueue_cnt:=subqueue_cnt+1;
case current_subqueue_state is
when IDLE =>
next_subqueue_state<=SUBHEADER;
subqueue_cnt:=0;
subqueue_size:=0;
for i in 7 downto 0 loop
subqueue_size:=subqueue_size*2;
if data_in(i)='1' then
subqueue_size:=subqueue_size+1;
end if;
end loop;
when SUBHEADER =>
if subqueue_cnt<4 then
for i in 7 downto 0 loop
subqueue_size:=subqueue_size*2;
if data_in(i)='1' then
subqueue_size:=subqueue_size+1;
end if;
end loop;
end if;
if subqueue_cnt=4 then
subqueue_size:=subqueue_size+4;
end if;
if(subqueue_cnt>=8)and(subqueue_cnt<12)then
for i in 7 downto 0 loop
event_id((11-subqueue_cnt)*8+i):=data_in(i);
end loop;
end if;
if(subqueue_cnt>=12)and(subqueue_cnt<16)then
for i in 7 downto 0 loop
trigger_id((15-subqueue_cnt)*8+i):=data_in(i);
end loop;
end if;
if subqueue_cnt=15 then
next_subqueue_state<=SUBQUEUE;
eventID<=event_id;
triggerID<=trigger_id;
end if;
when SUBQUEUE =>
if subqueue_cnt>=(subqueue_size-1)then
next_subqueue_state<=IDLE;
subqueue_cnt:=0;
end if;
end case;
end if;
end if;
end if;
end process parcer_subqueue;
parce_dataitems: process(clk_read)
variable dataitem_cnt,data_words_number:integer:=0;
variable device_id:std_logic_vector(15 downto 0);
variable current_word:std_logic_vector(31 downto 0);
begin
if rising_edge(clk_read)then
if reset='1' then
next_item_state<=IDLE;
elsif(data_valid='1')and(current_data_state=PACKET)then
if current_subqueue_state=SUBQUEUE then
if not(current_item_state=IDLE)then
dataitem_cnt:=dataitem_cnt+1;
end if;
case current_item_state is
when IDLE =>
dataitem_cnt:=0;
data_words_number:=0;
for i in 7 downto 0 loop
data_words_number:=data_words_number*2;
if data_in(i)='1' then
data_words_number:=data_words_number+1;
end if;
end loop;
next_item_state<=ITEMHEADER;
when ITEMHEADER =>
if dataitem_cnt<2 then
for i in 7 downto 0 loop
data_words_number:=data_words_number*2;
if data_in(i)='1' then
data_words_number:=data_words_number+1;
end if;
end loop;
else
for i in 7 downto 0 loop
device_id((3-dataitem_cnt)*8+i):=data_in(i);
end loop;
if dataitem_cnt=3 then
deviceID<=device_id;
next_item_state<=ITEMBODY;
end if;
end if;
when ITEMBODY =>
for i in 7 downto 0 loop
current_word((3-(dataitem_cnt mod 4))*8+i):=data_in(i);
end loop;
if (dataitem_cnt mod 4)=3 then
dataWORD<=current_word;
out_data<='1';
end if;
if dataitem_cnt>=((data_words_number+1)*4)-1 then
next_item_state<=IDLE;
end if;
end case;
end if;
else
out_data<='0';
end if;
if not(current_subqueue_state=SUBQUEUE) then
next_item_state<=IDLE;
end if;
end if;
end process parce_dataitems;
end Behavioral;
| gpl-3.0 | f46296d38695ac1870c121c75bd10dc4 | 0.650838 | 2.929752 | false | false | false | false |
xcthulhu/periphondemand | src/library/wrappers/imx9328_wb16_wrapper/hdl/imx9328_wb16_wrapper.vhd | 1 | 3,352 | -------------------------------------------------------------------------------
--
-- File : imx9328_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabrice Mousset ([email protected])
-- Project : i.MX wrapper to Wishbone bus
--
-- Creation Date : 2007/01/19
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
-----
-- 2008/03/05
-- Fabien Marteau ([email protected])
-- adding comments and changing some signals names
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
Entity imx9328_wb16_wrapper is
-- ----------------------------------------------------------------------------
port
(
-- i.MX Signals
imx_address : in std_logic_vector(11 downto 0); -- LSB not used
imx_data : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb3_n : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Interrupt out for write error
-- int_err : out std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(12 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
Architecture RTL of imx9328_wb16_wrapper is
-- ----------------------------------------------------------------------------
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(12 downto 0);
begin
-- ----------------------------------------------------------------------------
-- External signals synchronization process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
write <= '0';
read <= '0';
strobe <= '0';
writedata <= (others => '0');
address <= (others => '0');
elsif(rising_edge(gls_clk)) then
strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
write <= not (imx_cs_n or imx_eb3_n);
read <= not (imx_cs_n or imx_oe_n);
address <= imx_address & '0';
writedata <= imx_data;
end if;
end process;
wbm_address <= address when (strobe = '1') else (others => '0');
wbm_writedata <= writedata when (write = '1') else (others => '0');
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
imx_data <= wbm_readdata when(read = '1' ) else (others => 'Z');
end architecture RTL;
| lgpl-2.1 | 23d253294005984687822ca965308740 | 0.456742 | 4.058111 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_tx_buffer_count_checksum_data.vhd | 1 | 6,480 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_tx_buffer_count_checksum_data - Behavioral
--
-- Description: Count and checksum the data to be put into a UDP packet
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_tx_buffer_count_checksum_data is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_length : out std_logic_vector(15 downto 0) := (others => '0');
data_checksum : out std_logic_vector(15 downto 0) := (others => '0'));
end udp_tx_buffer_count_checksum_data;
architecture Behavioral of udp_tx_buffer_count_checksum_data is
type a_data_buffer is array (0 to 2047) of std_logic_vector(8 downto 0);
signal write_ptr : unsigned(10 downto 0) := (others => '0');
signal read_ptr : unsigned(10 downto 0) := (others => '1');
signal checkpoint : unsigned(10 downto 0) := (others => '1');
signal data_buffer : a_data_buffer := (others =>( others => '0'));
attribute ram_style : string;
attribute ram_style of data_buffer : signal is "block";
signal data_count : unsigned(10 downto 0) := to_unsigned(128,11);
signal wrote_valid_data : std_logic := '0';
signal data_valid_in_last : std_logic := '0';
signal checksum : unsigned(16 downto 0) := (others => '0');
signal read_data : std_logic_vector(8 downto 0) := (others => '0');
begin
data_valid_out <= read_data(8);
data_out <= read_data(7 downto 0);
infer_dp_mem_process: process(clk)
variable write_data : std_logic_vector(8 downto 0) := (others => '0');
variable write_enable : std_logic;
begin
if rising_edge(clk) then
write_enable := '0';
if data_valid_in = '1' then
write_data := data_valid_in & data_in;
wrote_valid_data <= '1';
write_enable := '1';
elsif data_count < 64-14-20-8-4 then -- Minimum UDP datasize to make minimum ethernet frame
-- Padding to make minimum packet size
write_data := '1'& x"00";
wrote_valid_data <= '1';
write_enable := '1';
else
if wrote_valid_data = '1' then
write_enable := '1';
end if;
wrote_valid_data <= '0';
write_data := '0'& x"00";
end if;
if write_enable = '1' then
data_buffer(to_integer(write_ptr)) <= write_data;
end if;
read_data <= data_buffer(to_integer(read_ptr));
end if;
end process;
main_proc: process(clk)
variable v_checksum : unsigned(16 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if data_valid_in = '1' or data_valid_in_last = '1' or data_count < 64-14-20-8-3 then
write_ptr <= write_ptr + 1;
end if;
if data_valid_in = '1' then
if data_valid_in_last = '0' then
data_count <= to_unsigned(1,11);
else
data_count <= data_count + 1;
end if;
--- Update the checksum here
if data_count(0) = '0' then
checksum <= to_unsigned(0,17) + checksum(15 downto 0) + checksum(16 downto 16) + (unsigned(data_in) & to_unsigned(0,8));
else
checksum <= to_unsigned(0,17) + checksum(15 downto 0) + checksum(16 downto 16) + unsigned(data_in);
end if;
else -- data_valid_in = '0'
if data_valid_in_last = '1' then
-- End of packet
v_checksum := to_unsigned(0,17) + checksum(15 downto 0) + checksum(16 downto 16);
data_checksum <= std_logic_vector(v_checksum(15 downto 0) + v_checksum(16 downto 16));
data_length <= "00000" & std_logic_vector(data_count);
end if;
-- This is where padding is added
if data_count < 64-14-20-8-3 then
data_count <= data_count + 1;
else
-- Enough data so checkpoint it
checkpoint <= write_ptr-1;
end if;
checksum <= (others => '0');
end if;
data_valid_in_last <= data_valid_in;
if read_ptr /= checkpoint then
read_ptr <= read_ptr+1;
end if;
end if;
end process;
end Behavioral;
| mit | 832dbee2009cbd5ea6c2c2eef13d90e3 | 0.525617 | 4.090909 | false | false | false | false |
xcthulhu/periphondemand | src/library/syscons/rstgen_syscon/hdl/rstgen_syscon.vhd | 1 | 1,628 | ---------------------------------------------------------------------------
-- Company : ARMadeus Systems
-- Author(s) : Fabien Marteau
--
-- Creation Date : 05/03/2008
-- File : rstgen_syscon.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity rstgen_syscon is
---------------------------------------------------------------------------
generic(
invert_reset : std_logic := '0' -- 0 : not invert, 1 invert
);
port
(
-- external signals
ext_clk : in std_logic ;
--internal signals
gls_clk : out std_logic ;
gls_reset : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture rstgen_syscon_1 of rstgen_syscon is
---------------------------------------------------------------------------
signal dly: std_logic := '0';
signal rst: std_logic := '0';
signal ext_reset : std_logic;
begin
ext_reset <= '0';
----------------------------------------------------------------------------
-- RESET signal generator.
----------------------------------------------------------------------------
process(ext_clk)
begin
if(rising_edge(ext_clk)) then
dly <= ( not(ext_reset) and dly and not(rst) )
or ( not(ext_reset) and not(dly) and rst );
rst <= ( not(ext_reset) and not(dly) and not(rst) );
end if;
end process;
gls_clk <= ext_clk;
gls_reset <= rst xor invert_reset ;
end architecture rstgen_syscon_1;
| lgpl-2.1 | 77d2c9f937c16d88977a6a02c1255d8e | 0.394963 | 4.448087 | false | false | false | false |
S0obi/SY23 | lcd_display/lcd_display.vhdl | 1 | 4,222 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:02:56 09/23/2015
-- Design Name:
-- Module Name: lcd_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd_display is
Port ( clk : in STD_LOGIC;
data: in STD_LOGIC_VECTOR(7 downto 0);
wr: in STD_LOGIC;
lcd_rw : out STD_LOGIC;
lcd_rs : out STD_LOGIC;
lcd_en : out STD_LOGIC;
lcd_data : out STD_LOGIC_VECTOR(3 downto 0)
);
end lcd_display;
architecture Behavioral of lcd_display is
component counter is
GENERIC (
Nbits: integer := 32;
Nmax: integer := 9
);
Port ( clk : in STD_LOGIC;
reset_counter : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (Nbits-1 downto 0));
end component;
constant t_start_to_init0: integer := 750000; -- 15ms
constant t_init0_to_init1: integer := 950000; -- 19ms
constant t_init1_to_init2: integer := 1050000; -- 21ms
constant t_init2_to_init3: integer := 1150000; -- 23ms
constant t_init3_to_set : integer := 1155000; -- 23,1ms
constant t_set_to_entry : integer := 1160000; -- 23,2ms
constant t_entry_to_on : integer := 1165000; -- 23,3ms
constant t_on_to_clear : integer := 1170000; -- 23,4ms
constant t_clear_to_ready: integer := 1270000; -- 25,4ms
type T_etat is (start, init0, init1, init2, init3, set, entry, state_on, clear, ready, setaddress, writeaddress, writedata);
signal next_state, state_reg : T_etat;
begin
data <= "10000001";
state_reg_process: process(clk)
begin
if rising_edge(clk) then
if state_reg /= ready then
state_reg <= start;
reset_counter <= '1';
reset_counter <= '0';
case Q is
when t_start_to_init0 =>
state_reg <= init0;
D <= (7 downto 4 => x"3");
when t_init0_to_init1 =>
state_reg <= init1;
D <= (7 downto 4 => x"3");
when t_init1_to_init2 =>
state_reg <= init2;
D <= (7 downto 4 => x"3");
when t_init2_to_init3 =>
state_reg <= init3;
D <= (7 downto 4 => x"2");
when t_init3_to_set =>
state_reg <= set;
D <= (7 downto 4 => x"2");
D <= (7 downto 4 => x"8");
when t_set_to_entry =>
state_reg <= entry;
D <= (7 downto 4 => x"0");
D <= (7 downto 4 => x"6");
when t_entry_to_on =>
state_reg <= state_on;
D <= (7 downto 4 => x"0");
D <= (7 downto 4 => x"C");
when t_on_to_clear =>
state_reg <= clear;
D <= (7 downto 4 => x"0");
D <= (7 downto 4 => x"1");
when t_clear_to_ready =>
state_reg <= ready;
state_reg <= next_state;
end case;
end if;
end if;
end process state_reg_process;
next_state_process: process(state_reg)
begin
next_state <= state_reg;
case state_reg is
when clear =>
reset_counter <= '1';
reset_counter <= '0';
if Q="100000" then -- 2ms
next_state <= ready;
D(7 downto 4) <= x"0";
D(7 downto 4) <= x"1";
end if;
when ready =>
if wr='1' and data=x"C" then
next_state <= clear;
else if wr='1' and data/=x"D" and data/=x"A" and data/=x"C" then
next_state <= writedata;
end if;
when writedata =>
LCD_DATA <= data(3 downto 0);
LCD_EN <= '1';
reset_counter <= '1';
reset_counter <= '0';
case Q is
when "50" => -- 1µs
LCD_EN <= '0';
LCD_DATA <= data(7 downto 4);
LCD_EN <= '1';
when "100" => -- 1+1µs
LCD_EN <= '0';
when "2100" => -- 40+1+1µs
next_state <= ready;
end case;
end case;
end process next_state_process
end architecture Behavioral;
| gpl-2.0 | bb944989f088d80f42990533a7b655f5 | 0.53425 | 3.099927 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp/tcp_rx_packet.vhd | 1 | 13,007 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_rx_packet - Behavioral
--
-- Description: For receiving UDP packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tcp_rx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : out std_logic := '0';
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0')
);
end tcp_rx_packet;
architecture Behavioral of tcp_rx_packet is
component ethernet_extract_header
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
filter_ether_type : in STD_LOGIC_VECTOR (15 downto 0);
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_dst_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal ether_extracted_data_valid : STD_LOGIC := '0';
signal ether_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ether_is_ipv4 : STD_LOGIC := '0';
signal ether_src_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
component ip_extract_header
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
filter_protocol : in STD_LOGIC_VECTOR (7 downto 0);
ip_version : out STD_LOGIC_VECTOR (3 downto 0);
ip_type_of_service : out STD_LOGIC_VECTOR (7 downto 0);
ip_length : out STD_LOGIC_VECTOR (15 downto 0);
ip_identification : out STD_LOGIC_VECTOR (15 downto 0);
ip_flags : out STD_LOGIC_VECTOR (2 downto 0);
ip_fragment_offset : out STD_LOGIC_VECTOR (12 downto 0);
ip_ttl : out STD_LOGIC_VECTOR (7 downto 0);
ip_checksum : out STD_LOGIC_VECTOR (15 downto 0);
ip_src_ip : out STD_LOGIC_VECTOR (31 downto 0);
ip_dest_ip : out STD_LOGIC_VECTOR (31 downto 0);
ip_dest_broadcast : out STD_LOGIC);
end component;
signal ip_extracted_data_valid : STD_LOGIC := '0';
signal ip_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_version : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal ip_type_of_service : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_flags : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal ip_ttl : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal ip_dest_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal ip_dest_broadcast : STD_LOGIC := '0';
component tcp_extract_header
port(
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0) := (others => '0');
data_valid_in : in std_logic := '0';
data_out : out std_logic_vector(7 downto 0) := (others => '0');
data_valid_out : out std_logic := '0';
tcp_hdr_valid : out std_logic := '0';
tcp_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_flag_urg : out std_logic := '0';
tcp_flag_ack : out std_logic := '0';
tcp_flag_psh : out std_logic := '0';
tcp_flag_rst : out std_logic := '0';
tcp_flag_syn : out std_logic := '0';
tcp_flag_fin : out std_logic := '0';
tcp_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
signal tcp_extracted_data_valid : STD_LOGIC := '0';
signal tcp_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal tcp_hdr_valid : std_logic := '0';
signal tcp_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_flag_urg : std_logic := '0';
signal tcp_flag_ack : std_logic := '0';
signal tcp_flag_psh : std_logic := '0';
signal tcp_flag_rst : std_logic := '0';
signal tcp_flag_syn : std_logic := '0';
signal tcp_flag_fin : std_logic := '0';
signal tcp_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
COMPONENT ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT ;
begin
i_ethernet_extract_header: ethernet_extract_header generic map (
our_mac => our_mac)
port map (
clk => clk,
data_valid_in => packet_in_valid,
data_in => packet_in_data,
data_valid_out => ether_extracted_data_valid,
data_out => ether_extracted_data,
filter_ether_type => x"0800",
ether_dst_mac => open,
ether_src_mac => ether_src_mac);
i_ip_extract_header: ip_extract_header generic map (
our_ip => our_ip,
our_broadcast => our_broadcast)
port map (
clk => clk,
data_valid_in => ether_extracted_data_valid,
data_in => ether_extracted_data,
data_valid_out => ip_extracted_data_valid,
data_out => ip_extracted_data,
filter_protocol => x"06",
ip_version => ip_version,
ip_type_of_service => ip_type_of_service,
ip_length => ip_length,
ip_identification => ip_identification,
ip_flags => ip_flags,
ip_fragment_offset => ip_fragment_offset,
ip_ttl => ip_ttl,
ip_checksum => ip_checksum,
ip_src_ip => ip_src_ip,
ip_dest_ip => ip_dest_ip,
ip_dest_broadcast => ip_dest_broadcast);
--i_ila_0: ila_0 port map (
-- clk => clk,
-- probe0(0) => ip_extracted_data_valid,
-- probe1 => ip_extracted_data,
-- probe2(0) => ip_extracted_data_valid,
-- probe3(0) => tcp_hdr_valid,
-- probe4(0) => tcp_extracted_data_valid,
-- probe5 => tcp_extracted_data);
i_tcp_extract_header: tcp_extract_header port map (
clk => clk,
data_valid_in => ip_extracted_data_valid,
data_in => ip_extracted_data,
data_valid_out => tcp_extracted_data_valid,
data_out => tcp_extracted_data,
tcp_hdr_valid => tcp_hdr_valid,
tcp_src_port => tcp_src_port,
tcp_dst_port => tcp_dst_port,
tcp_seq_num => tcp_seq_num,
tcp_ack_num => tcp_ack_num,
tcp_window => tcp_window,
tcp_flag_urg => tcp_flag_urg,
tcp_flag_ack => tcp_flag_ack,
tcp_flag_psh => tcp_flag_psh,
tcp_flag_rst => tcp_flag_rst,
tcp_flag_syn => tcp_flag_syn,
tcp_flag_fin => tcp_flag_fin,
tcp_checksum => tcp_checksum,
tcp_urgent_ptr => tcp_urgent_ptr);
----------------------------------------------
-- Pass the received data stream to the
-- rest of the FPGA desig.
----------------------------------------------
tcp_rx_data_valid <= tcp_extracted_data_valid;
tcp_rx_data <= tcp_extracted_data;
tcp_rx_src_ip <= ip_src_ip;
tcp_rx_dst_broadcast <= ip_dest_broadcast;
tcp_rx_hdr_valid <= tcp_hdr_valid;
tcp_rx_src_port <= tcp_src_port;
tcp_rx_dst_port <= tcp_dst_port;
tcp_rx_seq_num <= tcp_seq_num;
tcp_rx_ack_num <= tcp_ack_num;
tcp_rx_window <= tcp_window;
tcp_rx_flag_urg <= tcp_flag_urg;
tcp_rx_flag_ack <= tcp_flag_ack;
tcp_rx_flag_psh <= tcp_flag_psh;
tcp_rx_flag_rst <= tcp_flag_rst;
tcp_rx_flag_syn <= tcp_flag_syn;
tcp_rx_flag_fin <= tcp_flag_fin;
tcp_rx_checksum <= tcp_checksum;
tcp_rx_urgent_ptr <= tcp_urgent_ptr;
end Behavioral;
| mit | f43b032974b62f90b10d391e5f230a61 | 0.531637 | 3.483396 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles_graphs/synthesisShowcase/caseStmtNest.vhd | 2 | 708 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
process(A) is
begin
case A is
when '0' => case B is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
when '1' => case C is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
end case;
end process;
end behv;
| gpl-3.0 | 24018cc943ec36d54ff7796423937102 | 0.429379 | 3.668394 | false | false | false | false |
wifidar/wifidar_fpga | src/adc_receiver.vhd | 2 | 3,083 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity adc_receiver is
port(
send_data: in std_logic;
busy: out std_logic;
spi_sck: out std_logic;
spi_miso: in std_logic;
ad_conv: out std_logic;
outputA: out std_logic_vector (13 downto 0);
outputB: out std_logic_vector (13 downto 0);
new_reading: out std_logic;
clk: in std_logic
);
end adc_receiver;
architecture Behavioral of adc_receiver is
type adc_read_type is (start_pulse,a_data,b_data,write_data);
signal adc_state: adc_read_type;
signal outputA_register: std_logic_vector(13 downto 0);
signal outputB_register: std_logic_vector(13 downto 0);
signal outputA_temp: std_logic_vector(15 downto 0);
signal outputB_temp: std_logic_vector(15 downto 0);
signal curr_pos: integer range 0 to 15 := 0;
signal spi_clk_en: std_logic;
signal new_reading_temp: std_logic;
signal en: std_logic;
begin
main_proc: process(clk)
begin
if(falling_edge(clk)) then
if(send_data = '1') then
en <= '1';
busy <= '1';
end if;
if(en = '1') then
ad_conv <= '0';
new_reading <= '0';
busy <= '1';
case adc_state is
when start_pulse =>
curr_pos <= curr_pos + 1;
new_reading_temp <= '1';
if(curr_pos = 0) then
ad_conv <= '1';
end if;
if(curr_pos = 3) then
spi_clk_en <= '1';
end if;
if(curr_pos = 4) then
adc_state <= a_data;
curr_pos <= 15;
end if;
when a_data =>
curr_pos <= curr_pos - 1;
outputA_temp(curr_pos) <= spi_miso;
if(curr_pos = 0) then
curr_pos <= 15;
adc_state <= b_data;
end if;
when b_data =>
curr_pos <= curr_pos - 1;
outputB_temp(curr_pos) <= spi_miso;
if(curr_pos = 0) then
curr_pos <= 0;
adc_state <= write_data;
end if;
when write_data =>
curr_pos <= curr_pos + 1;
outputA_register <= outputA_temp(13 downto 0);
outputB_register <= outputB_temp(15 downto 2);
if(new_reading_temp = '1') then
new_reading <= '1';
new_reading_temp <= '0';
end if;
if(curr_pos = 2) then
curr_pos <= 0;
adc_state <= start_pulse;
spi_clk_en <= '0';
en <= '0';
busy <= '0';
end if;
end case;
-- spi_clk_sig <= not spi_clk_sig;
--
-- if(spi_clk_sig = '1') then
-- if(curr_pos = 0) then
-- ad_conv <= '1';
-- outputA_register <= input_register(16 downto 3);
-- outputB_register <= input_register(32 downto 19);
-- else
-- ad_conv <= '0';
-- end if;
--
-- if((curr_pos > 1) and (curr_pos < 33)) then
-- input_register(curr_pos) <= spi_miso;
-- end if;
--
-- if(curr_pos = 36) then
-- curr_pos <= 0;
-- end if;
-- end if;
end if;
end if;
end process;
spi_sck <= clk when spi_clk_en = '1' else '0';
outputA <= outputA_register;
outputB <= outputB_register;
end Behavioral;
| mit | c2bb0609c472de707090d3c9bc22fc8c | 0.566007 | 2.779982 | false | false | false | false |
qu1x/fsio | src/lib/fsio_get.vhd | 1 | 1,393 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
library fsio;
use fsio.fsio.all;
entity fsio_get is
generic (
cap: integer := CAP;
len: integer := LEN
);
port (
clk: in std_logic;
hsi: in std_logic;
hso: out std_logic;
fsi: in std_logic_vector(cap - 1 downto 0);
fso: out std_logic_vector(cap - 1 downto 0);
dat: out std_logic_vector(len - 1 downto 0);
req: out std_logic;
ack: in std_logic
);
end fsio_get;
architecture behavioral of fsio_get is
begin
dat <= fso(len - 1 downto 0);
req <= hso xor hsi;
fso <= fsi;
ctl: process(clk)
begin
if rising_edge(clk) then
hso <= hso xor (req and ack);
end if;
end process ctl;
end behavioral;
| agpl-3.0 | 6ee212ae30910261bb9568715b16114c | 0.697775 | 3.15873 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/ip/ip_extract_header.vhd | 1 | 8,369 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: ip_extract_header - Behavioral
--
-- Description: Extract the IP header fields
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ip_extract_header is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
filter_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_version : out STD_LOGIC_VECTOR ( 3 downto 0) := (others => '0');
ip_type_of_service : out STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_length : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_identification : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_flags : out STD_LOGIC_VECTOR ( 2 downto 0) := (others => '0');
ip_fragment_offset : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
ip_ttl : out STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_checksum : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_src_ip : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dest_ip : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dest_broadcast : out STD_LOGIC);
end ip_extract_header;
architecture Behavioral of ip_extract_header is
signal count : unsigned(6 downto 0) := (others => '0');
signal header_len : unsigned(6 downto 0) := (others => '0');
signal i_ip_version : STD_LOGIC_VECTOR ( 3 downto 0) := (others => '0');
signal i_ip_type_of_service : STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
signal i_ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ip_flags : STD_LOGIC_VECTOR ( 2 downto 0) := (others => '0');
signal i_ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal i_ip_ttl : STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
signal i_ip_protocol : STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
signal i_ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal i_ip_dest_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal data_count : UNSIGNED(10 downto 0) := (others => '0');
begin
ip_version <= i_ip_version;
ip_type_of_service <= i_ip_type_of_service;
ip_length <= i_ip_length;
ip_identification <= i_ip_identification;
ip_flags <= i_ip_flags;
ip_fragment_offset <= i_ip_fragment_offset;
ip_ttl <= i_ip_ttl;
ip_checksum <= i_ip_checksum;
ip_src_ip <= i_ip_src_ip;
ip_dest_ip <= i_ip_dest_ip;
ip_dest_broadcast <= '1' when i_ip_dest_ip = our_broadcast else '0';
process(clk)
begin
if rising_edge(clk) then
data_out <= data_in;
if data_valid_in = '1' then
-- Note, at count of zero,
data_count <= data_count + 1;
case count is
when "0000000" => i_ip_version <= data_in(7 downto 4);
header_len(5 downto 2) <= unsigned(data_in(3 downto 0));
when "0000001" => i_ip_type_of_service <= data_in;
when "0000010" => i_ip_length(15 downto 8) <= data_in;
when "0000011" => i_ip_length( 7 downto 0) <= data_in;
when "0000100" => i_ip_identification(15 downto 8) <= data_in;
when "0000101" => i_ip_identification( 7 downto 0) <= data_in;
when "0000110" => i_ip_fragment_offset(12 downto 8) <= data_in(4 downto 0);
i_ip_flags <= data_in(7 downto 5);
when "0000111" => i_ip_fragment_offset( 7 downto 0) <= data_in;
when "0001000" => i_ip_ttl <= data_in;
when "0001001" => i_ip_protocol <= data_in;
when "0001010" => i_ip_checksum(15 downto 8) <= data_in;
when "0001011" => i_ip_checksum( 7 downto 0) <= data_in;
when "0001100" => i_ip_src_ip( 7 downto 0) <= data_in;
when "0001101" => i_ip_src_ip(15 downto 8) <= data_in;
when "0001110" => i_ip_src_ip(23 downto 16) <= data_in;
when "0001111" => i_ip_src_ip(31 downto 24) <= data_in;
when "0010000" => i_ip_dest_ip( 7 downto 0) <= data_in;
when "0010001" => i_ip_dest_ip(15 downto 8) <= data_in;
when "0010010" => i_ip_dest_ip(23 downto 16) <= data_in;
when "0010011" => i_ip_dest_ip(31 downto 24) <= data_in;
when others => null;
end case;
-- So that additional IP options get dropped
if unsigned(count) >= unsigned(header_len) and unsigned(count) > 4
and i_ip_version = x"4" and i_ip_protocol = filter_protocol
and (i_ip_dest_ip = our_ip or i_ip_dest_ip = our_broadcast) then
if data_count < unsigned(i_ip_length) then
data_valid_out <= data_valid_in;
else
data_valid_out <= '0';
end if;
data_out <= data_in;
end if;
if count /= "1111111" then
count <= count+1;
end if;
else
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
data_count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| mit | 637176f6f5708b7d805a904cb7f0af0c | 0.487633 | 3.925422 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/mmcm/top.vhdl | 1 | 1,873 | --
-- Mixed-Mode Clock Manager on ml605
--
-- To Do
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(5 downto 0)
);
end entity Top;
architecture RTL of Top is
signal blink_reset, locked : std_logic;
signal clk50, clk100, clk150, clk200, clk250, clk300 : std_logic;
begin
mmcm_inst: entity work.mmcm
port map (
-- Clock in ports
CLK_IN1_P => clk_p_i,
CLK_IN1_N => clk_n_i,
-- Clock out ports
CLK_OUT1 => clk50,
CLK_OUT2 => clk100,
CLK_OUT3 => clk150,
CLK_OUT4 => clk200,
CLK_OUT5 => clk250,
CLK_OUT6 => clk300,
-- Status and control signals
RESET => rst_i,
LOCKED => locked
);
blink_reset <= not(locked);
blink50_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk50, rst_i => blink_reset, blink_o => leds_o(0));
blink100_inst: Blink
generic map (FREQUENCY => 100e6)
port map(clk_i => clk100, rst_i => blink_reset, blink_o => leds_o(1));
blink150_inst: Blink
generic map (FREQUENCY => 150e6)
port map(clk_i => clk150, rst_i => blink_reset, blink_o => leds_o(2));
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => blink_reset, blink_o => leds_o(3));
blink250_inst: Blink
generic map (FREQUENCY => 250e6)
port map(clk_i => clk250, rst_i => blink_reset, blink_o => leds_o(4));
blink300_inst: Blink
generic map (FREQUENCY => 300e6)
port map(clk_i => clk300, rst_i => blink_reset, blink_o => leds_o(5));
end architecture RTL;
| bsd-3-clause | 07393b19a2dbf3a39f6036a44fc59a95 | 0.610785 | 2.982484 | false | false | false | false |
freecores/hilbert_transformer | vhdl/analytic_filter_h_a4.vhd | 1 | 7,497 | -- Implementation of Filter H_a4(z)
-- using Complex Frequency sampling filer (FSF) as Hilbert transformer
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
package analytic_filter_h_a4_pkg is
component analytic_filter_h_a4
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a4_pkg;
package body analytic_filter_h_a4_pkg is
end analytic_filter_h_a4_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.fsf_comb_filter_pkg.all;
use work.fsf_pole_filter_pkg.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
use work.real_pole_filter_shift_reg_pkg.all;
use work.complex_fsf_filter_c_90_pkg.all;
use work.complex_fsf_filter_inv_c_m30_m150_pkg.all;
use work.resize_tools_pkg.all;
entity analytic_filter_h_a4 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end analytic_filter_h_a4;
architecture analytic_filter_h_a4_arch of analytic_filter_h_a4 is
--signal y : std_logic_vector (data_width-1 downto 0);
--signal x : std_logic_vector (data_width-1 downto 0);
signal data_i_res : std_logic_vector (data_width-1 downto 0);
signal t1 : std_logic_vector (data_width-1 downto 0);
signal t1_res : std_logic_vector (data_width-1 downto 0);
signal t2 : std_logic_vector (data_width-1 downto 0);
signal t3 : std_logic_vector (data_width-1 downto 0);
signal t4 : std_logic_vector (data_width-1 downto 0);
signal t4_res : std_logic_vector (data_width-1 downto 0);
signal t5 : std_logic_vector (data_width-1 downto 0);
signal t5_res : std_logic_vector (data_width-1 downto 0);
signal t6 : std_logic_vector (data_width-1 downto 0);
signal c1_i : std_logic_vector (data_width-1 downto 0);
signal c1_q : std_logic_vector (data_width-1 downto 0);
signal c2_i : std_logic_vector (data_width-1 downto 0);
signal c2_q : std_logic_vector (data_width-1 downto 0);
signal c3_i : std_logic_vector (data_width-1 downto 0);
signal c3_q : std_logic_vector (data_width-1 downto 0);
signal c4_i : std_logic_vector (data_width-1 downto 0);
signal c4_q : std_logic_vector (data_width-1 downto 0);
signal c4_i_res : std_logic_vector (data_width-1 downto 0);
signal c4_q_res : std_logic_vector (data_width-1 downto 0);
signal t1_str : std_logic;
signal t2_str : std_logic;
signal t3_str : std_logic;
signal t4_str : std_logic;
signal t5_str : std_logic;
signal t6_str : std_logic;
signal c1_str : std_logic;
signal c2_str : std_logic;
signal c3_str : std_logic;
signal c4_str : std_logic;
begin
data_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(data_i),2)),data_width);
real_pole_filter_1 : real_pole_filter_shift_reg
generic map (
data_width => data_width,
internal_data_width => data_width,
shift_value => 1
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => data_i_res,
data_str_i => data_str_i,
data_o => t1,
data_str_o => t1_str
);
t1_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(t1),2)),data_width);
real_pole_filter_2 : real_pole_filter_shift_reg
generic map (
data_width => data_width,
internal_data_width => data_width,
shift_value => 1
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t1_res,
data_str_i => t1_str,
data_o => t2,
data_str_o => t2_str
);
comb_stage1 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t2,
data_str_i => t2_str,
data_o => t3,
data_str_o => t3_str
);
comb_stage2 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t3,
data_str_i => t3_str,
data_o => t4,
data_str_o => t4_str
);
c_0_180_filter1 : fsf_pole_filter
generic map (
data_width => data_width,
coeff => c_0_180_coeff,
no_of_coefficients => 2
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t4,
-- data_i => t4_res,
data_str_i => t4_str,
data_o => t5,
data_str_o => t5_str
);
c_0_180_filter2 : fsf_pole_filter
generic map (
data_width => data_width,
coeff => c_0_180_coeff,
no_of_coefficients => 2
)
port map(
clk_i => clk_i,
rst_i => rst_i,
-- data_i => t5_res,
data_i => t5,
data_str_i => t5_str,
data_o => t6,
data_str_o => t6_str
);
complex_fsf_filter_c_90_1 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => t6,
data_q_i => (others => '0'),
data_str_i => t6_str,
data_i_o => c1_i,
data_q_o => c1_q,
data_str_o => c1_str
);
complex_fsf_filter_c_90_2 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c1_i,
data_q_i => c1_q,
data_str_i => c1_str,
data_i_o => c2_i,
data_q_o => c2_q,
data_str_o => c2_str
);
complex_fsf_filter_inv_c_m30_m150_1 : complex_fsf_filter_inv_c_m30_m150
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c2_i,
data_q_i => c2_q,
data_str_i => c2_str,
data_i_o => c3_i,
data_q_o => c3_q,
data_str_o => c3_str
);
complex_fsf_filter_inv_c_m30_m150_2 : complex_fsf_filter_inv_c_m30_m150
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c3_i,
data_q_i => c3_q,
data_str_i => c3_str,
data_i_o => c4_i,
data_q_o => c4_q,
data_str_o => c4_str
);
data_i_o <= c4_i;
data_q_o <= c4_q;
data_str_o <= c4_str;
end analytic_filter_h_a4_arch; | gpl-3.0 | ee073450c5ff576ab07527a55061b2b1 | 0.593037 | 2.542218 | false | false | false | false |
xcthulhu/periphondemand | src/platforms/apf27/simulation/apf27_test_pkg.vhd | 1 | 5,378 | ----------------------------------------------
-- Design Name : Test bench utils for apf27
-- File Name : apf27_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <[email protected]>
-- Version : 1.00
---------------------------------------------
-----------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package apf27_test_pkg is
CONSTANT CS_MIN : time := 13.6 ns;
CONSTANT CLOCK_PERIOD : time := 7.5188 ns;
CONSTANT WE3 : time := 2.25 ns;
CONSTANT WE4 : time := 2.25 ns;
-- write procedures
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
);
-- read procedures
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
);
end package apf27_test_pkg;
package body apf27_test_pkg is
-- Write value from imx
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Write value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_eb3_n <= '0';
wait until falling_edge(gls_clk);
wait for 2500 ps;
imx_data <= value;
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk); -- WSC = 2
end loop;
end if;
wait for 1 ns;
imx_cs_n <= '1';
imx_eb3_n <= '1';
imx_address <= (others => 'Z');
imx_data <= (others => 'Z');
end procedure imx_write;
-- Read a value from imx
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Read value
wait until falling_edge(gls_clk);
wait for WE3;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_oe_n <= '0';
wait for CS_MIN; -- minimum chip select time
if WSC > 1 then
for n in 2 to WSC loop
wait until falling_edge(gls_clk);
end loop;
--wait for CLOCK_PERIOD*(WSC-1);
end if;
wait for WE4;
value <= imx_data;
imx_cs_n <= '1';
imx_oe_n <= '1';
imx_address <= (others => 'Z');
end procedure imx_read;
end package body apf27_test_pkg;
| lgpl-2.1 | 6ad011a0cde8b359f1008a47b4723aa0 | 0.55913 | 3.609396 | false | false | false | false |
wifidar/wifidar_fpga | src/wifidar_fpga.vhdl | 1 | 6,696 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity wifidar_fpga is
generic(
num_samples: integer range 0 to 20000 := 395;
sample_length_bits: integer range 0 to 32 := 14
);
port(
-- rot_a: in std_logic;
-- rot_b: in std_logic;
-- button_in: in std_logic_vector(3 downto 0);
SPI_SS_B: out std_logic;
AMP_CS: out std_logic;
AD_CONV: out std_logic;
SF_CE0: out std_logic;
FPGA_INIT_B: out std_logic;
AMP_SHDN: out std_logic;
SPI_MOSI: out std_logic;
SPI_MISO: in std_logic;
SPI_SCK: out std_logic;
-- DAC_SCK: out std_logic;
-- DAC_CS: out std_logic;
-- DAC_MOSI: out std_logic;
-- current_mode_out: out std_logic_vector(1 downto 0);
initial_sample: in std_logic;
uart_tx: out std_logic;
debug: out std_logic;
debug2: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end wifidar_fpga;
architecture structural of wifidar_fpga is
component uart
generic(
clk_freq: integer := 50000000;
baud_rate: integer := 38400
);
port(
uart_tx: out std_logic;
data_in: in std_logic_vector(7 downto 0);
ready: out std_logic;
send_data: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component sample_buffer
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
sample_in: in std_logic_vector(sample_length_bits - 1 downto 0);
sample_out: out std_logic_vector(sample_length_bits - 1 downto 0);
sample_in_ready: in std_logic;
initial_sample: in std_logic;
sample_out_index: in std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
buffer_full: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component adc_controller
generic(
sample_div: integer := 2500
);
port(
spi_to_amp: out std_logic_vector(3 downto 0);
req_adc: out std_logic;
req_amp: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component uart_minibuf
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
data_in: in std_logic_vector (sample_length_bits -1 downto 0);
data_out: out std_logic_vector(7 downto 0);
index_data_in: out std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
sample_buffer_full: in std_logic;
uart_send_data: out std_logic;
uart_ready: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component spi_arbitrator
port(
----- other devices on SPI BUS ---
SPI_SS_B: out std_logic; -- set to 1
SF_CE0: out std_logic; -- set to 1
FPGA_INIT_B: out std_logic; -- set to 1
----- chip selects ---
AMP_CS: out std_logic; -- active low pre-amp chip select
--AD_CONV: out std_logic; -- active high ADC chip select
--DAC_CS: out std_logic; -- active low DAC chip select
----- resets ---
AMP_SHDN: out std_logic; -- ADC pre-amp shutdown signal (active high)
-- control signals
spi_controller_busy: in std_logic;
dac_ready: in std_logic;
adc_send_data: out std_logic;
amp_send_data: out std_logic;
dac_send_data: out std_logic;
req_adc: in std_logic;
req_amp: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end component;
component adc_receiver
port(
send_data: in std_logic;
busy: out std_logic;
spi_sck: out std_logic;
spi_miso: in std_logic;
ad_conv: out std_logic;
outputA: out std_logic_vector (13 downto 0);
outputB: out std_logic_vector (13 downto 0);
new_reading: out std_logic;
clk: in std_logic
);
end component;
component preamp_config
port(
preamp_done: out std_logic;
send_data: in std_logic;
busy: out std_logic;
spi_mosi: out std_logic;
spi_sck: out std_logic;
clk: in std_logic
);
end component;
component dac_serial
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end component;
signal uart_data: std_logic_vector(7 downto 0);
signal uart_send_data: std_logic;
signal uart_ready: std_logic;
signal adc_sample_data: std_logic_vector(13 downto 0);
signal sample_buffer_out: std_logic_vector(13 downto 0);
signal load_adc: std_logic;
signal sample_out_index: std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
signal sample_buffer_full: std_logic;
--signal spi_to_amp: std_logic_vector(3 downto 0);
signal req_adc: std_logic;
signal req_amp: std_logic;
signal spi_controller_busy: std_logic;
signal spi_mosi_sig2: std_logic;
signal spi_sck_sig2: std_logic;
signal spi_sck_sig3: std_logic;
signal adc_busy: std_logic;
signal adc_send: std_logic;
signal amp_send: std_logic;
signal amp_busy: std_logic;
begin
uarter: uart port map (uart_tx,uart_data,uart_ready,uart_send_data,rst,clk);
sample_buefferer: sample_buffer generic map (num_samples,sample_length_bits) port map (adc_sample_data,sample_buffer_out,load_adc,initial_sample,sample_out_index,sample_buffer_full,rst,clk);
adc_controllerer: adc_controller port map (open,req_adc,req_amp,rst,clk);
uart_minibuffer: uart_minibuf generic map (num_samples,sample_length_bits) port map (sample_buffer_out,uart_data,sample_out_index,sample_buffer_full,uart_send_data,uart_ready,rst,clk);
spi_arbitratorer: spi_arbitrator port map (SPI_SS_B,SF_CE0,FPGA_INIT_B,AMP_CS,AMP_SHDN,
spi_controller_busy,'0',adc_send,amp_send,open,
req_adc,req_amp,rst,clk);
--dac_controller: dac_serial port map (DAC_SCK,DAC_CS,DAC_MOSI,ramp_data_sig,dac_ready,dac_send,clk);
adc_spi_control: adc_receiver port map (adc_send,adc_busy,spi_sck_sig2,SPI_MISO,AD_CONV,adc_sample_data,open,load_adc,clk);
amp_controller: preamp_config port map (open,amp_send,amp_busy,spi_mosi_sig2,spi_sck_sig3,clk);
SPI_MOSI <= spi_mosi_sig2;
SPI_SCK <= spi_sck_sig2 or spi_sck_sig3;
spi_controller_busy <= adc_busy or amp_busy;
debug <= sample_buffer_full;
debug2 <= initial_sample;
end structural;
| mit | f2c15d7e62e06e06a35ff7cff42f6226 | 0.648596 | 2.856655 | false | false | false | false |
freecores/hilbert_transformer | vhdl/resize_tools.vhd | 2 | 2,650 | -- functions for resizing vectors with the comma located at the MSB
-- resize_to_msb_trunc realizes a truncation to the new wordsize, if new_size is lower than old size
-- resize_to_msb_trunc realizes a rounding to the new wordsize, if new_size is lower than old size with the use of one additional adder
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package resize_tools_pkg is
-- function declarations
function resize_to_msb_trunc(
x : std_logic_vector;
new_size : integer
) return std_logic_vector;
function resize_to_msb_round(
x : std_logic_vector;
new_size : integer
) return std_logic_vector;
end resize_tools_pkg;
-- package body
package body resize_tools_pkg is
-- function implementations
function resize_to_msb_trunc(
x : std_logic_vector;
new_size : integer
) return std_logic_vector is
variable x_res : std_logic_vector(new_size-1 downto 0);
begin
if new_size > x'length then
x_res(new_size-1 downto new_size-x'length) := x;
x_res(new_size-x'length-1 downto 0) := (others => '0');
elsif x'length >= new_size then
x_res := x(x'length-1 downto x'length-new_size);
end if;
return x_res;
end resize_to_msb_trunc;
function resize_to_msb_round(
x : std_logic_vector;
new_size : integer
) return std_logic_vector is
variable x_res : std_logic_vector(new_size-1 downto 0);
begin
if x'length = new_size then
x_res := x;
elsif new_size > x'length then
x_res(new_size-1 downto new_size-x'length) := x;
x_res(new_size-x'length-1 downto 0) := (others => '0');
elsif x'length > new_size then
if x(x'length-new_size-1) = '1' then
x_res := std_logic_vector(signed(x(x'length-1 downto x'length-new_size)) + 1);
else
x_res := x(x'length-1 downto x'length-new_size);
end if;
end if;
return x_res;
end resize_to_msb_round;
end resize_tools_pkg;
| gpl-3.0 | b50df5f76d55a81e4228bd763c16ce3e | 0.673962 | 3.324969 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tx/tx_add_crc32.vhd | 1 | 4,195 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tx_add_crc32 - Behavioral
--
-- Description: Add the required 8 bytes of preamble to the data packet.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_add_crc32 is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC := '0';
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end tx_add_crc32;
architecture Behavioral of tx_add_crc32 is
signal crc : std_logic_vector(31 downto 0) := (others => '1');
signal trailer_left : std_logic_vector(3 downto 0) := (others => '0');
begin
add_crc_proc: process(clk)
variable v_crc : std_logic_vector(31 downto 0) := (others => '1');
begin
if rising_edge(clk) then
if data_valid_in = '1' then
-- Pass the data through
data_out <= data_in;
data_valid_out <= '1';
-- Flag that we need to output 8 bytes of CRC
trailer_left <= (others => '1');
----------------------------------------
-- Update the CRC
--
-- This uses a variable to make the code
-- simple to follow and more compact
----------------------------------------
v_crc := crc;
for i in 0 to 7 loop
if data_in(i) = v_crc(31) then
v_crc := v_crc(30 downto 0) & '0';
else
v_crc := (v_crc(30 downto 0)& '0') xor x"04C11DB7";
end if;
end loop;
crc <= v_crc;
elsif trailer_left(trailer_left'high)= '1' then
-- append the CRC
data_out <= not (crc(24) & crc(25) & crc(26) & crc(27) & crc(28) & crc(29) & crc(30) & crc(31));
crc <= crc(23 downto 0) & "11111111";
trailer_left <= trailer_left(trailer_left'high-1 downto 0) & '0';
data_valid_out <= '1';
else
-- Idle
data_out <= "00000000";
data_valid_out <= '0';
end if;
end if;
end process;
end Behavioral; | mit | 4188e6c1cbc8a75026e0a56431471864 | 0.47938 | 4.462766 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_serial_input/testbench/top_input_test_tb.vhd | 1 | 9,299 | ---------------------------------------------------------------------------
-- Company : Automaticaly generated by POD
-- Author(s) :
--
-- Creation Date : 2009-05-13
-- File : Top_testinput_tb.vhd
--
-- Abstract :
-- insert a description here
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.apf27_test_pkg.all;
entity top_input_test_tb is
end entity top_input_test_tb;
architecture RTL of top_input_test_tb is
CONSTANT HALF_PERIODE : time := 3.75939849624 ns; -- Half clock period
CONSTANT IRQ_MNGR00_IRQ_MNGR_MASK : std_logic_vector := x"0000";
CONSTANT IRQ_MNGR00_IRQ_MNGR_PENDING_ACK : std_logic_vector := x"0002";
CONSTANT IRQ_MNGR00_ID : std_logic_vector := x"0004";
CONSTANT INPUT_DATA : std_logic_vector := x"0008";
CONSTANT INPUT_READ_PER : std_logic_vector := x"000a";
CONSTANT INPUT_BUS_PER : std_logic_vector := x"000c";
CONSTANT INPUT_ID : std_logic_vector := x"000e";
CONSTANT WSC : natural := 4;
signal irq_mngr00_gls_irq : std_logic;
signal imx27_wb16_wrapper00_imx_cs_n : std_logic;
signal imx27_wb16_wrapper00_imx_data : std_logic_vector(15 downto 0);
signal rstgen_syscon00_ext_clk : std_logic;
signal imx27_wb16_wrapper00_imx_eb3_n : std_logic;
signal imx27_wb16_wrapper00_imx_oe_n : std_logic;
signal imx27_wb16_wrapper00_imx_address : std_logic_vector(11 downto 0);
signal input_spi_ld_n : std_logic;
signal input_spi_sop : std_logic;
signal input_spi_sip : std_logic;
signal input_spi_clk : std_logic;
signal general_input : std_logic_vector( 7 downto 0);
component top_input_test
port (
irq_mngr00_gls_irq : out std_logic;
imx27_wb16_wrapper00_imx_cs_n : in std_logic;
imx27_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
rstgen_syscon00_ext_clk : in std_logic;
imx27_wb16_wrapper00_imx_eb3_n : in std_logic;
imx27_wb16_wrapper00_imx_oe_n : in std_logic;
imx27_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
input_spi_ld_n : out std_logic;
input_spi_sop : in std_logic;
input_spi_sip : out std_logic;
input_spi_clk : out std_logic
);
end component top_input_test;
component serializer
port (
-- serial signals
clk : in std_logic ;
ce_n : in std_logic ;
ld_n : in std_logic ;
sop : out std_logic ;
sip : in std_logic ;
-- parallel input
input : in std_logic_vector( 7 downto 0)
);
end component serializer;
signal value : std_logic_vector( 15 downto 0);
signal read_per_s : std_logic_vector(15 downto 0) := x"0001";
signal bus_per_s : std_logic_vector(15 downto 0) := x"0070";
begin
top : top_input_test
port map(
irq_mngr00_gls_irq => irq_mngr00_gls_irq,
imx27_wb16_wrapper00_imx_cs_n => imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_data => imx27_wb16_wrapper00_imx_data,
rstgen_syscon00_ext_clk => rstgen_syscon00_ext_clk,
imx27_wb16_wrapper00_imx_eb3_n => imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_oe_n => imx27_wb16_wrapper00_imx_oe_n,
imx27_wb16_wrapper00_imx_address => imx27_wb16_wrapper00_imx_address,
input_spi_ld_n => input_spi_ld_n,
input_spi_sop => input_spi_sop,
input_spi_sip => input_spi_sip,
input_spi_clk => input_spi_clk
);
serializer_p : serializer
port map (
clk => input_spi_clk,
ce_n => '0',
ld_n => input_spi_ld_n,
sop => input_spi_sop,
sip => input_spi_sip,
input=> general_input
);
stimulis : process
begin
imx27_wb16_wrapper00_imx_cs_n <= '1';
imx27_wb16_wrapper00_imx_oe_n <= '1';
imx27_wb16_wrapper00_imx_eb3_n <= '1';
imx27_wb16_wrapper00_imx_address <= (others => '0');
imx27_wb16_wrapper00_imx_data <= (others => 'Z');
-- enable interruption for input industrial
imx_write(IRQ_MNGR00_IRQ_MNGR_MASK,x"0001",
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
general_input <= x"ca";
-- configure module (enable interrupts)
imx_write(INPUT_DATA,x"0100",
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
-- configure read period
imx_read(INPUT_READ_PER,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
assert value = x"0000"
report "Wrong read per default value : "&integer'image(to_integer(unsigned(value)))
severity warning;
imx_write(INPUT_READ_PER,read_per_s,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
imx_read(INPUT_READ_PER,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
assert value = read_per_s
report "Wrong read per default value : "&integer'image(to_integer(unsigned(value)))
severity warning;
-- wait for interruption (value changed)
-----------------------------------------
wait until rising_edge(irq_mngr00_gls_irq);
imx_write(IRQ_MNGR00_IRQ_MNGR_PENDING_ACK,x"0001", -- acknowledge interrupt
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
-- read value
imx_read(INPUT_DATA,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
assert value(7 downto 0) = general_input report "Wrong value read" severity warning;
report "read value "&integer'image(to_integer(unsigned(value(7 downto 0))))&".";
wait for 9 us;
general_input <= x"ac";
-- configure bus period
imx_read(INPUT_BUS_PER,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
assert value = x"010A"
report "Wrong bus per default value : "&integer'image(to_integer(unsigned(value)))
severity warning;
imx_write(INPUT_BUS_PER,bus_per_s,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
imx_read(INPUT_BUS_PER,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
assert value = bus_per_s
report "Wrong bus per default value : "&integer'image(to_integer(unsigned(value)))
severity warning;
-- wait for interruption (value changed)
-----------------------------------------
wait until rising_edge(irq_mngr00_gls_irq);
imx_write(IRQ_MNGR00_IRQ_MNGR_PENDING_ACK,x"0001", -- acknowledge interrupt
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
-- read value
imx_read(INPUT_DATA,value,
rstgen_syscon00_ext_clk,imx27_wb16_wrapper00_imx_cs_n,
imx27_wb16_wrapper00_imx_oe_n,imx27_wb16_wrapper00_imx_eb3_n,
imx27_wb16_wrapper00_imx_address,imx27_wb16_wrapper00_imx_data,
WSC);
wait for 50 us;
assert false report "End of test" severity error;
end process stimulis;
clockp : process
begin
rstgen_syscon00_ext_clk <= '1';
wait for HALF_PERIODE;
rstgen_syscon00_ext_clk <= '0';
wait for HALF_PERIODE;
end process clockp;
end architecture RTL;
| lgpl-2.1 | cbca739ec51f1fec5ee42addba8ee811 | 0.600602 | 3.160775 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx2/top.vhdl | 1 | 3,098 | --
-- Top level of gtx2 example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
use FPGALIB.sync.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
rst_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
clk_o : out std_logic;
sma_rx_p_i : in std_logic;
sma_rx_n_i : in std_logic;
sma_tx_p_o : out std_logic;
sma_tx_n_o : out std_logic;
pbc_i : in std_logic;
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of top is
constant BYTES : positive:=2;
signal sysclk, clk : std_logic;
signal rst_gtx, rst_loop : std_logic;
signal locked, ready : std_logic;
signal loopback : std_logic;
-- GBT data
signal rx_data, rx_data_bound, tx_data : std_logic_vector(BYTES*8-1 downto 0);
signal rx_isk, rx_isk_bound, tx_isk : std_logic_vector(BYTES-1 downto 0);
--
signal finish : std_logic;
signal errors : std_logic_vector(4 downto 0);
begin
-- From 200 MHz differential to 150 MHz single-ended.
mmcm_inst: entity work.mmcm200to150
port map (
CLK_IN1_P => clk_p_i,
CLK_IN1_N => clk_n_i,
CLK_OUT1 => sysclk,
RESET => rst_i,
LOCKED => locked
);
rst_gtx <= not locked;
loopback <= not pbc_i;
gbt_i: entity work.Wrapper
port map (
clk_i => sysclk,
rst_i => rst_gtx,
clk_o => clk,
--
rxp_i => sma_rx_p_i,
rxn_i => sma_rx_n_i,
txp_o => sma_tx_p_o,
txn_o => sma_tx_n_o,
--
loopback_i=> loopback,
rx_data_o => rx_data,
rx_isk_o => rx_isk,
tx_data_i => tx_data,
tx_isk_i => tx_isk,
ready_o => ready
);
-- To ensure that we understand *rx_data* in the same order that *tx_data*.
bound_i: Boundary
generic map(BYTES => BYTES)
port map(
clk_i => clk,
pattern_i => (others => '1'),
comma_i => rx_isk,
data_i => rx_data,
comma_o => rx_isk_bound,
data_o => rx_data_bound
);
rst_loop <= not ready;
-- For test the loop.
loop_i: TransLoop
generic map(
TSIZE => 2048,
DBYTES => BYTES,
FSIZE => 512
)
port map(
-- TX side
tx_clk_i => clk,
tx_rst_i => rst_loop,
tx_data_i => (others => '0'),
tx_data_o => tx_data,
tx_isk_o => tx_isk,
tx_ready_i => ready,
-- RX side
rx_clk_i => clk,
rx_rst_i => rst_loop,
rx_data_i => rx_data_bound,
rx_isk_i => rx_isk_bound,
rx_errors_o => errors,
rx_finish_o => finish,
rx_cycles_o => open
);
leds_o <= finish & "00" & errors;
clk_o <= clk;
end architecture RTL;
| bsd-3-clause | ac1720a98e96ce87d1e6b157dc7e494a | 0.505487 | 3.067327 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/rtl/mig_39_2.vhd | 1 | 35,086 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : mig_39_2.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mig_39_2 is
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 6000;
-- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 2
-- External memory bank address width.
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_cke : out std_logic;
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c1_p1_cmd_clk : in std_logic;
c1_p1_cmd_en : in std_logic;
c1_p1_cmd_instr : in std_logic_vector(2 downto 0);
c1_p1_cmd_bl : in std_logic_vector(5 downto 0);
c1_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p1_cmd_empty : out std_logic;
c1_p1_cmd_full : out std_logic;
c1_p1_wr_clk : in std_logic;
c1_p1_wr_en : in std_logic;
c1_p1_wr_mask : in std_logic_vector(C1_P1_MASK_SIZE - 1 downto 0);
c1_p1_wr_data : in std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_wr_full : out std_logic;
c1_p1_wr_empty : out std_logic;
c1_p1_wr_count : out std_logic_vector(6 downto 0);
c1_p1_wr_underrun : out std_logic;
c1_p1_wr_error : out std_logic;
c1_p1_rd_clk : in std_logic;
c1_p1_rd_en : in std_logic;
c1_p1_rd_data : out std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_rd_full : out std_logic;
c1_p1_rd_empty : out std_logic;
c1_p1_rd_count : out std_logic_vector(6 downto 0);
c1_p1_rd_overflow : out std_logic;
c1_p1_rd_error : out std_logic
);
end mig_39_2;
architecture arc of mig_39_2 is
component memc1_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb1_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb1_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb1_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb1_dram_cke : out std_logic;
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C1_CLKOUT0_DIVIDE : integer := 2;
constant C1_CLKOUT1_DIVIDE : integer := 2;
constant C1_CLKOUT2_DIVIDE : integer := 16;
constant C1_CLKOUT3_DIVIDE : integer := 8;
constant C1_CLKFBOUT_MULT : integer := 4;
constant C1_DIVCLK_DIVIDE : integer := 1;
constant C1_INCLK_PERIOD : integer := ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
constant C1_ARB_NUM_TIME_SLOTS : integer := 12;
constant C1_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"10";
constant C1_MEM_TRAS : integer := 42000;
constant C1_MEM_TRCD : integer := 18000;
constant C1_MEM_TREFI : integer := 7800000;
constant C1_MEM_TRFC : integer := 70000;
constant C1_MEM_TRP : integer := 18000;
constant C1_MEM_TWR : integer := 15000;
constant C1_MEM_TRTP : integer := 7500;
constant C1_MEM_TWTR : integer := 1;
constant C1_MEM_TYPE : string := "MDDR";
constant C1_MEM_DENSITY : string := "256Mb";
constant C1_MEM_BURST_LEN : integer := 4;
constant C1_MEM_CAS_LATENCY : integer := 3;
constant C1_MEM_NUM_COL_BITS : integer := 9;
constant C1_MEM_DDR1_2_ODS : string := "FULL";
constant C1_MEM_DDR2_RTT : string := "50OHMS";
constant C1_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C1_MEM_DDR2_3_PA_SR : string := "FULL";
constant C1_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C1_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C1_MEM_DDR3_ODS : string := "DIV6";
constant C1_MEM_DDR3_RTT : string := "DIV2";
constant C1_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C1_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C1_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C1_MEM_MOBILE_PA_SR : string := "FULL";
constant C1_MEM_MDDR_ODS : string := "HALF";
constant C1_MC_CALIB_BYPASS : string := "NO";
constant C1_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C1_MC_CALIBRATION_DELAY : string := "HALF";
constant C1_SKIP_IN_TERM_CAL : integer := 1;
constant C1_SKIP_DYNAMIC_CAL : integer := 0;
constant C1_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_DQ0_TAP_DELAY_VAL : integer := 0;
constant C1_DQ1_TAP_DELAY_VAL : integer := 0;
constant C1_DQ2_TAP_DELAY_VAL : integer := 0;
constant C1_DQ3_TAP_DELAY_VAL : integer := 0;
constant C1_DQ4_TAP_DELAY_VAL : integer := 0;
constant C1_DQ5_TAP_DELAY_VAL : integer := 0;
constant C1_DQ6_TAP_DELAY_VAL : integer := 0;
constant C1_DQ7_TAP_DELAY_VAL : integer := 0;
constant C1_DQ8_TAP_DELAY_VAL : integer := 0;
constant C1_DQ9_TAP_DELAY_VAL : integer := 0;
constant C1_DQ10_TAP_DELAY_VAL : integer := 0;
constant C1_DQ11_TAP_DELAY_VAL : integer := 0;
constant C1_DQ12_TAP_DELAY_VAL : integer := 0;
constant C1_DQ13_TAP_DELAY_VAL : integer := 0;
constant C1_DQ14_TAP_DELAY_VAL : integer := 0;
constant C1_DQ15_TAP_DELAY_VAL : integer := 0;
constant C1_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
signal c1_async_rst : std_logic;
signal c1_sysclk_2x : std_logic;
signal c1_sysclk_2x_180 : std_logic;
signal c1_pll_ce_0 : std_logic;
signal c1_pll_ce_90 : std_logic;
signal c1_pll_lock : std_logic;
signal c1_mcb_drp_clk : std_logic;
signal c1_cmp_error : std_logic;
signal c1_cmp_data_valid : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c1_cmp_data : std_logic_vector(31 downto 0);
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
begin
c1_sys_clk_p <= '0';
c1_sys_clk_n <= '0';
c1_selfrefresh_enter <= '0';
memc1_infrastructure_inst : memc1_infrastructure
generic map
(
C_RST_ACT_LOW => C1_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C1_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C1_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C1_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C1_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C1_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C1_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C1_INCLK_PERIOD
)
port map
(
sys_clk_p => c1_sys_clk_p,
sys_clk_n => c1_sys_clk_n,
sys_clk => c1_sys_clk,
sys_rst_i => c1_sys_rst_i,
clk0 => c1_clk0,
rst0 => c1_rst0,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk
);
-- wrapper instantiation
memc1_wrapper_inst : memc1_wrapper
generic map
(
C_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C1_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C1_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C1_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C1_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C1_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C1_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C1_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C1_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C1_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C1_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C1_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C1_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C1_ARB_TIME_SLOT_11,
C_MEM_TRAS => C1_MEM_TRAS,
C_MEM_TRCD => C1_MEM_TRCD,
C_MEM_TREFI => C1_MEM_TREFI,
C_MEM_TRFC => C1_MEM_TRFC,
C_MEM_TRP => C1_MEM_TRP,
C_MEM_TWR => C1_MEM_TWR,
C_MEM_TRTP => C1_MEM_TRTP,
C_MEM_TWTR => C1_MEM_TWTR,
C_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_TYPE => C1_MEM_TYPE,
C_MEM_DENSITY => C1_MEM_DENSITY,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C1_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C1_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C1_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C1_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C1_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C1_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C1_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C1_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C1_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C1_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C1_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C1_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C1_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C1_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C1_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C1_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C1_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C1_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C1_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C1_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C1_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C1_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C1_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C1_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C1_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C1_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C1_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C1_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C1_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C1_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C1_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C1_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C1_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C1_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C1_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C1_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C1_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C1_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C1_DQ15_TAP_DELAY_VAL
)
port map
(
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_rzq => mcb1_rzq,
mcb1_dram_udm => mcb1_dram_udm,
calib_done => c1_calib_done,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
p0_cmd_clk => c1_p0_cmd_clk,
p0_cmd_en => c1_p0_cmd_en,
p0_cmd_instr => c1_p0_cmd_instr,
p0_cmd_bl => c1_p0_cmd_bl,
p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
p0_cmd_empty => c1_p0_cmd_empty,
p0_cmd_full => c1_p0_cmd_full,
p0_wr_clk => c1_p0_wr_clk,
p0_wr_en => c1_p0_wr_en,
p0_wr_mask => c1_p0_wr_mask,
p0_wr_data => c1_p0_wr_data,
p0_wr_full => c1_p0_wr_full,
p0_wr_empty => c1_p0_wr_empty,
p0_wr_count => c1_p0_wr_count,
p0_wr_underrun => c1_p0_wr_underrun,
p0_wr_error => c1_p0_wr_error,
p0_rd_clk => c1_p0_rd_clk,
p0_rd_en => c1_p0_rd_en,
p0_rd_data => c1_p0_rd_data,
p0_rd_full => c1_p0_rd_full,
p0_rd_empty => c1_p0_rd_empty,
p0_rd_count => c1_p0_rd_count,
p0_rd_overflow => c1_p0_rd_overflow,
p0_rd_error => c1_p0_rd_error,
p1_cmd_clk => c1_p1_cmd_clk,
p1_cmd_en => c1_p1_cmd_en,
p1_cmd_instr => c1_p1_cmd_instr,
p1_cmd_bl => c1_p1_cmd_bl,
p1_cmd_byte_addr => c1_p1_cmd_byte_addr,
p1_cmd_empty => c1_p1_cmd_empty,
p1_cmd_full => c1_p1_cmd_full,
p1_wr_clk => c1_p1_wr_clk,
p1_wr_en => c1_p1_wr_en,
p1_wr_mask => c1_p1_wr_mask,
p1_wr_data => c1_p1_wr_data,
p1_wr_full => c1_p1_wr_full,
p1_wr_empty => c1_p1_wr_empty,
p1_wr_count => c1_p1_wr_count,
p1_wr_underrun => c1_p1_wr_underrun,
p1_wr_error => c1_p1_wr_error,
p1_rd_clk => c1_p1_rd_clk,
p1_rd_en => c1_p1_rd_en,
p1_rd_data => c1_p1_rd_data,
p1_rd_full => c1_p1_rd_full,
p1_rd_empty => c1_p1_rd_empty,
p1_rd_count => c1_p1_rd_count,
p1_rd_overflow => c1_p1_rd_overflow,
p1_rd_error => c1_p1_rd_error,
selfrefresh_enter => c1_selfrefresh_enter,
selfrefresh_mode => c1_selfrefresh_mode
);
end arc;
| cc0-1.0 | 30f39ebeed4c126fc95dcf4af6b26e6b | 0.454825 | 3.429717 | false | false | false | false |
wifidar/wifidar_fpga | src/dac_section/ramp_block.vhdl | 1 | 3,512 | library IEEE;
use IEEE.std_logic_1164.all;
entity ramp_block is
port(
rot_a: in std_logic;
rot_b: in std_logic;
button_in: in std_logic_vector(3 downto 0);
new_waveform: out std_logic;
ramp_data: out std_logic_vector(11 downto 0);
current_mode_out: out std_logic_vector(1 downto 0);
clk: in std_logic
);
end ramp_block;
architecture structural of ramp_block is
component ramp_gen
generic(
ramp_length_bits: integer := 10
);
port(
x_in: in std_logic_vector(ramp_length_bits - 1 downto 0);
ramp_out: out std_logic_vector(11 downto 0) -- 12 bit output for DAC
);
end component;
component buttonStructural
port(
rot_a: in std_logic;
rot_b: in std_logic;
button_in: in std_logic_vector(3 downto 0);
current_mode: out std_logic_vector(1 downto 0);
current_channel: out std_logic_vector(1 downto 0);
adjust: out std_logic_vector(1 downto 0);
clk: in std_logic
);
end component;
component phase_acc
generic(
sine_length_bits: integer := 10
);
port(
x_out: out std_logic_vector(sine_length_bits - 1 downto 0);
freq_mult: in std_logic_vector(9 downto 0);
phase_in: in std_logic_vector(7 downto 0);
new_signal: out std_logic;
clk: in std_logic
);
end component;
component dac_controller
generic(
sine_length_bits: integer := 10;
num_channels: integer := 1
);
port(
-- sine wave control related
freq_mult: out std_logic_vector((num_channels * 10) - 1 downto 0);
offset_adjust: out std_logic_vector((num_channels * 12) - 1 downto 0);
amplitude_adjust: out std_logic_vector((num_channels * 6) - 1 downto 0);
-- control related
current_mode: in std_logic_vector (1 downto 0); -- 00 = freq, 01 = phase, 10 = amplitude
current_channel: in std_logic_vector(1 downto 0);
adjust: in std_logic_vector(1 downto 0); -- pulses for adjustment of values, 0 up, 1 down
clk: in std_logic
);
end component;
component amplitude_adjust
port(
sine_in: in std_logic_vector(11 downto 0);
sine_out: out std_logic_vector(11 downto 0);
adjust: in std_logic_vector(5 downto 0);
clk: in std_logic
);
end component;
component offset_adjust
port(
ramp_in: in std_logic_vector(11 downto 0);
ramp_out: out std_logic_vector(11 downto 0);
adjust: in std_logic_vector(11 downto 0)
);
end component;
signal curr_ramp_sig: std_logic_vector(11 downto 0);
signal curr_x_sig: std_logic_vector(9 downto 0);
signal current_mode_sig: std_logic_vector(1 downto 0);
signal current_channel_sig: std_logic_vector(1 downto 0);
signal adjust_sig: std_logic_vector(1 downto 0);
signal freq_mult_sig: std_logic_vector(9 downto 0);
signal offset_adjust_sig: std_logic_vector(11 downto 0);
signal amplitude_adjust_sig: std_logic_vector(5 downto 0);
signal amplitude_adjusted_ramp: std_logic_vector(11 downto 0);
begin
ramp: ramp_gen port map (curr_x_sig,curr_ramp_sig);
buttons: buttonStructural port map (rot_a,rot_b,button_in,current_mode_sig,current_channel_sig,adjust_sig,clk);
phase_accumulator: phase_acc port map (curr_x_sig,freq_mult_sig,"00000000",new_waveform,clk);
controller: dac_controller port map (freq_mult_sig,offset_adjust_sig,amplitude_adjust_sig,current_mode_sig,current_channel_sig,adjust_sig,clk);
amp_adj: amplitude_adjust port map (curr_ramp_sig,amplitude_adjusted_ramp,amplitude_adjust_sig,clk);
off_adj: offset_adjust port map (amplitude_adjusted_ramp,ramp_data,offset_adjust_sig);
current_mode_out <= current_mode_sig;
end structural;
| mit | 9bcc52aef1b05f753af912dfcc630cf6 | 0.700171 | 2.951261 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/terasic_de10nano/clock/top.vhdl | 1 | 1,088 | --
-- Clock on de10nano
--
-- There is three clock sources on de10nano board:
-- * 3 x On-board 50MHz clock oscillator.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017-2019 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_i : in std_logic;
clk2_i : in std_logic;
clk3_i : in std_logic;
rst_n_i : in std_logic;
leds_o : out std_logic_vector(2 downto 0)
);
end entity Top;
architecture RTL of Top is
signal rst, led0, led1, led2 : std_logic;
begin
rst <= not rst_n_i;
blink0prog_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk_i, rst_i => rst, blink_o => led0);
blink1prog_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk2_i, rst_i => rst, blink_o => led1);
blink2prog_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk3_i, rst_i => rst, blink_o => led2);
leds_o <= led2 & led1 & led0;
end architecture RTL;
| bsd-3-clause | df61d9e8155bb10e5a81b6774173d983 | 0.622243 | 2.870712 | false | false | false | false |
daniw/ecs | vhdl/sw10/calc/calc.vhd | 1 | 3,807 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:28:55 11/20/2014
-- Design Name:
-- Module Name: calc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity calc is
generic (clk_frq: Integer := 50_000_000); -- 50 MHz
Port (
rst : in STD_ULOGIC; -- BTN_SOUTH
clk : in STD_ULOGIC;
rot_c : in STD_ULOGIC;
btn_east : in STD_ULOGIC;
btn_west : in STD_ULOGIC;
btn_north : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0));
end calc;
architecture Behavioral of calc is
signal op1 : STD_ULOGIC_VECTOR (3 downto 0);
signal op2 : STD_ULOGIC_VECTOR (3 downto 0);
signal op : STD_ULOGIC_VECTOR (2 downto 0);
signal dbnc_cnt : integer;
signal rot_c_prev : STD_ULOGIC;
signal rot_c_dbnc : STD_ULOGIC;
component ctrl is
Port (
rst : in STD_ULOGIC;
clk : in STD_ULOGIC;
rot_c : in STD_ULOGIC;
btn_east : in STD_ULOGIC;
btn_west : in STD_ULOGIC;
btn_north : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
op1 : out STD_ULOGIC_VECTOR (3 downto 0);
op2 : out STD_ULOGIC_VECTOR (3 downto 0);
op : out STD_ULOGIC_VECTOR (2 downto 0)
);
end component ctrl;
component proc is
Port (
op1 : in STD_ULOGIC_VECTOR (3 downto 0);
op2 : in STD_ULOGIC_VECTOR (3 downto 0);
op : in STD_ULOGIC_VECTOR (2 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0)
);
end component;
begin
ctrlinst : ctrl
Port Map ( rst => rst ,
clk => clk ,
rot_c => rot_c_dbnc,
btn_east => btn_east ,
btn_west => btn_west ,
btn_north => btn_north,
sw => sw ,
op1 => op1 ,
op2 => op2 ,
op => op
);
procinst : proc
Port Map ( op1 => op1,
op2 => op2,
op => op ,
led => led
);
dbnc_rot_c : process(rot_c, rst, clk)
begin
if rst = '1' then
dbnc_cnt <= 5000000;
rot_c_dbnc <= '0';
elsif rising_edge(clk) then
if dbnc_cnt = 0 then
dbnc_cnt <= 5000000;
rot_c_dbnc <= rot_c_dbnc;
elsif dbnc_cnt < 5000000 then
dbnc_cnt <= dbnc_cnt - 1;
rot_c_dbnc <= rot_c_dbnc;
elsif rot_c_prev /= rot_c then
dbnc_cnt <= dbnc_cnt - 1;
rot_c_dbnc <= rot_c;
else
dbnc_cnt <= 5000000;
rot_c_dbnc <= rot_c_dbnc;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 0e7dda9d9f2d30bcc2eff19cb9c20f6a | 0.444444 | 3.936918 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_FPGA_webserver.vhd | 1 | 3,669 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.06.2016 22:56:59
-- Design Name:
-- Module Name: tb_FPGA_webserver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_FPGA_webserver is
end tb_FPGA_webserver;
architecture Behavioral of tb_FPGA_webserver is
component FPGA_webserver is
Port ( clk100MHz : in std_logic; -- system clock
switches : in std_logic_vector(3 downto 0);
leds : out std_logic_vector(7 downto 0);
-- Ethernet Control signals
eth_int_b : in std_logic; -- interrupt
eth_pme_b : in std_logic; -- power management event
eth_rst_b : out std_logic := '0'; -- reset
-- Ethernet Management interface
eth_mdc : out std_logic := '0';
eth_mdio : inout std_logic := '0';
-- Ethernet Receive interface
eth_rxck : in std_logic;
eth_rxctl : in std_logic;
eth_rxd : in std_logic_vector(3 downto 0);
-- Ethernet Transmit interface
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0')
);
end component;
signal clk100MHz : std_logic; -- system clock
signal switches : std_logic_vector(3 downto 0);
signal leds : std_logic_vector(7 downto 0);
-- Ethernet Control signals
signal eth_int_b : std_logic := '0'; -- interrupt
signal eth_pme_b : std_logic := '0'; -- power management event
signal eth_rst_b : std_logic := '0'; -- reset
-- Ethernet Management interface
signal eth_mdc : std_logic := '0';
signal eth_mdio : std_logic := '0';
-- Ethernet Receive interface
signal eth_rxck : std_logic := '0';
signal eth_rxctl : std_logic := '0';
signal eth_rxd : std_logic_vector(3 downto 0) := (others => '0');
-- Ethernet Transmit interface
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
begin
process
begin
clk100MHz <= '1';
wait for 5.0 ns;
clk100Mhz <= '0';
wait for 5.0 ns;
end process;
uut: FPGA_webserver port map (
clk100MHz => clk100MHz,
switches => switches,
leds => leds,
-- Ethernet Control signals
eth_int_b => eth_int_b,
eth_pme_b => eth_pme_b,
eth_rst_b => eth_rst_b,
-- Ethernet Management interface
eth_mdc => eth_mdc,
eth_mdio => eth_mdio,
-- Ethernet Receive interface
eth_rxck => eth_rxck,
eth_rxctl => eth_rxctl,
eth_rxd => eth_rxd,
-- Ethernet Transmit interface
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd
);
end Behavioral;
| mit | b64f68ba05fc18ada5ba9f41e21e4881 | 0.529845 | 3.928266 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/rom.vhd | 1 | 2,115 | -------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 12-May-14
-------------------------------------------------------------------------------
-- Description:
-- Program memory for simple von-Neumann MCU with registerd read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: DW
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity rom is
port(clk : in std_logic;
-- ROM bus signals
bus_in : in t_bus2ros;
bus_out : out t_ros2bus
);
end rom;
architecture rtl of rom is
type t_rom is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
constant rom_table : t_rom := (
---------------------------------------------------------------------------
-- program code -----------------------------------------------------------
---------------------------------------------------------------------------
0 => X"FFFF", -- command xy
1 => X"EEEE", -- command xy
2 => X"DDDD", -- command xy
3 => X"CCCC", -- command xy
4 => X"BBBB", -- command xy
5 => X"AAAA", -- command xy
6 => X"9999", -- command xy
7 => X"8888", -- command xy
8 => X"7777", -- command xy
others => (others => '0')
);
begin
-----------------------------------------------------------------------------
-- sequential process: ROM table with registerd output
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
bus_out.data <= rom_table(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
| gpl-2.0 | 6419a105d4b5e1b08cb1c57e4c66f744 | 0.313948 | 5.36802 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_zc706/gtx/wrapper.vhdl | 1 | 8,346 | --
-- Wrapper of gtx example
--
-- Author:
-- * Rodrigo A. Melo, [email protected]
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
gtxclk_i : in std_logic;
sysclk_i : in std_logic;
rst_i : in std_logic;
--
rxp_i : in std_logic;
rxn_i : in std_logic;
txp_o : out std_logic;
txn_o : out std_logic;
--
loopback_i: in std_logic;
rx_data_o : out std_logic_vector(39 downto 0);
tx_data_i : in std_logic_vector(39 downto 0);
ready_o : out std_logic
);
end entity Wrapper;
architecture Structural of Wrapper is
signal rx_fsm_reset, tx_fsm_reset : std_logic;
signal rxresetdone, txresetdone : std_logic;
signal txoutclk, txusrclk : std_logic;
signal loopback : std_logic_vector(2 downto 0);
signal qplloutclk, qplloutrefclk : std_logic;
signal qplllock, qpllrefclklost : std_logic;
signal qpllreset : std_logic;
begin
loopback <= '0' & loopback_i & '0';
ready_o <= rxresetdone and txresetdone and rx_fsm_reset and tx_fsm_reset;
gbt1_i : entity work.gbt1
port map (
sysclk_in => sysclk_i,
soft_reset_tx_in => '0',
soft_reset_rx_in => '0',
dont_reset_on_data_error_in => '0',
gt0_tx_fsm_reset_done_out => tx_fsm_reset,
gt0_rx_fsm_reset_done_out => rx_fsm_reset,
gt0_data_valid_in => '0',
---------------------------- Channel - DRP Ports --------------------------
gt0_drpaddr_in => "000000000",
gt0_drpclk_in => sysclk_i,
gt0_drpdi_in => "0000000000000000",
gt0_drpdo_out => open,
gt0_drpen_in => '0',
gt0_drprdy_out => open,
gt0_drpwe_in => '0',
--------------------------- Digital Monitor Ports --------------------------
gt0_dmonitorout_out => open,
------------------------------- Loopback Ports -----------------------------
gt0_loopback_in => loopback,
--------------------- RX Initialization and Reset Ports --------------------
gt0_eyescanreset_in => '0',
gt0_rxuserrdy_in => '0',
-------------------------- RX Margin Analysis Ports ------------------------
gt0_eyescandataerror_out => open,
gt0_eyescantrigger_in => '0',
------------------ Receive Ports - FPGA RX Interface Ports -----------------
gt0_rxusrclk_in => txusrclk,
gt0_rxusrclk2_in => txusrclk,
------------------ Receive Ports - FPGA RX interface Ports -----------------
gt0_rxdata_out => rx_data_o,
--------------------------- Receive Ports - RX AFE -------------------------
gt0_gtxrxp_in => rxp_i,
------------------------ Receive Ports - RX AFE Ports ----------------------
gt0_gtxrxn_in => rxn_i,
--------------------- Receive Ports - RX Equalizer Ports -------------------
gt0_rxdfelpmreset_in => '0',
gt0_rxmonitorout_out => open,
gt0_rxmonitorsel_in => "00",
--------------- Receive Ports - RX Fabric Output Control Ports -------------
gt0_rxoutclkfabric_out => open,
------------- Receive Ports - RX Initialization and Reset Ports ------------
gt0_gtrxreset_in => '0',
gt0_rxpmareset_in => '0',
-------------- Receive Ports -RX Initialization and Reset Ports ------------
gt0_rxresetdone_out => rxresetdone,
--------------------- TX Initialization and Reset Ports --------------------
gt0_gttxreset_in => '0',
gt0_txuserrdy_in => '0',
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
gt0_txusrclk_in => txusrclk,
gt0_txusrclk2_in => txusrclk,
------------------ Transmit Ports - TX Data Path interface -----------------
gt0_txdata_in => tx_data_i,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
gt0_gtxtxn_out => txn_o,
gt0_gtxtxp_out => txp_o,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
gt0_txoutclk_out => txoutclk,
gt0_txoutclkfabric_out => open,
gt0_txoutclkpcs_out => open,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
gt0_txresetdone_out => txresetdone,
--
gt0_qplllock_in => qplllock,
gt0_qpllrefclklost_in => qpllrefclklost,
gt0_qpllreset_out => qpllreset,
gt0_qplloutclk_in => qplloutclk,
gt0_qplloutrefclk_in => qplloutrefclk
);
txoutclk_i : BUFG
port map (I => txoutclk, O => txusrclk);
gtxe2_common_i : GTXE2_COMMON
generic map (
-- Simulation attributes
SIM_RESET_SPEEDUP => ("TRUE"),
SIM_QPLLREFCLK_SEL => "111", -- "010"
SIM_VERSION => ("4.0"),
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000040000001000"),
COMMON_CFG => (x"00000000"),
QPLL_CFG => (x"0680181"),
QPLL_CLKOUT_CFG => ("0000"),
QPLL_COARSE_FREQ_OVRD => ("010000"),
QPLL_COARSE_FREQ_OVRD_EN => ('0'),
QPLL_CP => ("0000011111"),
QPLL_CP_MONITOR_EN => ('0'),
QPLL_DMONITOR_SEL => ('0'),
QPLL_FBDIV => ("0101110000"),
QPLL_FBDIV_MONITOR_EN => ('0'),
QPLL_FBDIV_RATIO => ('1'),
QPLL_INIT_CFG => (x"000006"),
QPLL_LOCK_CFG => (x"21E8"),
QPLL_LPF => ("1111"),
QPLL_REFCLK_DIV => (2)
)
port map (
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => "00000000",
DRPCLK => '0',
DRPDI => "0000000000000000",
DRPDO => open,
DRPEN => '0',
DRPRDY => open,
DRPWE => '0',
---------------------- Common Block - Ref Clock Ports ---------------------
GTGREFCLK => gtxclk_i,
GTNORTHREFCLK0 => '0',
GTNORTHREFCLK1 => '0',
GTREFCLK0 => '0',
GTREFCLK1 => '0',
GTSOUTHREFCLK0 => '0',
GTSOUTHREFCLK1 => '0',
------------------------- Common Block - QPLL Ports -----------------------
QPLLDMONITOR => open,
----------------------- Common Block - Clocking Ports ----------------------
QPLLOUTCLK => qplloutclk,
QPLLOUTREFCLK => qplloutrefclk,
REFCLKOUTMONITOR => open,
------------------------- Common Block - QPLL Ports ------------------------
QPLLFBCLKLOST => open,
QPLLLOCK => qplllock,
QPLLLOCKDETCLK => sysclk_i,
QPLLLOCKEN => '1',
QPLLOUTRESET => '0',
QPLLPD => '0',
QPLLREFCLKLOST => qpllrefclklost,
QPLLREFCLKSEL => "111", -- "010"
QPLLRESET => qpllreset,
QPLLRSVD1 => "0000000000000000",
QPLLRSVD2 => "11111",
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => '1',
BGMONITORENB => '1',
BGPDB => '1',
BGRCALOVRD => "11111",
PMARSVD => "00000000",
RCALENB => '1'
);
end architecture Structural;
| bsd-3-clause | 1adfb43a9f8fa9d6b57eecc48f8d914b | 0.413372 | 4.35595 | false | false | false | false |
daniw/ecs | vhdl/sw02/ueb2_1/EnableGate.vhd | 1 | 1,573 | -------------------------------------------------------------------------------
-- Company : HSLU, Waj
-- Create Date: 20-Apr-12
-- Project : ECS, Uebung 2
-- Description: Combinational circuit (Enable gate) described in different
-- forms
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity EnableGate is
port(
x : in std_ulogic_vector(3 downto 0);
en : in std_ulogic;
y : out std_ulogic_vector(3 downto 0)
);
end EnableGate;
-- concurrent signal assignment (naive)
architecture A_conc_sig_ass_1 of EnableGate is
begin
y(0) <= x(0) and en;
y(1) <= x(1) and en;
y(2) <= x(2) and en;
y(3) <= x(3) and en;
end architecture;
architecture A_conc_sig_ass_2 of EnableGate is
begin
y <= x and (others => en);
end architecture;
-- conditional signal assignment
architecture A_cond_sig_ass_1 of EnableGate is
begin
y <= x when en = '1' else (others => '0');
end architecture;
-- selected signal assignment
architecture A_sel_sig_ass_1 of EnableGate is
begin
with en select
y <= x when '1',
(others => '0') when others;
end architecture;
-- process statement with sequential signal ass. (naive)
architecture A_proc_seq_sig_ass_1 of EnableGate is
begin
process(x, en)
begin
y(0) <= x(0) and en;
y(1) <= x(1) and en;
y(2) <= x(2) and en;
y(3) <= x(3) and en;
end process;
end architecture;
| gpl-2.0 | f7a46f2bbab80eddda3dea9eadff2b3d | 0.528926 | 3.480088 | false | false | false | false |
freecores/hilbert_transformer | vhdl/analytic_filter_h_a2.vhd | 1 | 3,556 | -- Implementation of Filter H_a2(z)
-- using Complex Frequency sampling filer (FSF) as Hilbert transformer
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
package analytic_filter_h_a2_pkg is
component analytic_filter_h_a2
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a2_pkg;
package body analytic_filter_h_a2_pkg is
end analytic_filter_h_a2_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.fsf_comb_filter_pkg.all;
use work.fsf_pole_filter_pkg.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
use work.complex_fsf_filter_c_90_pkg.all;
use work.complex_fsf_filter_inv_c_m30_m150_pkg.all;
use work.resize_tools_pkg.all;
entity analytic_filter_h_a2 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end analytic_filter_h_a2;
architecture analytic_filter_h_a2_arch of analytic_filter_h_a2 is
--signal y : std_logic_vector (data_width-1 downto 0);
--signal x : std_logic_vector (data_width-1 downto 0);
signal data_i_res : std_logic_vector (data_width-1 downto 0);
signal t1 : std_logic_vector (data_width-1 downto 0);
signal c1_i : std_logic_vector (data_width-1 downto 0);
signal c1_q : std_logic_vector (data_width-1 downto 0);
signal t1_str : std_logic;
signal c1_str : std_logic;
begin
data_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(data_i),1)),data_width);
real_pole_filter_1 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => data_i_res,
data_str_i => data_str_i,
data_o => t1,
data_str_o => t1_str
);
complex_fsf_filter_c_90_1 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => t1,
data_q_i => (others => '0'),
data_str_i => t1_str,
data_i_o => c1_i,
data_q_o => c1_q,
data_str_o => c1_str
);
data_i_o <= c1_i;
data_q_o <= c1_q;
data_str_o <= c1_str;
end analytic_filter_h_a2_arch; | gpl-3.0 | efa0c8e7f898b50580ebb89dc0647f21 | 0.644826 | 2.733282 | false | false | false | false |
99yen/vhdl-snake | vga.vhd | 1 | 2,676 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VGA is
port (
CLK : in std_logic;
RST : in std_logic;
R_IN : in std_logic_vector(3 downto 0);
G_IN : in std_logic_vector(3 downto 0);
B_IN : in std_logic_vector(3 downto 0);
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(9 downto 0);
R_OUT : out std_logic_vector(3 downto 0);
G_OUT : out std_logic_vector(3 downto 0);
B_OUT : out std_logic_vector(3 downto 0);
BLANK_H : out std_logic;
BLANK_V : out std_logic;
HSYNC : out std_logic;
VSYNC : out std_logic
);
end VGA;
architecture RTL of VGA is
signal HSYNC_CNT : std_logic_vector(9 downto 0);
signal VSYNC_CNT : std_logic_vector(9 downto 0);
signal NEXT_HSYNC_CNT : std_logic_vector(9 downto 0);
signal NEXT_VSYNC_CNT : std_logic_vector(9 downto 0);
signal BLANK_H_BUF : std_logic;
signal BLANK_V_BUF : std_logic;
signal HSYNC_CARRY : std_logic;
begin
-- VISIBLE 1 UNVISIBLE 0
-- BLANKING AREA H
BLANK_H_BUF <= '0' when (NEXT_HSYNC_CNT < 160) else '1';
BLANK_H <= BLANK_H_BUF;
-- BLANKING AERA V
BLANK_V_BUF <= '0' when (NEXT_VSYNC_CNT < 36 or NEXT_VSYNC_CNT >= 516) else '1';
BLANK_V <= BLANK_V_BUF;
-- DISPLAYING X, Y
X <= (NEXT_HSYNC_CNT - 160) when (BLANK_H_BUF = '1') else (others => '0');
Y <= (NEXT_VSYNC_CNT - 36) when (BLANK_V_BUF = '1') else (others => '0');
-- HSYNC COUNTER 800
HSYNC_CARRY <= '1' when HSYNC_CNT = 799 else '0';
NEXT_HSYNC_CNT <= (others => '0') when HSYNC_CNT = 799 else HSYNC_CNT + 1;
process(CLK, RST) begin
if (RST = '0') then
HSYNC_CNT <= (others => '0');
HSYNC <= '1';
elsif (CLK'event and CLK = '1') then
HSYNC_CNT <= NEXT_HSYNC_CNT;
-- REFRESH COLOR OUTPUT
if (BLANK_H_BUF = '1' and BLANK_H_BUF ='1') then
R_OUT <= R_IN;
G_OUT <= G_IN;
B_OUT <= B_IN;
else
R_OUT <= (others => '0');
G_OUT <= (others => '0');
B_OUT <= (others => '0');
end if;
-- HSYNC SIGNAL (NEGATIVE) and BLANKING AREA
if (NEXT_HSYNC_CNT = 16) then
HSYNC <= '0';
elsif (NEXT_HSYNC_CNT = 112) then
HSYNC <= '1';
end if;
end if;
end process;
-- VSYNC COUNTER 525
NEXT_VSYNC_CNT <= (others => '0') when VSYNC_CNT = 524 else VSYNC_CNT + 1;
process(CLK, RST) begin
if (RST = '0') then
VSYNC_CNT <= (others => '0');
VSYNC <= '0';
elsif (CLK'event and CLK = '1') then
if (HSYNC_CARRY = '1') then
VSYNC_CNT <= NEXT_VSYNC_CNT;
-- VSYNC SIGNAL (NEGATIVE) and BLANKING AREA
if (NEXT_VSYNC_CNT = 0) then
VSYNC <= '0';
elsif (NEXT_VSYNC_CNT = 2) then
VSYNC <= '1';
end if;
end if;
end if;
end process;
end RTL;
| gpl-2.0 | 8bc42cd5347ab578cbedab0956a10d27 | 0.593423 | 2.608187 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_serial_input/testbench/serializer.vhd | 1 | 1,450 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 13/05/2009
-- File : serializer.vhd
--
-- Abstract : this component simulate the behavior of sn65
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity serializer is
---------------------------------------------------------------------------
port
(
-- serial signals
clk : in std_logic ;
ce_n: in std_logic ;
ld_n: in std_logic ;
sop : out std_logic ;
sip : in std_logic ;
-- parallel input
input : in std_logic_vector( 7 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture serializer_1 of serializer is
---------------------------------------------------------------------------
signal int_register : std_logic_vector( 7 downto 0):= x"00";
begin
sop <= int_register(7);
latch : process (clk,ld_n,ce_n)
begin
if ld_n = '0' then
int_register <= input;
elsif ce_n = '0' and rising_edge(clk) then
int_register <= int_register(6 downto 0)&sip;
end if;
end process latch;
end architecture serializer_1;
| lgpl-2.1 | a45affa912c2ec9087caeb7d51a467ec | 0.422069 | 4.707792 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_dff_compedge_case.vhd | 1 | 916 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(D : out std_logic;
A : out std_logic;
sel : in std_logic_vector(2 downto 0);
clock : in std_logic;
enable2 : in std_logic;
enable : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if rising_edge(clock) and enable = '1' and not (enable2 = '0') then
case sel is
when "000" => D <= '0';
when "001" => D <= '1';
when "010" => D <= '0';
when "011" => D <= '1';
when "100" => A <= '0';
when "101" => D <= '1';
when "110" => D <= '1';
when "111" => D <= '0';
end case;
end if;
end process;
end behv;
| gpl-3.0 | 8eae183ae31f2cb9bd03d6da104c2fea | 0.489083 | 3.259786 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_main_design_icmp.vhd | 1 | 11,351 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design_icmp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--
-- 16:24:47.966461 IP (tos 0x0, ttl 128, id 15103, offset 0, flags [none],
-- proto: ICMP (1), length: 60) 192.168.146.22 > 192.168.144.5: ICMP echo request,
-- id 1, seq 38, length 40
-- 0x0000: 4500 003c 3aff 0000 8001 5c55 c0a8 9216 E..<:.....\U....
-- 0x0010: c0a8 9005 0800 4d35 0001 0026 6162 6364 ......M5...&abcd
-- 0x0020: 6566 6768 696a 6b6c 6d6e 6f70 7172 7374 efghijklmnopqrst
-- 0x0030: 7576 7761 6263 6465 6667 6869 uvwabcdefghi
--
-----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_main_design_icmp is
end tb_main_design_icmp;
architecture Behavioral of tb_main_design_icmp is
signal clk125Mhz : STD_LOGIC := '0';
signal clk125Mhz90 : STD_LOGIC := '0';
signal phy_ready : STD_LOGIC := '1';
signal status : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal input_empty : STD_LOGIC := '0';
signal input_read : STD_LOGIC := '0';
signal input_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal input_data_present : STD_LOGIC := '0';
signal input_data_error : STD_LOGIC := '0';
component main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
signal count : integer := 999;
signal count2 : integer := 180;
signal arp_src_hw : std_logic_vector(47 downto 0) := x"a0b3cc4cf9ef";
signal arp_src_ip : std_logic_vector(31 downto 0) := x"0A000001";
signal arp_tgt_hw : std_logic_vector(47 downto 0) := x"ab8967452302";
signal arp_tgt_ip : std_logic_vector(31 downto 0) := x"0A00000A";
begin
process
begin
clk125Mhz <= '1';
wait for 2 ns;
clk125Mhz90 <= '1';
wait for 2 ns;
clk125Mhz <= '0';
wait for 2 ns;
clk125Mhz90 <= '0';
wait for 2 ns;
end process;
i_main_design: main_design
generic map (
our_mac => arp_tgt_hw,
our_ip => arp_tgt_ip)
port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => status,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if count < 86 then
input_empty <= '0';
else
input_empty <= '1';
end if;
if count2 = 20000 then
count <= 0;
count2 <= 0;
else
count2 <= count2+1;
end if;
if input_read = '1' then
if count = 87 then
count <= 0;
else
count <= count + 1;
end if;
case count is
-----------------------------
-- Ethernet preamble
-----------------------------
when 0 => input_data <= x"55"; input_data_present <= '1';
when 1 => input_data <= x"55";
when 2 => input_data <= x"55";
when 3 => input_data <= x"55";
when 4 => input_data <= x"55";
when 5 => input_data <= x"55";
when 6 => input_data <= x"55";
when 7 => input_data <= x"D5";
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 8 => input_data <= arp_tgt_hw( 7 downto 0);
when 9 => input_data <= arp_tgt_hw(15 downto 8);
when 10 => input_data <= arp_tgt_hw(23 downto 16);
when 11 => input_data <= arp_tgt_hw(31 downto 24);
when 12 => input_data <= arp_tgt_hw(39 downto 32);
when 13 => input_data <= arp_tgt_hw(47 downto 40);
-- Source MAC address
when 14 => input_data <= arp_src_hw(47 downto 40);
when 15 => input_data <= arp_src_hw(39 downto 32);
when 16 => input_data <= arp_src_hw(31 downto 24);
when 17 => input_data <= arp_src_hw(23 downto 16);
when 18 => input_data <= arp_src_hw(15 downto 8);
when 19 => input_data <= arp_src_hw( 7 downto 0);
-- Ethernet frame tyoe
when 20 => input_data <= x"08"; -- Ether Type 08:00 - IP
when 21 => input_data <= x"00";
------------------------
-- IP Header
------------------------
when 22 => input_data <= x"45"; -- Protocol & Header Len
when 23 => input_data <= x"00";
when 24 => input_data <= x"00"; -- Length
when 25 => input_data <= x"3C";
when 26 => input_data <= x"5d"; -- Identificaiton
when 27 => input_data <= x"15";
when 28 => input_data <= x"00"; -- Flags and offset
when 29 => input_data <= x"00";
when 30 => input_data <= x"80"; -- TTL
when 31 => input_data <= x"01"; -- Protocol
when 32 => input_data <= x"b4"; -- Checksum
when 33 => input_data <= x"fd";
when 34 => input_data <= x"0A"; -- Source IP Address
when 35 => input_data <= x"00";
when 36 => input_data <= x"00";
when 37 => input_data <= x"01";
when 38 => input_data <= x"0A"; -- Destination IP address
when 39 => input_data <= x"00";
when 40 => input_data <= x"00";
when 41 => input_data <= x"0A";
-------------------------------------
-- ICMP Header
-------------------------------------
when 42 => input_data <= x"08"; -- ICMP Tyoe
when 43 => input_data <= x"00"; -- Code
when 44 => input_data <= x"fd"; -- Checksum
when 45 => input_data <= x"b1";
when 46 => input_data <= x"00"; -- Identifier
when 47 => input_data <= x"01";
when 48 => input_data <= x"05"; -- Sequence
when 49 => input_data <= x"6d";
-------------------------------------
-- ICMP Ping data
-------------------------------------
when 50 => input_data <= x"61";
when 51 => input_data <= x"62";
when 52 => input_data <= x"63";
when 53 => input_data <= x"64";
when 54 => input_data <= x"65";
when 55 => input_data <= x"66";
when 56 => input_data <= x"67";
when 57 => input_data <= x"68";
when 58 => input_data <= x"69";
when 59 => input_data <= x"6A";
when 60 => input_data <= x"6B";
when 61 => input_data <= x"6C";
when 62 => input_data <= x"6D";
when 63 => input_data <= x"6E";
when 64 => input_data <= x"6F";
when 65 => input_data <= x"70";
when 66 => input_data <= x"71";
when 67 => input_data <= x"72";
when 68 => input_data <= x"73";
when 69 => input_data <= x"74";
when 70 => input_data <= x"75";
when 71 => input_data <= x"76";
when 72 => input_data <= x"77";
when 73 => input_data <= x"61";
when 74 => input_data <= x"62";
when 75 => input_data <= x"63";
when 76 => input_data <= x"64";
when 77 => input_data <= x"65";
when 78 => input_data <= x"66";
when 79 => input_data <= x"67";
when 80 => input_data <= x"68";
when 81 => input_data <= x"FF";
when 82 => input_data <= x"FF";
when 83 => input_data <= x"FF";
when 84 => input_data <= x"FF";
-----------------------------------
-- END OF PACKET
-----------------------------------
when 85 => input_data <= x"DD"; input_data_present <= '0';
when others => input_data <= x"DD"; input_data_present <= '0';
end case;
count2 <= 0;
end if;
end if;
end process;
end Behavioral; | mit | a9148fcdc5f2d7b98be46b7eb826773c | 0.381112 | 4.182388 | false | false | false | false |
99yen/vhdl-snake | gengraphic.vhd | 1 | 1,595 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GENGRAPHIC is
port (
VGA_X, VGA_Y : in std_logic_vector(9 downto 0);
TITLE : in std_logic;
SCORE : in std_logic_vector(7 downto 0);
VISIBLE : in std_logic;
MAP_X, MAP_Y : out std_logic_vector(5 downto 0);
R_OUT, G_OUT, B_OUT : out std_logic_vector(3 downto 0)
);
end GENGRAPHIC;
architecture RTL of GENGRAPHIC is
component XY2MAP
port (
VGA_X, VGA_Y : in std_logic_vector(9 downto 0);
GRID_X, GRID_Y : out std_logic_vector(5 downto 0);
BOX_X, BOX_Y : out std_logic_vector(3 downto 0)
);
end component;
signal BOX_X, BOX_Y : std_logic_vector(3 downto 0);
signal GRID_X, GRID_Y : std_logic_vector(5 downto 0);
signal R_ENABLE, G_ENABLE, B_ENABLE, BOX_ENABLE : std_logic;
signal FRAME : std_logic;
begin
U1: XY2MAP port map(VGA_X => VGA_X, VGA_Y => VGA_Y, GRID_X => GRID_X, GRID_Y => GRID_Y, BOX_X => BOX_X, BOX_Y => BOX_Y);
-- outer frame
FRAME <= '1' when (VGA_Y = 30 or VGA_Y = 448 or VGA_X = 110 or VGA_X = 528) else '0';
-- box
MAP_X <= GRID_X - 7;
MAP_Y <= GRID_Y - 2;
BOX_ENABLE <= '0' when (BOX_X = "1111" or BOX_Y = "1111") else '1';
R_ENABLE <= '1' when ((BOX_ENABLE = '1' and VISIBLE = '1') or FRAME = '1') else '0';
G_ENABLE <= '1' when ((BOX_ENABLE = '1' and VISIBLE = '1') or FRAME = '1') else '0';
B_ENABLE <= '1' when ((BOX_ENABLE = '1' and VISIBLE = '1') or FRAME = '1') else '0';
R_OUT <= "1111" when R_ENABLE = '1' else "0000";
G_OUT <= "1111" when G_ENABLE = '1' else "0000";
B_OUT <= "1111" when B_ENABLE = '1' else "0000";
end RTL;
| gpl-2.0 | 51179cae047455e3e75028f458ca9f98 | 0.609404 | 2.420334 | false | false | false | false |
wifidar/wifidar_fpga | src/uart_minibuf.vhd | 2 | 2,698 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity uart_minibuf is
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
data_in: in std_logic_vector (sample_length_bits -1 downto 0);
data_out: out std_logic_vector(7 downto 0);
index_data_in: out std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
sample_buffer_full: in std_logic;
uart_send_data: out std_logic;
uart_ready: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end uart_minibuf;
architecture behavioral of uart_minibuf is
type uart_minibuf_state is (reset,waiting,upper_half,upper_half_hold,lower_half,lower_half_hold);
signal curr_state: uart_minibuf_state;
signal curr_index: integer range 0 to (2**10)-1 := 0;
signal uart_ready_prev: std_logic := '0';
signal buffer_full_prev: std_logic := '0';
signal end_buff: std_logic := '0';
begin
process(clk,rst)
begin
if(rst = '1') then
curr_state <= reset;
elsif(rising_edge(clk)) then
uart_ready_prev <= uart_ready;
buffer_full_prev <= sample_buffer_full;
if((buffer_full_prev = '1') and (sample_buffer_full = '0')) then
end_buff <= '1';
end if;
case curr_state is
when reset =>
curr_state <= waiting;
when waiting =>
data_out <= (others => '0');
curr_index <= 0;
uart_send_data <= '0';
if(sample_buffer_full = '1') then
curr_state <= upper_half;
end if;
when upper_half =>
if(curr_index = 0) then
data_out <= "1" & data_in(13 downto 7);
else
data_out <= "0" & data_in(13 downto 7);
end if;
if(uart_ready = '1') then
uart_send_data <= '1';
curr_state <= upper_half_hold;
end if;
when upper_half_hold =>
if(uart_ready = '0') then
uart_send_data <= '0';
end if;
if(uart_ready = '1' and uart_ready_prev = '0') then
curr_state <= lower_half;
end if;
when lower_half =>
curr_index <= curr_index + 1;
data_out <= "0" & data_in(6 downto 0);
if(uart_ready = '1') then
uart_send_data <= '1';
curr_state <= lower_half_hold;
end if;
when lower_half_hold =>
if(uart_ready = '0') then
uart_send_data <= '0';
end if;
if(uart_ready = '1' and uart_ready_prev = '0') then
curr_state <= upper_half;
end if;
if(end_buff = '1') then
end_buff <= '0';
curr_state <= waiting;
end if;
end case;
end if;
end process;
index_data_in <= std_logic_vector(to_unsigned(curr_index,integer(ceil(log(real(num_samples))/log(real(2)))) + 1));
end behavioral;
| mit | 5b05fca791bfe707596cef1f10a98e50 | 0.599333 | 2.792961 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/arp/arp_handler.vhd | 1 | 13,243 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: arp_handler - Behavioral
--
-- Description: Processing for ARP packets.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
------------- From the RFC ---------------------------------------
-- 1: ?Do I have the hardware type in ar$hrd?
-- 2: Yes: (almost definitely)
-- 3: [optionally check the hardware length ar$hln]
-- 4: ?Do I speak the protocol in ar$pro?
-- 5: Yes:
-- 6: [optionally check the protocol length ar$pln]
-- 7: Merge_flag := false
-- 8: If the pair <protocol type, sender protocol address> is
-- 9: already in my translation table, update the sender
--10: hardware address field of the entry with the new
--11: information in the packet and set Merge_flag to true.
--12: ?Am I the target protocol address?
--13: Yes:
--14: If Merge_flag is false, add the triplet <protocol type,
--15: sender protocol address, sender hardware address> to
--16: the translation table.
--17: ?Is the opcode ares_op$REQUEST? (NOW look at the opcode!!)
--18: Yes:
--20: Swap hardware and protocol fields, putting the local
--21: hardware and protocol addresses in the sender fields.
--22: Set the ar$op field to ares_op$REPLY
--23: Send the packet to the (new) target hardware address on
--24: the same hardware on which the request was received.
-------------------------------------------------------------------
-- Lines 1 - 6 : Has already been checked in the RX_ARP module.
-- Lines 7 & 11: Any ARP packet that comes through will update the 256-entry table,
-- always forcing Merge_flag to be true.
-- Line 12 : Need to compare against my IP address - if match then
-- Lines 14-16 : Can be ignored as Merge Flag is true
-- Lines 17 : The op_request field can be used as the CE for the outbound FIFO
-- Lines 20-24 : Requires the our MAC address to place in the etherent and ARP header
-- To send an ARP reply we need to queue the following:
-- ce <= (op_request)
-- dest eth MAC <= src eth MAC
-- src eth MAC <= our eth MAC
-- src hw address <= our eth MAC
-- src prot address <= our IP address
-- op <= REPLY
-- target hw address <= src hw address
-- target prot address <= src prot address
--
-- To start ARP discovery we need to queue the following:
-- ce <= '1'
-- dest eth MAC <= FF:FF:FF:FF:FF:FF
-- src eth MAC <= our eth MAC
-- src hw address <= our eth MAC
-- src prot address <= our IP address
-- op <= REQUEST
-- target hw address <= Desired IP Address
-- target prot address <= 00:00:00:00:00:00
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic;
packet_out_data : out std_logic_vector(7 downto 0);
-- For the wider design to send any ARP on the wire
queue_request : in std_logic;
queue_request_ip : in std_logic_vector(31 downto 0);
-- to enable IP->MAC lookup for outbound packets
update_valid : out std_logic := '0';
update_ip : out std_logic_vector(31 downto 0) := (others => '0');
update_mac : out std_logic_vector(47 downto 0) := (others => '0'));
end arp_handler;
architecture Behavioral of arp_handler is
component rx_arp is
Port ( clk : in STD_LOGIC;
packet_data_valid : in STD_LOGIC;
packet_data : in STD_LOGIC_VECTOR (7 downto 0);
arp_de : out STD_LOGIC;
arp_op_request : out STD_LOGIC;
arp_sender_hw : out STD_LOGIC_VECTOR(47 downto 0);
arp_sender_ip : out STD_LOGIC_VECTOR(31 downto 0);
arp_target_hw : out STD_LOGIC_VECTOR(47 downto 0);
arp_target_ip : out STD_LOGIC_VECTOR(31 downto 0));
end component;
signal arp_tx_write : std_logic := '0';
signal arp_tx_full : std_logic := '0';
signal arp_tx_op_request : std_logic := '0';
signal arp_tx_src_hw : std_logic_vector(47 downto 0) := our_mac;
signal arp_tx_src_ip : std_logic_vector(31 downto 0) := our_ip;
signal arp_tx_tgt_hw : std_logic_vector(47 downto 0) := (others => '0');
signal arp_tx_tgt_ip : std_logic_vector(31 downto 0) := our_ip;
signal arp_in_write : STD_LOGIC := '0';
signal arp_in_full : STD_LOGIC := '0';
signal arp_in_op_request : STD_LOGIC := '0';
signal arp_in_src_hw : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
signal arp_in_src_ip : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal arp_in_tgt_hw : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
signal arp_in_tgt_ip : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
component arp_tx_fifo
Port ( clk : in STD_LOGIC;
arp_in_write : in STD_LOGIC;
arp_in_full : out STD_LOGIC;
arp_in_op_request : in STD_LOGIC;
arp_in_tgt_hw : in STD_LOGIC_VECTOR(47 downto 0);
arp_in_tgt_ip : in STD_LOGIC_VECTOR(31 downto 0);
arp_out_empty : out std_logic;
arp_out_read : in std_logic := '0';
arp_out_op_request : out std_logic;
arp_out_tgt_hw : out std_logic_vector(47 downto 0);
arp_out_tgt_ip : out std_logic_vector(31 downto 0));
end component;
signal arp_out_empty : std_logic;
signal arp_out_read : std_logic := '0';
signal arp_out_op_request : std_logic;
signal arp_out_src_hw : std_logic_vector(47 downto 0);
signal arp_out_src_ip : std_logic_vector(31 downto 0);
signal arp_out_tgt_hw : std_logic_vector(47 downto 0);
signal arp_out_tgt_ip : std_logic_vector(31 downto 0);
component arp_send_packet
Port ( clk : in STD_LOGIC;
-- Interface to the outgoing ARP queue
arp_fifo_empty : in std_logic;
arp_fifo_read : out std_logic := '0';
arp_op_request : in std_logic;
arp_src_hw : in std_logic_vector(47 downto 0);
arp_src_ip : in std_logic_vector(31 downto 0);
arp_tgt_hw : in std_logic_vector(47 downto 0);
arp_tgt_ip : in std_logic_vector(31 downto 0);
-- Interface into the Ethernet TX subsystem
packet_request : out std_logic := '0';
packet_granted : in std_logic := '0';
packet_valid : out std_logic;
packet_data : out std_logic_vector(7 downto 0));
end component;
signal hold_request : std_logic := '0';
signal hold_request_ip : std_logic_vector(31 downto 0) := (others => '0');
begin
i_rx_arp: rx_arp Port map (
clk => clk,
packet_data_valid => packet_in_valid,
packet_data => packet_in_data,
arp_de => arp_in_write,
arp_op_request => arp_in_op_request,
arp_sender_hw => arp_in_src_hw,
arp_sender_ip => arp_in_src_ip,
arp_target_hw => arp_in_tgt_hw,
arp_target_ip => arp_in_tgt_ip);
process(clk)
begin
if rising_edge(clk) then
if arp_in_write = '0' or ((arp_in_src_ip and our_netmask) /= (our_ip and our_netmask))then
-- If there is no write , or it is not for our IP subnet then ignore it
-- and queue any request for a new ARP broadcast
update_valid <= '0';
arp_tx_write <= '0';
if queue_request = '1' then
arp_tx_write <= '1';
arp_tx_op_request <= '1';
arp_tx_src_hw <= our_mac;
arp_tx_src_ip <= our_ip;
arp_tx_tgt_hw <= (others => '0');
arp_tx_tgt_ip <= queue_request_ip;
elsif hold_request = '1' then
-- if a request was delayed, then write it.
arp_tx_write <= '1';
arp_tx_op_request <= '1';
arp_tx_src_hw <= our_mac;
arp_tx_src_ip <= our_ip;
arp_tx_tgt_hw <= (others => '0');
arp_tx_tgt_ip <= hold_request_ip;
hold_request <= '0';
end if;
else
-- It is a write for our subnet, so update the ARP resolver table.
update_valid <= '1';
update_ip <= arp_in_src_ip;
update_mac <= arp_in_src_hw;
if arp_in_op_request = '1' and arp_in_tgt_ip = our_ip and arp_tx_full = '0' then
-- And if it is a request for our MAC, then send it
-- by queuing the outbound reply
arp_tx_write <= '1';
arp_tx_op_request <= '0';
arp_tx_src_hw <= our_mac;
arp_tx_src_ip <= our_ip;
arp_tx_tgt_hw <= arp_in_src_hw;
arp_tx_tgt_ip <= arp_in_src_ip;
-- If the request to send an ARP packet gets gazumped by a request
-- from the wire, then hold onto it to and send it next.
hold_request <= queue_request;
hold_request_ip <= queue_request_ip;
end if;
end if;
end if;
end process;
i_arp_tx_fifo: arp_tx_fifo Port map (
clk => clk,
arp_in_write => arp_tx_write,
arp_in_full => arp_tx_full,
arp_in_op_request => arp_tx_op_request,
arp_in_tgt_hw => arp_tx_tgt_hw,
arp_in_tgt_ip => arp_tx_tgt_ip,
arp_out_empty => arp_out_empty,
arp_out_read => arp_out_read,
arp_out_op_request => arp_out_op_request,
arp_out_tgt_hw => arp_out_tgt_hw,
arp_out_tgt_ip => arp_out_tgt_ip);
i_arp_send_packet: arp_send_packet port map (
clk => clk,
arp_fifo_empty => arp_out_empty,
arp_fifo_read => arp_out_read,
arp_op_request => arp_out_op_request,
arp_src_hw => our_mac,
arp_src_ip => our_ip,
arp_tgt_hw => arp_out_tgt_hw,
arp_tgt_ip => arp_out_tgt_ip,
packet_request => packet_out_request,
packet_granted => packet_out_granted,
packet_data => packet_out_data,
packet_valid => packet_out_valid);
end Behavioral;
| mit | c10cf4a3de62268cb1034162ba19bccd | 0.516575 | 3.763285 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/simplegpio/hdl/simplegpio.vhd | 1 | 2,878 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 03/09/2008
-- File : simplegpio.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity simplegpio is
---------------------------------------------------------------------------
generic(
id : natural := 3; -- identify id
size : natural := 16 -- wishbone data size 8,16 or 32
);
port
(
-- clock and reset
clk_i : in std_logic ; -- master clock input
rst_i : in std_logic ; -- asynchronous reset
-- wishbone
adr_i : in std_logic_vector( 1 downto 0);
dat_i : in std_logic_vector( size-1 downto 0);
dat_o : out std_logic_vector( size-1 downto 0);
we_i : in std_logic ;
stb_i : in std_logic ;
ack_o : out std_logic ;
cyc_i : in std_logic;
-- gpio
gpio : inout std_logic_vector( size-1 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture simplegpio_1 of simplegpio is
---------------------------------------------------------------------------
signal write_register : std_logic_vector( size-1 downto 0);
signal ctrl_register : std_logic_vector( size-1 downto 0);
signal rd_ack : std_logic ;
signal wr_ack : std_logic ;
begin
-- register reading process
process(clk_i, rst_i)
begin
if(rst_i = '1') then
dat_o <= (others => '0');
rd_ack <= '0';
elsif(rising_edge(clk_i)) then
rd_ack <= '0';
if(stb_i = '1' and we_i = '0' and cyc_i = '1') then
rd_ack <= '1';
if(adr_i = "00") then
dat_o <= gpio;
elsif(adr_i = "01") then
dat_o <= ctrl_register;
elsif(adr_i = "10") then
dat_o <= std_logic_vector(to_unsigned(id,size));
else
dat_o <= (others => '0');
end if;
end if;
end if;
end process;
-- register write process
process(clk_i,rst_i)
begin
if(rst_i = '1') then
ctrl_register <= (others => '0');
write_register <= (others => '0');
wr_ack <= '0';
elsif(rising_edge(clk_i)) then
wr_ack <= '0';
if(stb_i = '1' and we_i = '1' and cyc_i = '1') then
wr_ack <= '1';
if(adr_i = "00") then
write_register <= dat_i;
elsif(adr_i = "01") then
ctrl_register <= dat_i;
end if;
end if;
end if;
end process;
-- acknowledge
ack_o <= rd_ack or wr_ack;
-- gpio write
gpiogen : for i in 0 to (size-1) generate
gpio(i) <= write_register(i) when ctrl_register(i) = '1' else 'Z';
end generate;
end architecture simplegpio_1;
| lgpl-2.1 | 53a6b437e3db7f5454a070f1fa0ea93c | 0.470118 | 3.509756 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/button/hdl/button.vhd | 1 | 2,473 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 10/03/2008
-- File : button.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity button is
---------------------------------------------------------------------------
generic(
id : natural := 2
);
port
(
-- global signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_add : in std_logic ;
wbs_readdata : out std_logic_vector( 15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- irq
irq : out std_logic ;
-- fpga input
button : in std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture button_1 of button is
---------------------------------------------------------------------------
signal button_r : std_logic ;
signal reg : std_logic_vector( 15 downto 0);
begin
-- connect button
cbutton : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg <= (others => '0');
elsif rising_edge(gls_clk) then
reg <= "000000000000000"&button;
end if;
end process cbutton;
-- rise interruption
pbutton : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
irq <= '0';
button_r <= '0';
elsif rising_edge(gls_clk) then
if button_r /= button then
irq <= '1';
else
irq <= '0';
end if;
button_r <= button;
end if;
end process pbutton;
-- register reading process
pread : process(gls_clk,gls_reset)
begin
if(gls_reset = '1') then
wbs_ack <= '0';
wbs_readdata <= (others => '0');
elsif(rising_edge(gls_clk)) then
wbs_ack <= '0';
if(wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1')then
wbs_ack <= '1';
if wbs_add = '0' then
wbs_readdata <= std_logic_vector(to_unsigned(id,16));
else
wbs_readdata <= reg;
end if;
else
wbs_readdata <= (others => '0');
end if;
end if;
end process pread;
end architecture button_1;
| lgpl-2.1 | e9702bc7aaf53dcb25a67106b1bb0fd2 | 0.464618 | 3.599709 | false | false | false | false |
freecores/hilbert_transformer | vhdl/complex_fsf_filter_inv_c_m30_m150.vhd | 1 | 4,446 | -- This is the implementation of the complex filter C^{-1}_{-30/-150}(z) = (1 + j z^{-1} - z^{-2})
-- which creates zeros at e^-j30 [deg] and e^-j150 [deg]
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package complex_fsf_filter_inv_c_m30_m150_pkg is
component complex_fsf_filter_inv_c_m30_m150
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i_i : in std_logic_vector(data_width-1 downto 0);
data_q_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end complex_fsf_filter_inv_c_m30_m150_pkg;
package body complex_fsf_filter_inv_c_m30_m150_pkg is
end complex_fsf_filter_inv_c_m30_m150_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.resize_tools_pkg.all;
entity complex_fsf_filter_inv_c_m30_m150 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i_i : in std_logic_vector(data_width-1 downto 0);
data_q_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end complex_fsf_filter_inv_c_m30_m150;
architecture complex_fsf_filter_inv_c_m30_m150_arch of complex_fsf_filter_inv_c_m30_m150 is
signal xi : std_logic_vector(data_width-1 downto 0);
signal xq : std_logic_vector(data_width-1 downto 0);
signal yi : std_logic_vector(data_width-1 downto 0);
signal yq : std_logic_vector(data_width-1 downto 0);
signal xid : std_logic_vector(data_width-1 downto 0);
signal xidd : std_logic_vector(data_width-1 downto 0);
signal xqd : std_logic_vector(data_width-1 downto 0);
signal xqdd : std_logic_vector(data_width-1 downto 0);
signal xisxidd : std_logic_vector(data_width-1 downto 0);
signal xqsxqdd : std_logic_vector(data_width-1 downto 0);
signal ti : std_logic_vector(data_width-1 downto 0);
signal tq : std_logic_vector(data_width-1 downto 0);
signal tid : std_logic_vector(data_width-1 downto 0);
signal tqd : std_logic_vector(data_width-1 downto 0);
signal tidsxqdd : std_logic_vector(data_width-1 downto 0);
signal tqdaxidd : std_logic_vector(data_width-1 downto 0);
begin
xi <= data_i_i;
xq <= data_q_i;
data_i_o <= yi;
data_q_o <= yq;
xisxidd <= resize_to_msb_round(std_logic_vector(signed(xi) - signed(xidd)),data_width);
xqsxqdd <= resize_to_msb_round(std_logic_vector(signed(xq) - signed(xqdd)),data_width);
ti <= xisxidd;
tq <= xqsxqdd;
tidsxqdd <= resize_to_msb_round(std_logic_vector(signed(tid) - signed(xqdd)),data_width);
tqdaxidd <= resize_to_msb_round(std_logic_vector(signed(tqd) + signed(xidd)),data_width);
process (clk_i, rst_i)
begin
if rst_i = '1' then
xid <= (others => '0');
xidd <= (others => '0');
xqd <= (others => '0');
xqdd <= (others => '0');
tid <= (others => '0');
tqd <= (others => '0');
yi <= (others => '0');
yq <= (others => '0');
data_str_o <= '0';
elsif clk_i'EVENT and clk_i = '1' then
data_str_o <= data_str_i;
if data_str_i='1' then
xid <= xi;
xidd <= xid;
xqd <= xq;
xqdd <= xqd;
tid <= ti;
tqd <= tq;
yi <= tidsxqdd;
yq <= tqdaxidd;
end if;
end if;
end process;
end complex_fsf_filter_inv_c_m30_m150_arch;
| gpl-3.0 | 36a3406a683b2a2a12b596f913323273 | 0.647548 | 2.78921 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles_graphs/synthesisShowcase/caseStmt.vhd | 2 | 609 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity caseT is
port(A : out std_logic;
baz : in std_logic_vector(2 downto 0));
end caseT;
architecture behv of caseT is
begin
process(A) is
begin
case baz is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => A <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
| gpl-3.0 | 08d5b54e353a7d88b1ea125863d1571b | 0.486043 | 3.045 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tx/tx_interface.vhd | 1 | 8,508 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tx_interface - Behavioral
--
-- Description: To send data streams out to an Ethernet PHY over RGMII
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tx_interface is
Port ( clk125MHz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
--
phy_ready : in STD_LOGIC;
link_10mb : in STD_LOGIC;
link_100mb : in STD_LOGIC;
link_1000mb : in STD_LOGIC;
---
arp_request : in STD_LOGIC;
arp_granted : out STD_LOGIC;
arp_valid : in STD_LOGIC;
arp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
icmp_request : in STD_LOGIC;
icmp_granted : out STD_LOGIC;
icmp_valid : in STD_LOGIC;
icmp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
udp_request : in STD_LOGIC;
udp_granted : out STD_LOGIC;
udp_valid : in STD_LOGIC;
udp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
tcp_request : in STD_LOGIC;
tcp_granted : out STD_LOGIC;
tcp_valid : in STD_LOGIC;
tcp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
eth_txck : out STD_LOGIC;
eth_txctl : out STD_LOGIC;
eth_txd : out STD_LOGIC_VECTOR (3 downto 0));
end tx_interface;
architecture Behavioral of tx_interface is
component tx_arbiter is
generic (
idle_time : std_logic_vector(5 downto 0));
Port ( clk : in STD_LOGIC;
ready : in STD_LOGIC;
ch0_request : in STD_LOGIC;
ch0_granted : out STD_LOGIC;
ch0_valid : in STD_LOGIC;
ch0_data : in STD_LOGIC_VECTOR (7 downto 0);
ch1_request : in STD_LOGIC;
ch1_granted : out STD_LOGIC;
ch1_valid : in STD_LOGIC;
ch1_data : in STD_LOGIC_VECTOR (7 downto 0);
ch2_request : in STD_LOGIC;
ch2_granted : out STD_LOGIC;
ch2_valid : in STD_LOGIC;
ch2_data : in STD_LOGIC_VECTOR (7 downto 0);
ch3_request : in STD_LOGIC;
ch3_granted : out STD_LOGIC;
ch3_valid : in STD_LOGIC;
ch3_data : in STD_LOGIC_VECTOR (7 downto 0);
merged_data_valid : out STD_LOGIC;
merged_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component tx_add_crc32 is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC := '0';
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end component;
component tx_add_preamble is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end component;
signal merged_data_valid : STD_LOGIC;
signal merged_data : STD_LOGIC_VECTOR (7 downto 0);
signal with_crc_data_valid : STD_LOGIC;
signal with_crc_data : STD_LOGIC_VECTOR (7 downto 0);
signal framed_data_valid : STD_LOGIC;
signal framed_data : STD_LOGIC_VECTOR (7 downto 0);
signal data : STD_LOGIC_VECTOR (7 downto 0);
signal data_valid : STD_LOGIC;
signal data_enable : STD_LOGIC;
signal data_error : STD_LOGIC;
component tx_rgmii is
Port ( clk : in STD_LOGIC;
clk90 : in STD_LOGIC;
phy_ready : in STD_LOGIC;
data_valid : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_error : in STD_LOGIC;
data_enable : in STD_LOGIC := '1';
eth_txck : out STD_LOGIC;
eth_txctl : out STD_LOGIC;
eth_txd : out STD_LOGIC_VECTOR (3 downto 0));
end component ;
begin
i_tx_arbiter: tx_arbiter generic map(idle_time => "010111") Port map (
clk => clk125MHz,
------------------------------
ready => phy_ready,
ch0_request => tcp_request,
ch0_granted => tcp_granted,
ch0_data => tcp_data,
ch0_valid => tcp_valid,
ch1_request => arp_request,
ch1_granted => arp_granted,
ch1_data => arp_data,
ch1_valid => arp_valid,
ch2_request => icmp_request,
ch2_granted => icmp_granted,
ch2_data => icmp_data,
ch2_valid => icmp_valid,
ch3_request => udp_request,
ch3_granted => udp_granted,
ch3_data => udp_data,
ch3_valid => udp_valid,
merged_data_valid => merged_data_valid,
merged_data => merged_data);
--i_ila_0: ila_0 port map (
-- clk => clk125Mhz,
-- probe0(0) => merged_data_valid,
-- probe1(0) => merged_data_valid,
-- probe2 => merged_data,
-- probe3(0) => merged_data_valid);
i_tx_add_crc32: tx_add_crc32 port map (
clk => clk125MHz,
data_valid_in => merged_data_valid,
data_in => merged_data,
data_valid_out => with_crc_data_valid,
data_out => with_crc_data);
i_tx_add_preamble: tx_add_preamble port map (
clk => clk125MHz,
data_valid_in => with_crc_data_valid,
data_in => with_crc_data,
data_valid_out => framed_data_valid,
data_out => framed_data);
----------------------------------------------------------------------
-- A FIFO needs to go here to slow down data for the 10/100 operation.
--
-- Plan is for a 4K FIFO, with an almost full at about 2500. That will
-- Allow space for a full packet and at least 50 cycles for latency
-- within the feedback loop.
----------------------------------------------------------------------
-- A module need to go here to adapt the output of the FIFO to the
-- slowere speeds
--
-- link_10mb : in STD_LOGIC;
-- link_100mb : in STD_LOGIC;
-- link_1000mb : in STD_LOGIC;
----------------------------------------------------------------------
i_tx_rgmii: tx_rgmii port map (
clk => clk125MHz,
clk90 => clk125MHz90,
phy_ready => phy_ready,
data_valid => framed_data_valid,
data => framed_data,
data_error => '0',
data_enable => '1',
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
end Behavioral;
| mit | c4de106ad87617ed2a85c1e70c65c316 | 0.515867 | 3.803308 | false | false | false | false |
S0obi/SY23 | clock_divider/clock_divider.vhdl | 1 | 711 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider is
GENERIC (
N: positive := 60
);
Port ( clk : in STD_LOGIC;
tc : out STD_LOGIC);
end divider;
architecture divider_architecture of divider is
signal cpt : STD_LOGIC_VECTOR (3 downto 0);
begin
count: process(clk)
begin
if rising_edge(clk) then
if cpt < N -1 then
cpt <= cpt + 1;
else
cpt <= (others => '0');
end if;
end if;
end process count;
remainder: process(cpt)
begin
if cpt = N-1 then
tc <= '1';
else
tc <= '0';
end if;
end process remainder;
end divider_architecture;
| gpl-2.0 | 61f24ed05cfb56e90c2d0fdff2c5729c | 0.590717 | 3.369668 | false | false | false | false |
xcthulhu/periphondemand | src/library/wrappers/imx51_wb16_wrapper/hdl/imx51_wb16_wrapper.vhd | 1 | 3,196 | -------------------------------------------------------------------------------
--
-- File : imx51_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabien Marteau <[email protected]>
-- Project : i.MX51 wrapper to Wishbone bus
--
-- Creation Date : 17/12/2010
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity imx51_wb16_wrapper is
---------------------------------------------------------------------------
port
(
-- i.MX Signals
imx_da : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_rw : in std_logic ;
imx_adv : in std_logic ;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
---------------------------------------------------------------------------
Architecture RTL of imx51_wb16_wrapper is
---------------------------------------------------------------------------
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(15 downto 0);
begin
-- ----------------------------------------------------------------------------
-- External signals synchronization process
-- ----------------------------------------------------------------------------
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
write <= '0';
read <= '0';
strobe <= '0';
writedata <= (others => '0');
address <= (others => '0');
elsif(rising_edge(gls_clk)) then
strobe <= not (imx_cs_n);
write <= (not (imx_cs_n)) or (not(imx_rw));
read <= (not (imx_cs_n)) and imx_rw;
if (imx_adv = '0') then
address <= imx_da;
else
writedata <= imx_da;
end if;
end if;
end process;
wbm_address <= address when (strobe = '1') else (others => '0');
wbm_writedata <= writedata when (write = '1') else (others => '0');
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
imx_da <= wbm_readdata when ((read = '1') and (strobe = '1')) else (others => 'Z');
end architecture RTL;
| lgpl-2.1 | 3f423f90396f719887a25ce746c81157 | 0.422403 | 4.330623 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_candidate_01.vhd | 1 | 3,624 | -- this vhdl source resembles following verilog code
-- module ripplemod(a, b, cin, sum, cout);
-- input [7:0] a;
-- input [7:0] b;
-- input cin;
-- output [7:0]sum;
-- output cout;
-- wire[6:0] c;
--
-- fulladd a1(a[0],b[0],cin,sum[0],c[0]);
-- fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
-- fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
-- fulladd a4(a[3],b[3],c[2],sum[3],c[3]);
-- fulladd a5(a[4],b[4],c[3],sum[4],c[4]);
-- fulladd a6(a[5],b[5],c[4],sum[5],c[5]);
-- fulladd a7(a[6],b[6],c[5],sum[6],c[6]);
-- fulladd a8(a[7],b[7],c[6],sum[7],cout);
-- endmodule
--
-- module fulladd(a, b, cin, sum, cout);
-- input a; input b; input cin;
-- output sum; output cout;
--
-- assign sum=(a^b^cin);
-- assign cout=((a&b)|(b&cin)|(a&cin));
-- endmodule
--
-- which expands to:
--
-- sum(0) <= a(0) xor b(0) xor cin
-- c(0) <= (a(0) and b(0)) or (b(0) and cin) or (a(0) and cin);
--
-- sum(1) <= a(1) xor b(1) xor c(0)
-- c(1) <= (a(1) and b(1)) or (b(1) and c(0)) or (a(1) and c(0));
--
-- sum(2) <= a(2) xor b(2) xor c(1)
-- c(2) <= (a(2) and b(2)) or (b(2) and c(1)) or (a(2) and c(1));
--
-- sum(3) <= a(3) xor b(3) xor c(2)
-- c(3) <= (a(3) and b(3)) or (b(3) and c(2)) or (a(3) and c(2));
--
-- sum(4) <= a(4) xor b(4) xor c(3)
-- c(4) <= (a(4) and b(4)) or (b(4) and c(3)) or (a(4) and c(3));
--
-- sum(5) <= a(5) xor b(5) xor c(4)
-- c(5) <= (a(5) and b(5)) or (b(5) and c(4)) or (a(5) and c(4));
--
-- sum(6) <= a(6) xor b(6) xor c(5)
-- c(6) <= (a(6) and b(6)) or (b(6) and c(5)) or (a(6) and c(5));
--
-- sum(7) <= a(7) xor b(7) xor c(6)
-- cout <= (a(7) and b(7)) or (b(7) and c(6)) or (a(7) and c(6));
----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector(7 downto 0));
end adder;
architecture behv of adder is
signal wire : std_logic_vector(8 downto 0);
begin
wire(0) <= cin;
cout <= wire(8);
rippleCarry : for pos in 0 to 7 generate
sum(pos) <= a(pos) xor b(pos) xor wire(pos);
wire(pos + 1) <=
(a(pos) and b(pos)) or
(b(pos) and wire(pos)) or
(a(pos) and wire(pos));
end generate rippleCarry;
end behv;
----
-- for n = 1 this expands to:
----------------
-- library ieee;
-- use ieee.std_logic_1164.all;
-- use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--
-- entity adder is
-- port(A : in std_logic_vector(1 downto 0);
-- B : in std_logic_vector(1 downto 0);
-- cin : in std_logic;
-- cout : out std_logic;
-- sum : out std_logic_vector(1 downto 0));
-- end adder;
--
-- architecture behv of adder is
-- signal wire : std_logic_vector(2 downto 0);
-- begin
-- wire(0) <= cin;
-- cout <= wire(2);
--
-- rippleCarry : for pos in 0 to 1 generate
-- sum(pos) <= a(pos) xor b(pos) xor wire(pos);
-- wire(pos + 1) <=
-- (a(pos) and b(pos)) or
-- (b(pos) and wire(pos)) or
-- (a(pos) and wire(pos));
-- end generate rippleCarry;
--
-- -- which in turn expands to:
-- sum(0) <= a(0) xor b(0) xor wire(0);
-- wire(1) <= (a(0) and b(0)) or
-- (b(0) and wire(0)) or
-- (a(0) and wire(0));
--
-- sum(1) <= a(1) xor b(1) xor wire(1);
-- wire(2) <= (a(1) and b(1)) or
-- (b(1) and wire(1)) or
-- (a(1) and wire(1));
--
-- end behv;
----
| gpl-3.0 | 550bd119353a4a1219e73fd27e0a610e | 0.49117 | 2.312699 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/terasic_de0nano/clock/top.vhdl | 1 | 793 | --
-- Clock on de0nano
--
-- There is one clock source on de0nano board:
-- * On-board 50MHz clock oscillator.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of Top is
signal rst, led : std_logic;
begin
rst <= not(rst_n_i);
blink_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk_i, rst_i => rst, blink_o => led);
leds_o <= led & not(led) & led & not(led) & led & not(led) & led & not(led);
end architecture RTL;
| bsd-3-clause | f4bc4af82cc73a0d1ac1270a7b8ffe6f | 0.624212 | 2.958955 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx3/wrapper.vhdl | 1 | 3,637 | --
-- Wrapper of gtx2 example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
clk_i : in std_logic;
rst_i : in std_logic;
clk_o : out std_logic;
--
rxp_i : in std_logic;
rxn_i : in std_logic;
txp_o : out std_logic;
txn_o : out std_logic;
--
loopback_i: in std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
rx_isk_o : out std_logic_vector(3 downto 0);
tx_data_i : in std_logic_vector(31 downto 0);
tx_isk_i : in std_logic_vector(3 downto 0);
ready_o : out std_logic
);
end entity Wrapper;
architecture Structural of Wrapper is
signal refclk : std_logic_vector(1 downto 0);
signal outclk : std_logic;
signal rx_plllkdet : std_logic;
signal usrclk, usrclk2 : std_logic;
signal rx_ready, tx_ready : std_logic;
signal loopback : std_logic_vector(2 downto 0);
signal reset, locked : std_logic;
begin
reset <= not rx_plllkdet;
mmcm_gtx_i: entity work.mmcm150and75
port map (
CLK_IN1 => outclk,
CLK_OUT1 => usrclk,
CLK_OUT2 => usrclk2,
RESET => reset,
LOCKED => locked
);
refclk <= '0' & clk_i;
loopback <= '0' & loopback_i & '0';
gtx_v6_i : entity work.gbt3_gtx
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
GTX_TX_CLK_SOURCE => "RXPLL",
GTX_POWER_SAVE => "0000110100"
)
port map (
LOOPBACK_IN => loopback, -- Near-End PMA Loopback
-- RX 8b10b Decoder
RXCHARISK_OUT => rx_isk_o,
RXDISPERR_OUT => open,
RXNOTINTABLE_OUT => open,
-- RX Comma Detection and Alignment
RXBYTEISALIGNED_OUT => open,
RXENMCOMMAALIGN_IN => '1',
RXENPCOMMAALIGN_IN => '1',
-- RX Data Path interface
RXDATA_OUT => rx_data_o,
RXUSRCLK_IN => usrclk,
RXUSRCLK2_IN => usrclk2,
-- RX Driver
RXN_IN => rxn_i,
RXP_IN => rxp_i,
-- RX PLL Ports
GTXRXRESET_IN => rst_i,
MGTREFCLKRX_IN => refclk,
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rx_plllkdet,
RXRESETDONE_OUT => rx_ready,
-- TX 8b10b Encoder Control Ports
TXCHARISK_IN => tx_isk_i,
-- TX Data Path interface
TXDATA_IN => tx_data_i,
TXOUTCLK_OUT => outclk,
TXUSRCLK_IN => usrclk,
TXUSRCLK2_IN => usrclk2,
-- TX Driver
TXN_OUT => txn_o,
TXP_OUT => txp_o,
TXPOSTEMPHASIS_IN => "00000",
TXPREEMPHASIS_IN => "0000",
-- TX PLL Ports
GTXTXRESET_IN => rst_i,
MGTREFCLKTX_IN => refclk,
PLLTXRESET_IN => '0',
TXPLLLKDET_OUT => open,
TXRESETDONE_OUT => tx_ready
);
clk_o <= usrclk2;
ready_o <= rx_ready and tx_ready and rx_plllkdet and locked;
end architecture Structural;
| bsd-3-clause | ea82b634ccdea27848a3e48f44722dff | 0.469893 | 3.987939 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_output/testbench/apf27_test_pkg.vhd | 1 | 5,221 | ----------------------------------------------
-- Design Name : Test bench utils for apf27
-- File Name : apf27_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <[email protected]>
-- Version : 1.00
---------------------------------------------
-----------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package apf27_test_pkg is
-- write procedures
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
);
-- read procedures
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
);
end package apf27_test_pkg;
package body apf27_test_pkg is
-- Write value from imx
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Write value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_eb3_n <= '0';
wait until falling_edge(gls_clk);
wait for 2500 ps;
imx_data <= value;
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk); -- WSC = 2
end loop;
end if;
wait for 1 ns;
imx_cs_n <= '1';
imx_eb3_n <= '1';
imx_address <= (others => 'Z');
imx_data <= (others => 'Z');
end procedure imx_write;
-- Read a value from imx
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Read value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_oe_n <= '0';
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk);
end loop;
end if;
wait until falling_edge(gls_clk);
value <= imx_data;
imx_cs_n <= '1';
imx_oe_n <= '1';
imx_address <= (others => 'Z');
wait for 20 ns;
end procedure imx_read;
end package body apf27_test_pkg;
| lgpl-2.1 | e4934143690a8df03c55c485d0997dac | 0.558705 | 3.625694 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_rx_packet.vhd | 1 | 9,304 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_rx_packet - Behavioral
--
-- Description: For receiving UDP packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity udp_rx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0'));
end udp_rx_packet;
architecture Behavioral of udp_rx_packet is
component ethernet_extract_header
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
filter_ether_type : in STD_LOGIC_VECTOR (15 downto 0);
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_dst_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal ether_extracted_data_valid : STD_LOGIC := '0';
signal ether_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ether_is_ipv4 : STD_LOGIC := '0';
signal ether_src_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
component ip_extract_header
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
filter_protocol : in STD_LOGIC_VECTOR (7 downto 0);
ip_version : out STD_LOGIC_VECTOR (3 downto 0);
ip_type_of_service : out STD_LOGIC_VECTOR (7 downto 0);
ip_length : out STD_LOGIC_VECTOR (15 downto 0);
ip_identification : out STD_LOGIC_VECTOR (15 downto 0);
ip_flags : out STD_LOGIC_VECTOR (2 downto 0);
ip_fragment_offset : out STD_LOGIC_VECTOR (12 downto 0);
ip_ttl : out STD_LOGIC_VECTOR (7 downto 0);
ip_checksum : out STD_LOGIC_VECTOR (15 downto 0);
ip_src_ip : out STD_LOGIC_VECTOR (31 downto 0);
ip_dest_ip : out STD_LOGIC_VECTOR (31 downto 0);
ip_dest_broadcast : out STD_LOGIC);
end component;
signal ip_extracted_data_valid : STD_LOGIC := '0';
signal ip_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_version : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal ip_type_of_service : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_flags : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal ip_ttl : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal ip_dest_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal ip_dest_broadcast : STD_LOGIC := '0';
component udp_extract_udp_header
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
udp_src_port : out STD_LOGIC_VECTOR (15 downto 0);
udp_dst_port : out STD_LOGIC_VECTOR (15 downto 0);
udp_length : out STD_LOGIC_VECTOR (15 downto 0);
udp_checksum : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal udp_extracted_data_valid : STD_LOGIC := '0';
signal udp_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal udp_checksum : STD_LOGIC_VECTOR (15 downto 0);
signal udp_src_port : STD_LOGIC_VECTOR (15 downto 0);
signal udp_dst_port : STD_LOGIC_VECTOR (15 downto 0);
signal udp_length : STD_LOGIC_VECTOR (15 downto 0);
begin
i_ethernet_extract_header: ethernet_extract_header generic map (
our_mac => our_mac)
port map (
clk => clk,
data_valid_in => packet_in_valid,
data_in => packet_in_data,
data_valid_out => ether_extracted_data_valid,
data_out => ether_extracted_data,
filter_ether_type => x"0800",
ether_dst_mac => open,
ether_src_mac => ether_src_mac);
i_ip_extract_header: ip_extract_header generic map (
our_ip => our_ip,
our_broadcast => our_broadcast)
port map (
clk => clk,
data_valid_in => ether_extracted_data_valid,
data_in => ether_extracted_data,
data_valid_out => ip_extracted_data_valid,
data_out => ip_extracted_data,
filter_protocol => x"11",
ip_version => ip_version,
ip_type_of_service => ip_type_of_service,
ip_length => ip_length,
ip_identification => ip_identification,
ip_flags => ip_flags,
ip_fragment_offset => ip_fragment_offset,
ip_ttl => ip_ttl,
ip_checksum => ip_checksum,
ip_src_ip => ip_src_ip,
ip_dest_ip => ip_dest_ip,
ip_dest_broadcast => ip_dest_broadcast);
i_udp_extract_udp_header : udp_extract_udp_header port map (
clk => clk,
data_valid_in => ip_extracted_data_valid,
data_in => ip_extracted_data,
data_valid_out => udp_extracted_data_valid,
data_out => udp_extracted_data,
udp_src_port => udp_src_port,
udp_dst_port => udp_dst_port,
udp_length => udp_length,
udp_checksum => udp_checksum);
----------------------------------------------
-- Pass the received data stream to the
-- rest of the FPGA desig.
----------------------------------------------
udp_rx_valid <= udp_extracted_data_valid;
udp_rx_data <= udp_extracted_data;
udp_rx_src_ip <= ip_src_ip;
udp_rx_src_port <= udp_src_port;
udp_rx_dst_broadcast <= ip_dest_broadcast;
udp_rx_dst_port <= udp_dst_port;
end Behavioral;
| mit | e222f39639eea1b6c06a8f5eb53c9627 | 0.537081 | 3.769854 | false | false | false | false |
wifidar/wifidar_fpga | src/dac_serial.vhd | 1 | 5,005 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end dac_serial;
architecture Behavioral of dac_serial is
signal current_bit: integer range 0 to 16 := 0;
signal ready_flag_sig: std_logic := '0';
signal spi_clk_delay: std_logic := '0';
signal dac_cs_delay: std_logic := '0';
begin
process(clk)
begin
if(rising_edge(clk)) then
if(send_data = '1') and (ready_flag_sig = '1') then
ready_flag_sig <= '0';
dac_cs_delay <= '0';
DAC_CS <= dac_cs_delay;
elsif ready_flag_sig = '0' then
if(spi_clk_delay = '1') then
spi_clk_delay <= '0';
else
spi_clk_delay <= '1';
current_bit <= current_bit + 1;
case current_bit is
-- don't cares
when 1 => SPI_MOSI_1 <= '0';
when 2 => SPI_MOSI_1 <= '0';
-- command
when 3 => SPI_MOSI_1 <= '0';
when 4 => SPI_MOSI_1 <= '0';
-- data
when 5 => SPI_MOSI_1 <= data_in_1(11);
when 6 => SPI_MOSI_1 <= data_in_1(10);
when 7 => SPI_MOSI_1 <= data_in_1(9);
when 8 => SPI_MOSI_1 <= data_in_1(8);
when 9 => SPI_MOSI_1 <= data_in_1(7);
when 10 => SPI_MOSI_1 <= data_in_1(6);
when 11 => SPI_MOSI_1 <= data_in_1(5);
when 12 => SPI_MOSI_1 <= data_in_1(4);
when 13 => SPI_MOSI_1 <= data_in_1(3);
when 14 => SPI_MOSI_1 <= data_in_1(2);
when 15 => SPI_MOSI_1 <= data_in_1(1);
when 16 => SPI_MOSI_1 <= data_in_1(0);
DAC_CS <= '1';
ready_flag_sig <= '1';
-- other
when others => SPI_MOSI_1 <= '0'; -- used for don't cares
end case;
end if;
else
DAC_CS <= '1';
current_bit <= 0;
spi_clk_delay <= '1';
end if;
--DAC_CS <= dac_cs_delay;
SPI_SCK <= not spi_clk_delay;
ready_flag <= ready_flag_sig;
end if;
end process;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
--
--entity dac_serial is
-- port (
-- dac_clk: out std_logic;
-- dac_sync: out std_logic;
-- dac_data: out std_logic;
-- data_in: in std_logic_vector(11 downto 0);
-- ready: out std_logic;
-- send: in std_logic;
-- clk: in std_logic
-- );
--end dac_serial;
--
--architecture behavioral of dac_serial is
--
-- current_bit: unsigned(3 downto 0);
-- divide_counter: unsigned(3 downto 0);
-- sending: std_logic;
-- data_en: std_logic;
-- send_en: std_logic;
--
--begin
-- clk_divide:process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(divide_counter = to_unsigned(5,4)) then
-- divide_counter <= divide_counter + '1';
-- send_en <= '1';
-- elsif(divide_counter = to_unsigned(10,4)) then
-- divide_counter <= (others => '0');
-- data_en <= '1';
-- send_en <= '1';
-- else
-- divide_counter <= divide_counter + '1';
-- data_en <= '0';
-- send_en <= '0';
-- end if;
-- end if;
-- end process;
--
-- serial_clk: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(sending = '1') then
--
-- end process;
--
-- serial_data: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(send = '1') and (sending = '0') then
-- sending <= '1';
-- sending <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- elsif(data_en = '1') then
-- if(sending = '1') then
-- current_bit <= current_bit + '1';
-- dac_sync <= '0';
-- case current_bit is
-- when "0000" =>
-- dac_data <= '0'; -- don't care
-- when "0001" =>
-- dac_data <= '0'; -- don't care
-- when "0010" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0011" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0100" =>
-- dac_data <= data_in(11);
-- when "0101" =>
-- dac_data <= data_in(10);
-- when "0110" =>
-- dac_data <= data_in(9);
-- when "0111" =>
-- dac_data <= data_in(8);
-- when "1000" =>
-- dac_data <= data_in(7);
-- when "1001" =>
-- dac_data <= data_in(6);
-- when "1010" =>
-- dac_data <= data_in(5);
-- when "1011" =>
-- dac_data <= data_in(4);
-- when "1100" =>
-- dac_data <= data_in(3);
-- when "1101" =>
-- dac_data <= data_in(2);
-- when "1110" =>
-- dac_data <= data_in(1);
-- when "1111" =>
-- dac_data <= data_in(0);
-- when others =>
-- dac_data <= '0';
-- end case;
-- else
-- dac_sync <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
--
--end behavioral;
| mit | c4ab0cbea803af4a3b7b7210f96b5c7f | 0.515684 | 2.571942 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/ciaa_acc/clock/top.vhdl | 1 | 1,008 | --
-- GPIOs on Zybo (only PL)
--
-- Author(s):
-- * Rodrigo A. Melo
-- * Bruno Valinoti
--
-- Copyright (c) 2019 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
sysclk_p_i : in std_logic;
sysclk_n_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
signal clk : std_logic;
signal led0, led1, led2, led3 : std_logic;
begin
blink200MHz_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk, rst_i => '0', blink_o => led0);
ibufgds_inst : IBUFGDS
generic map (DIFF_TERM => TRUE, IOSTANDARD => "LVDS")
port map (I => sysclk_p_i, IB => sysclk_n_i, O => clk);
led1 <= '1';
led2 <= led0;
led3 <= '0';
leds_o <= led3 & led2 & led1 & led0;
end architecture RTL;
| bsd-3-clause | b4a12e12ea83138bdb73641c3397b1a9 | 0.610119 | 2.982249 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/avnet_s6micro/clock/top.vhdl | 1 | 1,700 | --
-- Clocks on s5micro
--
-- There are four clock sources on s6micro board:
-- * 3 are user programmable. Default values:
-- * 1 Optional user installable of 66 MHz (not installed)
-- They are used to blink user leds.
-- The clock of 40 MHz (programmable) is used to blink LEDs 0.
-- The clock of 66.7 MHz (programmable) is used to blink LEDs 1.
-- The clock of 100 MHz (programmable) is used to blink LEDs 2.
-- The clock of 66.7 MHz (Fixed) is used to blink LEDs 3.
-- CPU_RESET push-button is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk2_i : in std_logic;
clk3_i : in std_logic;
clk4_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
signal led0, led1, led2, led3 : std_logic;
begin
blink40prog_inst: Blink
generic map (FREQUENCY => 40e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led0);
blink66prog_inst: Blink
generic map (FREQUENCY => 66700e3)
port map(clk_i => clk2_i, rst_i => rst_i, blink_o => led1);
blink100prog_inst: Blink
generic map (FREQUENCY => 100e6)
port map(clk_i => clk3_i, rst_i => rst_i, blink_o => led2);
blink66fixed_inst: Blink
generic map (FREQUENCY => 66700e3)
port map(clk_i => clk4_i, rst_i => rst_i, blink_o => led3);
leds_o <= led3 & led2 & led1 & led0;
end architecture RTL;
| bsd-3-clause | b71f7e5d5493dfe07d17f6b4398dfaa6 | 0.651176 | 3.00885 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_output/testbench/bascule_d.vhd | 1 | 1,931 | --
-- Copyright (c) ARMadeus Project 2009
--
--
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : bascule_d.vhd
-- Created on : 05/06/2009
-- Author : Fabien Marteau <[email protected]>
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity bascule_d is
---------------------------------------------------------------------------
port
(
d : in std_logic ;
clk : in std_logic ;
r : in std_logic ;
q : out std_logic;
q_n : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture bascule_d_1 of bascule_d is
---------------------------------------------------------------------------
signal q_s : std_logic ;
begin
process (clk)
begin
if rising_edge(clk) then
if r = '1' then
q_s <= '0';
else
q_s <= d;
end if;
end if;
end process;
q <= q_s;
q_n <= not q_s;
end architecture bascule_d_1;
| lgpl-2.1 | c9bbbdd876dea1730fb7d0997ec1193d | 0.485759 | 4.565012 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/generate02.vhd | 1 | 1,532 | library ieee;
use ieee.std_logic_1164.all;
entity driver is
port(x: in std_logic;
F: out std_logic);
end Driver;
architecture behav of driver is
begin
mygen: for I in 2 downto 1 generate
mygen_nested: for J in I downto 1 generate
my_if : if (I /= J) generate
myproc: process(x) is
variable foo : integer := J;
variable bar : integer := I;
begin
if (x='1') then
F <= '1';
else
F <= '0';
end if;
end process myproc;
end generate my_if;
end generate mygen_nested;
end generate mygen;
end behav;
--
-- elaboration von mygen
--
mygen : block
constant i : integer := 2;
begin
mygen_nested : block
constant j : integer := 2;
begin
-- fällt weg wegen (2 /= 2) = false
end mygen_nested;
mygen_nested : block
constant j : integer := 1;
begin
my_if : block
begin
myproc : process(x) is
variable foo : integer := 1;
variable bar : integer := 2;
begin
if (x = '1') then
f <= '1';
else
f <= '0';
end if;
end process myproc;
end block my_if;
end mygen_nested;
end mygen;
mygen : block
constant i : integer := 1;
begin
mygen_nested : block
constant j : integer := 1;
begin
-- fällt weg wegen (1 /= 1) = false
end block mygen_nested;
end block mygen;
| gpl-3.0 | f00790ad91a7f3d87a183ec3be5a6423 | 0.506536 | 3.933162 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_case_simple.vhd | 1 | 806 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
baz : out std_logic_vector(7 downto 0);
sum : out std_logic);
end adder;
architecture behv of adder is
begin
process(A) is
begin
baz <= "00101100";
case "100" is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
| gpl-3.0 | 426189ea87cdc4ffffd4eef099e5ae25 | 0.476427 | 3.211155 | false | false | false | false |
qu1x/fsio | src/lib/fsio_put.vhd | 1 | 1,412 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
library fsio;
use fsio.fsio.all;
entity fsio_put is
generic (
cap: integer := CAP;
len: integer := LEN
);
port (
clk: in std_logic;
hsi: in std_logic;
hso: out std_logic;
fsi: in std_logic_vector(cap - 1 downto 0);
fso: out std_logic_vector(cap - 1 downto 0);
dat: in std_logic_vector(len - 1 downto 0);
req: out std_logic;
ack: in std_logic
);
end fsio_put;
architecture behavioral of fsio_put is
begin
fso(len - 1 downto 0) <= dat;
req <= hso xor hsi;
ctl: process(clk)
begin
if rising_edge(clk) then
if fso = fsi then
hso <= hso xor (req and ack);
end if;
end if;
end process ctl;
end behavioral;
| agpl-3.0 | 7a22764caa3e916b4095d73d9f785526 | 0.695467 | 3.151786 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/i2cocore/testbench/top_i2ctest_tb.vhd | 1 | 7,973 | ---------------------------------------------------------------------------
-- Company : Automaticaly generated by POD
-- Author(s) :
--
-- Creation Date : 2008-10-20
-- File : Top_i2ctest_tb.vhd
--
-- Abstract :
-- insert a description here
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
--
-- Defines communication functions between imx and fpga:
--
-- write procedures
-- procedure imx_write
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
--
-- read procedures
-- procedure imx_read
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
--
use work.apf_test_pkg.all;
entity top_i2ctest_tb is
end entity top_i2ctest_tb;
architecture RTL of top_i2ctest_tb is
CONSTANT HALF_PERIODE : time := 5.20833333333 ns; -- Half clock period
CONSTANT IRQ_MNGR00_IRQ_MNGR_MASK : std_logic_vector := x"0000";
CONSTANT IRQ_MNGR00_IRQ_MNGR_PENDING_ACK : std_logic_vector := x"0002";
CONSTANT IRQ_MNGR00_ID : std_logic_vector := x"0004";
CONSTANT I2C_PRESCLO : std_logic_vector := x"0020";
CONSTANT I2C_PRESCHI : std_logic_vector := x"0022";
CONSTANT I2C_CTR : std_logic_vector := x"0024";
CONSTANT I2C_CR : std_logic_vector := x"0028";
CONSTANT I2C_TXR : std_logic_vector := x"002a";
CONSTANT I2C_SR : std_logic_vector := x"002c";
CONSTANT I2C_RXR : std_logic_vector := x"002e";
CONSTANT I2C_ID : std_logic_vector := x"0030";
-- Values
CONSTANT PRELo : std_logic_vector := x"00BF";
CONSTANT PREHi : std_logic_vector := x"0000";
-- read/write (accelerometer)
CONSTANT ADDR : std_logic_vector := x"001D"; -- lis3lv02dl
CONSTANT SUBADDR : std_logic_vector := x"0016"; -- OFFSET_X
CONSTANT VALUE : std_logic_vector := x"00BB";
--/* irq position in irqmngr */
CONSTANT IRQ : std_logic_vector := x"0001";
--/* CTR register */
CONSTANT I2C_EN : std_logic_vector := x"0080";
CONSTANT I2C_IEN : std_logic_vector := x"0040";
--/* CR register */
CONSTANT I2C_STA : std_logic_vector := x"0080";
CONSTANT I2C_STO : std_logic_vector := x"0040";
CONSTANT I2C_RD : std_logic_vector := x"0020";
CONSTANT I2C_WR : std_logic_vector := x"0010";
CONSTANT I2C_ACK : std_logic_vector := x"0008";
CONSTANT I2C_IACK : std_logic_vector := x"0001";
--/* read/write bit */
CONSTANT I2C_ADD_READ : std_logic := '1';
CONSTANT I2C_ADD_WRITE : std_logic := '0';
-- i2c
signal i2c_scl : std_logic;
signal i2c_sda : std_logic;
-- imx9328
signal imx9328_wb16_wrapper00_imx_address : std_logic_vector(11 downto 0);
signal imx9328_wb16_wrapper00_imx_cs_n : std_logic;
signal imx9328_wb16_wrapper00_imx_data : std_logic_vector(15 downto 0);
signal imx9328_wb16_wrapper00_imx_eb3_n : std_logic;
signal imx9328_wb16_wrapper00_imx_oe_n : std_logic;
-- irq
signal irq_mngr00_gls_irq : std_logic;
-- rstgen
signal rstgen_syscon00_ext_clk : std_logic;
component top_i2ctest
port (
-- i2c
i2c_scl : inout std_logic;
i2c_sda : inout std_logic;
-- imx9328
imx9328_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
imx9328_wb16_wrapper00_imx_cs_n : in std_logic;
imx9328_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
imx9328_wb16_wrapper00_imx_eb3_n : in std_logic;
imx9328_wb16_wrapper00_imx_oe_n : in std_logic;
-- irq
irq_mngr00_gls_irq : out std_logic;
-- rstgen
rstgen_syscon00_ext_clk : in std_logic
);
end component top_i2ctest;
begin
top : top_i2ctest
port map(
i2c_scl => i2c_scl,
i2c_sda => i2c_sda,
imx9328_wb16_wrapper00_imx_address => imx9328_wb16_wrapper00_imx_address,
imx9328_wb16_wrapper00_imx_cs_n => imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_data => imx9328_wb16_wrapper00_imx_data,
imx9328_wb16_wrapper00_imx_eb3_n => imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_oe_n => imx9328_wb16_wrapper00_imx_oe_n,
irq_mngr00_gls_irq => irq_mngr00_gls_irq,
rstgen_syscon00_ext_clk => rstgen_syscon00_ext_clk
);
pullup_p : process
begin
i2c_sda <= 'H';
i2c_scl <= 'H';
end process pullup_p;
stimulis : process
begin
imx9328_wb16_wrapper00_imx_address <= (others => '0');
imx9328_wb16_wrapper00_imx_cs_n <= '1';
imx9328_wb16_wrapper00_imx_data <= (others => 'Z');
imx9328_wb16_wrapper00_imx_eb3_n <= '1';
imx9328_wb16_wrapper00_imx_oe_n <= '1';
-- unmask interrupt for i2c in interrupt manager
imx_write(IRQ_MNGR00_IRQ_MNGR_MASK,IRQ,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* set prescale */
imx_write(I2C_PRESCLO,PRELo,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
imx_write(I2C_PRESCHI,PREHi,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* set core enable and interrupt enable*/
imx_write(I2C_CTR,(I2C_EN or I2C_IEN),
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* write slave adresse on TXR */
imx_write(I2C_TXR,ADDR(14 downto 0)&I2C_ADD_READ,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* and CTR register*/
imx_write(I2C_CTR,(I2C_STA or I2C_WR or I2C_IACK),
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
wait for 10 us;
assert false report "End of test" severity error;
end process stimulis;
clockp : process
begin
rstgen_syscon00_ext_clk <= '1';
wait for HALF_PERIODE;
rstgen_syscon00_ext_clk <= '0';
wait for HALF_PERIODE;
end process clockp;
end architecture RTL;
| lgpl-2.1 | 390040b29a46380cf20db9d724709fbb | 0.576822 | 3.158875 | false | false | false | false |
S0obi/SY23 | counter/counter.vhdl | 1 | 699 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
GENERIC (
Nbits: integer := 4;
Nmax: integer := 9
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture counter_architecture of counter is
signal cpt : STD_LOGIC_VECTOR (3 downto 0);
signal enable : STD_LOGIC;
begin
Q <= cpt;
count: process(clk)
begin
if rising_edge(clk) then
if reset='1' then
cpt <= (others => '0');
elsif enable = '1' then
cpt <= cpt + 1;
end if;
end if;
end process count;
end counter_architecture;
| gpl-2.0 | aeba1dddc74672c1c162a026280c1a51 | 0.615165 | 3.29717 | false | false | false | false |
freecores/hilbert_transformer | vhdl/fsf_comb_filter.vhd | 1 | 2,825 | -- comb filter implementation for frequency sampling filers (FSF)
-- The filter transfer function F(z)=1+z^(-comb_delay)
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package fsf_comb_filter_pkg is
component fsf_comb_filter
generic(
data_width : integer;
comb_delay : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end fsf_comb_filter_pkg;
package body fsf_comb_filter_pkg is
end fsf_comb_filter_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
entity fsf_comb_filter is
generic(
data_width : integer := 16;
comb_delay : integer := 2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end fsf_comb_filter;
architecture fsf_comb_filter_arch of fsf_comb_filter is
signal xc : std_logic_vector (data_width-1 downto 0);
signal yc : std_logic_vector (data_width-1 downto 0);
type delay_array_type is array (0 to comb_delay-1) of std_logic_vector (data_width-1 downto 0);
signal ycd : delay_array_type;
begin
xc <= data_i;
yc <= conv_std_logic_vector(conv_integer(xc) - conv_integer(ycd(comb_delay-1)), data_width);
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to comb_delay-1 loop
ycd(i) <= (others => '0');
end loop;
data_str_o <= '0';
data_o <= (others => '0');
elsif clk_i'EVENT and clk_i = '1' then
data_str_o <= data_str_i;
data_o <= yc;
if data_str_i='1' then
ycd(0) <= xc;
for i in 1 to comb_delay-1 loop
ycd(i) <= ycd(i-1);
end loop;
end if;
end if;
end process;
end fsf_comb_filter_arch;
| gpl-3.0 | b2fc24d5f3dbc474ff48a5cf2c83eef6 | 0.656637 | 2.933541 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp/tcp_extract_header.vhd | 1 | 8,045 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_extract_header - Behavioral
--
-- Description: Extract the TCP header fields
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_extract_header is
port(
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0) := (others => '0');
data_valid_in : in std_logic := '0';
data_out : out std_logic_vector(7 downto 0) := (others => '0');
data_valid_out : out std_logic := '0';
tcp_hdr_valid : out std_logic := '0';
tcp_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_flag_urg : out std_logic := '0';
tcp_flag_ack : out std_logic := '0';
tcp_flag_psh : out std_logic := '0';
tcp_flag_rst : out std_logic := '0';
tcp_flag_syn : out std_logic := '0';
tcp_flag_fin : out std_logic := '0';
tcp_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end tcp_extract_header;
architecture Behavioral of tcp_extract_header is
signal i_tcp_hdr_valid : std_logic := '0';
signal i_tcp_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal i_tcp_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal i_tcp_window : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_flag_urg : std_logic := '0';
signal i_tcp_flag_ack : std_logic := '0';
signal i_tcp_flag_psh : std_logic := '0';
signal i_tcp_flag_rst : std_logic := '0';
signal i_tcp_flag_syn : std_logic := '0';
signal i_tcp_flag_fin : std_logic := '0';
signal i_tcp_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal byte_hdr_len : unsigned(10 downto 0) := (others => '0');
signal data_count : unsigned(10 downto 0) := (others => '0');
signal count : unsigned( 4 downto 0) := (others => '0');
begin
tcp_hdr_valid <= i_tcp_hdr_valid;
tcp_src_port <= i_tcp_src_port;
tcp_dst_port <= i_tcp_dst_port;
tcp_seq_num <= i_tcp_seq_num;
tcp_ack_num <= i_tcp_ack_num;
tcp_window <= i_tcp_window;
tcp_flag_urg <= i_tcp_flag_urg;
tcp_flag_ack <= i_tcp_flag_ack;
tcp_flag_psh <= i_tcp_flag_psh;
tcp_flag_rst <= i_tcp_flag_rst;
tcp_flag_syn <= i_tcp_flag_syn;
tcp_flag_fin <= i_tcp_flag_fin;
tcp_checksum <= i_tcp_checksum;
tcp_urgent_ptr <= i_tcp_urgent_ptr;
process(clk)
begin
if rising_edge(clk) then
data_valid_out <= '0';
data_out <= (others => '0');
i_tcp_hdr_valid <= '0';
if data_valid_in = '1' then
case count is
when "00000" => i_tcp_src_port(15 downto 8) <= data_in;
when "00001" => i_tcp_src_port( 7 downto 0) <= data_in;
when "00010" => i_tcp_dst_port(15 downto 8) <= data_in;
when "00011" => i_tcp_dst_port( 7 downto 0) <= data_in;
when "00100" => i_tcp_seq_num(31 downto 24) <= data_in;
when "00101" => i_tcp_seq_num(23 downto 16) <= data_in;
when "00110" => i_tcp_seq_num(15 downto 8) <= data_in;
when "00111" => i_tcp_seq_num( 7 downto 0) <= data_in;
when "01000" => i_tcp_ack_num(31 downto 24) <= data_in;
when "01001" => i_tcp_ack_num(23 downto 16) <= data_in;
when "01010" => i_tcp_ack_num(15 downto 8) <= data_in;
when "01011" => i_tcp_ack_num( 7 downto 0) <= data_in;
when "01100" => byte_hdr_len(5 downto 2) <= unsigned(data_in( 7 downto 4));
when "01101" => i_tcp_flag_urg <= data_in(5);
i_tcp_flag_ack <= data_in(4);
i_tcp_flag_psh <= data_in(3);
i_tcp_flag_rst <= data_in(2);
i_tcp_flag_syn <= data_in(1);
i_tcp_flag_fin <= data_in(0);
when "01110" => i_tcp_window(15 downto 8) <= data_in;
when "01111" => i_tcp_window( 7 downto 0) <= data_in;
when "10000" => i_tcp_checksum(15 downto 8) <= data_in;
when "10001" => i_tcp_checksum( 7 downto 0) <= data_in;
when "10010" => i_tcp_urgent_ptr(15 downto 8) <= data_in;
when "10011" => i_tcp_urgent_ptr( 7 downto 0) <= data_in;
when others => if data_count = byte_hdr_len then
data_valid_out <= data_valid_in;
data_out <= data_in;
i_tcp_hdr_valid <= '1';
elsif data_count > byte_hdr_len then
data_valid_out <= data_valid_in;
data_out <= data_in;
i_tcp_hdr_valid <= '0';
end if;
end case;
if count /= "11111" then
count <= count+1;
end if;
data_count <= data_count + 1;
else
-- For when TCP packets have no data
if data_count = byte_hdr_len and byte_hdr_len /= 0 then
i_tcp_hdr_valid <= '1';
end if;
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
data_count <= (others => '0');
end if;
end if;
end process;
end Behavioral; | mit | 5d1c7b27309f604aaf52381c9e0d491a | 0.496706 | 3.620612 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles_graphs/synthesisShowcase/clusterfuck.vhd | 2 | 1,021 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clufu is
port(A : out std_logic;
B : out std_logic;
Co : out std_logic;
sel : in std_logic_vector(1 downto 0);
enable : in std_logic;
enable2 : in std_logic;
clock : in std_logic);
end clufu;
architecture b of clufu is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if A = B then
if not A then
if rising_edge(clock) then
case sel is
when "00" =>
if rising_edge(clock) and enable = '1' and (not enable2 = '0') then
Co <= '0';
end if;
when "01" => Co <= '1';
when "10" => Co <= '1';
when "11" => Co <= '1';
end case;
end if;
end if;
end if;
end process;
end b;
| gpl-3.0 | 4a666128aebb6a4e4f2f8dedf400dcdd | 0.463271 | 3.59507 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/FIR.vhd | 1 | 3,417 | ---------------------------------------------------------------
-- FIR Digital Filter Design (DSP example)
-- tested by Weijun Zhang, 04/2001
--
-- VHDL Data-Flow modeling
-- KEYWORD:
-- generate, array, range, constant and subtype
---------------------------------------------------------------
library IEEE; -- declare the library
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
---------------------------------------------------------------
entity FIR_filter is
port(rst : in std_logic;
clk : in std_logic;
coef_ld : in std_logic;
start : in std_logic;
o_enable : in std_logic;
bypass : in std_logic;
Xn_in : in std_logic_vector(3 downto 0);
Yn_in : in std_logic_vector(15 downto 0);
Xn_out : out std_logic_vector(3 downto 0);
Yn_out : out std_logic_vector(15 downto 0));
end FIR_filter;
architecture BEH of FIR_filter is
constant K : integer := 4; -- circuit has four stages
-- use type and subtype to define the complex signals
subtype bit4 is std_logic_vector(3 downto 0);
subtype bit8 is std_logic_vector(7 downto 0);
subtype bit16 is std_logic_vector(15 downto 0);
type klx4 is array (K downto 0) of bit4;
type kx8 is array (K-1 downto 0) of bit8;
type klx8 is array (K downto 0) of bit8;
type kx16 is array (K-1 downto 0) of bit16;
type klx16 is array (K downto 0) of bit16;
-- define signal in type of arrays
signal REG1, REG2, COEF : klx4;
signal MULT8 : kx8;
signal MULT16 : kx16;
signal SUM : klx16;
signal Xn_tmp : bit4;
signal Yn_tmp : bit16;
begin
-- initialize the first stage of FIR circuit
REG2(K) <= Xn_in when (start = '1')
else (REG2(K)'range => '0');
REG1(K) <= (REG1(K)'range => '0');
SUM(K) <= Yn_in;
COEF(K) <= Xn_in;
-- start the computation, use generate to obtain the
-- multiple stages
gen8 : for j in K-1 downto 0 generate
stages : process (rst, clk)
begin
if (rst = '0') then
REG1(j) <= (REG1(j)'range => '0');
REG2(j) <= (REG2(j)'range => '0');
COEF(j) <= (COEF(j)'range => '0');
MULT16(j) <= (MULT16(j)'range => '0');
SUM(j) <= (SUM(j)'range => '0');
elsif (clk'event and clk = '1') then
REG1(j) <= REG2(j+1);
REG2(j) <= REG1(j);
if (coef_ld = '1') then
COEF(j) <= COEF(j+1);
end if;
MULT8(j) <= signed(REG1(j))*signed(COEF(j));
MULT16(j)(7 downto 0) <= MULT8(j);
if (MULT8(j)(7) = '0') then
MULT16(j)(15 downto 8) <= "00000000";
else
MULT16(j)(15 downto 8) <= "11111111";
end if;
SUM(j) <= signed(MULT16(j))+signed(SUM(j+1));
end if;
end process;
end generate;
-- control the outputs by concurrent statements
Xn_tmp <= Xn_in when bypass = '1' else
REG2(0) when coef_ld = '0' else
COEF(0);
Yn_tmp <= Yn_in when bypass = '1' else
SUM(0);
Xn_out <= Xn_tmp when o_enable = '0' else
(Xn_out'range => 'Z');
Yn_out <= Yn_tmp when o_enable = '0' else
(Yn_out'range => 'Z');
end BEH;
| gpl-3.0 | ffad31efe6ef6c9ccf92d2cef26491ae | 0.48844 | 3.42042 | false | false | false | false |
xcthulhu/periphondemand | src/tests/industrial_serial_input.vhd | 1 | 10,149 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 30/04/2009
-- File : industrial_serial_input.vhd
--
-- Abstract : This IP manage input serialized by the
-- industrial 8-digital-input serializer : SN65HVS882
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity industrial_serial_input is
---------------------------------------------------------------------------
generic(
id : natural := 1; -- identification register value
wb_size : natural := 16; -- Data port size for wishbone
clk_freq : natural := 133000 -- fpga clock speed
);
port
(
-- Syscon signals
reset : in std_logic ; -- reset
clk : in std_logic ; -- general clock
-- Wishbone signals
wbs_add : in std_logic_vector( 1 downto 0) ; -- address bus
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- interrupt
interrupt : out std_logic ; -- interrupt signal
-- SN65HVS882 controls signals
spi_sip : out std_logic ;
spi_ld_n : out std_logic ;
spi_clk : out std_logic ; -- SPI clock
spi_sop : in std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture industrial_serial_input_1 of industrial_serial_input is
---------------------------------------------------------------------------
-- usefull constants
constant ZERO : std_logic_vector( 31 downto 0) := (others => '0');
-- states type
type state is (spi_init_state,spi_read7_state,spi_read_state,spi_end_state);
signal state_reg : state;
signal next_state_reg : state;
-- registers addresses
constant REG_DATA : std_logic_vector( 1 downto 0) := "00"; -- |x[15:9]|int_en|data[7:0]
constant REG_READ_PER : std_logic_vector( 1 downto 0) := "01"; -- read period = reg x read period
constant REG_BUS_PER : std_logic_vector( 1 downto 0) := "10"; -- register period = reg x clock period
constant REG_ID : std_logic_vector( 1 downto 0) := "11"; -- identification register
-- registers
signal data : std_logic_vector( 7 downto 0);
signal int_en : std_logic ;
signal read_per : std_logic_vector( wb_size-1 downto 0);
signal bus_per : std_logic_vector( wb_size-1 downto 0);
-- local clocks signals
signal local_clk : std_logic ;
signal div_clk : std_logic ;
signal clock_rise_pulse : std_logic ;
signal clock_fall_pulse : std_logic ;
-- spi signals
signal spi_read_pulse : std_logic ;
signal spi_read_count : natural range 0 to 7;
-- wisbone acks
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
-- read process
read_p : process (clk,reset)
begin
if reset = '1' then
wbs_readdata <= (others => '0');
elsif rising_edge(clk) then
if (wbs_strobe and (not wbs_write) and wbs_cycle) = '1' then
read_ack <= '1';
case wbs_add is
when REG_DATA =>
wbs_readdata <= ZERO(6 downto 0)&int_en&data;
when REG_READ_PER =>
wbs_readdata <= read_per;
when REG_BUS_PER =>
wbs_readdata <= bus_per;
when REG_ID =>
wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
when others =>
wbs_readdata <= (others => '0');
end case;
else
read_ack <= '0';
wbs_readdata <= (others => '0');
end if;
end if;
end process read_p;
-- write process
write_p : process (clk, reset)
begin
if reset = '1' then
int_en <= '0';
elsif rising_edge(clk) then
if (wbs_strobe and (not wbs_write) and wbs_cycle) = '1' then
case wbs_add is
when REG_DATA =>
int_en <= wbs_writedata(8);
write_ack <= '1';
when REG_READ_PER =>
read_per <= wbs_writedata;
write_ack <= '1';
when REG_BUS_PER =>
bus_per <= wbs_writedata;
write_ack <= '1';
when others =>
write_ack <= '1';
end case;
else
write_ack <= '0';
end if;
end if;
end process write_p;
wbs_ack <= read_ack or write_ack;
-- SPI clock generator
local_clk <= clk when bus_per = x"0000" else div_clk;
clock_divider : process (clk,reset)
variable count : natural range 0 to (2**wb_size)-1;
begin
if reset = '1' then
count := 0;
div_clk <= '0';
clock_rise_pulse <= '0';
clock_fall_pulse <= '0';
elsif rising_edge(clk) then
if (count < to_integer(unsigned(bus_per))) then
count := count + 1;
div_clk <= div_clk;
clock_rise_pulse <= '0';
clock_fall_pulse <= '0';
else
clock_fall_pulse <= div_clk;
clock_rise_pulse <= not div_clk;
div_clk <= not div_clk;
count := 0;
end if;
end if;
end process clock_divider;
-- read_pulse generator
read_pulse_p : process (clk,reset)
variable count : natural range 0 to (2**wb_size)-1;
begin
if reset = '1' then
count := 0;
spi_read_pulse <= '0';
elsif rising_edge(clk) then
if (count < to_integer(unsigned(read_per))) then
if clock_rise_pulse = '1' then
count := count + 1;
spi_read_pulse <= spi_read_pulse;
elsif clock_fall_pulse = '1' then
spi_read_pulse <= '0';
end if;
elsif clock_rise_pulse = '1' then
count := 0;
spi_read_pulse <= '1';
end if;
end if;
end process read_pulse_p;
-- interrupt management process
interrupt_p : process (clk,reset)
begin
if reset = '1' then
interrupt <= '0';
elsif rising_edge(clk) then
if state_reg = spi_end_state then
interrupt <= int_en;
elsif (read_ack = '1') and (wbs_add = REG_DATA) then
interrupt <= '0'; -- reset interrupt when data register is read
end if;
end if;
end process interrupt_p;
----------------------------
-- spi read state machine --
----------------------------
-- state register
spi_state_register_p : process (clk,reset)
begin
if reset = '1' then
state_reg <= spi_init_state;
elsif rising_edge(clk) then
state_reg <= next_state_reg;
end if;
end process spi_state_register_p;
-- next-state logic
nstate_p : process (state_reg,spi_read_pulse,clock_rise_pulse,spi_read_count)
begin
case state_reg is
when spi_init_state =>
if spi_read_pulse = '1' then
next_state_reg <= spi_read7_state;
else
next_state_reg <= spi_init_state;
end if;
when spi_read7_state =>
if spi_read_pulse = '0' and clock_rise_pulse = '1' then
next_state_reg <= spi_read_state;
else
next_state_reg <= spi_read7_state;
end if;
when spi_read_state =>
if spi_read_count > 6 then
next_state_reg <= spi_end_state;
else
next_state_reg <= spi_read_state;
end if;
when spi_end_state =>
next_state_reg <= spi_init_state;
when others =>
next_state_reg <= spi_init_state;
end case;
end process nstate_p;
-- output logic
--output_p : process (state_reg,spi_sop,data,local_clk)
output_p : process (clk,reset)
begin
if reset = '1' then
data <= (others => '0');
spi_clk <= '0';
elsif rising_edge(clk) then
case state_reg is
when spi_init_state =>
data <= (others => '0');
spi_clk <= '0';
when spi_read7_state =>
spi_clk <= local_clk;
data <= ZERO(7 downto 1)&spi_sop;
when spi_read_state =>
spi_clk <= local_clk;
data <= data(6 downto 0)&spi_sop;
when others =>
spi_clk <= local_clk;
end case;
end if;
end process output_p;
spi_ld_n <= not spi_read_pulse;
spi_sip <= '1';
-- read count
read_count_p : process (clk, reset)
begin
if reset = '1' then
spi_read_count <= 0;
elsif rising_edge(clk) then
if state_reg = spi_read_state and clock_rise_pulse = '1' then
spi_read_count <= spi_read_count + 1;
else
spi_read_count <= 0;
end if;
end if;
end process read_count_p;
end architecture industrial_serial_input_1;
| lgpl-2.1 | 5b3631f63a97fc67739f4a66790b1d29 | 0.460735 | 4.18343 | false | false | false | false |
xcthulhu/periphondemand | src/library/syscons/dcm_syscon/hdl/wb_syscon.vhd | 1 | 5,351 | ---------------------------------------------------------------------------
-- Company : ARMadeus Systems
-- Author(s) : Fabien Marteau
--
-- Creation Date : 05/03/2008
-- File : wb_syscon.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- for dcm simulation
Library UNISIM;
use UNISIM.vcomponents.all;
---------------------------------------------------------------------------
Entity wb_syscon is
---------------------------------------------------------------------------
port
(
-- external signals
ext_clk : in std_logic ;
--internal signals
gls_clk : out std_logic ;
gls_reset : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture wb_syscon_1 of wb_syscon is
---------------------------------------------------------------------------
signal dly: std_logic := '0';
signal rst: std_logic := '0';
signal ext_reset : std_logic;
signal CLK0 : std_logic ;
signal CLK180 : std_logic; -- 180 degree DCM CLK output
signal CLK270 : std_logic; -- 270 degree DCM CLK output
signal CLK2X : std_logic; -- 2X DCM CLK output
signal CLK2X180 : std_logic; -- 2X, 180 degree DCM CLK out
signal CLK90 : std_logic; -- 90 degree DCM CLK output
signal CLKDV : std_logic; -- Divided DCM CLK out (CLKDV_DIVIDE)
signal CLKFX : std_logic; -- DCM CLK synthesis out (M/D)
signal CLKFX180 : std_logic; -- 180 degree CLK synthesis out
signal LOCKED : std_logic; -- DCM LOCK status output
signal PSDONE : std_logic; -- Dynamic phase adjust done output
signal STATUS : std_logic_vector( 7 downto 0); -- 8-bit DCM status bits output
signal CLKFB : std_logic; -- DCM clock feedback
signal CLKIN : std_logic; -- Clock input (from IBUFG, BUFG or DCM)
signal PSCLK : std_logic; -- Dynamic phase adjust clock input
signal PSEN : std_logic; -- Dynamic phase adjust enable input
signal PSINCDEC : std_logic; -- Dynamic phase adjust increment/decrement
--signal RST : std_logic ; -- DCM asynchronous reset input
begin
ext_reset <= '0';
----------------------------------------------------------------------------
-- RESET signal generator.
----------------------------------------------------------------------------
process(ext_clk)
begin
if(rising_edge(ext_clk)) then
dly <= ( not(ext_reset) and dly and not(rst) )
or ( not(ext_reset) and not(dly) and rst );
rst <= ( not(ext_reset) and not(dly) and not(rst) );
end if;
end process;
gls_clk <= CLK2X;
gls_reset <= rst;
CLKIN <= ext_clk;
CLKFB <= CLK2X;
-- DCM: Digital Clock Manager Circuit
-- Virtex-II/II-Pro and Spartan-3
-- Xilinx HDL Language Template, version 10.1
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 0.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DCM CLK ouptput
CLK180 => CLK180, -- 180 degree DCM CLK output
CLK270 => CLK270, -- 270 degree DCM CLK output
CLK2X => CLK2X, -- 2X DCM CLK output
CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
CLK90 => CLK90, -- 90 degree DCM CLK output
CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => CLKFX, -- DCM CLK synthesis out (M/D)
CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
LOCKED => LOCKED, -- DCM LOCK status output
PSDONE => PSDONE, -- Dynamic phase adjust done output
STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => CLKFB, -- DCM clock feedback
CLKIN => CLKIN, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => PSCLK, -- Dynamic phase adjust clock input
PSEN => PSEN, -- Dynamic phase adjust enable input
PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => rst -- DCM asynchronous reset input
);
-- End of DCM_inst instantiation
end architecture wb_syscon_1;
| lgpl-2.1 | 082bf9ba8d0b4ac4b7acebc773f61575 | 0.540086 | 4.038491 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/defragment_and_check_crc.vhd | 1 | 7,383 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: defragment_and_check_crc - Behavioral
--
-- Description: Defragment packets into a stream of contiguious bytes,
-- NOTE - does not yet check CRCs.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity defragment_and_check_crc is
Port ( clk : in STD_LOGIC;
input_data_enable : in STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
packet_data_valid : out STD_LOGIC := '0';
packet_data : out STD_LOGIC_VECTOR (7 downto 0) := (others=>'0'));
end defragment_and_check_crc;
architecture Behavioral of defragment_and_check_crc is
type a_buffer is array(0 to 2047) of std_logic_vector(8 downto 0);
signal data_buffer : a_buffer := (others => (others => '0'));
signal read_addr : unsigned(10 downto 0) := (others => '0');
signal start_of_packet_addr : unsigned(10 downto 0) := (others => '0');
signal write_addr : unsigned(10 downto 0) := (others => '0');
--------------------------------------------------------------------
-- because all frames must be > 15 bytes long, the maximum frames
-- in the buffer is 2048/15 = 136
--------------------------------------------------------------------
signal complete_packets : unsigned(7 downto 0) := (others => '0');
signal input_data_present_last : std_logic := '0';
signal ram_data_out : std_logic_vector(8 downto 0);
begin
packet_data_valid <= ram_data_out(8);
packet_data <= ram_data_out(7 downto 0);
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--!! TODO: CRC CHECK NOT YET IMPLEMENTED
--!! ERROR CHECK NOT YET IMPLEMENTED
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
process(clk)
variable v_complete_packets : unsigned(7 downto 0) := (others => '0');
begin
if rising_edge(clk) then
--------------------------------------------------
-- The decrementing of complete_packets is delayed
-- one cycle (occurs after the cycle where the data
-- is read.
--
-- This is done this way to allow the data
-- to be held in a block RAM, rather than using
-- a huge amount of LUTs.
----------------------------------------------------
if v_complete_packets /= 0 and ram_data_out(8) = '0' then
v_complete_packets := v_complete_packets - 1;
else
v_complete_packets := complete_packets;
end if;
---------------------------------------
-- Writing in any fragments of a packet
---------------------------------------
if input_data_enable = '1' then
if input_data_present_last = '0' then
if input_data_present = '0' then
------------------------------------------------------------
-- What to do if there are two or more idle words in a row
------------------------------------------------------------
NULL;
else
--------------------------------
-- What to do on start of packet
--------------------------------
start_of_packet_addr <= write_addr;
data_buffer(to_integer(write_addr)) <= input_data_present & input_data;
write_addr <= write_addr + 1;
end if;
else
if input_data_present = '1' then
data_buffer(to_integer(write_addr)) <= input_data_present & input_data;
write_addr <= write_addr + 1;
else
------------------------------------------------------------
-- What to do on end of packet
------------------------------------------------------------
-- Skip backwards over the frame check sequence (CRC) when
-- we see the end of packet.
--
-- If the packet had any errors we will skip back to the start
-- of the packet (but am not checking at the moment!)
-----------------------------------------------------------
v_complete_packets := v_complete_packets + 1;
data_buffer(to_integer(write_addr-4)) <= input_data_present & input_data;
write_addr <= write_addr - 4 + 1;
end if;
end if;
------------------------------------------------
-- Remember if we had data this active cycle, so
-- we can detect the starts and ends of packets
------------------------------------------------
input_data_present_last <= input_data_present;
end if;
---------------------------------------
-- Streaming out any completed packets
---------------------------------------
if v_complete_packets /= 0 then
ram_data_out <= data_buffer(to_integer(read_addr));
read_addr <= read_addr+1;
else
ram_data_out <= (others => '0');
end if;
complete_packets <= v_complete_packets;
end if;
end process;
end Behavioral;
| mit | 52744d5f6f866f79bcbb93c1e001bd3b | 0.445347 | 5.247335 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx3/top.vhdl | 1 | 3,098 | --
-- Top level of gtx3 example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
use FPGALIB.sync.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
rst_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
clk_o : out std_logic;
sma_rx_p_i : in std_logic;
sma_rx_n_i : in std_logic;
sma_tx_p_o : out std_logic;
sma_tx_n_o : out std_logic;
pbc_i : in std_logic;
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of top is
constant BYTES : positive:=4;
signal sysclk, clk : std_logic;
signal rst_gtx, rst_loop : std_logic;
signal locked, ready : std_logic;
signal loopback : std_logic;
-- GBT data
signal rx_data, rx_data_bound, tx_data : std_logic_vector(BYTES*8-1 downto 0);
signal rx_isk, rx_isk_bound, tx_isk : std_logic_vector(BYTES-1 downto 0);
--
signal finish : std_logic;
signal errors : std_logic_vector(4 downto 0);
begin
-- From 200 MHz differential to 150 MHz single-ended.
mmcm_inst: entity work.mmcm200to150
port map (
CLK_IN1_P => clk_p_i,
CLK_IN1_N => clk_n_i,
CLK_OUT1 => sysclk,
RESET => rst_i,
LOCKED => locked
);
rst_gtx <= not locked;
loopback <= not pbc_i;
gbt_i: entity work.Wrapper
port map (
clk_i => sysclk,
rst_i => rst_gtx,
clk_o => clk,
--
rxp_i => sma_rx_p_i,
rxn_i => sma_rx_n_i,
txp_o => sma_tx_p_o,
txn_o => sma_tx_n_o,
--
loopback_i=> loopback,
rx_data_o => rx_data,
rx_isk_o => rx_isk,
tx_data_i => tx_data,
tx_isk_i => tx_isk,
ready_o => ready
);
-- To ensure that we understand *rx_data* in the same order that *tx_data*.
bound_i: Boundary
generic map(BYTES => BYTES)
port map(
clk_i => clk,
pattern_i => (others => '1'),
comma_i => rx_isk,
data_i => rx_data,
comma_o => rx_isk_bound,
data_o => rx_data_bound
);
rst_loop <= not ready;
-- For test the loop.
loop_i: TransLoop
generic map(
TSIZE => 2048,
DBYTES => BYTES,
FSIZE => 512
)
port map(
-- TX side
tx_clk_i => clk,
tx_rst_i => rst_loop,
tx_data_i => (others => '0'),
tx_data_o => tx_data,
tx_isk_o => tx_isk,
tx_ready_i => ready,
-- RX side
rx_clk_i => clk,
rx_rst_i => rst_loop,
rx_data_i => rx_data_bound,
rx_isk_i => rx_isk_bound,
rx_errors_o => errors,
rx_finish_o => finish,
rx_cycles_o => open
);
leds_o <= finish & "00" & errors;
clk_o <= clk;
end architecture RTL;
| bsd-3-clause | 8f28484613c20d4079564cd31b8e90fe | 0.505487 | 3.067327 | false | false | false | false |
wifidar/wifidar_fpga | src/dac_section/phase_acc.vhd | 1 | 822 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phase_acc is
generic(
sine_length_bits: integer := 10
);
port(
x_out: out std_logic_vector(sine_length_bits - 1 downto 0);
freq_mult: in std_logic_vector(9 downto 0);
phase_in: in std_logic_vector(7 downto 0);
new_signal: out std_logic;
clk: in std_logic
);
end phase_acc;
architecture Behavioral of phase_acc is
signal big_ol_counter: unsigned(20 downto 0) := (others => '0');
begin
process(clk)
begin
if(rising_edge(clk)) then
big_ol_counter <= big_ol_counter + unsigned(freq_mult);
if(big_ol_counter < "10000") then
new_signal <= '1';
else
new_signal <= '0';
end if;
end if;
end process;
x_out <= std_logic_vector(big_ol_counter(20 downto 11) + unsigned(phase_in & "00"));
end Behavioral;
| mit | f7aaeee5f06e8546726fe1e57f4fddc3 | 0.663017 | 2.730897 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles_graphs/synthesisShowcase/syncCaseStmt.vhd | 2 | 787 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity syncCase is
port(A : in std_logic;
sel : in std_logic_vector(2 downto 0);
clock : in std_logic);
end syncCase;
architecture behv of syncCase is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if rising_edge(clock) then
case sel is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => A <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end if;
end process;
end behv;
| gpl-3.0 | b51b11fe640886aff902aa17c76ab5ae | 0.491741 | 3.279167 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/fifo_rxclk_to_clk125MHz.vhd | 1 | 3,622 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: fifo_rxclk_to_clk125MHz - Behavioral
--
-- Description: A wrapper around a IP FIFO
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_rxclk_to_clk125MHz is
Port ( rx_clk : in STD_LOGIC;
rx_write : in STD_LOGIC := '1';
rx_data : in STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
rx_data_present : in STD_LOGIC := '0';
rx_data_error : in STD_LOGIC := '0';
clk125Mhz : in STD_LOGIC;
empty : out STD_LOGIC := '1';
read : in STD_LOGIC := '1';
data : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_present : out STD_LOGIC := '0';
data_error : out STD_LOGIC := '0');
end fifo_rxclk_to_clk125MHz;
architecture Behavioral of fifo_rxclk_to_clk125MHz is
COMPONENT fifo_dual_clock_10_bits_16_deep
PORT (
wr_clk : IN STD_LOGIC;
full : OUT STD_LOGIC;
wr_en : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_clk : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
empty : OUT STD_LOGIC);
END COMPONENT;
begin
i_fifo_dual_clock_10_bits_16_deep : fifo_dual_clock_10_bits_16_deep PORT MAP (
wr_clk => rx_clk,
wr_en => rx_write,
din(9) => rx_data_present,
din(8) => rx_data_error,
din(7 downto 0) => rx_data,
full => open,
rd_clk => clk125Mhz,
empty => empty,
rd_en => read,
dout(9) => data_present,
dout(8) => data_error,
dout(7 downto 0) => data);
end Behavioral;
| mit | 1afabdb05087710b0b05c534526c569d | 0.511872 | 4.266196 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp/tcp_tx_packet.vhd | 1 | 13,469 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 05.06.2016 22:31:14
-- Module Name: tcp_tx_packet - Behavioral
--
-- Description: Construct and send out TCP packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_tx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
tcp_tx_busy : out std_logic;
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end tcp_tx_packet;
architecture Behavioral of tcp_tx_packet is
signal busy_countdown : unsigned(7 downto 0) := (others => '0');
-- For holding the destination and port details on the first data transfer
signal tcp_tx_hdr_valid_last : STD_LOGIC := '0';
signal tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tx_dst_mac : std_logic_vector(47 downto 0) := (others => '0');
signal tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_length : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal pre_tcp_valid : STD_LOGIC := '0';
signal pre_tcp_data : STD_LOGIC_VECTOR (7 downto 0);
component buffer_count_and_checksum_data is
generic (min_length : natural);
Port ( clk : in STD_LOGIC;
hdr_valid_in : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_length : out std_logic_vector(15 downto 0);
data_checksum : out std_logic_vector(15 downto 0));
end component;
signal data_length : std_logic_vector(15 downto 0);
signal data_checksum : std_logic_vector(15 downto 0);
component tcp_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
tcp_src_port : in std_logic_vector(15 downto 0);
tcp_dst_port : in std_logic_vector(15 downto 0);
tcp_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_flag_urg : in std_logic := '0';
tcp_flag_ack : in std_logic := '0';
tcp_flag_psh : in std_logic := '0';
tcp_flag_rst : in std_logic := '0';
tcp_flag_syn : in std_logic := '0';
tcp_flag_fin : in std_logic := '0';
tcp_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0));
end component;
signal pre_ip_valid : STD_LOGIC := '0';
signal pre_ip_data : STD_LOGIC_VECTOR (7 downto 0);
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_data_length : std_logic_vector(15 downto 0);
component ip_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_data_length : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end component;
signal pre_header_valid : STD_LOGIC := '0';
signal pre_header_data : STD_LOGIC_VECTOR (7 downto 0);
component ethernet_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_type : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ether_dst_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal complete_valid : STD_LOGIC := '0';
signal complete_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
component transport_commit_buffer
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
begin
process(clk)
begin
if rising_edge(clk) then
-- Capture the destination address data on the first cycle of the data packet
if tcp_tx_hdr_valid = '1' then
if tcp_tx_hdr_valid_last = '0' then
tx_src_port <= tcp_tx_src_port;
tx_dst_mac <= tcp_tx_dst_mac;
tx_dst_ip <= tcp_tx_dst_ip;
tx_dst_port <= tcp_tx_dst_port;
busy_countdown <= to_unsigned(8+64+12-4,8);
-- 8 = preamble
-- 64 = minimum ethernet header
-- 12 = minimum inter-packet gap
-- and -4 is a fix for latency
tcp_tx_busy <= '1';
else
-- Allow for the bytes that will be added
if busy_countdown > 8+14+20+8+4+12 -3 then
-- allow for premable (8)
-- and ethernet Header(14)
-- and ip header (20)
-- and udp hereader (8)
-- and ethernet FCS (4)
-- and minimum inter-packet gap
-- and -3 is a fix for latency
busy_countdown <= busy_countdown-1;
end if;
end if;
else
-- Keep udp_tx_busy asserted to allow for
-- everything to be wrapped around the data
if busy_countdown > 0 then
busy_countdown <= busy_countdown - 1;
else
tcp_tx_busy <= '0';
end if;
end if;
tcp_tx_hdr_valid_last <= tcp_tx_hdr_valid;
end if;
end process;
i_buffer_count_and_checksum_data: buffer_count_and_checksum_data generic map (
min_length => 60-14-20-20
) port map (
clk => clk,
hdr_valid_in => tcp_tx_hdr_valid,
data_valid_in => tcp_tx_data_valid,
data_in => tcp_tx_data,
data_valid_out => pre_tcp_valid,
data_out => pre_tcp_data,
data_length => data_length,
data_checksum => data_checksum);
i_tcp_add_header: tcp_add_header port map (
clk => clk,
data_valid_in => pre_tcp_valid,
data_in => pre_tcp_data,
data_valid_out => pre_ip_valid,
data_out => pre_ip_data,
data_length => data_length,
data_checksum => data_checksum,
ip_src_ip => our_ip,
ip_dst_ip => tcp_tx_dst_ip,
tcp_src_port => tcp_tx_src_port,
tcp_dst_port => tcp_tx_dst_port,
tcp_seq_num => tcp_tx_seq_num,
tcp_ack_num => tcp_tx_ack_num,
tcp_window => tcp_tx_window,
tcp_flag_urg => tcp_tx_flag_urg,
tcp_flag_ack => tcp_tx_flag_ack,
tcp_flag_psh => tcp_tx_flag_psh,
tcp_flag_rst => tcp_tx_flag_rst,
tcp_flag_syn => tcp_tx_flag_syn,
tcp_flag_fin => tcp_tx_flag_fin,
tcp_urgent_ptr => tcp_tx_urgent_ptr);
ip_data_length <= std_logic_vector(unsigned(data_length)+20);
i_ip_add_header: ip_add_header port map (
clk => clk,
data_valid_in => pre_ip_valid,
data_in => pre_ip_data,
data_valid_out => pre_header_valid,
data_out => pre_header_data,
ip_data_length => ip_data_length,
ip_protocol => x"06",
ip_src_ip => our_ip,
ip_dst_ip => tx_dst_ip);
i_ethernet_add_header: ethernet_add_header port map (
clk => clk,
data_valid_in => pre_header_valid,
data_in => pre_header_data,
data_valid_out => complete_valid,
data_out => complete_data,
ether_type => x"0800",
ether_dst_mac => tx_dst_mac,
ether_src_mac => our_mac);
i_transport_commit_buffer: transport_commit_buffer port map (
clk => clk,
data_valid_in => complete_valid,
data_in => complete_data,
packet_out_request => packet_out_request,
packet_out_granted => packet_out_granted,
packet_out_valid => packet_out_valid,
packet_out_data => packet_out_data);
end Behavioral; | mit | 596daae0c0a8743dc0e74ac0de6af57d | 0.502413 | 3.676037 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/uart16750/hdl/uart16550_wb16.vhd | 1 | 5,840 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 25/06/2008
-- File : uart_top_vhdl.vhd
--
-- Abstract : wrapper for uar16750 from opencores to VHDL-Wishbone16 bus
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity uart16750 is
---------------------------------------------------------------------------
generic(
id : natural := 1;
wb_size : natural := 16
);
port (
-- clock
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector( 3 downto 0);
wb_dat_i : in std_logic_vector( 15 downto 0);
wb_dat_o : out std_logic_vector( 15 downto 0);
wb_we_i : in std_logic ;
wb_stb_i : in std_logic ;
wb_cyc_i : in std_logic ;
wb_ack_o : out std_logic ;
-- interrupt
int_o : out std_logic ;
-- uart signals
srx_pad_i : in std_logic ;
stx_pad_o : out std_logic ;
rts_pad_o : out std_logic ;
cts_pad_i : in std_logic ;
dtr_pad_o : out std_logic ;
dsr_pad_i : in std_logic ;
ri_pad_i : in std_logic ;
dcd_pad_i : in std_logic
-- optional baudrate output
-- baud_o : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture uart_top_vhdl_1 of uart16750 is
---------------------------------------------------------------------------
component uart_16750
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end component uart_16750;
signal wb_dat_i_int : std_logic_vector( 7 downto 0);
signal wb_dat_o_int : std_logic_vector( 7 downto 0);
signal strobe : std_logic ;
signal baudrateX16 : std_logic ;
begin
wb_dat_i_int <= wb_dat_i(7 downto 0);
strobe <= wb_stb_i when wb_adr_i(3) = '0' else '0';
wb_dat_o <= std_logic_vector(to_unsigned(id,wb_size))
when wb_adr_i = "1000" and wb_stb_i = '1' and wb_we_i = '0'
else "00000000"&wb_dat_o_int
when wb_adr_i(3)= '0' and wb_stb_i = '1' and wb_we_i = '0'
else (others => '0');
uart_connect : uart_16750
port map (
CLK => wb_clk_i, -- Clock
RST => wb_rst_i, -- Reset
BAUDCE => '1', -- Baudrate generator clock enable
CS => wb_stb_i, -- Chip select
WR => wb_we_i, -- Write to UART
RD => not wb_we_i, -- Read from UART
A => wb_adr_i(2 downto 0), -- Register select
DIN => wb_dat_i_int, -- Data bus input
DOUT => wb_dat_o_int, -- Data bus output
DDIS => open, -- Driver disable
INT => int_o, -- Interrupt output
OUT1N => open, -- Output 1
OUT2N => open, -- Output 2
RCLK => baudrateX16, -- Receiver clock (16x baudrate)
BAUDOUTN => baudrateX16, -- Baudrate generator output (16x baudrate)
RTSN => rts_pad_o, -- RTS output
DTRN => dtr_pad_o, -- DTR output
CTSN => cts_pad_i, -- CTS input
DSRN => dsr_pad_i, -- DSR input
DCDN => dcd_pad_i, -- DCD input
RIN => ri_pad_i, -- RI input
SIN => srx_pad_i, -- Receiver input
SOUT => stx_pad_o -- Transmitter output
);
end architecture uart_top_vhdl_1;
| lgpl-2.1 | 39f3e9ed9436b1d62312e1b22cb02fef | 0.39863 | 4.316334 | false | false | false | false |
99yen/vhdl-snake | ps2keyboard.vhd | 1 | 2,387 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PS2KEYBOARD is
port (
CLK : in std_logic;
RST : in std_logic;
PS2_KBCLK, PS2_KBDAT : in std_logic;
KEYCODE : out std_logic_vector(7 downto 0);
CODE_ENABLE : out std_logic
);
end PS2KEYBOARD;
architecture RTL of PS2KEYBOARD is
type STATE_SET is (START_BIT, DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, PARITY_BIT, STOP_BIT);
signal PS2CLK : std_logic_vector(1 downto 0);
signal KEYCODE_BUF : std_logic_vector(7 downto 0);
signal STATE : STATE_SET;
signal PARITY : std_logic;
begin
KEYCODE <= KEYCODE_BUF;
PARITY <= KEYCODE_BUF(0) xor KEYCODE_BUF(1) xor KEYCODE_BUF(2) xor KEYCODE_BUF(3) xor
KEYCODE_BUF(4) xor KEYCODE_BUF(5) xor KEYCODE_BUF(6) xor KEYCODE_BUF(7) xor '1';
process (CLK, RST) begin
if (RST = '0') then
PS2CLK <= "00";
STATE <= START_BIT;
KEYCODE_BUF <= (others => '0');
CODE_ENABLE <= '0';
elsif (CLK'event and CLK = '1') then
PS2CLK <= PS2CLK(0) & PS2_KBCLK;
if (PS2CLK = "10") then
case STATE is
when START_BIT =>
if (PS2_KBDAT = '0') then
STATE <= DATA0;
CODE_ENABLE <= '0';
else
STATE <= START_BIT;
end if;
when DATA0 =>
STATE <= DATA1;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA1 =>
STATE <= DATA2;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA2 =>
STATE <= DATA3;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA3 =>
STATE <= DATA4;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA4 =>
STATE <= DATA5;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA5 =>
STATE <= DATA6;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA6 =>
STATE <= DATA7;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when DATA7 =>
STATE <= PARITY_BIT;
KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1);
when PARITY_BIT =>
if (PS2_KBDAT = PARITY) then
STATE <= STOP_BIT;
else
STATE <= START_BIT;
end if;
when STOP_BIT =>
if (PS2_KBDAT = '1') then
STATE <= START_BIT;
CODE_ENABLE <= '1';
else
STATE <= START_BIT;
end if;
end case;
end if;
end if;
end process;
end RTL;
| gpl-2.0 | a52cab41fbd23b83d2d1875e3c946bd1 | 0.583997 | 2.889831 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | shared/vivado_repo/AXIF_MASTER_DPRAM/AXIF_MASTER_DPRAM.vhdl | 1 | 8,013 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIF_MASTER_DPRAM is
generic (
C_NO_WRITE_RESPONSE : boolean:= FALSE;
C_AxCACHE : std_logic_vector(3 downto 0) := "0010";
-- Parameters of Axi Slave Bus Interface S_AXIL
C_S_AXIL_ADDR_WIDTH : integer := 4;
-- Parameters of Axi Master Bus Interface M_AXIF
C_M_AXIF_ID_WIDTH : integer := 1;
C_M_AXIF_AWUSER_WIDTH : integer := 1;
C_M_AXIF_ARUSER_WIDTH : integer := 1;
C_M_AXIF_WUSER_WIDTH : integer := 4;
C_M_AXIF_RUSER_WIDTH : integer := 4;
C_M_AXIF_BUSER_WIDTH : integer := 1
);
port (
-- Users to add ports here
aclk : in std_logic;
aresetn : in std_logic;
-- User ports ends
-- Ports of Axi Slave Bus Interface S_AXIL
s_axil_awaddr : in std_logic_vector(C_S_AXIL_ADDR_WIDTH-1 downto 0);
s_axil_awprot : in std_logic_vector(2 downto 0);
s_axil_awvalid : in std_logic;
s_axil_awready : out std_logic;
s_axil_wdata : in std_logic_vector(31 downto 0);
s_axil_wstrb : in std_logic_vector((32/8)-1 downto 0);
s_axil_wvalid : in std_logic;
s_axil_wready : out std_logic;
s_axil_bresp : out std_logic_vector(1 downto 0);
s_axil_bvalid : out std_logic;
s_axil_bready : in std_logic;
s_axil_araddr : in std_logic_vector(C_S_AXIL_ADDR_WIDTH-1 downto 0);
s_axil_arprot : in std_logic_vector(2 downto 0);
s_axil_arvalid : in std_logic;
s_axil_arready : out std_logic;
s_axil_rdata : out std_logic_vector(31 downto 0);
s_axil_rresp : out std_logic_vector(1 downto 0);
s_axil_rvalid : out std_logic;
s_axil_rready : in std_logic;
-- Ports of Axi Master Bus Interface M_AXIF
m_axif_awid : out std_logic_vector(C_M_AXIF_ID_WIDTH-1 downto 0);
m_axif_awaddr : out std_logic_vector(31 downto 0);
m_axif_awlen : out std_logic_vector(7 downto 0);
m_axif_awsize : out std_logic_vector(2 downto 0);
m_axif_awburst : out std_logic_vector(1 downto 0);
m_axif_awlock : out std_logic;
m_axif_awcache : out std_logic_vector(3 downto 0);
m_axif_awprot : out std_logic_vector(2 downto 0);
m_axif_awqos : out std_logic_vector(3 downto 0);
m_axif_awuser : out std_logic_vector(C_M_AXIF_AWUSER_WIDTH-1 downto 0);
m_axif_awvalid : out std_logic;
m_axif_awready : in std_logic;
m_axif_wdata : out std_logic_vector(31 downto 0);
m_axif_wstrb : out std_logic_vector(32/8-1 downto 0);
m_axif_wlast : out std_logic;
m_axif_wuser : out std_logic_vector(C_M_AXIF_WUSER_WIDTH-1 downto 0);
m_axif_wvalid : out std_logic;
m_axif_wready : in std_logic;
m_axif_bid : in std_logic_vector(C_M_AXIF_ID_WIDTH-1 downto 0);
m_axif_bresp : in std_logic_vector(1 downto 0);
m_axif_buser : in std_logic_vector(C_M_AXIF_BUSER_WIDTH-1 downto 0);
m_axif_bvalid : in std_logic;
m_axif_bready : out std_logic;
m_axif_arid : out std_logic_vector(C_M_AXIF_ID_WIDTH-1 downto 0);
m_axif_araddr : out std_logic_vector(31 downto 0);
m_axif_arlen : out std_logic_vector(7 downto 0);
m_axif_arsize : out std_logic_vector(2 downto 0);
m_axif_arburst : out std_logic_vector(1 downto 0);
m_axif_arlock : out std_logic;
m_axif_arcache : out std_logic_vector(3 downto 0);
m_axif_arprot : out std_logic_vector(2 downto 0);
m_axif_arqos : out std_logic_vector(3 downto 0);
m_axif_aruser : out std_logic_vector(C_M_AXIF_ARUSER_WIDTH-1 downto 0);
m_axif_arvalid : out std_logic;
m_axif_arready : in std_logic;
m_axif_rid : in std_logic_vector(C_M_AXIF_ID_WIDTH-1 downto 0);
m_axif_rdata : in std_logic_vector(31 downto 0);
m_axif_rresp : in std_logic_vector(1 downto 0);
m_axif_rlast : in std_logic;
m_axif_ruser : in std_logic_vector(C_M_AXIF_RUSER_WIDTH-1 downto 0);
m_axif_rvalid : in std_logic;
m_axif_rready : out std_logic
);
end AXIF_MASTER_DPRAM;
architecture arch_imp of AXIF_MASTER_DPRAM is
signal status : std_logic_vector(31 downto 0):=(others => '0');
signal control : std_logic_vector(31 downto 0);
signal length : std_logic_vector(31 downto 0);
signal rd_addr : std_logic_vector(31 downto 0);
signal wr_addr : std_logic_vector(31 downto 0);
begin
S_AXIL_inst : entity work.AXIF_MASTER_DPRAM_S_AXIL
generic map (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => C_S_AXIL_ADDR_WIDTH
)
port map (
status_i => status,
control_o => control,
length_o => length,
rd_addr_o => rd_addr,
wr_addr_o => wr_addr,
--
S_AXI_ACLK => aclk,
S_AXI_ARESETN => aresetn,
S_AXI_AWADDR => s_axil_awaddr,
S_AXI_AWPROT => s_axil_awprot,
S_AXI_AWVALID => s_axil_awvalid,
S_AXI_AWREADY => s_axil_awready,
S_AXI_WDATA => s_axil_wdata,
S_AXI_WSTRB => s_axil_wstrb,
S_AXI_WVALID => s_axil_wvalid,
S_AXI_WREADY => s_axil_wready,
S_AXI_BRESP => s_axil_bresp,
S_AXI_BVALID => s_axil_bvalid,
S_AXI_BREADY => s_axil_bready,
S_AXI_ARADDR => s_axil_araddr,
S_AXI_ARPROT => s_axil_arprot,
S_AXI_ARVALID => s_axil_arvalid,
S_AXI_ARREADY => s_axil_arready,
S_AXI_RDATA => s_axil_rdata,
S_AXI_RRESP => s_axil_rresp,
S_AXI_RVALID => s_axil_rvalid,
S_AXI_RREADY => s_axil_rready
);
M_AXIF_inst : entity work.AXIF_MASTER_DPRAM_M_AXIF
generic map (
C_NO_WRITE_RESPONSE => C_NO_WRITE_RESPONSE,
C_AxCACHE => C_AxCACHE,
C_M_AXI_ID_WIDTH => C_M_AXIF_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_AWUSER_WIDTH => C_M_AXIF_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXIF_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXIF_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXIF_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXIF_BUSER_WIDTH
)
port map (
start_i => control(0),
length_i => length,
rd_addr_i => rd_addr,
wr_addr_i => wr_addr,
busy_o => status(0),
--
M_AXI_ACLK => aclk,
M_AXI_ARESETN => aresetn,
M_AXI_AWID => m_axif_awid,
M_AXI_AWADDR => m_axif_awaddr,
M_AXI_AWLEN => m_axif_awlen,
M_AXI_AWSIZE => m_axif_awsize,
M_AXI_AWBURST => m_axif_awburst,
M_AXI_AWLOCK => m_axif_awlock,
M_AXI_AWCACHE => m_axif_awcache,
M_AXI_AWPROT => m_axif_awprot,
M_AXI_AWQOS => m_axif_awqos,
M_AXI_AWUSER => m_axif_awuser,
M_AXI_AWVALID => m_axif_awvalid,
M_AXI_AWREADY => m_axif_awready,
M_AXI_WDATA => m_axif_wdata,
M_AXI_WSTRB => m_axif_wstrb,
M_AXI_WLAST => m_axif_wlast,
M_AXI_WUSER => m_axif_wuser,
M_AXI_WVALID => m_axif_wvalid,
M_AXI_WREADY => m_axif_wready,
M_AXI_BID => m_axif_bid,
M_AXI_BRESP => m_axif_bresp,
M_AXI_BUSER => m_axif_buser,
M_AXI_BVALID => m_axif_bvalid,
M_AXI_BREADY => m_axif_bready,
M_AXI_ARID => m_axif_arid,
M_AXI_ARADDR => m_axif_araddr,
M_AXI_ARLEN => m_axif_arlen,
M_AXI_ARSIZE => m_axif_arsize,
M_AXI_ARBURST => m_axif_arburst,
M_AXI_ARLOCK => m_axif_arlock,
M_AXI_ARCACHE => m_axif_arcache,
M_AXI_ARPROT => m_axif_arprot,
M_AXI_ARQOS => m_axif_arqos,
M_AXI_ARUSER => m_axif_aruser,
M_AXI_ARVALID => m_axif_arvalid,
M_AXI_ARREADY => m_axif_arready,
M_AXI_RID => m_axif_rid,
M_AXI_RDATA => m_axif_rdata,
M_AXI_RRESP => m_axif_rresp,
M_AXI_RLAST => m_axif_rlast,
M_AXI_RUSER => m_axif_ruser,
M_AXI_RVALID => m_axif_rvalid,
M_AXI_RREADY => m_axif_rready
);
end arch_imp; | bsd-3-clause | 48f910774673a210c4e471cb431bc976 | 0.577437 | 2.898011 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/memc1_tb_top.vhd | 2 | 29,603 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc1_tb_top;
architecture arc of memc1_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
| cc0-1.0 | 8d6fa15f2d6502f024d5d7356ac4d318 | 0.497281 | 3.307967 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/ethernet/ethernet_extract_header.vhd | 1 | 5,379 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: ethernet_extract_header - Behavioral
--
-- Description: Extract the Ethernet header fields
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ethernet_extract_header is
generic (our_mac : std_logic_vector(47 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
filter_ether_type : in STD_LOGIC_VECTOR (15 downto 0);
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_dst_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end ethernet_extract_header;
architecture Behavioral of ethernet_extract_header is
signal count : unsigned(3 downto 0) := (others => '0');
signal ether_type : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ether_dst_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
signal i_ether_src_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
signal valid_mac : STD_LOGIC := '1';
begin
ether_dst_mac <= i_ether_dst_mac;
ether_src_mac <= i_ether_src_mac;
process(clk)
begin
if rising_edge(clk) then
data_out <= data_in;
if data_valid_in = '1' then
-- Note, at count of zero,
case count is
when "0000" => i_ether_dst_mac( 7 downto 0) <= data_in;
when "0001" => i_ether_dst_mac(15 downto 8) <= data_in;
when "0010" => i_ether_dst_mac(23 downto 16) <= data_in;
when "0011" => i_ether_dst_mac(31 downto 24) <= data_in;
when "0100" => i_ether_dst_mac(39 downto 32) <= data_in;
when "0101" => i_ether_dst_mac(47 downto 40) <= data_in;
when "0110" => i_ether_src_mac( 7 downto 0) <= data_in;
when "0111" => i_ether_src_mac(15 downto 8) <= data_in;
when "1000" => i_ether_src_mac(23 downto 16) <= data_in;
when "1001" => i_ether_src_mac(31 downto 24) <= data_in;
when "1010" => i_ether_src_mac(39 downto 32) <= data_in;
when "1011" => i_ether_src_mac(47 downto 40) <= data_in;
if i_ether_dst_mac = x"FFFFFFFFFFFF" or i_ether_dst_mac = our_mac then
valid_mac <= '1';
else
valid_mac <= '0';
end if;
when "1100" => ether_type(15 downto 8) <= data_in;
when "1101" => ether_type(7 downto 0) <= data_in;
when others => if valid_mac = '1' and ether_type = filter_ether_type then
data_valid_out <= data_valid_in;
data_out <= data_in;
else
data_valid_out <= '0';
data_out <= (others => '0');
end if;
end case;
if count /= "1111" then
count <= count+1;
end if;
else
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
end if;
end if;
end process;
end Behavioral; | mit | 36b94ad79d0c2716aa9493e1c57dcd6d | 0.493958 | 4.215517 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/rtl/memc1_infrastructure.vhd | 2 | 12,268 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc1_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 2;
C_CLKOUT1_DIVIDE : integer := 2;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 4;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc1_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| cc0-1.0 | afd3eb2a8527311366e08f4f117f4274 | 0.531219 | 3.967658 | false | false | false | false |
99yen/vhdl-snake | snake.vhd | 1 | 4,143 | -- snake game
-- 99yen
-- 2014/01/14
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SNAKE is
port (
CLK : in std_logic;
RST : in std_logic;
VGA_VS, VGA_HS : out std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(3 downto 0);
PS2_KBCLK, PS2_KBDAT : in std_logic;
LED4, LED3, LED2, LED1 : out std_logic_vector(7 downto 0)
;DEBUG : out std_logic
);
end SNAKE;
architecture RTL of SNAKE is
component CLK25M
port (
CLK_IN : in std_logic;
CLK_OUT : out std_logic
);
end component;
component VGA
port (
CLK : in std_logic;
RST : in std_logic;
R_IN : in std_logic_vector(3 downto 0);
G_IN : in std_logic_vector(3 downto 0);
B_IN : in std_logic_vector(3 downto 0);
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(9 downto 0);
R_OUT : out std_logic_vector(3 downto 0);
G_OUT : out std_logic_vector(3 downto 0);
B_OUT : out std_logic_vector(3 downto 0);
BLANK_H : out std_logic;
BLANK_V : out std_logic;
HSYNC : out std_logic;
VSYNC : out std_logic
);
end component;
component PS2KEYBOARD
port (
CLK : in std_logic;
RST : in std_logic;
PS2_KBCLK, PS2_KBDAT : in std_logic;
KEYCODE : out std_logic_vector(7 downto 0);
CODE_ENABLE : out std_logic
);
end component;
component LED7SEG
port (
A : in std_logic_vector(3 downto 0);
Y : out std_logic_vector(6 downto 0)
);
end component;
component GENGRAPHIC
port (
VGA_X, VGA_Y : in std_logic_vector(9 downto 0);
TITLE : in std_logic;
SCORE : in std_logic_vector(7 downto 0);
VISIBLE : in std_logic;
MAP_X, MAP_Y : out std_logic_vector(5 downto 0);
R_OUT, G_OUT, B_OUT : out std_logic_vector(3 downto 0)
);
end component;
component GAME
port (
CLK : in std_logic;
RST : in std_logic;
BLANKING : in std_logic;
KEYCODE : in std_logic_vector(7 downto 0);
CODE_ENABLE : in std_logic;
MAP_X, MAP_Y : in std_logic_vector(5 downto 0);
TITLE : out std_logic;
SCORE : out std_logic_vector(7 downto 0);
VISIBLE : out std_logic
;DEBUG : out std_logic
);
end component;
signal CLK_VGA : std_logic;
signal X, Y : std_logic_vector(9 downto 0);
signal R_IN, G_IN, B_IN : std_logic_vector(3 downto 0);
signal R_OUT, G_OUT, B_OUT : std_logic_vector(3 downto 0);
signal BLANK_H, BLANK_V : std_logic;
signal KEYCODE : std_logic_vector(7 downto 0);
signal CODE_ENABLE : std_logic;
signal BOX_X, BOX_Y : std_logic_vector(5 downto 0);
signal CN_PULSE : std_logic;
signal LEDBUF1, LEDBUF2, LEDBUF3, LEDBUF4 : std_logic_vector(6 downto 0);
signal VISIBLE : std_logic;
signal MAP_X, MAP_Y : std_logic_vector(5 downto 0);
signal SCORE : std_logic_vector(7 downto 0);
begin
U_CLK: CLK25M
port map(CLK_IN => CLK, CLK_OUT => CLK_VGA);
U_VGA: VGA
port map(
CLK => CLK_VGA, RST => RST,
R_IN => R_OUT, G_IN => G_OUT, B_IN => B_OUT,
X => X, Y => Y,
R_OUT => VGA_R, G_OUT => VGA_G, B_OUT => VGA_B,
BLANK_H => BLANK_H, BLANK_V => BLANK_V,
HSYNC => VGA_HS, VSYNC => VGA_VS);
U_PS2: PS2KEYBOARD
port map(
CLK => CLK_VGA, RST => RST,
PS2_KBCLK => PS2_KBCLK, PS2_KBDAT => PS2_KBDAT,
KEYCODE => KEYCODE, CODE_ENABLE => CODE_ENABLE);
U_GENGRAPHIC : GENGRAPHIC
port map(
VGA_X => X, VGA_Y => Y,
TITLE => '0', SCORE => "00000000", VISIBLE => VISIBLE,
MAP_X => MAP_X, MAP_Y => MAP_Y,
R_OUT => R_OUT, G_OUT => G_OUT, B_OUT => B_OUT);
U_GAME : GAME
port map (
CLK => CLK_VGA, RST => RST,
BLANKING => BLANK_V,
KEYCODE => KEYCODE, CODE_ENABLE => CODE_ENABLE,
MAP_X => MAP_X, MAP_Y => MAP_Y,
TITLE => open, SCORE => SCORE, VISIBLE => VISIBLE, DEBUG => DEBUG);
U_LED1: LED7SEG port map(A => KEYCODE(3 downto 0), Y => LEDBUF1);
U_LED2: LED7SEG port map(A => KEYCODE(7 downto 4), Y => LEDBUF2);
U_LED3: LED7SEG port map(A => SCORE(3 downto 0), Y => LEDBUF3);
U_LED4: LED7SEG port map(A => SCORE(7 downto 4), Y => LEDBUF4);
LED1 <= not (CODE_ENABLE & LEDBUF1);
LED2 <= not ("0" & LEDBUF2);
LED3 <= not ("1" & LEDBUF3);
LED4 <= not ("0" & LEDBUF4);
end RTL;
| gpl-2.0 | 2a0a7be1565612b803635fc21d870c8f | 0.611151 | 2.560569 | false | false | false | false |
S0obi/SY23 | programmable_clock_divider/programmable_clock_divider.vhdl | 1 | 1,095 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity programmable_clock_divider is
GENERIC (
Nbits: integer := 8;
Nmax: integer := 128
);
Port ( clk : in STD_LOGIC;
clkdiv: in STD_LOGIC_VECTOR(Nbits-1 downto 0);
reset: in STD_LOGIC;
clk_out : out STD_LOGIC);
end programmable_clock_divider;
architecture behavior of programmable_clock_divider is
signal cpt : STD_LOGIC_VECTOR (Nbits-1 downto 0);
signal tmp: STD_LOGIC;
begin
clk_out <= tmp;
count: process(reset, clk)
begin
if reset = '1' then
tmp <= '0';
cpt <= (others => '0');
elsif rising_edge(clk) then
if cpt = clkdiv then
tmp <= NOT(tmp);
cpt <= (others => '0');
else
cpt <= cpt + 1;
end if;
end if;
end process count;
--remainder: process(cpt,clkdiv)
--begin
-- if cpt = clkdiv then
-- clk_out <= '1';
-- cpt <= (others => '0');
-- else
-- clk_out <= '0';
-- end if;
--end process remainder;
end behavior;
| gpl-2.0 | a1d2473e854ba721f1b10b89962e480a | 0.570776 | 3.338415 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_main_design_arp.vhd | 1 | 10,234 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_main_design_arp is
end tb_main_design_arp;
architecture Behavioral of tb_main_design_arp is
signal clk125Mhz : STD_LOGIC := '0';
signal clk125Mhz90 : STD_LOGIC := '0';
signal phy_ready : STD_LOGIC := '1';
signal status : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal input_empty : STD_LOGIC := '0';
signal input_read : STD_LOGIC := '0';
signal input_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal input_data_present : STD_LOGIC := '0';
signal input_data_error : STD_LOGIC := '0';
component main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
signal count : integer := 999;
signal count2 : integer := 180;
signal arp_src_hw : std_logic_vector(47 downto 0) := x"A0B3CC4CF9EF";
signal arp_src_ip : std_logic_vector(31 downto 0) := x"0A000001";
signal arp_tgt_hw : std_logic_vector(47 downto 0) := x"000000000000";
signal arp_tgt_ip : std_logic_vector(31 downto 0) := x"0A00000A";
constant our_mac : std_logic_vector(47 downto 0) := x"AB_89_67_45_23_02"; -- NOTE this is 02:23:45:67:89:AB
constant our_ip : std_logic_vector(31 downto 0) := x"0A_00_00_0A";
constant our_netmask : std_logic_vector(31 downto 0) := x"00_FF_FF_FF";
begin
process
begin
clk125Mhz <= '1';
wait for 2 ns;
clk125Mhz90 <= '1';
wait for 2 ns;
clk125Mhz <= '0';
wait for 2 ns;
clk125Mhz90 <= '0';
wait for 2 ns;
end process;
i_main_design: main_design generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip
) port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => status,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if count < 72 then
input_empty <= '0';
else
input_empty <= '1';
end if;
if count2 = 200000 then
count <= 0;
count2 <= 0;
else
count2 <= count2+1;
end if;
if input_read = '1' then
if count = 73 then
count <= 0;
else
count <= count + 1;
end if;
case count is
when 0 => input_data <= x"55"; input_data_present <= '1';
when 1 => input_data <= x"55";
when 2 => input_data <= x"55";
when 3 => input_data <= x"55";
when 4 => input_data <= x"55";
when 5 => input_data <= x"55";
when 6 => input_data <= x"55";
when 7 => input_data <= x"D5";
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 8 => input_data <= x"FF";
when 9 => input_data <= x"FF";
when 10 => input_data <= x"FF";
when 11 => input_data <= x"FF";
when 12 => input_data <= x"FF";
when 13 => input_data <= x"FF";
-- Source MAC address
when 14 => input_data <= x"A0";
when 15 => input_data <= x"B3";
when 16 => input_data <= x"CC";
when 17 => input_data <= x"4C";
when 18 => input_data <= x"F9";
when 19 => input_data <= x"EF";
------------------------
-- ARP packet
------------------------
when 20 => input_data <= x"08"; -- Ether Type 08:06 << ARP!
when 21 => input_data <= x"06";
when 22 => input_data <= x"00"; -- Media type
when 23 => input_data <= x"01";
when 24 => input_data <= x"08"; -- Protocol (IP)
when 25 => input_data <= x"00";
when 26 => input_data <= x"06"; -- Hardware address length
when 27 => input_data <= x"04"; -- Protocol address length
-- Operation
when 28 => input_data <= x"00";
when 29 => input_data <= x"01"; -- request
-- Target MAC
when 30 => input_data <= arp_src_hw(47 downto 40);
when 31 => input_data <= arp_src_hw(39 downto 32);
when 32 => input_data <= arp_src_hw(31 downto 24);
when 33 => input_data <= arp_src_hw(23 downto 16);
when 34 => input_data <= arp_src_hw(15 downto 8);
when 35 => input_data <= arp_src_hw( 7 downto 0);
-- Target IP
when 36 => input_data <= arp_src_ip(31 downto 24);
when 37 => input_data <= arp_src_ip(23 downto 16);
when 38 => input_data <= arp_src_ip(15 downto 8);
when 39 => input_data <= arp_src_ip( 7 downto 0);
-- Source MAC
when 40 => input_data <= arp_tgt_hw(47 downto 40);
when 41 => input_data <= arp_tgt_hw(39 downto 32);
when 42 => input_data <= arp_tgt_hw(31 downto 24);
when 43 => input_data <= arp_tgt_hw(23 downto 16);
when 44 => input_data <= arp_tgt_hw(15 downto 8);
when 45 => input_data <= arp_tgt_hw( 7 downto 0);
-- Source IP
when 46 => input_data <= arp_tgt_ip(31 downto 24);
when 47 => input_data <= arp_tgt_ip(23 downto 16);
when 48 => input_data <= arp_tgt_ip(15 downto 8);
when 49 => input_data <= arp_tgt_ip( 7 downto 0);
-- We can release the bus now and go back to the idle state.
when 50 => input_data <= x"00";
when 51 => input_data <= x"00";
when 52 => input_data <= x"00";
when 53 => input_data <= x"00";
when 54 => input_data <= x"00";
when 55 => input_data <= x"00";
when 56 => input_data <= x"00";
when 57 => input_data <= x"00";
when 58 => input_data <= x"00";
when 59 => input_data <= x"00";
when 60 => input_data <= x"00";
when 61 => input_data <= x"00";
when 62 => input_data <= x"00";
when 63 => input_data <= x"00";
when 64 => input_data <= x"00";
when 65 => input_data <= x"00";
when 66 => input_data <= x"00";
when 67 => input_data <= x"12";
when 68 => input_data <= x"12";
when 69 => input_data <= x"12";
when 70 => input_data <= x"12";
when 71 => input_data <= x"DD"; input_data_present <= '0';
when others => input_data <= x"DD"; input_data_present <= '0';
end case;
count2 <= 0;
end if;
end if;
end process;
end Behavioral;
| mit | f41d258d266808928a6f37796ac9f3e6 | 0.418409 | 4.163548 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_output/testbench/deserializer.vhd | 1 | 3,604 | --
-- Copyright (c) ARMadeus Project 2009
--
-- simulation component for SN74HC594
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : deserializer.vhd
-- Created on : 05/06/2009
-- Author : Fabien Marteau <[email protected]>
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity deserializer is
---------------------------------------------------------------------------
port
(
rclr_n : in std_logic ;
rclk : in std_logic ;
srclr_n : in std_logic ;
srclk : in std_logic ;
ser : in std_logic ;
q : out std_logic_vector(7 downto 0);
qh : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture deserializer_1 of deserializer is
---------------------------------------------------------------------------
component bascule_d
port (
d : in std_logic ;
clk : in std_logic ;
r : in std_logic ;
q : out std_logic;
q_n : out std_logic
);
end component bascule_d;
component bascule_rs
port (
r1 : in std_logic ;
r2 : in std_logic ;
clk : in std_logic ;
s : in std_logic;
q : out std_logic;
q_n : out std_logic
);
end component bascule_rs;
signal qint_n : std_logic_vector(7 downto 0);
signal qint : std_logic_vector(7 downto 0);
signal srclr : std_logic ;
signal rclr : std_logic ;
begin
srclr <= not srclr_n;
rclr <= not rclr_n;
-- bascule d
bascule_d_connect : bascule_d
port map (
d => ser,
clk => srclk,
r => srclr,
q => qint(0),
q_n => qint_n(0)
);
-- generate bascule rs input
d_g : for j in 1 to 7 generate
rs_p2 : bascule_rs
port map (
r1 => qint_n(j-1),
r2 => srclr,
clk => srclk,
s => qint(j-1),
q => qint(j),
q_n => qint_n(j)
);
end generate d_g;
-- generate bascule rs output
rs_out : for i in 0 to 7 generate
rs_p : bascule_rs
port map (
r1 => rclr,
r2 => qint_n(i),
clk => rclk,
s => qint(i),
q => q(i),
q_n => open
);
end generate rs_out;
end architecture deserializer_1;
| lgpl-2.1 | 8f9775e2397f6c580d5d9319a870601b | 0.442564 | 4.471464 | false | false | false | false |
xcthulhu/periphondemand | src/platforms/apf9328/simulation/apf_test_pkg.vhd | 1 | 5,201 | ----------------------------------------------
-- Design Name : Test bench utils
-- File Name : apf_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <[email protected]>
-- Version : 1.00
---------------------------------------------
-----------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package apf_test_pkg is
-- write procedures
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
);
-- read procedures
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
);
end package apf_test_pkg;
package body apf_test_pkg is
-- Write value from imx
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Write value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_eb3_n <= '0';
wait until falling_edge(gls_clk);
wait for 2500 ps;
imx_data <= value;
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk); -- WSC = 2
end loop;
end if;
wait for 1 ns;
imx_cs_n <= '1';
imx_eb3_n <= '1';
imx_address <= (others => 'Z');
imx_data <= (others => 'Z');
end procedure imx_write;
-- Read a value from imx
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Read value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_oe_n <= '0';
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk);
end loop;
end if;
wait until falling_edge(gls_clk);
value <= imx_data;
imx_cs_n <= '1';
imx_oe_n <= '1';
imx_address <= (others => 'Z');
wait for 20 ns;
end procedure imx_read;
end package body apf_test_pkg;
| lgpl-2.1 | ffeb3a90804f5aff6d48f93e6837e85f | 0.557393 | 3.631983 | false | false | false | false |
99yen/vhdl-snake | led7seg.vhd | 1 | 786 | library ieee;
use ieee.std_logic_1164.all;
entity LED7SEG is
port (
A : in std_logic_vector(3 downto 0);
Y : out std_logic_vector(6 downto 0)
);
end LED7SEG;
architecture RTL of LED7SEG is
begin
Y <= "0111111" when A = X"0" else
"0000110" when A = X"1" else
"1011011" when A = X"2" else
"1001111" when A = X"3" else
"1100110" when A = X"4" else
"1101101" when A = X"5" else
"1111101" when A = X"6" else
"0100111" when A = X"7" else
"1111111" when A = X"8" else
"1101111" when A = X"9" else
"1110111" when A = X"A" else
"1111100" when A = X"B" else
"0111001" when A = X"C" else
"1011110" when A = X"D" else
"1111001" when A = X"E" else
"1110001" when A = X"F" else
"1110110"; -- other
end RTL;
| gpl-2.0 | e7057a563ed9dde1b4d09da908f4886a | 0.573791 | 2.787234 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/icmp/icmp_handler.vhd | 1 | 13,340 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: icmp_handler - Behavioral
--
-- Description: For TXand RX of ICMP Ping packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity icmp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end icmp_handler;
architecture Behavioral of icmp_handler is
component ethernet_extract_header
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
filter_ether_type : in STD_LOGIC_VECTOR (15 downto 0);
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_dst_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : out STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal ether_extracted_data_valid : STD_LOGIC := '0';
signal ether_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ether_is_ipv4 : STD_LOGIC := '0';
signal ether_src_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
component ip_extract_header
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
filter_protocol : in STD_LOGIC_VECTOR (7 downto 0);
ip_version : out STD_LOGIC_VECTOR (3 downto 0);
ip_type_of_service : out STD_LOGIC_VECTOR (7 downto 0);
ip_length : out STD_LOGIC_VECTOR (15 downto 0);
ip_identification : out STD_LOGIC_VECTOR (15 downto 0);
ip_flags : out STD_LOGIC_VECTOR (2 downto 0);
ip_fragment_offset : out STD_LOGIC_VECTOR (12 downto 0);
ip_ttl : out STD_LOGIC_VECTOR (7 downto 0);
ip_checksum : out STD_LOGIC_VECTOR (15 downto 0);
ip_src_ip : out STD_LOGIC_VECTOR (31 downto 0);
ip_dest_ip : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal ip_extracted_data_valid : STD_LOGIC := '0';
signal ip_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_version : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal ip_type_of_service : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_flags : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
signal ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal ip_ttl : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_protocol : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal ip_dest_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
component icmp_extract_icmp_header
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
icmp_type : out STD_LOGIC_VECTOR (7 downto 0);
icmp_code : out STD_LOGIC_VECTOR (7 downto 0);
icmp_checksum : out STD_LOGIC_VECTOR (15 downto 0);
icmp_identifier : out STD_LOGIC_VECTOR (15 downto 0);
icmp_sequence : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal icmp_extracted_data_valid : STD_LOGIC := '0';
signal icmp_extracted_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal icmp_type : STD_LOGIC_VECTOR (7 downto 0);
signal icmp_code : STD_LOGIC_VECTOR (7 downto 0);
signal icmp_checksum : STD_LOGIC_VECTOR (15 downto 0);
signal icmp_identifier : STD_LOGIC_VECTOR (15 downto 0);
signal icmp_sequence : STD_LOGIC_VECTOR (15 downto 0);
component icmp_build_reply
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
ether_is_ipv4 : in STD_LOGIC;
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0);
ip_version : in STD_LOGIC_VECTOR (3 downto 0);
ip_type_of_service : in STD_LOGIC_VECTOR (7 downto 0);
ip_length : in STD_LOGIC_VECTOR (15 downto 0);
ip_identification : in STD_LOGIC_VECTOR (15 downto 0);
ip_flags : in STD_LOGIC_VECTOR (2 downto 0);
ip_fragment_offset : in STD_LOGIC_VECTOR (12 downto 0);
ip_ttl : in STD_LOGIC_VECTOR (7 downto 0);
ip_protocol : in STD_LOGIC_VECTOR (7 downto 0);
ip_checksum : in STD_LOGIC_VECTOR (15 downto 0);
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0);
ip_dest_ip : in STD_LOGIC_VECTOR (31 downto 0);
icmp_type : in STD_LOGIC_VECTOR (7 downto 0);
icmp_code : in STD_LOGIC_VECTOR (7 downto 0);
icmp_checksum : in STD_LOGIC_VECTOR (15 downto 0);
icmp_identifier : in STD_LOGIC_VECTOR (15 downto 0);
icmp_sequence : in STD_LOGIC_VECTOR (15 downto 0));
end component;
signal reply_data_valid : std_logic := '0';
signal reply_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
component transport_commit_buffer
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal i_packet_out_valid : std_logic := '0';
signal i_packet_out_request : std_logic := '0';
signal i_packet_out_granted : std_logic := '0';
signal i_packet_out_data : std_logic_vector(7 DOWNTO 0) := (others => '0');
begin
i_ethernet_extract_header: ethernet_extract_header generic map (
our_mac => our_mac)
port map (
clk => clk,
data_valid_in => packet_in_valid,
data_in => packet_in_data,
data_valid_out => ether_extracted_data_valid,
data_out => ether_extracted_data,
filter_ether_type => x"0800",
ether_dst_mac => open,
ether_src_mac => ether_src_mac);
i_ip_extract_header: ip_extract_header generic map (
our_ip => our_ip)
port map (
clk => clk,
data_valid_in => ether_extracted_data_valid,
data_in => ether_extracted_data,
data_valid_out => ip_extracted_data_valid,
data_out => ip_extracted_data,
filter_protocol => x"01",
ip_version => ip_version,
ip_type_of_service => ip_type_of_service,
ip_length => ip_length,
ip_identification => ip_identification,
ip_flags => ip_flags,
ip_fragment_offset => ip_fragment_offset,
ip_ttl => ip_ttl,
ip_checksum => ip_checksum,
ip_src_ip => ip_src_ip,
ip_dest_ip => ip_dest_ip);
i_icmp_extract_icmp_header : icmp_extract_icmp_header port map (
clk => clk,
data_valid_in => ip_extracted_data_valid,
data_in => ip_extracted_data,
data_valid_out => icmp_extracted_data_valid,
data_out => icmp_extracted_data,
icmp_type => icmp_type,
icmp_code => icmp_code,
icmp_checksum => icmp_checksum,
icmp_identifier => icmp_identifier,
icmp_sequence => icmp_sequence);
i_icmp_build_reply: icmp_build_reply generic map (
our_mac => our_mac,
our_ip => our_ip)
port map (
clk => clk,
data_valid_in => icmp_extracted_data_valid,
data_in => icmp_extracted_data,
data_valid_out => reply_data_valid,
data_out => reply_data,
ether_is_ipv4 => ether_is_ipv4,
ether_src_mac => ether_src_mac,
ip_version => ip_version,
ip_type_of_service => ip_type_of_service,
ip_length => ip_length,
ip_identification => ip_identification,
ip_flags => ip_flags,
ip_fragment_offset => ip_fragment_offset,
ip_ttl => ip_ttl,
ip_protocol => ip_protocol,
ip_checksum => ip_checksum,
ip_src_ip => ip_src_ip,
ip_dest_ip => ip_dest_ip,
icmp_type => icmp_type,
icmp_code => icmp_code,
icmp_checksum => icmp_checksum,
icmp_identifier => icmp_identifier,
icmp_sequence => icmp_sequence);
i_transport_commit_buffer: transport_commit_buffer port map (
clk => clk,
data_valid_in => reply_data_valid,
data_in => reply_data,
packet_out_request => i_packet_out_request,
packet_out_granted => i_packet_out_granted,
packet_out_valid => i_packet_out_valid,
packet_out_data => i_packet_out_data);
packet_out_request <= i_packet_out_request;
i_packet_out_granted <= packet_out_granted;
packet_out_valid <= i_packet_out_valid;
packet_out_data <= i_packet_out_data;
--i_ila_0: ila_0 port map (
-- clk => clk,
-- probe0(0) => reply_data_valid,
-- probe1 => reply_data,
-- probe2(0) => i_packet_out_request,
-- probe3(0) => i_packet_out_granted,
-- probe4(0) => i_packet_out_valid,
-- probe5 => i_packet_out_data);
end Behavioral;
| mit | e2ea2ca590db844cfe7161028f6589fd | 0.529085 | 3.742985 | false | false | false | false |
freecores/hilbert_transformer | vhdl/const_delay.vhd | 1 | 2,593 | -- This is the implementation of a constant delay
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
package const_delay_pkg is
component const_delay
generic(
data_width : integer;
delay_in_clks : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end const_delay_pkg;
package body const_delay_pkg is
end const_delay_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity const_delay is
generic(
data_width : integer := 16;
delay_in_clks : integer := 10
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end const_delay;
architecture const_delay_arch of const_delay is
type register_line is array(0 to delay_in_clks-1) of std_logic_vector(data_width-1 downto 0);
type data_str_line is array(0 to delay_in_clks-1) of std_logic;
signal data_int : register_line;
signal data_str_int : data_str_line;
begin
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to delay_in_clks-1 loop
data_int(i) <= (others => '0');
data_str_int(i) <= '0';
end loop;
elsif clk_i'EVENT and clk_i = '1' then
data_int(0) <= data_i;
data_str_int(0) <= data_str_i;
for i in 0 to delay_in_clks-2 loop
data_int(i+1) <= data_int(i);
data_str_int(i+1) <= data_str_int(i);
end loop;
end if;
end process;
data_o <= data_int(delay_in_clks-1);
data_str_o <= data_str_int(delay_in_clks-1);
end const_delay_arch; | gpl-3.0 | cecef0593182ac8869db7f7311190299 | 0.679907 | 3.015116 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_case_dff.vhd | 1 | 974 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
baz : out std_logic_vector(7 downto 0);
clock : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
baz <= "00101100";
case "100" is
when "000" =>
if rising_edge(clock) then
A <= '0';
end if;
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end process;
end behv;
| gpl-3.0 | 923d7ee19e33719e243a0669080582ee | 0.480493 | 3.324232 | false | false | false | false |
freecores/hilbert_transformer | vhdl/analytic_filter_h_a1.vhd | 1 | 3,609 | -- Implementation of Filter H_a1(z)
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
package analytic_filter_h_a1_pkg is
component analytic_filter_h_a1
generic(
input_data_width : integer;
output_data_width : integer;
filter_delay_in_clks : integer --delay of hilbert filter
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_str_i : in std_logic;
data_i : in std_logic_vector(input_data_width-1 downto 0);
data_i_o : out std_logic_vector(output_data_width-1 downto 0);
data_q_o : out std_logic_vector(output_data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a1_pkg;
package body analytic_filter_h_a1_pkg is
end analytic_filter_h_a1_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use work.const_delay_pkg.all;
use work.hilbert_filter_pkg.all;
entity analytic_filter_h_a1 is
generic(
input_data_width : integer := 16;
output_data_width : integer := 16;
filter_delay_in_clks : integer := 7 --delay of hilbert filter (including pipeline delay)
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_str_i : in std_logic;
data_i : in std_logic_vector(input_data_width-1 downto 0);
data_i_o : out std_logic_vector(output_data_width-1 downto 0);
data_q_o : out std_logic_vector(output_data_width-1 downto 0);
data_str_o : out std_logic
);
end analytic_filter_h_a1;
architecture analytic_filter_h_a1_arch of analytic_filter_h_a1 is
function maximum_int(
x1 : integer;
x2 : integer
) return integer is
begin
if x1 > x2 then
return x1;
else
return x2;
end if;
end maximum_int;
constant max_data_width : integer := maximum_int(input_data_width,output_data_width);
signal const_delay_data_i, const_delay_data_o : std_logic_vector(max_data_width-1 downto 0);
begin
const_delay_data_i(max_data_width-1 downto max_data_width-input_data_width) <= data_i;
zero_pad: if max_data_width-input_data_width > 0 generate
const_delay_data_i(max_data_width-input_data_width-1 downto 0) <= (others => '0');
end generate;
data_i_o <= const_delay_data_o(max_data_width-1 downto max_data_width-output_data_width);
in_phase_channel : const_delay
generic map(
data_width => max_data_width,
delay_in_clks => filter_delay_in_clks
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => const_delay_data_i,
data_str_i => data_str_i,
data_o => const_delay_data_o,
data_str_o => data_str_o
);
quadrature_phase_channel : hilbert_filter
generic map(
input_data_width => input_data_width,
output_data_width => output_data_width,
internal_data_width => max_data_width
)
port map(
clk => clk_i,
clk_enable => data_str_i,
reset => rst_i,
filter_in => data_i,
filter_out => data_q_o
);
end analytic_filter_h_a1_arch; | gpl-3.0 | 543b0f29e8c1d0391b534d64cc2d7c8d | 0.682738 | 3.012521 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/bus.vhd | 1 | 4,205 | -------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 12-May-14
-------------------------------------------------------------------------------
-- Description:
-- Data/address/control bus for simple von-Neumann MCU.
-- The bus master (CPU) can read/write in every cycle. The bus slaves are
-- assumed to have registerd read data output with an address-in to data-out
-- latency of 1 cc. The read data muxing from bus slaves to the bus master is
-- done combinationally. Thus, at the bus master interface, there results a
-- read data latency of 1 cc.
-------------------------------------------------------------------------------
-- Note on code portability:
-------------------------------------------------------------------------------
-- The address decoding logic as implemented in process P_dec below, shows how
-- to write portable code by means of a user-defined enumaration type which is
-- used as the index range for a constant array, see mcu_pkg. This allows to
-- leave the local code (in process P_dec) unchanged when the number and/or
-- base addresses of the bus slaves in the system change. Such changes then
-- need only to be made in the global definition package.
-- To generate such portable code for the rest of the functionality (e.g. for
-- the read data mux) would require to organize all data input vectors in a
-- signal array first. This would destroy the portability of the code, since it
-- requires manual code adaption when design parameter change.
-------------------------------------------------------------------------------
-- Total # of FFs: 2
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity buss is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
cpu_in : in t_cpu2bus;
cpu_out : out t_bus2cpu;
-- ROM bus signals
rom_in : in t_ros2bus;
rom_out : out t_bus2ros;
-- RAM bus signals
ram_in : in t_rws2bus;
ram_out : out t_bus2rws;
-- GPIO bus signals
gpio_in : in t_rws2bus;
gpio_out : out t_bus2rws;
-- LCD bus signals
lcd_in : in t_rws2bus;
lcd_out : out t_bus2rws
);
end buss;
architecture rtl of buss is
signal slave : std_logic_vector(AWH - 1 downto 0);
signal slave_reg : std_logic_vector(AWH - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- address decoding
-----------------------------------------------------------------------------
rom_out.addr <= cpu_in.addr(AWL-1 downto 0);
ram_out.addr <= cpu_in.addr(AWL-1 downto 0);
gpio_out.addr <= cpu_in.addr(AWL-1 downto 0);
lcd_out.addr <= cpu_in.addr(AWL-1 downto 0);
slave <= cpu_in.addr(AW-1 downto AWL);
------------------------------------------------------------------------------
-- write transfer logic
-----------------------------------------------------------------------------
ram_out.data <= cpu_in.data;
gpio_out.data <= cpu_in.data;
lcd_out.data <= cpu_in.data;
ram_out.we <= cpu_in.r_w when slave_reg = "01" else '0';
gpio_out.we <= cpu_in.r_w when slave_reg = "10" else '0';
lcd_out.we <= cpu_in.r_w when slave_reg = "11" else '0';
-----------------------------------------------------------------------------
-- read transfer logic
-----------------------------------------------------------------------------
with slave_reg select
cpu_out.data <=
rom_in.data when "00",
ram_in.data when "01",
gpio_in.data when "10",
lcd_in.data when "11",
(others => '0') when others;
-----------------------------------------------------------------------------
-- FF to buffer slave
-----------------------------------------------------------------------------
P_slave_reg: process(rst, clk) begin
if (rst = '1') then
slave_reg <= "00";
elsif (rising_edge(clk)) then
slave_reg <= slave;
end if;
end process;
end rtl;
| gpl-2.0 | 217990cab4196a2299f26f7ca24531a7 | 0.468014 | 4.326132 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp_engine/tcp_engine.vhd | 1 | 35,177 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_engine - Behavioral
--
-- Description: Implement the TCP/IP session protocol.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine is
port ( clk : in STD_LOGIC;
status : out std_logic_vector(7 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : in std_logic := '0';
tcp_rx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : in std_logic := '0';
tcp_rx_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : in std_logic := '0';
tcp_rx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : in std_logic := '0';
tcp_rx_flag_ack : in std_logic := '0';
tcp_rx_flag_psh : in std_logic := '0';
tcp_rx_flag_rst : in std_logic := '0';
tcp_rx_flag_syn : in std_logic := '0';
tcp_rx_flag_fin : in std_logic := '0';
tcp_rx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TP
tcp_tx_busy : in std_logic := '0';
tcp_tx_data_valid : out std_logic := '0';
tcp_tx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : out std_logic := '0';
tcp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : out std_logic := '0';
tcp_tx_flag_ack : out std_logic := '0';
tcp_tx_flag_psh : out std_logic := '0';
tcp_tx_flag_rst : out std_logic := '0';
tcp_tx_flag_syn : out std_logic := '0';
tcp_tx_flag_fin : out std_logic := '0';
tcp_tx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end tcp_engine;
architecture Behavioral of tcp_engine is
constant listen_port : std_logic_vector(15 downto 0) := x"0050";
component tcp_engine_session_filter is
port ( clk : in STD_LOGIC;
listen_port : in std_logic_vector(15 downto 0) := (others => '0');
drop_connection : in STD_LOGIC;
connected : out STD_LOGIC;
-- data received over TCP/IP
in_data_valid : in std_logic := '0';
in_data : in std_logic_vector(7 downto 0) := (others => '0');
in_hdr_valid : in std_logic := '0';
in_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
out_data_valid : out std_logic := '0';
out_data : out std_logic_vector(7 downto 0) := (others => '0');
out_hdr_valid : out std_logic := '0';
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_from_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_from_port : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
signal session_data_valid : std_logic := '0';
signal session_data : std_logic_vector(7 downto 0) := (others => '0');
signal session_hdr_valid : std_logic := '0';
signal session_from_ip : std_logic_vector(31 downto 0) := (others => '0');
signal session_from_port : std_logic_vector(15 downto 0) := (others => '0');
signal session_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal session_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal session_window : std_logic_vector(15 downto 0) := (others => '0');
signal session_flag_urg : std_logic := '0';
signal session_flag_ack : std_logic := '0';
signal session_flag_psh : std_logic := '0';
signal session_flag_rst : std_logic := '0';
signal session_flag_syn : std_logic := '0';
signal session_flag_fin : std_logic := '0';
signal session_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
component tcp_engine_seq_generator is
port (
clk : in std_logic;
seq : out std_logic_vector(31 downto 0) := (others => '0'));
end component;
signal random_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal send_enable : std_logic := '0';
signal send_ack : std_logic := '0';
signal send_some_data : std_logic := '0';
signal send_rst : std_logic := '0';
signal send_fin : std_logic := '0';
signal send_syn_ack : std_logic := '0';
signal send_fin_ack : std_logic := '0';
-- For sending packets
signal tosend_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tosend_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tosend_seq_num_next : std_logic_vector(31 downto 0) := (others => '0');
signal tosend_data_addr : std_logic_vector(15 downto 0) := (others => '0');
signal tosend_data_len : std_logic_vector(10 downto 0) := (others => '0');
signal tosend_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal tosend_flag_urg : std_logic := '0';
signal tosend_flag_ack : std_logic := '0';
signal tosend_flag_psh : std_logic := '0';
signal tosend_flag_rst : std_logic := '0';
signal tosend_flag_syn : std_logic := '0';
signal tosend_flag_fin : std_logic := '0';
signal tosend_window : std_logic_vector(15 downto 0) := x"2000";
type t_state is (state_dropping, state_closed, state_listen, state_syn_rcvd, state_syn_sent,
state_established, state_rx_data, state_fin_wait_1, state_fin_wait_2,
state_closing, state_time_wait, state_close_wait, state_last_ack);
signal state : t_state := state_closed;
signal last_state : t_state := state_closed;
signal timeout : std_logic := '0';
signal timeout_counter : unsigned(29 downto 0);
component tcp_engine_tx_fifo is
Port ( clk : in STD_LOGIC;
write_en : in std_logic := '0';
full : out std_logic := '0';
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_addr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_len : in std_logic_vector(10 downto 0) := (others => '0');
read_en : in std_logic := '0';
empty : out std_logic := '0';
out_src_port : out std_logic_vector(15 downto 0) := (others => '0');
out_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_addr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_len : out std_logic_vector(10 downto 0) := (others => '0'));
end component;
signal fifo_read_en : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_hdr_valid : std_logic := '0';
signal fifo_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal fifo_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal fifo_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_window : std_logic_vector(15 downto 0) := (others => '0');
signal fifo_flag_urg : std_logic := '0';
signal fifo_flag_ack : std_logic := '0';
signal fifo_flag_psh : std_logic := '0';
signal fifo_flag_rst : std_logic := '0';
signal fifo_flag_syn : std_logic := '0';
signal fifo_flag_fin : std_logic := '0';
signal fifo_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal fifo_data_addr : std_logic_vector(15 downto 0) := (others => '0');
signal fifo_data_len : std_logic_vector(10 downto 0) := (others => '0');
component tcp_engine_add_data is
Port ( clk : in STD_LOGIC;
read_en : out std_logic := '0';
empty : in std_logic := '0';
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_addr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_len : in std_logic_vector(10 downto 0) := (others => '0');
out_hdr_valid : out std_logic := '0';
out_src_port : out std_logic_vector(15 downto 0) := (others => '0');
out_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_valid : out std_logic := '0';
out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
COMPONENT ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT ;
signal session_connected : std_logic := '0';
signal drop_connection : std_logic := '0';
begin
process(clK)
begin
if rising_edge(clk) then
case state is
when state_dropping => status <= x"01";
when state_closed => status <= x"02";
when state_listen => status <= x"03";
when state_syn_rcvd => status <= x"04";
when state_syn_sent => status <= x"05";
when state_established => status <= x"06";
when state_rx_data => status <= x"07";
when state_fin_wait_1 => status <= x"08";
when state_fin_wait_2 => status <= x"09";
when state_closing => status <= x"0A";
when state_time_wait => status <= x"0B";
when state_close_wait => status <= x"0C";
when state_last_ack => status <= x"0D";
when others => status <= x"FF";
end case;
status(7) <= session_connected;
end if;
end process;
--debug : ila_0
-- PORT MAP (
-- clk => clk,
-- probe0(0) => session_hdr_valid,
-- probe1 => session_data,
-- probe2(0) => session_data_valid,
-- probe3(0) => session_flag_ack,
-- probe4(0) => session_flag_fin,
-- probe5 => fifo_data_len(7 downto 0));
i_tcp_engine_seq_generator: tcp_engine_seq_generator port map (
clk => clk,
seq => random_seq_num);
timeout_proc: process(clk)
begin
if rising_edge(clk) then
timeout <= '0';
if last_state /= state then
timeout_counter <= to_unsigned(5*125_000_000,30); -- 5 seconds
timeout <= '0';
elsif timeout_counter = 0 then
timeout <= '1';
else
if state = state_syn_rcvd then
timeout_counter <= timeout_counter - 1;
end if;
end if;
last_state <= state;
end if;
end process;
i_tcp_engine_session_filter: tcp_engine_session_filter port map (
clk => clk,
listen_port => listen_port,
drop_connection => drop_connection,
connected => session_connected,
in_data_valid => tcp_rx_data_valid,
in_data => tcp_rx_data,
in_hdr_valid => tcp_rx_hdr_valid,
in_src_ip => tcp_rx_src_ip,
in_src_port => tcp_rx_src_port,
in_dst_port => tcp_rx_dst_port,
in_seq_num => tcp_rx_seq_num,
in_ack_num => tcp_rx_ack_num,
in_window => tcp_rx_window,
in_flag_urg => tcp_rx_flag_urg,
in_flag_ack => tcp_rx_flag_ack,
in_flag_psh => tcp_rx_flag_psh,
in_flag_rst => tcp_rx_flag_rst,
in_flag_syn => tcp_rx_flag_syn,
in_flag_fin => tcp_rx_flag_fin,
in_urgent_ptr => tcp_rx_urgent_ptr,
out_data_valid => session_data_valid,
out_data => session_data,
out_hdr_valid => session_hdr_valid,
out_from_ip => session_from_ip,
out_from_port => session_from_port,
out_seq_num => session_seq_num,
out_ack_num => session_ack_num,
out_window => session_window,
out_flag_urg => session_flag_urg,
out_flag_ack => session_flag_ack,
out_flag_psh => session_flag_psh,
out_flag_rst => session_flag_rst,
out_flag_syn => session_flag_syn,
out_flag_fin => session_flag_fin,
out_urgent_ptr => session_urgent_ptr);
process(clk)
begin
if rising_edge(clk) then
drop_connection <= '0';
send_ack <= '0';
send_rst <= '0';
send_fin <= '0';
send_fin_ack <= '0';
send_syn_ack <= '0';
send_some_data <= '0';
case state is
when state_dropping =>
drop_connection <= '1';
state <= state_closed;
when state_closed =>
-- Passive open
if session_connected = '0' then
state <= state_listen;
end if;
when state_listen =>
-- Is this a SYN packet
if session_connected = '1' then
send_syn_ack <='1';
tosend_ack_num <= std_logic_vector(unsigned(session_seq_num) + 1);
state <= state_syn_rcvd;
end if;
when state_syn_rcvd =>
if session_hdr_valid = '1' then
if session_flag_syn = '1' then
-- We are seeing a retransmit of the SYN packet
tosend_ack_num <= std_logic_vector(unsigned(session_seq_num) + 1);
send_syn_ack <='1';
elsif session_flag_ack = '1' then
-- We are getting the ACK from the other end
if unsigned(session_ack_num) = unsigned(tosend_seq_num)+1 then
state <= state_established;
end if;
end if;
elsif timeout = '1' then
-- We haven't seen an ACK
send_rst <= '1';
state <= state_closing;
end if;
when state_syn_sent =>
-- This is only used for active opens, so we don't use it.
NULL;
when state_established =>
if session_hdr_valid = '1' then
if session_flag_ack = '1' then
if session_ack_num = tosend_seq_num then
if session_data_valid = '1' then
tosend_ack_num <= std_logic_vector(unsigned(tosend_ack_num) + 1);
state <= state_rx_data;
elsif session_flag_fin = '1' then
send_fin_ack <= '1';
tosend_ack_num <= std_logic_vector(unsigned(tosend_ack_num) + 1);
state <= state_fin_wait_1;
end if;
end if;
end if;
end if;
when state_rx_data =>
-- Receive a byte, and when finished send an ACK and wait for more.
if session_data_valid = '1' then
tosend_ack_num <= std_logic_vector(unsigned(tosend_ack_num) + 1);
else
send_ack <= '1';
send_some_data <= '1';
-- Send with the sequence we have acked up to
state <= state_established;
end if;
when state_fin_wait_1 =>
if session_hdr_valid = '1' then
if session_ack_num = tosend_seq_num then
if session_flag_ack = '1' and session_flag_fin = '1' then
send_ack <='1';
end if;
elsif unsigned(session_ack_num) = unsigned(tosend_seq_num)+1 then
tosend_seq_num <= std_logic_vector(unsigned(tosend_seq_num) + 1);
tosend_seq_num_next <= std_logic_vector(unsigned(tosend_seq_num) + 1);
if session_flag_ack = '1' and session_flag_fin = '1' then
-- If we get a FIN+ACK we can send an ACK and straight to time_wait
send_ack <='1';
state <= state_time_wait;
elsif session_flag_ack = '1' then
send_ack <='1';
state <= state_fin_wait_2;
elsif session_flag_fin = '1' then
send_ack <='1';
state <= state_fin_wait_2;
end if;
end if;
end if;
when state_fin_wait_2 =>
if session_hdr_valid = '1' then
if session_ack_num = tosend_seq_num then
if session_flag_fin = '1' then
send_ack <='1';
state <= state_time_wait;
end if;
end if;
end if;
when state_closing =>
if tcp_rx_hdr_valid = '1' then
if session_ack_num = tosend_seq_num then
if tcp_rx_flag_ack = '1' then
state <= state_time_wait;
end if;
end if;
end if;
when state_time_wait =>
if timeout = '1' then
state <= state_closing;
end if;
when state_close_wait =>
send_fin <= '1';
state <= state_last_ack;
when state_last_ack =>
if tcp_rx_hdr_valid = '1' then
if session_ack_num = tosend_seq_num then
if tcp_rx_flag_ack = '1' then
state <= state_dropping;
end if;
end if;
end if;
end case;
end if;
end process;
send_packets: process(clk)
begin
if rising_edge(clk) then
-------------------------------------------------------------
-- Update the sequence number if a packet was sent last cycle
-------------------------------------------------------------
tosend_seq_num <= tosend_seq_num_next;
-------------------------------------------------
-- This block is to set up the initial sequence
-- numbers during the initial three-way handshake
-------------------------------------------------
if state = state_listen then
if session_connected = '1' then
tosend_seq_num <= random_seq_num;
tosend_seq_num_next <= random_seq_num;
end if;
elsif state = state_syn_rcvd then
if session_hdr_valid = '1' then
if session_flag_syn = '0' and session_flag_ack = '1' then
-- We are seing a ACK with the correct sequence number
if unsigned(session_ack_num) = unsigned(tosend_seq_num) + 1 then
tosend_seq_num <= std_logic_vector(unsigned(tosend_seq_num) + 1);
tosend_seq_num_next <= std_logic_vector(unsigned(tosend_seq_num) + 1);
end if;
end if;
end if;
end if;
-------------------------------------------------
-- Sending out packets
-------------------------------------------------
send_enable <= '0';
if send_ack = '1' then
send_enable <= '1';
-- Send a few bytes of data with every ACK
tosend_data_addr <= (others => '0');
if send_some_data = '1' then
tosend_data_len <= "00000010000";
tosend_seq_num_next <= std_logic_vector(unsigned(tosend_seq_num)+16);
else
tosend_data_len <= (others => '0');
end if;
tosend_flag_urg <= '0';
tosend_flag_ack <= '1';
tosend_flag_psh <= '0';
tosend_flag_rst <= '0';
tosend_flag_syn <= '0';
tosend_flag_fin <= '0';
elsif send_syn_ack = '1' then
send_enable <= '1';
tosend_data_addr <= (others => '0');
tosend_data_len <= (others => '0');
tosend_flag_urg <= '0';
tosend_flag_ack <= '1';
tosend_flag_psh <= '0';
tosend_flag_rst <= '0';
tosend_flag_syn <= '1';
tosend_flag_fin <= '0';
elsif send_fin_ack = '1' then
send_enable <= '1';
tosend_data_addr <= (others => '0');
tosend_data_len <= (others => '0');
tosend_flag_urg <= '0';
tosend_flag_ack <= '1';
tosend_flag_psh <= '0';
tosend_flag_rst <= '0';
tosend_flag_syn <= '0';
tosend_flag_fin <= '1';
elsif send_fin = '1' then
send_enable <= '1';
tosend_data_addr <= (others => '0');
tosend_data_len <= (others => '0');
tosend_flag_urg <= '0';
tosend_flag_ack <= '0';
tosend_flag_psh <= '0';
tosend_flag_rst <= '0';
tosend_flag_syn <= '0';
tosend_flag_fin <= '1';
elsif send_rst = '1' then
send_enable <= '1';
tosend_data_addr <= (others => '0');
tosend_data_len <= (others => '0');
tosend_flag_urg <= '0';
tosend_flag_ack <= '0';
tosend_flag_psh <= '0';
tosend_flag_rst <= '1';
tosend_flag_syn <= '0';
tosend_flag_fin <= '0';
tosend_seq_num <= (others => '0');
tosend_seq_num_next <= (others => '0');
end if;
end if;
end process;
i_tcp_engine_tx_fifo: tcp_engine_tx_fifo port map (
clk => clk,
write_en => send_enable,
full => open,
in_src_port => listen_port,
in_dst_ip => session_from_ip,
in_dst_port => session_from_port,
in_seq_num => tosend_seq_num,
in_ack_num => tosend_ack_num,
in_window => tosend_window,
in_flag_urg => tosend_flag_urg,
in_flag_ack => tosend_flag_ack,
in_flag_psh => tosend_flag_psh,
in_flag_rst => tosend_flag_rst,
in_flag_syn => tosend_flag_syn,
in_flag_fin => tosend_flag_fin,
in_urgent_ptr => tosend_urgent_ptr,
in_data_addr => tosend_data_addr,
in_data_len => tosend_data_len,
read_en => fifo_read_en,
empty => fifo_empty,
out_src_port => fifo_src_port,
out_dst_ip => fifo_dst_ip,
out_dst_port => fifo_dst_port,
out_seq_num => fifo_seq_num,
out_ack_num => fifo_ack_num,
out_window => fifo_window,
out_flag_urg => fifo_flag_urg,
out_flag_ack => fifo_flag_ack,
out_flag_psh => fifo_flag_psh,
out_flag_rst => fifo_flag_rst,
out_flag_syn => fifo_flag_syn,
out_flag_fin => fifo_flag_fin,
out_urgent_ptr => fifo_urgent_ptr,
out_data_addr => fifo_data_addr,
out_data_len => fifo_data_len);
i_tcp_engine_add_data: tcp_engine_add_data port map (
clk => clk,
read_en => fifo_read_en,
empty => fifo_empty,
in_src_port => fifo_src_port,
in_dst_ip => fifo_dst_ip,
in_dst_port => fifo_dst_port,
in_seq_num => fifo_seq_num,
in_ack_num => fifo_ack_num,
in_window => fifo_window,
in_flag_urg => fifo_flag_urg,
in_flag_ack => fifo_flag_ack,
in_flag_psh => fifo_flag_psh,
in_flag_rst => fifo_flag_rst,
in_flag_syn => fifo_flag_syn,
in_flag_fin => fifo_flag_fin,
in_urgent_ptr => fifo_urgent_ptr,
in_data_addr => fifo_data_addr,
in_data_len => fifo_data_len,
out_hdr_valid => tcp_tx_hdr_valid,
out_src_port => tcp_tx_src_port,
out_dst_ip => tcp_tx_dst_ip,
out_dst_port => tcp_tx_dst_port,
out_seq_num => tcp_tx_seq_num,
out_ack_num => tcp_tx_ack_num,
out_window => tcp_tx_window,
out_flag_urg => tcp_tx_flag_urg,
out_flag_ack => tcp_tx_flag_ack,
out_flag_psh => tcp_tx_flag_psh,
out_flag_rst => tcp_tx_flag_rst,
out_flag_syn => tcp_tx_flag_syn,
out_flag_fin => tcp_tx_flag_fin,
out_urgent_ptr => tcp_tx_urgent_ptr,
out_data => tcp_tx_data,
out_data_valid => tcp_tx_data_valid);
end Behavioral; | mit | 050bf5f9306b0ca0e7e3e45c8d373980 | 0.441169 | 3.849951 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/avnet_s3dev1500/clock/top.vhdl | 1 | 1,652 | --
-- Clocks on s3dev1500
--
-- There are four clock sources on s6micro board:
-- * 3 are user programmable. Default values:
-- * 1 Optional user installable (not installed)
-- They are used to blink user leds.
-- The clock of 66 MHz is used to blink LEDs 0.
-- The clock of HEADER is used to blink LEDs 1.
-- The clock of 100 MHz is used to blink LEDs 2.
-- The clock of 40 MHz is used to blink LEDs 3.
-- SW1 push-button is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
-- * Bruno valinoti
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk2_i : in std_logic;
clk3_i : in std_logic;
clk4_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
signal led0, led1, led2, led3 : std_logic;
begin
blink40prog_inst: Blink
generic map (FREQUENCY => 66666e3)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led0);
blink66prog_inst: Blink
generic map (FREQUENCY => 66700e3)
port map(clk_i => clk2_i, rst_i => rst_i, blink_o => led1);
blink100prog_inst: Blink
generic map (FREQUENCY => 100e6)
port map(clk_i => clk3_i, rst_i => rst_i, blink_o => led2);
blink66fixed_inst: Blink
generic map (FREQUENCY => 40e6)
port map(clk_i => clk4_i, rst_i => rst_i, blink_o => led3);
leds_o <= led3 & led2 & led1 & led0;
end architecture RTL;
| bsd-3-clause | 86cc064ebcbbef8e4134023c43d0a89b | 0.646489 | 2.992754 | false | false | false | false |
freecores/hilbert_transformer | vhdl/fsf_pole_filter.vhd | 1 | 4,893 | -- pole filter implementation for frequency sampling filers (FSF)
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition of fsf_pole_filter_coeff_array_type
library ieee;
use ieee.std_logic_1164.all;
package fsf_pole_filter_coeff_def_pkg is
type fsf_pole_filter_coeff_array_type is array(0 to 5) of integer range -1 to 1;
constant c_0_coeff : fsf_pole_filter_coeff_array_type := (-1,0,0,0,0,0);
constant c_180_coeff : fsf_pole_filter_coeff_array_type := (1,0,0,0,0,0);
constant c_120_coeff : fsf_pole_filter_coeff_array_type := (1,1,0,0,0,0);
constant c_90_coeff : fsf_pole_filter_coeff_array_type := (0,1,0,0,0,0);
constant c_60_coeff : fsf_pole_filter_coeff_array_type := (-1,1,0,0,0,0);
constant c_0_180_coeff : fsf_pole_filter_coeff_array_type := (0,-1,0,0,0,0);
constant c_0_90_coeff : fsf_pole_filter_coeff_array_type := (-1,1,-1,0,0,0);
constant c_0_120_coeff : fsf_pole_filter_coeff_array_type := (0,0,-1,0,0,0);
constant c_180_60_coeff : fsf_pole_filter_coeff_array_type := (0,0,1,0,0,0);
constant c_180_90_coeff : fsf_pole_filter_coeff_array_type := (1,1,1,0,0,0);
--and in meyer-baese syntax:
constant c_1_coeff : fsf_pole_filter_coeff_array_type := c_0_coeff;
constant c_2_coeff : fsf_pole_filter_coeff_array_type := c_180_coeff;
constant c_3_coeff : fsf_pole_filter_coeff_array_type := c_120_coeff;
constant c_4_coeff : fsf_pole_filter_coeff_array_type := c_90_coeff;
constant c_6_coeff : fsf_pole_filter_coeff_array_type := c_60_coeff;
end fsf_pole_filter_coeff_def_pkg;
package body fsf_pole_filter_coeff_def_pkg is
end fsf_pole_filter_coeff_def_pkg;
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
package fsf_pole_filter_pkg is
component fsf_pole_filter
generic(
data_width : integer;
no_of_coefficients : integer; --must be in the range 1..6
coeff : fsf_pole_filter_coeff_array_type
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end fsf_pole_filter_pkg;
package body fsf_pole_filter_pkg is
end fsf_pole_filter_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
entity fsf_pole_filter is
generic(
data_width : integer;
no_of_coefficients : integer; --must be in the range 1..6
coeff : fsf_pole_filter_coeff_array_type
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end fsf_pole_filter;
architecture fsf_pole_filter_arch of fsf_pole_filter is
signal y : std_logic_vector (data_width-1 downto 0);
signal x : std_logic_vector (data_width-1 downto 0);
type signal_chain_array_type is array (0 to no_of_coefficients-1) of std_logic_vector (data_width-1 downto 0);
signal t : signal_chain_array_type;
signal td : signal_chain_array_type;
begin
data_o <= y;
x <= data_i;
y <= td(no_of_coefficients-1);
t(0) <= conv_std_logic_vector(conv_integer(x) + (((-1)*coeff(no_of_coefficients-1)) * conv_integer(y)),data_width);
next_adder_decision : if no_of_coefficients > 1 generate
next_adder : for i in 1 to no_of_coefficients-1 generate
t(i) <= conv_std_logic_vector(conv_integer(td(i-1)) + (((-1)*coeff(no_of_coefficients-i-1))*conv_integer(y)),data_width);
end generate;
end generate;
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to no_of_coefficients-1 loop
td(i) <= (others => '0');
end loop;
data_str_o <= '0';
elsif clk_i'EVENT and clk_i = '1' then
if data_str_i='1' then
data_str_o <= '1';
for i in 0 to no_of_coefficients-1 loop
td(i) <= t(i);
end loop;
else
data_str_o <= '0';
end if;
end if;
end process;
end fsf_pole_filter_arch; | gpl-3.0 | 05a8be205319ad81f60cbc9f036764e4 | 0.668915 | 2.800801 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | shared/vivado_repo/AXIF_MASTER_DPRAM/AXIF_MASTER_DPRAM_M_AXIF.vhdl | 1 | 16,109 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIF_MASTER_DPRAM_M_AXIF is
generic (
C_NO_WRITE_RESPONSE : boolean:= FALSE;
C_AxCACHE : std_logic_vector(3 downto 0) := "0010";
--
C_M_AXI_ID_WIDTH : integer:= 1;
C_M_AXI_ADDR_WIDTH : integer:= 32;
C_M_AXI_DATA_WIDTH : integer:= 32;
C_M_AXI_AWUSER_WIDTH : integer:= 0;
C_M_AXI_ARUSER_WIDTH : integer:= 0;
C_M_AXI_WUSER_WIDTH : integer:= 0;
C_M_AXI_RUSER_WIDTH : integer:= 0;
C_M_AXI_BUSER_WIDTH : integer:= 0
);
port (
start_i : in std_logic;
length_i : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
rd_addr_i : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
wr_addr_i : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
busy_o : out std_logic;
--
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end AXIF_MASTER_DPRAM_M_AXIF;
architecture implementation of AXIF_MASTER_DPRAM_M_AXIF is
constant C_M_AXI_BURST_LEN : natural := 16;
constant C_BURST_BYTES : natural := C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8;
type state_t is ( IDLE, INIT_WRITE, INIT_READ);
signal rd_state, wr_state : state_t;
signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awvalid : std_logic;
signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_bready : std_logic;
signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arvalid : std_logic;
signal axi_rready : std_logic;
signal wr_cnt, rd_cnt : unsigned(3 downto 0);
signal wr_burst_cnt, rd_burst_cnt : unsigned(31 downto 0);
signal wr_burst_start, rd_burst_start : std_logic;
signal wr_done, rd_done : std_logic;
signal wr_burst_active, rd_burst_active : std_logic;
signal wr_next, rd_next : std_logic;
signal burst_length : unsigned(31 downto 0);
-- RAM
type ram_type is array(0 to 63) of std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
signal ram : ram_type;
signal ram_rd_addr, ram_wr_addr : unsigned(5 downto 0);
begin
burst_length <= unsigned(length_i) / C_M_AXI_BURST_LEN;
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= std_logic_vector(unsigned(wr_addr_i) + unsigned(axi_awaddr));
M_AXI_AWLEN <= std_logic_vector(to_unsigned(C_M_AXI_BURST_LEN-1,8));
M_AXI_AWSIZE <= std_logic_vector(to_unsigned(2,3));
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= C_AxCACHE;
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= (others => '1');
M_AXI_AWVALID <= axi_awvalid;
M_AXI_WDATA <= axi_wdata;
M_AXI_WSTRB <= (others => '1');
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (others => '0');
M_AXI_WVALID <= axi_wvalid;
M_AXI_BREADY <= axi_bready;
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= std_logic_vector(unsigned(rd_addr_i) + unsigned(axi_araddr));
M_AXI_ARLEN <= std_logic_vector(to_unsigned(C_M_AXI_BURST_LEN-1,8));
M_AXI_ARSIZE <= std_logic_vector(to_unsigned(2,3));
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= C_AxCACHE;
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= (others => '1');
M_AXI_ARVALID <= axi_arvalid;
M_AXI_RREADY <= axi_rready;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_awvalid <= '0';
else
if axi_awvalid = '0' and wr_burst_start = '1' then
axi_awvalid <= '1';
elsif M_AXI_AWREADY = '1' and axi_awvalid = '1' then
axi_awvalid <= '0';
else
axi_awvalid <= axi_awvalid;
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_awaddr <= (others => '0');
else
if M_AXI_AWREADY= '1' and axi_awvalid = '1' then
axi_awaddr <= std_logic_vector(unsigned(axi_awaddr) + C_BURST_BYTES);
end if;
end if;
end if;
end process;
wr_next <= M_AXI_WREADY and axi_wvalid;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_wvalid <= '0';
else
if axi_wvalid = '0' and wr_burst_start = '1' then
axi_wvalid <= '1';
elsif wr_next = '1' and axi_wlast = '1' then
axi_wvalid <= '0';
else
axi_wvalid <= axi_wvalid;
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_wlast <= '0';
else
if ((wr_cnt = C_M_AXI_BURST_LEN-2 and C_M_AXI_BURST_LEN >= 2) and wr_next = '1') or (C_M_AXI_BURST_LEN = 1) then
axi_wlast <= '1';
elsif wr_next = '1' then
axi_wlast <= '0';
elsif axi_wlast = '1' and C_M_AXI_BURST_LEN = 1 then
axi_wlast <= '0';
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or wr_burst_start = '1' or start_i = '1' then
wr_cnt <= (others => '0');
else
if wr_next = '1' and (wr_cnt < C_M_AXI_BURST_LEN) then
wr_cnt <= wr_cnt + 1;
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_bready <= '0';
else
if C_NO_WRITE_RESPONSE then
axi_bready <= '1';
else
if M_AXI_BVALID = '1' and axi_bready = '0' then
axi_bready <= '1';
elsif axi_bready = '1' then
axi_bready <= '0';
end if;
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_arvalid <= '0';
else
if axi_arvalid = '0' and rd_burst_start = '1' then
axi_arvalid <= '1';
elsif M_AXI_ARREADY = '1' and axi_arvalid = '1' then
axi_arvalid <= '0';
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_araddr <= (others => '0');
else
if M_AXI_ARREADY = '1' and axi_arvalid = '1' then
axi_araddr <= std_logic_vector(unsigned(axi_araddr) + C_BURST_BYTES);
end if;
end if;
end if;
end process;
rd_next <= M_AXI_RVALID and axi_rready;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or rd_burst_start = '1' or start_i = '1' then
rd_cnt <= (others => '0');
else
if (rd_next = '1' and rd_cnt < C_M_AXI_BURST_LEN) then
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
axi_rready <= '0';
else
if M_AXI_RVALID = '1' then
if M_AXI_RLAST = '1' and axi_rready = '1' then
axi_rready <= '0';
else
axi_rready <= '1';
end if;
end if;
end if;
end if;
end process;
-- Application
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
wr_burst_cnt <= (others => '0');
else
if M_AXI_AWREADY = '1' and axi_awvalid = '1' then
if wr_burst_cnt < burst_length then
wr_burst_cnt <= wr_burst_cnt + 1;
end if;
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
rd_burst_cnt <= (others => '0');
else
if M_AXI_ARREADY = '1' and axi_arvalid = '1' then
if rd_burst_cnt < burst_length then
rd_burst_cnt <= rd_burst_cnt + 1;
end if;
end if;
end if;
end if;
end process;
busy_o <= '1' when wr_state /= IDLE else '0';
read_proc : process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
rd_state <= IDLE;
rd_burst_start <= '0';
else
case rd_state is
when IDLE =>
if start_i = '1' then
rd_state <= INIT_READ;
end if;
when INIT_READ =>
if rd_done = '1' then
rd_state <= IDLE;
else
if axi_arvalid = '0' and rd_burst_active = '0' and rd_burst_start = '0' then
rd_burst_start <= '1';
else
rd_burst_start <= '0';
end if;
end if;
when others =>
rd_state <= IDLE;
end case;
end if;
end if;
end process;
write_proc : process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' then
wr_state <= IDLE;
wr_burst_start <= '0';
else
case wr_state is
when IDLE =>
if start_i = '1' then
wr_state <= INIT_READ;
end if;
when INIT_READ =>
if ram_rd_addr > 15 then
wr_state <= INIT_WRITE;
end if;
when INIT_WRITE =>
if wr_done = '1' then
wr_state <= IDLE;
else
if ram_rd_addr-ram_wr_addr > 15 or ram_rd_addr < ram_wr_addr then
if axi_awvalid = '0' and wr_burst_start = '0' and wr_burst_active = '0' then
wr_burst_start <= '1';
else
wr_burst_start <= '0';
end if;
end if;
end if;
when others =>
wr_state <= IDLE;
end case;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
wr_burst_active <= '0';
else
if wr_burst_start = '1' then
wr_burst_active <= '1';
elsif ((M_AXI_BVALID = '1' and not(C_NO_WRITE_RESPONSE)) or (axi_wlast = '1' and C_NO_WRITE_RESPONSE)) and axi_bready = '1' then
wr_burst_active <= '0';
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
wr_done <= '0';
else
if ((M_AXI_BVALID = '1' and not(C_NO_WRITE_RESPONSE)) or (axi_wlast = '1' and C_NO_WRITE_RESPONSE)) and wr_burst_cnt = burst_length and axi_bready = '1' then
wr_done <= '1';
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
rd_burst_active <= '0';
else
if rd_burst_start = '1'then
rd_burst_active <= '1';
elsif M_AXI_RVALID = '1' and axi_rready = '1' and M_AXI_RLAST = '1' then
rd_burst_active <= '0';
end if;
end if;
end if;
end process;
process(M_AXI_ACLK)
begin
if rising_edge (M_AXI_ACLK) then
if M_AXI_ARESETN = '0' or start_i = '1' then
rd_done <= '0';
else
if M_AXI_RVALID = '1' and axi_rready = '1' and (rd_cnt = (C_M_AXI_BURST_LEN-1)) and rd_burst_cnt = burst_length then
rd_done <= '1';
end if;
end if;
end if;
end process;
-- The Dual-Port RAM
read_p:
process (M_AXI_ACLK)
--variable aux : unsigned(31 downto 0);
begin
if rising_edge(M_AXI_ACLK) then
if (M_AXI_ARESETN = '0' or start_i = '1') then
ram_rd_addr <= (others => '0');
--aux := (others => '0');
else
if rd_next='1' then
--ram(to_integer(ram_rd_addr)) <= std_logic_vector(aux);
--aux := aux + 1;
ram(to_integer(ram_rd_addr)) <= M_AXI_RDATA;
ram_rd_addr <= ram_rd_addr + 1;
end if;
end if;
end if;
end process read_p;
write_p:
process (M_AXI_ACLK)
--variable aux : unsigned(31 downto 0);
begin
if rising_edge(M_AXI_ACLK) then
if (M_AXI_ARESETN = '0' or start_i = '1') then
ram_wr_addr <= (others => '0');
--aux := (others => '0');
else
if wr_next='1' then
axi_wdata <= ram(to_integer(ram_wr_addr));
--aux := aux + 1;
ram_wr_addr <= ram_wr_addr + 1;
end if;
end if;
end if;
end process write_p;
end implementation; | bsd-3-clause | aaa6f67103ce21e351ecfdcb43cf4e99 | 0.511267 | 3.164833 | false | false | false | false |
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