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AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/synth/design_1_dlmb_bram_if_cntlr_0.vhd
| 2 | 13,327 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_dlmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_dlmb_bram_if_cntlr_0;
ARCHITECTURE design_1_dlmb_bram_if_cntlr_0_arch OF design_1_dlmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dlmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x40000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"40000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_dlmb_bram_if_cntlr_0_arch;
|
gpl-3.0
|
9071ed449b4fcc112e53a06324ce7a7d
| 0.661514 | 3.148358 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/fwft_fifo.vhd
| 2 | 6,603 |
-------------------------------------------------------------------------------
--! @file fwft_fifo.vhd
--! @brief First-Word-Fall-Through FIFO
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! @ref This code is based on the fwft_fifo by
--! http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fwft_fifo is
generic (
G_W : integer := 64; --! Width of I/O (bits)
G_LOG2DEPTH : integer := 9; --! LOG(2) of depth
G_ASYNC_RSTN : boolean := False --! Async reset active low
);
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(G_W -1 downto 0);
din_valid : in std_logic;
din_ready : out std_logic;
dout : out std_logic_vector(G_W -1 downto 0);
dout_valid : out std_logic;
dout_ready : in std_logic
);
end fwft_fifo;
architecture structure of fwft_fifo is
type t_mem is array (2**G_LOG2DEPTH-1 downto 0)
of std_logic_vector(G_W-1 downto 0);
signal iready : std_logic;
signal ovalid : std_logic;
begin
din_ready <= iready;
dout_valid <= ovalid;
gSync:
if (not G_ASYNC_RSTN) generate
process(clk)
variable memory : t_mem;
variable wrptr : std_logic_vector(G_LOG2DEPTH -1 downto 0);
variable rdptr : std_logic_vector(G_LOG2DEPTH -1 downto 0);
variable looped : boolean;
begin
if rising_edge(clk) then
if (rst = '1') then
wrptr := (others => '0');
rdptr := (others => '0');
looped := False;
iready <= '1';
ovalid <= '0';
else
if (dout_ready = '1' and ovalid = '1') then
if ((looped = True) or (wrptr /= rdptr)) then
if (unsigned(rdptr) = 2**G_LOG2DEPTH-1) then
looped := False;
end if;
rdptr := std_logic_vector(unsigned(rdptr) + 1);
end if;
end if;
if (din_valid = '1' and iready = '1') then
if ((looped = False) or (wrptr /= rdptr)) then
memory(to_integer(unsigned(wrptr))) := din;
if (unsigned(wrptr) = 2**G_LOG2DEPTH-1) then
looped := True;
end if;
wrptr := std_logic_vector(unsigned(wrptr) + 1);
end if;
end if;
dout <= memory(to_integer(unsigned(rdptr)));
--! Update flags
if (wrptr = rdptr) then
if (looped) then
iready <= '0';
else
ovalid <= '0';
end if;
else
iready <= '1';
ovalid <= '1';
end if;
end if;
end if;
end process;
end generate;
gAsync:
if (G_ASYNC_RSTN) generate
process(clk, rst)
variable memory : t_mem;
variable wrptr : std_logic_vector(G_LOG2DEPTH -1 downto 0);
variable rdptr : std_logic_vector(G_LOG2DEPTH -1 downto 0);
variable looped : boolean;
begin
if (rst = '0') then
wrptr := (others => '0');
rdptr := (others => '0');
looped := False;
iready <= '1';
ovalid <= '0';
elsif rising_edge(clk) then
if (dout_ready = '1' and ovalid = '1') then
if ((looped = True) or (wrptr /= rdptr)) then
if (unsigned(rdptr) = 2**G_LOG2DEPTH-1) then
looped := False;
end if;
rdptr := std_logic_vector(unsigned(rdptr) + 1);
end if;
end if;
if (din_valid = '1' and iready = '1') then
if ((looped = False) or (wrptr /= rdptr)) then
memory(to_integer(unsigned(wrptr))) := din;
if (unsigned(wrptr) = 2**G_LOG2DEPTH-1) then
looped := True;
end if;
wrptr := std_logic_vector(unsigned(wrptr) + 1);
end if;
end if;
dout <= memory(to_integer(unsigned(rdptr)));
--! Update flags
if (wrptr = rdptr) then
if (looped) then
iready <= '0';
else
ovalid <= '0';
end if;
else
iready <= '1';
ovalid <= '1';
end if;
end if;
end process;
end generate;
end architecture structure;
|
apache-2.0
|
1f2b08d8e36837b16ea320b881ee73ec
| 0.389941 | 5.004549 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sources_1/new/topmodule.vhd
| 1 | 24,544 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.12.2015 15:39:44
-- Design Name:
-- Module Name: topmodule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity topmodule is
Port (
clk : IN STD_LOGIC;
SCL1 : INOUT STD_LOGIC;
SDA1 : INOUT STD_LOGIC;
SCL2 : INOUT STD_LOGIC;
SDA2 : INOUT STD_LOGIC;
SCL3 : INOUT STD_LOGIC;
SDA3 : INOUT STD_LOGIC;
SCL4 : INOUT STD_LOGIC;
SDA4 : INOUT STD_LOGIC;
SCL5 : INOUT STD_LOGIC;
SDA5 : INOUT STD_LOGIC;
SCL6 : INOUT STD_LOGIC;
SDA6 : INOUT STD_LOGIC;
SCL7 : INOUT STD_LOGIC;
SDA7 : INOUT STD_LOGIC;
SCL8 : INOUT STD_LOGIC;
SDA8 : INOUT STD_LOGIC;
SCL9 : INOUT STD_LOGIC;
SDA9 : INOUT STD_LOGIC;
SCL10 : INOUT STD_LOGIC;
SDA10 : INOUT STD_LOGIC;
--RsRx : IN STD_LOGIC;
RsTx : OUT STD_LOGIC;
--RsCts :
--RsRts :
btnCpuReset : IN STD_LOGIC
);
end topmodule;
architecture Behavioral of topmodule is
-- internal reset
signal resetin, reset, reset_n: std_logic;
-- serial to serialLoader signals
signal txd, ready, send: std_logic;
signal serialData: std_logic_vector (7 downto 0);
-- FIFO Signals serial loader to FIFO signals
signal Serial_FIFO_Empty, Serial_FIFO_Full, Serial_FIFO_ReadEn, Serial_FIFO_WriteEn: std_logic;
signal Serial_FIFO_DataOut, Serial_FIFO_DataIn: std_logic_vector (7 downto 0);
--SENSORS:
-- Global stuff
constant I2C_RW : std_logic := '1'; -- we will always be reading so we can set this constant
constant I2C_DELIMETER : std_logic_vector (7 downto 0):= "00000000"; -- the byte that will be between each reading.
constant I2C_ADDR : std_logic_vector (6 downto 0):= "0101000"; -- the address of the
--SENSOR1:
constant I2C1_Id : std_Logic_vector (7 downto 0) := "00000001"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C1_FIFO_Empty, I2C1_FIFO_Full, I2C1_FIFO_ReadEn, I2C1_FIFO_WriteEn: std_logic;
signal I2C1_FIFO_DataOut, I2C1_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C1_ENA,I2C1_RW,I2C1_BUSY,I2C1_ACK_ERROR : std_logic;
signal I2C1_DATA_RD : std_logic_vector (7 downto 0);
signal I2C1_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR2:
constant I2C2_Id : std_Logic_vector (7 downto 0) := "00000010"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C2_FIFO_Empty, I2C2_FIFO_Full, I2C2_FIFO_ReadEn, I2C2_FIFO_WriteEn: std_logic;
signal I2C2_FIFO_DataOut, I2C2_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C2_ENA,I2C2_RW,I2C2_BUSY,I2C2_ACK_ERROR : std_logic;
signal I2C2_DATA_RD : std_logic_vector (7 downto 0);
signal I2C2_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR3:
constant I2C3_Id : std_Logic_vector (7 downto 0) := "00000011"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C3_FIFO_Empty, I2C3_FIFO_Full, I2C3_FIFO_ReadEn, I2C3_FIFO_WriteEn: std_logic;
signal I2C3_FIFO_DataOut, I2C3_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C3_ENA,I2C3_RW,I2C3_BUSY,I2C3_ACK_ERROR : std_logic;
signal I2C3_DATA_RD : std_logic_vector (7 downto 0);
signal I2C3_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR4:
constant I2C4_Id : std_Logic_vector (7 downto 0) := "00000100"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C4_FIFO_Empty, I2C4_FIFO_Full, I2C4_FIFO_ReadEn, I2C4_FIFO_WriteEn: std_logic;
signal I2C4_FIFO_DataOut, I2C4_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C4_ENA,I2C4_RW,I2C4_BUSY,I2C4_ACK_ERROR : std_logic;
signal I2C4_DATA_RD : std_logic_vector (7 downto 0);
signal I2C4_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR5:
constant I2C5_Id : std_Logic_vector (7 downto 0) := "00000101"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C5_FIFO_Empty, I2C5_FIFO_Full, I2C5_FIFO_ReadEn, I2C5_FIFO_WriteEn: std_logic;
signal I2C5_FIFO_DataOut, I2C5_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C5_ENA,I2C5_RW,I2C5_BUSY,I2C5_ACK_ERROR : std_logic;
signal I2C5_DATA_RD : std_logic_vector (7 downto 0);
signal I2C5_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR6:
constant I2C6_Id : std_Logic_vector (7 downto 0) := "00000110"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C6_FIFO_Empty, I2C6_FIFO_Full, I2C6_FIFO_ReadEn, I2C6_FIFO_WriteEn: std_logic;
signal I2C6_FIFO_DataOut, I2C6_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C6_ENA,I2C6_RW,I2C6_BUSY,I2C6_ACK_ERROR : std_logic;
signal I2C6_DATA_RD : std_logic_vector (7 downto 0);
signal I2C6_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR7:
constant I2C7_Id : std_Logic_vector (7 downto 0) := "00000111"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C7_FIFO_Empty, I2C7_FIFO_Full, I2C7_FIFO_ReadEn, I2C7_FIFO_WriteEn: std_logic;
signal I2C7_FIFO_DataOut, I2C7_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C7_ENA,I2C7_RW,I2C7_BUSY,I2C7_ACK_ERROR : std_logic;
signal I2C7_DATA_RD : std_logic_vector (7 downto 0);
signal I2C7_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR8:
constant I2C8_Id : std_Logic_vector (7 downto 0) := "00001000"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C8_FIFO_Empty, I2C8_FIFO_Full, I2C8_FIFO_ReadEn, I2C8_FIFO_WriteEn: std_logic;
signal I2C8_FIFO_DataOut, I2C8_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C8_ENA,I2C8_RW,I2C8_BUSY,I2C8_ACK_ERROR : std_logic;
signal I2C8_DATA_RD : std_logic_vector (7 downto 0);
signal I2C8_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR9:
constant I2C9_Id : std_Logic_vector (7 downto 0) := "00001001"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C9_FIFO_Empty, I2C9_FIFO_Full, I2C9_FIFO_ReadEn, I2C9_FIFO_WriteEn: std_logic;
signal I2C9_FIFO_DataOut, I2C9_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C9_ENA,I2C9_RW,I2C9_BUSY,I2C9_ACK_ERROR : std_logic;
signal I2C9_DATA_RD : std_logic_vector (7 downto 0);
signal I2C9_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR10:
constant I2C10_Id : std_Logic_vector (7 downto 0) := "00001010"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C10_FIFO_Empty, I2C10_FIFO_Full, I2C10_FIFO_ReadEn, I2C10_FIFO_WriteEn: std_logic;
signal I2C10_FIFO_DataOut, I2C10_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C10_ENA,I2C10_RW,I2C10_BUSY,I2C10_ACK_ERROR : std_logic;
signal I2C10_DATA_RD : std_logic_vector (7 downto 0);
signal I2C10_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
begin
--wire up the global reset
resetDebounce_unit: entity work.debouncer(Behavioral)
port map(
resetin => resetin,
resetout => reset,
resetout_n => reset_n
);
resetin <= btnCpuReset;
serial_unit: entity work.UART_TX_CTRL(Behavioral)
port map(
SEND => send,
DATA => serialData,
CLK => clk,
READY => ready,
UART_TX => txd
);
RsTx <= txd;
serialLoader_unit: entity work.serialLoader(Behavioral)
port map (
-- global clock
clk => clk,
reset => reset,
--serial control signals
S_Send => send,
S_DataOut => serialData,
S_Ready => ready,
--FIFO DATA
FIFO_Empty => Serial_FIFO_Empty,
FIFO_Data => Serial_FIFO_DataOut,
FIFO_ReadEn => Serial_FIFO_ReadEn
);
serialFIFObuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => Serial_FIFO_WriteEn,
DataIn => Serial_FIFO_DataIn,
ReadEn => Serial_FIFO_ReadEn,
DataOut => Serial_FIFO_DataOut,
Empty => Serial_FIFO_Empty,
Full => Serial_FIFO_Full
);
DataSequencer_unit: entity work.DataSequencer(Behavioral)
port map (
clk => clk,
reset => reset,
S_FIFO_WriteEn => Serial_FIFO_WriteEn,
S_FIFO_DataIn => Serial_FIFO_DataIn,
S_FIFO_Full => Serial_FIFO_Full,
I2C1_FIFO_ReadEn => I2C1_FIFO_ReadEn,
I2C1_FIFO_DataOut => I2C1_FIFO_DataOut,
I2C1_FIFO_Empty => I2C1_FIFO_Empty,
I2C2_FIFO_ReadEn => I2C2_FIFO_ReadEn,
I2C2_FIFO_DataOut => I2C2_FIFO_DataOut,
I2C2_FIFO_Empty => I2C2_FIFO_Empty,
I2C3_FIFO_ReadEn => I2C3_FIFO_ReadEn,
I2C3_FIFO_DataOut => I2C3_FIFO_DataOut,
I2C3_FIFO_Empty => I2C3_FIFO_Empty,
I2C4_FIFO_ReadEn => I2C4_FIFO_ReadEn,
I2C4_FIFO_DataOut => I2C4_FIFO_DataOut,
I2C4_FIFO_Empty => I2C4_FIFO_Empty,
I2C5_FIFO_ReadEn => I2C5_FIFO_ReadEn,
I2C5_FIFO_DataOut => I2C5_FIFO_DataOut,
I2C5_FIFO_Empty => I2C5_FIFO_Empty,
I2C6_FIFO_ReadEn => I2C6_FIFO_ReadEn,
I2C6_FIFO_DataOut => I2C6_FIFO_DataOut,
I2C6_FIFO_Empty => I2C6_FIFO_Empty,
I2C7_FIFO_ReadEn => I2C7_FIFO_ReadEn,
I2C7_FIFO_DataOut => I2C7_FIFO_DataOut,
I2C7_FIFO_Empty => I2C7_FIFO_Empty,
I2C8_FIFO_ReadEn => I2C8_FIFO_ReadEn,
I2C8_FIFO_DataOut => I2C8_FIFO_DataOut,
I2C8_FIFO_Empty => I2C8_FIFO_Empty,
I2C9_FIFO_ReadEn => I2C9_FIFO_ReadEn,
I2C9_FIFO_DataOut => I2C9_FIFO_DataOut,
I2C9_FIFO_Empty => I2C9_FIFO_Empty,
I2C10_FIFO_ReadEn => I2C10_FIFO_ReadEn,
I2C10_FIFO_DataOut => I2C10_FIFO_DataOut,
I2C10_FIFO_Empty => I2C10_FIFO_Empty
);
-- LOGIC FOR SENSORS:
--SENSOR1:
I2C1_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C1_FIFO_WriteEn,
DataIn => I2C1_FIFO_DataIn,
ReadEn => I2C1_FIFO_ReadEn,
DataOut => I2C1_FIFO_DataOut,
Empty => I2C1_FIFO_Empty,
Full => I2C1_FIFO_Full
);
I2C1_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C1_FIFO_WriteEn,
FIFO_DataIn => I2C1_FIFO_DataIn,
FIFO_Full => I2C1_FIFO_Full,
ena => I2C1_ENA,
busy => I2C1_BUSY,
data_rd => I2C1_DATA_RD,
ack_error => I2C1_ACK_ERROR,
sensorId => I2C1_Id,
delimeter => I2C_DELIMETER
);
I2C1_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C1_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C1_DATA_WR,
busy => I2C1_BUSY,
data_rd => I2C1_DATA_RD,
ack_error => I2C1_ACK_ERROR,
sda => SDA1,-- sda,
scl => SCL1 --scl
);
--SENSOR2:
I2C2_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C2_FIFO_WriteEn,
DataIn => I2C2_FIFO_DataIn,
ReadEn => I2C2_FIFO_ReadEn,
DataOut => I2C2_FIFO_DataOut,
Empty => I2C2_FIFO_Empty,
Full => I2C2_FIFO_Full
);
I2C2_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C2_FIFO_WriteEn,
FIFO_DataIn => I2C2_FIFO_DataIn,
FIFO_Full => I2C2_FIFO_Full,
ena => I2C2_ENA,
busy => I2C2_BUSY,
data_rd => I2C2_DATA_RD,
ack_error => I2C2_ACK_ERROR,
sensorId => I2C2_Id,
delimeter => I2C_DELIMETER
);
I2C2_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C2_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C2_DATA_WR,
busy => I2C2_BUSY,
data_rd => I2C2_DATA_RD,
ack_error => I2C2_ACK_ERROR,
sda => SDA2,-- sda,
scl => SCL2 --scl
);
--SENSOR3:
I2C3_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C3_FIFO_WriteEn,
DataIn => I2C3_FIFO_DataIn,
ReadEn => I2C3_FIFO_ReadEn,
DataOut => I2C3_FIFO_DataOut,
Empty => I2C3_FIFO_Empty,
Full => I2C3_FIFO_Full
);
I2C3_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C3_FIFO_WriteEn,
FIFO_DataIn => I2C3_FIFO_DataIn,
FIFO_Full => I2C3_FIFO_Full,
ena => I2C3_ENA,
busy => I2C3_BUSY,
data_rd => I2C3_DATA_RD,
ack_error => I2C3_ACK_ERROR,
sensorId => I2C3_Id,
delimeter => I2C_DELIMETER
);
I2C3_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C3_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C3_DATA_WR,
busy => I2C3_BUSY,
data_rd => I2C3_DATA_RD,
ack_error => I2C3_ACK_ERROR,
sda => SDA3,-- sda,
scl => SCL3 --scl
);
--SENSOR4:
I2C4_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C4_FIFO_WriteEn,
DataIn => I2C4_FIFO_DataIn,
ReadEn => I2C4_FIFO_ReadEn,
DataOut => I2C4_FIFO_DataOut,
Empty => I2C4_FIFO_Empty,
Full => I2C4_FIFO_Full
);
I2C4_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C4_FIFO_WriteEn,
FIFO_DataIn => I2C4_FIFO_DataIn,
FIFO_Full => I2C4_FIFO_Full,
ena => I2C4_ENA,
busy => I2C4_BUSY,
data_rd => I2C4_DATA_RD,
ack_error => I2C4_ACK_ERROR,
sensorId => I2C4_Id,
delimeter => I2C_DELIMETER
);
I2C4_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C4_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C4_DATA_WR,
busy => I2C4_BUSY,
data_rd => I2C4_DATA_RD,
ack_error => I2C4_ACK_ERROR,
sda => SDA4,-- sda,
scl => SCL4 --scl
);
--SENSOR5:
I2C5_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C5_FIFO_WriteEn,
DataIn => I2C5_FIFO_DataIn,
ReadEn => I2C5_FIFO_ReadEn,
DataOut => I2C5_FIFO_DataOut,
Empty => I2C5_FIFO_Empty,
Full => I2C5_FIFO_Full
);
I2C5_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C5_FIFO_WriteEn,
FIFO_DataIn => I2C5_FIFO_DataIn,
FIFO_Full => I2C5_FIFO_Full,
ena => I2C5_ENA,
busy => I2C5_BUSY,
data_rd => I2C5_DATA_RD,
ack_error => I2C5_ACK_ERROR,
sensorId => I2C5_Id,
delimeter => I2C_DELIMETER
);
I2C5_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C5_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C5_DATA_WR,
busy => I2C5_BUSY,
data_rd => I2C5_DATA_RD,
ack_error => I2C5_ACK_ERROR,
sda => SDA5,-- sda,
scl => SCL5 --scl
);
--SENSOR6:
I2C6_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C6_FIFO_WriteEn,
DataIn => I2C6_FIFO_DataIn,
ReadEn => I2C6_FIFO_ReadEn,
DataOut => I2C6_FIFO_DataOut,
Empty => I2C6_FIFO_Empty,
Full => I2C6_FIFO_Full
);
I2C6_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C6_FIFO_WriteEn,
FIFO_DataIn => I2C6_FIFO_DataIn,
FIFO_Full => I2C6_FIFO_Full,
ena => I2C6_ENA,
busy => I2C6_BUSY,
data_rd => I2C6_DATA_RD,
ack_error => I2C6_ACK_ERROR,
sensorId => I2C6_Id,
delimeter => I2C_DELIMETER
);
I2C6_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C6_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C6_DATA_WR,
busy => I2C6_BUSY,
data_rd => I2C6_DATA_RD,
ack_error => I2C6_ACK_ERROR,
sda => SDA6,-- sda,
scl => SCL6 --scl
);
--SENSOR7:
I2C7_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C7_FIFO_WriteEn,
DataIn => I2C7_FIFO_DataIn,
ReadEn => I2C7_FIFO_ReadEn,
DataOut => I2C7_FIFO_DataOut,
Empty => I2C7_FIFO_Empty,
Full => I2C7_FIFO_Full
);
I2C7_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C7_FIFO_WriteEn,
FIFO_DataIn => I2C7_FIFO_DataIn,
FIFO_Full => I2C7_FIFO_Full,
ena => I2C7_ENA,
busy => I2C7_BUSY,
data_rd => I2C7_DATA_RD,
ack_error => I2C7_ACK_ERROR,
sensorId => I2C7_Id,
delimeter => I2C_DELIMETER
);
I2C7_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C7_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C7_DATA_WR,
busy => I2C7_BUSY,
data_rd => I2C7_DATA_RD,
ack_error => I2C7_ACK_ERROR,
sda => SDA7,-- sda,
scl => SCL7 --scl
);
--SENSOR8:
I2C8_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C8_FIFO_WriteEn,
DataIn => I2C8_FIFO_DataIn,
ReadEn => I2C8_FIFO_ReadEn,
DataOut => I2C8_FIFO_DataOut,
Empty => I2C8_FIFO_Empty,
Full => I2C8_FIFO_Full
);
I2C8_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C8_FIFO_WriteEn,
FIFO_DataIn => I2C8_FIFO_DataIn,
FIFO_Full => I2C8_FIFO_Full,
ena => I2C8_ENA,
busy => I2C8_BUSY,
data_rd => I2C8_DATA_RD,
ack_error => I2C8_ACK_ERROR,
sensorId => I2C8_Id,
delimeter => I2C_DELIMETER
);
I2C8_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C8_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C8_DATA_WR,
busy => I2C8_BUSY,
data_rd => I2C8_DATA_RD,
ack_error => I2C8_ACK_ERROR,
sda => SDA8,-- sda,
scl => SCL8 --scl
);
--SENSOR9:
I2C9_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C9_FIFO_WriteEn,
DataIn => I2C9_FIFO_DataIn,
ReadEn => I2C9_FIFO_ReadEn,
DataOut => I2C9_FIFO_DataOut,
Empty => I2C9_FIFO_Empty,
Full => I2C9_FIFO_Full
);
I2C9_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C9_FIFO_WriteEn,
FIFO_DataIn => I2C9_FIFO_DataIn,
FIFO_Full => I2C9_FIFO_Full,
ena => I2C9_ENA,
busy => I2C9_BUSY,
data_rd => I2C9_DATA_RD,
ack_error => I2C9_ACK_ERROR,
sensorId => I2C9_Id,
delimeter => I2C_DELIMETER
);
I2C9_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C9_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C9_DATA_WR,
busy => I2C9_BUSY,
data_rd => I2C9_DATA_RD,
ack_error => I2C9_ACK_ERROR,
sda => SDA9,-- sda,
scl => SCL9 --scl
);
--SENSOR10:
I2C10_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C10_FIFO_WriteEn,
DataIn => I2C10_FIFO_DataIn,
ReadEn => I2C10_FIFO_ReadEn,
DataOut => I2C10_FIFO_DataOut,
Empty => I2C10_FIFO_Empty,
Full => I2C10_FIFO_Full
);
I2C10_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C10_FIFO_WriteEn,
FIFO_DataIn => I2C10_FIFO_DataIn,
FIFO_Full => I2C10_FIFO_Full,
ena => I2C10_ENA,
busy => I2C10_BUSY,
data_rd => I2C10_DATA_RD,
ack_error => I2C10_ACK_ERROR,
sensorId => I2C10_Id,
delimeter => I2C_DELIMETER
);
I2C10_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C10_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C10_DATA_WR,
busy => I2C10_BUSY,
data_rd => I2C10_DATA_RD,
ack_error => I2C10_ACK_ERROR,
sda => SDA10,-- sda,
scl => SCL10 --scl
);
end Behavioral;
|
gpl-3.0
|
600c1b2a61d896102d0c5df73435b86c
| 0.526035 | 3.010056 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/bocntr.vhd
| 4 | 18,015 |
-------------------------------------------------------------------------------
-- bocntr - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : bocntr.vhd
-- Version : v2.0
-- Description : This is the transmit collision back off counter
-- the back off delay for retry n (1 <= n <= 16) is defined as
-- delay where delay is a uniformly distributed integer number
-- of slot times (512 bit times) defined as
-- 0 <= delay <= 2^k where k is min(n, 10) i.e., k is equal
-- to the retry attempt up to 10 and then remains at 10 for
-- retry attempts 11 through 16. So the delay for retry 1
-- would be 0, 1, or 2 slot times. The delay for retry 2
-- would be 0, 1, 2, 3, or 4 slot times.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clken -- Clock enable
-- InitBackoff -- Backoff initialized
-- RetryCnt -- Retry count
-- BackingOff -- Backing off from transmit
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity bocntr is
port (
Clk : in std_logic; -- tx Clk based (2.5 or 25 MHz)
Clken : in std_logic;
Rst : in std_logic;
InitBackoff : in std_logic;
RetryCnt : in std_logic_vector(0 to 4);
BackingOff : out std_logic);
end bocntr;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of bocntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type StateName is (idle, shifting, inBackoff);
signal thisState : StateName;
signal nextState : StateName;
signal initBackoffLtch : std_logic;
signal initBackoffLtchRst : std_logic;
signal backingOff_i : std_logic;
signal lfsrOut : std_logic;
signal slotCntRst : std_logic;
signal slotCntEnbl : std_logic;
signal slotCnt : std_logic_vector(0 to 6);
signal backOffCntLd : std_logic;
signal backOffCntEnbl : std_logic;
signal backOffCnt : std_logic_vector(0 to 9);
signal shftCntLd : std_logic;
signal shftCntEnbl : std_logic;
signal shftCnt : std_logic_vector(0 to 3);
signal shftRst : std_logic;
signal shftEnbl : std_logic;
signal shftData : std_logic_vector(0 to 9);
signal slotDone : std_logic;
signal numRetries : std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
LFSRP : entity axi_ethernetlite_v3_0.lfsr16
port map(
Rst => Rst,
Clk => Clk,
Clken => Clken,
Enbl => shftEnbl,
Shftout => lfsrOut);
numRetries <= "1010" when (((RetryCnt(1) = '1') and -- 8 or larger and
((RetryCnt(3) = '1') or -- 10, 11, 14, 15 or
(RetryCnt(2) = '1'))) or -- 12 thru 15
(RetryCnt(0) = '1')) else -- 12 thru 15
RetryCnt(1 to 4); -- 9 or less
-------------------------------------------------------------------------------
-- INT_SHFT_PROCESS
-------------------------------------------------------------------------------
INT_SHFT_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if shftRst = '1' then
shftData <= (others => '0');
elsif (shftEnbl = '1') then
shftData(9) <= lfsrOut;
shftData(8) <= shftData(9);
shftData(7) <= shftData(8);
shftData(6) <= shftData(7);
shftData(5) <= shftData(6);
shftData(4) <= shftData(5);
shftData(3) <= shftData(4);
shftData(2) <= shftData(3);
shftData(1) <= shftData(2);
shftData(0) <= shftData(1);
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SHFT_PROCESS;
-------------------------------------------------------------------------------
-- INT_SLOT_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_SLOT_COUNT_PROCESS: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if ((slotCntRst = '1') or (slotDone = '1')) then
slotCnt <= "1111111";
elsif (slotCntEnbl = '1' and not(slotCnt = "0000000")) then
slotCnt <= slotCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SLOT_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_BACKOFF_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_BACKOFF_COUNT_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if (backOffCntLd = '1') then
backOffCnt <= shftData;
elsif (backOffCntEnbl = '1' and not(backOffCnt = "0000000000") and
(slotDone = '1')) then
backOffCnt <= backOffCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_BACKOFF_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_SHIFT_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_SHIFT_COUNT_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if (shftCntLd = '1') then
shftCnt <= numRetries;
elsif (shftCntEnbl = '1' and not(shftCnt = "0000")) then
shftCnt <= shftCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SHIFT_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_BACKOFFDONE_PROCESS
-------------------------------------------------------------------------------
INT_BACKOFFDONE_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
backingOff_i <= '0';
elsif (InitBackoff = '1') then
backingOff_i <= '1';
elsif ((backOffCntEnbl = '1') and (backOffCnt = "000000000")) then
backingOff_i <= '0';
-- coverage off
else
null;
-- coverage on
end if;
end if;
end process INT_BACKOFFDONE_PROCESS;
BackingOff <= backingOff_i;
-------------------------------------------------------------------------------
-- INT_SLOT_TIME_DONE_PROCESS
-------------------------------------------------------------------------------
INT_SLOT_TIME_DONE_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
slotDone <= '0';
elsif (slotCntEnbl = '0') then
slotDone <= '0';
elsif ((slotDone = '1') and (Clken = '1')) then
slotDone <= '0';
elsif ((slotCntEnbl = '1') and (slotCnt = "0000000")) then
slotDone <= '1';
else
null;
end if;
end if;
end process INT_SLOT_TIME_DONE_PROCESS;
-------------------------------------------------------------------------------
-- INT_LATCH_PROCESS
-------------------------------------------------------------------------------
INT_LATCH_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
initBackoffLtch <= '0';
elsif (InitBackoff = '1') then
initBackoffLtch <= '1';
elsif (initBackoffLtchRst = '1') then
initBackoffLtch <= '0';
-- coverage off
else
null;
-- coverage on
-- coverage on
end if;
end if;
end process INT_LATCH_PROCESS;
-------------------------------------------------------------------------------
-- An FSM that deals with backing off
-------------------------------------------------------------------------------
FSMR : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
thisState <= idle;
elsif (Clken = '1') then
thisState <= nextState;
end if;
end if;
end process FSMR;
-------------------------------------------------------------------------------
-- State Machine
-------------------------------------------------------------------------------
FSMC : process (thisState,initBackoffLtch,shftCnt,backOffCnt)
begin --
case thisState is
when idle =>
if (initBackoffLtch = '1') then
nextState <= shifting;
else
nextState <= idle;
end if;
when shifting =>
if (shftCnt = "0000") then
nextState <= inBackoff;
else
nextState <= shifting;
end if;
when inBackoff =>
if (backOffCnt = "000000000") then
nextState <= idle;
else
nextState <= inBackoff;
end if;
-- coverage off
when others => null;
nextState <= idle;
-- coverage on
end case;
end process FSMC;
-------------------------------------------------------------------------------
-- State Machine Control signals generation
-------------------------------------------------------------------------------
FSMD : process(thisState)
begin
if (thisState = idle) then
shftRst <= '1';
shftCntLd <= '1';
else
shftRst <= '0';
shftCntLd <= '0';
end if;
if ((thisState = idle) or (thisState = shifting)) then
slotCntRst <= '1';
backOffCntLd <= '1';
else
slotCntRst <= '0';
backOffCntLd <= '0';
end if;
if (thisState = shifting) then
shftCntEnbl <= '1';
shftEnbl <= '1';
initBackoffLtchRst <= '1';
else
shftCntEnbl <= '0';
shftEnbl <= '0';
initBackoffLtchRst <= '0';
end if;
if (thisState = inBackoff) then
slotCntEnbl <= '1';
backOffCntEnbl <= '1';
else
slotCntEnbl <= '0';
backOffCntEnbl <= '0';
end if;
end process FSMD;
end implementation;
|
gpl-3.0
|
fac6ed7839f497dfa8792f80a55aaad8
| 0.400167 | 5.112089 | false | false | false | false |
lowRISC/greth-library
|
greth_library/gnsslib/sync/reclk.vhd
| 2 | 1,510 |
-----------------------------------------------------------------------------
-- Package: fse_v2
-- File: reclk.vhd
-- Author: Sergey Khabarov - [email protected]
-- Description: Reclocking from ADC clock domain into FSE clock domain
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library gnsslib;
use gnsslib.types_sync.all;
entity Reclk is
port (
i : in reclk_in_type;
o : out reclk_out_type
);
end;
architecture rtl of Reclk is
type regtype is record
I : std_logic_vector(1 downto 0);
Q : std_logic_vector(1 downto 0);
ms_pulse : std_logic;
pps : std_logic;
clk_adc : std_logic_vector(1 downto 0);
end record;
signal r, rin : regtype;
begin
comb : process (r, i)
variable v : regtype;
begin
v := r;
v.clk_adc := r.clk_adc(0) & i.clk_adc;
v.I := i.I;
v.Q := i.Q;
v.ms_pulse := i.ms_pulse;
v.pps := i.pps;
-- Reset all
if i.nrst = '0' then
v.I := (others => '0');
v.Q := (others => '0');
v.ms_pulse := '0';
v.pps := '0';
v.clk_adc := (others => '0');
end if;
rin <= v;
end process;
o.I <= r.I;
o.Q <= r.Q;
o.ms_pulse <= r.ms_pulse;
o.pps <= r.pps;
o.adc_valid <= not r.clk_adc(0) and r.clk_adc(1);
regs : process(i.clk_fse)
begin
if rising_edge(i.clk_fse) then
r <= rin;
end if;
end process;
end;
|
bsd-2-clause
|
acff2aa0dfeab27119e73a4e34af891d
| 0.503311 | 3.05668 | false | false | false | false |
lowRISC/greth-library
|
greth_library/rocketlib/eth/greth_pkg.vhd
| 2 | 36,022 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
constant eth_rx_in_none : eth_rx_ahb_in_type := (
'0', '0', (others => '0'), (others => '0'), (others => '0'));
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
rx_en : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
iotest : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type;
iotmact : in std_ulogic;
iotdata : in std_logic_vector(9 downto 0)
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type;
iotdata : out std_logic_vector(9 downto 0));
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
component eth_axi_mst is
generic (
xindex : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
aximi : in nasti_master_in_type;
aximo : out nasti_master_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
-- ETH registers
type eth_mdio_command_type is record
valid : std_ulogic;
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
end record;
constant eth_mdio_command_none : eth_mdio_command_type := (
'0', (others => '0'), '0', '0', (others => '0')
);
type eth_mdio_status_type is record
cmd : eth_mdio_command_type;
busy : std_ulogic;
linkfail : std_ulogic;
end record;
type eth_mac_status_type is record
txdsel : std_logic_vector(9 downto 3);
rxdsel : std_logic_vector(9 downto 3);
txen : std_ulogic;
rxen : std_ulogic;
tx_int : std_ulogic;
rx_int : std_ulogic;
tx_err : std_ulogic;
rx_err : std_ulogic;
edcltx_idle : std_ulogic;
edclrx_idle : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
phystat : std_ulogic;
full_duplex : std_ulogic;
speed : std_ulogic;
reset : std_ulogic;
mdio : eth_mdio_status_type;
end record;
--! Latched values set via external Bus Interface
type eth_control_type is record
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
prom : std_ulogic;
pstatirqen : std_ulogic;
mcasten : std_ulogic;
--! Enable access to the internal FIFOs via system BUS (disabled default)
ramdebugen : std_ulogic;
--! Disable EDCL access
edcldis : std_ulogic;
disableduplex : std_ulogic;
--! Physical address.
--! Can be changed in a runtime, but become actual only after system reset.
mdio_phyadr : std_logic_vector(4 downto 0);
mac_addr : std_logic_vector(47 downto 0);
--! Tx descriptor
txdesc : std_logic_vector(31 downto 10);
--! Rx descriptor
rxdesc : std_logic_vector(31 downto 10);
--! EDCL IP
edclip : std_logic_vector(31 downto 0);
--! Multicast enabling hash value
hash : std_logic_vector(63 downto 0);
emacaddr : std_logic_vector(47 downto 0);
end record;
--! @name DBG access unique IDs to the internal FIFOs blocks.
--! @{
constant DBG_ACCESS_NONE : std_logic_vector(1 downto 0) := "00";
constant DBG_ACCESS_TX_BUFFER : std_logic_vector(1 downto 0) := "01";
constant DBG_ACCESS_RX_BUFFER : std_logic_vector(1 downto 0) := "10";
constant DBG_ACCESS_EDCL_BUFFER : std_logic_vector(1 downto 0) := "11";
--! @}
--! Bus interface read/write actions transforming into these commands.
type eth_command_type is record
--! Tx/Rx can be enabled externally but they're cleared inside of MAC
--! in a case of disabled Descriptor or in a case of BUS error.
set_txena : std_ulogic;
clr_txena : std_ulogic;
set_rxena : std_ulogic;
clr_rxena : std_ulogic;
--! Set new descriptor index in the array of descriptors table
set_txdsel : std_ulogic;
set_rxdsel : std_ulogic;
txdsel : std_logic_vector(9 downto 3);
rxdsel : std_logic_vector(9 downto 3);
--! The following values can be changed during initialization stage.
set_full_duplex : std_ulogic;
clr_full_duplex : std_ulogic;
set_speed : std_ulogic;
clr_speed : std_ulogic;
set_reset : std_ulogic;
clr_reset : std_ulogic;
--! Clear status bits commands:
clr_status_tx_int : std_ulogic;
clr_status_rx_int : std_ulogic;
clr_status_tx_err : std_ulogic;
clr_status_rx_err : std_ulogic;
clr_status_txahberr : std_ulogic;
clr_status_rxahberr : std_ulogic;
clr_status_toosmall : std_ulogic;
clr_status_invaddr : std_ulogic;
clr_status_phystat : std_ulogic;
--! mdi interface command
mdio_cmd : eth_mdio_command_type;
--! Request ID values:
dbg_access_id : std_logic_vector(1 downto 0);
dbg_wr_ena : std_logic;
dbg_rd_ena : std_logic;
dbg_addr : std_logic_vector(13 downto 0);
dbg_wdata : std_logic_vector(31 downto 0);
end record;
constant eth_command_none : eth_command_type := (
'0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0', '0', '0', eth_mdio_command_none,
DBG_ACCESS_NONE, '0', '0', (others => '0'), (others => '0')
);
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
tx_clk_90 : std_ulogic;
rx_clk : std_ulogic;
tx_dv : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_en : std_ulogic;
rx_crs : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable : std_ulogic;
end record;
constant eth_in_none : eth_in_type := (
'0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type := (
'0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
component grethc64 is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in eth_control_type;
cmdi : in eth_command_type;
statuso : out eth_mac_status_type;
--! Debug value read from internal buffers suing external bus interface
rdbgdatao : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
tmsto : out eth_tx_ahb_in_type;
tmsti : in eth_tx_ahb_out_type;
tmsto2 : out eth_tx_ahb_in_type;
tmsti2 : in eth_tx_ahb_out_type;
rmsto : out eth_rx_ahb_in_type;
rmsti : in eth_rx_ahb_out_type
);
end component;
component grethaxi is
generic(
xslvindex : integer := 0;
xmstindex : integer := 0;
xmstindex2 : integer := 1;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : in nasti_master_in_type;
msto : out nasti_master_out_type;
mstcfg : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
slvi : in nasti_slave_in_type;
slvo : out nasti_slave_out_type;
slvcfg : out nasti_slave_config_type;
ethi : in eth_in_type;
etho : out eth_out_type;
irq : out std_logic
);
end component;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--function calccrc_8(data : in std_logic_vector( 7 downto 0);
-- crc : in std_logic_vector(31 downto 0))
-- return std_logic_vector is
-- variable ncrc : std_logic_vector(31 downto 0);
-- variable d : std_logic_vector(7 downto 0);
--begin
-- d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3);
-- d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7);
-- ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30);
-- ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31);
-- ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31);
-- ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31);
-- ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29);
-- ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29);
-- ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30);
-- ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31);
-- ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29);
-- ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30);
-- ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31);
-- ncrc(20) := d(4) xor crc(12) xor crc(28);
-- ncrc(21) := d(5) xor crc(13) xor crc(29);
-- ncrc(22) := d(0) xor crc(14) xor crc(24);
-- ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30);
-- ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31);
-- ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27);
-- ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30);
-- ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31);
-- ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31);
-- ncrc(31) := d(5) xor crc(23) xor crc(29);
-- return ncrc;
--end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
|
bsd-2-clause
|
9d0cc785c0ac5ff017de124ad8c0e9da
| 0.544723 | 3.180189 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sources_1/new/uart_TX.vhd
| 1 | 4,747 |
----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
--2Mbaud --> 49 -- 100MHz / 2Mbaud -1 = 50 -1 = 49 = 00000000110001
--constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "00000000110001"; --2Mbaud
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
|
gpl-3.0
|
4dabda88d504ce8fee7a778fc34700e5
| 0.571519 | 3.705699 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/bus_master.vhd
| 4 | 27,908 |
-------------------------------------------------------------------------------
-- bus_master.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: bus_master.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- bus_master.vhd
-- - srl_fifo
-- - srl_fifo
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2013-11-01 First Version
-- stefana 2013-06-15 Added direct write port
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural := 32;
C_M_AXI_THREAD_ID_WIDTH : natural := 4;
C_M_AXI_ADDR_WIDTH : natural := 32;
C_DATA_SIZE : natural := 32;
C_HAS_FIFO_PORTS : boolean := true;
C_HAS_DIRECT_PORT : boolean := false
);
port (
-- Bus read and write transaction
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
-- Bus read and write data
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
-- Direct write port
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
-- LMB bus
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- AXI bus
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end entity bus_master;
library IEEE;
use ieee.numeric_std.all;
library mdm_v3_2;
use mdm_v3_2.all;
architecture IMP of bus_master is
component SRL_FIFO is
generic (
C_DATA_BITS : natural;
C_DEPTH : natural
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end component SRL_FIFO;
-- Calculate WSTRB given size and low address bits
function Calc_WSTRB (Wr_Size : std_logic_vector(1 downto 0);
Wr_Addr : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
if Wr_Size = "00" then -- Byte
case Wr_Addr is
when "00" => return "0001";
when "01" => return "0010";
when "10" => return "0100";
when "11" => return "1000";
when others => null;
end case;
end if;
if Wr_Size = "01" then -- Halfword
if Wr_Addr(1) = '0' then
return "0011";
else
return "1100";
end if;
end if;
return "1111"; -- Word
end function Calc_WSTRB;
type wr_state_type is (idle, start, wait_on_ready, wait_on_bchan);
signal wr_state : wr_state_type;
signal wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal axi_wvalid : std_logic; -- internal M_AXI_WVALID
signal axi_wr_start : std_logic; -- LMB did not respond, start AXI write
signal axi_wr_idle : std_logic; -- AXI write is idle
signal axi_wr_resp : std_logic_vector(1 downto 0); -- AXI write response
signal axi_do_read : std_logic; -- read word from write FIFO for AXI
signal axi_dwr_addr : std_logic_vector(31 downto 0);
signal axi_dwr_len : std_logic_vector(4 downto 0);
signal axi_dwr_size : std_logic_vector(1 downto 0);
signal axi_dwr_exclusive : std_logic;
signal axi_dwr_start : std_logic;
signal axi_dwr_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_dwr_wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal axi_dwr_sel : std_logic;
signal axi_dwr_done : std_logic;
begin -- architecture IMP
assert (C_DATA_SIZE = C_M_AXI_DATA_WIDTH)
report "LMB and AXI data widths must be the same" severity FAILURE;
Has_FIFO: if C_HAS_FIFO_PORTS generate
type lmb_state_type is (idle, start_rd, wait_rd, start_wr, wait_wr, sample_rd, sample_wr, direct_wr);
type rd_state_type is (idle, start, wait_on_ready, wait_on_data);
signal lmb_state : lmb_state_type;
signal rd_state : rd_state_type;
signal reset : std_logic;
signal rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal lmb_addr : std_logic_vector(4 downto 0); -- LMB word address
signal lmb_addr_next : std_logic_vector(4 downto 0); -- LMB word address incremented
signal lmb_len : std_logic_vector(4 downto 0); -- LMB length
signal lmb_len_next : std_logic_vector(4 downto 0); -- LMB length decremented
signal lmb_rd_idle : std_logic; -- LMB read is idle
signal lmb_wr_idle : std_logic; -- LMB write is idle
signal lmb_rd_resp : std_logic_vector(1 downto 0); -- LMB read response
signal lmb_wr_resp : std_logic_vector(1 downto 0); -- LMB write response
signal axi_rready : std_logic; -- internal M_AXI_RREADY
signal axi_rd_start : std_logic; -- LMB did not respond, start AXI read
signal axi_rd_idle : std_logic; -- AXI read is idle
signal axi_rd_resp : std_logic_vector(1 downto 0); -- AXI read response
signal axi_do_write : std_logic; -- write word to read FIFO for AXI
signal wdata_exists : std_logic; -- write FIFO has data
begin
reset <= not M_AXI_ARESETn;
-- Read FIFO instantiation
Read_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => 32,
C_DEPTH => 32
)
port map (
Clk => M_AXI_ACLK,
Reset => reset,
FIFO_Write => do_write,
Data_In => rdata,
FIFO_Read => Data_Rd,
Data_Out => Data_Out,
FIFO_Full => open,
Data_Exists => Data_Exists
);
-- Write FIFO instantiation
Write_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => 32,
C_DEPTH => 32
)
port map (
Clk => M_AXI_ACLK,
Reset => reset,
FIFO_Write => Data_Wr,
Data_In => Data_In,
FIFO_Read => do_read,
Data_Out => wdata,
FIFO_Full => open,
Data_Exists => wdata_exists
);
-- Common signals
Data_Empty <= not wdata_exists;
Rd_Idle <= lmb_rd_idle and axi_rd_idle;
Rd_Response <= lmb_rd_resp or axi_rd_resp;
Wr_Idle <= lmb_wr_idle and axi_wr_idle;
Wr_Response <= lmb_wr_resp or axi_wr_resp;
wstrb <= Calc_WSTRB(Wr_Size, Wr_Addr(1 downto 0));
rdata <= LMB_Data_Read when (LMB_Ready = '1' and lmb_rd_idle = '0') else M_AXI_RDATA;
do_write <= (LMB_Ready and not lmb_rd_idle) or axi_do_write;
do_read <= (LMB_Ready and not lmb_wr_idle) or axi_do_read;
-- LMB implementation
LMB_Data_Addr <= Wr_Addr(C_M_AXI_ADDR_WIDTH-1 downto 7) & lmb_addr & Wr_Addr(1 downto 0);
LMB_Data_Write <= wdata;
LMB_Byte_Enable <= wstrb;
lmb_addr_next <= std_logic_vector(unsigned(lmb_addr) + 1);
lmb_len_next <= std_logic_vector(unsigned(lmb_len) - 1);
LMB_Executing : process (M_AXI_ACLK) is
variable ue : std_logic;
begin -- process LMB_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then
if (M_AXI_ARESETn = '0') then
lmb_state <= idle;
axi_dwr_sel <= '0';
axi_rd_start <= '0';
axi_wr_start <= '0';
lmb_addr <= (others => '0');
lmb_rd_idle <= '1';
lmb_wr_idle <= '1';
lmb_len <= (others => '0');
lmb_rd_resp <= "00";
lmb_wr_resp <= "00";
ue := '0';
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
LMB_Write_Strobe <= '0';
else
axi_rd_start <= '0';
axi_wr_start <= '0';
case lmb_state is
when idle =>
lmb_addr <= Wr_Addr(6 downto 2);
lmb_len <= Wr_Len;
lmb_rd_idle <= '1';
lmb_wr_idle <= '1';
ue := '0';
if (Direct_Wr_Start = '1' and C_HAS_DIRECT_PORT) then
lmb_state <= direct_wr;
axi_dwr_sel <= '1';
end if;
if (Rd_Start = '1') then
lmb_state <= start_rd;
axi_dwr_sel <= '0';
lmb_rd_idle <= '0';
lmb_rd_resp <= "00";
LMB_Addr_Strobe <= '1';
LMB_Read_Strobe <= '1';
end if;
if (Wr_Start = '1') then
lmb_state <= start_wr;
axi_dwr_sel <= '0';
lmb_wr_idle <= '0';
lmb_wr_resp <= "00";
LMB_Addr_Strobe <= '1';
LMB_Write_Strobe <= '1';
end if;
when start_rd =>
lmb_state <= wait_rd;
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
when wait_rd =>
lmb_state <= sample_rd;
when sample_rd =>
if (LMB_Ready = '1') then
if (lmb_len = (lmb_len'range => '0')) then
lmb_state <= idle;
else
lmb_state <= start_rd;
LMB_Addr_Strobe <= '1';
LMB_Read_Strobe <= '1';
end if;
lmb_addr <= lmb_addr_next;
lmb_len <= lmb_len_next;
ue := LMB_UE or ue;
lmb_rd_resp <= ue & '0';
elsif (LMB_Wait = '0') then
lmb_state <= idle;
axi_rd_start <= '1';
end if;
when start_wr =>
lmb_state <= wait_wr;
LMB_Addr_Strobe <= '0';
LMB_Write_Strobe <= '0';
when wait_wr =>
lmb_state <= sample_wr;
when sample_wr =>
if (LMB_Ready = '1') then
if (lmb_len = (lmb_len'range => '0')) then
lmb_state <= idle;
else
lmb_state <= start_wr;
LMB_Addr_Strobe <= '1';
LMB_Write_Strobe <= '1';
end if;
lmb_addr <= lmb_addr_next;
lmb_len <= lmb_len_next;
ue := LMB_UE or ue;
lmb_wr_resp <= ue & '0';
elsif (LMB_Wait = '0') then
lmb_state <= idle;
axi_wr_start <= '1';
end if;
when direct_wr => -- Handle AXI direct write
if axi_dwr_done = '1' and Direct_Wr_Start = '0' then
lmb_state <= idle;
axi_dwr_sel <= '0';
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process LMB_Executing;
-- AXI Read FSM
Rd_Executing : process (M_AXI_ACLK) is
variable rd_resp : std_logic_vector(1 downto 0);
begin -- process Rd_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
rd_resp := "00";
axi_rready <= '0';
axi_rd_idle <= '1';
axi_rd_resp <= "00";
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= "010"; -- 32-bit accesses
M_AXI_ARLOCK <= '0'; -- No locking
M_AXI_ARVALID <= '0';
rd_state <= idle;
else
case rd_state is
when idle =>
rd_resp := "00";
axi_rd_idle <= '1';
if axi_rd_start = '1' then
rd_state <= start;
axi_rd_idle <= '0';
axi_rd_resp <= "00";
end if;
when start =>
M_AXI_ARVALID <= '1';
M_AXI_ARADDR <= Rd_Addr;
M_AXI_ARLEN <= "000" & Rd_Len;
M_AXI_ARSIZE <= "0" & Rd_Size;
M_AXI_ARLOCK <= Rd_Exclusive;
rd_state <= wait_on_ready;
when wait_on_ready =>
if (M_AXI_ARREADY = '1') then
M_AXI_ARVALID <= '0';
axi_rready <= '1';
rd_state <= wait_on_data;
end if;
when wait_on_data =>
if (M_AXI_RVALID = '1') then
if rd_resp = "00" and M_AXI_RRESP /= "00" then
rd_resp := M_AXI_RRESP; -- Sticky error response
end if;
if (M_AXI_RLAST = '1') then
rd_state <= idle;
axi_rd_resp <= rd_resp;
axi_rready <= '0';
end if;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process Rd_Executing;
axi_do_write <= axi_rready and M_AXI_RVALID;
end generate Has_FIFO;
No_FIFO: if not C_HAS_FIFO_PORTS generate
type state_type is (idle, direct_wr);
signal state : state_type;
begin
Rd_Idle <= '1';
Rd_Response <= "00";
Data_Out <= (others => '0');
Data_Exists <= '0';
Data_Empty <= '0';
Wr_Idle <= '0';
Wr_Response <= "00";
LMB_Data_Addr <= (others => '0');
LMB_Data_Write <= (others => '0');
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
LMB_Write_Strobe <= '0';
LMB_Byte_Enable <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARVALID <= '0';
wdata <= (others => '0');
wstrb <= (others => '0');
axi_wr_start <= '0';
AXI_Direct_Write: process (M_AXI_ACLK) is
begin -- process AXI_Direct_Write
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
state <= idle;
axi_dwr_sel <= '0';
else
case state is
when idle =>
if Direct_Wr_Start = '1' then
state <= direct_wr;
axi_dwr_sel <= '1';
end if;
when direct_wr =>
if axi_dwr_done = '1' and Direct_Wr_Start = '0' then
state <= idle;
axi_dwr_sel <= '0';
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process AXI_Direct_Write;
end generate No_FIFO;
Has_Direct_Write: if C_HAS_DIRECT_PORT generate
begin
Direct_Wr_Next <= axi_do_read when axi_dwr_sel = '1' else '0';
Direct_Wr_Done <= axi_dwr_done when axi_dwr_sel = '1' else '0';
Direct_Wr_Resp <= axi_wr_resp;
axi_dwr_addr <= Direct_Wr_Addr when axi_dwr_sel = '1' else Wr_Addr;
axi_dwr_len <= Direct_Wr_Len when axi_dwr_sel = '1' else Wr_Len;
axi_dwr_size <= "10" when axi_dwr_sel = '1' else Wr_Size;
axi_dwr_exclusive <= '0' when axi_dwr_sel = '1' else Wr_Exclusive;
axi_dwr_start <= Direct_Wr_Start when axi_dwr_sel = '1' else axi_wr_start;
axi_dwr_wdata <= Direct_Wr_Data when axi_dwr_sel = '1' else wdata;
axi_dwr_wstrb <= "1111" when axi_dwr_sel = '1' else wstrb;
end generate Has_Direct_Write;
No_Direct_Write: if not C_HAS_DIRECT_PORT generate
begin
Direct_Wr_Next <= '0';
Direct_Wr_Done <= '0';
Direct_Wr_Resp <= "00";
axi_dwr_addr <= Wr_Addr;
axi_dwr_len <= Wr_Len;
axi_dwr_size <= Wr_Size;
axi_dwr_exclusive <= Wr_Exclusive;
axi_dwr_start <= axi_wr_start;
axi_dwr_wdata <= wdata;
axi_dwr_wstrb <= wstrb;
end generate No_Direct_Write;
-- AW signals constant values
M_AXI_AWPROT <= "010"; -- Non-secure data accesses only
M_AXI_AWQOS <= "0000"; -- Don't participate in QoS handling
M_AXI_AWID <= (others => '0'); -- ID fixed to zero
M_AXI_AWBURST <= "01"; -- Only INCR bursts
M_AXI_AWCACHE <= "0011"; -- Set "Modifiable" and "Bufferable" bit
-- AR signals constant values
M_AXI_ARPROT <= "010"; -- Normal and non-secure Data access only
M_AXI_ARQOS <= "0000"; -- Don't participate in QoS handling
M_AXI_ARID <= (others => '0'); -- ID fixed to zero
M_AXI_ARBURST <= "01"; -- Only INCR bursts
M_AXI_ARCACHE <= "0011"; -- Set "Modifiable" and "Bufferable" bit
-- R signals constant values
M_AXI_RREADY <= '1'; -- Always accepting read data
-- B signals value
M_AXI_BREADY <= '1' when wr_state = wait_on_bchan else '0';
-- AXI Write FSM
Wr_Executing : process (M_AXI_ACLK) is
variable address_done : boolean;
variable data_done : boolean;
variable len : std_logic_vector(4 downto 0);
begin -- process Wr_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
axi_wr_idle <= '1';
axi_wr_resp <= "00";
axi_wvalid <= '0';
M_AXI_WVALID <= '0';
M_AXI_WLAST <= '0';
M_AXI_WSTRB <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= "010"; -- 32-bit accesses
M_AXI_AWLOCK <= '0'; -- No locking
M_AXI_AWVALID <= '0';
axi_dwr_done <= '0';
address_done := false;
data_done := false;
len := (others => '0');
wr_state <= idle;
else
case wr_state is
when idle =>
axi_wr_idle <= '1';
axi_dwr_done <= '0';
address_done := false;
data_done := false;
len := (others => '0');
if axi_dwr_start = '1' then
wr_state <= start;
axi_wr_idle <= '0';
axi_wr_resp <= "00";
end if;
when start =>
M_AXI_WLAST <= '0';
M_AXI_AWVALID <= '1';
M_AXI_AWADDR <= axi_dwr_addr;
M_AXI_AWLEN <= "000" & axi_dwr_len;
M_AXI_AWSIZE <= "0" & axi_dwr_size;
M_AXI_AWLOCK <= axi_dwr_exclusive;
axi_wvalid <= '1';
M_AXI_WVALID <= '1';
if axi_dwr_len = "00000" then
M_AXI_WLAST <= '1';
end if;
M_AXI_WSTRB <= axi_dwr_wstrb;
len := axi_dwr_len;
wr_state <= wait_on_ready;
when wait_on_ready =>
if M_AXI_AWREADY = '1' then
M_AXI_AWVALID <= '0';
address_done := true;
end if;
if M_AXI_WREADY = '1' then
if len = "00000" then
axi_wvalid <= '0';
M_AXI_WVALID <= '0';
data_done := true;
else
if len = "00001" then
M_AXI_WLAST <= '1';
end if;
len := std_logic_vector(unsigned(len) - 1);
end if;
end if;
if (address_done and data_done) then
wr_state <= wait_on_bchan;
end if;
when wait_on_bchan =>
if (M_AXI_BVALID = '1') then
wr_state <= idle;
axi_dwr_done <= '1';
axi_wr_resp <= M_AXI_BRESP;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process Wr_Executing;
axi_do_read <= axi_wvalid and M_AXI_WREADY;
M_AXI_WDATA <= axi_dwr_wdata;
end architecture IMP;
|
gpl-3.0
|
07cc391ca747a28013b1f31fa8b0402d
| 0.494876 | 3.590839 | false | false | false | false |
hoangt/PoC
|
tb/fifo/fifo_cc_got_tempgot_tb.vhdl
| 2 | 5,862 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO with Common Clock (cc) and Pipelined Interface
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
entity fifo_cc_got_tempgot_tb is
end entity;
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
architecture tb of fifo_cc_got_tempgot_tb is
-- component generics
constant D_BITS : positive := 8;
constant MIN_DEPTH : positive := 8;
constant ESTATE_WR_BITS : natural := 2;
constant FSTATE_RD_BITS : natural := 2;
constant ISPEC : string := "C C Cccccpppp pppp c ccc pp Cppppp ppp rp RpC";
constant OSPEC : string := "ggg gggggggg ggg G G";
-- Sequence Generator
constant GEN : bit_vector := "100110001";
constant ORG : std_logic_vector := "00000001";
-- Clock Control
signal rst : std_logic;
signal clk : std_logic := '0';
signal done : std_logic_vector(0 to 7) := (others => '0');
begin
clk <= not clk after 5 ns when done /= (done'range => '1') else '0';
genTests: for c in 0 to 7 generate
constant DATA_REG : boolean := c mod 2 > 0;
constant STATE_REG : boolean := c mod 4 > 1;
constant OUTPUT_REG : boolean := c mod 8 > 3;
signal put : std_logic;
signal putx : std_logic;
signal di : std_logic_vector(D_BITS-1 downto 0);
signal ful : std_logic;
signal commit : std_logic;
signal rollback : std_logic;
signal got : std_logic;
signal gotx : std_logic;
signal do : std_logic_vector(D_BITS-1 downto 0);
signal dox : std_logic_vector(D_BITS-1 downto 0);
signal vld : std_logic;
begin
putx <= put and not ful;
geni : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => putx,
mask => di
);
process
begin
rst <= '1';
wait until rising_edge(clk);
rst <= '0';
for i in ISPEC'range loop
put <= '0';
commit <= '0';
rollback <= '0';
case ISPEC(i) is
when ' ' =>
wait until rising_edge(clk);
when 'p' =>
put <= '1';
wait until rising_edge(clk) and ful = '0';
when 'c' =>
commit <= '1';
wait until rising_edge(clk);
when 'C' =>
put <= '1';
commit <= '1';
wait until rising_edge(clk) and ful = '0';
when 'r' =>
rollback <= '1';
wait until rising_edge(clk);
when 'R' =>
put <= '1';
rollback <= '1';
wait until rising_edge(clk) and ful = '0';
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
put <= '0';
commit <= '0';
wait;
end process;
DUT : entity PoC.fifo_cc_got_tempgot
generic map (
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
DATA_REG => DATA_REG,
STATE_REG => STATE_REG,
OUTPUT_REG => OUTPUT_REG,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
rst => rst,
clk => clk,
put => put,
din => di,
full => ful,
estate_wr => open,
commit => commit,
rollback => rollback,
got => got,
dout => do,
valid => vld,
fstate_rd => open
);
process
begin
for i in OSPEC'range loop
case OSPEC(i) is
when ' ' =>
got <= '0';
wait until rising_edge(clk);
when 'g' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do = dox report "Test #"&integer'image(c)&": Output Mismatch." severity error;
when 'G' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do /= dox report "Output Mismatch." severity error;
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
done(c) <= '1';
report "Test #"&integer'image(c)&" completed." severity note;
wait;
end process;
gotx <= got and vld;
geno : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => gotx,
mask => dox
);
end generate;
end tb;
|
apache-2.0
|
bf8e9746dcecb7a83e49bf304b202f1c
| 0.4971 | 3.905396 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sources_1/new/serialLoader.vhd
| 1 | 3,102 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 17:22:42
-- Design Name:
-- Module Name: serialLoader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity serialLoader is
Port (
--serial control data
S_Send : out STD_LOGIC:='0';
S_DataOut : out std_logic_vector (7 downto 0);
S_Ready : in STD_LOGIC;
--FIFO DATA
FIFO_Empty : in STD_LOGIC; -- flag if no data is left
FIFO_Data : in STD_LOGIC_VECTOR (7 downto 0); -- actual data
FIFO_ReadEn : out STD_LOGIC := '0'; -- enable read
-- global clock
clk : in STD_LOGIC;
reset: in STD_LOGIC
);
end serialLoader;
architecture Behavioral of serialLoader is
type state_type is ( STATE_WAIT, STATE_STARTREAD, STATE_ENDREAD, STATE_STARTWRITE, STATE_ENDWRITE, STATE_CLOCKIN);
signal state_reg: state_type := STATE_WAIT;
begin
process (clk, FIFO_Empty, S_Ready, reset) -- process to handle the next state
begin
if (reset = '1') then
--reset state:
FIFO_ReadEn <= '0';
S_Send <= '0';
state_reg <= STATE_WAIT;
else
if rising_edge (clk) then
case state_reg is
when STATE_WAIT =>
if (FIFO_Empty = '1' or S_Ready = '0') then
state_reg <= STATE_WAIT;
else
state_reg <= STATE_STARTREAD;
end if;
when STATE_STARTREAD =>
-- request the data
FIFO_ReadEn <= '1';
state_reg <= STATE_ENDREAD;
when STATE_ENDREAD =>
FIFO_ReadEn <= '0';
state_reg <= STATE_CLOCKIN;
when STATE_CLOCKIN =>
--clock the data out
S_DataOut <= FIFO_Data;
state_reg <= STATE_STARTWRITE;
when STATE_STARTWRITE =>
-- tell the serial module to pickup the data
S_Send <= '1';
state_reg <= STATE_ENDWRITE;
when STATE_ENDWRITE =>
-- close all the modules down
S_Send <= '0';
--if (FIFO_Empty = '0' and S_Ready = '1') then
-- state_reg <= STATE_STARTREAD;
--else
state_reg <= STATE_WAIT;
--end if;
when others =>
state_reg <= STATE_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
85ec970969e2267cd57d3b892a135f14
| 0.509994 | 4.260989 | false | false | false | false |
hoangt/PoC
|
src/mem/ocram/altera/ocram_esdp_altera.vhdl
| 2 | 5,290 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiate enhanced simple dual-port memory on Altera
-- FPGAs.
--
-- Description:
-- ------------------------------------
-- Quartus synthesis does not infer this RAM type correctly.
-- Instead, altsyncram is instantiated directly.
--
-- For further documentation see module "ocram_esdp"
-- (src/mem/ocram/ocram_esdp.vhdl).
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library altera_mf;
use altera_mf.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_esdp_altera is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_esdp_altera;
architecture rtl of ocram_esdp_altera is
component altsyncram
generic (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING;
wrcontrol_wraddress_reg_b : STRING
);
port (
clocken0 : in STD_LOGIC;
clocken1 : in STD_LOGIC;
wren_a : in STD_LOGIC;
clock0 : in STD_LOGIC;
wren_b : in STD_LOGIC;
clock1 : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (widthad_a-1 downto 0);
address_b : in STD_LOGIC_VECTOR (widthad_b-1 downto 0);
q_a : out STD_LOGIC_VECTOR (width_a-1 downto 0);
q_b : out STD_LOGIC_VECTOR (width_b-1 downto 0);
data_a : in STD_LOGIC_VECTOR (width_a-1 downto 0);
data_b : in STD_LOGIC_VECTOR (width_b-1 downto 0)
);
end component;
constant DEPTH : positive := 2**A_BITS;
constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME);
signal a1_sl : std_logic_vector(A_BITS-1 downto 0);
signal a2_sl : std_logic_vector(A_BITS-1 downto 0);
begin
a1_sl <= std_logic_vector(a1);
a2_sl <= std_logic_vector(a2);
mem : altsyncram
generic map (
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
indata_reg_b => "CLOCK1",
init_file => INIT_FILE,
intended_device_family => "Stratix",
lpm_type => "altsyncram",
numwords_a => DEPTH,
numwords_b => DEPTH,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
widthad_b => A_BITS,
width_a => D_BITS,
width_b => D_BITS,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE",
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
clock0 => clk1,
clock1 => clk2,
clocken0 => ce1,
clocken1 => ce2,
wren_a => we1,
wren_b => '0',
address_a => a1_sl,
address_b => a2_sl,
data_a => d1,
data_b => (others => '0'),
q_a => q1,
q_b => q2
);
end rtl;
|
apache-2.0
|
2c5c8b11c6ce16302be3cc2b1de1fbac
| 0.560113 | 2.976927 | false | false | false | false |
lowRISC/greth-library
|
greth_library/techmap/mem/ram32_tech.vhd
| 2 | 2,460 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific RAM selector
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity Ram32_tech is
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_tech is
component Ram32_inferred
generic (
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
-- micron 180 nm tech
component micron180_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
-- TODO: add there other ASIC components
begin
genmem0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
ram_infer : Ram32_inferred generic map
(
generic_kWords => generic_kWords
) port map
(
i_clk,
i_address,
i_wr_ena,
i_data,
o_data
);
end generate;
genmem1 : if generic_tech = micron180 generate
k4 : if generic_kWords = 4 generate
x0 : micron180_syncram
generic map (12, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
k8 : if generic_kWords = 8 generate
x0 : micron180_syncram
generic map (13, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
end generate;
end;
|
bsd-2-clause
|
d1ad09b63f48b0ba639dd160e09a6a31
| 0.571951 | 3.534483 | false | false | false | false |
hoangt/PoC
|
src/fifo/fifo_cc_got_tempgot.vhdl
| 2 | 13,813 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Module: FIFO, common clock (cc), pipelined interface,
-- reads only become effective after explicit commit
--
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- As uncommitted reads occupy FIFO space that is not yet available for
-- writing, an instance of this FIFO can, indeed, report 'full' and 'not vld'
-- at the same time. While a 'commit' would eventually make space available for
-- writing ('not ful'), a 'rollback' would re-iterate data for reading
-- ('vld').
--
-- 'commit' and 'rollback' are inclusive and apply to all reads ('got') since
-- the previous 'commit' or 'rollback' up to and including a potentially
-- simultaneous read.
--
-- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is
-- *undefined*!
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.ocram_sdp;
entity fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end fifo_cc_got_tempgot;
architecture rtl of fifo_cc_got_tempgot is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-- Commited Read Pointer (Commit Marker)
signal OPm : unsigned(A_BITS-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
OPm <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read or Rollback
if rollback = '1' then
OP0 <= OPm;
elsif re = '1' then
OP0 <= OP1;
end if;
-- Update Commit Marker
if commit = '1' then
if re = '1' then
OPm <= OP1;
else
OPm <= OP0;
end if;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(fulli, IP0, OP0, OPm)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
-- Available Space
if ESTATE_WR_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OPm); -- true number of valid entries
end if;
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
else
estate_wr <= (others => 'X');
end if;
-- Available Content
if FSTATE_RD_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
else
fstate_rd <= (others => 'X');
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
--
-- The STATE_REG generic is ignored as two different comparators are
-- needed to compare IP with OPm (full) and IP with OP (empty) anyways.
-- So the register implementation is always used.
blkState: block
signal Ful : std_logic := '0';
signal Pnd : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Pnd <= '0';
Avl <= '0';
else
-- Pending Indicator for uncommitted Data
if commit = '1' or rollback = '1' then
Pnd <= '0';
elsif re = '1' then
Pnd <= '1';
end if;
-- Update Full Indicator
if commit = '1' and (re = '1' or Pnd = '1') then
Ful <= '0';
elsif we = '1' and IP1 = OPm then
Ful <= '1';
end if;
-- Update Empty Indicator
if we = '1' or (rollback = '1' and Pnd = '1') then
Avl <= '1';
elsif re = '1' and we = '0' and OP1 = IP0 then
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end block;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
apache-2.0
|
958855d8a45de20fbbd8cdf7fc23a3f1
| 0.518063 | 3.95448 | false | false | false | false |
hoangt/PoC
|
src/mem/ocram/altera/ocram_sp_altera.vhdl
| 2 | 3,813 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiate single-port memory on Altera FPGAs.
--
-- Description:
-- ------------------------------------
-- Quartus synthesis does not infer this RAM type correctly.
-- Instead, altsyncram is instantiated directly.
--
-- For further documentation see module "ocram_sp"
-- (src/mem/ocram/ocram_sp.vhdl).
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library altera_mf;
use altera_mf.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sp_altera is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocram_sp_altera is
component altsyncram
generic (
address_aclr_a : STRING;
indata_aclr_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL;
wrcontrol_aclr_a : STRING
);
port (
clocken0 : in STD_LOGIC;
wren_a : in STD_LOGIC;
clock0 : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR(widthad_a-1 downto 0);
q_a : out STD_LOGIC_VECTOR(width_a-1 downto 0);
data_a : in STD_LOGIC_VECTOR(width_a-1 downto 0)
);
end component;
constant DEPTH : positive := 2**A_BITS;
constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME);
signal a_sl : std_logic_vector(A_BITS-1 downto 0);
begin
a_sl <= std_logic_vector(a);
mem : altsyncram
generic map (
address_aclr_a => "NONE",
indata_aclr_a => "NONE",
init_file => INIT_FILE,
intended_device_family => "Stratix",
lpm_hint => "ENABLE_RUNTIME_MOD = NO",
lpm_type => "altsyncram",
numwords_a => DEPTH,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
width_a => D_BITS,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
port map (
clocken0 => ce,
wren_a => we,
clock0 => clk,
address_a => a_sl,
data_a => d,
q_a => q
);
end architecture;
|
apache-2.0
|
4c8d4f155792def5350b470733fceee7
| 0.5754 | 3.164315 | false | false | false | false |
IAIK/ascon_hardware
|
asconv1/ascon_128_xlow_area/ascon_counter.vhdl
| 1 | 2,691 |
-------------------------------------------------------------------------------
-- Title : Ascon Counter
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_counter.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2014-05-20
-- Last update: 2014-05-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-20 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon_counter is
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CountEnablexSI : in std_logic;
CounterRoundxDO : out std_logic_vector(3 downto 0);
CounterFunctSelxDO : out std_logic_vector(2 downto 0);
CounterSubIterationxDO : out std_logic_vector(5 downto 0));
end entity ascon_counter;
architecture structural of ascon_counter is
signal CounterxDP : std_logic_vector(12 downto 0);
begin -- architecture structural
counter_reg_p: process (ClkxCI, RstxRBI) is
begin -- process counter_reg_p
if RstxRBI = '0' then -- asynchronous reset (active low)
CounterxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if CountEnablexSI = '1' then -- Count enable
CounterxDP <= std_logic_vector(unsigned(CounterxDP) + 1);
end if;
end if;
end process counter_reg_p;
CounterRoundxDO <= CounterxDP(12 downto 9);
CounterFunctSelxDO <= CounterxDP( 8 downto 6);
CounterSubIterationxDO <= CounterxDP( 5 downto 0);
end architecture structural;
|
apache-2.0
|
b1833d3222c7e9c2351ce484791bb4bd
| 0.545151 | 4.663778 | false | false | false | false |
FOSSEE/eSim
|
Examples/Mixed_Signal/custom_mixed_signal/customblock.vhdl
| 1 | 1,276 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity customblock is
port(C : in std_logic;
D : in std_logic;
Q : out std_logic);
end customblock;
architecture bhv of customblock is
signal count: integer:=1; --counts number of CLOCK cycles
signal period: integer:=10; --PWM signal period is 10 times of clock period
signal boost : integer:=9; --number of clock pulses during T_ON
signal buck : integer:=1; --number of clock pulses during T_OFF
begin
process (C,D)
begin
if(C='1' and C'event) then
count<=count+1;
if(count=period)then -- resets count for period
count<=1;
end if;
if(D='1') then --boost duty cycle when compartor output is high--
if(count<=boost)then
Q<='1';
elsif(count>boost) then
Q<='0';
end if;
end if;
if(D='0')then --buck duty cycle when compartor output is low--
if(count<=buck)then --
Q<='1';
elsif(count>buck)then
Q<='0';
end if;
end if;
end if;
end process;
end bhv;
|
gpl-3.0
|
6e74926d249edd559ff0d306f57bfc4a
| 0.512539 | 3.9875 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/pselect_mask.vhd
| 4 | 7,017 |
-------------------------------------------------------------------------------
-- pselect_mask.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
architecture imp of pselect_mask is
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
CS <= Valid when A_Bus=BAR else '0';
end imp;
|
gpl-3.0
|
e38b05dbb5615d99d2ff34e7c61dd2a0
| 0.528003 | 4.28912 | false | false | false | false |
hoangt/PoC
|
src/fifo/fifo_shift.vhdl
| 2 | 3,592 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Entity: fifo_shift
--
-- Module: FIFO, common clock, pipelined interface
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- This FIFO implementation is based on an internal shift register. This is
-- especially useful for smaller FIFO sizes, which can be implemented in LUT
-- storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is
-- maintained, which determines the number of valid entries within the
-- underlying shift register.
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use Poc.utils.all;
entity fifo_shift is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end fifo_shift;
library IEEE;
use IEEE.numeric_std.all;
library poc;
use poc.utils.all;
architecture rtl of fifo_shift is
-- Data Register
type tData is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal Dat : tData(0 to MIN_DEPTH-1);
signal Ptr : unsigned(log2ceilnz(MIN_DEPTH) downto 0);
begin
-- Data anf Pointer Registers
process(clk)
begin
if clk'event and clk = '1' then
if put = '1' then
Dat <= din & Dat(0 to MIN_DEPTH-2);
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
Ptr <= (others => '0');
else
if put /= got then
if put = '1' then
Ptr <= Ptr - 1;
else
Ptr <= Ptr + 1;
end if;
end if;
end if;
end if;
end process;
-- Outputs
dout <= Dat(to_integer(not Ptr(Ptr'left-1 downto 0)));
vld <= Ptr(Ptr'left);
ful <= '1' when ((not Ptr(Ptr'left-1 downto 0)) and to_unsigned(MIN_DEPTH-1, Ptr'length-1)) = MIN_DEPTH-1 else '0';
end rtl;
|
apache-2.0
|
62d7e4a849c26812d6c6720b5060d5ee
| 0.571548 | 3.955947 | false | false | false | false |
BogdanArdelean/FPWAM
|
hardware/src/hdl/TrailUnit.vhd
| 1 | 1,732 |
-------------------------------------------------------------------------------
-- FILE NAME : TrailUnit.vhd
-- MODULE NAME : TrailUnit
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that executes the trail(a) WAM ancillary operation
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity TrailUnit is
generic
(
kAddressWidth : natural := kWamAddressWidth
);
port
(
trail : in std_logic;
trail_address : in std_logic_vector(kAddressWidth -1 downto 0);
H : in std_logic_vector(kAddressWidth -1 downto 0);
HB : in std_logic_vector(kAddressWidth -1 downto 0);
B : in std_logic_vector(kAddressWidth -1 downto 0);
a : out std_logic_vector(kAddressWidth -1 downto 0);
do_trail : out std_logic
);
end TrailUnit;
architecture Behavioral of TrailUnit is
begin
a <= trail_address;
DOTRAIL: process(trail, trail_address, H, HB, B)
begin
do_trail <= '0';
if trail = '1' then
if (unsigned(trail_address) < unsigned(HB))
or ((unsigned(H) < unsigned(trail_address)) and (unsigned(trail_address) < unsigned(B))) then
do_trail <= '1';
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
f3d9e80049579f1c7e6fa0f680468831
| 0.507506 | 4.340852 | false | false | false | false |
hoangt/PoC
|
src/io/ddrio/ddrio_out.vhdl
| 2 | 3,378 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Chip-Specific DDR Output Registers
--
-- Description:
-- ------------------------------------
-- Instantiates chip-specific DDR output registers.
--
-- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if
-- necessary. If an output enable is not required, you may save some logic by
-- setting NO_OUTPUT_ENABLE = true. However, "OutputEnable" must be set to '1'.
--
-- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with
-- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought
-- out with this rising edge. "DataOut_low" is brought out with the falling
-- edge.
--
-- "Pad" must be connected to a PAD because FPGAs only have these registers in
-- IOBs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.config.all;
use PoC.ddrio.all;
entity ddrio_out is
generic (
NO_OUTPUT_ENABLE : BOOLEAN := false;
BITS : POSITIVE;
INIT_VALUE : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_out is
begin
assert (VENDOR = VENDOR_XILINX) or (VENDOR = VENDOR_ALTERA)
report "PoC.io.ddrio.out is not implemented for given DEVICE."
severity FAILURE;
genXilinx : if (VENDOR = VENDOR_XILINX) generate
i : ddrio_out_xilinx
generic map (
NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE,
BITS => BITS,
INIT_VALUE => INIT_VALUE
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
OutputEnable => OutputEnable,
DataOut_high => DataOut_high,
DataOut_low => DataOut_low,
Pad => Pad
);
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
i : ddrio_out_altera
generic map (
BITS => BITS
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
OutputEnable => OutputEnable,
DataOut_high => DataOut_high,
DataOut_low => DataOut_low,
Pad => Pad
);
end generate;
end architecture;
|
apache-2.0
|
0c8784664054303542d3b2bc04c2569a
| 0.615157 | 3.570825 | false | false | false | false |
hoangt/PoC
|
src/arith/arith_prefix_or.vhdl
| 2 | 2,917 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix OR computation: y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- ================================================================================
-- Copyright 2007-2015 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
library poc;
use poc.config.all;
entity arith_prefix_or is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_or;
architecture rtl of arith_prefix_or is
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) or x(1);
gen2: if N > 2 generate
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
s <= std_logic_vector(('1' & p) - 1);
y(N-1 downto 2) <= s(N downto 3) xnor ('1' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
component MUXCY
port (
S : in std_logic;
DI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
constant d : std_logic_vector(N-2 downto 0) := (N-2 downto 1 => '1') & '0';
signal c : std_logic_vector(N-1 downto 0);
begin
p(N-1 downto 2) <= not unsigned(x(N-1 downto 2));
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : MUXCY
port map (
S => p(i),
DI => d(i-1),
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
|
apache-2.0
|
2d807ae4088ac1a13d0f78c799b95f5a
| 0.580933 | 3.276404 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl_hs/AEAD.vhd
| 1 | 2,982 |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Entity of authenticated encryption unit.
--! User should modify the default generics based on the
--! design requirements of a target archtiecture of the
--! implemented cipher.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features parameters
G_ENABLE_PAD : boolean := False; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! Padding options
G_PAD_STYLE : integer := 0; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
|
apache-2.0
|
36bc8d43506286744c39247d8346302b
| 0.502349 | 4.441133 | false | false | false | false |
JoseHawk/Signal_Generator
|
Generador de señales/ROM_Seno.vhd
| 1 | 5,369 |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom
-- ============================================================
-- File Name: ROM_Seno.vhd
-- Megafunction Name(s):
-- lpm_rom
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY ROM_Seno IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ROM_Seno;
ARCHITECTURE SYN OF rom_seno IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_rom
GENERIC (
intended_device_family : STRING;
lpm_address_control : STRING;
lpm_file : STRING;
lpm_outdata : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthad : NATURAL
);
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
lpm_rom_component : lpm_rom
GENERIC MAP (
intended_device_family => "FLEX10K",
lpm_address_control => "REGISTERED",
lpm_file => "seno.mif",
lpm_outdata => "UNREGISTERED",
lpm_type => "LPM_ROM",
lpm_width => 8,
lpm_widthad => 8
)
PORT MAP (
address => address,
inclock => inclock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "FLEX10K"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "seno.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: OutputRegistered NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAdd NUMERIC "1"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "FLEX10K"
-- Retrieval info: CONSTANT: LPM_ADDRESS_CONTROL STRING "REGISTERED"
-- Retrieval info: CONSTANT: LPM_FILE STRING "seno.mif"
-- Retrieval info: CONSTANT: LPM_OUTDATA STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ROM"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "8"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: CONNECT: @address 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Seno_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-2.0
|
dc3e3f6aec8d3b5d49b46959cec18108
| 0.666791 | 3.66735 | false | false | false | false |
hoangt/PoC
|
src/misc/sync/sync_Reset_Altera.vhdl
| 2 | 3,095 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Reset_Altera
--
-- Description:
-- ------------------------------------
-- This is a clock-domain-crossing circuit for reset signals optimized for
-- Altera FPGAs. It infers 2 flip flops with asynchronous preset and notifies
-- Quartus II, that these flip flops are synchronizer flip flops. If you need
-- a platform independent version of this synchronizer, please use
-- 'PoC.misc.sync.sync_Reset', which internally instantiates this module if
-- a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for reset signals.
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Reset_Altera is
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC; -- Data to be synchronized
Output : out STD_LOGIC -- synchronised data
);
end entity;
architecture rtl of sync_Reset_Altera is
attribute altera_attribute : STRING;
attribute preserve : BOOLEAN;
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := '1';
signal Data_sync : STD_LOGIC := '1';
-- Apply a SDC constraint to meta stable flip flop
--attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to *|sync_Reset_Altera:*|Data_meta """;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute altera_attribute of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
-- preserve both registers (no optimization, shift register extraction, ...)
attribute preserve of Data_meta : signal is TRUE;
attribute preserve of Data_sync : signal is TRUE;
begin
Data_async <= '0';
process(Clock)
begin
if (Input = '1') then
Data_meta <= '1';
Data_sync <= '1';
elsif rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output <= Data_sync;
end architecture;
|
apache-2.0
|
aa9edde036de3af27fa906bfa1d501e4
| 0.639742 | 3.825711 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/shared_ram_ivar.vhd
| 4 | 8,678 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
gpl-3.0
|
699e53be154a7c002dc57ed9483b3cbe
| 0.478682 | 4.799779 | false | false | false | false |
hoangt/PoC
|
tb/mem/lut/lut_Sine_tb.vhdl
| 2 | 3,864 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for sine wave LUT
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity lut_Sine_tb is
end;
architecture test of lut_Sine_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
signal Clock1 : STD_LOGIC := '1';
signal sim_Stop : STD_LOGIC := '0';
signal lut_in : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal lut_Q1_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q1_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q2_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q2_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q3_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q3_out : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q4_in : STD_LOGIC_VECTOR(7 downto 0);
signal lut_Q4_out : STD_LOGIC_VECTOR(7 downto 0);
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= (Clock1 xnor sim_Stop) after CLOCK_1_PERIOD / 2;
end process;
process
begin
wait for 4 * CLOCK_1_PERIOD;
for i in 0 to 1024 loop
lut_in <= to_slv(i, lut_in'length);
wait for CLOCK_1_PERIOD;
end loop;
wait for 4 * CLOCK_1_PERIOD;
sim_Stop <= '1';
wait;
end process;
lut_Q1_in <= lut_in;
lut_Q2_in <= lut_in;
lut_Q3_in <= lut_in;
lut_Q4_in <= lut_in;
lutQ1 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 1
)
port map (
Clock => Clock1, --
Input => lut_Q1_in, --
Output => lut_Q1_out --
);
lutQ2 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 2
)
port map (
Clock => Clock1, --
Input => lut_Q2_in, --
Output => lut_Q2_out --
);
lutQ3 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 0.0,
QUARTERS => 4
)
port map (
Clock => Clock1, --
Input => lut_Q3_in, --
Output => lut_Q3_out --
);
lutQ4 : entity PoC.lut_Sine
generic map (
REG_OUTPUT => TRUE,
MAX_AMPLITUDE => 127,
POINTS => 256,
OFFSET_DEG => 45.0,
QUARTERS => 4
)
port map (
Clock => Clock1, --
Input => lut_Q4_in, --
Output => lut_Q4_out --
);
end;
|
apache-2.0
|
8695196cf61cf656381b863c994d5ac6
| 0.52795 | 3.047319 | false | false | false | false |
hoangt/PoC
|
src/io/ddrio/ddrio_in.vhdl
| 2 | 3,256 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Chip-Specific DDR Input Registers
--
-- Description:
-- ------------------------------------
-- Instantiates chip-specific DDR input registers.
--
-- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if
-- necessary. If an output enable is not required, you may save some logic by
-- setting NO_OUTPUT_ENABLE = true. However, "OutputEnable" must be set to '1'.
--
-- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with
-- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought
-- out with this rising edge. "DataOut_low" is brought out with the falling
-- edge.
--
-- "Pad" must be connected to a PAD because FPGAs only have these registers in
-- IOBs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.config.all;
use PoC.ddrio.all;
entity ddrio_in is
generic (
BITS : POSITIVE;
INIT_VALUE_HIGH : BIT_VECTOR := "1";
INIT_VALUE_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_in is
begin
assert (VENDOR = VENDOR_XILINX)-- or (VENDOR = VENDOR_ALTERA)
report "PoC.io.ddrio.in is not implemented for given DEVICE."
severity FAILURE;
genXilinx : if (VENDOR = VENDOR_XILINX) generate
i : ddrio_in_xilinx
generic map (
BITS => BITS,
INIT_VALUE_HIGH => INIT_VALUE_IN_HIGH,
INIT_VALUE_LOW => INIT_VALUE_IN_LOW
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
DataIn_high => DataIn_high,
DataIn_low => DataIn_low,
Pad => Pad
);
end generate;
-- genAltera : if (VENDOR = VENDOR_ALTERA) generate
-- i : ddrio_in_altera
-- generic map (
-- WIDTH => WIDTH
-- )
-- port map (
-- clk => clk,
-- ce => ce,
-- dh => dh,
-- dl => dl,
-- oe => oe,
-- q => q
-- );
-- end generate;
end architecture;
|
apache-2.0
|
97eab9ffd69968b84f510e6b8ce44eb0
| 0.599816 | 3.409424 | false | false | false | false |
wrousseau/a14-2-vhdl
|
test_bench.vhd
| 1 | 2,940 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:29 10/21/2014
-- Design Name:
-- Module Name: /auto/d/diallo/Cours/3A/A14/A14-2/project/dev/vhdl/test_bench.vhd
-- Project Name: vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: filter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_bench IS
END test_bench;
ARCHITECTURE arc1 OF test_bench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Filter is
PORT(
clk : in STD_LOGIC;
R0 : in STD_LOGIC_VECTOR (31 downto 0);
R1 : in STD_LOGIC_VECTOR (31 downto 0);
R2 : in STD_LOGIC_VECTOR (31 downto 0);
R3 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT Filter;
--Inputs
signal clk : STD_LOGIC := '0';
signal R0 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal R1 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal R2 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
--Outputs
signal R3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
theFilter : Filter PORT MAP (
clk => clk,
R0 => R0,
R1 => R1,
R2 => R2,
R3 => R3
);
-- Clock process definitions
clk_process : PROCESS
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: PROCESS is
BEGIN
-- hold reset state for 100 ns.
--wait for 100 ns;
-- Black-White line 11111111000000001111111100000000
-- White-Black line 00000000111111110000000011111111
R0 <= "00000000000000000000000000000000";
R1 <= "10100010101000101010001010100010";
R2 <= "00111010101100100000011010001110";
wait on clk;
R0 <= R1;
R1 <= R2;
R2 <= "11111111000000001111111100000000";
wait on clk;
R0 <= R1;
R1 <= R2;
R2 <= "00000000111111110000000011111111";
wait on clk;
R0 <= R1;
R1 <= R2;
R2 <= "00000000000000000000000000000000";
END PROCESS;
END;
|
apache-2.0
|
c0c272c7cb338ff8ca0d806b0fee0914
| 0.610204 | 3.656716 | false | true | false | false |
hoangt/PoC
|
src/arith/arith_div.vhdl
| 2 | 7,093 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: Implementation of a Non-Performing restoring divider with a configurable radix.
-- For detailed documentation see below.
--
-- Authors: Thomas B. Preusser
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library poc;
USE PoC.utils.ALL;
entity arith_div is
generic (
N : positive;-- := 32; -- Operand /Result Bit Widths
RAPOW : positive;-- := 1; -- Power of Radix used (2**RAPOW)
REGISTERED : boolean -- := false -- Output is registered
);
port (
-- Global Reset/Clock
clk : in std_logic;
rst : in std_logic;
-- Ready / Start
start : in std_logic;
rdy : out std_logic;
-- Arguments / Result (2's complement)
arg1, arg2 : in std_logic_vector(N-1 downto 0);
res : out std_logic_vector(N-1 downto 0)
);
end arith_div;
-------------------------------------------------------------------------------
-- Implementation of a Non-Performing Restoring Divider
--
-- Multi-Cycle division controlled by 'start' / 'rdy'. A new division can be
-- started, if 'rdy' = '1'. The result is available if 'rdy' is '1' again.
--
-- Note that the registered version is no slower than the unregistered one
-- as the conversion to a negative result is performed on-the-fly. It is,
-- however, somewhat more expensive as illustrated below.
--
-- Synthesis Costs of the differing feasible configurations:
--
-- Baseline values of Radix-2 unregistered configuration per 2009-12-08.
-- XST: Optimization Goal AREA
--
-- Radix 2 4 8
-- Registered
--
-- no 134 -2 -2 Flip Flops
-- 244 +95 +189 LUT4
--
-- yes +30 +26 +24 Flip Flops
-- +1 +97 +189 LUT4
--
--
-------------------------------------------------------------------------------
architecture div_npr of arith_div is
-- Constants
constant STEPS : positive := (N+RAPOW-1)/RAPOW; -- Number of Iteration Steps
-- State
signal Exec : std_logic; -- Operation is being executed
-- Argument/Result Registers
signal A : unsigned(N -1 downto 0); -- Dividend
signal B : unsigned(N+RAPOW*(STEPS-1)-1 downto 0); -- Divisor
signal S : std_logic; -- Quotient Sign
signal An : unsigned(N -1 downto 0); -- Next Residue Value
signal dn : unsigned(RAPOW-1 downto 0); -- Next Quotient Digit
-- Iteration Counter
signal Cnt : unsigned(1 to log2ceil(STEPS));
signal CntDD : unsigned(1 to log2ceil(STEPS)); -- Cnt - 1
signal CntEx0 : std_logic; -- Cnt = 0
begin -- div_npr
-- Registers
process(clk)
begin
if clk'event and clk = '1' then
-- Reset
if rst = '1' then
Exec <= '0';
-- Iteration Step
elsif Exec = '1' then
Cnt <= CntDD;
A <= An;
B <= (1 to RAPOW => '0') & B(B'LEFT downto RAPOW);
if CntEx0 = '1' then
Exec <= '0';
end if;
-- Operation Initialization
elsif start = '1' then
Exec <= '1';
if arg1(N-1) = '0' then
A <= unsigned(arg1);
else
A <= 0 - unsigned(arg1);
end if;
if arg2(N-1) = '0' then
B(B'LEFT downto (STEPS-1)*RAPOW) <= unsigned(arg2);
else
B(B'LEFT downto (STEPS-1)*RAPOW) <= 0 - unsigned(arg2);
end if;
B((STEPS-1)*RAPOW-1 downto 0) <= (others => '0');
S <= arg1(N-1) xor arg2(N-1);
Cnt <= to_unsigned(STEPS-1, log2ceil(STEPS));
end if;
end if;
end process;
rdy <= not Exec;
-- Counter Logic
CntDD <= Cnt - 1;
CntEx0 <= not Cnt(Cnt'LEFT) and CntDD(CntDD'LEFT);
-- Subtractor
blkSub: block
subtype tData is unsigned(N-1 downto 0);
subtype tDatx is unsigned(N downto 0);
type tDataArr is array (natural range<>) of tData;
type tDatxArr is array (natural range<>) of tDatx;
signal rng : std_logic_vector(RAPOW-1 downto 0); -- B beyond Range
signal di : tDatxArr(RAPOW-1 downto 0);
signal Ai : tDataArr(RAPOW downto 0);
begin
-- Calculate Ranges
rng(0) <= '1' when B(B'LEFT downto N) /= (B'LEFT downto N => '0') else '0';
lr: for i in 1 to RAPOW-1 generate
rng(i) <= rng(i-1) or B(N-i);
end generate lr;
-- Speculative Subtractions
Ai(RAPOW) <= A;
ls: for i in RAPOW-1 downto 0 generate
ieq0: if i = 0 generate
di(i) <= ('0' & Ai(i+1)) - ('0' & B(N-1 downto 0));
end generate ieq0;
ine0: if i /= 0 generate
di(i) <= ('0' & Ai(i+1)) - ('0' & B(N-i-1 downto 0) & (1 to i => '0'));
end generate ine0;
dn(i) <= not(rng(i) or di(i)(N));
Ai(i) <= di(i)(N-1 downto 0) when dn(i) = '1' else Ai(i+1);
end generate ls;
An <= Ai(0);
end block blkSub;
-- Quotient Composition
gNRG: if not REGISTERED generate
blkOut: block
signal Q : unsigned(N-1 downto 0); -- Quotient
begin
process(clk)
begin
if clk'event and clk = '1' then
if Exec = '1' then
Q <= Q(N-RAPOW-1 downto 0) & (dn xor (1 to RAPOW => S));
end if;
end if;
end process;
res <= std_logic_vector(Q + ("0" & S));
end block blkOut;
end generate gNRG;
gREG: if REGISTERED generate
blkOut: block
signal Q : unsigned(N -1 downto 0); -- Quotient
signal Qm1 : unsigned(N-RAPOW-1 downto 0); -- Quotient - 1
signal dnx : unsigned( RAPOW downto 0); -- (not dn) + 1
begin
dnx <= ('0' & not dn) + 1;
process(clk)
begin
if clk'event and clk = '1' then
if Exec = '1' then
if S = '0' then
Q <= Q(N-RAPOW-1 downto 0) & dn;
else
if dnx(RAPOW) = '1' then
Q(N-1 downto RAPOW) <= Q (N-RAPOW-1 downto 0);
else
Q(N-1 downto RAPOW) <= Qm1(N-RAPOW-1 downto 0);
end if;
Q(RAPOW-1 downto 0) <= dnx(RAPOW-1 downto 0);
Qm1 <= Qm1(N-2*RAPOW-1 downto 0) & not dn;
end if;
end if;
end if;
end process;
res <= std_logic_vector(Q);
end block blkOut;
end generate gREG;
end div_npr;
|
apache-2.0
|
4ef5c118196b5f1a69fdb977b4f4be61
| 0.557107 | 3.194595 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/emc.vhd
| 4 | 73,849 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: emc.vhd
-- Version: v2.1
-- Description: Common interface for External Memory Controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 03/01/08 First Version
-- ^^^^^^^^^^
-- This file is based on version v3_01_c updated to fixed CR #466745: -
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE. The same generic is mapped to
-- component io_registers from emc_common_v3_03_a.
-- ~~~~~~~~~
-- NSK 03/12/08 Updated
-- ^^^^^^^^
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE in comment "Definition of Generics"
-- section.
-- ~~~~~~~~
-- NSK 03/03/08 Updated
-- ^^^^^^^^
-- 1. Removed generic C_MEM_DQ_CAPTURE_NEGEDGE.
-- 2. Added the port RdClk used as clock to capture the data from memory.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_03_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
--
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
--
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 03/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 03/11/11 version v5_03_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- emc_common_v3_0 library is used for emc_common component declarations
-------------------------------------------------------------------------------
library emc_common_v3_0;
use emc_common_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_IPIF_DWIDTH -- Width of processor data bus
-- C_IPIF_AWIDTH -- Width of processor address bus
-- C_MEM(0:3)_BASEADDR -- Memory bank (0:3) base address
-- C_MEM(0:3)_HIGHADDR -- Memory bank (0:3) high address
-- C_INCLUDE_NEGEDGE_IOREGS -- Include negative edge IO registers
-- C_PAGEMODE_FLASH_(0:3) -- Whether a PAGE MODE Flash device is used
-- C_MEM(0:3)_WIDTH -- Width of memory bank's data bus
-- C_MAX_MEM_WIDTH -- Maximum width of memory data bus
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3) -- Include datawidth matching logic for
-- -- memory bank
-- C_BUS_CLOCK_PERIOD_PS -- Bus clock period to calculate wait
-- state pulse widths.
-- C_SYNCH_MEM_(0:3) -- Memory bank is synchronous
-- C_TCEDV_PS_MEM_(0:3) -- Chip Enable to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TAVDV_PS_MEM_(0:3) -- Address Valid to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TPACC_PS_FLASH_(0:3) -- Address Valid to Data Valid Time
-- -- for a PAGE Read for a PAGE MODE Flash
-- C_THZCE_PS_MEM_(0:3) -- Chip Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_THZOE_PS_MEM_(0:3) -- Output Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_TWC_PS_MEM_(0:3) -- Write Cycle Time
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TWP_PS_MEM_(0:3) -- Write Enable Minimum Pulse Width
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TLZWE_PS_MEM_(0:3) -- Write Enable High to Data Bus Low
-- Impedance (Applied as Write Recovery
-- before Read)
-- C_WR_REC_TIME_MEM_(0:3) -- Write recovery time between the write
-- -- and next consecutive read transaction
-- Definition of Ports:
--
-- Bus2IP_Clk -- System clock
-- RdClk -- Read Clock
-- Bus2IP_Reset -- System Reset
--
-- Bus and IPIC Interface signals
-- Bus2IP_Addr -- Processor bus address
-- Bus2IP_BE -- Processor bus byte enables
-- Bus2IP_Data -- Processor data
-- Bus2IP_RNW -- Processor read not write
-- Bus2IP_Burst -- Processor burst
-- Bus2IP_WrReq -- Processor write request
-- Bus2IP_RdReq -- Processor read request
-- Bus2IP_Mem_CS -- Memory address range is being accessed
--
-- EMC to bus signals
-- IP2Bus_Data -- Data to processor bus
-- IP2Bus_errAck -- Error acknowledge
-- IP2Bus_retry -- Retry indicator
-- IP2Bus_toutSup -- Suppress watch dog timer
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_AddrAck -- Read/Write Address acknowledge
--
-- Memory signals
-- Mem_A -- Memory address inputs
-- Mem_DQ_I -- Memory input data bus
-- Mem_DQ_O -- Memory output data bus
-- Mem_DQ_T -- Memory data output enable
-- Mem_CEN -- Memory chip select
-- Mem_OEN -- Memory output enable
-- Mem_WEN -- Memory write enable
-- Mem_QWEN -- Memory qualified write enable
-- Mem_BEN -- Memory byte enables
-- Mem_RPN -- Memory reset/power down
-- Mem_CE -- Memory chip enable
-- Mem_ADV_LDN -- Memory counter advance/load (=0)
-- Mem_LBON -- Memory linear/interleaved burst order (=0)
-- Mem_CKEN -- Memory clock enable (=0)
-- Mem_RNW -- Memory read not write
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity EMC is
generic (
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_IPIF_DWIDTH : integer := 32;
C_IPIF_AWIDTH : integer := 32;
C_MEM0_BASEADDR : std_logic_vector := x"30000000";
C_MEM0_HIGHADDR : std_logic_vector := x"3000ffff";
C_MEM1_BASEADDR : std_logic_vector := x"40000000";
C_MEM1_HIGHADDR : std_logic_vector := x"4000ffff";
C_MEM2_BASEADDR : std_logic_vector := x"50000000";
C_MEM2_HIGHADDR : std_logic_vector := x"5000ffff";
C_MEM3_BASEADDR : std_logic_vector := x"60000000";
C_MEM3_HIGHADDR : std_logic_vector := x"6000ffff";
C_INCLUDE_NEGEDGE_IOREGS : integer := 0;
C_PAGEMODE_FLASH_0 : integer := 0;
C_PAGEMODE_FLASH_1 : integer := 0;
C_PAGEMODE_FLASH_2 : integer := 0;
C_PAGEMODE_FLASH_3 : integer := 0;
C_MEM0_WIDTH : integer range 8 to 64 := 32;
C_MEM1_WIDTH : integer range 8 to 64 := 32;
C_MEM2_WIDTH : integer range 8 to 64 := 32;
C_MEM3_WIDTH : integer range 8 to 64 := 32;
C_MAX_MEM_WIDTH : integer range 8 to 64 := 32;
C_MEM0_TYPE : integer range 0 to 5 := 0;
C_MEM1_TYPE : integer range 0 to 5 := 0;
C_MEM2_TYPE : integer range 0 to 5 := 0;
C_MEM3_TYPE : integer range 0 to 5 := 0;
C_PARITY_TYPE_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_3 : integer range 0 to 2 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer := 0;
C_BUS_CLOCK_PERIOD_PS : integer := 10000;
-- Memory Channel 0 Timing Parameters
C_SYNCH_MEM_0 : integer := 0;
--C_SUPPORT_SYNC_RD_0 : integer := 0;
C_SYNCH_PIPEDELAY_0 : integer := 2;
C_TCEDV_PS_MEM_0 : integer := 15000;
C_TAVDV_PS_MEM_0 : integer := 15000;
C_TPACC_PS_FLASH_0 : integer := 25;
C_THZCE_PS_MEM_0 : integer := 7000;
C_THZOE_PS_MEM_0 : integer := 7000;
C_TWC_PS_MEM_0 : integer := 15000;
C_TWP_PS_MEM_0 : integer := 12000;
C_TWPH_PS_MEM_0 : integer := 12000;
C_TLZWE_PS_MEM_0 : integer := 0;
C_WR_REC_TIME_MEM_0 : integer := 100000;
-- Memory Channel 1 Timing Parameters
C_SYNCH_MEM_1 : integer := 0;
--C_SUPPORT_SYNC_RD_1 : integer := 0;
C_SYNCH_PIPEDELAY_1 : integer := 2;
C_TCEDV_PS_MEM_1 : integer := 15000;
C_TAVDV_PS_MEM_1 : integer := 15000;
C_TPACC_PS_FLASH_1 : integer := 25000;
C_THZCE_PS_MEM_1 : integer := 7000;
C_THZOE_PS_MEM_1 : integer := 7000;
C_TWC_PS_MEM_1 : integer := 15000;
C_TWP_PS_MEM_1 : integer := 12000;
C_TWPH_PS_MEM_1 : integer := 12000;
C_TLZWE_PS_MEM_1 : integer := 0;
C_WR_REC_TIME_MEM_1 : integer := 100000;
-- Memory Channel 2 Timing Parameters
C_SYNCH_MEM_2 : integer := 0;
--C_SUPPORT_SYNC_RD_2 : integer := 0;
C_SYNCH_PIPEDELAY_2 : integer := 2;
C_TCEDV_PS_MEM_2 : integer := 15000;
C_TAVDV_PS_MEM_2 : integer := 15000;
C_TPACC_PS_FLASH_2 : integer := 25000;
C_THZCE_PS_MEM_2 : integer := 7000;
C_THZOE_PS_MEM_2 : integer := 7000;
C_TWC_PS_MEM_2 : integer := 15000;
C_TWP_PS_MEM_2 : integer := 12000;
C_TWPH_PS_MEM_2 : integer := 12000;
C_TLZWE_PS_MEM_2 : integer := 0;
C_WR_REC_TIME_MEM_2 : integer := 100000;
-- Memory Channel 3 Timing Parameters
C_SYNCH_MEM_3 : integer := 0;
--C_SUPPORT_SYNC_RD_3 : integer := 0;
C_SYNCH_PIPEDELAY_3 : integer := 2;
C_TCEDV_PS_MEM_3 : integer := 15000;
C_TAVDV_PS_MEM_3 : integer := 15000;
C_TPACC_PS_FLASH_3 : integer := 25000;
C_THZCE_PS_MEM_3 : integer := 7000;
C_THZOE_PS_MEM_3 : integer := 7000;
C_TWC_PS_MEM_3 : integer := 15000;
C_TWP_PS_MEM_3 : integer := 12000;
C_TWPH_PS_MEM_3 : integer := 12000;
C_TLZWE_PS_MEM_3 : integer := 0 ;
C_WR_REC_TIME_MEM_3 : integer := 100000
);
port (
Bus2IP_Clk : in std_logic;
RdClk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus and IPIC Interface signals
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Burst : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_BurstLength : in std_logic_vector (0 to 7);
Linear_flash_brst_rd_flag : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
IP2Bus_errAck : out std_logic;
IP2Bus_retry : out std_logic;
IP2Bus_toutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_AddrAck : out std_logic;
parity_error_adrss : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
parity_error_mem : out std_logic_vector(0 to 1);
Type_of_xfer : in std_logic;
psram_page_mode : in std_logic;
original_wrce : in std_logic;
Mem_DQ_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PRTY_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_A : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic;
Cre_reg_en : in std_logic;
Mem_WAIT : in std_logic;
Synch_mem12 : out std_logic;
last_addr1 : in std_logic;
pr_idle : out std_logic; -- 11-12-2012
axi_trans_size_reg : in std_logic_vector(1 downto 0); -- 1/3/2013
axi_wvalid : in std_logic;
axi_wlast : in std_logic;
axi_arsize : in std_logic_vector(2 downto 0);
Parity_err : out std_logic
);
end entity EMC;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of EMC is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Data Types
-------------------------------------------------------------------------------
type EMC_ARRAY_TYPE is array (0 to 3) of integer;
-- type EMC_ARRAY_TYPE is array (0 to C_NUM_BANKS_MEM-1) of integer;
type INTEGER_ARRAY is array (natural range <>) of integer;
type MEM_ADDR_ARRAY is array (0 to C_NUM_BANKS_MEM-1) of
std_logic_vector(0 to C_IPIF_AWIDTH-1);
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- not_all_zeros()
-------------------------------------------------------------------------------
function not_all_zeros(input_array : EMC_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 16 := 0;
begin
for i in 0 to num_real_elements -1 loop
sum := sum + input_array(i);
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_zeros;
--------------------------------------------------------------------------------
function check_flash_mem(input_array : EMC_ARRAY_TYPE; -- 9/7/2011
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 10 := 0;
begin
for i in 0 to num_real_elements -1 loop
if(input_array(i) = 2)or
(input_array(i) = 3)or
(input_array(i) = 5)or
(input_array(i) = 4)then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function check_flash_mem;
-- --------------------------------------------------------------------------------
-- -- flash_supports_sync_rd: below function is used to check if any of the memories in the assigned
-- -- memory location is of Linear Flash which supports Sync Burst Read mode
-- --------------------------------------------------------------------------------
-- function flash_supports_sync_rd (input_flash_array : EMC_ARRAY_TYPE;
-- num_of_mem_banks : integer)
-- return integer is
-- variable flash_sync_rd : integer range 0 to 1 := 0;
-- begin
-- for i in 0 to num_of_mem_banks -1 loop
-- flash_sync_rd := flash_sync_rd + input_flash_array(i);
-- end loop;
--
-- if flash_sync_rd = 0 then
-- return 0;
-- else
-- return 1;
-- end if;
-- end function flash_supports_sync_rd;
-- -------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- minimum memory data width supported is 8 bits
constant MIN_MEM_WIDTH : integer := 8;
-- address offset
constant ADDR_OFFSET : integer range 0 to 4
:= log2(C_IPIF_DWIDTH/8);
constant ADDR_CNTR_WIDTH : integer range 1 to 5
:= max2(1,log2(C_IPIF_DWIDTH/8));
-- create arrays of generics for use in functions
constant SYNCH_MEM_ARRAY : EMC_ARRAY_TYPE :=
(C_SYNCH_MEM_0,
C_SYNCH_MEM_1,
C_SYNCH_MEM_2,
C_SYNCH_MEM_3);
constant DATAWIDTH_MATCH_ARRAY : EMC_ARRAY_TYPE :=
(C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3);
constant C_PAGEMODE_FLASH : EMC_ARRAY_TYPE :=
(C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3);
-- constant C_FLASH_SUPPORTS_SYNC_RD : EMC_ARRAY_TYPE :=
-- (
-- C_SUPPORT_SYNC_RD_0,
-- C_SUPPORT_SYNC_RD_1,
-- C_SUPPORT_SYNC_RD_2,
-- C_SUPPORT_SYNC_RD_3
-- );
type MEM_PARITY_ARRAY_TYPE is array (0 to 3) of integer range 0 to 2;
constant MEM_PARITY_TYPE_ARRAY : EMC_ARRAY_TYPE :=
(
C_PARITY_TYPE_0,
C_PARITY_TYPE_1,
C_PARITY_TYPE_2,
C_PARITY_TYPE_3
);
-- constant C_WRITE_RECOVERY_TIME : EMC_ARRAY_TYPE :=
-- (
-- C_WR_REC_TIME_MEM_0,
-- C_WR_REC_TIME_MEM_1,
-- C_WR_REC_TIME_MEM_2,
-- C_WR_REC_TIME_MEM_3
-- );
constant C_FLASH_TYPE_MEM : EMC_ARRAY_TYPE :=
(C_MEM0_TYPE,
C_MEM1_TYPE,
C_MEM2_TYPE,
C_MEM3_TYPE);
-------------------------------------------------------------------------------
-- Create global constants that indicate if any data matching is needed or if
-- any memories are synchronous. These can be used to eliminate un-necessary
-- logic.
-------------------------------------------------------------------------------
-- check for any memory in configuration is SYNC type or not.
constant GLOBAL_SYNC_MEM : integer range 0 to 1
:= not_all_zeros(SYNCH_MEM_ARRAY,
C_NUM_BANKS_MEM);
-- check for any memory in configuration needs Data Width Matching or not.
constant GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1
:= not_all_zeros(DATAWIDTH_MATCH_ARRAY,
C_NUM_BANKS_MEM);
-- check for any memory in configuration is Page Mode Flash type or not.
constant PAGEMODE_FLASH : integer range 0 to 1
:= not_all_zeros(C_PAGEMODE_FLASH,
C_NUM_BANKS_MEM);
--constant C_FLASH_SYNC_RD : integer range 0 to 1
-- := flash_supports_sync_rd(C_FLASH_SUPPORTS_SYNC_RD,
-- C_NUM_BANKS_MEM);
-- check for any memory in configuration is parity enabled or not.
-- 0 - no parity
-- 1 - odd parity
-- 2 - even parity
constant PARITY_TYPE_MEMORY : integer range 0 to 2
:= not_all_zeros(MEM_PARITY_TYPE_ARRAY,
C_NUM_BANKS_MEM);
constant FLASH_TYP_MEM : integer range 0 to 1
:= check_flash_mem(C_FLASH_TYPE_MEM,
C_NUM_BANKS_MEM);
-------------------------------------------------------------------------------
-- Memory Cycle Time Calculations
-------------------------------------------------------------------------------
-- Read Cycle (maximum of CE or Address Change to Valid Data)
-- Note: Minimum 1 extra clock is required to interface from the asynchronous
-- environment to a synchronous environment.
-------------------------------------------------------------------------------
-- C_TCEDV_PS_MEM_x:
-- Read cycle chip enable low to data valid duration of memory bank x
-- C_TAVDV_PS_MEM_x:
-- Read cycle address valid to data valid duration of memory bank x
-- CE ----\
-- \-------------
-- _ _ _ _ _ _
-- Addr __/
-- \_ _ _ _ _ _
--
-- TRD_CLKS_x
-- |<------>|
-- _ _ _ _ _
-- Data _ _ _ _ _ __/
-- \_ _ _ _ _
constant TRD_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_0,
C_TAVDV_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_1,
C_TAVDV_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_2,
C_TAVDV_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_3,
C_TAVDV_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- std logic vector counter for rd_clks_x
constant TRDCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_0+1, 5);
constant TRDCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_1+1, 5);
constant TRDCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_2+1, 5);
constant TRDCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_3+1, 5);
-----------------------------------------------------------------------------
-- TRD_TPACC_x: Page access time of memory bank x in page mode flash mode
constant TRD_TPACC_0 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_0/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_1 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_1/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_2 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_2/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_3 :integer range 0 to 31 -- := (0);
:= (C_TPACC_PS_FLASH_3/C_BUS_CLOCK_PERIOD_PS);
-- TRD_TPACC_x: std logic vector counter for Page Access Time
constant TPACC_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_0+1, 5);
constant TPACC_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_1+1, 5);
constant TPACC_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_2+1, 5);
constant TPACC_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_3+1, 5);
-------------------------------------------------------------------------------
-- Read Cycle End to Data Bus High Impedance
-------------------------------------------------------------------------------
-- C_THZCE_PS_MEM_x:
-- Read cycle chip enable low to data valid duration of memory bank x
-- C_THZOE_PS_MEM_x:
-- Enable high to data bus high impedance duration of memory bank x
-- CE ----\ /--------
-- \-----------xx-------/
-- OE ----\ /--------
-- \-----------xx-------/
-- THZ_CLKS_x
-- |<------->|
-- _ _ _ _ _ _ _ _ _ _ _
-- Data _ _ _ _ _ __/ \_ _ _ _
-- \_ _ _ _ _ _ _ _ _ _ _/
constant THZ_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_0,
C_THZOE_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_1,
C_THZOE_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_2,
C_THZOE_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_3,
C_THZOE_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- HZ counter in std logic vector
constant THZCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_0+1, 5);
constant THZCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_1+1, 5);
constant THZCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_2+1, 5);
constant THZCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_3+1, 5);
-------------------------------------------------------------------------------
-- Write Cycle to Data Store
-------------------------------------------------------------------------------
-- C_TWC_PS_MEM_x:
-- Write cycle time of memory bank x
-- C_TWP_PS_MEM_x:
-- Write enable minimum pulse width duration of memory bank x
constant TWR_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_0,
C_TWP_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_1,
C_TWP_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_2,
C_TWP_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_3,
C_TWP_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- TWRCNT_x: std logic vector counter for Write cycle Time
constant TWRCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_0, 5);
constant TWRCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_1, 5);
constant TWRCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_2, 5);
constant TWRCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_3, 5);
-------------------------------------------------------------------------------
-- Write Cycle High Period
-------------------------------------------------------------------------------
constant TWPH_CLKS_0 : integer range 0 to 31
:= (C_TWPH_PS_MEM_0/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_1 : integer range 0 to 31
:= (C_TWPH_PS_MEM_1/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_2 : integer range 0 to 31
:= (C_TWPH_PS_MEM_2/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_3 : integer range 0 to 31
:= (C_TWPH_PS_MEM_3/C_BUS_CLOCK_PERIOD_PS);
-- TWPHCNT_x: std logic vector counter for Write Cycle High Time
constant TWPHCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_0+1, 5);
constant TWPHCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_1+1, 5);
constant TWPHCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_2+1, 5);
constant TWPHCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_3+1, 5);
------------------------------------------------------------------------------
-- Write Cycle End Data Hold Time
-------------------------------------------------------------------------------
-- C_TLZWE_PS_MEM_x:
-- Write cycle write enable high to data bus low impedance
-- duration of memory bank x
-- WE ----\ /--------
-- \------------/
-- TLZ_CLKS_x
-- |<----->|
-- _ _ _ _ _ _ _ _ _ _ _
-- Data __/ \_ _ _ _
-- \_ _ _ _ _ _ _ _ _ _ _/
constant TLZ_CLKS_0 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_0)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_1 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_1)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_2 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_2)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_3 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_3)-1)/C_BUS_CLOCK_PERIOD_PS);
-- TLZCNT_x: std logic vector counter for Write Cycle End Data Hold Time
constant TLZCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_0+1, 5);
constant TLZCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_1+1, 5);
constant TLZCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_2+1, 5);
constant TLZCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_3+1, 5);
--------------------------------------------------------------
-- Write recovery time for Flash. some idle time is needed for Flash memories
-- after write and begin of next consecutive read cycle.
-- TWR_REC_TIME_x: Write recovery time of memory bank x in flash mode
constant TWR_REC_TIME_0 :integer range 0 to 65535 -- 7/4/2011
:= (C_WR_REC_TIME_MEM_0/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_1 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_1/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_2 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_2/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_3 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_3/C_BUS_CLOCK_PERIOD_PS);
constant TP_WR_REC_CNT_0 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_0+1, 16);
constant TP_WR_REC_CNT_1 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_1+1, 16);
constant TP_WR_REC_CNT_2 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_2+1, 16);
constant TP_WR_REC_CNT_3 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_3+1, 16);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- Write Cycle Time
signal twr_data : std_logic_vector(0 to 4);
signal twr_load : std_logic;
signal twr_cnt_en : std_logic;
signal twr_end : std_logic;
-- Write Cycle High Time
signal twph_data : std_logic_vector(0 to 4);
signal twph_load : std_logic;
signal twph_cnt_en : std_logic;
signal twph_end : std_logic;
-- Write Cycle End To Data Bus Low-Z
signal tlz_data : std_logic_vector(0 to 4);
signal tlz_load : std_logic;
signal Tlz_cnt_en : std_logic;
signal tlz_end : std_logic;
-- Read Cycle End To Data Bus High-Z
signal thz_data : std_logic_vector(0 to 4);
signal thz_load : std_logic;
signal Thz_cnt_en : std_logic;
signal thz_end : std_logic;
-- Read Cycle Address Change to Valid Data
signal trd_data : std_logic_vector(0 to 4);
signal trd_load : std_logic;
signal trd_cnt_en : std_logic;
signal trd_end : std_logic;
-- Read Cycle Address Change to Valid Data
signal tpacc_data : std_logic_vector(0 to 4);
signal tpacc_load : std_logic;
signal tpacc_cnt_en : std_logic;
signal tpacc_end : std_logic;
-- Write recovery time for flash
-- signal twr_rec_data : std_logic_vector(0 to 4);--7/4/2011
-- signal twr_rec_load : std_logic;
-- signal twr_rec_cnt_en : std_logic;
-- signal twr_rec_end : std_logic;
signal twr_rec_data_int : std_logic_vector(0 to 15);--7/4/2011
signal twr_rec_load_int : std_logic;
signal twr_rec_cnt_en_int : std_logic;
signal twr_rec_end_int : std_logic;
-- Memory Access IPIC Signals
signal bus2ip_cs_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal bus2ip_cs_reg_d1 : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal cs_Strobe : std_logic;
signal new_page_access : std_logic;
signal Parity_enable : std_logic;
signal Parity_type : std_logic;
signal Parity_err_i : std_logic;
signal bus2Mem_CS : std_logic;
signal bus2Mem_RdReq : std_logic;
signal bus2Mem_WrReq : std_logic;
signal mem2Bus_RdAck : std_logic;
signal mem2Bus_WrAck : std_logic;
signal mem2Bus_RdAddrAck : std_logic;
signal mem2Bus_WrAddrAck : std_logic;
signal mem2Bus_Data : std_logic_vector(0 to C_IPIF_DWIDTH - 1);
signal write_req_ack : std_logic;
signal read_req_ack : std_logic;
signal read_data_en : std_logic;
signal read_ack : std_logic;
-- Memory Control Internal Signals
signal mem_CEN_cmb : std_logic;
signal mem_OEN_cmb : std_logic;
signal mem_WEN_cmb : std_logic;
signal bus2ip_ben_int : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal bus2ip_ben_fixed : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal mem_a_int : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal par_error_addr : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal mem_dq_i_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_o_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_t_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_parity_i_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_parity_o_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_parity_t_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_cen_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_oen_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_wen_int : std_logic;
signal mem_qwen_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_ben_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_rpn_int : std_logic;
signal mem_ce_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_adv_ldn_int : std_logic;
signal mem_lbon_int : std_logic;
signal mem_cken_int : std_logic;
signal mem_rnw_int : std_logic;
signal mem_be_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
-- Data Width Matching Address Management
signal addr_cnt_ce : std_logic;
signal addr_cnt_rst : std_logic;
signal addr_cnt : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal addr_align : std_logic;
signal addr_align_rd : std_logic;
signal addr_align_write : std_logic;
signal CS_par_addr : std_logic;
signal cycle_cnt_en : std_logic;
signal cycle_cnt_ld : std_logic;
signal cycle_End : std_logic;
signal address_strobe : std_logic;
signal data_strobe : std_logic;
-- Access Parameters
signal mem_width_bytes : std_logic_vector(0 to 3);
signal datawidth_match : std_logic;
signal synch_mem1 : std_logic;
signal two_pipe_delay : std_logic;
signal ip2Bus_RdAck_i : std_logic;
signal IP2Bus_errAck_i : std_logic;
signal Mem_Addr_rst : std_logic;
signal transaction_done_i : std_logic;
signal Bus2IP_Mem_CS_i : std_logic;
signal single_transaction : std_logic;
signal temp_parity_error_adrss: std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal last_burst_cnt : std_logic;
signal Write_req_data_ack : std_logic;
signal Write_req_addr_ack : std_logic;
signal address_strobe_c : std_logic;
signal be_strobe_c : std_logic;
signal data_strobe_c : std_logic;
signal pr_state_wait_temp_cmb : std_logic;
signal ns_idle : std_logic;
signal flash_mem_access_int : std_logic;
signal flash_mem_access_int_1 : std_logic;
signal int_Flash_mem_access_dis : std_logic;
signal Adv_L_N : std_logic;
signal stop_oen : std_logic;
signal bus2ip_ben_all_1 : std_logic;-- 12-12-2012
--signal Linear_flash_brst_rd_flag : std_logic;
--signal Linear_flash_rd_data_ack : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
mem_rpn_int <= not Bus2IP_Reset;
mem_adv_ldn_int <= '0';
mem_lbon_int <= '0';
mem_cken_int <= '0';
IP2Bus_RdAck <= ip2Bus_RdAck_i;
IP2Bus_errAck <= IP2Bus_errAck_i;
Parity_err <= Parity_err_i;
Bus2IP_Mem_CS_i <= or_reduce(Bus2IP_Mem_CS);
---------------------------------------------------------------------------
-- Store the Chip Select Coming from IPIF in case C_NUM_BANKS_MEM > 1
---------------------------------------------------------------------------
CS_STORE_GEN: if (C_NUM_BANKS_MEM > 1) generate
begin
CS_STORE_PROCESS:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if Bus2IP_Reset = '1' then
bus2ip_cs_reg_d1 <= (others=>'0');
else
bus2ip_cs_reg_d1 <= bus2ip_cs_reg;
end if;
end if;
end process CS_STORE_PROCESS;
bus2ip_cs_reg <= Bus2IP_Mem_CS when (cs_Strobe = '1')
else
bus2ip_cs_reg_d1;
end generate CS_STORE_GEN;
---------------------------------------------------------------------------
-- Pass on the Chip Select Coming from IPIF in case C_NUM_BANKS_MEM = 1
---------------------------------------------------------------------------
CS_PASS_GEN: if (C_NUM_BANKS_MEM = 1) generate
-----
function int_to_std (flash_type: integer) return std_logic is
begin
if (flash_type = 1) then
return '1';
else
return '0';
end if;
end function;
------------------------------------------------------------------------------
begin
-----
bus2ip_cs_reg <= Bus2IP_Mem_CS;
flash_mem_access_int_1 <= int_to_std(FLASH_TYP_MEM);
end generate CS_PASS_GEN;
------------------------------------------------------------------------------
-- Generate single transaction signals for multiple memory banks.
------------------------------------------------------------------------------
SINGLE_BURST_GEN_PROCESS: process(Bus2IP_Mem_CS,
bus2ip_burst,
Bus2IP_BurstLength)is
-----
begin
-----
single_transaction <= '0';
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1' and
--bus2ip_burst= '0' and
or_reduce(Bus2IP_BurstLength) = '0') then -- = "00000000") then
single_transaction <= '1';
end if;
end loop;
end process SINGLE_BURST_GEN_PROCESS;
----------------------------------------------------------------
MULTIPLE_MEM_FLASH_ACCESS_GEN: if (C_NUM_BANKS_MEM > 1) generate
-----
begin
-----
REG_FLASH_ACCESS: process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(flash_mem_access_int = '1') then
flash_mem_access_int_1 <= '1';
elsif(Bus2IP_Reset = '1' or int_Flash_mem_access_dis = '1')then
flash_mem_access_int_1 <= '0';
end if;
end if;
end process REG_FLASH_ACCESS;
FLASH_ACCESS_PROCESS: process (Bus2IP_Mem_CS) is
-----
begin
-----
flash_mem_access_int <= '0';
for i in 0 to C_NUM_BANKS_MEM -1 loop
if((Bus2IP_Mem_CS(i) = '1') and
((C_FLASH_TYPE_MEM(i) = 2)or -- check if the memory is flash,page mode flash
(C_FLASH_TYPE_MEM(i) = 3)or
(C_FLASH_TYPE_MEM(i) = 4)or
(C_FLASH_TYPE_MEM(i) = 5)
)) then
flash_mem_access_int <= '1';
--else
-- flash_mem_access_int <= '0';
end if;
end loop;
end process FLASH_ACCESS_PROCESS;
---------------------------------
end generate MULTIPLE_MEM_FLASH_ACCESS_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- IPIC Interface
-------------------------------------------------------------------------------
IPIC_IF_I : entity emc_common_v3_0.ipic_if
generic map (
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_IPIF_DWIDTH => C_IPIF_DWIDTH
)
port map (
Bus2IP_Clk => Bus2IP_Clk ,
Bus2IP_Reset => Bus2IP_Reset ,
Bus2IP_RNW => Bus2IP_RNW ,-- in std_logic;
Bus2IP_Mem_CS => Bus2IP_Mem_CS ,-- in std_logic_vector
Mem2Bus_RdAddrAck => mem2Bus_RdAddrAck ,-- in std_logic;
Mem2Bus_WrAddrAck => mem2Bus_WrAddrAck ,-- in std_logic;
Mem2Bus_RdAck => mem2Bus_RdAck ,-- in std_logic;
Mem2Bus_WrAck => mem2Bus_WrAck ,-- in std_logic;
Mem2Bus_Data => mem2Bus_Data ,-- in std_logic;
Bus2IP_WrReq => Bus2IP_WrReq ,-- in std_logic;
Bus2IP_RdReq => Bus2IP_RdReq ,-- in std_logic_vector
Bus2IP_Burst => bus2ip_burst ,-- in std_logic;
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc ,-- in std_logic;
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc ,-- in std_logic;
Bus2Mem_CS => bus2Mem_CS ,-- out std_logic;
Bus2Mem_RdReq => bus2Mem_RdReq ,-- out std_logic;
Bus2Mem_WrReq => bus2Mem_WrReq ,-- out std_logic;
Parity_err => Parity_err_i ,-- in std_logic;
IP2Bus_Data => IP2Bus_Data ,-- out std_logic_vector
IP2Bus_errAck => IP2Bus_errAck_i ,-- out std_logic;
IP2Bus_retry => IP2Bus_retry ,-- out std_logic;
IP2Bus_toutSup => IP2Bus_toutSup ,-- out std_logic;
IP2Bus_RdAck => ip2Bus_RdAck_i ,-- out std_logic;
IP2Bus_WrAck => IP2Bus_WrAck ,-- out std_logic;
IP2Bus_AddrAck => IP2Bus_AddrAck ,-- out std_logic;
Type_of_xfer => Type_of_xfer ,-- in std_logic;
Burst_length => Bus2IP_BurstLength ,-- in std_logic_vector(
Transaction_done => transaction_done_i ,-- in std_logic;
single_transaction=> single_transaction ,-- in std_logic;
last_burst_cnt => last_burst_cnt ,-- out std_logic;
pr_state_wait_temp_cmb => pr_state_wait_temp_cmb ,
Synch_mem => synch_mem1 ,
Mem_width_bytes => mem_width_bytes , -- 10-12-2012
stop_oen => stop_oen , -- 10-12-2012
axi_trans_size_reg => axi_trans_size_reg ,-- 1/3/2013
Linear_flash_brst_rd_flag=> Linear_flash_brst_rd_flag -- 1/28/2013
);
-------------------------------------------------------------------------------
-- Memory State Machine
-------------------------------------------------------------------------------
MEM_STATE_MACHINE_I : entity emc_common_v3_0.mem_state_machine
port map (
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_RdReq => bus2Mem_RdReq,
Bus2IP_WrReq => Bus2Mem_WrReq,
original_wrce => original_wrce,
--flash_mem_access => flash_mem_access_int,
Synch_mem => synch_mem1,
Two_pipe_delay => two_pipe_delay,
Cycle_End => cycle_End,
Bus2IP_Mem_CS => Bus2IP_Mem_CS_i,
Bus2IP_Burst => bus2ip_burst,
Read_data_en => read_data_en,
Read_ack => read_ack,
Address_strobe => address_strobe,
-- Data_strobe => data_strobe,09-12-2012
CS_Strobe => cs_Strobe,
axi_wvalid => axi_wvalid,
axi_wlast => axi_wlast,
Addr_cnt_ce => addr_cnt_ce,
Addr_cnt_rst => addr_cnt_rst,
Cycle_cnt_ld => cycle_cnt_ld,
Cycle_cnt_en => cycle_cnt_en,
single_trans => single_transaction,
Trd_cnt_en => trd_cnt_en,
Twr_cnt_en => twr_cnt_en,
Twph_cnt_en => twph_cnt_en,
Tpacc_cnt_en => tpacc_cnt_en,
Trd_load => trd_load,
Twr_load => twr_load,
Twph_load => twph_load,
Tpacc_load => tpacc_load,
Thz_load => thz_load,
Tlz_load => tlz_load,
Trd_end => trd_end,
Twr_end => twr_end,
Twph_end => twph_end,
Thz_end => thz_end,
Tlz_end => tlz_end,
Tpacc_end => Tpacc_end,
New_page_access => new_page_access,
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack,
MSM_Mem_CEN => mem_CEN_cmb,
MSM_Mem_OEN => mem_OEN_cmb,
MSM_Mem_WEN => mem_WEN_cmb,
CS_Strobe_par_addr => CS_par_addr,
Addr_align => addr_align_write,
Addr_align_rd => addr_align_rd,
Write_req_ack => write_req_ack,
Read_req_ack => read_req_ack,
Transaction_done => transaction_done_i,
Mem_Addr_rst => Mem_Addr_rst,
last_burst_cnt => last_burst_cnt,
Write_req_data_ack => Write_req_data_ack,
Write_req_addr_ack => Write_req_addr_ack,
address_strobe_c => address_strobe_c,
be_strobe_c => be_strobe_c,
data_strobe_c => data_strobe_c,
ns_idle => ns_idle ,
pr_state_wait_temp_cmb => pr_state_wait_temp_cmb,
Twr_rec_load => twr_rec_load_int ,
Twr_rec_cnt_en => twr_rec_cnt_en_int,
Twr_rec_end => twr_rec_end_int,
Flash_mem_access_disable => int_Flash_mem_access_dis, --
Flash_mem_access => flash_mem_access_int_1, --Flash_mem_access_int
Mem_WAIT => Mem_WAIT,
Adv_L_N => Adv_L_N,
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc, -- 17-10-2012
last_addr1 => last_addr1,
stop_oen => stop_oen,
pr_idle => pr_idle, -- 11-12-2012
bus2ip_ben_all_1 => bus2ip_ben_all_1
--Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
--Linear_flash_rd_data_ack => Linear_flash_rd_data_ack
);
bus2ip_ben_fixed <= (others=>'0') when Type_of_xfer = '0'
else
Bus2IP_BE;
bus2ip_ben_all_1 <= and_reduce(Bus2IP_BE);-- 13-12-2012
parity_error_adrss <= temp_parity_error_adrss when (ip2Bus_RdAck_i = '1' and IP2Bus_errAck_i = '1') else (others => '0');
-------------------------------------------------------------------------------
-- Datawidth Matching Address Counter
-------------------------------------------------------------------------------
ADDR_COUNTER_MUX_I : entity emc_common_v3_0.addr_counter_mux
generic map (
C_ADDR_CNTR_WIDTH => ADDR_CNTR_WIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_ADDR_OFFSET => ADDR_OFFSET,
PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH
)
port map (
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_BE => bus2ip_ben_fixed,
Address_strobe => address_strobe,
--Data_strobe => data_strobe,09-12-2012
Mem_width_bytes => mem_width_bytes,
Datawidth_match => datawidth_match,
Bus2Mem_CS => bus2Mem_CS,
Addr_cnt_ce => addr_cnt_ce,
Addr_cnt_rst => addr_cnt_rst,
Addr_cnt => addr_cnt,
Addr_align => addr_align_write,
CS_par_addr => CS_par_addr,
par_error_addr => temp_parity_error_adrss,
Cycle_cnt_ld => cycle_cnt_ld,
Cycle_cnt_en => cycle_cnt_en,
Cycle_End => cycle_End,
Mem_addr => Mem_A_int,
Mem_Ben => bus2ip_ben_int,
address_strobe_c => address_strobe_c,
be_strobe_c => be_strobe_c ,
data_strobe_c => data_strobe_c,
Cre_reg_en => Cre_reg_en,
Bus2IP_RdReq => bus2Mem_RdReq, -- 17-10-2012
psram_page_mode => psram_page_mode,
axi_trans_size_reg => axi_trans_size_reg -- 1/17/2013
);
-------------------------------------------------------------------------------
-- Asynchronous Memory Cycle Timers
-------------------------------------------------------------------------------
COUNTERS_I: entity emc_common_v3_0.counters
port map (
Synch_mem => synch_mem1,
Twr_data => twr_data,
Twr_load => twr_load,
Twr_cnt_en => twr_cnt_en,
twph_data => twph_data,
twph_load => twph_load,
twph_cnt_en => twph_cnt_en,
Tlz_data => tlz_data,
Tlz_load => tlz_load,
Trd_data => trd_data,
Trd_load => trd_load,
Trd_cnt_en => trd_cnt_en,
Tpacc_data => tpacc_data,
Tpacc_load => tpacc_load,
Tpacc_cnt_en => tpacc_cnt_en,
Thz_data => thz_data,
Thz_load => thz_load,
Twr_end => twr_end,
Twph_end => twph_end,
Tlz_end => tlz_end,
Trd_end => trd_end,
Thz_end => thz_end,
Tpacc_end => Tpacc_end,
--------------------------
Twr_rec_data => twr_rec_data_int ,
Twr_rec_load => twr_rec_load_int ,
Twr_rec_cnt_en => twr_rec_cnt_en_int,
Twr_rec_end => twr_rec_end_int ,
--------------------------
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset
);
-------------------------------------------------------------------------------
-- Memory Paramter Selector
-------------------------------------------------------------------------------
SELECT_PARAM_I: entity emc_common_v3_0.select_param
generic map (
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_GLOBAL_SYNC_MEM => GLOBAL_SYNC_MEM,
C_SYNCH_MEM_0 => C_SYNCH_MEM_0,
C_SYNCH_MEM_1 => C_SYNCH_MEM_1,
C_SYNCH_MEM_2 => C_SYNCH_MEM_2,
C_SYNCH_MEM_3 => C_SYNCH_MEM_3,
C_MEM0_WIDTH => C_MEM0_WIDTH,
C_MEM1_WIDTH => C_MEM1_WIDTH,
C_MEM2_WIDTH => C_MEM2_WIDTH,
C_MEM3_WIDTH => C_MEM3_WIDTH,
C_PAGEMODE_FLASH => PAGEMODE_FLASH,
C_PAGEMODE_FLASH_0 => C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1 => C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2 => C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3 => C_PAGEMODE_FLASH_3,
PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_PARITY_TYPE_0 => C_PARITY_TYPE_0,
C_PARITY_TYPE_1 => C_PARITY_TYPE_1,
C_PARITY_TYPE_2 => C_PARITY_TYPE_2,
C_PARITY_TYPE_3 => C_PARITY_TYPE_3,
C_SYNCH_PIPEDELAY_0 => C_SYNCH_PIPEDELAY_0,
C_SYNCH_PIPEDELAY_1 => C_SYNCH_PIPEDELAY_1,
C_SYNCH_PIPEDELAY_2 => C_SYNCH_PIPEDELAY_2,
C_SYNCH_PIPEDELAY_3 => C_SYNCH_PIPEDELAY_3,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH,
C_INCLUDE_DATAWIDTH_MATCHING_0 => C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3 => C_INCLUDE_DATAWIDTH_MATCHING_3,
TRDCNT_0 => TRDCNT_0,
TRDCNT_1 => TRDCNT_1,
TRDCNT_2 => TRDCNT_2,
TRDCNT_3 => TRDCNT_3,
THZCNT_0 => THZCNT_0,
THZCNT_1 => THZCNT_1,
THZCNT_2 => THZCNT_2,
THZCNT_3 => THZCNT_3,
TWRCNT_0 => TWRCNT_0,
TWRCNT_1 => TWRCNT_1,
TWRCNT_2 => TWRCNT_2,
TWRCNT_3 => TWRCNT_3,
TWPHCNT_0 => TWPHCNT_0,
TWPHCNT_1 => TWPHCNT_1,
TWPHCNT_2 => TWPHCNT_2,
TWPHCNT_3 => TWPHCNT_3,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
TPACC_0 => TPACC_0,
TPACC_1 => TPACC_1,
TPACC_2 => TPACC_2,
TPACC_3 => TPACC_3,
TLZCNT_0 => TLZCNT_0,
TLZCNT_1 => TLZCNT_1,
TLZCNT_2 => TLZCNT_2,
TLZCNT_3 => TLZCNT_3,
TP_WR_REC_CNT_0 => TP_WR_REC_CNT_0,--7/4/2011
TP_WR_REC_CNT_1 => TP_WR_REC_CNT_1,
TP_WR_REC_CNT_2 => TP_WR_REC_CNT_2,
TP_WR_REC_CNT_3 => TP_WR_REC_CNT_3
)
port map (
Bus2IP_Mem_CS => bus2ip_cs_reg,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_RNW => Bus2IP_RNW,
psram_page_mode => psram_page_mode,
New_page_access => new_page_access,
Parity_enable => Parity_enable,
Parity_type => Parity_type,
Twr_data => twr_data,
Twph_data => twph_data,
Tlz_data => tlz_data,
Trd_data => trd_data,
Thz_data => thz_data,
Tpacc_data => tpacc_data,
Twr_rec_data => twr_rec_data_int,-- 9/6/2011
Synch_mem => synch_mem1,
Mem_width_bytes => mem_width_bytes,
Two_pipe_delay => two_pipe_delay,
Datawidth_match => datawidth_match
);
-------------------------------------------------------------------------------
-- Memory Data/Control Steering Logic
-------------------------------------------------------------------------------
MEM_STEER_I : entity emc_common_v3_0.mem_steer
generic map(
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_MIN_MEM_WIDTH => MIN_MEM_WIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_ADDR_CNTR_WIDTH => ADDR_CNTR_WIDTH,
C_PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_GLOBAL_SYNC_MEM => GLOBAL_SYNC_MEM,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH
)
port map(
--
--Clk => Bus2IP_Clk,
--Rst => Bus2IP_Reset
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_Data => Bus2IP_Data, -- in std_logic_vector
Bus2IP_BE => bus2ip_ben_int, -- in std_logic_vector
Bus2IP_Mem_CS => bus2ip_cs_reg, -- in std_logic_vector
Bus2IP_RdReq => bus2Mem_RdReq, -- in std_logic;
Bus2IP_Burst => bus2ip_burst, -- in std_logic;
Write_req_ack => write_req_ack, -- in std_logic;
Read_req_ack => read_req_ack, -- in std_logic;
Read_ack => read_ack, -- in std_logic;
Read_data_en => read_data_en, -- in std_logic;
--Data_strobe => data_strobe, -- in std_logic;09-12-2012
MSM_Mem_CEN => mem_CEN_cmb, -- in std_logic;
MSM_Mem_OEN => mem_OEN_cmb, -- in std_logic;
MSM_Mem_WEN => mem_WEN_cmb, -- in std_logic;
Mem2Bus_WrAddrAck => mem2Bus_WrAddrAck,-- out std_logic;
Mem2Bus_WrAck => mem2Bus_WrAck, -- out std_logic;
Mem2Bus_RdAddrAck => mem2Bus_RdAddrAck,-- out std_logic;
Mem2Bus_RdAck => mem2Bus_RdAck, -- out std_logic;
Mem2Bus_Data => mem2Bus_Data, -- out std_logic_vector
Mem_width_bytes => mem_width_bytes, -- in std_logic_vector
Synch_mem => synch_mem1, -- in std_logic;
Two_pipe_delay => two_pipe_delay, -- in std_logic;
single_transaction => single_transaction,-- in std_logic;
Parity_enable => Parity_enable, -- out std_logic_vector
Parity_type => Parity_type, -- in std_logic;
parity_error_mem => parity_error_mem, -- in std_logic;
Parity_err => Parity_err_i, -- out std_logic;
Addr_cnt => addr_cnt, -- in std_logic_vector
Addr_align => addr_align_write, -- in std_logic
Addr_align_rd => addr_align_rd, -- in std_logic
MemSteer_Mem_DQ_I => mem_dq_i_int, -- in std_logic_vector
MemSteer_Mem_DQ_O => mem_dq_o_int, -- out std_logic_vector
MemSteer_Mem_DQ_T => mem_dq_t_int, -- out std_logic_vector
MemSteer_Mem_DQ_prty_I => mem_dq_parity_i_int,-- in std_logic_vector
MemSteer_Mem_DQ_prty_O => mem_dq_parity_o_int,-- out std_logic_vector
MemSteer_Mem_DQ_prty_T => mem_dq_parity_t_int,-- out std_logic_vector
MemSteer_Mem_CEN => mem_cen_int, -- out std_logic_vector
MemSteer_Mem_OEN => mem_oen_int, -- out std_logic_vector
MemSteer_Mem_WEN => mem_wen_int, -- out std_logic
MemSteer_Mem_QWEN => mem_qwen_int, -- out std_logic_vector
MemSteer_Mem_BEN => mem_ben_int, -- out std_logic_vector
MemSteer_Mem_CE => mem_ce_int, -- out std_logic_vector
MemSteer_Mem_RNW => mem_rnw_int, -- out std_logic
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc, -- in std_logic;
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc, -- in std_logic;
Write_req_data_ack => Write_req_data_ack,
Write_req_addr_ack => Write_req_addr_ack,
address_strobe_c => address_strobe_c, --- in
be_strobe_c => be_strobe_c , -- in
data_strobe_c => data_strobe_c, -- in
ns_idle => ns_idle , -- in
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack,
last_addr => last_addr1, -- 10-12-2012
stop_oen => stop_oen ,-- 10-12-2012
cycle_end => cycle_End ,
axi_arsize => axi_arsize,
axi_trans_size_reg => axi_trans_size_reg
);
-------------------------------------------------------------------------------
-- Instantiate the IO register block to memory
-- IO registers will be instantiated based on the parameter settings
-------------------------------------------------------------------------------
IO_REGISTERS_I: entity emc_common_v3_0.io_registers
generic map (
--C_FLASH_SYNC_RD => C_FLASH_SYNC_RD,
C_INCLUDE_NEGEDGE_IOREGS => C_INCLUDE_NEGEDGE_IOREGS,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM
)
port map (
Linear_flash_brst_rd_flag=> Linear_flash_brst_rd_flag, -- 1/28/2013
Clk => Bus2IP_Clk, --in std_logic
RdClk => RdClk, --in std_logic
Rst => Bus2IP_Reset, --in std_logic
Mem_A_int => mem_a_int, --in std_logic_vector
Mem_DQ_I_int => mem_dq_i_int, --out std_logic_vector
Mem_DQ_O_int => mem_dq_o_int, --in std_logic_vector
Mem_DQ_T_int => mem_dq_t_int, --in std_logic_vector
Mem_DQ_PARITY_I_int => mem_dq_parity_i_int, --out std_logic_vector
Mem_DQ_PARITY_O_int => mem_dq_parity_o_int, --in std_logic_vector
Mem_DQ_PARITY_T_int => mem_dq_parity_t_int, --in std_logic_vector
Mem_CEN_int => mem_cen_int, --in std_logic_vector
Mem_OEN_int => mem_oen_int, --in std_logic_vector
Mem_WEN_int => mem_wen_int, --in std_logic;
Mem_QWEN_int => mem_qwen_int, --in std_logic_vector
Mem_BEN_int => mem_ben_int, --in std_logic_vector
Mem_RPN_int => mem_rpn_int, --in std_logic;
Mem_CE_int => mem_ce_int, --in std_logic_vector
Mem_ADV_LDN_int => mem_adv_ldn_int, --in std_logic;
Mem_LBON_int => mem_lbon_int, --in std_logic;
Mem_CKEN_int => mem_cken_int, --in std_logic;
Mem_RNW_int => mem_rnw_int, --in std_logic;
Mem_Addr_rst => Mem_Addr_rst, --in std_logic
--Linear_flash_rd_data_ack => Linear_flash_rd_data_ack, -- out std_logic;
Mem_A => Mem_A, --out std_logic_vector
Mem_DQ_I => Mem_DQ_I, --in std_logic_vector
Mem_DQ_O => Mem_DQ_O, --out std_logic_vector
Mem_DQ_T => Mem_DQ_T, --out std_logic_vector
Mem_DQ_PRTY_I => Mem_DQ_PRTY_I, --in std_logic_vector
Mem_DQ_PRTY_O => Mem_DQ_PRTY_O, --out std_logic_vector
Mem_DQ_PRTY_T => Mem_DQ_PRTY_T, --out std_logic_vector
Mem_CEN => Mem_CEN, --out std_logic_vector
Mem_OEN => Mem_OEN, --out std_logic_vector
Mem_WEN => Mem_WEN, --out std_logic;
Mem_QWEN => Mem_QWEN, --out std_logic_vector
Mem_BEN => Mem_BEN, --out std_logic_vector
Mem_RPN => Mem_RPN, --out std_logic;
Mem_CE => Mem_CE, --out std_logic_vector
Mem_ADV_LDN => Mem_ADV_LDN, --out std_logic;
Mem_LBON => Mem_LBON, --out std_logic;
Mem_CKEN => Mem_CKEN, --out std_logic;
Mem_RNW => Mem_RNW --out std_logic
--Mem_WAIT => Mem_WAIT, --in std_logic
--Mem_Flash_clk => Mem_Flash_clk --in std_logic
);
synch_mem12 <= synch_mem1;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File emc.vhd
-------------------------------------------------------------------------------
|
gpl-3.0
|
6e224e0fb568439ed8f81d85a87a8333
| 0.467752 | 3.753443 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl/old/CipherCore_Datapath.vhd
| 1 | 5,205 |
-------------------------------------------------------------------------------
--! @file CipherCore_Datapath.vhd
--! @author Ekawat (ice) Homsirikamol
--! @brief Datapath unit for ASCON
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CipherCore_Datapath is
port (
clk : in std_logic;
rst : in std_logic;
--! Input
bdi : in std_logic_vector(64 -1 downto 0);
bdi_valid_bytes : in std_logic_vector( 8 -1 downto 0);
key : in std_logic_vector(32 -1 downto 0);
--! Datapath
en_key : in std_logic;
en_npub : in std_logic;
en_state : in std_logic;
en_cmp : in std_logic;
is_last_ad : in std_logic;
clr_rc : in std_logic;
en_rc : in std_logic;
sel_key_hi : in std_logic;
sel_key_lo : in std_logic;
sel_decrypt : in std_logic;
sel_state : in std_logic_vector(2 -1 downto 0);
sel_tag : in std_logic_vector(2 -1 downto 0);
--! Output
bdo : out std_logic_vector(64 -1 downto 0);
tag : out std_logic_vector(128 -1 downto 0);
msg_auth_valid : out std_logic
);
end entity CipherCore_Datapath;
architecture structure of CipherCore_Datapath is
signal reg_key : std_logic_vector(128 -1 downto 0);
signal reg_npub_hi : std_logic_vector(64 -1 downto 0);
signal bdi_xor : std_logic_vector(64 -1 downto 0);
signal bdi_xor_sel : std_logic_vector(64 -1 downto 0);
signal bdi_valid_bits : std_logic_vector(64 -1 downto 0);
signal init_state0 : std_logic_vector(320 -1 downto 0);
signal init_statex : std_logic_vector(320 -1 downto 0);
signal istate : std_logic_vector(320 -1 downto 0);
signal ostate : std_logic_vector(320 -1 downto 0);
signal oround : std_logic_vector(320 -1 downto 0);
signal bdo_s : std_logic_vector(64 -1 downto 0);
signal msg_auth_valid_s : std_logic;
signal msg_auth_valid_r : std_logic;
constant ZEROS : std_logic_vector(128 -1 downto 0)
:= (others => '0');
signal rc : std_logic_vector( 8 -1 downto 0);
signal rc_new : std_logic_vector( 8 -1 downto 0);
begin
p_clk:
process(clk)
begin
if rising_edge(clk) then
if (en_key = '1') then
reg_key <= reg_key(95 downto 0) & key;
end if;
if (en_state = '1') then
ostate <= istate;
end if;
if (en_npub = '1') then
reg_npub_hi <= bdi;
end if;
if (clr_rc = '1') then
rc <= x"F0";
elsif (en_rc = '1') then
rc <= rc_new;
end if;
if (en_cmp = '1') then
msg_auth_valid_r <= msg_auth_valid_s;
end if;
end if;
end process;
rc_new(7 downto 4) <= std_logic_vector(unsigned(rc(7 downto 4)) - "0001");
rc_new(3 downto 0) <= std_logic_vector(unsigned(rc(3 downto 0)) + "0001");
init_state0 <= x"80" & x"0C" & x"06" & ZEROS(39 downto 0)
& reg_key & reg_npub_hi & bdi;
init_statex(319 downto 256) <= bdi_xor_sel;
init_statex(255 downto 128) <= ostate(255 downto 128) when sel_key_hi = '0' else (ostate(255 downto 128) xor reg_key);
init_statex(127 downto 1) <= ostate(127 downto 1) when sel_key_lo = '0' else (ostate(127 downto 1) xor reg_key(127 downto 1));
init_statex( 0) <= (ostate( 0) xor is_last_ad) when sel_key_lo = '0' else (ostate( 0) xor reg_key( 0) xor is_last_ad);
gBits:
for i in 7 downto 0 generate
bdi_xor_sel(7+i*8 downto i*8) <= bdi(7+i*8 downto i*8)
when (sel_decrypt = '1' and bdi_valid_bytes(i) = '1')
else bdi_xor(7+i*8 downto i*8);
end generate;
with sel_state(1 downto 0) select
istate <= oround when "00",
init_statex when "01",
init_state0 when others;
u_round:
entity work.ASCON_Round(structure)
port map (ii => ostate, oo => oround, rc => rc);
bdi_xor <= ostate(319 downto 256) xor bdi;
with sel_tag select
bdo_s <= init_statex(127 downto 64) when "10",
init_statex(63 downto 0) when "11",
bdi_xor when others;
bdo <= bdo_s;
msg_auth_valid_s <= '1' when bdo_s = bdi else '0';
msg_auth_valid <= msg_auth_valid_r and msg_auth_valid_s;
end architecture structure;
|
apache-2.0
|
22de63f0d28a19393ba7bfbc4449c6cd
| 0.466667 | 3.612075 | false | false | false | false |
hoangt/PoC
|
tb/fifo/fifo_ic_got_tb.vhdl
| 2 | 6,591 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO with independent clocks
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity fifo_ic_got_tb is
end entity;
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
architecture tb of fifo_ic_got_tb is
-- FIFO Parameters
constant D_BITS : positive := 9;
constant MIN_DEPTH : positive := 8;
constant OUTPUT_REG : boolean := true;
constant ESTATE_WR_BITS : natural := 2;
constant FSTATE_RD_BITS : natural := 2;
-- Sequence Generator
constant GEN : bit_vector := "100110001";
constant ORG : std_logic_vector := "00000001";
-- Clock Generation and Reset
signal rst : std_logic := '1';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal clk2 : std_logic := '0';
signal done : std_logic := '0';
-- clk0 -> clk1 Transfer
signal di0 : std_logic_vector(D_BITS-1 downto 0);
signal put0 : std_logic;
signal ful0 : std_logic;
signal do1 : std_logic_vector(D_BITS-1 downto 0);
signal vld1 : std_logic;
signal got1 : std_logic;
-- clk1 -> clk2 Transfer
signal di1 : std_logic_vector(D_BITS-1 downto 0);
signal put1 : std_logic;
signal ful1 : std_logic;
signal do2 : std_logic_vector(D_BITS-1 downto 0);
signal vld2 : std_logic;
signal got2 : std_logic;
signal dat2 : std_logic_vector(D_BITS-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Clock Generation and Reset
clk0 <= clk0 xnor done after 7 ns;
clk1 <= clk1 xnor done after 12 ns;
clk2 <= clk2 xnor done after 5 ns;
process
begin
wait for 16 ns;
rst <= '0';
wait;
end process;
-----------------------------------------------------------------------------
-- Initial Generator
gen0 : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk0,
set => rst,
din => ORG,
step => put0,
mask => di0
);
process
variable cnt : natural := 0;
begin
put0 <= '0';
wait until rst = '0' and rising_edge(clk0);
-- Slow Input Phase
while cnt < 2*MIN_DEPTH loop
wait until falling_edge(clk0);
if ful0 = '0' and vld1 = '0' then
put0 <= '1';
cnt := cnt + 1;
else
put0 <= '0';
end if;
end loop;
-- Fast Input Phase
while cnt < 4*MIN_DEPTH loop
wait until falling_edge(clk0);
if ful0 = '0' then
put0 <= '1';
cnt := cnt + 1;
else
put0 <= '0';
end if;
end loop;
-- Let it drain
wait until falling_edge(clk0);
put0 <= '0';
report "Sending Complete." severity note;
wait;
end process;
fifo0_1 : entity PoC.fifo_ic_got
generic map (
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
OUTPUT_REG => OUTPUT_REG,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
clk_wr => clk0,
rst_wr => rst,
put => put0,
din => di0,
full => ful0,
estate_wr => open,
clk_rd => clk1,
rst_rd => rst,
got => got1,
valid => vld1,
dout => do1,
fstate_rd => open
);
-----------------------------------------------------------------------------
-- Intermediate Checker
gen1 : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk1,
set => rst,
din => ORG,
step => put1,
mask => di1
);
got1 <= vld1 and not ful1;
put1 <= got1;
process
variable cnt : natural := 0;
begin
-- Pass-thru Checking
wait until rising_edge(clk1);
assert rst = '1' or put1 = '0' or do1 = di1
report "Mismatch in clk1."
severity error;
if put1 = '1' then
cnt := cnt + 1;
end if;
end process;
fifo1_2 : entity PoC.fifo_ic_got
generic map (
DATA_REG => true,
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
clk_wr => clk1,
rst_wr => rst,
put => put1,
din => di1,
full => ful1,
estate_wr => open,
clk_rd => clk2,
rst_rd => rst,
got => got2,
valid => vld2,
dout => do2,
fstate_rd => open
);
-----------------------------------------------------------------------------
-- Final Checker
gen2 : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk2,
set => rst,
din => ORG,
step => got2,
mask => dat2
);
process
variable cnt : natural := 0;
variable del : natural := 0;
begin
-- Final Checking
wait until rising_edge(clk2);
got2 <= '0';
if vld2 = '1' then
del := del + 1;
if del = 3 then
got2 <= '1';
assert dat2 = do2
report "Mismatch in clk2."
severity error;
cnt := cnt + 1;
del := 0;
end if;
end if;
--port "Count: "&integer'image(cnt) severity note;
if cnt = 4*MIN_DEPTH then
done <= '1';
report "Test Complete." severity note;
end if;
end process;
end tb;
|
apache-2.0
|
bb94d93178d66dbe98b65aa67faf3e47
| 0.50129 | 3.715333 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_uartlite_0_0/synth/design_1_axi_uartlite_0_0.vhd
| 2 | 8,976 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_uartlite_0_0_arch : ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
|
gpl-3.0
|
9794d790116190fbbc3bd456876c9ef6
| 0.697193 | 3.292737 | false | false | false | false |
lowRISC/greth-library
|
greth_library/rocketlib/misc/nasti_gpio.vhd
| 1 | 3,976 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Controller of the GPIOs with the AMBA AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_gpio is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type;
i_glip : in std_logic_vector(31 downto 0);
o_glip : out std_logic_vector(31 downto 0)
);
end;
architecture arch_nasti_gpio of nasti_gpio is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPIO,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type bank_type is record
o_glip : std_logic_vector(31 downto 0);
i_glip : std_logic_vector(31 downto 0);
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
constant RESET_VALUE : registers := (
NASTI_SLAVE_BANK_RESET,
((others => '0'), (others => '0'))
);
signal r, rin : registers;
signal r_istb, r_ostb, r_istb2, r_ostb2, r_istbin, r_ostbin : std_logic;
begin
comblogic : process(i, i_glip, r, nrst)
variable istb, ostb : std_logic;
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
begin
v := r;
istb := '0';
ostb := '0';
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := r.bank0.o_glip;
when 1 => tmp := r.bank0.i_glip; istb := '1';
when 2 => tmp := r.bank0.i_glip;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
wstrb := i.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i.w_data(32*(n+1)-1 downto 32*n);
if conv_integer(wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
v.bank0.o_glip := tmp; ostb := '1' ;
end if;
end loop;
end if;
o <= functionAxi4Output(r.bank_axi, rdata);
v.bank0.i_glip := i_glip;
if nrst = '0' then
v := RESET_VALUE;
end if;
rin <= v;
r_istbin <= istb;
r_ostbin <= ostb;
end process;
cfg <= xconfig;
o_glip <= (r_ostb and not r_ostb2) & (r_istb and not r_istb2) & r.bank0.o_glip(29 downto 0);
-- registers:
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
r_istb <= r_istbin;
r_ostb <= r_ostbin;
r_istb2 <= r_istb;
r_ostb2 <= r_ostb;
end if;
end process;
end;
|
bsd-2-clause
|
a52f8ea6047da8bd4e1ac5d70405374a
| 0.569668 | 3.26169 | false | false | false | false |
hoangt/PoC
|
src/misc/sync/sync_Bits_Altera.vhdl
| 2 | 3,365 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Bits_Altera
--
-- Description:
-- ------------------------------------
-- This is a multi-bit clock-domain-crossing circuit optimized for Altera FPGAs.
-- It generates 2 flip flops per input bit and notifies Quartus II, that these
-- flip flops are synchronizer flip flops. If you need a platform independent
-- version of this synchronizer, please use 'PoC.misc.sync.sync_Flag', which
-- internally instantiates this module if a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for long time stable signals (flags).
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Bits_Altera is
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits
);
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data
);
end entity;
architecture rtl of sync_Bits_Altera is
attribute PRESERVE : BOOLEAN;
attribute ALTERA_ATTRIBUTE : STRING;
-- Apply a SDC constraint to meta stable flip flop
attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """;
begin
gen : for i in 0 to BITS - 1 generate
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := INIT(i);
signal Data_sync : STD_LOGIC := INIT(i);
-- preserve both registers (no optimization, shift register extraction, ...)
attribute PRESERVE of Data_meta : signal is TRUE;
attribute PRESERVE of Data_sync : signal is TRUE;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute ALTERA_ATTRIBUTE of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
begin
Data_async <= Input(i);
process(Clock)
begin
if rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output(i) <= Data_sync;
end generate;
end architecture;
|
apache-2.0
|
42924ac8721a026c52ff6868ac198ad1
| 0.635661 | 3.797968 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/lmb_bram_if_cntlr.vhd
| 4 | 50,382 |
-------------------------------------------------------------------------------
-- lmb_bram_if_cntlr.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => false) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_TARGET => C_TARGET,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => true) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_TARGET => C_TARGET,
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
gpl-3.0
|
e8fe9c20181d5c27ffef0243d7fb8b42
| 0.536164 | 3.611354 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
| 1 | 14,171 |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Thu Nov 19 17:38:29 2015
--Host : ALI-WORKSTATION running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_io : inout STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end design_1_wrapper;
architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
reset : in STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
sys_clock : in STD_LOGIC
);
end component design_1;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal cellular_ram_dq_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal cellular_ram_dq_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal cellular_ram_dq_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal cellular_ram_dq_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal cellular_ram_dq_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal cellular_ram_dq_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal cellular_ram_dq_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal cellular_ram_dq_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal cellular_ram_dq_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal cellular_ram_dq_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal cellular_ram_dq_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal cellular_ram_dq_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal cellular_ram_dq_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal cellular_ram_dq_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal cellular_ram_dq_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal cellular_ram_dq_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal cellular_ram_dq_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal eth_mdio_mdc_mdio_i : STD_LOGIC;
signal eth_mdio_mdc_mdio_o : STD_LOGIC;
signal eth_mdio_mdc_mdio_t : STD_LOGIC;
begin
cellular_ram_dq_iobuf_0: component IOBUF
port map (
I => cellular_ram_dq_o_0(0),
IO => cellular_ram_dq_io(0),
O => cellular_ram_dq_i_0(0),
T => cellular_ram_dq_t_0(0)
);
cellular_ram_dq_iobuf_1: component IOBUF
port map (
I => cellular_ram_dq_o_1(1),
IO => cellular_ram_dq_io(1),
O => cellular_ram_dq_i_1(1),
T => cellular_ram_dq_t_1(1)
);
cellular_ram_dq_iobuf_10: component IOBUF
port map (
I => cellular_ram_dq_o_10(10),
IO => cellular_ram_dq_io(10),
O => cellular_ram_dq_i_10(10),
T => cellular_ram_dq_t_10(10)
);
cellular_ram_dq_iobuf_11: component IOBUF
port map (
I => cellular_ram_dq_o_11(11),
IO => cellular_ram_dq_io(11),
O => cellular_ram_dq_i_11(11),
T => cellular_ram_dq_t_11(11)
);
cellular_ram_dq_iobuf_12: component IOBUF
port map (
I => cellular_ram_dq_o_12(12),
IO => cellular_ram_dq_io(12),
O => cellular_ram_dq_i_12(12),
T => cellular_ram_dq_t_12(12)
);
cellular_ram_dq_iobuf_13: component IOBUF
port map (
I => cellular_ram_dq_o_13(13),
IO => cellular_ram_dq_io(13),
O => cellular_ram_dq_i_13(13),
T => cellular_ram_dq_t_13(13)
);
cellular_ram_dq_iobuf_14: component IOBUF
port map (
I => cellular_ram_dq_o_14(14),
IO => cellular_ram_dq_io(14),
O => cellular_ram_dq_i_14(14),
T => cellular_ram_dq_t_14(14)
);
cellular_ram_dq_iobuf_15: component IOBUF
port map (
I => cellular_ram_dq_o_15(15),
IO => cellular_ram_dq_io(15),
O => cellular_ram_dq_i_15(15),
T => cellular_ram_dq_t_15(15)
);
cellular_ram_dq_iobuf_2: component IOBUF
port map (
I => cellular_ram_dq_o_2(2),
IO => cellular_ram_dq_io(2),
O => cellular_ram_dq_i_2(2),
T => cellular_ram_dq_t_2(2)
);
cellular_ram_dq_iobuf_3: component IOBUF
port map (
I => cellular_ram_dq_o_3(3),
IO => cellular_ram_dq_io(3),
O => cellular_ram_dq_i_3(3),
T => cellular_ram_dq_t_3(3)
);
cellular_ram_dq_iobuf_4: component IOBUF
port map (
I => cellular_ram_dq_o_4(4),
IO => cellular_ram_dq_io(4),
O => cellular_ram_dq_i_4(4),
T => cellular_ram_dq_t_4(4)
);
cellular_ram_dq_iobuf_5: component IOBUF
port map (
I => cellular_ram_dq_o_5(5),
IO => cellular_ram_dq_io(5),
O => cellular_ram_dq_i_5(5),
T => cellular_ram_dq_t_5(5)
);
cellular_ram_dq_iobuf_6: component IOBUF
port map (
I => cellular_ram_dq_o_6(6),
IO => cellular_ram_dq_io(6),
O => cellular_ram_dq_i_6(6),
T => cellular_ram_dq_t_6(6)
);
cellular_ram_dq_iobuf_7: component IOBUF
port map (
I => cellular_ram_dq_o_7(7),
IO => cellular_ram_dq_io(7),
O => cellular_ram_dq_i_7(7),
T => cellular_ram_dq_t_7(7)
);
cellular_ram_dq_iobuf_8: component IOBUF
port map (
I => cellular_ram_dq_o_8(8),
IO => cellular_ram_dq_io(8),
O => cellular_ram_dq_i_8(8),
T => cellular_ram_dq_t_8(8)
);
cellular_ram_dq_iobuf_9: component IOBUF
port map (
I => cellular_ram_dq_o_9(9),
IO => cellular_ram_dq_io(9),
O => cellular_ram_dq_i_9(9),
T => cellular_ram_dq_t_9(9)
);
design_1_i: component design_1
port map (
cellular_ram_addr(22 downto 0) => cellular_ram_addr(22 downto 0),
cellular_ram_adv_ldn => cellular_ram_adv_ldn,
cellular_ram_ben(1 downto 0) => cellular_ram_ben(1 downto 0),
cellular_ram_ce_n => cellular_ram_ce_n,
cellular_ram_cre => cellular_ram_cre,
cellular_ram_dq_i(15) => cellular_ram_dq_i_15(15),
cellular_ram_dq_i(14) => cellular_ram_dq_i_14(14),
cellular_ram_dq_i(13) => cellular_ram_dq_i_13(13),
cellular_ram_dq_i(12) => cellular_ram_dq_i_12(12),
cellular_ram_dq_i(11) => cellular_ram_dq_i_11(11),
cellular_ram_dq_i(10) => cellular_ram_dq_i_10(10),
cellular_ram_dq_i(9) => cellular_ram_dq_i_9(9),
cellular_ram_dq_i(8) => cellular_ram_dq_i_8(8),
cellular_ram_dq_i(7) => cellular_ram_dq_i_7(7),
cellular_ram_dq_i(6) => cellular_ram_dq_i_6(6),
cellular_ram_dq_i(5) => cellular_ram_dq_i_5(5),
cellular_ram_dq_i(4) => cellular_ram_dq_i_4(4),
cellular_ram_dq_i(3) => cellular_ram_dq_i_3(3),
cellular_ram_dq_i(2) => cellular_ram_dq_i_2(2),
cellular_ram_dq_i(1) => cellular_ram_dq_i_1(1),
cellular_ram_dq_i(0) => cellular_ram_dq_i_0(0),
cellular_ram_dq_o(15) => cellular_ram_dq_o_15(15),
cellular_ram_dq_o(14) => cellular_ram_dq_o_14(14),
cellular_ram_dq_o(13) => cellular_ram_dq_o_13(13),
cellular_ram_dq_o(12) => cellular_ram_dq_o_12(12),
cellular_ram_dq_o(11) => cellular_ram_dq_o_11(11),
cellular_ram_dq_o(10) => cellular_ram_dq_o_10(10),
cellular_ram_dq_o(9) => cellular_ram_dq_o_9(9),
cellular_ram_dq_o(8) => cellular_ram_dq_o_8(8),
cellular_ram_dq_o(7) => cellular_ram_dq_o_7(7),
cellular_ram_dq_o(6) => cellular_ram_dq_o_6(6),
cellular_ram_dq_o(5) => cellular_ram_dq_o_5(5),
cellular_ram_dq_o(4) => cellular_ram_dq_o_4(4),
cellular_ram_dq_o(3) => cellular_ram_dq_o_3(3),
cellular_ram_dq_o(2) => cellular_ram_dq_o_2(2),
cellular_ram_dq_o(1) => cellular_ram_dq_o_1(1),
cellular_ram_dq_o(0) => cellular_ram_dq_o_0(0),
cellular_ram_dq_t(15) => cellular_ram_dq_t_15(15),
cellular_ram_dq_t(14) => cellular_ram_dq_t_14(14),
cellular_ram_dq_t(13) => cellular_ram_dq_t_13(13),
cellular_ram_dq_t(12) => cellular_ram_dq_t_12(12),
cellular_ram_dq_t(11) => cellular_ram_dq_t_11(11),
cellular_ram_dq_t(10) => cellular_ram_dq_t_10(10),
cellular_ram_dq_t(9) => cellular_ram_dq_t_9(9),
cellular_ram_dq_t(8) => cellular_ram_dq_t_8(8),
cellular_ram_dq_t(7) => cellular_ram_dq_t_7(7),
cellular_ram_dq_t(6) => cellular_ram_dq_t_6(6),
cellular_ram_dq_t(5) => cellular_ram_dq_t_5(5),
cellular_ram_dq_t(4) => cellular_ram_dq_t_4(4),
cellular_ram_dq_t(3) => cellular_ram_dq_t_3(3),
cellular_ram_dq_t(2) => cellular_ram_dq_t_2(2),
cellular_ram_dq_t(1) => cellular_ram_dq_t_1(1),
cellular_ram_dq_t(0) => cellular_ram_dq_t_0(0),
cellular_ram_oen => cellular_ram_oen,
cellular_ram_wait => cellular_ram_wait,
cellular_ram_wen => cellular_ram_wen,
eth_mdio_mdc_mdc => eth_mdio_mdc_mdc,
eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i,
eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o,
eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t,
eth_ref_clk => eth_ref_clk,
eth_rmii_crs_dv => eth_rmii_crs_dv,
eth_rmii_rx_er => eth_rmii_rx_er,
eth_rmii_rxd(1 downto 0) => eth_rmii_rxd(1 downto 0),
eth_rmii_tx_en => eth_rmii_tx_en,
eth_rmii_txd(1 downto 0) => eth_rmii_txd(1 downto 0),
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
eth_mdio_mdc_mdio_iobuf: component IOBUF
port map (
I => eth_mdio_mdc_mdio_o,
IO => eth_mdio_mdc_mdio_io,
O => eth_mdio_mdc_mdio_i,
T => eth_mdio_mdc_mdio_t
);
end STRUCTURE;
|
gpl-3.0
|
dd15651a8a371611682b1bfef03f3426
| 0.602498 | 2.733076 | false | false | false | false |
RussGlover/381-module-1
|
project/hardware/vhdl/lights.vhd
| 1 | 5,740 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY lights IS
PORT (
SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLOCK_50 : IN STD_LOGIC;
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DRAM_CLK, DRAM_CKE : OUT STD_LOGIC;
DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
DRAM_BA_0, DRAM_BA_1 : BUFFER STD_LOGIC;
DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
DRAM_UDQM, DRAM_LDQM : BUFFER STD_LOGIC;
LCD_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
LCD_ON, LCD_BLON, LCD_EN, LCD_RS, LCD_RW : OUT STD_LOGIC;
VGA_R: OUT std_logic_vector (9 downto 0);
VGA_G: OUT std_logic_vector(9 downto 0);
VGA_B: OUT std_logic_vector(9 downto 0);
VGA_CLK: OUT std_logic;
VGA_BLANK: OUT std_logic;
VGA_HS: OUT std_logic;
VGA_VS: OUT std_logic;
VGA_SYNC: OUT std_logic;
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 downto 0);
SRAM_LB_N : OUT STD_LOGIC;
SRAM_UB_N : OUT STD_LOGIC;
SRAM_CE_N : OUT STD_LOGIC;
SRAM_OE_N : OUT STD_LOGIC;
SRAM_WE_N : OUT STD_LOGIC;
SD_CMD : inout std_logic;
SD_DAT : inout std_logic;
SD_DAT3 : inout std_logic;
SD_CLK : out std_logic;
I2C_SDAT : inout std_logic;
I2C_SCLK : out std_logic;
AUD_XCK : out std_logic;
CLOCK_27 : in std_logic;
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic
);
END lights;
ARCHITECTURE Structure OF lights IS
COMPONENT nios_system
PORT (
clk_clk : IN STD_LOGIC;
reset_reset_n : IN STD_LOGIC;
sdram_clk_clk : OUT STD_LOGIC;
leds_export : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
switches_export : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
keys_export : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sdram_wire_addr : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sdram_wire_ba : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
sdram_wire_cas_n : OUT STD_LOGIC;
sdram_wire_cke : OUT STD_LOGIC;
sdram_wire_cs_n : OUT STD_LOGIC;
sdram_wire_dq : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sdram_wire_dqm : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0);
sdram_wire_ras_n : OUT STD_LOGIC;
sdram_wire_we_n : OUT STD_LOGIC ;
lcd_data_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
lcd_data_ON : OUT STD_LOGIC;
lcd_data_BLON : OUT STD_LOGIC;
lcd_data_EN : OUT STD_LOGIC;
lcd_data_RS : OUT STD_LOGIC;
lcd_data_RW : OUT STD_LOGIC;
vga_controller_R: OUT std_logic_vector(9 downto 0);
vga_controller_G: OUT std_logic_vector(9 downto 0);
vga_controller_B: OUT std_logic_vector(9 downto 0);
vga_controller_CLK: OUT std_logic;
vga_controller_BLANK: OUT std_logic;
vga_controller_HS: OUT std_logic;
vga_controller_VS: OUT std_logic;
vga_controller_SYNC: OUT std_logic;
pixel_buffer_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
pixel_buffer_ADDR : OUT STD_LOGIC_VECTOR(17 downto 0);
pixel_buffer_LB_N : OUT STD_LOGIC;
pixel_buffer_UB_N : OUT STD_LOGIC;
pixel_buffer_CE_N : OUT STD_LOGIC;
pixel_buffer_OE_N : OUT STD_LOGIC;
pixel_buffer_WE_N : OUT STD_LOGIC;
sdcard_b_SD_cmd : inout std_logic;
sdcard_b_SD_dat : inout std_logic;
sdcard_b_SD_dat3 : inout std_logic;
sdcard_o_SD_clock : out std_logic;
audio_and_video_config_SDAT : inout std_logic;
audio_and_video_config_SCLK : out std_logic;
audio_clk_clk : out std_logic;
clk_in_secondary_clk : in std_logic;
audio_ADCDAT : in std_logic;
audio_ADCLRCK : in std_logic;
audio_BCLK : in std_logic;
audio_DACDAT : out std_logic;
audio_DACLRCK : in std_logic
);
END COMPONENT;
SIGNAL DQM : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL BA : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
DRAM_BA_0 <= BA(0);
DRAM_BA_1 <= BA(1);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Instantiate the Nios II system entity generated by the Qsys tool.
NiosII: nios_system
PORT MAP (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_clk_clk => DRAM_CLK,
leds_export => LEDG,
switches_export => SW,
keys_export => KEY(3 DOWNTO 1),
sdram_wire_addr => DRAM_ADDR,
sdram_wire_ba => BA,
sdram_wire_cas_n => DRAM_CAS_N,
sdram_wire_cke => DRAM_CKE,
sdram_wire_cs_n => DRAM_CS_N,
sdram_wire_dq => DRAM_DQ,
sdram_wire_dqm => DQM,
sdram_wire_ras_n => DRAM_RAS_N,
sdcard_b_SD_cmd => SD_CMD,
sdcard_b_SD_dat => SD_DAT,
sdcard_b_SD_dat3 => SD_DAT3,
sdcard_o_SD_clock => SD_CLK,
sdram_wire_we_n => DRAM_WE_N,
lcd_data_DATA => LCD_DATA,
lcd_data_ON => LCD_ON,
lcd_data_EN => LCD_EN,
lcd_data_BLON => LCD_BLON,
lcd_data_RS => LCD_RS,
lcd_data_RW => LCD_RW,
vga_controller_CLK => VGA_CLK,
vga_controller_HS => VGA_HS,
vga_controller_VS => VGA_VS,
vga_controller_BLANK => VGA_BLANK,
vga_controller_SYNC => VGA_SYNC,
vga_controller_R => VGA_R,
vga_controller_G => VGA_G,
vga_controller_B => VGA_B,
pixel_buffer_DQ => SRAM_DQ,
pixel_buffer_ADDR => SRAM_ADDR,
pixel_buffer_LB_N => SRAM_LB_N,
pixel_buffer_UB_N => SRAM_UB_N,
pixel_buffer_CE_N => SRAM_CE_N,
pixel_buffer_OE_N => SRAM_OE_N,
pixel_buffer_WE_N => SRAM_WE_N,
audio_and_video_config_SDAT => I2C_SDAT,
audio_and_video_config_SCLK => I2C_SCLK,
audio_clk_clk => AUD_XCK,
clk_in_secondary_clk => CLOCK_27,
audio_ADCDAT => AUD_ADCDAT,
audio_ADCLRCK => AUD_ADCLRCK,
audio_BCLK => AUD_BCLK,
audio_DACDAT => AUD_DACDAT,
audio_DACLRCK => AUD_DACLRCK
);
END Structure;
|
mit
|
8fcb34a2c5cee636e2064ab89c04eb52
| 0.629443 | 2.734636 | false | false | false | false |
lowRISC/greth-library
|
greth_library/rocketlib/eth/grethc64.vhd
| 2 | 77,543 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethc
-- File: grethc.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library rocketlib;
use rocketlib.grethpkg.all;
entity grethc64 is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in eth_control_type;
cmdi : in eth_command_type;
statuso : out eth_mac_status_type;
--! Debug value read from internal buffers suing external bus interface
rdbgdatao : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
tmsto : out eth_tx_ahb_in_type;
tmsti : in eth_tx_ahb_out_type;
tmsto2 : out eth_tx_ahb_in_type;
tmsti2 : in eth_tx_ahb_out_type;
rmsto : out eth_rx_ahb_in_type;
rmsti : in eth_rx_ahb_out_type
);
end entity;
architecture rtl of grethc64 is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := capbil(4) or capbil(3) or capbil(2);
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
-- constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--tranceiver constants
constant maxsizetx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus1,
etdone, getlen, ahberror, fill_fifo2, wrbus2);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
status : eth_mac_status_type;
--master tx interface
tmsto : eth_tx_ahb_in_type;
tmsto2 : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxrenable : std_ulogic;
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrok : std_ulogic;
addrdone : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
msbgood : std_ulogic;
rxburstav : std_ulogic;
hashlookup : std_ulogic;
mcast : std_ulogic;
mcastacc : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_logic_vector(mdiohold-1 downto 0);
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
init_busy : std_ulogic;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
mdint_sync : std_logic_vector(2 downto 0);
--edcl
erenable : std_ulogic;
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
edclsepahb : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal r, rin : reg_type;
begin
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.status.reset;
irst <= rst and not r.status.reset;
comb : process(rst, irst, ctrli, cmdi, r, rmsti, tmsti, txo, rxo,
erdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, edcladdr, mdint, tmsti2, edcldisable,
edclsepahb) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vrdbgdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic; --rising mdio clk edge
variable nmclk : std_ulogic; --falling mdio clk edge
variable mclkvec : std_logic_vector(mdiohold downto 0);
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vrdbgdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0'; vrxfi.raddress := v.rfrpnt;
if edcl /= 0 then
veri.renable := r.erenable;
veri.datain := rxo.dataout;
veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
end if;
vtxfi.renable := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt;
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := r.rxrenable; vrxenable := r.status.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
if enable_mdint = 1 then
v.mdint_sync(0) := mdint;
v.mdint_sync(1) := r.mdint_sync(0);
v.mdint_sync(2) := r.mdint_sync(1);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
if cmdi.set_speed = '1' then v.status.speed := '1';
elsif cmdi.clr_speed = '1' then v.status.speed := '0';
end if;
if cmdi.set_reset = '1' then v.status.reset := '1';
elsif cmdi.clr_reset = '1' then v.status.reset := '0';
end if;
if cmdi.set_full_duplex = '1' then v.status.full_duplex := '1';
elsif cmdi.clr_full_duplex = '1' then v.status.full_duplex := '0';
end if;
if cmdi.set_rxena = '1' then v.status.rxen := '1';
elsif cmdi.clr_rxena = '1' then v.status.rxen := '0';
end if;
if cmdi.set_txena = '1' then v.status.txen := '1';
elsif cmdi.clr_txena = '1' then v.status.txen := '0';
end if;
if cmdi.clr_status_phystat = '1' then v.status.phystat := '0'; end if;
if cmdi.clr_status_invaddr = '1' then v.status.invaddr := '0'; end if;
if cmdi.clr_status_toosmall = '1' then v.status.toosmall := '0'; end if;
if cmdi.clr_status_txahberr = '1' then v.status.txahberr := '0'; end if;
if cmdi.clr_status_rxahberr = '1' then v.status.rxahberr := '0'; end if;
if cmdi.clr_status_tx_int = '1' then v.status.tx_int := '0'; end if;
if cmdi.clr_status_rx_int = '1' then v.status.rx_int := '0'; end if;
if cmdi.clr_status_tx_err = '1' then v.status.tx_err := '0'; end if;
if cmdi.clr_status_rx_err = '1' then v.status.rx_err := '0'; end if;
if cmdi.mdio_cmd.valid = '1' then
v.status.mdio.cmd.data := cmdi.mdio_cmd.data;
v.status.mdio.cmd.regadr := cmdi.mdio_cmd.regadr;
v.status.mdio.cmd.read := cmdi.mdio_cmd.read;
v.status.mdio.cmd.write := cmdi.mdio_cmd.write;
v.status.mdio.busy := cmdi.mdio_cmd.read or cmdi.mdio_cmd.write;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_TX_BUFFER then
vtxfi.write := cmdi.dbg_wr_ena;
vtxfi.waddress := cmdi.dbg_addr(txfabits+1 downto 2);
vtxfi.datain := cmdi.dbg_wdata;
vtxfi.raddress := cmdi.dbg_addr(txfabits+1 downto 2);
vtxfi.renable := cmdi.dbg_rd_ena;
vrdbgdata := txrdata;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_RX_BUFFER then
vrxfi.write := cmdi.dbg_wr_ena;
vrxfi.waddress := cmdi.dbg_addr(fabits+1 downto 2);
vrxfi.datain := cmdi.dbg_wdata;
vrxfi.raddress := cmdi.dbg_addr(fabits+1 downto 2);
vrxfi.renable := cmdi.dbg_rd_ena;
vrdbgdata := rxrdata;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_EDCL_BUFFER then
veri.writem := cmdi.dbg_wr_ena;
veri.writel := cmdi.dbg_wr_ena;
veri.waddressm := cmdi.dbg_addr(eabits+1 downto 2);
veri.waddressl := cmdi.dbg_addr(eabits+1 downto 2);
veri.datain := cmdi.dbg_wdata;
veri.raddress := cmdi.dbg_addr(eabits+1 downto 2);
veri.renable := cmdi.dbg_rd_ena;
vrdbgdata := erdata;
end if;
--PHY STATUS DETECTION
if enable_mdint = 1 then
if mdint_pol = 0 then
if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then
v.status.phystat := '1';
if ctrli.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
else
if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then
v.status.phystat := '1';
if ctrli.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
end if;
end if;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
if (conv_integer(r.abufs) /= 0) then
v.status.edcltx_idle := '0';
else
v.status.edcltx_idle := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0'; v.erenable := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and
(ctrli.edcldis = '0') then
v.erenable := '1'; v.status.edcltx_idle := '0';
if r.erenable = '1' then
v.txdstate := getlen;
end if;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.status.txen = '1' then
v.txdstate := read_desc;
v.tmsto.write := '0';
v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.req := '1';
--! AXI_ENABLE: burst transaction size in bytes
v.tmsto.burst_bytes := conv_std_logic_vector(8, 11);
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4;
if r.txburstcnt(0) = '1' then
v.tmsto.req := '0';
end if;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1;
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.status.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (unsigned(r.txlength) > unsigned(maxsizetx)) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result;
v.tmsto.req := '1';
v.tmsto.write := '1';
v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.data := (others => '0');
--! AXI_ENABLE: length of transaction not defined so use simple DMA access
v.tmsto.burst_bytes := conv_std_logic_vector(4,11);
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00";
v.txcnt(10 downto 0) := r.txlength;
--! AXI_ENABLE: length of transaction defined
v.tmsto.burst_bytes := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
if (edclsepahbg = 0) or (edcl = 0) or
(r.edclsepahb = '0') or (r.tedcl = '0') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
else
v.tmsto2.req := '1'; v.txdstate := fill_fifo2;
end if;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when fill_fifo2 =>
if edclsepahbg = 1 then
v.txburstav := '0';
vtxfi.datain := tmsti2.data;
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then
v.tmsto2.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto2.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := ctrli.tx_irqen and r.txirq;
if r.txwrap = '0' then v.status.txdsel := r.status.txdsel + 1;
else v.status.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.status.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
if ramdebug = 0 then
vtxfi.renable := v.txdataav;
else
vtxfi.renable := vtxfi.renable or v.txdataav;
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
if r.status.rxen = '1' then
v.rxdstate := read_desc;
v.rmsto.req := '1';
v.rmsto.addr := ctrli.rxdesc & r.status.rxdsel & "000";
--! AXI_ENABLE: burst transaction descriptor header size in bytes
v.rmsto.burst_bytes := conv_std_logic_vector(8, 11);
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4;
if r.rxburstcnt(0) = '1' then
v.rmsto.req := '0';
--! AXI_ENABLE: don't use burst operation:
v.rmsto.burst_bytes := conv_std_logic_vector(4,11);
end if;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1;
case r.rxcnt(1 downto 0) is
when "00" =>
v.status.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
v.rxrenable := '1';
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := ctrli.rxdesc & r.status.rxdsel & "000";
v.rxdstate := write_status2;
if multicast = 1 then
v.rmsto.data := "00000" & r.mcastacc & "0000000" &
r.rxstatus & "000" & r.rxlength;
else
v.rmsto.data := "0000000000000" &
r.rxstatus & "000" & r.rxlength;
end if;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (ctrli.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.status.rxdsel := (others => '0');
else
v.status.rxdsel := r.status.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
if r.rxstatus(3) = '1' then
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.rxdstate := idle;
elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if ctrli.prom = '1' then
v.addrok := '1';
end if;
v.mcast := r.checkdata(24);
if r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
if r.checkdata = ctrli.mac_addr(47 downto 16) then
v.msbgood := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) = broadcast(15 downto 0) then
if r.bcast = '1' then
v.addrok := '1';
end if;
else
v.bcast := '0';
end if;
if r.checkdata(31 downto 16) = ctrli.mac_addr(15 downto 0) then
if r.msbgood = '1' then
v.addrok := '1';
end if;
end if;
if multicast = 1 then
v.hashlookup := ctrli.hash(conv_integer(rxo.mcasthash));
end if;
when "011" =>
if multicast = 1 then
if (r.hashlookup and ctrli.mcasten and r.mcast) = '1' then
v.addrok := '1';
if r.bcast = '0' then
v.mcastacc := '1';
end if;
end if;
end if;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
v.addrdone := '1';
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
v.rxdoneack := not r.rxdoneack;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
if (ramdebug = 0) or (ctrli.ramdebugen = '0') then
vrxfi.raddress := v.rfrpnt;
end if;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclkvec := r.mdioclkold & r.mdioclk;
mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold);
nmclk := mclkvec(1) and not mclkvec(0);
v.mdioclkold := mclkvec(mdiohold-1 downto 0);
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
case r.mdio_state is
when idle =>
if (enable_mdio = 1) and (edcl = 0) and (r.status.reset = '1') then
v.mdio_state := idle; v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.write := '0'; v.status.mdio.busy := '0';
v.status.mdio.cmd.data := (others => '0');
v.status.mdio.cmd.regadr := (others => '0');
v.status.reset := '0';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if mclk = '1' then
v.cnt := (others => '0');
if r.status.mdio.busy = '1' then
v.status.mdio.linkfail := '0';
if r.status.mdio.cmd.read = '1' then
v.status.mdio.cmd.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
end if;
when preamble =>
if mclk = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
end if;
when startst =>
if mclk = '1' then
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
end if;
when op =>
if mclk = '1' then
v.mdio_state := op2;
if r.status.mdio.cmd.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
end if;
when op2 =>
if mclk = '1' then
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
end if;
when phyadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := ctrli.mdio_phyadr(4);
when 1 => v.mdioo := ctrli.mdio_phyadr(3);
when 2 => v.mdioo := ctrli.mdio_phyadr(2);
when 3 => v.mdioo := ctrli.mdio_phyadr(1);
when 4 => v.mdioo := ctrli.mdio_phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
end if;
when regadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.status.mdio.cmd.regadr(4);
when 1 => v.mdioo := r.status.mdio.cmd.regadr(3);
when 2 => v.mdioo := r.status.mdio.cmd.regadr(2);
when 3 => v.mdioo := r.status.mdio.cmd.regadr(1);
when 4 => v.mdioo := r.status.mdio.cmd.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
end if;
when ta =>
if mclk = '1' then
v.mdio_state := ta2;
if r.status.mdio.cmd.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
end if;
when ta2 =>
if mclk = '1' then
v.cnt := "01111"; v.mdio_state := ta3;
if r.status.mdio.cmd.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
end if;
when ta3 =>
if mclk = '1' then
v.mdio_state := data;
end if;
if nmclk = '1' then
if r.mdioi /= '0' then
v.status.mdio.linkfail := '1';
end if;
end if;
when data =>
if mclk = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
if r.status.mdio.cmd.read = '0' then
v.mdioo := r.status.mdio.cmd.data(mdioindex);
end if;
end if;
if nmclk = '1' then
if r.status.mdio.cmd.read = '1' then
v.status.mdio.cmd.data(mdioindex) := r.mdioi;
end if;
end if;
when dataend =>
if mclk = '1' then
if (rmii = 1) or (edcl /= 0) then
v.init_busy := '0';
if (r.duplexstate = done or ctrli.edcldis = '1' or ctrli.disableduplex = '1') then
v.status.mdio.busy := '0';
end if;
else
v.status.mdio.busy := '0';
end if;
v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
when others =>
null;
end case;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
if (ramdebug /= 2) or (ctrli.ramdebugen = '0') then
veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
vrxenable := '1';
end if;
swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0';
if vrxwrite = '1' then
if ctrli.edcldis = '0' then
v.rxwriteack := not r.rxwriteack;
end if;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0'; v.status.edclrx_idle := '1';
if (ramdebug /= 2) or (ctrli.ramdebugen = '0') then
if (rxstart and not ctrli.edcldis) = '1' then
v.edclrstate := wrda; v.edclactive := '0'; v.status.edclrx_idle := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (ctrli.emacaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (ctrli.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
if r.nak = '0' then
v.seq := r.seq + 1;
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := ctrli.emacaddr(31 downto 16) & ctrli.emacaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := ctrli.emacaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= ctrli.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= ctrli.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := ctrli.emacaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := ctrli.emacaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
-- AXI_ENABLE: EDCL burst length decoded from payload
v.tmsto.burst_bytes := r.txcnt;
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.addr := r.txaddr & "00";
v.tmsto2.write := r.write(conv_integer(r.tpnt));
-- AXI_ENABLE: EDCL burst length decoded from payload
v.tmsto2.burst_bytes := r.txcnt;
end if;
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
v.tmsto.req := '0';
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.req := '0';
end if;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.tedcl := '1';
v.tcnt := r.tcnt + 1;
if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then
v.tmsto.req := '1'; v.tmsto.data := erdata;
v.txdstate := wrbus1;
else
v.tmsto2.req := '1'; v.tmsto2.data := erdata;
v.txdstate := wrbus2;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus1 =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
when wrbus2 =>
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready or tmsti2.error) = '1' then
v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto2.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti2.retry = '1' then
v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1';
end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
if (ramdebug /= 2) or (edcl = 0) or (cmdi.dbg_rd_ena = '0') then
veri.raddress := r.tpnt & v.tcnt;
end if;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
if (ctrli.edcldis = '0' and ctrli.disableduplex = '0') then
v.status.mdio.cmd.regadr := r.regaddr; v.init_busy := '1';
v.status.mdio.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.status.mdio.cmd.write := '1';
else
v.status.mdio.cmd.read := '1';
end if;
if r.rstphy = '1' then
v.status.mdio.cmd.data := X"9000";
end if;
end if;
when waitop =>
if r.init_busy = '0' then
if r.status.mdio.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.status.mdio.cmd.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.status.mdio.cmd.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
if ctrli.disableduplex = '1' then
v.duplexstate := done; v.status.mdio.busy := '0';
end if;
when "00001" =>
v.ext := r.status.mdio.cmd.data(8); --extended status register
v.extcap := r.status.mdio.cmd.data(1); --extended register capabilities
v.duplexstate := start;
if r.status.mdio.cmd.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.status.mdio.cmd.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.status.mdio.cmd.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
if ctrli.disableduplex = '1' then
v.duplexstate := done; v.status.mdio.busy := '0';
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.status.mdio.cmd.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.status.mdio.cmd.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done; v.status.mdio.busy := '0';
if r.phywr = '1' then
v.status.full_duplex := '0'; v.status.speed := '0';
else
sel_op_mode(r.capbil, v.status.speed, v.status.full_duplex);
end if;
when done =>
null;
end case;
-- MDIO Disable
if ctrli.edcldis = '1' or ctrli.disableduplex = '1' then
if v.duplexstate /= start then
v.duplexstate := start;
v.status.mdio.cmd.regadr := (others => '0');
v.status.mdio.busy := '0';
v.init_busy := '0';
v.status.mdio.cmd.write := '0';
v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.data := X"0000";
end if;
end if;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
if (edclsepahbg /= 0) and (edcl /= 0) then
--transmitter retry
if tmsti2.retry = '1' then
v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto2.req := '0'; v.txdstate := ahberror;
end if;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.rfwpnt := (others => '0');
v.rfcnt := (others => '0');
v.status.txen := '0';
v.status.tx_int := '0';
v.status.rx_int := '0';
v.status.tx_err := '0';
v.status.rx_err := '0';
v.status.txahberr := '0';
v.status.rxahberr := '0';
v.txirqgen := '0'; v.status.rxen := '0';
v.status.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.status.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.status.invaddr := '0'; v.status.toosmall := '0';
v.status.full_duplex := '0'; v.writeok := '1';
if (enable_mdio = 0) or (edcl /= 0) then
v.status.reset := '0';
end if;
if enable_mdint = 1 then
v.status.phystat := '0';
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
end if;
if (rmii = 1) then
v.status.speed := '1';
else
v.status.speed := '1';
end if;
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
v.seq := (others => '0');
v.mdioo := '0';
if (enable_mdio = 1) then
v.mdccnt := divisor; v.mdioclk := '0';
end if;
v.status.reset := '0';
if (enable_mdio = 1) then
v.mdio_state := idle; v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.valid := '0';
v.status.mdio.cmd.write := '0'; v.status.mdio.busy := '0';
v.status.mdio.cmd.data := (others => '0');
v.status.mdio.cmd.regadr := (others => '0');
v.status.reset := '0'; v.status.mdio.linkfail := '1';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
v.cnt := (others => '0');
end if;
if edclsepahbg /= 0 then
v.edclsepahb := edclsepahb;
end if;
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
v.tedcl := '0'; v.erenable := '0';
v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
v.gotframe := '0';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.txburstav := '0'; v.txdataav := '0';
v.txstatus := (others => '0'); v.txstart := '0';
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0'); v.txaddr := (others => '0');
v.txdata := (others => '0');
v.txvalid := '0';
v.txlength := (others => '0');
v.cnt := (others => '0');
v.rxaddr := (others => '0');
v.rxstatus := (others => '0');
v.rxwrap := '0'; v.rxden := '0';
v.rmsto.req := '0';
v.rmsto.write := '0';
v.rmsto.addr := (others => '0');
v.rmsto.data := (others => '0');
v.tmsto.req := '0';
v.tmsto.write := '0';
v.tmsto.addr := (others => '0');
v.tmsto.data := (others => '0');
v.tmsto2.req := '0';
v.tmsto2.write := '0';
v.tmsto2.addr := (others => '0');
v.tmsto2.data := (others => '0');
v.nak := '0'; v.ewr := '0';
v.write := (others => '0');
v.applength := (others => '0');
v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0');
v.txwrap := '0';
v.txden := '0';
v.txirq := '0';
v.rxirq := '0';
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
rdbgdatao <= vrdbgdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
statuso <= r.status;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.status.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
rxi.rx_en <= rx_en;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.status.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.status.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
txi.datavalid <= tx_dv;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
tmsto2 <= r.tmsto2;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
speed <= r.status.speed;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
--! Tx FIFO
tx_fifo0 : syncram_2p_tech generic map (
tech => memtech,
abits => txfabits,
dbits => 32,
sepclk => 0
) port map (
clk,
txrenable,
txraddress(txfabits-1 downto 0),
txrdata,
clk,
txwrite,
txwaddress(txfabits-1 downto 0),
txwdata
);
--! Rx FIFO
rx_fifo0 : syncram_2p_tech generic map (
tech => memtech,
abits => fabits,
dbits => 32,
sepclk => 0
) port map (
clk,
rxrenable,
rxraddress(fabits-1 downto 0),
rxrdata,
clk,
rxwrite,
rxwaddress(fabits-1 downto 0),
rxwdata
);
--! EDCL buffer ram
edclramnft : if (edcl /= 0) generate
r0 : syncram_2p_tech generic map (
memtech,
eabits,
16
) port map (
clk,
erenable,
eraddress(eabits-1 downto 0),
erdata(31 downto 16),
clk,
ewritem,
ewaddressm(eabits-1 downto 0),
ewdata(31 downto 16)
);
r1 : syncram_2p_tech generic map (
memtech,
eabits,
16
) port map(
clk,
erenable,
eraddress(eabits-1 downto 0),
erdata(15 downto 0),
clk,
ewritel,
ewaddressl(eabits-1 downto 0),
ewdata(15 downto 0)
);
end generate;
end architecture;
|
bsd-2-clause
|
bfb49a024ec3b1071308b85215ac18cd
| 0.492643 | 3.551154 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_bmg_v1_0/1cb7cddc/hdl/src/vhdl/blk_mem_gen_wrapper.vhd
| 4 | 30,610 |
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
gpl-3.0
|
cfd28f6c3190cb7a330ff2ad9c1f3001
| 0.34773 | 4.864908 | false | false | false | false |
kevintownsend/convey_spmv
|
rtl/mac/OutputIEEE_11_52_to_11_52.vhdl
| 1 | 2,243 |
--------------------------------------------------------------------------------
-- OutputIEEE_11_52_to_11_52
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: F. Ferrandi (2009)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity OutputIEEE_11_52_to_11_52 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(11+52+2 downto 0);
R : out std_logic_vector(63 downto 0) );
end entity;
architecture arch of OutputIEEE_11_52_to_11_52 is
signal expX, expX_d1 : std_logic_vector(10 downto 0);
signal fracX, fracX_d1 : std_logic_vector(51 downto 0);
signal sX, sX_d1 : std_logic;
signal exnX, exnX_d1 : std_logic_vector(1 downto 0);
signal expZero, expZero_d1 : std_logic;
signal sfracX : std_logic_vector(51 downto 0);
signal fracR : std_logic_vector(51 downto 0);
signal expR : std_logic_vector(10 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
expX_d1 <= expX;
fracX_d1 <= fracX;
sX_d1 <= sX;
exnX_d1 <= exnX;
expZero_d1 <= expZero;
end if;
end process;
expX <= X(62 downto 52);
fracX <= X(51 downto 0);
sX <= X(63);
exnX <= X(65 downto 64);
expZero <= '1' when expX = (10 downto 0 => '0') else '0';
-- since we have one more exponent value than IEEE (field 0...0, value emin-1),
-- we can represent subnormal numbers whose mantissa field begins with a 1
----------------Synchro barrier, entering cycle 1----------------
sfracX <=
(51 downto 0 => '0') when (exnX_d1 = "00") else
'1' & fracX_d1(51 downto 1) when (expZero_d1 = '1' and exnX_d1 = "01") else
fracX_d1 when (exnX_d1 = "01") else
(51 downto 1 => '0') & exnX_d1(0);
fracR <= sfracX;
expR <=
(10 downto 0 => '0') when (exnX_d1 = "00") else
expX_d1 when (exnX_d1 = "01") else
(10 downto 0 => '1');
R <= sX_d1 & expR & fracR;
end architecture;
|
apache-2.0
|
fe496708fbb556efc32ed384d1d5a91d
| 0.547481 | 3.27924 | false | false | false | false |
MikhailKoslowski/Variax
|
Quartus/UartTransmitter.vhd
| 1 | 1,141 |
-----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY UartTransmitter IS
PORT (
clk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
send : IN STD_LOGIC;
rdy : OUT STD_LOGIC := '1';
TXD : OUT STD_LOGIC := '1'
);
END ENTITY;
-----------------------------------------------------------
ARCHITECTURE structure OF UartTransmitter IS
SIGNAL running : STD_LOGIC := '0';
SIGNAL s_data : STD_LOGIC_VECTOR (0 TO 9);
BEGIN
PROCESS (clk)
VARIABLE outBit : INTEGER RANGE -1 to 9 := -1;
BEGIN
IF clk'EVENT AND clk='1' THEN
IF send = '1' AND running = '0' THEN
s_data(1 TO 8) <= data;
s_data(9) <= '0'; -- Start bit
s_data(0) <= '1'; -- Stop bit
outBit := 9;
rdy <= '0';
running <= '1';
ELSIF running = '1' AND outBit >= 0 THEN
TXD <= s_data(outBit);
outBit := outBit-1;
ELSE
running <= '0';
rdy <= '1';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE structure;
|
mit
|
7d6765039aa2c82989923dc6aa575e93
| 0.501315 | 3.307246 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/synth/design_1_microblaze_0_axi_intc_0.vhd
| 2 | 11,544 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_intc:4.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_intc_v4_1;
USE axi_intc_v4_1.axi_intc;
ENTITY design_1_microblaze_0_axi_intc_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_microblaze_0_axi_intc_0;
ARCHITECTURE design_1_microblaze_0_axi_intc_0_arch OF design_1_microblaze_0_axi_intc_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_intc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_NUM_SW_INTR : INTEGER;
C_KIND_OF_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_EDGE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_LVL : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ASYNC_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_NUM_SYNC_FF : INTEGER;
C_IVAR_RESET_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ENABLE_ASYNC : INTEGER;
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_HAS_ILR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : STD_LOGIC;
C_DISABLE_SYNCHRONIZERS : INTEGER;
C_MB_CLK_NOT_CONNECTED : INTEGER;
C_HAS_FAST : INTEGER;
C_EN_CASCADE_MODE : INTEGER;
C_CASCADE_MASTER : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt_address_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
processor_ack_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi_intc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "axi_intc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_axi_intc_0_arch : ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_intc,x_ipVersion=4.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_intc_inst,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_NUM_INTR_INPUTS=2,C_NUM_SW_INTR=0,C_KIND_OF_INTR=0xfffffffe,C_KIND_OF_EDGE=0xffffffff,C_KIND_OF_LVL=0xffffffff,C_ASYNC_INTR=0xFFFFFFFC,C_NUM_SYNC_FF=2,C_IVAR_RESET_VALUE=0x00000010,C_ENABLE_ASYNC=0,C_HAS_IPR=1,C_HAS_SIE=1,C_HAS_CIE=1,C_HAS_IVR=1,C_HAS_ILR=0,C_IRQ_IS_LEVEL=1,C_IRQ_ACTIVE=0x1,C_DISABLE_SYNCHRONIZERS=1,C_MB_CLK_NOT_CONNECTED=1,C_HAS_FAST=1,C_EN_CASCADE_MODE=0,C_CASCADE_MASTER=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_resetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF intr: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 proc_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF processor_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 proc_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK";
ATTRIBUTE X_INTERFACE_INFO OF interrupt_address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS";
BEGIN
U0 : axi_intc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_intc_inst",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_INTR_INPUTS => 2,
C_NUM_SW_INTR => 0,
C_KIND_OF_INTR => X"fffffffe",
C_KIND_OF_EDGE => X"ffffffff",
C_KIND_OF_LVL => X"ffffffff",
C_ASYNC_INTR => X"FFFFFFFC",
C_NUM_SYNC_FF => 2,
C_IVAR_RESET_VALUE => X"00000010",
C_ENABLE_ASYNC => 0,
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_HAS_ILR => 0,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1',
C_DISABLE_SYNCHRONIZERS => 1,
C_MB_CLK_NOT_CONNECTED => 1,
C_HAS_FAST => 1,
C_EN_CASCADE_MODE => 0,
C_CASCADE_MASTER => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
intr => intr,
processor_clk => processor_clk,
processor_rst => processor_rst,
irq => irq,
processor_ack => processor_ack,
interrupt_address => interrupt_address,
interrupt_address_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_microblaze_0_axi_intc_0_arch;
|
gpl-3.0
|
bb515b60e8602cefa139b796abaa9260
| 0.686244 | 3.203997 | false | false | false | false |
s-kostyuk/vhdl_samples
|
cnt_jk_8/jk_trig.vhd
| 1 | 1,658 |
library IEEE;
use ieee.std_logic_1164.all;
entity jk_trig is
port (
R, S, C, J, K : in std_logic;
Q, notQ : out std_logic
);
end entity;
-- JK-триггер с синхронизацией по заднему фронту,
-- инверсными входами асинхронного сброса и установки
architecture jk_trig of jk_trig is
begin
-- Процесс со списком чувствительности,
-- в списке обычно указывают все входы схемы
process (R, S, C, J, K) is
-- декларативная часть процесса - объявляем переменные
variable vQ : std_logic;
-- Тело процесса
begin
if R = '0' and S = '0' then
-- Запрещенное состояние асинхронной части
vQ := 'X';
elsif R = '0' then
-- Асинхронный сброс в '0'
vQ := '0';
elsif S = '0' then
-- Асинхронная установка в '1'
vQ := '1';
elsif falling_edge(c) then
-- Синхронная часть
if J = '1' and K = '1' then
-- переключение в противоположное состояние
vQ := not vQ;
elsif J = '1' then
-- установка в 1-цу
vQ := '1';
elsif K = '1' then
-- сброс в ноль
vQ := '0';
end if;
end if;
-- Последние операторы параллельного назначения
-- выставляют полученное значение на выход с задержкой
Q <= vQ after 10 ns;
notQ <= not vQ after 10 ns;
end process;
end architecture;
|
mit
|
780f7e745006b34b0b2b2a2125211db4
| 0.643678 | 1.93949 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rx_fifo_disposer.vhd
| 4 | 28,176 |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
|
gpl-3.0
|
30d8b425a07eae7e8f31979f4c4231f5
| 0.415424 | 3.136242 | false | false | false | false |
lowRISC/greth-library
|
greth_library/techmap/mem/srambytes_tech.vhd
| 2 | 3,943 |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Internal SRAM implementation with the byte access.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity srambytes_tech is
generic (
memtech : integer := 0;
abits : integer := 16;
init_file : string := ""
);
port (
clk : in std_logic;
raddr : in global_addr_array_type;
rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
waddr : in global_addr_array_type;
we : in std_logic;
wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture rtl of srambytes_tech is
--! reduced name of configuration constant:
constant dw : integer := CFG_NASTI_ADDR_OFFSET;
type local_addr_type is array (0 to CFG_NASTI_DATA_BYTES-1) of
std_logic_vector(abits-dw-1 downto 0);
signal address : local_addr_type;
signal wr_ena : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
--! @brief Declaration of the one-byte SRAM element.
--! @details This component is used for the FPGA implementation.
component sram8_inferred is
generic (
abits : integer := 12;
byte_idx : integer := 0
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end component;
--! @brief Declaration of the one-byte SRAM element with init function.
--! @details This component is used for the RTL simulation.
component sram8_inferred_init is
generic (
abits : integer := 12;
byte_idx : integer := 0;
init_file : string
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end component;
begin
--! Instantiate component for RTL simulation
rtlsim0 : if memtech = inferred generate
rx : for n in 0 to CFG_NASTI_DATA_BYTES-1 generate
wr_ena(n) <= we and wstrb(n);
address(n) <= waddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw) when we = '1'
else raddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw);
x0 : sram8_inferred_init generic map
(
abits => abits-dw,
byte_idx => n,
init_file => init_file
) port map (
clk,
address => address(n),
rdata => rdata(8*(n+1)-1 downto 8*n),
we => wr_ena(n),
wdata => wdata(8*(n+1)-1 downto 8*n)
);
end generate; -- cycle
end generate; -- tech=inferred
--! Instantiate component for FPGA (checked with Xilinx)
fpgasim0 : if memtech /= inferred and is_fpga(memtech) /= 0 generate
rx : for n in 0 to CFG_NASTI_DATA_BYTES-1 generate
wr_ena(n) <= we and wstrb(n);
address(n) <= waddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw) when we = '1'
else raddr(n / CFG_ALIGN_BYTES)(abits-1 downto dw);
x0 : sram8_inferred generic map
(
abits => abits-dw,
byte_idx => n
) port map (
clk,
address => address(n),
rdata => rdata(8*(n+1)-1 downto 8*n),
we => wr_ena(n),
wdata => wdata(8*(n+1)-1 downto 8*n)
);
end generate; -- cycle
end generate; -- tech=inferred
end;
|
bsd-2-clause
|
6df4ff718141a0b005cd8d63c7100893
| 0.57824 | 3.617431 | false | false | false | false |
hoangt/PoC
|
tb/arith/arith_convert_bin2bcd_tb.vhdl
| 2 | 4,567 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Converter Binary to BCD.
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith_converter_bin2bcd
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
entity arith_convert_bin2bcd_tb is
end;
architecture test of arith_convert_bin2bcd_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant INPUT_1 : INTEGER := 38442113;
constant INPUT_2 : INTEGER := 78734531;
constant INPUT_3 : INTEGER := 14902385;
constant CONV1_BITS : POSITIVE := 30;
constant CONV1_DIGITS : POSITIVE := 8;
constant CONV2_BITS : POSITIVE := 27;
constant CONV2_DIGITS : POSITIVE := 8;
signal SimStop : std_logic := '0';
signal Clock : STD_LOGIC := '1';
signal Reset : STD_LOGIC := '0';
signal Start : STD_LOGIC := '0';
signal Conv1_Binary : STD_LOGIC_VECTOR(CONV1_BITS - 1 downto 0);
signal Conv1_BCDDigits : T_BCD_VECTOR(CONV1_DIGITS - 1 DOWNTO 0);
signal Conv1_Sign : STD_LOGIC;
signal Conv2_Binary : STD_LOGIC_VECTOR(CONV2_BITS - 1 downto 0);
signal Conv2_BCDDigits : T_BCD_VECTOR(CONV2_DIGITS - 1 DOWNTO 0);
signal Conv2_Sign : STD_LOGIC;
begin
blkClock : block
constant CLOCK_PERIOD : TIME := to_time(CLOCK_FREQ);
begin
Clock <= Clock xnor SimStop after CLOCK_PERIOD / 2.0;
end block;
process
begin
wait until rising_edge(Clock);
Reset <= '1';
wait until rising_edge(Clock);
Reset <= '0';
wait until rising_edge(Clock);
Start <= '1';
Conv1_Binary <= to_slv(INPUT_1, CONV1_BITS);
Conv2_Binary <= to_slv(INPUT_1, CONV2_BITS);
wait until rising_edge(Clock);
Start <= '0';
wait until rising_edge(Clock);
for i in 0 to (CONV1_BITS - 1) loop
wait until rising_edge(Clock);
end loop;
Start <= '1';
Conv1_Binary <= to_slv(INPUT_2, CONV1_BITS);
Conv2_Binary <= to_slv(INPUT_2, CONV2_BITS);
wait until rising_edge(Clock);
Start <= '0';
wait until rising_edge(Clock);
for i in 0 to (CONV1_BITS - 1) loop
wait until rising_edge(Clock);
end loop;
Start <= '1';
Conv1_Binary <= to_slv(INPUT_3, CONV1_BITS);
Conv2_Binary <= to_slv(INPUT_3, CONV2_BITS);
wait until rising_edge(Clock);
Start <= '0';
wait until rising_edge(Clock);
for i in 0 to (CONV1_BITS - 1) loop
wait until rising_edge(Clock);
end loop;
wait until rising_edge(Clock);
wait until rising_edge(Clock);
-- Report overall simulation result
tbPrintResult;
SimStop <= '1';
wait;
end process;
conv1 : entity PoC.arith_convert_bin2bcd
generic map (
BITS => CONV1_BITS,
DIGITS => CONV1_DIGITS,
RADIX => 8
)
port map (
Clock => Clock,
Reset => Reset,
Start => Start,
Busy => open,
Binary => Conv1_Binary,
IsSigned => '0',
BCDDigits => Conv1_BCDDigits,
Sign => Conv1_Sign
);
conv2 : entity PoC.arith_convert_bin2bcd
generic map (
BITS => CONV2_BITS,
DIGITS => CONV2_DIGITS,
RADIX => 2
)
port map (
Clock => Clock,
Reset => Reset,
Start => Start,
Busy => open,
Binary => Conv2_Binary,
IsSigned => '1',
BCDDigits => Conv2_BCDDigits,
Sign => Conv2_Sign
);
end;
|
apache-2.0
|
dc0498c3b6fb8a730ea6b3d45bf8e7e2
| 0.595139 | 3.087897 | false | false | false | false |
bpervan/uart
|
UARTEcho.vhd
| 1 | 2,262 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:44:11 03/13/2014
-- Design Name:
-- Module Name: UARTEcho - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTEcho is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC;
led : out std_logic_vector (6 downto 0));
end UARTEcho;
architecture Behavioral of UARTEcho is
component UARTController port
( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx : in STD_LOGIC;
w_data : in STD_LOGIC_VECTOR (7 downto 0);
w_start : in STD_LOGIC;
tx : out STD_LOGIC;
w_done : out STD_LOGIC;
r_data : out STD_LOGIC_VECTOR (7 downto 0);
r_done : out STD_LOGIC;
led_out : out std_logic_vector (6 downto 0));
end component;
component Echo port
( d_in : in STD_LOGIC_VECTOR (7 downto 0);
r_done : in STD_LOGIC;
w_done : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
w_start : out STD_LOGIC;
d_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal w_data: std_logic_vector (7 downto 0);
signal w_start: std_logic;
signal w_done: std_logic;
signal r_done_sig: std_logic;
signal r_data: std_logic_vector (7 downto 0);
begin
UARTCon: entity work.UARTController port map (clk => clk, rst => rst, rx => rx, w_data => w_data, w_start => w_start,
tx => tx, w_done => w_done, r_data => r_data, r_done => r_done_sig, led_out => led);
EchoModul: entity work.Echo port map (d_in => r_data, r_done => r_done_sig, w_done => w_done, clk => clk, rst => rst, w_start => w_start, d_out => w_data);
end Behavioral;
|
mit
|
68665ef971db1ab2aac30f5eaa9a551b
| 0.591512 | 3.236052 | false | false | false | false |
kevintownsend/convey_spmv
|
rtl/mac/FPAdder_11_52_uid2.vhdl
| 1 | 26,372 |
-- Flopoco adder pipeline delay: 14 clock cycles
-- TODO: verilog instantiation
--------------------------------------------------------------------------------
-- IntAdder_66_f400_uid4
-- (IntAdderAlternative_66_f400_uid8)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_66_f400_uid4 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end entity;
architecture arch of IntAdder_66_f400_uid4 is
signal s_sum_l0_idx0 : std_logic_vector(42 downto 0);
signal s_sum_l0_idx1, s_sum_l0_idx1_d1 : std_logic_vector(24 downto 0);
signal sum_l0_idx0, sum_l0_idx0_d1 : std_logic_vector(41 downto 0);
signal c_l0_idx0, c_l0_idx0_d1 : std_logic_vector(0 downto 0);
signal sum_l0_idx1 : std_logic_vector(23 downto 0);
signal c_l0_idx1 : std_logic_vector(0 downto 0);
signal s_sum_l1_idx1 : std_logic_vector(24 downto 0);
signal sum_l1_idx1 : std_logic_vector(23 downto 0);
signal c_l1_idx1 : std_logic_vector(0 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
s_sum_l0_idx1_d1 <= s_sum_l0_idx1;
sum_l0_idx0_d1 <= sum_l0_idx0;
c_l0_idx0_d1 <= c_l0_idx0;
end if;
end process;
--Alternative
s_sum_l0_idx0 <= ( "0" & X(41 downto 0)) + ( "0" & Y(41 downto 0)) + Cin;
s_sum_l0_idx1 <= ( "0" & X(65 downto 42)) + ( "0" & Y(65 downto 42));
sum_l0_idx0 <= s_sum_l0_idx0(41 downto 0);
c_l0_idx0 <= s_sum_l0_idx0(42 downto 42);
sum_l0_idx1 <= s_sum_l0_idx1(23 downto 0);
c_l0_idx1 <= s_sum_l0_idx1(24 downto 24);
----------------Synchro barrier, entering cycle 1----------------
s_sum_l1_idx1 <= s_sum_l0_idx1_d1 + c_l0_idx0_d1(0 downto 0);
sum_l1_idx1 <= s_sum_l1_idx1(23 downto 0);
c_l1_idx1 <= s_sum_l1_idx1(24 downto 24);
R <= sum_l1_idx1(23 downto 0) & sum_l0_idx0_d1(41 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_11_52_uid2_RightShifter
-- (RightShifter_53_by_max_55_uid10)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity FPAdder_11_52_uid2_RightShifter is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
S : in std_logic_vector(5 downto 0);
R : out std_logic_vector(107 downto 0) );
end entity;
architecture arch of FPAdder_11_52_uid2_RightShifter is
signal level0 : std_logic_vector(52 downto 0);
signal ps, ps_d1 : std_logic_vector(5 downto 0);
signal level1 : std_logic_vector(53 downto 0);
signal level2 : std_logic_vector(55 downto 0);
signal level3 : std_logic_vector(59 downto 0);
signal level4, level4_d1 : std_logic_vector(67 downto 0);
signal level5 : std_logic_vector(83 downto 0);
signal level6 : std_logic_vector(115 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
ps_d1 <= ps;
level4_d1 <= level4;
end if;
end process;
level0<= X;
ps<= S;
level1<= (0 downto 0 => '0') & level0 when ps(0) = '1' else level0 & (0 downto 0 => '0');
level2<= (1 downto 0 => '0') & level1 when ps(1) = '1' else level1 & (1 downto 0 => '0');
level3<= (3 downto 0 => '0') & level2 when ps(2) = '1' else level2 & (3 downto 0 => '0');
level4<= (7 downto 0 => '0') & level3 when ps(3) = '1' else level3 & (7 downto 0 => '0');
----------------Synchro barrier, entering cycle 1----------------
level5<= (15 downto 0 => '0') & level4_d1 when ps_d1(4) = '1' else level4_d1 & (15 downto 0 => '0');
level6<= (31 downto 0 => '0') & level5 when ps_d1(5) = '1' else level5 & (31 downto 0 => '0');
R <= level6(115 downto 8);
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_56_f400_uid12
-- (IntAdderClassical_56_f400_uid14)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_56_f400_uid12 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(55 downto 0);
Y : in std_logic_vector(55 downto 0);
Cin : in std_logic;
R : out std_logic_vector(55 downto 0) );
end entity;
architecture arch of IntAdder_56_f400_uid12 is
signal x0 : std_logic_vector(10 downto 0);
signal y0 : std_logic_vector(10 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(2 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(2 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(11 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
end if;
end process;
--Classical
x0 <= X(10 downto 0);
y0 <= Y(10 downto 0);
x1 <= X(52 downto 11);
y1 <= Y(52 downto 11);
x2 <= X(55 downto 53);
y2 <= Y(55 downto 53);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin;
----------------Synchro barrier, entering cycle 1----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(11);
----------------Synchro barrier, entering cycle 2----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(2 downto 0) & sum1_d1(41 downto 0) & sum0_d2(10 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- LZCShifter_57_to_57_counting_64_uid18
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Florent de Dinechin, Bogdan Pasca (2007)
--------------------------------------------------------------------------------
-- Pipeline depth: 5 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity LZCShifter_57_to_57_counting_64_uid18 is
port ( clk, rst : in std_logic;
I : in std_logic_vector(56 downto 0);
Count : out std_logic_vector(5 downto 0);
O : out std_logic_vector(56 downto 0) );
end entity;
architecture arch of LZCShifter_57_to_57_counting_64_uid18 is
signal level6, level6_d1 : std_logic_vector(56 downto 0);
signal count5, count5_d1, count5_d2, count5_d3, count5_d4, count5_d5 : std_logic;
signal level5 : std_logic_vector(56 downto 0);
signal count4, count4_d1, count4_d2, count4_d3, count4_d4 : std_logic;
signal level4, level4_d1 : std_logic_vector(56 downto 0);
signal count3, count3_d1, count3_d2, count3_d3 : std_logic;
signal level3, level3_d1 : std_logic_vector(56 downto 0);
signal count2, count2_d1, count2_d2 : std_logic;
signal level2, level2_d1 : std_logic_vector(56 downto 0);
signal count1, count1_d1 : std_logic;
signal level1, level1_d1 : std_logic_vector(56 downto 0);
signal count0 : std_logic;
signal level0 : std_logic_vector(56 downto 0);
signal sCount : std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
level6_d1 <= level6;
count5_d1 <= count5;
count5_d2 <= count5_d1;
count5_d3 <= count5_d2;
count5_d4 <= count5_d3;
count5_d5 <= count5_d4;
count4_d1 <= count4;
count4_d2 <= count4_d1;
count4_d3 <= count4_d2;
count4_d4 <= count4_d3;
level4_d1 <= level4;
count3_d1 <= count3;
count3_d2 <= count3_d1;
count3_d3 <= count3_d2;
level3_d1 <= level3;
count2_d1 <= count2;
count2_d2 <= count2_d1;
level2_d1 <= level2;
count1_d1 <= count1;
level1_d1 <= level1;
end if;
end process;
level6 <= I ;
count5<= '1' when level6(56 downto 25) = (56 downto 25=>'0') else '0';
----------------Synchro barrier, entering cycle 1----------------
level5<= level6_d1(56 downto 0) when count5_d1='0' else level6_d1(24 downto 0) & (31 downto 0 => '0');
count4<= '1' when level5(56 downto 41) = (56 downto 41=>'0') else '0';
level4<= level5(56 downto 0) when count4='0' else level5(40 downto 0) & (15 downto 0 => '0');
----------------Synchro barrier, entering cycle 2----------------
count3<= '1' when level4_d1(56 downto 49) = (56 downto 49=>'0') else '0';
level3<= level4_d1(56 downto 0) when count3='0' else level4_d1(48 downto 0) & (7 downto 0 => '0');
----------------Synchro barrier, entering cycle 3----------------
count2<= '1' when level3_d1(56 downto 53) = (56 downto 53=>'0') else '0';
level2<= level3_d1(56 downto 0) when count2='0' else level3_d1(52 downto 0) & (3 downto 0 => '0');
----------------Synchro barrier, entering cycle 4----------------
count1<= '1' when level2_d1(56 downto 55) = (56 downto 55=>'0') else '0';
level1<= level2_d1(56 downto 0) when count1='0' else level2_d1(54 downto 0) & (1 downto 0 => '0');
----------------Synchro barrier, entering cycle 5----------------
count0<= '1' when level1_d1(56 downto 56) = (56 downto 56=>'0') else '0';
level0<= level1_d1(56 downto 0) when count0='0' else level1_d1(55 downto 0) & (0 downto 0 => '0');
O <= level0;
sCount <= count5_d5 & count4_d4 & count3_d3 & count2_d2 & count1_d1 & count0;
Count <= sCount;
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_66_f400_uid20
-- (IntAdderClassical_66_f400_uid22)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_66_f400_uid20 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end entity;
architecture arch of IntAdder_66_f400_uid20 is
signal x0 : std_logic_vector(17 downto 0);
signal y0 : std_logic_vector(17 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(5 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(5 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(18 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(6 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
end if;
end process;
--Classical
x0 <= X(17 downto 0);
y0 <= Y(17 downto 0);
x1 <= X(59 downto 18);
y1 <= Y(59 downto 18);
x2 <= X(65 downto 60);
y2 <= Y(65 downto 60);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin;
----------------Synchro barrier, entering cycle 1----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(18);
----------------Synchro barrier, entering cycle 2----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(5 downto 0) & sum1_d1(41 downto 0) & sum0_d2(17 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- FPAdder_11_52_uid2
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 14 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity FPAdder_11_52_uid2 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(11+52+2 downto 0);
Y : in std_logic_vector(11+52+2 downto 0);
R : out std_logic_vector(11+52+2 downto 0) );
end entity;
architecture arch of FPAdder_11_52_uid2 is
component FPAdder_11_52_uid2_RightShifter is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
S : in std_logic_vector(5 downto 0);
R : out std_logic_vector(107 downto 0) );
end component;
component IntAdder_56_f400_uid12 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(55 downto 0);
Y : in std_logic_vector(55 downto 0);
Cin : in std_logic;
R : out std_logic_vector(55 downto 0) );
end component;
component IntAdder_66_f400_uid20 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end component;
component IntAdder_66_f400_uid4 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(65 downto 0);
Y : in std_logic_vector(65 downto 0);
Cin : in std_logic;
R : out std_logic_vector(65 downto 0) );
end component;
component LZCShifter_57_to_57_counting_64_uid18 is
port ( clk, rst : in std_logic;
I : in std_logic_vector(56 downto 0);
Count : out std_logic_vector(5 downto 0);
O : out std_logic_vector(56 downto 0) );
end component;
signal excExpFracX : std_logic_vector(64 downto 0);
signal excExpFracY : std_logic_vector(64 downto 0);
signal eXmeY, eXmeY_d1 : std_logic_vector(11 downto 0);
signal eYmeX, eYmeX_d1 : std_logic_vector(11 downto 0);
signal addCmpOp1 : std_logic_vector(65 downto 0);
signal addCmpOp2 : std_logic_vector(65 downto 0);
signal cmpRes : std_logic_vector(65 downto 0);
signal swap : std_logic;
signal newX, newX_d1, newX_d2, newX_d3 : std_logic_vector(65 downto 0);
signal newY, newY_d1 : std_logic_vector(65 downto 0);
signal expX, expX_d1, expX_d2, expX_d3, expX_d4, expX_d5 : std_logic_vector(10 downto 0);
signal excX : std_logic_vector(1 downto 0);
signal excY, excY_d1 : std_logic_vector(1 downto 0);
signal signX, signX_d1 : std_logic;
signal signY : std_logic;
signal EffSub, EffSub_d1, EffSub_d2, EffSub_d3, EffSub_d4, EffSub_d5, EffSub_d6, EffSub_d7, EffSub_d8, EffSub_d9, EffSub_d10, EffSub_d11, EffSub_d12, EffSub_d13 : std_logic;
signal sdsXsYExnXY, sdsXsYExnXY_d1 : std_logic_vector(5 downto 0);
signal sdExnXY : std_logic_vector(3 downto 0);
signal fracY : std_logic_vector(52 downto 0);
signal excRt, excRt_d1, excRt_d2, excRt_d3, excRt_d4, excRt_d5, excRt_d6, excRt_d7, excRt_d8, excRt_d9, excRt_d10, excRt_d11, excRt_d12 : std_logic_vector(1 downto 0);
signal signR, signR_d1, signR_d2, signR_d3, signR_d4, signR_d5, signR_d6, signR_d7, signR_d8, signR_d9, signR_d10, signR_d11, signR_d12 : std_logic;
signal expDiff : std_logic_vector(11 downto 0);
signal shiftedOut : std_logic;
signal shiftVal, shiftVal_d1 : std_logic_vector(5 downto 0);
signal shiftedFracY, shiftedFracY_d1 : std_logic_vector(107 downto 0);
signal sticky, sticky_d1, sticky_d2 : std_logic;
signal fracYfar : std_logic_vector(55 downto 0);
signal fracYfarXorOp : std_logic_vector(55 downto 0);
signal fracXfar : std_logic_vector(55 downto 0);
signal cInAddFar : std_logic;
signal fracAddResult : std_logic_vector(55 downto 0);
signal fracGRS : std_logic_vector(56 downto 0);
signal extendedExpInc, extendedExpInc_d1, extendedExpInc_d2, extendedExpInc_d3, extendedExpInc_d4, extendedExpInc_d5, extendedExpInc_d6 : std_logic_vector(12 downto 0);
signal nZerosNew, nZerosNew_d1 : std_logic_vector(5 downto 0);
signal shiftedFrac, shiftedFrac_d1 : std_logic_vector(56 downto 0);
signal updatedExp : std_logic_vector(12 downto 0);
signal eqdiffsign, eqdiffsign_d1, eqdiffsign_d2 : std_logic;
signal expFrac : std_logic_vector(65 downto 0);
signal stk, stk_d1 : std_logic;
signal rnd, rnd_d1 : std_logic;
signal grd, grd_d1 : std_logic;
signal lsb, lsb_d1 : std_logic;
signal addToRoundBit : std_logic;
signal RoundedExpFrac : std_logic_vector(65 downto 0);
signal upExc : std_logic_vector(1 downto 0);
signal fracR : std_logic_vector(51 downto 0);
signal expR : std_logic_vector(10 downto 0);
signal exExpExc : std_logic_vector(3 downto 0);
signal excRt2 : std_logic_vector(1 downto 0);
signal excR : std_logic_vector(1 downto 0);
signal computedR : std_logic_vector(65 downto 0);
signal X_d1 : std_logic_vector(11+52+2 downto 0);
signal Y_d1 : std_logic_vector(11+52+2 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
eXmeY_d1 <= eXmeY;
eYmeX_d1 <= eYmeX;
newX_d1 <= newX;
newX_d2 <= newX_d1;
newX_d3 <= newX_d2;
newY_d1 <= newY;
expX_d1 <= expX;
expX_d2 <= expX_d1;
expX_d3 <= expX_d2;
expX_d4 <= expX_d3;
expX_d5 <= expX_d4;
excY_d1 <= excY;
signX_d1 <= signX;
EffSub_d1 <= EffSub;
EffSub_d2 <= EffSub_d1;
EffSub_d3 <= EffSub_d2;
EffSub_d4 <= EffSub_d3;
EffSub_d5 <= EffSub_d4;
EffSub_d6 <= EffSub_d5;
EffSub_d7 <= EffSub_d6;
EffSub_d8 <= EffSub_d7;
EffSub_d9 <= EffSub_d8;
EffSub_d10 <= EffSub_d9;
EffSub_d11 <= EffSub_d10;
EffSub_d12 <= EffSub_d11;
EffSub_d13 <= EffSub_d12;
sdsXsYExnXY_d1 <= sdsXsYExnXY;
excRt_d1 <= excRt;
excRt_d2 <= excRt_d1;
excRt_d3 <= excRt_d2;
excRt_d4 <= excRt_d3;
excRt_d5 <= excRt_d4;
excRt_d6 <= excRt_d5;
excRt_d7 <= excRt_d6;
excRt_d8 <= excRt_d7;
excRt_d9 <= excRt_d8;
excRt_d10 <= excRt_d9;
excRt_d11 <= excRt_d10;
excRt_d12 <= excRt_d11;
signR_d1 <= signR;
signR_d2 <= signR_d1;
signR_d3 <= signR_d2;
signR_d4 <= signR_d3;
signR_d5 <= signR_d4;
signR_d6 <= signR_d5;
signR_d7 <= signR_d6;
signR_d8 <= signR_d7;
signR_d9 <= signR_d8;
signR_d10 <= signR_d9;
signR_d11 <= signR_d10;
signR_d12 <= signR_d11;
shiftVal_d1 <= shiftVal;
shiftedFracY_d1 <= shiftedFracY;
sticky_d1 <= sticky;
sticky_d2 <= sticky_d1;
extendedExpInc_d1 <= extendedExpInc;
extendedExpInc_d2 <= extendedExpInc_d1;
extendedExpInc_d3 <= extendedExpInc_d2;
extendedExpInc_d4 <= extendedExpInc_d3;
extendedExpInc_d5 <= extendedExpInc_d4;
extendedExpInc_d6 <= extendedExpInc_d5;
nZerosNew_d1 <= nZerosNew;
shiftedFrac_d1 <= shiftedFrac;
eqdiffsign_d1 <= eqdiffsign;
eqdiffsign_d2 <= eqdiffsign_d1;
stk_d1 <= stk;
rnd_d1 <= rnd;
grd_d1 <= grd;
lsb_d1 <= lsb;
X_d1 <= X;
Y_d1 <= Y;
end if;
end process;
-- Exponent difference and swap --
excExpFracX <= X(65 downto 64) & X(62 downto 0);
excExpFracY <= Y(65 downto 64) & Y(62 downto 0);
eXmeY <= ("0" & X(62 downto 52)) - ("0" & Y(62 downto 52));
eYmeX <= ("0" & Y(62 downto 52)) - ("0" & X(62 downto 52));
addCmpOp1<= "0" & excExpFracX;
addCmpOp2<= "1" & not(excExpFracY);
cmpAdder: IntAdder_66_f400_uid4 -- pipelineDepth=1 maxInDelay=0
port map ( clk => clk,
rst => rst,
Cin => '1',
R => cmpRes,
X => addCmpOp1,
Y => addCmpOp2);
----------------Synchro barrier, entering cycle 1----------------
swap <= cmpRes(65);
newX <= X_d1 when swap = '0' else Y_d1;
newY <= Y_d1 when swap = '0' else X_d1;
expX<= newX(62 downto 52);
excX<= newX(65 downto 64);
excY<= newY(65 downto 64);
signX<= newX(63);
signY<= newY(63);
EffSub <= signX xor signY;
sdsXsYExnXY <= signX & signY & excX & excY;
sdExnXY <= excX & excY;
----------------Synchro barrier, entering cycle 2----------------
fracY <= "00000000000000000000000000000000000000000000000000000" when excY_d1="00" else ('1' & newY_d1(51 downto 0));
with sdsXsYExnXY_d1 select
excRt <= "00" when "000000"|"010000"|"100000"|"110000",
"01" when "000101"|"010101"|"100101"|"110101"|"000100"|"010100"|"100100"|"110100"|"000001"|"010001"|"100001"|"110001",
"10" when "111010"|"001010"|"001000"|"011000"|"101000"|"111000"|"000010"|"010010"|"100010"|"110010"|"001001"|"011001"|"101001"|"111001"|"000110"|"010110"|"100110"|"110110",
"11" when others;
signR<= '0' when (sdsXsYExnXY_d1="100000" or sdsXsYExnXY_d1="010000") else signX_d1;
---------------- cycle 1----------------
expDiff <= eXmeY_d1 when swap = '0' else eYmeX_d1;
shiftedOut <= '1' when (expDiff >= 54) else '0';
shiftVal <= expDiff(5 downto 0) when shiftedOut='0' else CONV_STD_LOGIC_VECTOR(55,6) ;
----------------Synchro barrier, entering cycle 2----------------
RightShifterComponent: FPAdder_11_52_uid2_RightShifter -- pipelineDepth=1 maxInDelay=5.3072e-10
port map ( clk => clk,
rst => rst,
R => shiftedFracY,
S => shiftVal_d1,
X => fracY);
----------------Synchro barrier, entering cycle 3----------------
----------------Synchro barrier, entering cycle 4----------------
sticky <= '0' when (shiftedFracY_d1(52 downto 0)=CONV_STD_LOGIC_VECTOR(0,52)) else '1';
---------------- cycle 3----------------
----------------Synchro barrier, entering cycle 4----------------
fracYfar <= "0" & shiftedFracY_d1(107 downto 53);
fracYfarXorOp <= fracYfar xor (55 downto 0 => EffSub_d3);
fracXfar <= "01" & (newX_d3(51 downto 0)) & "00";
cInAddFar <= EffSub_d3 and not sticky;
fracAdder: IntAdder_56_f400_uid12 -- pipelineDepth=2 maxInDelay=1.57344e-09
port map ( clk => clk,
rst => rst,
Cin => cInAddFar,
R => fracAddResult,
X => fracXfar,
Y => fracYfarXorOp);
----------------Synchro barrier, entering cycle 6----------------
fracGRS<= fracAddResult & sticky_d2;
extendedExpInc<= ("00" & expX_d5) + '1';
LZC_component: LZCShifter_57_to_57_counting_64_uid18 -- pipelineDepth=5 maxInDelay=7.37e-10
port map ( clk => clk,
rst => rst,
Count => nZerosNew,
I => fracGRS,
O => shiftedFrac);
----------------Synchro barrier, entering cycle 11----------------
----------------Synchro barrier, entering cycle 12----------------
updatedExp <= extendedExpInc_d6 - ("0000000" & nZerosNew_d1);
eqdiffsign <= '1' when nZerosNew_d1="111111" else '0';
expFrac<= updatedExp & shiftedFrac_d1(55 downto 3);
---------------- cycle 11----------------
stk<= shiftedFrac(1) or shiftedFrac(0);
rnd<= shiftedFrac(2);
grd<= shiftedFrac(3);
lsb<= shiftedFrac(4);
----------------Synchro barrier, entering cycle 12----------------
addToRoundBit<= '0' when (lsb_d1='0' and grd_d1='1' and rnd_d1='0' and stk_d1='0') else '1';
roundingAdder: IntAdder_66_f400_uid20 -- pipelineDepth=2 maxInDelay=1.41172e-09
port map ( clk => clk,
rst => rst,
Cin => addToRoundBit,
R => RoundedExpFrac,
X => expFrac,
Y => "000000000000000000000000000000000000000000000000000000000000000000");
---------------- cycle 14----------------
upExc <= RoundedExpFrac(65 downto 64);
fracR <= RoundedExpFrac(52 downto 1);
expR <= RoundedExpFrac(63 downto 53);
exExpExc <= upExc & excRt_d12;
with (exExpExc) select
excRt2<= "00" when "0000"|"0100"|"1000"|"1100"|"1001"|"1101",
"01" when "0001",
"10" when "0010"|"0110"|"0101",
"11" when others;
excR <= "00" when (eqdiffsign_d2='1' and EffSub_d13='1') else excRt2;
computedR <= excR & signR_d12 & expR & fracR;
R <= computedR;
end architecture;
|
apache-2.0
|
d8a9e7e553fe622402e0e6252101d6e5
| 0.556006 | 3.178881 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/hdl/design_1.vhd
| 1 | 275,844 |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date : Tue Nov 17 20:19:34 2015
--Host : ALI-WORKSTATION running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1R706YB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1R706YB;
architecture STRUCTURE of m00_couplers_imp_1R706YB is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= m00_couplers_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= m00_couplers_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= m00_couplers_to_m00_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= m00_couplers_to_m00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= m00_couplers_to_m00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= m00_couplers_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= m00_couplers_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= m00_couplers_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= m00_couplers_to_m00_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= m00_couplers_to_m00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= m00_couplers_to_m00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= m00_couplers_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= m00_couplers_to_m00_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bid(0) <= m00_couplers_to_m00_couplers_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rid(0) <= m00_couplers_to_m00_couplers_RID(0);
S_AXI_rlast(0) <= m00_couplers_to_m00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_m00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_m00_couplers_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_m00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_m00_couplers_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_m00_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_m00_couplers_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_m00_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_m00_couplers_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BID(0) <= M_AXI_bid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RID(0) <= M_AXI_rid(0);
m00_couplers_to_m00_couplers_RLAST(0) <= M_AXI_rlast(0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WLAST(0) <= S_AXI_wlast(0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_8RVYHO is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_8RVYHO;
architecture STRUCTURE of m00_couplers_imp_8RVYHO is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(8 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1UTB3Y5 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1UTB3Y5;
architecture STRUCTURE of m01_couplers_imp_1UTB3Y5 is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(3 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(3 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_7ANRHB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_7ANRHB;
architecture STRUCTURE of m02_couplers_imp_7ANRHB is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(12 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(12 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(12 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(12 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(12 downto 0) <= S_AXI_araddr(12 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(12 downto 0) <= S_AXI_awaddr(12 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1W07O72 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1W07O72;
architecture STRUCTURE of m03_couplers_imp_1W07O72 is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(4 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(4 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(4 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(4 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(4 downto 0) <= S_AXI_araddr(4 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(4 downto 0) <= S_AXI_awaddr(4 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_local_memory_imp_1K0VQXK is
port (
DLMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_addrstrobe : in STD_LOGIC;
DLMB_be : in STD_LOGIC_VECTOR ( 0 to 3 );
DLMB_ce : out STD_LOGIC;
DLMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_readstrobe : in STD_LOGIC;
DLMB_ready : out STD_LOGIC;
DLMB_ue : out STD_LOGIC;
DLMB_wait : out STD_LOGIC;
DLMB_writedbus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_writestrobe : in STD_LOGIC;
ILMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_addrstrobe : in STD_LOGIC;
ILMB_ce : out STD_LOGIC;
ILMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_readstrobe : in STD_LOGIC;
ILMB_ready : out STD_LOGIC;
ILMB_ue : out STD_LOGIC;
ILMB_wait : out STD_LOGIC;
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end microblaze_0_local_memory_imp_1K0VQXK;
architecture STRUCTURE of microblaze_0_local_memory_imp_1K0VQXK is
component design_1_dlmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component design_1_dlmb_v10_0;
component design_1_ilmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component design_1_ilmb_v10_0;
component design_1_dlmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component design_1_dlmb_bram_if_cntlr_0;
component design_1_ilmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component design_1_ilmb_bram_if_cntlr_0;
component design_1_lmb_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_lmb_bram_0;
signal GND_1 : STD_LOGIC;
signal SYS_Rst_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_dlmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_CE : STD_LOGIC;
signal microblaze_0_dlmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_READY : STD_LOGIC;
signal microblaze_0_dlmb_UE : STD_LOGIC;
signal microblaze_0_dlmb_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_bus_CE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READY : STD_LOGIC;
signal microblaze_0_dlmb_bus_UE : STD_LOGIC;
signal microblaze_0_dlmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_dlmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_CE : STD_LOGIC;
signal microblaze_0_ilmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_READY : STD_LOGIC;
signal microblaze_0_ilmb_UE : STD_LOGIC;
signal microblaze_0_ilmb_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_bus_CE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READY : STD_LOGIC;
signal microblaze_0_ilmb_bus_UE : STD_LOGIC;
signal microblaze_0_ilmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_ilmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_dlmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x0 32 > design_1 microblaze_0_local_memory/lmb_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr : label is "yes";
begin
DLMB_ce <= microblaze_0_dlmb_CE;
DLMB_readdbus(0 to 31) <= microblaze_0_dlmb_READDBUS(0 to 31);
DLMB_ready <= microblaze_0_dlmb_READY;
DLMB_ue <= microblaze_0_dlmb_UE;
DLMB_wait <= microblaze_0_dlmb_WAIT;
ILMB_ce <= microblaze_0_ilmb_CE;
ILMB_readdbus(0 to 31) <= microblaze_0_ilmb_READDBUS(0 to 31);
ILMB_ready <= microblaze_0_ilmb_READY;
ILMB_ue <= microblaze_0_ilmb_UE;
ILMB_wait <= microblaze_0_ilmb_WAIT;
SYS_Rst_1(0) <= SYS_Rst(0);
microblaze_0_Clk <= LMB_Clk;
microblaze_0_dlmb_ABUS(0 to 31) <= DLMB_abus(0 to 31);
microblaze_0_dlmb_ADDRSTROBE <= DLMB_addrstrobe;
microblaze_0_dlmb_BE(0 to 3) <= DLMB_be(0 to 3);
microblaze_0_dlmb_READSTROBE <= DLMB_readstrobe;
microblaze_0_dlmb_WRITEDBUS(0 to 31) <= DLMB_writedbus(0 to 31);
microblaze_0_dlmb_WRITESTROBE <= DLMB_writestrobe;
microblaze_0_ilmb_ABUS(0 to 31) <= ILMB_abus(0 to 31);
microblaze_0_ilmb_ADDRSTROBE <= ILMB_addrstrobe;
microblaze_0_ilmb_READSTROBE <= ILMB_readstrobe;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
dlmb_bram_if_cntlr: component design_1_dlmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_dlmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_dlmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_dlmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_dlmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_dlmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_dlmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_dlmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_dlmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_dlmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_dlmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_dlmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_dlmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_dlmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_dlmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_dlmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_dlmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_dlmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_dlmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_dlmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_dlmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_dlmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_dlmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_dlmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_dlmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_dlmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_dlmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_dlmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_dlmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_dlmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_dlmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_dlmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_dlmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_dlmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_dlmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_dlmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_dlmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_dlmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_dlmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_dlmb_bus_READY,
Sl_UE => microblaze_0_dlmb_bus_UE,
Sl_Wait => microblaze_0_dlmb_bus_WAIT
);
dlmb_v10: component design_1_dlmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_dlmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_dlmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Ready => microblaze_0_dlmb_READY,
LMB_Rst => NLW_dlmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_dlmb_UE,
LMB_Wait => microblaze_0_dlmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_dlmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_dlmb_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_dlmb_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_dlmb_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_dlmb_READSTROBE,
M_WriteStrobe => microblaze_0_dlmb_WRITESTROBE,
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_dlmb_bus_READY,
Sl_UE(0) => microblaze_0_dlmb_bus_UE,
Sl_Wait(0) => microblaze_0_dlmb_bus_WAIT
);
ilmb_bram_if_cntlr: component design_1_ilmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_ilmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_ilmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_ilmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_ilmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_ilmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_ilmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_ilmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_ilmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_ilmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_ilmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_ilmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_ilmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_ilmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_ilmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_ilmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_ilmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_ilmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_ilmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_ilmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_ilmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_ilmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_ilmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_ilmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_ilmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_ilmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_ilmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_ilmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_ilmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_ilmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_ilmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_ilmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_ilmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_ilmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_ilmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_ilmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_ilmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_ilmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_ilmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_ilmb_bus_READY,
Sl_UE => microblaze_0_ilmb_bus_UE,
Sl_Wait => microblaze_0_ilmb_bus_WAIT
);
ilmb_v10: component design_1_ilmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_ilmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_ilmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Ready => microblaze_0_ilmb_READY,
LMB_Rst => NLW_ilmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ilmb_UE,
LMB_Wait => microblaze_0_ilmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ilmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ilmb_ADDRSTROBE,
M_BE(0) => GND_1,
M_BE(1) => GND_1,
M_BE(2) => GND_1,
M_BE(3) => GND_1,
M_DBus(0) => GND_1,
M_DBus(1) => GND_1,
M_DBus(2) => GND_1,
M_DBus(3) => GND_1,
M_DBus(4) => GND_1,
M_DBus(5) => GND_1,
M_DBus(6) => GND_1,
M_DBus(7) => GND_1,
M_DBus(8) => GND_1,
M_DBus(9) => GND_1,
M_DBus(10) => GND_1,
M_DBus(11) => GND_1,
M_DBus(12) => GND_1,
M_DBus(13) => GND_1,
M_DBus(14) => GND_1,
M_DBus(15) => GND_1,
M_DBus(16) => GND_1,
M_DBus(17) => GND_1,
M_DBus(18) => GND_1,
M_DBus(19) => GND_1,
M_DBus(20) => GND_1,
M_DBus(21) => GND_1,
M_DBus(22) => GND_1,
M_DBus(23) => GND_1,
M_DBus(24) => GND_1,
M_DBus(25) => GND_1,
M_DBus(26) => GND_1,
M_DBus(27) => GND_1,
M_DBus(28) => GND_1,
M_DBus(29) => GND_1,
M_DBus(30) => GND_1,
M_DBus(31) => GND_1,
M_ReadStrobe => microblaze_0_ilmb_READSTROBE,
M_WriteStrobe => GND_1,
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_ilmb_bus_READY,
Sl_UE(0) => microblaze_0_ilmb_bus_UE,
Sl_Wait(0) => microblaze_0_ilmb_bus_WAIT
);
lmb_bram: component design_1_lmb_bram_0
port map (
addra(31) => microblaze_0_dlmb_cntlr_ADDR(0),
addra(30) => microblaze_0_dlmb_cntlr_ADDR(1),
addra(29) => microblaze_0_dlmb_cntlr_ADDR(2),
addra(28) => microblaze_0_dlmb_cntlr_ADDR(3),
addra(27) => microblaze_0_dlmb_cntlr_ADDR(4),
addra(26) => microblaze_0_dlmb_cntlr_ADDR(5),
addra(25) => microblaze_0_dlmb_cntlr_ADDR(6),
addra(24) => microblaze_0_dlmb_cntlr_ADDR(7),
addra(23) => microblaze_0_dlmb_cntlr_ADDR(8),
addra(22) => microblaze_0_dlmb_cntlr_ADDR(9),
addra(21) => microblaze_0_dlmb_cntlr_ADDR(10),
addra(20) => microblaze_0_dlmb_cntlr_ADDR(11),
addra(19) => microblaze_0_dlmb_cntlr_ADDR(12),
addra(18) => microblaze_0_dlmb_cntlr_ADDR(13),
addra(17) => microblaze_0_dlmb_cntlr_ADDR(14),
addra(16) => microblaze_0_dlmb_cntlr_ADDR(15),
addra(15) => microblaze_0_dlmb_cntlr_ADDR(16),
addra(14) => microblaze_0_dlmb_cntlr_ADDR(17),
addra(13) => microblaze_0_dlmb_cntlr_ADDR(18),
addra(12) => microblaze_0_dlmb_cntlr_ADDR(19),
addra(11) => microblaze_0_dlmb_cntlr_ADDR(20),
addra(10) => microblaze_0_dlmb_cntlr_ADDR(21),
addra(9) => microblaze_0_dlmb_cntlr_ADDR(22),
addra(8) => microblaze_0_dlmb_cntlr_ADDR(23),
addra(7) => microblaze_0_dlmb_cntlr_ADDR(24),
addra(6) => microblaze_0_dlmb_cntlr_ADDR(25),
addra(5) => microblaze_0_dlmb_cntlr_ADDR(26),
addra(4) => microblaze_0_dlmb_cntlr_ADDR(27),
addra(3) => microblaze_0_dlmb_cntlr_ADDR(28),
addra(2) => microblaze_0_dlmb_cntlr_ADDR(29),
addra(1) => microblaze_0_dlmb_cntlr_ADDR(30),
addra(0) => microblaze_0_dlmb_cntlr_ADDR(31),
addrb(31) => microblaze_0_ilmb_cntlr_ADDR(0),
addrb(30) => microblaze_0_ilmb_cntlr_ADDR(1),
addrb(29) => microblaze_0_ilmb_cntlr_ADDR(2),
addrb(28) => microblaze_0_ilmb_cntlr_ADDR(3),
addrb(27) => microblaze_0_ilmb_cntlr_ADDR(4),
addrb(26) => microblaze_0_ilmb_cntlr_ADDR(5),
addrb(25) => microblaze_0_ilmb_cntlr_ADDR(6),
addrb(24) => microblaze_0_ilmb_cntlr_ADDR(7),
addrb(23) => microblaze_0_ilmb_cntlr_ADDR(8),
addrb(22) => microblaze_0_ilmb_cntlr_ADDR(9),
addrb(21) => microblaze_0_ilmb_cntlr_ADDR(10),
addrb(20) => microblaze_0_ilmb_cntlr_ADDR(11),
addrb(19) => microblaze_0_ilmb_cntlr_ADDR(12),
addrb(18) => microblaze_0_ilmb_cntlr_ADDR(13),
addrb(17) => microblaze_0_ilmb_cntlr_ADDR(14),
addrb(16) => microblaze_0_ilmb_cntlr_ADDR(15),
addrb(15) => microblaze_0_ilmb_cntlr_ADDR(16),
addrb(14) => microblaze_0_ilmb_cntlr_ADDR(17),
addrb(13) => microblaze_0_ilmb_cntlr_ADDR(18),
addrb(12) => microblaze_0_ilmb_cntlr_ADDR(19),
addrb(11) => microblaze_0_ilmb_cntlr_ADDR(20),
addrb(10) => microblaze_0_ilmb_cntlr_ADDR(21),
addrb(9) => microblaze_0_ilmb_cntlr_ADDR(22),
addrb(8) => microblaze_0_ilmb_cntlr_ADDR(23),
addrb(7) => microblaze_0_ilmb_cntlr_ADDR(24),
addrb(6) => microblaze_0_ilmb_cntlr_ADDR(25),
addrb(5) => microblaze_0_ilmb_cntlr_ADDR(26),
addrb(4) => microblaze_0_ilmb_cntlr_ADDR(27),
addrb(3) => microblaze_0_ilmb_cntlr_ADDR(28),
addrb(2) => microblaze_0_ilmb_cntlr_ADDR(29),
addrb(1) => microblaze_0_ilmb_cntlr_ADDR(30),
addrb(0) => microblaze_0_ilmb_cntlr_ADDR(31),
clka => microblaze_0_dlmb_cntlr_CLK,
clkb => microblaze_0_ilmb_cntlr_CLK,
dina(31) => microblaze_0_dlmb_cntlr_DIN(0),
dina(30) => microblaze_0_dlmb_cntlr_DIN(1),
dina(29) => microblaze_0_dlmb_cntlr_DIN(2),
dina(28) => microblaze_0_dlmb_cntlr_DIN(3),
dina(27) => microblaze_0_dlmb_cntlr_DIN(4),
dina(26) => microblaze_0_dlmb_cntlr_DIN(5),
dina(25) => microblaze_0_dlmb_cntlr_DIN(6),
dina(24) => microblaze_0_dlmb_cntlr_DIN(7),
dina(23) => microblaze_0_dlmb_cntlr_DIN(8),
dina(22) => microblaze_0_dlmb_cntlr_DIN(9),
dina(21) => microblaze_0_dlmb_cntlr_DIN(10),
dina(20) => microblaze_0_dlmb_cntlr_DIN(11),
dina(19) => microblaze_0_dlmb_cntlr_DIN(12),
dina(18) => microblaze_0_dlmb_cntlr_DIN(13),
dina(17) => microblaze_0_dlmb_cntlr_DIN(14),
dina(16) => microblaze_0_dlmb_cntlr_DIN(15),
dina(15) => microblaze_0_dlmb_cntlr_DIN(16),
dina(14) => microblaze_0_dlmb_cntlr_DIN(17),
dina(13) => microblaze_0_dlmb_cntlr_DIN(18),
dina(12) => microblaze_0_dlmb_cntlr_DIN(19),
dina(11) => microblaze_0_dlmb_cntlr_DIN(20),
dina(10) => microblaze_0_dlmb_cntlr_DIN(21),
dina(9) => microblaze_0_dlmb_cntlr_DIN(22),
dina(8) => microblaze_0_dlmb_cntlr_DIN(23),
dina(7) => microblaze_0_dlmb_cntlr_DIN(24),
dina(6) => microblaze_0_dlmb_cntlr_DIN(25),
dina(5) => microblaze_0_dlmb_cntlr_DIN(26),
dina(4) => microblaze_0_dlmb_cntlr_DIN(27),
dina(3) => microblaze_0_dlmb_cntlr_DIN(28),
dina(2) => microblaze_0_dlmb_cntlr_DIN(29),
dina(1) => microblaze_0_dlmb_cntlr_DIN(30),
dina(0) => microblaze_0_dlmb_cntlr_DIN(31),
dinb(31) => microblaze_0_ilmb_cntlr_DIN(0),
dinb(30) => microblaze_0_ilmb_cntlr_DIN(1),
dinb(29) => microblaze_0_ilmb_cntlr_DIN(2),
dinb(28) => microblaze_0_ilmb_cntlr_DIN(3),
dinb(27) => microblaze_0_ilmb_cntlr_DIN(4),
dinb(26) => microblaze_0_ilmb_cntlr_DIN(5),
dinb(25) => microblaze_0_ilmb_cntlr_DIN(6),
dinb(24) => microblaze_0_ilmb_cntlr_DIN(7),
dinb(23) => microblaze_0_ilmb_cntlr_DIN(8),
dinb(22) => microblaze_0_ilmb_cntlr_DIN(9),
dinb(21) => microblaze_0_ilmb_cntlr_DIN(10),
dinb(20) => microblaze_0_ilmb_cntlr_DIN(11),
dinb(19) => microblaze_0_ilmb_cntlr_DIN(12),
dinb(18) => microblaze_0_ilmb_cntlr_DIN(13),
dinb(17) => microblaze_0_ilmb_cntlr_DIN(14),
dinb(16) => microblaze_0_ilmb_cntlr_DIN(15),
dinb(15) => microblaze_0_ilmb_cntlr_DIN(16),
dinb(14) => microblaze_0_ilmb_cntlr_DIN(17),
dinb(13) => microblaze_0_ilmb_cntlr_DIN(18),
dinb(12) => microblaze_0_ilmb_cntlr_DIN(19),
dinb(11) => microblaze_0_ilmb_cntlr_DIN(20),
dinb(10) => microblaze_0_ilmb_cntlr_DIN(21),
dinb(9) => microblaze_0_ilmb_cntlr_DIN(22),
dinb(8) => microblaze_0_ilmb_cntlr_DIN(23),
dinb(7) => microblaze_0_ilmb_cntlr_DIN(24),
dinb(6) => microblaze_0_ilmb_cntlr_DIN(25),
dinb(5) => microblaze_0_ilmb_cntlr_DIN(26),
dinb(4) => microblaze_0_ilmb_cntlr_DIN(27),
dinb(3) => microblaze_0_ilmb_cntlr_DIN(28),
dinb(2) => microblaze_0_ilmb_cntlr_DIN(29),
dinb(1) => microblaze_0_ilmb_cntlr_DIN(30),
dinb(0) => microblaze_0_ilmb_cntlr_DIN(31),
douta(31 downto 0) => microblaze_0_dlmb_cntlr_DOUT(31 downto 0),
doutb(31 downto 0) => microblaze_0_ilmb_cntlr_DOUT(31 downto 0),
ena => microblaze_0_dlmb_cntlr_EN,
enb => microblaze_0_ilmb_cntlr_EN,
rsta => microblaze_0_dlmb_cntlr_RST,
rstb => microblaze_0_ilmb_cntlr_RST,
wea(3) => microblaze_0_dlmb_cntlr_WE(0),
wea(2) => microblaze_0_dlmb_cntlr_WE(1),
wea(1) => microblaze_0_dlmb_cntlr_WE(2),
wea(0) => microblaze_0_dlmb_cntlr_WE(3),
web(3) => microblaze_0_ilmb_cntlr_WE(0),
web(2) => microblaze_0_ilmb_cntlr_WE(1),
web(1) => microblaze_0_ilmb_cntlr_WE(2),
web(0) => microblaze_0_ilmb_cntlr_WE(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RZP34U is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_1RZP34U;
architecture STRUCTURE of s00_couplers_imp_1RZP34U is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_7HNO1D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_7HNO1D;
architecture STRUCTURE of s00_couplers_imp_7HNO1D is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= s00_couplers_to_s00_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= s00_couplers_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= s00_couplers_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s00_couplers_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s00_couplers_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= s00_couplers_to_s00_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= s00_couplers_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= s00_couplers_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= s00_couplers_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= s00_couplers_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s00_couplers_to_s00_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bid(0) <= s00_couplers_to_s00_couplers_BID(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rid(0) <= s00_couplers_to_s00_couplers_RID(0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARID(0) <= S_AXI_arid(0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARLOCK(0) <= S_AXI_arlock(0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_s00_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_s00_couplers_AWID(0) <= S_AXI_awid(0);
s00_couplers_to_s00_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_s00_couplers_AWLOCK(0) <= S_AXI_awlock(0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BID(0) <= M_AXI_bid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RID(0) <= M_AXI_rid(0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WLAST(0) <= S_AXI_wlast(0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1W60HW0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s01_couplers_imp_1W60HW0;
architecture STRUCTURE of s01_couplers_imp_1W60HW0 is
signal s01_couplers_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s01_couplers_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s01_couplers_to_s01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s01_couplers_to_s01_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= s01_couplers_to_s01_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= s01_couplers_to_s01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= s01_couplers_to_s01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= s01_couplers_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= s01_couplers_to_s01_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= s01_couplers_to_s01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s01_couplers_to_s01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= s01_couplers_to_s01_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= s01_couplers_to_s01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= s01_couplers_to_s01_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s01_couplers_to_s01_couplers_AWVALID(0);
M_AXI_bready(0) <= s01_couplers_to_s01_couplers_BREADY(0);
M_AXI_rready(0) <= s01_couplers_to_s01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s01_couplers_to_s01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s01_couplers_to_s01_couplers_WVALID(0);
S_AXI_arready(0) <= s01_couplers_to_s01_couplers_ARREADY(0);
S_AXI_awready(0) <= s01_couplers_to_s01_couplers_AWREADY(0);
S_AXI_bid(0) <= s01_couplers_to_s01_couplers_BID(0);
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s01_couplers_to_s01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s01_couplers_to_s01_couplers_RDATA(31 downto 0);
S_AXI_rid(0) <= s01_couplers_to_s01_couplers_RID(0);
S_AXI_rlast(0) <= s01_couplers_to_s01_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s01_couplers_to_s01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s01_couplers_to_s01_couplers_RVALID(0);
S_AXI_wready(0) <= s01_couplers_to_s01_couplers_WREADY(0);
s01_couplers_to_s01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_s01_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s01_couplers_to_s01_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s01_couplers_to_s01_couplers_ARID(0) <= S_AXI_arid(0);
s01_couplers_to_s01_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s01_couplers_to_s01_couplers_ARLOCK(0) <= S_AXI_arlock(0);
s01_couplers_to_s01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_s01_couplers_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s01_couplers_to_s01_couplers_ARREADY(0) <= M_AXI_arready(0);
s01_couplers_to_s01_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s01_couplers_to_s01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWID(0) <= S_AXI_awid(0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWLOCK(0) <= S_AXI_awlock(0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s01_couplers_to_s01_couplers_AWREADY(0) <= M_AXI_awready(0);
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s01_couplers_to_s01_couplers_BID(0) <= M_AXI_bid(0);
s01_couplers_to_s01_couplers_BREADY(0) <= S_AXI_bready(0);
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID(0) <= M_AXI_bvalid(0);
s01_couplers_to_s01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s01_couplers_to_s01_couplers_RID(0) <= M_AXI_rid(0);
s01_couplers_to_s01_couplers_RLAST(0) <= M_AXI_rlast(0);
s01_couplers_to_s01_couplers_RREADY(0) <= S_AXI_rready(0);
s01_couplers_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s01_couplers_to_s01_couplers_RVALID(0) <= M_AXI_rvalid(0);
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST(0) <= S_AXI_wlast(0);
s01_couplers_to_s01_couplers_WREADY(0) <= M_AXI_wready(0);
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_1_axi_mem_intercon_0;
architecture STRUCTURE of design_1_axi_mem_intercon_0 is
component design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal s01_couplers_to_xbar_RID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_xbar_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_xbar_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_xbar_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0);
M00_AXI_arlock(0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_axi_mem_intercon_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0);
M00_AXI_awlock(0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_axi_mem_intercon_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_axi_mem_intercon_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_axi_mem_intercon_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wlast(0) <= m00_couplers_to_axi_mem_intercon_WLAST(0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_axi_mem_intercon_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= axi_mem_intercon_to_s00_couplers_AWREADY(0);
S00_AXI_bid(0) <= axi_mem_intercon_to_s00_couplers_BID(0);
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= axi_mem_intercon_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(0) <= axi_mem_intercon_to_s00_couplers_RID(0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= axi_mem_intercon_to_s00_couplers_WREADY(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_arready(0) <= axi_mem_intercon_to_s01_couplers_ARREADY(0);
S01_AXI_awready(0) <= axi_mem_intercon_to_s01_couplers_AWREADY(0);
S01_AXI_bid(0) <= axi_mem_intercon_to_s01_couplers_BID(0);
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid(0) <= axi_mem_intercon_to_s01_couplers_BVALID(0);
S01_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rid(0) <= axi_mem_intercon_to_s01_couplers_RID(0);
S01_AXI_rlast(0) <= axi_mem_intercon_to_s01_couplers_RLAST(0);
S01_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid(0) <= axi_mem_intercon_to_s01_couplers_RVALID(0);
S01_AXI_wready(0) <= axi_mem_intercon_to_s01_couplers_WREADY(0);
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARID(0) <= S00_AXI_arid(0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARLOCK(0) <= S00_AXI_arlock(0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWID(0) <= S00_AXI_awid(0);
axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_AWLOCK(0) <= S00_AXI_awlock(0);
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
axi_mem_intercon_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST(0) <= S00_AXI_wlast(0);
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0) <= S01_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0) <= S01_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARID(0) <= S01_AXI_arid(0);
axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0) <= S01_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_ARLOCK(0) <= S01_AXI_arlock(0);
axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0) <= S01_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0) <= S01_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARVALID(0) <= S01_AXI_arvalid(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWID(0) <= S01_AXI_awid(0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWLOCK(0) <= S01_AXI_awlock(0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWQOS(3 downto 0) <= S01_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID(0) <= S01_AXI_awvalid(0);
axi_mem_intercon_to_s01_couplers_BREADY(0) <= S01_AXI_bready(0);
axi_mem_intercon_to_s01_couplers_RREADY(0) <= S01_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST(0) <= S01_AXI_wlast(0);
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID(0) <= S01_AXI_wvalid(0);
m00_couplers_to_axi_mem_intercon_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_axi_mem_intercon_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_axi_mem_intercon_BID(0) <= M00_AXI_bid(0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(0) <= M00_AXI_rid(0);
m00_couplers_to_axi_mem_intercon_RLAST(0) <= M00_AXI_rlast(0);
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_axi_mem_intercon_WREADY(0) <= M00_AXI_wready(0);
m00_couplers: entity work.m00_couplers_imp_1R706YB
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0),
M_AXI_arlock(0) => m00_couplers_to_axi_mem_intercon_ARLOCK(0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_axi_mem_intercon_ARREADY(0),
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => m00_couplers_to_axi_mem_intercon_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0),
M_AXI_awlock(0) => m00_couplers_to_axi_mem_intercon_AWLOCK(0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_axi_mem_intercon_AWREADY(0),
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => m00_couplers_to_axi_mem_intercon_AWVALID(0),
M_AXI_bid(0) => m00_couplers_to_axi_mem_intercon_BID(0),
M_AXI_bready(0) => m00_couplers_to_axi_mem_intercon_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_axi_mem_intercon_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(0) => m00_couplers_to_axi_mem_intercon_RID(0),
M_AXI_rlast(0) => m00_couplers_to_axi_mem_intercon_RLAST(0),
M_AXI_rready(0) => m00_couplers_to_axi_mem_intercon_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_axi_mem_intercon_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wlast(0) => m00_couplers_to_axi_mem_intercon_WLAST(0),
M_AXI_wready(0) => m00_couplers_to_axi_mem_intercon_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_axi_mem_intercon_WVALID(0),
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast(0) => xbar_to_m00_couplers_RLAST(0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_7HNO1D
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(0) => s00_couplers_to_xbar_ARID(0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(0) => s00_couplers_to_xbar_AWID(0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bid(0) => s00_couplers_to_xbar_BID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rid(0) => s00_couplers_to_xbar_RID(0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s00_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => axi_mem_intercon_to_s00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_mem_intercon_to_s00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => axi_mem_intercon_to_s00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_mem_intercon_to_s00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s00_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s00_couplers_AWVALID(0),
S_AXI_bid(0) => axi_mem_intercon_to_s00_couplers_BID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => axi_mem_intercon_to_s00_couplers_RID(0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s00_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s00_couplers_WVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1W60HW0
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s01_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arid(0) => s01_couplers_to_xbar_ARID(0),
M_AXI_arlen(7 downto 0) => s01_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s01_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s01_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready(0) => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arsize(2 downto 0) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s01_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awid(0) => s01_couplers_to_xbar_AWID(0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready(0) => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s01_couplers_to_xbar_AWVALID(0),
M_AXI_bid(0) => s01_couplers_to_xbar_BID(1),
M_AXI_bready(0) => s01_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid(0) => s01_couplers_to_xbar_BVALID(1),
M_AXI_rdata(31 downto 0) => s01_couplers_to_xbar_RDATA(63 downto 32),
M_AXI_rid(0) => s01_couplers_to_xbar_RID(1),
M_AXI_rlast(0) => s01_couplers_to_xbar_RLAST(1),
M_AXI_rready(0) => s01_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid(0) => s01_couplers_to_xbar_RVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s01_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s01_couplers_to_xbar_WVALID(0),
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => axi_mem_intercon_to_s01_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => axi_mem_intercon_to_s01_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s01_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s01_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => axi_mem_intercon_to_s01_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => axi_mem_intercon_to_s01_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWQOS(3 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s01_couplers_AWVALID(0),
S_AXI_bid(0) => axi_mem_intercon_to_s01_couplers_BID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s01_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => axi_mem_intercon_to_s01_couplers_RID(0),
S_AXI_rlast(0) => axi_mem_intercon_to_s01_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s01_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s01_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s01_couplers_WVALID(0)
);
xbar: component design_1_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_xbar_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arregion(3 downto 0) => NLW_xbar_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_xbar_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awregion(3 downto 0) => NLW_xbar_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST(0),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => s01_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1) => s01_couplers_to_xbar_ARID(0),
s_axi_arid(0) => s00_couplers_to_xbar_ARID(0),
s_axi_arlen(15 downto 8) => s01_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1) => s01_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 4) => s01_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(1) => s01_couplers_to_xbar_AWID(0),
s_axi_awid(0) => s00_couplers_to_xbar_AWID(0),
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bid(1) => s01_couplers_to_xbar_BID(1),
s_axi_bid(0) => s00_couplers_to_xbar_BID(0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(63 downto 32) => s01_couplers_to_xbar_RDATA(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(1) => s01_couplers_to_xbar_RID(1),
s_axi_rid(0) => s00_couplers_to_xbar_RID(0),
s_axi_rlast(1) => s01_couplers_to_xbar_RLAST(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => s01_couplers_to_xbar_RREADY(0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST(0),
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST(0),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID(0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 4 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_1_microblaze_0_axi_periph_0;
architecture STRUCTURE of design_1_microblaze_0_axi_periph_0 is
component design_1_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_1_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_ACLK_net : STD_LOGIC;
signal microblaze_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid <= m00_couplers_to_microblaze_0_axi_periph_ARVALID;
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid <= m00_couplers_to_microblaze_0_axi_periph_AWVALID;
M00_AXI_bready <= m00_couplers_to_microblaze_0_axi_periph_BREADY;
M00_AXI_rready <= m00_couplers_to_microblaze_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_microblaze_0_axi_periph_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_ARADDR(3 downto 0);
M01_AXI_arvalid <= m01_couplers_to_microblaze_0_axi_periph_ARVALID;
M01_AXI_awaddr(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_AWADDR(3 downto 0);
M01_AXI_awvalid <= m01_couplers_to_microblaze_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_microblaze_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_microblaze_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_microblaze_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(12 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_ARADDR(12 downto 0);
M02_AXI_arvalid <= m02_couplers_to_microblaze_0_axi_periph_ARVALID;
M02_AXI_awaddr(12 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_AWADDR(12 downto 0);
M02_AXI_awvalid <= m02_couplers_to_microblaze_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_microblaze_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_microblaze_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_microblaze_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(4 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_ARADDR(4 downto 0);
M03_AXI_arvalid <= m03_couplers_to_microblaze_0_axi_periph_ARVALID;
M03_AXI_awaddr(4 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_AWADDR(4 downto 0);
M03_AXI_awvalid <= m03_couplers_to_microblaze_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_microblaze_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_microblaze_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_microblaze_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= microblaze_0_axi_periph_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= microblaze_0_axi_periph_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= microblaze_0_axi_periph_to_s00_couplers_WREADY(0);
m00_couplers_to_microblaze_0_axi_periph_ARREADY <= M00_AXI_arready;
m00_couplers_to_microblaze_0_axi_periph_AWREADY <= M00_AXI_awready;
m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_BVALID <= M00_AXI_bvalid;
m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RVALID <= M00_AXI_rvalid;
m00_couplers_to_microblaze_0_axi_periph_WREADY <= M00_AXI_wready;
m01_couplers_to_microblaze_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_microblaze_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_microblaze_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_microblaze_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_microblaze_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_microblaze_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_microblaze_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_microblaze_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_microblaze_0_axi_periph_WREADY <= M03_AXI_wready;
microblaze_0_axi_periph_ACLK_net <= ACLK;
microblaze_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
microblaze_0_axi_periph_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
microblaze_0_axi_periph_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers: entity work.m00_couplers_imp_8RVYHO
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_microblaze_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m00_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m00_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m00_couplers_to_microblaze_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m00_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m00_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m00_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m00_couplers_ARADDR(8 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(8 downto 0) => xbar_to_m00_couplers_AWADDR(8 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1UTB3Y5
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arready => m01_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awready => m01_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m01_couplers_ARADDR(35 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(3 downto 0) => xbar_to_m01_couplers_AWADDR(35 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_7ANRHB
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(12 downto 0) => m02_couplers_to_microblaze_0_axi_periph_ARADDR(12 downto 0),
M_AXI_arready => m02_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(12 downto 0) => m02_couplers_to_microblaze_0_axi_periph_AWADDR(12 downto 0),
M_AXI_awready => m02_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(12 downto 0) => xbar_to_m02_couplers_ARADDR(76 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(12 downto 0) => xbar_to_m02_couplers_AWADDR(76 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1W07O72
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(4 downto 0) => m03_couplers_to_microblaze_0_axi_periph_ARADDR(4 downto 0),
M_AXI_arready => m03_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(4 downto 0) => m03_couplers_to_microblaze_0_axi_periph_AWADDR(4 downto 0),
M_AXI_awready => m03_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(4 downto 0) => xbar_to_m03_couplers_ARADDR(100 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(4 downto 0) => xbar_to_m03_couplers_AWADDR(100 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
s00_couplers: entity work.s00_couplers_imp_1RZP34U
port map (
M_ACLK => microblaze_0_axi_periph_ACLK_net,
M_ARESETN(0) => microblaze_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => microblaze_0_axi_periph_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => microblaze_0_axi_periph_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => microblaze_0_axi_periph_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => microblaze_0_axi_periph_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => microblaze_0_axi_periph_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => microblaze_0_axi_periph_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => microblaze_0_axi_periph_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => microblaze_0_axi_periph_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => microblaze_0_axi_periph_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => microblaze_0_axi_periph_to_s00_couplers_WVALID(0)
);
xbar: component design_1_xbar_1
port map (
aclk => microblaze_0_axi_periph_ACLK_net,
aresetn => microblaze_0_axi_periph_ARESETN_net(0),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(11 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(11 downto 0),
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(11 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(11 downto 0),
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1 is
port (
cellular_ram_addr : out STD_LOGIC_VECTOR ( 22 downto 0 );
cellular_ram_adv_ldn : out STD_LOGIC;
cellular_ram_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
cellular_ram_ce_n : out STD_LOGIC;
cellular_ram_cre : out STD_LOGIC;
cellular_ram_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
cellular_ram_oen : out STD_LOGIC;
cellular_ram_wait : in STD_LOGIC;
cellular_ram_wen : out STD_LOGIC;
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
eth_rmii_crs_dv : in STD_LOGIC;
eth_rmii_rx_er : in STD_LOGIC;
eth_rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
eth_rmii_tx_en : out STD_LOGIC;
eth_rmii_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=29,numReposBlks=18,numNonXlnxBlks=0,numHierBlks=11,maxHierDepth=1,da_axi4_cnt=4,da_board_cnt=8,da_mb_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
end design_1;
architecture STRUCTURE of design_1 is
component design_1_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_AWLOCK : out STD_LOGIC;
M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWVALID : out STD_LOGIC;
M_AXI_IC_AWREADY : in STD_LOGIC;
M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_WLAST : out STD_LOGIC;
M_AXI_IC_WVALID : out STD_LOGIC;
M_AXI_IC_WREADY : in STD_LOGIC;
M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_BVALID : in STD_LOGIC;
M_AXI_IC_BREADY : out STD_LOGIC;
M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_ARLOCK : out STD_LOGIC;
M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARVALID : out STD_LOGIC;
M_AXI_IC_ARREADY : in STD_LOGIC;
M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_RLAST : in STD_LOGIC;
M_AXI_IC_RVALID : in STD_LOGIC;
M_AXI_IC_RREADY : out STD_LOGIC;
M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_AWLOCK : out STD_LOGIC;
M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWVALID : out STD_LOGIC;
M_AXI_DC_AWREADY : in STD_LOGIC;
M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_WLAST : out STD_LOGIC;
M_AXI_DC_WVALID : out STD_LOGIC;
M_AXI_DC_WREADY : in STD_LOGIC;
M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_BVALID : in STD_LOGIC;
M_AXI_DC_BREADY : out STD_LOGIC;
M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_ARLOCK : out STD_LOGIC;
M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARVALID : out STD_LOGIC;
M_AXI_DC_ARREADY : in STD_LOGIC;
M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_RLAST : in STD_LOGIC;
M_AXI_DC_RVALID : in STD_LOGIC;
M_AXI_DC_RREADY : out STD_LOGIC
);
end component design_1_microblaze_0_0;
component design_1_microblaze_0_axi_intc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 1 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_microblaze_0_axi_intc_0;
component design_1_microblaze_0_xlconcat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_1_microblaze_0_xlconcat_0;
component design_1_mdm_1_0 is
port (
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC
);
end component design_1_mdm_1_0;
component design_1_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
end component design_1_clk_wiz_1_0;
component design_1_rst_clk_wiz_1_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_rst_clk_wiz_1_100M_0;
component design_1_axi_emc_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rdclk : in STD_LOGIC;
s_axi_mem_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_mem_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_awlock : in STD_LOGIC;
s_axi_mem_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_mem_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_awvalid : in STD_LOGIC;
s_axi_mem_awready : out STD_LOGIC;
s_axi_mem_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_mem_wlast : in STD_LOGIC;
s_axi_mem_wvalid : in STD_LOGIC;
s_axi_mem_wready : out STD_LOGIC;
s_axi_mem_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_bvalid : out STD_LOGIC;
s_axi_mem_bready : in STD_LOGIC;
s_axi_mem_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_mem_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_arlock : in STD_LOGIC;
s_axi_mem_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_mem_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_mem_arvalid : in STD_LOGIC;
s_axi_mem_arready : out STD_LOGIC;
s_axi_mem_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_mem_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_mem_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_mem_rlast : out STD_LOGIC;
s_axi_mem_rvalid : out STD_LOGIC;
s_axi_mem_rready : in STD_LOGIC;
mem_dq_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
mem_dq_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
mem_dq_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
mem_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
mem_ce : out STD_LOGIC_VECTOR ( 0 to 0 );
mem_cen : out STD_LOGIC_VECTOR ( 0 to 0 );
mem_oen : out STD_LOGIC_VECTOR ( 0 to 0 );
mem_wen : out STD_LOGIC;
mem_ben : out STD_LOGIC_VECTOR ( 1 downto 0 );
mem_qwen : out STD_LOGIC_VECTOR ( 1 downto 0 );
mem_rpn : out STD_LOGIC;
mem_adv_ldn : out STD_LOGIC;
mem_lbon : out STD_LOGIC;
mem_cken : out STD_LOGIC;
mem_rnw : out STD_LOGIC;
mem_cre : out STD_LOGIC;
mem_wait : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1_axi_emc_0_0;
component design_1_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
end component design_1_axi_uartlite_0_0;
component design_1_mii_to_rmii_0_0 is
port (
rst_n : in STD_LOGIC;
ref_clk : in STD_LOGIC;
mac2rmii_tx_en : in STD_LOGIC;
mac2rmii_txd : in STD_LOGIC_VECTOR ( 3 downto 0 );
mac2rmii_tx_er : in STD_LOGIC;
rmii2mac_tx_clk : out STD_LOGIC;
rmii2mac_rx_clk : out STD_LOGIC;
rmii2mac_col : out STD_LOGIC;
rmii2mac_crs : out STD_LOGIC;
rmii2mac_rx_dv : out STD_LOGIC;
rmii2mac_rx_er : out STD_LOGIC;
rmii2mac_rxd : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy2rmii_crs_dv : in STD_LOGIC;
phy2rmii_rx_er : in STD_LOGIC;
phy2rmii_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
rmii2phy_txd : out STD_LOGIC_VECTOR ( 1 downto 0 );
rmii2phy_tx_en : out STD_LOGIC
);
end component design_1_mii_to_rmii_0_0;
component design_1_axi_ethernetlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
end component design_1_axi_ethernetlite_0_0;
component design_1_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component design_1_axi_timer_0_0;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal axi_emc_0_EMC_INTF_ADDR : STD_LOGIC_VECTOR ( 22 downto 0 );
signal axi_emc_0_EMC_INTF_ADV_LDN : STD_LOGIC;
signal axi_emc_0_EMC_INTF_BEN : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_emc_0_EMC_INTF_CE_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_emc_0_EMC_INTF_CRE : STD_LOGIC;
signal axi_emc_0_EMC_INTF_DQ_I : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_emc_0_EMC_INTF_DQ_O : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_emc_0_EMC_INTF_DQ_T : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_emc_0_EMC_INTF_OEN : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_emc_0_EMC_INTF_WAIT : STD_LOGIC;
signal axi_emc_0_EMC_INTF_WEN : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDC : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_I : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_O : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_T : STD_LOGIC;
signal axi_ethernetlite_0_MII_COL : STD_LOGIC;
signal axi_ethernetlite_0_MII_CRS : STD_LOGIC;
signal axi_ethernetlite_0_MII_RXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_RX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_DV : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_ER : STD_LOGIC;
signal axi_ethernetlite_0_MII_TXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_TX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_TX_EN : STD_LOGIC;
signal axi_ethernetlite_0_ip2intc_irpt : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_timer_0_interrupt : STD_LOGIC;
signal axi_uartlite_0_UART_RxD : STD_LOGIC;
signal axi_uartlite_0_UART_TxD : STD_LOGIC;
signal clk_wiz_1_clk_out2 : STD_LOGIC;
signal clk_wiz_1_locked : STD_LOGIC;
signal mdm_1_debug_sys_rst : STD_LOGIC;
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_AWLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_BREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_WLAST : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_DC_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_WVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_IC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_IC_AWLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_IC_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_AWVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_BREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_WLAST : STD_LOGIC;
signal microblaze_0_M_AXI_IC_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_M_AXI_IC_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_WVALID : STD_LOGIC;
signal microblaze_0_axi_dp_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_ARVALID : STD_LOGIC;
signal microblaze_0_axi_dp_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_AWVALID : STD_LOGIC;
signal microblaze_0_axi_dp_BREADY : STD_LOGIC;
signal microblaze_0_axi_dp_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_RREADY : STD_LOGIC;
signal microblaze_0_axi_dp_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_dp_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 4 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal microblaze_0_debug_CAPTURE : STD_LOGIC;
signal microblaze_0_debug_CLK : STD_LOGIC;
signal microblaze_0_debug_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal microblaze_0_debug_RST : STD_LOGIC;
signal microblaze_0_debug_SHIFT : STD_LOGIC;
signal microblaze_0_debug_TDI : STD_LOGIC;
signal microblaze_0_debug_TDO : STD_LOGIC;
signal microblaze_0_debug_UPDATE : STD_LOGIC;
signal microblaze_0_dlmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_1_CE : STD_LOGIC;
signal microblaze_0_dlmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_READY : STD_LOGIC;
signal microblaze_0_dlmb_1_UE : STD_LOGIC;
signal microblaze_0_dlmb_1_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_CE : STD_LOGIC;
signal microblaze_0_ilmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_READY : STD_LOGIC;
signal microblaze_0_ilmb_1_UE : STD_LOGIC;
signal microblaze_0_ilmb_1_WAIT : STD_LOGIC;
signal microblaze_0_intc_axi_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal microblaze_0_intc_axi_ARREADY : STD_LOGIC;
signal microblaze_0_intc_axi_ARVALID : STD_LOGIC;
signal microblaze_0_intc_axi_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal microblaze_0_intc_axi_AWREADY : STD_LOGIC;
signal microblaze_0_intc_axi_AWVALID : STD_LOGIC;
signal microblaze_0_intc_axi_BREADY : STD_LOGIC;
signal microblaze_0_intc_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_BVALID : STD_LOGIC;
signal microblaze_0_intc_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_RREADY : STD_LOGIC;
signal microblaze_0_intc_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_RVALID : STD_LOGIC;
signal microblaze_0_intc_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_WREADY : STD_LOGIC;
signal microblaze_0_intc_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_intc_axi_WVALID : STD_LOGIC;
signal microblaze_0_interrupt_ACK : STD_LOGIC_VECTOR ( 0 to 1 );
signal microblaze_0_interrupt_ADDRESS : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_interrupt_INTERRUPT : STD_LOGIC;
signal microblaze_0_intr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mii_to_rmii_0_RMII_PHY_M_CRS_DV : STD_LOGIC;
signal mii_to_rmii_0_RMII_PHY_M_RXD : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mii_to_rmii_0_RMII_PHY_M_RX_ER : STD_LOGIC;
signal mii_to_rmii_0_RMII_PHY_M_TXD : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mii_to_rmii_0_RMII_PHY_M_TX_EN : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rst_clk_wiz_1_100M_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_mb_reset : STD_LOGIC;
signal rst_clk_wiz_1_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_clock_1 : STD_LOGIC;
signal NLW_axi_emc_0_mem_cken_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_lbon_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_rnw_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_rpn_UNCONNECTED : STD_LOGIC;
signal NLW_axi_emc_0_mem_a_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 23 );
signal NLW_axi_emc_0_mem_ce_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_emc_0_mem_qwen_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_axi_ethernetlite_0_phy_rst_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_uartlite_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > design_1 microblaze_0_local_memory/dlmb_bram_if_cntlr";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
begin
axi_emc_0_EMC_INTF_DQ_I(15 downto 0) <= cellular_ram_dq_i(15 downto 0);
axi_emc_0_EMC_INTF_WAIT <= cellular_ram_wait;
axi_ethernetlite_0_MDIO_MDIO_I <= eth_mdio_mdc_mdio_i;
axi_uartlite_0_UART_RxD <= usb_uart_rxd;
cellular_ram_addr(22 downto 0) <= axi_emc_0_EMC_INTF_ADDR(22 downto 0);
cellular_ram_adv_ldn <= axi_emc_0_EMC_INTF_ADV_LDN;
cellular_ram_ben(1 downto 0) <= axi_emc_0_EMC_INTF_BEN(1 downto 0);
cellular_ram_ce_n <= axi_emc_0_EMC_INTF_CE_N(0);
cellular_ram_cre <= axi_emc_0_EMC_INTF_CRE;
cellular_ram_dq_o(15 downto 0) <= axi_emc_0_EMC_INTF_DQ_O(15 downto 0);
cellular_ram_dq_t(15 downto 0) <= axi_emc_0_EMC_INTF_DQ_T(15 downto 0);
cellular_ram_oen <= axi_emc_0_EMC_INTF_OEN(0);
cellular_ram_wen <= axi_emc_0_EMC_INTF_WEN;
eth_mdio_mdc_mdc <= axi_ethernetlite_0_MDIO_MDC;
eth_mdio_mdc_mdio_o <= axi_ethernetlite_0_MDIO_MDIO_O;
eth_mdio_mdc_mdio_t <= axi_ethernetlite_0_MDIO_MDIO_T;
eth_ref_clk <= clk_wiz_1_clk_out2;
eth_rmii_tx_en <= mii_to_rmii_0_RMII_PHY_M_TX_EN;
eth_rmii_txd(1 downto 0) <= mii_to_rmii_0_RMII_PHY_M_TXD(1 downto 0);
mii_to_rmii_0_RMII_PHY_M_CRS_DV <= eth_rmii_crs_dv;
mii_to_rmii_0_RMII_PHY_M_RXD(1 downto 0) <= eth_rmii_rxd(1 downto 0);
mii_to_rmii_0_RMII_PHY_M_RX_ER <= eth_rmii_rx_er;
reset_1 <= reset;
sys_clock_1 <= sys_clock;
usb_uart_txd <= axi_uartlite_0_UART_TxD;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_emc_0: component design_1_axi_emc_0_0
port map (
mem_a(31 downto 23) => NLW_axi_emc_0_mem_a_UNCONNECTED(31 downto 23),
mem_a(22 downto 0) => axi_emc_0_EMC_INTF_ADDR(22 downto 0),
mem_adv_ldn => axi_emc_0_EMC_INTF_ADV_LDN,
mem_ben(1 downto 0) => axi_emc_0_EMC_INTF_BEN(1 downto 0),
mem_ce(0) => NLW_axi_emc_0_mem_ce_UNCONNECTED(0),
mem_cen(0) => axi_emc_0_EMC_INTF_CE_N(0),
mem_cken => NLW_axi_emc_0_mem_cken_UNCONNECTED,
mem_cre => axi_emc_0_EMC_INTF_CRE,
mem_dq_i(15 downto 0) => axi_emc_0_EMC_INTF_DQ_I(15 downto 0),
mem_dq_o(15 downto 0) => axi_emc_0_EMC_INTF_DQ_O(15 downto 0),
mem_dq_t(15 downto 0) => axi_emc_0_EMC_INTF_DQ_T(15 downto 0),
mem_lbon => NLW_axi_emc_0_mem_lbon_UNCONNECTED,
mem_oen(0) => axi_emc_0_EMC_INTF_OEN(0),
mem_qwen(1 downto 0) => NLW_axi_emc_0_mem_qwen_UNCONNECTED(1 downto 0),
mem_rnw => NLW_axi_emc_0_mem_rnw_UNCONNECTED,
mem_rpn => NLW_axi_emc_0_mem_rpn_UNCONNECTED,
mem_wait(0) => axi_emc_0_EMC_INTF_WAIT,
mem_wen => axi_emc_0_EMC_INTF_WEN,
rdclk => microblaze_0_Clk,
s_axi_aclk => microblaze_0_Clk,
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_mem_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
s_axi_mem_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
s_axi_mem_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
s_axi_mem_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
s_axi_mem_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
s_axi_mem_arlock => axi_mem_intercon_M00_AXI_ARLOCK(0),
s_axi_mem_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
s_axi_mem_arready => axi_mem_intercon_M00_AXI_ARREADY,
s_axi_mem_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
s_axi_mem_arvalid => axi_mem_intercon_M00_AXI_ARVALID(0),
s_axi_mem_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
s_axi_mem_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
s_axi_mem_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
s_axi_mem_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
s_axi_mem_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
s_axi_mem_awlock => axi_mem_intercon_M00_AXI_AWLOCK(0),
s_axi_mem_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
s_axi_mem_awready => axi_mem_intercon_M00_AXI_AWREADY,
s_axi_mem_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
s_axi_mem_awvalid => axi_mem_intercon_M00_AXI_AWVALID(0),
s_axi_mem_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
s_axi_mem_bready => axi_mem_intercon_M00_AXI_BREADY(0),
s_axi_mem_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
s_axi_mem_bvalid => axi_mem_intercon_M00_AXI_BVALID,
s_axi_mem_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
s_axi_mem_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
s_axi_mem_rlast => axi_mem_intercon_M00_AXI_RLAST,
s_axi_mem_rready => axi_mem_intercon_M00_AXI_RREADY(0),
s_axi_mem_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
s_axi_mem_rvalid => axi_mem_intercon_M00_AXI_RVALID,
s_axi_mem_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
s_axi_mem_wlast => axi_mem_intercon_M00_AXI_WLAST(0),
s_axi_mem_wready => axi_mem_intercon_M00_AXI_WREADY,
s_axi_mem_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
s_axi_mem_wvalid => axi_mem_intercon_M00_AXI_WVALID(0)
);
axi_ethernetlite_0: component design_1_axi_ethernetlite_0_0
port map (
ip2intc_irpt => axi_ethernetlite_0_ip2intc_irpt,
phy_col => axi_ethernetlite_0_MII_COL,
phy_crs => axi_ethernetlite_0_MII_CRS,
phy_dv => axi_ethernetlite_0_MII_RX_DV,
phy_mdc => axi_ethernetlite_0_MDIO_MDC,
phy_mdio_i => axi_ethernetlite_0_MDIO_MDIO_I,
phy_mdio_o => axi_ethernetlite_0_MDIO_MDIO_O,
phy_mdio_t => axi_ethernetlite_0_MDIO_MDIO_T,
phy_rst_n => NLW_axi_ethernetlite_0_phy_rst_n_UNCONNECTED,
phy_rx_clk => axi_ethernetlite_0_MII_RX_CLK,
phy_rx_data(3 downto 0) => axi_ethernetlite_0_MII_RXD(3 downto 0),
phy_rx_er => axi_ethernetlite_0_MII_RX_ER,
phy_tx_clk => axi_ethernetlite_0_MII_TX_CLK,
phy_tx_data(3 downto 0) => axi_ethernetlite_0_MII_TXD(3 downto 0),
phy_tx_en => axi_ethernetlite_0_MII_TX_EN,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(12 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID,
s_axi_awaddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(12 downto 0),
s_axi_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID
);
axi_mem_intercon: entity work.design_1_axi_mem_intercon_0
port map (
ACLK => microblaze_0_Clk,
ARESETN(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => axi_mem_intercon_M00_AXI_ARLOCK(0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid(0) => axi_mem_intercon_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => axi_mem_intercon_M00_AXI_AWLOCK(0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid(0) => axi_mem_intercon_M00_AXI_AWVALID(0),
M00_AXI_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
M00_AXI_bready(0) => axi_mem_intercon_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
M00_AXI_rlast(0) => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready(0) => axi_mem_intercon_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wlast(0) => axi_mem_intercon_M00_AXI_WLAST(0),
M00_AXI_wready(0) => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => axi_mem_intercon_M00_AXI_WVALID(0),
S00_ACLK => microblaze_0_Clk,
S00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
S00_AXI_arid(0) => microblaze_0_M_AXI_DC_ARID(0),
S00_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
S00_AXI_arlock(0) => microblaze_0_M_AXI_DC_ARLOCK,
S00_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
S00_AXI_arready(0) => microblaze_0_M_AXI_DC_ARREADY(0),
S00_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => microblaze_0_M_AXI_DC_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
S00_AXI_awid(0) => microblaze_0_M_AXI_DC_AWID(0),
S00_AXI_awlen(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
S00_AXI_awlock(0) => microblaze_0_M_AXI_DC_AWLOCK,
S00_AXI_awprot(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
S00_AXI_awready(0) => microblaze_0_M_AXI_DC_AWREADY(0),
S00_AXI_awsize(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
S00_AXI_awvalid(0) => microblaze_0_M_AXI_DC_AWVALID,
S00_AXI_bid(0) => microblaze_0_M_AXI_DC_BID(0),
S00_AXI_bready(0) => microblaze_0_M_AXI_DC_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_M_AXI_DC_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
S00_AXI_rid(0) => microblaze_0_M_AXI_DC_RID(0),
S00_AXI_rlast(0) => microblaze_0_M_AXI_DC_RLAST(0),
S00_AXI_rready(0) => microblaze_0_M_AXI_DC_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_M_AXI_DC_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
S00_AXI_wlast(0) => microblaze_0_M_AXI_DC_WLAST,
S00_AXI_wready(0) => microblaze_0_M_AXI_DC_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_M_AXI_DC_WVALID,
S01_ACLK => microblaze_0_Clk,
S01_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S01_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
S01_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
S01_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
S01_AXI_arid(0) => microblaze_0_M_AXI_IC_ARID(0),
S01_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
S01_AXI_arlock(0) => microblaze_0_M_AXI_IC_ARLOCK,
S01_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
S01_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
S01_AXI_arready(0) => microblaze_0_M_AXI_IC_ARREADY(0),
S01_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
S01_AXI_arvalid(0) => microblaze_0_M_AXI_IC_ARVALID,
S01_AXI_awaddr(31 downto 0) => microblaze_0_M_AXI_IC_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => microblaze_0_M_AXI_IC_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => microblaze_0_M_AXI_IC_AWCACHE(3 downto 0),
S01_AXI_awid(0) => microblaze_0_M_AXI_IC_AWID(0),
S01_AXI_awlen(7 downto 0) => microblaze_0_M_AXI_IC_AWLEN(7 downto 0),
S01_AXI_awlock(0) => microblaze_0_M_AXI_IC_AWLOCK,
S01_AXI_awprot(2 downto 0) => microblaze_0_M_AXI_IC_AWPROT(2 downto 0),
S01_AXI_awqos(3 downto 0) => microblaze_0_M_AXI_IC_AWQOS(3 downto 0),
S01_AXI_awready(0) => microblaze_0_M_AXI_IC_AWREADY(0),
S01_AXI_awsize(2 downto 0) => microblaze_0_M_AXI_IC_AWSIZE(2 downto 0),
S01_AXI_awvalid(0) => microblaze_0_M_AXI_IC_AWVALID,
S01_AXI_bid(0) => microblaze_0_M_AXI_IC_BID(0),
S01_AXI_bready(0) => microblaze_0_M_AXI_IC_BREADY,
S01_AXI_bresp(1 downto 0) => microblaze_0_M_AXI_IC_BRESP(1 downto 0),
S01_AXI_bvalid(0) => microblaze_0_M_AXI_IC_BVALID(0),
S01_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
S01_AXI_rid(0) => microblaze_0_M_AXI_IC_RID(0),
S01_AXI_rlast(0) => microblaze_0_M_AXI_IC_RLAST(0),
S01_AXI_rready(0) => microblaze_0_M_AXI_IC_RREADY,
S01_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
S01_AXI_rvalid(0) => microblaze_0_M_AXI_IC_RVALID(0),
S01_AXI_wdata(31 downto 0) => microblaze_0_M_AXI_IC_WDATA(31 downto 0),
S01_AXI_wlast(0) => microblaze_0_M_AXI_IC_WLAST,
S01_AXI_wready(0) => microblaze_0_M_AXI_IC_WREADY(0),
S01_AXI_wstrb(3 downto 0) => microblaze_0_M_AXI_IC_WSTRB(3 downto 0),
S01_AXI_wvalid(0) => microblaze_0_M_AXI_IC_WVALID
);
axi_timer_0: component design_1_axi_timer_0_0
port map (
capturetrig0 => GND_1,
capturetrig1 => GND_1,
freeze => GND_1,
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(4 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID,
s_axi_awaddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(4 downto 0),
s_axi_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M03_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M03_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID
);
axi_uartlite_0: component design_1_axi_uartlite_0_0
port map (
interrupt => NLW_axi_uartlite_0_interrupt_UNCONNECTED,
rx => axi_uartlite_0_UART_RxD,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M01_AXI_ARVALID,
s_axi_awaddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
s_axi_awready => microblaze_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M01_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M01_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M01_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M01_AXI_WVALID,
tx => axi_uartlite_0_UART_TxD
);
clk_wiz_1: component design_1_clk_wiz_1_0
port map (
clk_in1 => sys_clock_1,
clk_out1 => microblaze_0_Clk,
clk_out2 => clk_wiz_1_clk_out2,
locked => clk_wiz_1_locked,
resetn => reset_1
);
mdm_1: component design_1_mdm_1_0
port map (
Dbg_Capture_0 => microblaze_0_debug_CAPTURE,
Dbg_Clk_0 => microblaze_0_debug_CLK,
Dbg_Reg_En_0(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Rst_0 => microblaze_0_debug_RST,
Dbg_Shift_0 => microblaze_0_debug_SHIFT,
Dbg_TDI_0 => microblaze_0_debug_TDI,
Dbg_TDO_0 => microblaze_0_debug_TDO,
Dbg_Update_0 => microblaze_0_debug_UPDATE,
Debug_SYS_Rst => mdm_1_debug_sys_rst
);
microblaze_0: component design_1_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
Clk => microblaze_0_Clk,
DCE => microblaze_0_dlmb_1_CE,
DReady => microblaze_0_dlmb_1_READY,
DUE => microblaze_0_dlmb_1_UE,
DWait => microblaze_0_dlmb_1_WAIT,
D_AS => microblaze_0_dlmb_1_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
Dbg_Capture => microblaze_0_debug_CAPTURE,
Dbg_Clk => microblaze_0_debug_CLK,
Dbg_Reg_En(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Shift => microblaze_0_debug_SHIFT,
Dbg_TDI => microblaze_0_debug_TDI,
Dbg_TDO => microblaze_0_debug_TDO,
Dbg_Update => microblaze_0_debug_UPDATE,
Debug_Rst => microblaze_0_debug_RST,
ICE => microblaze_0_ilmb_1_CE,
IFetch => microblaze_0_ilmb_1_READSTROBE,
IReady => microblaze_0_ilmb_1_READY,
IUE => microblaze_0_ilmb_1_UE,
IWAIT => microblaze_0_ilmb_1_WAIT,
I_AS => microblaze_0_ilmb_1_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
Interrupt => microblaze_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => microblaze_0_interrupt_ACK(0 to 1),
Interrupt_Address(0) => microblaze_0_interrupt_ADDRESS(31),
Interrupt_Address(1) => microblaze_0_interrupt_ADDRESS(30),
Interrupt_Address(2) => microblaze_0_interrupt_ADDRESS(29),
Interrupt_Address(3) => microblaze_0_interrupt_ADDRESS(28),
Interrupt_Address(4) => microblaze_0_interrupt_ADDRESS(27),
Interrupt_Address(5) => microblaze_0_interrupt_ADDRESS(26),
Interrupt_Address(6) => microblaze_0_interrupt_ADDRESS(25),
Interrupt_Address(7) => microblaze_0_interrupt_ADDRESS(24),
Interrupt_Address(8) => microblaze_0_interrupt_ADDRESS(23),
Interrupt_Address(9) => microblaze_0_interrupt_ADDRESS(22),
Interrupt_Address(10) => microblaze_0_interrupt_ADDRESS(21),
Interrupt_Address(11) => microblaze_0_interrupt_ADDRESS(20),
Interrupt_Address(12) => microblaze_0_interrupt_ADDRESS(19),
Interrupt_Address(13) => microblaze_0_interrupt_ADDRESS(18),
Interrupt_Address(14) => microblaze_0_interrupt_ADDRESS(17),
Interrupt_Address(15) => microblaze_0_interrupt_ADDRESS(16),
Interrupt_Address(16) => microblaze_0_interrupt_ADDRESS(15),
Interrupt_Address(17) => microblaze_0_interrupt_ADDRESS(14),
Interrupt_Address(18) => microblaze_0_interrupt_ADDRESS(13),
Interrupt_Address(19) => microblaze_0_interrupt_ADDRESS(12),
Interrupt_Address(20) => microblaze_0_interrupt_ADDRESS(11),
Interrupt_Address(21) => microblaze_0_interrupt_ADDRESS(10),
Interrupt_Address(22) => microblaze_0_interrupt_ADDRESS(9),
Interrupt_Address(23) => microblaze_0_interrupt_ADDRESS(8),
Interrupt_Address(24) => microblaze_0_interrupt_ADDRESS(7),
Interrupt_Address(25) => microblaze_0_interrupt_ADDRESS(6),
Interrupt_Address(26) => microblaze_0_interrupt_ADDRESS(5),
Interrupt_Address(27) => microblaze_0_interrupt_ADDRESS(4),
Interrupt_Address(28) => microblaze_0_interrupt_ADDRESS(3),
Interrupt_Address(29) => microblaze_0_interrupt_ADDRESS(2),
Interrupt_Address(30) => microblaze_0_interrupt_ADDRESS(1),
Interrupt_Address(31) => microblaze_0_interrupt_ADDRESS(0),
M_AXI_DC_ARADDR(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
M_AXI_DC_ARBURST(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
M_AXI_DC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
M_AXI_DC_ARID(0) => microblaze_0_M_AXI_DC_ARID(0),
M_AXI_DC_ARLEN(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
M_AXI_DC_ARLOCK => microblaze_0_M_AXI_DC_ARLOCK,
M_AXI_DC_ARPROT(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
M_AXI_DC_ARQOS(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
M_AXI_DC_ARREADY => microblaze_0_M_AXI_DC_ARREADY(0),
M_AXI_DC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
M_AXI_DC_ARVALID => microblaze_0_M_AXI_DC_ARVALID,
M_AXI_DC_AWADDR(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
M_AXI_DC_AWBURST(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
M_AXI_DC_AWCACHE(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
M_AXI_DC_AWID(0) => microblaze_0_M_AXI_DC_AWID(0),
M_AXI_DC_AWLEN(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
M_AXI_DC_AWLOCK => microblaze_0_M_AXI_DC_AWLOCK,
M_AXI_DC_AWPROT(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
M_AXI_DC_AWQOS(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
M_AXI_DC_AWREADY => microblaze_0_M_AXI_DC_AWREADY(0),
M_AXI_DC_AWSIZE(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
M_AXI_DC_AWVALID => microblaze_0_M_AXI_DC_AWVALID,
M_AXI_DC_BID(0) => microblaze_0_M_AXI_DC_BID(0),
M_AXI_DC_BREADY => microblaze_0_M_AXI_DC_BREADY,
M_AXI_DC_BRESP(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
M_AXI_DC_BVALID => microblaze_0_M_AXI_DC_BVALID(0),
M_AXI_DC_RDATA(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
M_AXI_DC_RID(0) => microblaze_0_M_AXI_DC_RID(0),
M_AXI_DC_RLAST => microblaze_0_M_AXI_DC_RLAST(0),
M_AXI_DC_RREADY => microblaze_0_M_AXI_DC_RREADY,
M_AXI_DC_RRESP(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
M_AXI_DC_RVALID => microblaze_0_M_AXI_DC_RVALID(0),
M_AXI_DC_WDATA(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
M_AXI_DC_WLAST => microblaze_0_M_AXI_DC_WLAST,
M_AXI_DC_WREADY => microblaze_0_M_AXI_DC_WREADY(0),
M_AXI_DC_WSTRB(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
M_AXI_DC_WVALID => microblaze_0_M_AXI_DC_WVALID,
M_AXI_DP_ARADDR(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => microblaze_0_axi_dp_ARREADY(0),
M_AXI_DP_ARVALID => microblaze_0_axi_dp_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => microblaze_0_axi_dp_AWREADY(0),
M_AXI_DP_AWVALID => microblaze_0_axi_dp_AWVALID,
M_AXI_DP_BREADY => microblaze_0_axi_dp_BREADY,
M_AXI_DP_BRESP(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
M_AXI_DP_BVALID => microblaze_0_axi_dp_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
M_AXI_DP_RREADY => microblaze_0_axi_dp_RREADY,
M_AXI_DP_RRESP(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
M_AXI_DP_RVALID => microblaze_0_axi_dp_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
M_AXI_DP_WREADY => microblaze_0_axi_dp_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
M_AXI_DP_WVALID => microblaze_0_axi_dp_WVALID,
M_AXI_IC_ARADDR(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
M_AXI_IC_ARBURST(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
M_AXI_IC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
M_AXI_IC_ARID(0) => microblaze_0_M_AXI_IC_ARID(0),
M_AXI_IC_ARLEN(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
M_AXI_IC_ARLOCK => microblaze_0_M_AXI_IC_ARLOCK,
M_AXI_IC_ARPROT(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
M_AXI_IC_ARQOS(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
M_AXI_IC_ARREADY => microblaze_0_M_AXI_IC_ARREADY(0),
M_AXI_IC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
M_AXI_IC_ARVALID => microblaze_0_M_AXI_IC_ARVALID,
M_AXI_IC_AWADDR(31 downto 0) => microblaze_0_M_AXI_IC_AWADDR(31 downto 0),
M_AXI_IC_AWBURST(1 downto 0) => microblaze_0_M_AXI_IC_AWBURST(1 downto 0),
M_AXI_IC_AWCACHE(3 downto 0) => microblaze_0_M_AXI_IC_AWCACHE(3 downto 0),
M_AXI_IC_AWID(0) => microblaze_0_M_AXI_IC_AWID(0),
M_AXI_IC_AWLEN(7 downto 0) => microblaze_0_M_AXI_IC_AWLEN(7 downto 0),
M_AXI_IC_AWLOCK => microblaze_0_M_AXI_IC_AWLOCK,
M_AXI_IC_AWPROT(2 downto 0) => microblaze_0_M_AXI_IC_AWPROT(2 downto 0),
M_AXI_IC_AWQOS(3 downto 0) => microblaze_0_M_AXI_IC_AWQOS(3 downto 0),
M_AXI_IC_AWREADY => microblaze_0_M_AXI_IC_AWREADY(0),
M_AXI_IC_AWSIZE(2 downto 0) => microblaze_0_M_AXI_IC_AWSIZE(2 downto 0),
M_AXI_IC_AWVALID => microblaze_0_M_AXI_IC_AWVALID,
M_AXI_IC_BID(0) => microblaze_0_M_AXI_IC_BID(0),
M_AXI_IC_BREADY => microblaze_0_M_AXI_IC_BREADY,
M_AXI_IC_BRESP(1 downto 0) => microblaze_0_M_AXI_IC_BRESP(1 downto 0),
M_AXI_IC_BVALID => microblaze_0_M_AXI_IC_BVALID(0),
M_AXI_IC_RDATA(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
M_AXI_IC_RID(0) => microblaze_0_M_AXI_IC_RID(0),
M_AXI_IC_RLAST => microblaze_0_M_AXI_IC_RLAST(0),
M_AXI_IC_RREADY => microblaze_0_M_AXI_IC_RREADY,
M_AXI_IC_RRESP(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
M_AXI_IC_RVALID => microblaze_0_M_AXI_IC_RVALID(0),
M_AXI_IC_WDATA(31 downto 0) => microblaze_0_M_AXI_IC_WDATA(31 downto 0),
M_AXI_IC_WLAST => microblaze_0_M_AXI_IC_WLAST,
M_AXI_IC_WREADY => microblaze_0_M_AXI_IC_WREADY(0),
M_AXI_IC_WSTRB(3 downto 0) => microblaze_0_M_AXI_IC_WSTRB(3 downto 0),
M_AXI_IC_WVALID => microblaze_0_M_AXI_IC_WVALID,
Read_Strobe => microblaze_0_dlmb_1_READSTROBE,
Reset => rst_clk_wiz_1_100M_mb_reset,
Write_Strobe => microblaze_0_dlmb_1_WRITESTROBE
);
microblaze_0_axi_intc: component design_1_microblaze_0_axi_intc_0
port map (
interrupt_address(31 downto 0) => microblaze_0_interrupt_ADDRESS(31 downto 0),
intr(1 downto 0) => microblaze_0_intr(1 downto 0),
irq => microblaze_0_interrupt_INTERRUPT,
processor_ack(1) => microblaze_0_interrupt_ACK(0),
processor_ack(0) => microblaze_0_interrupt_ACK(1),
processor_clk => microblaze_0_Clk,
processor_rst => rst_clk_wiz_1_100M_mb_reset,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_intc_axi_ARREADY,
s_axi_arvalid => microblaze_0_intc_axi_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_intc_axi_AWREADY,
s_axi_awvalid => microblaze_0_intc_axi_AWVALID,
s_axi_bready => microblaze_0_intc_axi_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_intc_axi_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
s_axi_rready => microblaze_0_intc_axi_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_intc_axi_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
s_axi_wready => microblaze_0_intc_axi_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_intc_axi_WVALID
);
microblaze_0_axi_periph: entity work.design_1_microblaze_0_axi_periph_0
port map (
ACLK => microblaze_0_Clk,
ARESETN(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
M00_AXI_arready => microblaze_0_intc_axi_ARREADY,
M00_AXI_arvalid => microblaze_0_intc_axi_ARVALID,
M00_AXI_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
M00_AXI_awready => microblaze_0_intc_axi_AWREADY,
M00_AXI_awvalid => microblaze_0_intc_axi_AWVALID,
M00_AXI_bready => microblaze_0_intc_axi_BREADY,
M00_AXI_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
M00_AXI_bvalid => microblaze_0_intc_axi_BVALID,
M00_AXI_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
M00_AXI_rready => microblaze_0_intc_axi_RREADY,
M00_AXI_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
M00_AXI_rvalid => microblaze_0_intc_axi_RVALID,
M00_AXI_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
M00_AXI_wready => microblaze_0_intc_axi_WREADY,
M00_AXI_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
M00_AXI_wvalid => microblaze_0_intc_axi_WVALID,
M01_ACLK => microblaze_0_Clk,
M01_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M01_AXI_araddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
M01_AXI_arready => microblaze_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => microblaze_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(3 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
M01_AXI_awready => microblaze_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => microblaze_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => microblaze_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => microblaze_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => microblaze_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => microblaze_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => microblaze_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => microblaze_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => microblaze_0_Clk,
M02_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M02_AXI_araddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(12 downto 0),
M02_AXI_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(12 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(12 downto 0),
M02_AXI_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => microblaze_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => microblaze_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => microblaze_0_Clk,
M03_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M03_AXI_araddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(4 downto 0),
M03_AXI_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(4 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(4 downto 0),
M03_AXI_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => microblaze_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => microblaze_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
S00_AXI_arready(0) => microblaze_0_axi_dp_ARREADY(0),
S00_AXI_arvalid(0) => microblaze_0_axi_dp_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
S00_AXI_awready(0) => microblaze_0_axi_dp_AWREADY(0),
S00_AXI_awvalid(0) => microblaze_0_axi_dp_AWVALID,
S00_AXI_bready(0) => microblaze_0_axi_dp_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_axi_dp_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
S00_AXI_rready(0) => microblaze_0_axi_dp_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_axi_dp_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
S00_AXI_wready(0) => microblaze_0_axi_dp_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_axi_dp_WVALID
);
microblaze_0_local_memory: entity work.microblaze_0_local_memory_imp_1K0VQXK
port map (
DLMB_abus(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
DLMB_addrstrobe => microblaze_0_dlmb_1_ADDRSTROBE,
DLMB_be(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
DLMB_ce => microblaze_0_dlmb_1_CE,
DLMB_readdbus(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
DLMB_readstrobe => microblaze_0_dlmb_1_READSTROBE,
DLMB_ready => microblaze_0_dlmb_1_READY,
DLMB_ue => microblaze_0_dlmb_1_UE,
DLMB_wait => microblaze_0_dlmb_1_WAIT,
DLMB_writedbus(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
DLMB_writestrobe => microblaze_0_dlmb_1_WRITESTROBE,
ILMB_abus(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
ILMB_addrstrobe => microblaze_0_ilmb_1_ADDRSTROBE,
ILMB_ce => microblaze_0_ilmb_1_CE,
ILMB_readdbus(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
ILMB_readstrobe => microblaze_0_ilmb_1_READSTROBE,
ILMB_ready => microblaze_0_ilmb_1_READY,
ILMB_ue => microblaze_0_ilmb_1_UE,
ILMB_wait => microblaze_0_ilmb_1_WAIT,
LMB_Clk => microblaze_0_Clk,
SYS_Rst(0) => rst_clk_wiz_1_100M_bus_struct_reset(0)
);
microblaze_0_xlconcat: component design_1_microblaze_0_xlconcat_0
port map (
In0(0) => axi_timer_0_interrupt,
In1(0) => axi_ethernetlite_0_ip2intc_irpt,
dout(1 downto 0) => microblaze_0_intr(1 downto 0)
);
mii_to_rmii_0: component design_1_mii_to_rmii_0_0
port map (
mac2rmii_tx_en => axi_ethernetlite_0_MII_TX_EN,
mac2rmii_tx_er => GND_1,
mac2rmii_txd(3 downto 0) => axi_ethernetlite_0_MII_TXD(3 downto 0),
phy2rmii_crs_dv => mii_to_rmii_0_RMII_PHY_M_CRS_DV,
phy2rmii_rx_er => mii_to_rmii_0_RMII_PHY_M_RX_ER,
phy2rmii_rxd(1 downto 0) => mii_to_rmii_0_RMII_PHY_M_RXD(1 downto 0),
ref_clk => clk_wiz_1_clk_out2,
rmii2mac_col => axi_ethernetlite_0_MII_COL,
rmii2mac_crs => axi_ethernetlite_0_MII_CRS,
rmii2mac_rx_clk => axi_ethernetlite_0_MII_RX_CLK,
rmii2mac_rx_dv => axi_ethernetlite_0_MII_RX_DV,
rmii2mac_rx_er => axi_ethernetlite_0_MII_RX_ER,
rmii2mac_rxd(3 downto 0) => axi_ethernetlite_0_MII_RXD(3 downto 0),
rmii2mac_tx_clk => axi_ethernetlite_0_MII_TX_CLK,
rmii2phy_tx_en => mii_to_rmii_0_RMII_PHY_M_TX_EN,
rmii2phy_txd(1 downto 0) => mii_to_rmii_0_RMII_PHY_M_TXD(1 downto 0),
rst_n => reset_1
);
rst_clk_wiz_1_100M: component design_1_rst_clk_wiz_1_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => rst_clk_wiz_1_100M_bus_struct_reset(0),
dcm_locked => clk_wiz_1_locked,
ext_reset_in => reset_1,
interconnect_aresetn(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_1_debug_sys_rst,
mb_reset => rst_clk_wiz_1_100M_mb_reset,
peripheral_aresetn(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => microblaze_0_Clk
);
end STRUCTURE;
|
gpl-3.0
|
ea123f32b1a93e662c88539d402cefec
| 0.66704 | 2.814706 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/ld_arith_reg.vhd
| 8 | 14,864 |
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
gpl-3.0
|
6bdd1cabc3a81b400b4d1cd8b5d67e2a
| 0.383881 | 4.966255 | false | false | false | false |
lowRISC/greth-library
|
greth_library/rocketlib/rocket_l2cache.vhd
| 2 | 16,572 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief RISC-V "Rocket Core" with enabled L2-cache.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! TileLink interface description.
use rocketlib.types_rocket.all;
--! @brief Rocket Chip Top-level with enabled L2-cache.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uached Tile AXI master index
--! @param[in] rst Reset.Active High. Usually assigned to button "Center".
--! @param[in] clk_sys System clock.
--! @param[in] clk_htif HTIF bus clock.
--! @param[in] msti AXI System bus response.
--! @param[out] msto1 Cached Tile requests converted to AXI system bus.
--! @param[out] msto2 Uncached Tile requests converted to AXI system bus.
--! @param[in] htifo HTIF bus request bus. Device-to-Tile.
--! @param[out] htifi HTIF bus response bus. Tile-to-Device
entity rocket_l2cache is
generic (
xindex1 : integer := 0;
xindex2 : integer := 0
);
port
(
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
--! @}
end rocket_l2cache;
--! @brief Rocket-chip with L2-cache architecture declaration.
architecture arch_rocket_l2cache of rocket_l2cache is
constant xmstconfig1 : nasti_master_config_type := (
xindex => xindex1,
vid => VENDOR_GNSSSENSOR,
did => RISCV_CACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
constant xmstconfig2 : nasti_master_config_type := (
xindex => xindex2,
vid => VENDOR_GNSSSENSOR,
did => RISCV_UNCACHED_TILELINK,
descrtype => PNP_CFG_TYPE_MASTER,
descrsize => PNP_CFG_MASTER_DESCR_BYTES
);
signal rstn : std_logic;
signal init_ena : std_logic;
--! Multiplexed signal of the external HTIF requests and of the
--! 'starter' module.
signal htifo_starter : host_out_type;
signal htifo_mux : host_out_type;
signal htifi_deser : host_in_type;
signal clk_htif : std_logic;
signal cpu2htif : htif_serdes_in_type;
signal htif2cpu : htif_serdes_out_type;
--! @brief Rocket Cores hard-reset initialization module
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allowed to CPU start
--! execution. This reseting cycle is continuing upto external
--! write 0-value into this MRESET register.
--! param[in] core_idx Recipient core index. Multicore not implemented yet.
--! param[in] clk Clock sinal for the HTIFIO bus.
--! param[in] nrst Module reset signal with the active Low level.
--! param[in] hosti HostIO interface input signals.
--! param[out] hosto HostIO interface output signals.
--! param[in] srdi HostIO serialized data input.
--! param[out] srdo HostIO serialized data output.
component htif_serdes is
generic (
core_idx : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
hostoi : in host_out_type;
hostio : out host_in_type;
srdi : in htif_serdes_in_type;
srdo : out htif_serdes_out_type
);
end component;
--! @brief Hard-reset 'Uncore' initializer.
--! @details Rocket-chip is constantly reseting after power-up to start
--! execution we must write into MRESET CSR register.
component starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end component;
--! @brief Rocket NoC Verilog implementation generated by SCALA.
component Top
port (
clk : in std_logic;
reset : in std_logic;
io_host_clk : out std_logic;
io_host_clk_edge : out std_logic;
io_host_in_ready : out std_logic;
io_host_in_valid : in std_logic;
io_host_in_bits : in std_logic_vector(15 downto 0);
io_host_out_ready : in std_logic;
io_host_out_valid : out std_logic;
io_host_out_bits : out std_logic_vector(15 downto 0);
io_host_debug_stats_csr : out std_logic;
io_mem_backup_ctrl_en : in std_logic;
io_mem_backup_ctrl_in_valid : in std_logic;
io_mem_backup_ctrl_out_ready : in std_logic;
io_mem_backup_ctrl_out_valid : out std_logic;
io_mem_0_aw_ready : in std_logic;
io_mem_0_aw_valid : out std_logic;
io_mem_0_aw_bits_addr : out std_logic_vector(31 downto 0);
io_mem_0_aw_bits_len : out std_logic_vector(7 downto 0);
io_mem_0_aw_bits_size : out std_logic_vector(2 downto 0);
io_mem_0_aw_bits_burst : out std_logic_vector(1 downto 0);
io_mem_0_aw_bits_lock : out std_logic;
io_mem_0_aw_bits_cache : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_prot : out std_logic_vector(2 downto 0);
io_mem_0_aw_bits_qos : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_region : out std_logic_vector(3 downto 0);
io_mem_0_aw_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_aw_bits_user : out std_logic;
io_mem_0_w_ready : in std_logic;
io_mem_0_w_valid : out std_logic;
io_mem_0_w_bits_data : out std_logic_vector(127 downto 0);
io_mem_0_w_bits_last : out std_logic;
io_mem_0_w_bits_strb : out std_logic_vector(15 downto 0);
io_mem_0_w_bits_user : out std_logic;
io_mem_0_b_ready : out std_logic;
io_mem_0_b_valid : in std_logic;
io_mem_0_b_bits_resp : in std_logic_vector(1 downto 0);
io_mem_0_b_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_b_bits_user : in std_logic;
io_mem_0_ar_ready : in std_logic;
io_mem_0_ar_valid : out std_logic;
io_mem_0_ar_bits_addr : out std_logic_vector(31 downto 0);
io_mem_0_ar_bits_len : out std_logic_vector(7 downto 0);
io_mem_0_ar_bits_size : out std_logic_vector(2 downto 0);
io_mem_0_ar_bits_burst : out std_logic_vector(1 downto 0);
io_mem_0_ar_bits_lock : out std_logic;
io_mem_0_ar_bits_cache : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_prot : out std_logic_vector(2 downto 0);
io_mem_0_ar_bits_qos : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_region : out std_logic_vector(3 downto 0);
io_mem_0_ar_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_ar_bits_user : out std_logic;
io_mem_0_r_ready : out std_logic;
io_mem_0_r_valid : in std_logic;
io_mem_0_r_bits_resp : in std_logic_vector(1 downto 0);
io_mem_0_r_bits_data : in std_logic_vector(127 downto 0);
io_mem_0_r_bits_last : in std_logic;
io_mem_0_r_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mem_0_r_bits_user : in std_logic;
--! mmio
io_mmio_aw_ready : in std_logic;
io_mmio_aw_valid : out std_logic;
io_mmio_aw_bits_addr : out std_logic_vector(31 downto 0);
io_mmio_aw_bits_len : out std_logic_vector(7 downto 0);
io_mmio_aw_bits_size : out std_logic_vector(2 downto 0);
io_mmio_aw_bits_burst : out std_logic_vector(1 downto 0);
io_mmio_aw_bits_lock : out std_logic;
io_mmio_aw_bits_cache : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_prot : out std_logic_vector(2 downto 0);
io_mmio_aw_bits_qos : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_region : out std_logic_vector(3 downto 0);
io_mmio_aw_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_aw_bits_user : out std_logic;
io_mmio_w_ready : in std_logic;
io_mmio_w_valid : out std_logic;
io_mmio_w_bits_data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
io_mmio_w_bits_last : out std_logic;
io_mmio_w_bits_strb : out std_logic_vector(15 downto 0);
io_mmio_w_bits_user : out std_logic;
io_mmio_b_ready : out std_logic;
io_mmio_b_valid : in std_logic;
io_mmio_b_bits_resp : in std_logic_vector(1 downto 0);
io_mmio_b_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_b_bits_user : in std_logic;
io_mmio_ar_ready : in std_logic;
io_mmio_ar_valid : out std_logic;
io_mmio_ar_bits_addr : out std_logic_vector(31 downto 0);
io_mmio_ar_bits_len : out std_logic_vector(7 downto 0);
io_mmio_ar_bits_size : out std_logic_vector(2 downto 0);
io_mmio_ar_bits_burst : out std_logic_vector(1 downto 0);
io_mmio_ar_bits_lock : out std_logic;
io_mmio_ar_bits_cache : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_prot : out std_logic_vector(2 downto 0);
io_mmio_ar_bits_qos : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_region : out std_logic_vector(3 downto 0);
io_mmio_ar_bits_id : out std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_ar_bits_user : out std_logic;
io_mmio_r_ready : out std_logic;
io_mmio_r_valid : in std_logic;
io_mmio_r_bits_resp : in std_logic_vector(1 downto 0);
io_mmio_r_bits_data : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
io_mmio_r_bits_last : in std_logic;
io_mmio_r_bits_id : in std_logic_vector(CFG_ROCKET_ID_BITS-1 downto 0);
io_mmio_r_bits_user : in std_logic
--init : in std_logic
);
end component;
begin
mstcfg1 <= xmstconfig1;
mstcfg2 <= xmstconfig2;
rstn <= not rst;
clk_htif <= clk_sys; -- clock htif not used in Scala generated sources when FPGA define enabled.
------------------------------------
-- Hardware init and MRESET for the CPUs
start0 : starter port map
(
clk => clk_htif,
nrst => rstn,
i_host => htifi_deser,
o_host => htifo_starter,
o_init_ena => init_ena
);
--! Starter HTIF bus has the highest priority because it is
--! unreset CPU/Uncore at the very begining after hard-reset and then
--! doesn't make any action.
htifo_mux <= htifo_starter when init_ena = '1' else htifoi;
serdes0 : htif_serdes generic map (
core_idx => 0
) port map (
clk => clk_htif,
nrst => rstn,
hostoi => htifo_mux,
hostio => htifi_deser,
srdi => cpu2htif,
srdo => htif2cpu
);
htifio <= htifi_deser;
------------------------------------
--! @brief NoC core instance.
rocket0 : Top port map
(
clk => clk_sys, --in
reset => rst, --in
io_host_in_valid => htif2cpu.valid, --in
io_host_in_ready => cpu2htif.ready, --out
io_host_in_bits => htif2cpu.bits, --in[15:0]
io_host_out_valid => cpu2htif.valid, --out
io_host_out_ready => htif2cpu.ready, --in
io_host_out_bits => cpu2htif.bits, --out[15:0] goes to Starter and Memory DeSerializer
io_host_clk => clk_htif, --out
io_host_clk_edge => open, --out
io_host_debug_stats_csr => open, --out (unused)
io_mem_backup_ctrl_en => '0', --in
io_mem_backup_ctrl_in_valid => '0',--mem_bk_in_valid_delay, --in
io_mem_backup_ctrl_out_ready => '0',--mem_bk_out_ready_delay,--in
io_mem_backup_ctrl_out_valid => open,--mem_bk_out_valid_delay,--out
--! mem
io_mem_0_aw_ready => msti.aw_ready,--in
io_mem_0_aw_valid => msto1.aw_valid,--out
io_mem_0_aw_bits_addr => msto1.aw_bits.addr,--out[31:0]
io_mem_0_aw_bits_len => msto1.aw_bits.len,--out[7:0]
io_mem_0_aw_bits_size => msto1.aw_bits.size,--out[2:0]
io_mem_0_aw_bits_burst => msto1.aw_bits.burst,--out[1:0]
io_mem_0_aw_bits_lock => msto1.aw_bits.lock,--out
io_mem_0_aw_bits_cache => msto1.aw_bits.cache,--out[3:0]
io_mem_0_aw_bits_prot => msto1.aw_bits.prot,--out[2:0]
io_mem_0_aw_bits_qos => msto1.aw_bits.qos,--out[3:0]
io_mem_0_aw_bits_region => msto1.aw_bits.region,--out[3:0]
io_mem_0_aw_bits_id => msto1.aw_id,--out[5:0]
io_mem_0_aw_bits_user => msto1.aw_user,--out
io_mem_0_w_ready => msti.w_ready,--in
io_mem_0_w_valid => msto1.w_valid,--out
io_mem_0_w_bits_data => msto1.w_data,--out[127:0]
io_mem_0_w_bits_last => msto1.w_last,--out
io_mem_0_w_bits_strb => msto1.w_strb,--out[15:0]
io_mem_0_w_bits_user => msto1.w_user,--out
io_mem_0_b_ready => msto1.b_ready,--out
io_mem_0_b_valid => msti.b_valid,--in
io_mem_0_b_bits_resp => msti.b_resp,--in[1:0]
io_mem_0_b_bits_id => msti.b_id,--in[5:0]
io_mem_0_b_bits_user => msti.b_user,--in
io_mem_0_ar_ready => msti.ar_ready,--in
io_mem_0_ar_valid => msto1.ar_valid,--out
io_mem_0_ar_bits_addr => msto1.ar_bits.addr,--out[31:0]
io_mem_0_ar_bits_len => msto1.ar_bits.len,--out[7:0]
io_mem_0_ar_bits_size => msto1.ar_bits.size,--out[2:0]
io_mem_0_ar_bits_burst => msto1.ar_bits.burst,--out[1:0]
io_mem_0_ar_bits_lock => msto1.ar_bits.lock,--out
io_mem_0_ar_bits_cache => msto1.ar_bits.cache,--out[3:0]
io_mem_0_ar_bits_prot => msto1.ar_bits.prot,--out[2:0]
io_mem_0_ar_bits_qos => msto1.ar_bits.qos,--out[3:0]
io_mem_0_ar_bits_region => msto1.ar_bits.region,--out[3:0]
io_mem_0_ar_bits_id => msto1.ar_id,--out[5:0]
io_mem_0_ar_bits_user => msto1.ar_user,--out
io_mem_0_r_ready => msto1.r_ready,--out
io_mem_0_r_valid => msti.r_valid,--in
io_mem_0_r_bits_resp => msti.r_resp,--in[1:0]
io_mem_0_r_bits_data => msti.r_data,--in[127:0]
io_mem_0_r_bits_last => msti.r_last,--in
io_mem_0_r_bits_id => msti.r_id,--in[5:0]
io_mem_0_r_bits_user => msti.r_user,--in
--! mmio
io_mmio_aw_ready => msti.aw_ready,--in
io_mmio_aw_valid => msto2.aw_valid,--out
io_mmio_aw_bits_addr => msto2.aw_bits.addr,--out[31:0]
io_mmio_aw_bits_len => msto2.aw_bits.len,--out[7:0]
io_mmio_aw_bits_size => msto2.aw_bits.size,--out[2:0]
io_mmio_aw_bits_burst => msto2.aw_bits.burst,--out[1:0]
io_mmio_aw_bits_lock => msto2.aw_bits.lock,--out
io_mmio_aw_bits_cache => msto2.aw_bits.cache,--out[3:0]
io_mmio_aw_bits_prot => msto2.aw_bits.prot,--out[2:0]
io_mmio_aw_bits_qos => msto2.aw_bits.qos,--out[3:0]
io_mmio_aw_bits_region => msto2.aw_bits.region,--out[3:0]
io_mmio_aw_bits_id => msto2.aw_id,--out[5:0]
io_mmio_aw_bits_user => msto2.aw_user,--out
io_mmio_w_ready => msti.w_ready,--in
io_mmio_w_valid => msto2.w_valid,--out
io_mmio_w_bits_data => msto2.w_data,--out[127:0]
io_mmio_w_bits_last => msto2.w_last,--out
io_mmio_w_bits_strb => msto2.w_strb,--out[15:0]
io_mmio_w_bits_user => msto2.w_user,--out
io_mmio_b_ready => msto2.b_ready,--out
io_mmio_b_valid => msti.b_valid,--in
io_mmio_b_bits_resp => msti.b_resp,--in[1:0]
io_mmio_b_bits_id => msti.b_id,--in[5:0]
io_mmio_b_bits_user => msti.b_user,--in
io_mmio_ar_ready => msti.ar_ready,--in
io_mmio_ar_valid => msto2.ar_valid,--out
io_mmio_ar_bits_addr => msto2.ar_bits.addr,--out[31:0]
io_mmio_ar_bits_len => msto2.ar_bits.len,--out[7:0]
io_mmio_ar_bits_size => msto2.ar_bits.size,--out[2:0]
io_mmio_ar_bits_burst => msto2.ar_bits.burst,--out[1:0]
io_mmio_ar_bits_lock => msto2.ar_bits.lock,--out
io_mmio_ar_bits_cache => msto2.ar_bits.cache,--out[3:0]
io_mmio_ar_bits_prot => msto2.ar_bits.prot,--out[2:0]
io_mmio_ar_bits_qos => msto2.ar_bits.qos,--out[3:0]
io_mmio_ar_bits_region => msto2.ar_bits.region,--out[3:0]
io_mmio_ar_bits_id => msto2.ar_id,--out[5:0]
io_mmio_ar_bits_user => msto2.ar_user,--out
io_mmio_r_ready => msto2.r_ready,--out
io_mmio_r_valid => msti.r_valid,--in
io_mmio_r_bits_resp => msti.r_resp,--in[1:0]
io_mmio_r_bits_data => msti.r_data,--in[127:0]
io_mmio_r_bits_last => msti.r_last,--in
io_mmio_r_bits_id => msti.r_id,--in[5:0]
io_mmio_r_bits_user => msti.r_user--in
);
end arch_rocket_l2cache;
|
bsd-2-clause
|
e48292ce4e9bc0e459054ccf3c6dc809
| 0.622677 | 2.803587 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/synth/design_1_lmb_bram_0.vhd
| 2 | 15,376 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_lmb_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_lmb_bram_0;
ARCHITECTURE design_1_lmb_bram_0_arch OF design_1_lmb_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_lmb_bram_0_arch : ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=design_1_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "design_1_lmb_bram_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 8192,
C_READ_DEPTH_A => 8192,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 8192,
C_READ_DEPTH_B => 8192,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_lmb_bram_0_arch;
|
gpl-3.0
|
2766e4d1c1b0c9b30a0104a663327f53
| 0.6343 | 3.033938 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/PressureTransducerArray/PressureTransducerArray.srcs/sim_1/new/tb_DataSequencer.vhd
| 1 | 4,575 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02.03.2016 15:04:38
-- Design Name:
-- Module Name: tb_DataSequencer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_DataSequencer is
-- Port ( );
end tb_DataSequencer;
architecture Behavioral of tb_DataSequencer is
constant Clk_period : time := 10ns;
signal clk :STD_LOGIC;
signal reset:STD_LOGIC;
signal Serial_FIFO_WriteEn : STD_LOGIC;
signal Serial_FIFO_DataIn : STD_LOGIC_VECTOR ( 7 downto 0);
signal Serial_FIFO_Full : STD_LOGIC:= '0';
--sensor 1
signal I2C1_FIFO_ReadEn : STD_LOGIC;
signal I2C1_FIFO_DataOut :STD_LOGIC_VECTOR ( 7 downto 0):= "00001010";
signal I2C1_FIFO_Empty : STD_LOGIC:= '0';
--sensor 2
signal I2C2_FIFO_ReadEn : STD_LOGIC;
signal I2C2_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C2_FIFO_Empty : STD_LOGIC:= '0';
--sensor 3
signal I2C3_FIFO_ReadEn : STD_LOGIC;
signal I2C3_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C3_FIFO_Empty : STD_LOGIC:= '0';
--sensor 4
signal I2C4_FIFO_ReadEn : STD_LOGIC;
signal I2C4_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C4_FIFO_Empty : STD_LOGIC:= '0';
--sensor 5
signal I2C5_FIFO_ReadEn : STD_LOGIC;
signal I2C5_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C5_FIFO_Empty : STD_LOGIC:= '0';
--sensor 6
signal I2C6_FIFO_ReadEn : STD_LOGIC;
signal I2C6_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C6_FIFO_Empty : STD_LOGIC:= '0';
--sensor 7
signal I2C7_FIFO_ReadEn : STD_LOGIC;
signal I2C7_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C7_FIFO_Empty : STD_LOGIC:= '0';
--sensor 8
signal I2C8_FIFO_ReadEn : STD_LOGIC;
signal I2C8_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C8_FIFO_Empty : STD_LOGIC:= '0';
--sensor 9
signal I2C9_FIFO_ReadEn : STD_LOGIC;
signal I2C9_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C9_FIFO_Empty : STD_LOGIC:= '0';
--sensor 10
signal I2C10_FIFO_ReadEn : STD_LOGIC;
signal I2C10_FIFO_DataOut : STD_LOGIC_VECTOR ( 7 downto 0);
signal I2C10_FIFO_Empty : STD_LOGIC:= '0';
begin
-- Clock process definitions
Clk_process :process
begin
clk <= '0';
wait for Clk_period/2;
clk <= '1';
wait for Clk_period/2;
end process;
UUT:entity work.DataSequencer(Behavioral)
port map (
clk => clk,
reset => reset,
S_FIFO_WriteEn => Serial_FIFO_WriteEn,
S_FIFO_DataIn => Serial_FIFO_DataIn,
S_FIFO_Full => Serial_FIFO_Full,
I2C1_FIFO_ReadEn => I2C1_FIFO_ReadEn,
I2C1_FIFO_DataOut => I2C1_FIFO_DataOut,
I2C1_FIFO_Empty => I2C1_FIFO_Empty,
I2C2_FIFO_ReadEn => I2C2_FIFO_ReadEn,
I2C2_FIFO_DataOut => I2C2_FIFO_DataOut,
I2C2_FIFO_Empty => I2C2_FIFO_Empty,
I2C3_FIFO_ReadEn => I2C3_FIFO_ReadEn,
I2C3_FIFO_DataOut => I2C3_FIFO_DataOut,
I2C3_FIFO_Empty => I2C3_FIFO_Empty,
I2C4_FIFO_ReadEn => I2C4_FIFO_ReadEn,
I2C4_FIFO_DataOut => I2C4_FIFO_DataOut,
I2C4_FIFO_Empty => I2C4_FIFO_Empty,
I2C5_FIFO_ReadEn => I2C5_FIFO_ReadEn,
I2C5_FIFO_DataOut => I2C5_FIFO_DataOut,
I2C5_FIFO_Empty => I2C5_FIFO_Empty,
I2C6_FIFO_ReadEn => I2C6_FIFO_ReadEn,
I2C6_FIFO_DataOut => I2C6_FIFO_DataOut,
I2C6_FIFO_Empty => I2C6_FIFO_Empty,
I2C7_FIFO_ReadEn => I2C7_FIFO_ReadEn,
I2C7_FIFO_DataOut => I2C7_FIFO_DataOut,
I2C7_FIFO_Empty => I2C7_FIFO_Empty,
I2C8_FIFO_ReadEn => I2C8_FIFO_ReadEn,
I2C8_FIFO_DataOut => I2C8_FIFO_DataOut,
I2C8_FIFO_Empty => I2C8_FIFO_Empty,
I2C9_FIFO_ReadEn => I2C9_FIFO_ReadEn,
I2C9_FIFO_DataOut => I2C9_FIFO_DataOut,
I2C9_FIFO_Empty => I2C9_FIFO_Empty,
I2C10_FIFO_ReadEn => I2C10_FIFO_ReadEn,
I2C10_FIFO_DataOut => I2C10_FIFO_DataOut,
I2C10_FIFO_Empty => I2C10_FIFO_Empty
);
end Behavioral;
|
gpl-3.0
|
0c3eb4de6264ddf17dcc2f6980c12d5d
| 0.628415 | 2.766022 | false | false | false | false |
IAIK/ascon_hardware
|
asconv1/ascon_small_64bit_datapath.vhdl
| 1 | 44,675 |
-------------------------------------------------------------------------------
-- Title : An area-optimized version of Ascon with a 64-bit datapath
-- Project : Ascon
-------------------------------------------------------------------------------
-- File : ascon_small_64bit_datapath.vhdl
-- Author : Erich Wenger <[email protected]>
-- Company : Graz University of Technology
-- Created : 2014-05-19
-- Last update: 2014-05-21
-- Platform : ASIC design
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-19 1.0 Erich Wenger Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon is
generic (
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic; -- active-high chip select
WExSI : in std_logic; -- active-high write enable
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity ascon;
architecture structural of ascon is
constant STATE_WORD_SIZE : integer := 64;
constant STATE_MACHINE_BITS : integer := 8;
constant ROUND_COUNTER_BITS : integer := 4;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
signal KeyxDP, KeyxDN : std_logic_vector(KEY_SIZE-1 downto 0);
signal IODataxDP, IODataxDN : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
signal State0xDP, State0xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State1xDP, State1xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State2xDP, State2xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State3xDP, State3xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal State4xDP, State4xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal Temp0xDP, Temp0xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal Temp1xDP, Temp1xDN : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal StatexDP : std_logic_vector(5*STATE_WORD_SIZE-1 downto 0);
signal StateMachinexDP, StateMachinexDN : std_logic_vector(STATE_MACHINE_BITS-1 downto 0);
signal RoundCounterxDP, RoundCounterxDN : std_logic_vector(ROUND_COUNTER_BITS-1 downto 0);
constant STATE_ROUND_OP : integer := 4;
constant STATE_AFTER_ROUND_OP : integer := STATE_ROUND_OP + 59;
signal DP_OpASelxS : std_logic_vector(3 downto 0);
signal DP_OpBSelxS : std_logic_vector(3 downto 0);
signal DP_OperationxS : std_logic_vector(3 downto 0);
signal DP_DestinationxS : std_logic_vector(3 downto 0);
signal DP_ALU_ResultxD : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant DP_OPERAND_SEL_ZERO : std_logic_vector(3 downto 0) := "0000";
constant DP_OPERAND_SEL_STATE0 : std_logic_vector(3 downto 0) := "1000";
constant DP_OPERAND_SEL_STATE1 : std_logic_vector(3 downto 0) := "1001";
constant DP_OPERAND_SEL_STATE2 : std_logic_vector(3 downto 0) := "1010";
constant DP_OPERAND_SEL_STATE3 : std_logic_vector(3 downto 0) := "1011";
constant DP_OPERAND_SEL_STATE4 : std_logic_vector(3 downto 0) := "1100";
constant DP_OPERAND_SEL_KEY0 : std_logic_vector(3 downto 0) := "1101";
constant DP_OPERAND_SEL_KEY1 : std_logic_vector(3 downto 0) := "1110";
constant DP_OPERAND_SEL_CONST_ONE : std_logic_vector(3 downto 0) := "0001";
constant DP_OPERAND_SEL_CONST_INIT : std_logic_vector(3 downto 0) := "0010";
constant DP_OPERAND_SEL_CONST_ROUND : std_logic_vector(3 downto 0) := "0011";
constant DP_OPERAND_SEL_IODATA : std_logic_vector(3 downto 0) := "0100";
constant DP_OPERAND_SEL_TEMP0 : std_logic_vector(3 downto 0) := "0110";
constant DP_OPERAND_SEL_TEMP1 : std_logic_vector(3 downto 0) := "0111";
constant DP_OPERATION_XOR : std_logic_vector(3 downto 0) := "0000";
constant DP_OPERATION_NOT_AND : std_logic_vector(3 downto 0) := "0001";
constant DP_OPERATION_NOT : std_logic_vector(3 downto 0) := "0010";
constant DP_OPERATION_BUS_LOW : std_logic_vector(3 downto 0) := "0100";
constant DP_OPERATION_BUS_HIGH : std_logic_vector(3 downto 0) := "0101";
constant DP_OPERATION_ROT1 : std_logic_vector(3 downto 0) := "1001";
constant DP_OPERATION_ROT2 : std_logic_vector(3 downto 0) := "1010";
constant DP_OPERATION_ROT4 : std_logic_vector(3 downto 0) := "1011";
constant DP_OPERATION_ROT8 : std_logic_vector(3 downto 0) := "1100";
constant DP_OPERATION_ROT16 : std_logic_vector(3 downto 0) := "1101";
constant DP_OPERATION_ROT32 : std_logic_vector(3 downto 0) := "1110";
constant DP_DESTINATION_NONE : std_logic_vector(3 downto 0) := "0000";
constant DP_DESTINATION_STATE0 : std_logic_vector(3 downto 0) := "1000";
constant DP_DESTINATION_STATE1 : std_logic_vector(3 downto 0) := "1001";
constant DP_DESTINATION_STATE2 : std_logic_vector(3 downto 0) := "1010";
constant DP_DESTINATION_STATE3 : std_logic_vector(3 downto 0) := "1011";
constant DP_DESTINATION_STATE4 : std_logic_vector(3 downto 0) := "1100";
constant DP_DESTINATION_IODATA : std_logic_vector(3 downto 0) := "0100";
constant DP_DESTINATION_TEMP0 : std_logic_vector(3 downto 0) := "0110";
constant DP_DESTINATION_TEMP1 : std_logic_vector(3 downto 0) := "0111";
signal CP_FinishedxS : std_logic;
signal CP_IdlexS : std_logic;
signal CP_CommandDirectxS : std_logic_vector(2 downto 0);
signal CP_CommandxSN, CP_CommandxSP : std_logic_vector(4 downto 0);
constant CP_DIRECT_NONE : std_logic_vector(2 downto 0) := "000";
constant CP_DIRECT_WR_IODATA0 : std_logic_vector(2 downto 0) := "010";
constant CP_DIRECT_WR_IODATA1 : std_logic_vector(2 downto 0) := "011";
constant CP_DIRECT_WR_NONCE0 : std_logic_vector(2 downto 0) := "100";
constant CP_DIRECT_WR_NONCE1 : std_logic_vector(2 downto 0) := "101";
constant CP_DIRECT_WR_NONCE2 : std_logic_vector(2 downto 0) := "110";
constant CP_DIRECT_WR_NONCE3 : std_logic_vector(2 downto 0) := "111";
constant CP_CMD_NONE : std_logic_vector(4 downto 0) := "00000";
constant CP_CMD_INIT : std_logic_vector(4 downto 0) := "00001";
constant CP_CMD_ASSOCIATE : std_logic_vector(4 downto 0) := "01000";
constant CP_CMD_ENCRYPT : std_logic_vector(4 downto 0) := "01001";
constant CP_CMD_DECRYPT : std_logic_vector(4 downto 0) := "01010";
constant CP_CMD_FINALIZE_ASSOCIATE : std_logic_vector(4 downto 0) := "01100";
constant CP_CMD_FINAL_ENCRYPT : std_logic_vector(4 downto 0) := "01101";
constant CP_CMD_FINAL_DECRYPT : std_logic_vector(4 downto 0) := "01110";
constant CP_CMD_RD_IODATA0 : std_logic_vector(4 downto 0) := "10110";
constant CP_CMD_RD_IODATA1 : std_logic_vector(4 downto 0) := "10111";
constant CP_CMD_RD_TAG0 : std_logic_vector(4 downto 0) := "11000";
constant CP_CMD_RD_TAG1 : std_logic_vector(4 downto 0) := "11001";
constant CP_CMD_RD_TAG2 : std_logic_vector(4 downto 0) := "11010";
constant CP_CMD_RD_TAG3 : std_logic_vector(4 downto 0) := "11011";
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
variable x : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- ROTATE_STATE_WORD
x := word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
return x;
end ROTATE_STATE_WORD;
begin -- architecture structural
StatexDP <= State4xDP & State3xDP & State2xDP & State1xDP & State0xDP;
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
KeyxDP <= (others => '0');
IODataxDP <= (others => '0');
State0xDP <= (others => '0');
State1xDP <= (others => '0');
State2xDP <= (others => '0');
State3xDP <= (others => '0');
State4xDP <= (others => '0');
StateMachinexDP <= (others => '0');
RoundCounterxDP <= (others => '0');
CP_CommandxSP <= (others => '0');
Temp0xDP <= (others => '0');
Temp1xDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
KeyxDP <= KeyxDN;
IODataxDP <= IODataxDN;
State0xDP <= State0xDN;
State1xDP <= State1xDN;
State2xDP <= State2xDN;
State3xDP <= State3xDN;
State4xDP <= State4xDN;
StateMachinexDP <= StateMachinexDN;
RoundCounterxDP <= RoundCounterxDN;
CP_CommandxSP <= CP_CommandxSN;
Temp0xDP <= Temp0xDN;
Temp1xDP <= Temp1xDN;
end if;
end process RegisterProc;
-- purpose: Glue the internal registers with the bus
-- type : combinational
DataBusLogicProc : process (AddressxDI, CP_CommandxSP, CP_FinishedxS,
CP_IdlexS, CSxSI, DP_ALU_ResultxD, DataWritexDI,
KeyxDP, WExSI) is
variable AddressxDV : integer;
variable index : integer;
begin -- process DataBusLogicProc
KeyxDN <= KeyxDP;
CP_CommandxSN <= CP_CommandxSP;
AddressxDV := to_integer(unsigned(AddressxDI));
index := 0;
DataReadxDO <= (others => '0');
if CP_FinishedxS = '1' then
CP_CommandxSN <= CP_CMD_NONE;
end if;
CP_CommandDirectxS <= CP_DIRECT_NONE;
-- TODO: only designed for DATA_BUS_WIDTH=32
if CSxSI = '1' then
if WExSI = '1' then
-- synchronous write
if AddressxDV = 2 then
-- command register
if DataWritexDI(0) = '1' then
CP_CommandxSN <= CP_CMD_INIT;
end if;
if DataWritexDI(1) = '1' then
CP_CommandxSN <= CP_CMD_ASSOCIATE;
end if;
if DataWritexDI(2) = '1' then
CP_CommandxSN <= CP_CMD_ENCRYPT;
end if;
if DataWritexDI(3) = '1' then
CP_CommandxSN <= CP_CMD_DECRYPT;
end if;
if DataWritexDI(4) = '1' then
CP_CommandxSN <= CP_CMD_FINAL_ENCRYPT;
end if;
if DataWritexDI(5) = '1' then
CP_CommandxSN <= CP_CMD_FINAL_DECRYPT;
end if;
if DataWritexDI(6) = '1' then
CP_CommandxSN <= CP_CMD_FINALIZE_ASSOCIATE;
end if;
elsif (AddressxDV >= 4) and (AddressxDV < 8) then
-- write the key
index := to_integer(unsigned(AddressxDI(1 downto 0)));
KeyxDN((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH) <= DataWritexDI;
elsif (AddressxDV >= 8) and (AddressxDV < 12) then
-- write the nonce
if AddressxDV = 8 then
CP_CommandDirectxS <= CP_DIRECT_WR_NONCE0;
elsif AddressxDV = 9 then
CP_CommandDirectxS <= CP_DIRECT_WR_NONCE1;
elsif AddressxDV = 10 then
CP_CommandDirectxS <= CP_DIRECT_WR_NONCE2;
elsif AddressxDV = 11 then
CP_CommandDirectxS <= CP_DIRECT_WR_NONCE3;
end if;
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- write the data to de/encrypt and associated data
if AddressxDV = 12 then
CP_CommandDirectxS <= CP_DIRECT_WR_IODATA0;
else
CP_CommandDirectxS <= CP_DIRECT_WR_IODATA1;
end if;
end if;
else
-- asynchronous read
if AddressxDV = 0 then
DataReadxDO <= x"deadbeef";
elsif AddressxDV = 1 then
-- status register
-- returns 1 if busy
DataReadxDO(0) <= not CP_IdlexS;
elsif (AddressxDV >= 12) and (AddressxDV < 20) then
if AddressxDV = 12 then
-- read the de/encrypted data and associated data
CP_CommandxSN <= CP_CMD_RD_IODATA0;
elsif AddressxDV = 13 then
CP_CommandxSN <= CP_CMD_RD_IODATA1;
elsif AddressxDV = 16 then
-- read the tag
CP_CommandxSN <= CP_CMD_RD_TAG0;
elsif AddressxDV = 17 then
CP_CommandxSN <= CP_CMD_RD_TAG1;
elsif AddressxDV = 18 then
CP_CommandxSN <= CP_CMD_RD_TAG2;
elsif AddressxDV = 19 then
CP_CommandxSN <= CP_CMD_RD_TAG3;
end if;
DataReadxDO <= DP_ALU_ResultxD(DATA_BUS_WIDTH-1 downto 0);
end if;
end if;
end if;
end process DataBusLogicProc;
-- purpose: Controlpath of Ascon
-- type : combinational
ControlProc : process (CP_CommandDirectxS, CP_CommandxSP, RoundCounterxDP,
StateMachinexDP) is
variable StateMachinexDV : integer;
variable RoundCounterxDV : integer;
begin -- process ControlProc
StateMachinexDN <= StateMachinexDP;
RoundCounterxDN <= RoundCounterxDP;
StateMachinexDV := to_integer(unsigned(StateMachinexDP));
RoundCounterxDV := to_integer(unsigned(RoundCounterxDP));
CP_IdlexS <= '0';
CP_FinishedxS <= '0';
DP_OpASelxS <= DP_OPERAND_SEL_ZERO;
DP_OpBSelxS <= DP_OPERAND_SEL_ZERO;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_NONE;
if CP_CommandxSP = CP_CMD_NONE then
StateMachinexDN <= (others => '0');
else
StateMachinexDN <= std_logic_vector(unsigned(StateMachinexDP) + 1);
end if;
if CP_CommandxSP = CP_CMD_NONE then
CP_IdlexS <= '1';
if CP_CommandDirectxS = CP_DIRECT_WR_NONCE0 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_BUS_LOW;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif CP_CommandDirectxS = CP_DIRECT_WR_NONCE1 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_BUS_HIGH;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif CP_CommandDirectxS = CP_DIRECT_WR_NONCE2 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_BUS_LOW;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif CP_CommandDirectxS = CP_DIRECT_WR_NONCE3 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_BUS_HIGH;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif CP_CommandDirectxS = CP_DIRECT_WR_IODATA0 then
DP_OpASelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_BUS_LOW;
DP_DestinationxS <= DP_DESTINATION_IODATA;
elsif CP_CommandDirectxS = CP_DIRECT_WR_IODATA1 then
DP_OpASelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_BUS_HIGH;
DP_DestinationxS <= DP_DESTINATION_IODATA;
end if;
---------------------------------------------------------------------------
elsif CP_CommandxSP = CP_CMD_RD_IODATA0 then
DP_OpASelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
StateMachinexDN <= (others => '0');
CP_FinishedxS <= '1';
elsif CP_CommandxSP = CP_CMD_RD_IODATA1 then
DP_OpASelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_ROT32;
StateMachinexDN <= (others => '0');
CP_FinishedxS <= '1';
elsif CP_CommandxSP = CP_CMD_RD_TAG0 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_XOR;
StateMachinexDN <= (others => '0');
CP_FinishedxS <= '1';
elsif CP_CommandxSP = CP_CMD_RD_TAG1 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_ROT32;
StateMachinexDN <= (others => '0');
CP_FinishedxS <= '1';
elsif CP_CommandxSP = CP_CMD_RD_TAG2 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_XOR;
StateMachinexDN <= (others => '0');
CP_FinishedxS <= '1';
elsif CP_CommandxSP = CP_CMD_RD_TAG3 then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_ROT32;
StateMachinexDN <= (others => '0');
CP_FinishedxS <= '1';
---------------------------------------------------------------------------
elsif CP_CommandxSP = CP_CMD_INIT then
if (StateMachinexDV = 0) then
DP_OpBSelxS <= DP_OPERAND_SEL_CONST_INIT;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = 1) then
DP_OpASelxS <= DP_OPERAND_SEL_KEY1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = 2) then
DP_OpASelxS <= DP_OPERAND_SEL_KEY0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
elsif (StateMachinexDV = STATE_AFTER_ROUND_OP + 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif (StateMachinexDV = STATE_AFTER_ROUND_OP + 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
CP_FinishedxS <= '1';
StateMachinexDN <= (others => '0');
end if;
elsif (CP_CommandxSP = CP_CMD_ASSOCIATE) then
if (StateMachinexDV = 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
end if;
elsif (CP_CommandxSP = CP_CMD_ENCRYPT) then
if (StateMachinexDV = 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_IODATA;
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
end if;
elsif (CP_CommandxSP = CP_CMD_FINALIZE_ASSOCIATE) then
if (StateMachinexDV = 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_CONST_ONE;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
CP_FinishedxS <= '1';
StateMachinexDN <= (others => '0');
end if;
elsif (CP_CommandxSP = CP_CMD_FINAL_ENCRYPT) then
if (StateMachinexDV = 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_IODATA;
elsif (StateMachinexDV = 2) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = 3) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
elsif (StateMachinexDV = STATE_AFTER_ROUND_OP + 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif (StateMachinexDV = STATE_AFTER_ROUND_OP + 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
CP_FinishedxS <= '1';
StateMachinexDN <= (others => '0');
end if;
elsif (CP_CommandxSP = CP_CMD_DECRYPT) then
if (StateMachinexDV = 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_IODATA;
elsif (StateMachinexDV = 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
end if;
elsif (CP_CommandxSP = CP_CMD_FINAL_DECRYPT) then
if (StateMachinexDV = 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_IODATA;
elsif (StateMachinexDV = 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_IODATA;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = 2) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = 3) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
elsif (StateMachinexDV = STATE_AFTER_ROUND_OP + 0) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif (StateMachinexDV = STATE_AFTER_ROUND_OP + 1) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_KEY0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
CP_FinishedxS <= '1';
StateMachinexDN <= (others => '0');
end if;
end if;
if (CP_CommandxSP = CP_CMD_INIT) or
(CP_CommandxSP = CP_CMD_ASSOCIATE) or
(CP_CommandxSP = CP_CMD_ENCRYPT) or
(CP_CommandxSP = CP_CMD_DECRYPT) or
(CP_CommandxSP = CP_CMD_FINAL_ENCRYPT) or
(CP_CommandxSP = CP_CMD_FINAL_DECRYPT) then
if (StateMachinexDV = STATE_ROUND_OP + 0) then
-- add the round constant
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_CONST_ROUND;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
elsif (StateMachinexDV = STATE_ROUND_OP + 1) then
-- perform the S-Box layer
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 2) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 3) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
elsif (StateMachinexDV = STATE_ROUND_OP + 4) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = STATE_ROUND_OP + 5) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = STATE_ROUND_OP + 6) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif (StateMachinexDV = STATE_ROUND_OP + 7) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif (StateMachinexDV = STATE_ROUND_OP + 8) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE1;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif (StateMachinexDV = STATE_ROUND_OP + 9) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif (StateMachinexDV = STATE_ROUND_OP + 10) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 11) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 12) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 13) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 14) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 15) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 16) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE1;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 17) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 18) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 19) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 20) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_NOT_AND;
DP_DestinationxS <= DP_DESTINATION_STATE2;
elsif (StateMachinexDV = STATE_ROUND_OP + 21) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = STATE_ROUND_OP + 22) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = STATE_ROUND_OP + 23) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = STATE_ROUND_OP + 24) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif (StateMachinexDV = STATE_ROUND_OP + 25) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_NOT;
DP_DestinationxS <= DP_DESTINATION_STATE2;
elsif (StateMachinexDV = STATE_ROUND_OP + 26) then
-- linear layer (State 0)
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OperationxS <= DP_OPERATION_ROT16;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 27) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT8;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 28) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_ROT4;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 29) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT2;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 30) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT1;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 31) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = STATE_ROUND_OP + 32) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE0;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE0;
elsif (StateMachinexDV = STATE_ROUND_OP + 33) then
-- linear layer (State 1)
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OperationxS <= DP_OPERATION_ROT32;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 34) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT1;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 35) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT4;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 36) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT16;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 37) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_ROT8;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 38) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT2;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 39) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = STATE_ROUND_OP + 40) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE1;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE1;
elsif (StateMachinexDV = STATE_ROUND_OP + 41) then
-- linear layer (State 2)
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_ROT1;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 42) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OperationxS <= DP_OPERATION_ROT2;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 43) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_ROT4;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 44) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
elsif (StateMachinexDV = STATE_ROUND_OP + 45) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE2;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE2;
elsif (StateMachinexDV = STATE_ROUND_OP + 46) then
-- linear layer (State 3)
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_ROT2;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 47) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT8;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 48) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OperationxS <= DP_OPERATION_ROT1;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 49) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_ROT16;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 50) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif (StateMachinexDV = STATE_ROUND_OP + 51) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE3;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE3;
elsif (StateMachinexDV = STATE_ROUND_OP + 52) then
-- linear layer (State 4)
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OperationxS <= DP_OPERATION_ROT1;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 53) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT8;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 54) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_ROT32;
DP_DestinationxS <= DP_DESTINATION_TEMP1;
elsif (StateMachinexDV = STATE_ROUND_OP + 55) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT2;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 56) then
DP_OpASelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_ROT4;
DP_DestinationxS <= DP_DESTINATION_TEMP0;
elsif (StateMachinexDV = STATE_ROUND_OP + 57) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP0;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
elsif (StateMachinexDV = STATE_ROUND_OP + 58) then
DP_OpASelxS <= DP_OPERAND_SEL_STATE4;
DP_OpBSelxS <= DP_OPERAND_SEL_TEMP1;
DP_OperationxS <= DP_OPERATION_XOR;
DP_DestinationxS <= DP_DESTINATION_STATE4;
if (CP_CommandxSP = CP_CMD_ENCRYPT) or
(CP_CommandxSP = CP_CMD_DECRYPT) or
(CP_CommandxSP = CP_CMD_ASSOCIATE) then
if RoundCounterxDV = ROUNDS_B-1 then
CP_FinishedxS <= '1';
StateMachinexDN <= (others => '0');
RoundCounterxDN <= (others => '0');
else
RoundCounterxDN <= std_logic_vector(unsigned(RoundCounterxDP) + 1);
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
end if;
end if;
if (CP_CommandxSP = CP_CMD_FINAL_ENCRYPT) or
(CP_CommandxSP = CP_CMD_FINAL_DECRYPT) or
(CP_CommandxSP = CP_CMD_INIT) then
if RoundCounterxDV = ROUNDS_A-1 then
RoundCounterxDN <= (others => '0');
else
RoundCounterxDN <= std_logic_vector(unsigned(RoundCounterxDP) + 1);
StateMachinexDN <= std_logic_vector(to_unsigned(STATE_ROUND_OP, STATE_MACHINE_BITS));
end if;
end if;
end if;
end if;
end process ControlProc;
-- purpose: Datapath of Ascon
-- type : combinational
DatapathProc : process (DP_DestinationxS, DP_OpASelxS, DP_OpBSelxS,
DP_OperationxS, DataWritexDI, IODataxDP, KeyxDP,
RoundCounterxDP, State0xDP, State1xDP, State2xDP,
State3xDP, State4xDP, Temp0xDP, Temp1xDP) is
variable OpAxDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable OpBxDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable ResxDV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- process DatapathProc
IODataxDN <= IODataxDP;
State0xDN <= State0xDP;
State1xDN <= State1xDP;
State2xDN <= State2xDP;
State3xDN <= State3xDP;
State4xDN <= State4xDP;
Temp0xDN <= Temp0xDP;
Temp1xDN <= Temp1xDP;
OpAxDV := (others => '0');
OpBxDV := (others => '0');
ResxDV := (others => '0');
case DP_OpASelxS is
when DP_OPERAND_SEL_STATE0 => OpAxDV := State0xDP;
when DP_OPERAND_SEL_STATE1 => OpAxDV := State1xDP;
when DP_OPERAND_SEL_STATE2 => OpAxDV := State2xDP;
when DP_OPERAND_SEL_STATE3 => OpAxDV := State3xDP;
when DP_OPERAND_SEL_STATE4 => OpAxDV := State4xDP;
when DP_OPERAND_SEL_KEY0 => OpAxDV := KeyxDP(63 downto 0);
when DP_OPERAND_SEL_KEY1 => OpAxDV := KeyxDP(127 downto 64);
when DP_OPERAND_SEL_CONST_INIT => OpAxDV := CONST_KEY_SIZE & CONST_ROUNDS_A & CONST_ROUNDS_B & ZEROS(64-3*8);
when DP_OPERAND_SEL_CONST_ROUND => OpAxDV := ZEROS(64-8) & not RoundCounterxDP(3 downto 0) & RoundCounterxDP(3 downto 0);
when DP_OPERAND_SEL_IODATA => OpAxDV := IODataxDP;
when DP_OPERAND_SEL_TEMP0 => OpAxDV := Temp0xDP;
when DP_OPERAND_SEL_TEMP1 => OpAxDV := Temp1xDP;
when others => null;
end case;
case DP_OpBSelxS is
when DP_OPERAND_SEL_STATE0 => OpBxDV := State0xDP;
when DP_OPERAND_SEL_STATE1 => OpBxDV := State1xDP;
when DP_OPERAND_SEL_STATE2 => OpBxDV := State2xDP;
when DP_OPERAND_SEL_STATE3 => OpBxDV := State3xDP;
when DP_OPERAND_SEL_STATE4 => OpBxDV := State4xDP;
when DP_OPERAND_SEL_KEY0 => OpBxDV := KeyxDP(63 downto 0);
when DP_OPERAND_SEL_KEY1 => OpBxDV := KeyxDP(127 downto 64);
when DP_OPERAND_SEL_CONST_INIT => OpBxDV := CONST_KEY_SIZE & CONST_ROUNDS_A & CONST_ROUNDS_B & ZEROS(64-3*8);
when DP_OPERAND_SEL_CONST_ROUND => OpBxDV := ZEROS(64-8) & not RoundCounterxDP(3 downto 0) & RoundCounterxDP(3 downto 0);
when DP_OPERAND_SEL_CONST_ONE => OpBxDV := std_logic_vector(to_unsigned(1, STATE_WORD_SIZE));
when DP_OPERAND_SEL_IODATA => OpBxDV := IODataxDP;
when DP_OPERAND_SEL_TEMP0 => OpBxDV := Temp0xDP;
when DP_OPERAND_SEL_TEMP1 => OpBxDV := Temp1xDP;
when others => null;
end case;
case DP_OperationxS is
when DP_OPERATION_XOR => ResxDV := OpAxDV xor OpBxDV;
when DP_OPERATION_NOT_AND => ResxDV := (not OpAxDV) and OpBxDV;
when DP_OPERATION_NOT => ResxDV := not OpAxDV;
when DP_OPERATION_BUS_LOW => ResxDV := OpAxDV(63 downto 32) & DataWritexDI;
when DP_OPERATION_BUS_HIGH => ResxDV := DataWritexDI & OpAxDV(31 downto 0);
when DP_OPERATION_ROT1 => ResxDV := ROTATE_STATE_WORD(OpAxDV, 1);
when DP_OPERATION_ROT2 => ResxDV := ROTATE_STATE_WORD(OpAxDV, 2);
when DP_OPERATION_ROT4 => ResxDV := ROTATE_STATE_WORD(OpAxDV, 4);
when DP_OPERATION_ROT8 => ResxDV := ROTATE_STATE_WORD(OpAxDV, 8);
when DP_OPERATION_ROT16 => ResxDV := ROTATE_STATE_WORD(OpAxDV, 16);
when DP_OPERATION_ROT32 => ResxDV := ROTATE_STATE_WORD(OpAxDV, 32);
when others => null;
end case;
DP_ALU_ResultxD <= ResxDV;
case DP_DestinationxS is
when DP_DESTINATION_STATE0 => State0xDN <= ResxDV;
when DP_DESTINATION_STATE1 => State1xDN <= ResxDV;
when DP_DESTINATION_STATE2 => State2xDN <= ResxDV;
when DP_DESTINATION_STATE3 => State3xDN <= ResxDV;
when DP_DESTINATION_STATE4 => State4xDN <= ResxDV;
when DP_DESTINATION_IODATA => IODataxDN <= ResxDV;
when DP_DESTINATION_TEMP0 => Temp0xDN <= ResxDV;
when DP_DESTINATION_TEMP1 => Temp1xDN <= ResxDV;
when others => null;
end case;
end process DatapathProc;
end architecture structural;
|
apache-2.0
|
3e09ec1483872b777b5c38835c917252
| 0.602932 | 3.760522 | false | false | false | false |
hoangt/PoC
|
src/mem/ocram/ocram_esdp.vhdl
| 2 | 7,572 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Enhanced simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating enhanced simple dual-port memory, with:
--
-- * dual clock, clock enable,
-- * 1 read/write port (1st port) plus 1 read port (2nd port).
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- * Same-Port Read-During Write:
-- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1')
-- is directly passed to the output "q1". This is also known as write-first
-- mode or read-through write behavior.
--
-- * Mixed-Port Read-During Write:
-- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix
-- and Stratix II FPGAs) defines the minimum time after which the written data
-- at port 1 can be read-out at port 2 again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d1" written at the rising-edge of "clk1" at address
-- "a1" can be read-out at the 2nd port from the same address with the
-- 2nd rising-edge of "clk2" following the falling-edge of "clk1".
-- If the rising-edge of "clk2" coincides with the falling-edge of "clk1"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "clk2" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_esdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_esdp;
architecture rtl of ocram_esdp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates extended simple dual-port
-- memory as expected.
-- RAM can be inferred correctly only for newer FPGAs!
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_esdp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_esdp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk1 => clk1,
clk2 => clk2,
ce1 => ce1,
ce2 => ce2,
we1 => we1,
a1 => a1,
a2 => a2,
d1 => d1,
q1 => q1,
q2 => q2
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
apache-2.0
|
f7530ccc0b688a10172f4421cbc2b86e
| 0.623745 | 3.127633 | false | false | false | false |
hoangt/PoC
|
src/arith/arith_same.vhdl
| 2 | 3,887 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: This module detects whether all bit positions of a std_logic_vector have the same value.
-- For detailed documentation see below.
--
-- Authors: Thomas B. Preusser
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
USE PoC.utils.ALL;
entity arith_same is
generic (
N : positive -- Input width
);
port (
g : in std_logic := '1'; -- Guard Input (!g => !y)
x : in std_logic_vector(N-1 downto 0); -- Input Vector
y : out std_logic -- All-same Output
);
end arith_same;
-- This module detects whether all bit positions of a std_logic_vector
-- have the same value.
--
-- This circuit may, for instance, be used to detect the first
-- sign change and, thus, the range of a two's complement
-- number.
--
-- These components may be chained by using the output of the
-- predecessor as guard input. This chaining allows to have
-- intermediate results available while still ensuring the use
-- of a fast carry chain on supporting FPGA architectures.
-- When chaining, make sure to overlap both vector slices
-- by one bit position as to avoid an undetected sign change
-- between the slices.
architecture rtl of arith_same is
constant K : positive := ARCH_PROPS.LUT_K; -- LUT Fanin
constant M : positive := (N-2+1/N)/(K-1) + 1; -- Required Stage Count
signal p : std_logic_vector(M-1 downto 0); -- Stage Propagates
begin
-- Compute Propagates in LUT Stages
genCC: for i in 0 to M-1 generate
-- Relevant Vector Slice
constant LO : natural := i *(K-1);
constant HI : natural := imin(N-1, (i+1)*(K-1));
begin
p(i) <= '1' when x(HI downto LO) = (HI downto LO => '0') else
'1' when x(HI downto LO) = (HI downto LO => '1') else
'0';
end generate;
-- Compute Equivalence in Carry Chain
genXLXn: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(M downto 0);
begin
-- Infere Carry Chain from Addition
s <= std_logic_vector(unsigned('0' & p) + (0 to 0 => g));
y <= s(M);
end generate genXLXn;
genXLXy: if VENDOR = VENDOR_XILINX generate
component inc_ovcy_xilinx is
generic (
N : positive -- Bit Width
);
port (
p : in std_logic_vector(N-1 downto 0); -- Argument
g : in std_logic; -- Increment Guard
v : out std_logic -- Overflow Output
);
end component;
begin
i: inc_ovcy_xilinx
generic map (
N => M
)
port map (
p => p,
g => g,
v => y
);
end generate genXLXy;
end rtl;
|
apache-2.0
|
fc28f9239caff5633c01bca2a18b482e
| 0.579002 | 3.765504 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/macaddrram.vhd
| 4 | 10,845 |
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : macaddram.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- There is a rom used in the MII to store the MAC address
--
-- Note that the two nibbles in each word of the MAC address
-- are transposed in order to transmit to the network in the
-- proper order.However, the generic value (MACAddr)of this
-- ROM keeps the normal order.
--
-- Representation of each word in this ROM (list with address order)
--
-- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec
-- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa
-- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef
-- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000
--
-- Uses 4 LUTs (4 rom16x1), 0 register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
--
-- MACAddr -- MAC Address
-- Filler -- Filler
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Addr -- Address
-- Dout -- Data output
-- Din -- Data input
-- We -- Write Enable
-- Clk -- Clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity MacAddrRAM is
generic
(MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa";
-- use the normal order
Filler : bit_vector(15 downto 0) := x"0000");
port(
Addr : in std_logic_vector (3 downto 0);
Dout : out std_logic_vector (3 downto 0);
Din : in std_logic_vector (3 downto 0);
We : in std_logic;
Clk : in std_logic
);
end MacAddrRAM;
architecture imp of MacAddrRAM is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
--component ram16x4
-- generic(
-- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0)
-- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4)
-- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8)
-- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12)
-- );
-- port(
-- Addr : in std_logic_vector(3 downto 0);
-- D : in std_logic_vector(3 downto 0);
-- We : in std_logic;
-- Clk : in std_logic;
-- Q : out std_logic_vector(3 downto 0));
--end component;
begin
ram16x4i: entity axi_ethernetlite_v3_0.ram16x4
generic map
(INIT_00 => netOrder(MACAddr(47 downto 32)),
INIT_01 => netOrder(MACAddr(31 downto 16)),
INIT_02 => netOrder(MACAddr(15 downto 0)),
INIT_03 => netOrder(Filler)
)
port map
(Addr => Addr,
D => Din,
Q => Dout,
We => We,
Clk => Clk
);
end imp;
|
gpl-3.0
|
9da06d5ab472bdf83d081d56aad7c26c
| 0.395758 | 5.067757 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/rx_statemachine.vhd
| 4 | 43,053 |
-------------------------------------------------------------------------------
-- rx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the receive control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- Rcv_en -- Receive enable
-- RxBusFifoRdAck -- RX FIFO read ack
-- BusFifoEmpty -- RX FIFO empty
-- Collision -- Collision detected
-- DataValid -- Data valid from PHY
-- RxError -- Receive error
-- BusFifoData -- RX FIFO data
-- CrcOk -- CRC correct in the receive data
-- BusFifoRd -- RX FIFO read
-- RxAbortRst -- Receive abort
-- RxCrcRst -- Receive CRC reset
-- RxCrcEn -- RX CRC enable
-- Rx_addr_en -- Receive address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_statemachine is
generic (
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port (
Clk : in std_logic;
Rst : in std_logic;
Emac_rx_rd_data_d1 : in std_logic_vector(0 to 5); -- 03-26-04
Receive_enable : out std_logic; -- 03-26-04
RxBusFifoRdAck : in std_logic;
BusFifoEmpty : in std_logic;
Collision : in std_logic;
DataValid : in std_logic;
RxError : in std_logic;
BusFifoData : in std_logic_vector(0 to 3);
CrcOk : in std_logic;
BusFifoRd : out std_logic;
RxAbortRst : out std_logic;
RxCrcRst : out std_logic;
RxCrcEn : out std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end rx_statemachine;
architecture imp of rx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
signal idle : std_logic; -- state 0
signal waitForSfd1 : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal waitForSfd2 : std_logic; -- state 3
signal startReadDestAdrNib : std_logic; -- state 4
signal rdDestAddrNib_eq_0 : std_logic;
signal rdDestAddrNib_eq_12 : std_logic;
signal startReadDataNib : std_logic; -- state 17
signal crcCheck : std_logic; -- state 18
signal rxDone : std_logic; -- state 20
signal receiveRst : std_logic; -- state 21
signal rxCollision : std_logic; -- state 22
signal idle_D : std_logic; -- state 0
signal waitForSfd1_D : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty_D : std_logic; -- state 2
signal waitForSfd2_D : std_logic; -- state 3
signal startReadDestAdrNib_D : std_logic; -- state 4
signal startReadDataNib_D : std_logic; -- state 17
signal crcCheck_D : std_logic; -- state 18
signal rxDone_D : std_logic; -- state 20
signal receiveRst_D : std_logic; -- state 21
signal rxCollision_D : std_logic; -- state 22
signal goto_idle_1 : std_logic; -- state 0
signal goto_idle_2 : std_logic; -- state 0
signal goto_idle_3 : std_logic; -- state 0
signal goto_idle_4 : std_logic; -- state 0
signal goto_waitForSfd1 : std_logic; -- state 1
signal goto_sfd1CheckBusFifoEmpty_1 : std_logic; -- state 2
signal goto_sfd1CheckBusFifoEmpty_2 : std_logic; -- state 2
signal goto_waitForSfd2 : std_logic; -- state 3
signal goto_startReadDestAdrNib_1 : std_logic; -- state 4
signal goto_readDestAdrNib1 : std_logic; -- state 5
signal goto_startReadDataNib_2 : std_logic; -- state 17
signal goto_crcCheck : std_logic; -- state 18
signal goto_rxDone_3 : std_logic; -- state 20
signal goto_receiveRst_1 : std_logic; -- state 21
signal goto_receiveRst_2 : std_logic; -- state 21
signal goto_receiveRst_3 : std_logic; -- state 21
signal goto_receiveRst_5 : std_logic; -- state 21
signal goto_receiveRst_9 : std_logic; -- state 21
signal goto_receiveRst_10 : std_logic; -- state 21
signal goto_receiveRst_14 : std_logic; -- state 21
signal goto_rxCollision_1 : std_logic; -- state 22
signal goto_rxCollision_2 : std_logic; -- state 22
signal goto_rxCollision_5 : std_logic; -- state 22
signal stay_idle : std_logic; -- state 0
signal stay_sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal stay_startReadDestAdrNib : std_logic; -- state 4
signal stay_startReadDataNib : std_logic; -- state 17
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal checkingBroadcastAdr_i : std_logic;
signal checkingBroadcastAdr_reg : std_logic;
signal busFifoData_is_5 : std_logic;
signal busFifoData_is_13 : std_logic;
signal busFifoData_not_5 : std_logic;
signal busFifoData_not_13 : std_logic;
signal bcastAddrGood : std_logic;
signal ucastAddrGood : std_logic;
signal crcokr1 : std_logic;
signal crcokin : std_logic;
signal rxCrcEn_i : std_logic;
signal mac_addr_ram_addr_rd_D : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t_q : std_logic_vector(0 to 3);
signal rxDone_i : std_logic;
signal preamble_valid : std_logic;
signal preamble_error_reg : std_logic;
signal preamble_error : std_logic;
signal busFifoData_is_5_d1 : std_logic;
signal busFifoData_is_5_d2 : std_logic;
signal busFifoData_is_5_d3 : std_logic;
signal pkt_length_cnt : integer range 0 to 127;
signal crc_rst : std_logic;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- CRC check
----------------------------------------------------------------------------
crcokin <= ((CrcOk -- set
or crcokr1) -- keep
and (not(rxCrcEn_i) or CrcOk)); -- clear when 0
crcokdelay: FDR
port map (
Q => crcokr1, --[out]
C => Clk, --[in]
D => crcokin, --[in]
R => crc_rst --[in]
);
-- Added this to reset CRCokr1 before starting the next packet reception.
crc_rst <= Rst or (not CrcOk and crcokr1);
-- RX Complete indicator
Rx_done <= rxDone_i; -- added Rx_done output for ping pong control
-- Generate rxdone only if received framelength is greater than minimum
-- frame length
rxDone_i <= '1' when rxDone='1' and pkt_length_cnt=0 else
'0';
-- Check start of Frame
-- If receive data=5
busFifoData_is_5 <= not(BusFifoData(0)) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=5
busFifoData_not_5 <= not(busFifoData_is_5);
-- If receive data=13
busFifoData_is_13 <= BusFifoData(0) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=13
busFifoData_not_13 <= not(busFifoData_is_13);
-- State Machine Reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle_1 <= rxDone;
goto_idle_2 <= receiveRst;
goto_idle_3 <= waitForSfd1 and (not(DataValid) or busFifoData_not_5);
goto_idle_4 <= waitForSfd2 and (not(DataValid) or
(busFifoData_not_5 and busFifoData_not_13));
stay_idle <= idle and not(goto_waitForSfd1);
idle_D <= goto_idle_1 or goto_idle_2 or goto_idle_3 or goto_idle_4
or stay_idle;
state0a: FDS
port map (
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd1 state
----------------------------------------------------------------------------
goto_waitForSfd1 <= idle and (RxBusFifoRdAck or not(BusFifoEmpty))
and (Rx_buffer_ready);
waitForSfd1_D <= goto_waitForSfd1;
state1a: FDR
port map (
Q => waitForSfd1, --[out]
C => Clk, --[in]
D => waitForSfd1_D, --[in]
R => state_machine_rst --[in]
);
Rx_idle <= idle or waitForSfd1;
----------------------------------------------------------------------------
-- sfd1CheckBusFifoEmpty state
----------------------------------------------------------------------------
goto_sfd1CheckBusFifoEmpty_1 <= waitForSfd1 and busFifoData_is_5
and DataValid;
goto_sfd1CheckBusFifoEmpty_2 <= waitForSfd2 and busFifoData_is_5
and DataValid;
stay_sfd1CheckBusFifoEmpty <= sfd1CheckBusFifoEmpty and
not(goto_rxCollision_1) and
not(goto_receiveRst_1) and
not(goto_waitForSfd2);
sfd1CheckBusFifoEmpty_D <= goto_sfd1CheckBusFifoEmpty_1 or
goto_sfd1CheckBusFifoEmpty_2 or
stay_sfd1CheckBusFifoEmpty;
state2a: FDR
port map (
Q => sfd1CheckBusFifoEmpty, --[out]
C => Clk, --[in]
D => sfd1CheckBusFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd2 state
----------------------------------------------------------------------------
goto_waitForSfd2 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1) and
not(goto_receiveRst_1) and (RxBusFifoRdAck or
not(BusFifoEmpty)) and
busFifoData_is_5;
waitForSfd2_D <= goto_waitForSfd2;
state3a: FDR
port map (
Q => waitForSfd2, --[out]
C => Clk, --[in]
D => waitForSfd2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--startReadDestAdrNib state
----------------------------------------------------------------------------
goto_startReadDestAdrNib_1 <= waitForSfd2 and busFifoData_is_13
and preamble_valid
and DataValid;
stay_startReadDestAdrNib <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
not(goto_readDestAdrNib1);
startReadDestAdrNib_D <= goto_startReadDestAdrNib_1 or
stay_startReadDestAdrNib;
state4a: FDR
port map (
Q => startReadDestAdrNib, --[out]
C => Clk, --[in]
D => startReadDestAdrNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--readDestAdrNib1 state
----------------------------------------------------------------------------
goto_readDestAdrNib1 <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
RxBusFifoRdAck;
rdDestAddrNib_eq_0 <= bo2sl(rdDestAddrNib_D_t_q = "0000");
rdDestAddrNib_eq_12 <= bo2sl(rdDestAddrNib_D_t_q = "1011");
----------------------------------------------------------------------------
-- STATE_REG_PROCESS
----------------------------------------------------------------------------
-- Registeting the read destination address.
----------------------------------------------------------------------------
STATE_REG_PROCESS : process (Clk)
begin
if (Clk'event and Clk='1') then
if (state_machine_rst = '1' or
goto_startReadDestAdrNib_1 = '1') then
rdDestAddrNib_D_t_q <= "0000";
else
rdDestAddrNib_D_t_q <= rdDestAddrNib_D_t;
end if;
end if;
end process STATE_REG_PROCESS;
----------------------------------------------------------------------------
-- FSM_CMB_PROCESS
----------------------------------------------------------------------------
-- This process generate read destination address for the MAC address RAM
-- for the received frame.
----------------------------------------------------------------------------
FSM_CMB_PROCESS : process (startReadDestAdrNib,goto_rxCollision_2,
goto_receiveRst_2,RxBusFifoRdAck,goto_receiveRst_3,bcastAddrGood,
ucastAddrGood,goto_receiveRst_5,
rdDestAddrNib_D_t_q)
begin
----
rdDestAddrNib_D_t <= rdDestAddrNib_D_t_q;
case (rdDestAddrNib_D_t_q) is
when "0000" =>
if (startReadDestAdrNib and not(goto_rxCollision_2) and
not(goto_receiveRst_2) and RxBusFifoRdAck) = '1' then
rdDestAddrNib_D_t <= "0001";
else
rdDestAddrNib_D_t <= "0000";
end if;
when "0001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0001";
end if;
when "0010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0010";
end if;
when "0011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0011";
end if;
when "0100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0101";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0100";
end if;
when "0101" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0110";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0101";
end if;
when "0110" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0111";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0110";
end if;
when "0111" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0111";
end if;
when "1000" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1001";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1000";
end if;
when "1001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1001";
end if;
when "1010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1010";
end if;
when "1011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1011";
end if;
when "1100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1100";
end if;
when others => null;
end case;
end process FSM_CMB_PROCESS;
----------------------------------------------------------------------------
--startReadDataNib state
----------------------------------------------------------------------------
goto_startReadDataNib_2 <= rdDestAddrNib_eq_12 and RxBusFifoRdAck and
(bcastAddrGood or ucastAddrGood) and not(goto_receiveRst_5) and
not(goto_receiveRst_3);
stay_startReadDataNib <= startReadDataNib and not(goto_rxCollision_5)
and not(goto_receiveRst_9) and DataValid;
startReadDataNib_D <= goto_startReadDataNib_2
or stay_startReadDataNib;
state17a: FDR
port map (
Q => startReadDataNib, --[out]
C => Clk, --[in]
D => startReadDataNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--crcCheck state
----------------------------------------------------------------------------
goto_crcCheck <= startReadDataNib and not(DataValid) ;
goto_receiveRst_1 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1)
and RxError;
goto_receiveRst_2 <= startReadDestAdrNib and not(goto_rxCollision_2)
and RxError;
goto_receiveRst_9 <= startReadDataNib and not(goto_rxCollision_5)
and RxError;
crcCheck_D <= goto_crcCheck or goto_receiveRst_1 or
goto_receiveRst_2 or
goto_receiveRst_9;
state18a: FDR
port map (
Q => crcCheck, --[out]
C => Clk, --[in]
D => crcCheck_D, --[in]
R => state_machine_rst --[in]
);
-------------------------------------------------------------------------------
--rxDone state
-------------------------------------------------------------------------------
--goto_rxDone_3 <= writeFinalData ;
goto_rxDone_3 <= crcCheck and crcokr1;
rxDone_D <= goto_rxDone_3 ;
state20a: FDR
port map (
Q => rxDone, --[out]
C => Clk, --[in]
D => rxDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--rxCollision state
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
goto_rxCollision_1 <= sfd1CheckBusFifoEmpty and Collision
and not(full_half_n);
goto_rxCollision_2 <= startReadDestAdrNib and Collision
and not(full_half_n);
goto_rxCollision_5 <= startReadDataNib and Collision
and not(full_half_n);
rxCollision_D <= goto_rxCollision_1 or goto_rxCollision_2 or
goto_rxCollision_5;
state21a: FDR
port map (
Q => rxCollision, --[out]
C => Clk, --[in]
D => rxCollision_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--receiveRst state
----------------------------------------------------------------------------
goto_receiveRst_3 <= not rdDestAddrNib_eq_0 and not(DataValid);
goto_receiveRst_5 <= not rdDestAddrNib_eq_0 and
not(BusFifoEmpty) and
not(bcastAddrGood or ucastAddrGood);
goto_receiveRst_10<= crcCheck and not(crcokr1);
goto_receiveRst_14<= rxCollision;
receiveRst_D <= goto_receiveRst_3 or
goto_receiveRst_5 or
goto_receiveRst_10 or
goto_receiveRst_14 or
preamble_error_reg;
state22a: FDR
port map (
Q => receiveRst, --[out]
C => Clk, --[in]
D => receiveRst_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- BROADCAST_ADDR_REG
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
BROADCAST_ADDR_REG : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
checkingBroadcastAdr_reg <= '0';
else
checkingBroadcastAdr_reg <= checkingBroadcastAdr_i;
end if;
end if;
end process BROADCAST_ADDR_REG;
----------------------------------------------------------------------------
-- RX_FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
RX_FSMD_PROCESS : process( DataValid,RxBusFifoRdAck,idle,
startReadDestAdrNib, startReadDataNib,
sfd1CheckBusFifoEmpty, rxDone, receiveRst,
waitForSfd2, Emac_rx_rd_data_d1,
checkingBroadcastAdr_reg, rdDestAddrNib_eq_0,
rdDestAddrNib_D_t_q)
begin
-- Reset RX CRC in idle state
if (idle = '1') then
RxCrcRst <= '1';
else
RxCrcRst <= '0';
end if;
-- RX CRC enable
if ((( startReadDestAdrNib or (not rdDestAddrNib_eq_0) or
(startReadDataNib and DataValid))
and RxBusFifoRdAck) = '1') then
RxCrcEn <= '1';
rxCrcEn_i <= '1';
else
RxCrcEn <= '0';
rxCrcEn_i <= '0';
end if;
-- RX buffer FIFO read enable
if ((idle = '1') or
(sfd1CheckBusFifoEmpty = '1') or
(not rdDestAddrNib_eq_0 = '1') or
(rxDone = '1') or -- 03-26-04
(startReadDestAdrNib = '1') or
(startReadDataNib = '1')) and (RxBusFifoRdAck = '0')then
BusFifoRd <= '1';
else
BusFifoRd <= '0';
end if;
-- RX abort reset
if (receiveRst = '1') then
RxAbortRst <= '1';
else
RxAbortRst <= '0';
end if;
-- RX buffer address enable
if RxBusFifoRdAck = '1' and
(
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) then
Rx_addr_en <= '1'; --enable address increment
else
Rx_addr_en <= '0';
end if;
-- Generate RX start after SFD is detected
if (waitForSfd2 = '1')then
Rx_start <= '1'; -- reset address to 0 for start of receive
else
Rx_start <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') or
((
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) and (RxBusFifoRdAck = '1')
) then
Rx_DPM_ce <= '1';
else
Rx_DPM_ce <= '0';
end if;
-- RX buffer read/write enable
if (startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1') then
Rx_DPM_wr_rd_n <= '1';
else
Rx_DPM_wr_rd_n <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') then
checkingBroadcastAdr_i <= '0'; -- reset
-- 06-09-04 Use delayed data for compare
elsif (rdDestAddrNib_D_t_q = x"1" and
Emac_rx_rd_data_d1(0 to 3) = x"f") then
checkingBroadcastAdr_i <= '1'; -- set
else
checkingBroadcastAdr_i <= checkingBroadcastAdr_reg; -- stay the same
end if;
end process RX_FSMD_PROCESS;
-- write data to Receive DPRAM
Rx_DPM_wr_data <= BusFifoData;
----------------------------------------------------------------------------
-- MARAR_PROC
----------------------------------------------------------------------------
-- This process generate MAC RAM address to get mac addres to compare with
-- incoming frame destination address
----------------------------------------------------------------------------
MARAR_PROC : process (rdDestAddrNib_D_t, idle_D, startReadDestAdrNib_D)
begin
case rdDestAddrNib_D_t is
when "0001" => mac_addr_ram_addr_rd_D <= x"0";
when "0010" => mac_addr_ram_addr_rd_D <= x"1";
when "0011" => mac_addr_ram_addr_rd_D <= x"2";
when "0100" => mac_addr_ram_addr_rd_D <= x"3";
when "0101" => mac_addr_ram_addr_rd_D <= x"4";
when "0110" => mac_addr_ram_addr_rd_D <= x"5";
when "0111" => mac_addr_ram_addr_rd_D <= x"6";
when "1000" => mac_addr_ram_addr_rd_D <= x"7";
when "1001" => mac_addr_ram_addr_rd_D <= x"8";
when "1010" => mac_addr_ram_addr_rd_D <= x"9";
when "1011" => mac_addr_ram_addr_rd_D <= x"a";
when "1100" => mac_addr_ram_addr_rd_D <= x"b";
when others => mac_addr_ram_addr_rd_D <= x"0";
end case;
-- Reset the address in idle or start of new frame
if (idle_D or startReadDestAdrNib_D) = '1' then
mac_addr_ram_addr_rd_D <= x"0";
end if;
end process MARAR_PROC;
----------------------------------------------------------------------------
-- OUTPUT_REG
----------------------------------------------------------------------------
-- Registerit the mac_addr_ram_addr_rd
----------------------------------------------------------------------------
OUTPUT_REG:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Mac_addr_ram_addr_rd <= (others => '0');
else
Mac_addr_ram_addr_rd <= mac_addr_ram_addr_rd_D;
end if;
end if;
end process OUTPUT_REG;
----------------------------------------------------------------------------
-- Check if the incoming packet is broadcast packet
----------------------------------------------------------------------------
bcastAddrGood <= '1' when checkingBroadcastAdr_i = '1' and
Emac_rx_rd_data_d1(0 to 3) = x"F" else -- 03-26-04
'0';
----------------------------------------------------------------------------
-- Check if the incoming packet is unicast and address matches to core
-- MAC address
----------------------------------------------------------------------------
ucastAddrGood <= '1' when checkingBroadcastAdr_i = '0' and
(Emac_rx_rd_data_d1(0 to 3) = Mac_addr_ram_data)
else -- 03-26-04
'0';
-- Genarate Receive enable
Receive_enable <= not(crcCheck or rxDone or receiveRst);
----------------------------------------------------------------------------
-- PROCESS : PKT_LENGTH_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_LENGTH_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' or preamble_error_reg = '1' ) then
pkt_length_cnt <= 0;
elsif goto_readDestAdrNib1 = '1' then -- load the counter for
pkt_length_cnt <= 127; -- minimum packet length
elsif (rxCrcEn_i='1') then -- Enable Down Counter
if (pkt_length_cnt = 0) then
pkt_length_cnt <= 0;
else
pkt_length_cnt <= pkt_length_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : SFD_CHECK_REG
----------------------------------------------------------------------------
-- This process registers the preamble nibble to checl if atleast last 2
-- preamble nibbles are valid before the SFD nibble.
----------------------------------------------------------------------------
SFD_CHECK_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
busFifoData_is_5_d1 <= '0';
busFifoData_is_5_d2 <= '0';
busFifoData_is_5_d3 <= '0';
elsif RxBusFifoRdAck = '1' then
busFifoData_is_5_d1 <= busFifoData_is_5;
busFifoData_is_5_d2 <= busFifoData_is_5_d1;
busFifoData_is_5_d3 <= busFifoData_is_5_d2;
end if;
end if;
end process;
preamble: FDR
port map (
Q => preamble_error_reg, --[out]
C => Clk, --[in]
D => preamble_error, --[in]
R => state_machine_rst --[in]
);
-- Premable valid
preamble_valid <= (busFifoData_is_5_d1) and
busFifoData_is_13;
-- Premable Error
preamble_error <= (not busFifoData_is_5 and
busFifoData_is_5_d1 and
not busFifoData_is_13) and waitForSfd2 ;
end imp;
|
gpl-3.0
|
4fffc0b96bc1f24fced7cf5ccc1e31b3
| 0.428727 | 4.879633 | false | false | false | false |
lowRISC/greth-library
|
greth_library/work/tb/rocket_soc_tb.vhd
| 2 | 8,828 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Testbench file for the SoC top-level impleemntation
------------------------------------------------------------------------------
--! @details File was automatically generated by C++ simulation software
------------------------------------------------------------------------------
--! @warning
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library commonlib;
use commonlib.types_util.all;
library rocketlib;
--use rocketlib.types_rocket.all;
entity rocket_soc_tb is
constant INCR_TIME : time := 3571 ps;--100 ns;--3571 ps;
end rocket_soc_tb;
architecture behavior of rocket_soc_tb is
constant EDCL_START_CLK : integer := 1000;
constant EDCL_WRITE_LEN : integer := 178;
constant EDCL_WRITE : std_logic_vector(EDCL_WRITE_LEN*4-1 downto 0) :=
X"5d207098001032badcacefebeb800000e300450000000029bf11000c8a00a00c8a00f07788556600a2ab86000000200100014000000000deef1000deef2000deef3000deef4000deef5000deef6000deef7000deef9701d69f";
constant EDCL_START_CLK2 : integer := 1500;
constant EDCL_START_CLK3 : integer := 15000;
constant EDCL_WR_MRESET_LEN : integer := 130;
-- write 1 to mreset reg:
constant EDCL_WR_MRESET1 : std_logic_vector(4*EDCL_WR_MRESET_LEN-1 downto 0):=
-- idx = 1
--X"5d207098001032badcacefebeb80000062004500000000293e11000c8a00a00c8a00f07788556600219673000000604000088087021000000000000000134d4ae5";
-- edcl_idx = 0
X"5d207098001032badcacefebeb80000062004500000000293e11000c8a00a00c8a00f077885566002196b3000000204000088087021000000000000000531a1143";
-- write 0 to mreset reg:
constant EDCL_WR_MRESET0 : std_logic_vector(4*EDCL_WR_MRESET_LEN-1 downto 0):=
X"5d207098001032badcacefebeb80000062004500000000293e11000c8a00a00c8a00f0778855660021a67300000060400008808702000000000000000056997ad3";
-- input/output signals:
signal i_rst : std_logic := '1';
signal i_sclk_p : std_logic;
signal i_sclk_n : std_logic;
signal i_clk_adc : std_logic := '0';
signal i_int_clkrf : std_logic;
signal i_dip : std_logic_vector(3 downto 1);
signal o_led : std_logic_vector(7 downto 0);
signal i_uart1_ctsn : std_logic := '0';
signal i_uart1_rd : std_logic := '1';
signal o_uart1_td : std_logic;
signal o_uart1_rtsn : std_logic;
signal i_gps_ld : std_logic := '0';--'1';
signal i_glo_ld : std_logic := '0';--'1';
signal o_max_sclk : std_logic;
signal o_max_sdata : std_logic;
signal o_max_ncs : std_logic_vector(1 downto 0);
signal i_antext_stat : std_logic := '0';
signal i_antext_detect : std_logic := '0';
signal o_antext_ena : std_logic;
signal o_antint_contr : std_logic;
signal o_emdc : std_logic;
signal io_emdio : std_logic;
signal i_rxd : std_logic_vector(3 downto 0) := "0000";
signal i_rxdv : std_logic := '0';
signal o_txd : std_logic_vector(3 downto 0);
signal o_txdv : std_logic;
signal adc_cnt : integer := 0;
signal clk_cur: std_logic := '1';
signal check_clk_bus : std_logic := '0';
signal iClkCnt : integer := 0;
signal iErrCnt : integer := 0;
signal iErrCheckedCnt : integer := 0;
signal iEdclCnt : integer := 0;
component rocket_soc is port
(
i_rst : in std_logic; -- button "Center"
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
i_clk_adc : in std_logic;
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
o_led : out std_logic_vector(7 downto 0);
-- uart1
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
-- ADC samples
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
-- rf front-end
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
end component;
begin
-- Process of reading
procReadingFile : process
variable clk_next: std_logic;
begin
wait for INCR_TIME;
if (adc_cnt + 26000000) >= 70000000 then
adc_cnt <= (adc_cnt + 26000000) - 70000000;
i_clk_adc <= not i_clk_adc;
else
adc_cnt <= (adc_cnt + 26000000);
end if;
while true loop
clk_next := not clk_cur;
if (clk_next = '1' and clk_cur = '0') then
check_clk_bus <= '1';
elsif (clk_next = '0' and clk_cur = '1') then
if iClkCnt >= EDCL_START_CLK and iClkCnt < (EDCL_START_CLK + EDCL_WRITE_LEN) then
i_rxd <= EDCL_WRITE(4*(EDCL_WRITE_LEN - (iClkCnt-EDCL_START_CLK))-1 downto 4*(EDCL_WRITE_LEN - (iClkCnt-EDCL_START_CLK))-4);
--i_rxdv <= '1';
elsif iClkCnt >= EDCL_START_CLK2 and iClkCnt < (EDCL_START_CLK2 + EDCL_WR_MRESET_LEN) then
i_rxd <= EDCL_WR_MRESET1(4*(EDCL_WR_MRESET_LEN - (iClkCnt-EDCL_START_CLK2))-1 downto 4*(EDCL_WR_MRESET_LEN - (iClkCnt-EDCL_START_CLK2))-4);
i_rxdv <= '1'; -- RESET CPU
elsif iClkCnt >= EDCL_START_CLK3 and iClkCnt < (EDCL_START_CLK3 + EDCL_WR_MRESET_LEN) then
i_rxd <= EDCL_WR_MRESET0(4*(EDCL_WR_MRESET_LEN - (iClkCnt-EDCL_START_CLK3))-1 downto 4*(EDCL_WR_MRESET_LEN - (iClkCnt-EDCL_START_CLK3))-4);
i_rxdv <= '1'; -- RESET CPU
else
i_rxd <= "0000";
i_rxdv <= '0';
end if;
end if;
wait for 1 ps;
check_clk_bus <= '0';
clk_cur <= clk_next;
wait for INCR_TIME;
if clk_cur = '1' then
iClkCnt <= iClkCnt + 1;
end if;
if (adc_cnt + 26000000) >= 70000000 then
adc_cnt <= (adc_cnt + 26000000) - 70000000;
i_clk_adc <= not i_clk_adc;
else
adc_cnt <= (adc_cnt + 26000000);
end if;
end loop;
report "Total clocks checked: " & tost(iErrCheckedCnt) & " Errors: " & tost(iErrCnt);
wait for 1 sec;
end process procReadingFile;
i_sclk_p <= clk_cur;
i_sclk_n <= not clk_cur;
procSignal : process (i_sclk_p, iClkCnt)
begin
if rising_edge(i_sclk_p) then
--! @note to make sync. reset of the logic that are clocked by
--! htif_clk which is clock/512 by default.
if iClkCnt = 15 then
i_rst <= '0';
end if;
end if;
end process procSignal;
i_dip <= "000";
i_int_clkrf <= '1';
-- signal parsment and assignment
tt : rocket_soc port map
(
i_rst => i_rst,
i_sclk_p => i_sclk_p,
i_sclk_n => i_sclk_n,
i_clk_adc => '0',--i_clk_adc,
i_int_clkrf => i_int_clkrf,
i_dip => i_dip,
o_led => o_led,
i_uart1_ctsn => i_uart1_ctsn,
i_uart1_rd => i_uart1_rd,
o_uart1_td => o_uart1_td,
o_uart1_rtsn => o_uart1_rtsn,
i_gps_I => "01",
i_gps_Q => "11",
i_glo_I => "11",
i_glo_Q => "01",
i_gps_ld => i_gps_ld,
i_glo_ld => i_glo_ld,
o_max_sclk => o_max_sclk,
o_max_sdata => o_max_sdata,
o_max_ncs => o_max_ncs,
i_antext_stat => i_antext_stat,
i_antext_detect => i_antext_detect,
o_antext_ena => o_antext_ena,
o_antint_contr => o_antint_contr,
i_gmiiclk_p => '0',
i_gmiiclk_n => '1',
o_egtx_clk => open,
i_etx_clk => i_sclk_p,
i_erx_clk => i_sclk_p,
i_erxd => i_rxd,
i_erx_dv => i_rxdv,
i_erx_er => '0',
i_erx_col => '0',
i_erx_crs => '0',
i_emdint => '0',
o_etxd => o_txd,
o_etx_en => o_txdv,
o_etx_er => open,
o_emdc => o_emdc,
io_emdio => io_emdio,
o_erstn => open
);
procCheck : process (i_rst, check_clk_bus)
begin
if rising_edge(check_clk_bus) then
if i_rst = '0' then
iErrCheckedCnt <= iErrCheckedCnt + 1;
end if;
end if;
end process procCheck;
end;
|
bsd-2-clause
|
4e54d8d29300b96ef210e01d9640b5e5
| 0.585523 | 2.949549 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl_hs/AEAD_Arch.vhd
| 1 | 8,748 |
-------------------------------------------------------------------------------
--! @file AEAD_Arch.vhd
--! @brief Architecture of authenticated encryption unit.
--! Note: This file should not be modified by a user.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
-------------------------------------------------------------------------------
--! @brief Architecture definition of AEAD
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant LBS_BYTES : integer := log2_ceil(G_DBLK_SIZE/8);
--! Signals from input processor
signal key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal bdi : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal key_valid : std_logic;
signal key_ready : std_logic;
signal key_update : std_logic;
signal decrypt : std_logic;
signal bdi_valid : std_logic;
signal bdi_ready : std_logic;
signal bdi_partial : std_logic;
signal bdi_eot : std_logic;
signal bdi_eoi : std_logic;
signal bdi_type : std_logic_vector(3 -1 downto 0);
signal bdi_size : std_logic_vector(LBS_BYTES+1 -1 downto 0);
signal bdi_valid_bytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal bdi_pad_loc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! Signals to output processor
signal bdo_ready : std_logic;
signal bdo_valid : std_logic;
signal bdo : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal bdo_size : std_logic_vector(LBS_BYTES+1 -1 downto 0);
signal msg_auth_done : std_logic;
signal msg_auth_valid : std_logic;
--! FIFO
signal cmd_din : std_logic_vector(24 -1 downto 0);
signal cmd_dout : std_logic_vector(24 -1 downto 0);
signal cmd_rd_ready : std_logic;
signal cmd_wr_ready : std_logic;
signal cmd_wr_valid : std_logic;
signal cmd_rd_valid : std_logic;
begin
u_input:
entity work.PreProcessor(structure)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_ENABLE_PAD => G_ENABLE_PAD ,
G_CIPH_EXP => G_CIPH_EXP ,
G_REVERSE_CIPH => G_REVERSE_CIPH ,
G_MERGE_TAG => G_MERGE_TAG ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_LBS_BYTES => LBS_BYTES ,
G_PAD_STYLE => G_PAD_STYLE ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! External
pdi_data => pdi_data ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi_data => sdi_data ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
--! CipherCore (Data)
bdi => bdi ,
key => key ,
--! CipherCore (Control)
key_valid => key_valid ,
key_ready => key_ready ,
key_update => key_update ,
decrypt => decrypt ,
bdi_ready => bdi_ready ,
bdi_valid => bdi_valid ,
bdi_type => bdi_type ,
bdi_partial => bdi_partial ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! cmd FIFO
cmd => cmd_din ,
cmd_ready => cmd_wr_ready ,
cmd_valid => cmd_wr_valid
);
u_cc:
entity work.CipherCore(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_LBS_BYTES => LBS_BYTES
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! PreProcessor (data)
key => key ,
bdi => bdi ,
--! PreProcessor (controls)
key_valid => key_valid ,
key_ready => key_ready ,
key_update => key_update ,
decrypt => decrypt ,
bdi_ready => bdi_ready ,
bdi_valid => bdi_valid ,
bdi_type => bdi_type ,
bdi_partial => bdi_partial ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! PostProcessor
bdo => bdo ,
bdo_ready => bdo_ready ,
bdo_valid => bdo_valid ,
bdo_size => bdo_size ,
msg_auth_valid => msg_auth_valid ,
msg_auth_done => msg_auth_done
);
u_output:
entity work.PostProcessor(structure)
generic map (
G_W => G_W ,
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_CIPH_EXP => G_CIPH_EXP ,
G_REVERSE_CIPH => G_REVERSE_CIPH ,
G_MERGE_TAG => G_MERGE_TAG ,
G_LBS_BYTES => LBS_BYTES ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! External
do_data => do_data ,
do_ready => do_ready ,
do_valid => do_valid ,
--! CipherCore
bdo_ready => bdo_ready ,
bdo_valid => bdo_valid ,
bdo => bdo ,
bdo_size => bdo_size ,
msg_auth_valid => msg_auth_valid ,
msg_auth_done => msg_auth_done ,
--! cmd FIFOs
cmd => cmd_dout ,
cmd_ready => cmd_rd_ready ,
cmd_valid => cmd_rd_valid
);
u_hdr_buffer:
entity work.fwft_fifo(structure)
generic map (
G_W => 24 ,
G_LOG2DEPTH => 2 ,
G_ASYNC_RSTN => G_ASYNC_RSTN
)
port map (
clk => clk ,
rst => rst ,
din => cmd_din ,
din_valid => cmd_wr_valid ,
din_ready => cmd_wr_ready ,
dout => cmd_dout ,
dout_valid => cmd_rd_valid ,
dout_ready => cmd_rd_ready
);
end structure;
|
apache-2.0
|
cd653a3ea58c3e919d43697e3bdf98d4
| 0.391493 | 4.304134 | false | false | false | false |
hoangt/PoC
|
src/fifo/fifo_cc_got_tempput.vhdl
| 2 | 13,816 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Module: FIFO, common clock (cc), pipelined interface,
-- writes only become effective after explicit commit
--
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- As uncommitted writes populate FIFO space that is not yet available for
-- reading, an instance of this FIFO can, indeed, report 'full' and 'not vld'
-- at the same time. While a 'commit' would eventually make data available for
-- reading ('vld'), a 'rollback' would free the space for subsequent writing
-- ('not ful').
--
-- 'commit' and 'rollback' are inclusive and apply to all writes ('put') since
-- the previous 'commit' or 'rollback' up to and including a potentially
-- simultaneous write.
--
-- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is
-- *undefined*!
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
USE poc.utils.all;
use poc.ocram.ocram_sdp;
entity fifo_cc_got_tempput is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
commit : in std_logic;
rollback : in std_logic;
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0)
);
end fifo_cc_got_tempput;
architecture rtl of fifo_cc_got_tempput is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-- Commited Write Pointer (Commit Marker)
signal IPm : unsigned(A_BITS-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
IPm <= (others => '0');
OP0 <= (others => '0');
else
-- Update Input Pointer upon Write
if rollback = '1' then
IP0 <= IPm;
elsif we = '1' then
IP0 <= IP1;
end if;
-- Update Commit Marker
if commit = '1' then
if we = '1' then
IPm <= IP1;
else
IPm <= IP0;
end if;
end if;
-- Update Output Pointer upon Read
if re = '1' then
OP0 <= OP1;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(fulli, IP0, IPm, OP0)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
-- Available Space
if ESTATE_WR_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
else
estate_wr <= (others => 'X');
end if;
-- Available Content
if FSTATE_RD_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IPm - OP0); -- true number of valid entries
end if;
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
else
fstate_rd <= (others => 'X');
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
--
-- The STATE_REG generic is ignored as two different comparators are
-- needed to compare OP with IPm (empty) and IP with OP (full) anyways.
-- So the register implementation is always used.
blkState: block
signal Ful : std_logic := '0';
signal Pnd : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Pnd <= '0';
Avl <= '0';
else
-- Pending Indicator for uncommitted Data
if commit = '1' or rollback = '1' then
Pnd <= '0';
elsif we = '1' then
Pnd <= '1';
end if;
-- Update Full Indicator
if re = '1' or (rollback = '1' and Pnd = '1') then
Ful <= '0';
elsif we = '1' and re = '0' and IP1 = OP0 then
Ful <= '1';
end if;
-- Update Empty Indicator
if commit = '1' and (we = '1' or Pnd = '1') then
Avl <= '1';
elsif re = '1' and OP1 = IPm then
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end block;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
apache-2.0
|
b60e307d66c644aab6f2059cf5a89ece
| 0.518312 | 3.957605 | false | false | false | false |
BogdanArdelean/FPWAM
|
hardware/src/hdl/TopLevel.vhd
| 1 | 69,164 |
-------------------------------------------------------------------------------
-- FILE NAME : TopLevel.vhd
-- MODULE NAME : TopLevel
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that binds all other components to form the processor
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity TopLevel is
port
(
clk : in std_logic
;rst_i : in std_logic
;led : out std_logic_vector(15 downto 0)
);
end TopLevel;
architecture Structural of TopLevel is
----- STACK AND HEAP MEMORY ----
signal mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_input_1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_input_2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_output_1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_output_2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_port1_rd : std_logic;
signal mem_port2_rd : std_logic;
signal mem_port1_wr : std_logic;
signal mem_port2_wr : std_logic;
----- GPRs -----
signal gpr_address1 : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal gpr_input1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_output1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_wr1 : std_logic;
signal gpr_address2 : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal gpr_input2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_output2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_wr2 : std_logic;
----- BIND UNIT -----
signal bind_start : std_logic;
signal bind_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal bind_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_mem_port1_wr : std_logic;
signal bind_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal bind_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_mem_port2_wr : std_logic;
signal bind_trail_input : std_logic_vector(kWamAddressWidth -1 downto 0);
signal bind_trail : std_logic;
signal bind_done : std_logic;
----- DEREF UNIT1 ----
signal deref1_start : std_logic;
signal deref1_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal deref1_mem_port1_rd : std_logic;
signal deref1_res_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_addr_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_addr : std_logic_vector(kWamAddressWidth -1 downto 0);
signal deref1_done : std_logic;
----- DEREF UNIT2 ----
----- THIS IS USED JUST BY UNIFYUNIT ----
signal deref2_start : std_logic;
signal deref2_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref2_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref2_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal deref2_mem_port2_rd : std_logic;
signal deref2_res_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref2_done : std_logic;
----- UNIFY UNIT ----
signal unify_start : std_logic;
signal unify_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref1_in : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref1_done : std_logic;
signal unify_deref2_in : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref2_done : std_logic;
signal unify_bind_done : std_logic;
signal unify_done : std_logic;
signal unify_fail : std_logic;
signal unify_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unify_mem_port1_rd : std_logic;
signal unify_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unify_mem_port2_rd : std_logic;
signal unify_deref1_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref1_start : std_logic;
signal unify_deref2_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref2_start : std_logic;
signal unify_bind_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_bind_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_bind_start : std_logic;
signal unify_mem_sel : unify_mem_sel_t;
signal unifyComb_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unifyComb_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unifyComb_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unifyComb_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
----- DATAFLOWCONTROL UNIT ----
signal dfc_instruction_in : std_logic_vector(kWamInstructionWidth-1 downto 0);
signal dfc_instruction_valid : std_logic;
signal dfc_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_deref1_done : std_logic;
signal dfc_mode_reg : wam_mode_t;
signal dfc_unify_done : std_logic;
signal dfc_bind_done : std_logic;
signal dfc_nr_args : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal dfc_unwind_done : std_logic;
signal dfc_local_fail : std_logic;
signal dfc_global_fail : std_logic;
signal dfc_b_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_new_b_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_deref_addr : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_deref_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_h_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_e_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_bsearch_done : std_logic;
signal dfc_bsearch_found : std_logic;
signal dfc_local_fail_rst : std_logic;
signal dfc_global_fail_out : std_logic;
signal dfc_global_fail_rst : std_logic;
signal dfc_get_instruction : std_logic;
signal dfc_deref1_start : std_logic;
signal dfc_deref1_input : deref_input_t;
signal dfc_S_wr : std_logic;
signal dfc_S_input : s_input_t;
signal dfc_mode_wr : std_logic;
signal dfc_mode_value : wam_mode_t;
signal dfc_mem_port1_rd : std_logic;
signal dfc_mem_port1_wr : std_logic;
signal dfc_mem_input1 : mem_port_input_t;
signal dfc_mem_addr1 : mem_addr_input_t;
signal dfc_mem_port2_rd : std_logic;
signal dfc_mem_port2_wr : std_logic;
signal dfc_mem_input2 : mem_port_input_t;
signal dfc_mem_addr2 : mem_addr_input_t;
signal dfc_bind_start : std_logic;
signal dfc_bind_port1 : bind_input_t;
signal dfc_bind_port2 : bind_input_t;
signal dfc_trail_input : trail_input_t;
signal dfc_H_wr : std_logic;
signal dfc_H_input : h_input_t;
signal dfc_gpr_wr1 : std_logic;
signal dfc_gpr_addr1 : GPR_addr_input_t;
signal dfc_gpr_input1 : gpr_input_t;
signal dfc_gpr_wr2 : std_logic;
signal dfc_gpr_addr2 : GPR_addr_input_t;
signal dfc_gpr_input2 : gpr_input_t;
signal dfc_unify_start : std_logic;
signal dfc_unify_input_a : unify_input_t;
signal dfc_unify_input_b : unify_input_t;
signal dfc_P_input : p_input_t;
signal dfc_P_wr : std_logic;
signal dfc_CP_wr : std_logic;
signal dfc_CP_input : cp_input_t;
signal dfc_nr_wr : std_logic;
signal dfc_nr_input : nrargs_input_t;
signal dfc_newE_wr : std_logic;
signal dfc_E_wr : std_logic;
signal dfc_E_input : e_input_t;
signal dfc_B_input : b_input_t;
signal dfc_b_wr : std_logic;
signal dfc_newB_wr : std_logic;
signal dfc_tr_wr : std_logic;
signal dfc_tr_input : tr_input_t;
signal dfc_hb_wr : std_logic;
signal dfc_hb_input : hb_input_t;
signal dfc_i : unsigned(kWamAddressWidth -1 downto 0);
signal dfc_start_unwind : std_logic;
signal dfc_mem_addr1_out : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_mem_addr2_out : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_mem_out1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_mem_out2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_trail_do : std_logic;
signal dfc_bladdr_wr : std_logic;
signal dfc_bhaddr_wr : std_logic;
signal dfc_bsearch_start : std_logic;
----- TRAIL -----
signal trail_start : std_logic;
signal trail_address : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_H : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_HB : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_B : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_a : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_do : std_logic;
signal trailm_addr_1 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal trailm_output_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_input_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_wr_1 : std_logic;
signal trailm_rd_1 : std_logic;
signal trailm_addr_2 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal trailm_output_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_input_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_wr_2 : std_logic;
signal trailm_rd_2 : std_logic;
----- UNWIND TRAIL ----
signal untrail_start : std_logic;
signal untrail_a1 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_a2 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_port_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_port_1_rd : std_logic;
signal untrail_addr_1 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_port_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_port_2_rd : std_logic;
signal untrail_addr_2 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_mem_port_1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal untrail_mem_port_1_wr : std_logic;
signal untrail_mem_addr_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_mem_port_2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal untrail_mem_port_2_wr : std_logic;
signal untrail_mem_addr_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_done : std_logic;
----- REGISTERS ------
----- H REGISTER
signal H_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal H_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal H_wr : std_logic;
----- S REGISTER
signal S_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal S_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal S_wr : std_logic;
----- MODE REGISTER
signal M_reg : wam_mode_t;
signal M_comb : wam_mode_t;
signal M_wr : std_logic;
----- P REGISTER
signal P_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal P_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal P_wr : std_logic;
----- CP REGISTER
signal CP_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal CP_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal CP_wr : std_logic;
----- NRARGS REGISTER
signal NRARGS_reg : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal NRARGS_comb : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal NRARGS_wr : std_logic;
----- E REGISTER
signal E_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal E_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal E_wr : std_logic;
----- NewE REGISTER
signal NewE_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewE_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewE_wr : std_logic;
----- B REGISTER
signal B_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal B_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal B_wr : std_logic;
----- NewB REGISTER
signal NewB_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewB_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewB_wr : std_logic;
------ TR REGISTER
signal TR_reg : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal TR_comb : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal TR_wr : std_logic;
------ HB register
signal HB_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal HB_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal HB_wr : std_logic;
------ LOCALFAIL register
signal LCLFAIL_reg : std_logic;
signal LCLFAIL_comb : std_logic;
signal LCLFAIL_rst : std_logic;
------ GLOBALFAIL register
signal GLBFAIL_reg : std_logic;
signal GLBFAIL_comb : std_logic;
signal GLBFAIL_rst : std_logic;
-- TEMPORARYMEMORY
type instr_mem is array (0 to 196) of std_logic_vector(kWamInstructionWidth - 1 downto 0);
-- signal mem : instr_mem :=
-- ("00000000000000000000000000000000" -- block
-- ,B"00001_000000001_00000000000001_0000" -- put_structure c/0, A1
-- ,B"00001_000000010_00000000000010_0000" -- put_structure d/0, A2
-- ,B"01010_000000000_00000000000100_0010" -- call p/2
-- ,"00000000000000000000000000000000" -- block
-- ,B"01110_000000000_00000000000000_1001" -- try_me_else 9 p(X,a).
-- ,B"00110_000000011_00000000000000_0001" -- get_variable x3, A1
-- ,B"00101_000000010_00000000000011_0000" -- get_structure a/0, A2
-- ,B"01011_000000000_00000000000000_0000" -- proceed.
-- ,"00000000000000000000000000000000" -- block
-- ,B"01111_000000000_00000000000000_1110" -- retry_me_else 14 p(b,X)
-- ,B"00101_000000001_00000000000100_0000" -- get_structure b/0, A1
-- ,B"00110_000000011_00000000000000_0010" -- get_variable x3, A2
-- ,B"01011_000000000_00000000000000_0000" -- proceed.
-- ,"00000000000000000000000000000000" -- block
-- ,B"10000_000000000_00000000000000_0000" -- trust_me p(X,Y) :- p(X, a), p(b, Y).
-- ,B"01100_000000000_00000000000000_0001" -- allocate 1
-- ,B"00110_000000011_00000000000000_0001" -- get_variable x3, A1
-- ,B"00110_000010001_00000000000000_0001" -- get_variable y1, A2
-- ,B"00100_000000011_00000000000000_0001" -- put_value X3, A1
-- ,B"00001_000000010_00000000000011_0000" -- put_structure a/0, A2
-- ,B"01010_000000000_00000000000100_0010" -- call p/2
-- ,B"00001_000000001_00000000000100_0000" -- put_structure a/0, A1
-- ,B"00100_000010001_00000000000000_0010" -- put_value Y1, A2
-- ,B"01010_000000000_00000000000100_0010" -- call p/2
-- ,B"01101_000000000_00000000000100_0000" -- deallocate
-- ,"00000000000000000000000000000000" -- block
-- );
--signal mem : instr_mem :=
--("00000000000000000000000000000000" -- block
--,B"10010_000000101_00000000000000_0000" -- put_list x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00010_000000100_00000000000000_0001" -- put_variable x4, A1
--,B"10010_000000010_00000000000000_0000" -- put_list A2
--,B"01001_000000100_00000000000000_0000" -- unify_value x4
--,B"01001_000000101_00000000000000_0000" -- unify_value x5
--,B"00001_000000011_00000000000001_0001" -- put_structure f/1, A3
--,B"01001_000000110_00000000000000_0000" -- unify_value x6
--,B"01010_000000000_00000000001011_0011" -- call p/3
--,"00000000000000000000000000000000" -- block
--,B"00101_000000001_00000000000001_0001" -- get_structure f/1, A1
--,B"01000_000000100_00000000000000_0000" -- unify_variable x4
--,B"10100_000000010_00000000000000_0000" -- get_list A2
--,B"01000_000000101_00000000000000_0000" -- unify_variable x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"00111_000000101_00000000000000_0011" -- get_value x5, A3
--,B"10100_000000110_00000000000000_0000" -- get_list x6
--,B"01000_000000111_00000000000000_0000" -- unify_variable x7
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00101_000000111_00000000000001_0001" -- get_structure f/1, A1
--,B"10111_000000000_11000000000000_0001" -- unify_constant a
--,B"01011_000000000_00000000000000_0000" -- proceed
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
-- );
--signal mem : instr_mem := -- p(Z. h(Z, W), f(W))?
--("00000000000000000000000000000000" -- block
--,B"00001_000000001_00000000000001_0010" -- put_list x5
--,B"01000_000000000_00000000000000_0000" -- unify_variable x6
--,B"01000_000000011_00000000000000_0000" -- unify_constant nil
--,B"00001_000000010_00000000000010_0001" -- put_variable x4, A1
--,B"01001_000000011_00000000000000_0000" -- put_list A2
--,B"01010_000000000_00000000000111_0011" -- unify_value x4
--,"00000000000000000000000000000000" -- block -- unify_value x5
--,B"00101_000000000_00000000000010_0001" -- put_structure f/1, A3
--,B"11000_000000000_00000000000000_0001" -- unify_value x6
--,B"00101_000000001_00000000000001_0010" -- call p/3
--,B"10110_000000010_00000000000000_0000"-- block
--,B"11101_000000000_00000000000010_0001" -- get_structure f/1, A1
--,B"10111_000000000_00000000000000_0001" -- unify_variable x4
--,B"01011_000000000_00000000000000_0000" -- get_list A2
--,"00000000000000000000000000000000" -- unify_variable x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"00111_000000101_00000000000000_0011" -- get_value x5, A3
--,B"10100_000000110_00000000000000_0000" -- get_list x6
--,B"01000_000000111_00000000000000_0000" -- unify_variable x7
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00101_000000111_00000000000001_0001" -- get_structure f/1, A1
--,B"10111_000000000_11000000000000_0001" -- unify_constant a
--,B"01011_000000000_00000000000000_0000" -- proceed
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--);
--signal mem : instr_mem :=
--("00000000000000000000000000000000" -- block
--,B"10010_000000101_00000000000000_0000" -- put_list x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00010_000000100_00000000000000_0001" -- put_variable x4, A1
--,B"10010_000000010_00000000000000_0000" -- put_list A2
--,B"01001_000000100_00000000000000_0000" -- unify_value x4
--,B"01001_000000101_00000000000000_0000" -- unify_value x5
--,B"00001_000000011_00000000000001_0001" -- put_structure f/1, A3
--,B"01001_000000110_00000000000000_0000" -- unify_value x6
--,B"01010_000000000_00000000001011_0011" -- call p/3
--,"00000000000000000000000000000000" -- block
--,B"00101_000000001_00000000000001_0001" -- get_structure f/1, A1
--,B"01000_000000100_00000000000000_0000" -- unify_variable x4
--,B"10100_000000010_00000000000000_0000" -- get_list A2
--,B"01000_000000101_00000000000000_0000" -- unify_variable x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"00111_000000101_00000000000000_0011" -- get_value x5, A3
--,B"10100_000000110_00000000000000_0000" -- get_list x6
--,B"01000_000000111_00000000000000_0000" -- unify_variable x7
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00101_000000111_00000000000001_0001" -- get_structure f/1, A1
--,B"10111_000000000_11000000000000_0001" -- unify_constant a
--,B"01011_000000000_00000000000000_0000" -- proceed
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
-- );
signal mem : instr_mem := --
(
B"000000_00000000_00000000000000_0000"
,B"001100_00000000_00000000000000_0001"
,B"000011_00010001_00000000000000_0001"
,B"001010_00000000_00000010000011_0001"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_0001"
,B"010111_00000000_11000000000000_0010"
,B"011000_00000000_00000000000000_0011"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_0011"
,B"010111_00000000_11000000000000_0100"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000000_0110"
,B"011000_00000000_00000000000000_0001"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_0111"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1000"
,B"011000_00000000_00000000000000_0001"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_0101"
,B"011000_00000000_00000000000000_0100"
,B"000001_00000010_00000000000011_0101"
,B"010111_00000000_11000000000000_1001"
,B"011000_00000000_00000000000000_0100"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010011010_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000000_1010"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1011"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_1100"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000000_1101"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000100_00010001_00000000000000_0001"
,B"010100_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"100001_00000000_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000001_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"100001_00000000_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11111111111111_1111"
,B"000101_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000000_1110"
,B"011000_00000000_00000000000000_0001"
,B"000100_00010001_00000000000000_0001"
,B"010100_00000001_00000000000000_0000"
,B"001000_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"000101_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1111"
,B"011000_00000000_00000000000000_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0100"
,B"010111_00000000_11000000000001_0000"
,B"000001_00000010_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_0001"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010100111_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0100"
,B"010111_00000000_11000000000000_1101"
,B"000001_00000010_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_0010"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010100111_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000001_0011"
,B"010111_00000000_11000000000001_0100"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000001_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_0110"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1111"
,B"011000_00000000_00000000000000_0011"
,B"000001_00000010_00000000000011_0101"
,B"010111_00000000_11000000000001_0111"
,B"011000_00000000_00000000000000_0100"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010100111_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_1000"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000001_1001"
,B"011000_00000000_00000000000000_0001"
,B"010001_00010001_00000000000000_0010"
,B"001101_00000000_00000000000000_0000"
,B"011100_00000000_00000010111011_0010"
,B"000000_00000000_00000000000000_0000"
,B"010100_00000001_00000000000000_0000"
,B"001000_00000101_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000100_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000011_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000010_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000001_00000000000000_0000"
,B"010111_00000000_11111111111111_1111"
,B"000101_00000101_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000100_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000011_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000010_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"001011_00000000_00000000000000_0000"
,B"000000_00000000_00000000000000_0000"
,B"001110_00000000_00000000001010_0001"
,B"010100_00000011_00000000000000_0000"
,B"010110_00000010_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"010000_00000000_00000000000000_0000"
,B"010100_00000011_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001000_00000011_00000000000000_0000"
,B"011100_00000000_00000010011010_0011"
,B"000000_00000000_00000000000000_0000"
,B"001110_00000000_00000000001010_1110"
,B"010100_00000011_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"010110_00000010_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"001111_00000000_00000000001011_0101"
,B"010100_00000011_00000000000000_0000"
,B"010110_00000010_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"010000_00000000_00000000000000_0000"
,B"010100_00000011_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001000_00000011_00000000000000_0000"
,B"011100_00000000_00000010100111_0011"
,B"000000_00000000_00000000000000_0000"
,B"001110_00000000_00000000001100_0000"
,B"010100_00000010_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"010000_00000000_00000000000000_0000"
,B"010100_00000010_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001000_00000010_00000000000000_0000"
,B"011100_00000000_00000010111011_0010"
);
signal instruction_counter : unsigned(7 downto 0);
signal instruction : std_logic_vector(kWamInstructionWidth -1 downto 0);
signal instruction_valid : std_logic;
signal instr_mem_addr : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal instr_mem_out : std_logic_vector(kWamInstructionWidth -1 downto 0);
signal instr_mem_rd : std_logic;
signal rst : std_logic := '1';
-- HASH TABLE REPLACEMENT
signal bsearch_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal bsearch_low_addr : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_high_addr : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_start : std_logic;
signal bsearch_done : std_logic;
signal bsearch_found : std_logic;
signal bsearch_memory_in : std_logic_vector(kWamWordWidth -1 downto 0);
signal bsearch_addr_out : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_memory_read : std_logic;
signal bsearch_laddr_wr : std_logic;
signal bsearch_laddr_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_laddr_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_haddr_wr : std_logic;
signal bsearch_haddr_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_haddr_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bmem_addr_port_1 : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bmem_port_1_out : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_1_in : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_1_wr : std_logic;
signal bmem_port_1_rd : std_logic;
signal bmem_addr_port_2 : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bmem_port_2_out : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_2_in : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_2_wr : std_logic;
signal bmem_port_2_rd : std_logic;
constant kTarget : integer := 100000;
signal clock_counter : integer;
signal millis : unsigned(11 downto 0);
signal do_count : boolean;
begin
clk_cnt: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
clock_counter <= 0;
else
if do_count then
if clock_counter = kTarget then
clock_counter <= 0;
else
clock_counter <= clock_counter + 1;
end if;
end if;
end if;
end if;
end process;
milliscnt: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
millis <= to_unsigned(0, millis'length);
else
if clock_counter = kTarget and do_count then
millis <= millis+1;
end if;
end if;
end if;
end process;
RSTPRC: process(clk)
begin
if rising_edge(clk) then
rst <= '0';
end if;
end process;
do_count <= not((fpwam_instr(dfc_instruction_in) = i_nop) and (unsigned(P_reg) = to_unsigned(1, P_reg'length)));
led(0) <= GLBFAIL_reg;
led(1) <= to_std_logic(fpwam_instr(dfc_instruction_in) = i_nop);
led(2) <= to_std_logic(unsigned(P_reg) = to_unsigned(1, P_reg'length));
led(3) <= '1';
led(15 downto 4) <= std_logic_vector(millis);
-- INSTRUCTION MEMORY
instr_mem_addr <= P_reg;
instr_mem_rd <= dfc_get_instruction;
instruction_valid <= '1';
dfc_instruction_in <= instr_mem_out;
-- TEMPORARYMEMORY
INSTCNT: process(clk)
begin
if rising_edge(clk) then
if instr_mem_rd = '1' then
instr_mem_out <= mem(to_integer(unsigned(instr_mem_addr)));
end if;
end if;
end process;
-- INSTRMEM: entity work.Memory(Behavioral)
-- generic map
-- (
-- kMemAddressWidth => kWamInstrMemWidth
-- ,kWordWidth => kWamInstructionWidth
-- )
-- port map
-- (
-- clk => clk
--
-- ,addr_port_1 => instr_mem_addr
-- ,word_port_1_o => instr_mem_out
-- ,word_port_1_i => open
-- ,wr_port_1 => open
-- ,rd_port_1 => instr_mem_rd
--
-- ,addr_port_2 => open
-- ,word_port_2_o => open
-- ,word_port_2_i => open
-- ,wr_port_2 => open
-- ,rd_port_2 => open
-- );
-- MODE REGISTER BEGIN
M_wr <= dfc_mode_wr;
M_comb <= dfc_mode_value;
MREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
M_reg <= mode_read_t;
elsif M_wr = '1' then
M_reg <= M_comb;
end if;
end if;
end process;
-- H REGISTER BEGIN
H_wr <= dfc_H_wr;
HMUX: process(dfc_H_input, H_reg, HB_reg, mem_output_1, mem_output_2, dfc_instruction_in)
begin
H_comb <= H_reg;
case dfc_H_input is
when HI_p1_t =>
H_comb <= std_logic_vector(unsigned(H_reg) + 1);
when HI_p2_t =>
H_comb <= std_logic_vector(unsigned(H_reg) + 2);
when HI_HB_t =>
H_comb <= HB_reg;
when HI_mem_port1_t =>
H_comb <= mem_output_1(kWamAddressWidth -1 downto 0);
when HI_mem_port2_t =>
H_comb <= mem_output_2(kWamAddressWidth -1 downto 0);
when HI_Hpconstant_t =>
H_comb <= std_logic_vector(unsigned(H_reg)+unsigned(dfc_instruction_in(kGPRAddressWidth -1 downto 0)));
when others =>
null;
end case;
end process;
HREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
H_reg <= kWamHeapStart;
elsif H_wr = '1' then
H_reg <= H_comb;
end if;
end if;
end process;
-- H REGISTER END
-- S REGISTER START
S_wr <= dfc_S_wr;
SMUX: process(dfc_S_input, S_reg, deref1_res_out, dfc_instruction_in)
begin
S_comb <= S_reg;
case dfc_S_input is
when SI_untag_deref_p1_t =>
S_comb <= std_logic_vector(unsigned(fpwam_value(deref1_res_out))+1);
when SI_p1_t =>
S_comb <= std_logic_vector(unsigned(S_reg)+1);
when SI_untag_deref_t =>
S_comb <= std_logic_vector(fpwam_value(deref1_res_out));
when SI_pconstant_t =>
S_comb <= std_logic_vector(unsigned(S_reg)+unsigned(dfc_instruction_in(kGPRAddressWidth -1 downto 0)));
when others =>
null;
end case;
end process;
SREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
S_reg <= (others => '0');
elsif S_wr = '1' then
S_reg <= S_comb;
end if;
end if;
end process;
-- S REGISTER END
-- P REGISTER BEGIN
PMUX: process(dfc_P_input, P_reg, CP_reg, instr_mem_out, dfc_i, bmem_port_1_out, mem_output_1, mem_output_2)
begin
case dfc_P_input is
when PI_p1_t =>
P_comb <= std_logic_vector(unsigned(P_reg)+1);
when PI_CP_t =>
P_comb <= CP_reg;
when PI_instr_t =>
P_comb <= fpwam_instr_addr(instr_mem_out);
when PI_mem_port1_t =>
P_comb <= mem_output_1(kWamInstrMemWidth -1 downto 0);
when PI_mem_port2_t =>
P_comb <= mem_output_2(kWamInstrMemWidth -1 downto 0);
when PI_PpI_t =>
P_comb <= std_logic_vector(unsigned(P_reg)+dfc_i(kWamInstrMemWidth -1 downto 0));
when PI_bmem_port1_t =>
P_comb <= bmem_port_1_out(kWamInstrMemWidth -1 downto 0);
when PI_constant_t =>
P_comb <= instr_mem_out(kWamInstrMemWidth -1 downto 0);
when others =>
P_comb <= std_logic_vector(unsigned(P_reg)+1);
end case;
end process;
P_wr <= dfc_P_wr;
PREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
P_reg <= std_logic_vector(to_unsigned(1, P_reg'length));
elsif P_wr = '1' then
P_reg <= P_comb;
end if;
end if;
end process;
-- CP REGISTER BEGIN
CP_wr <= dfc_CP_wr;
CP_comb <= P_reg when dfc_CP_input = CPI_P_t else
mem_output_1(kWamInstrMemWidth -1 downto 0) when dfc_CP_input = CPI_mem_port1_t else
mem_output_2(kWamInstrMemWidth -1 downto 0);
CPREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
CP_reg <= (others => '0');
elsif CP_wr = '1' then
CP_reg <= CP_comb;
end if;
end if;
end process;
-- NRARGS REGISTER BEGIN
NRARGS_wr <= dfc_nr_wr;
NRARGS_comb <= fpwam_instr_arity(dfc_instruction_in) when dfc_nr_input = NRARGSI_instr_t else
mem_output_1(kGPRAddressWidth -1 downto 0) when dfc_nr_input = NRARGSI_mem_port1_t else
mem_output_2(kGPRAddressWidth -1 downto 0);
NRARGSREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
NRARGS_reg <= (others => '0');
elsif NRARGS_wr = '1' then
NRARGS_reg <= NRARGS_comb;
end if;
end if;
end process;
-- E REGISTER BEGIN
E_wr <= dfc_E_wr;
E_comb <= NewE_reg when dfc_E_input = EI_newE_t else
mem_output_1(kWamAddressWidth -1 downto 0) when dfc_E_input = EI_mem_port1_t else
mem_output_2(kWamAddressWidth -1 downto 0);
EREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
E_reg <= kWamStackStart;
elsif E_wr = '1' then
E_reg <= E_comb;
end if;
end if;
end process;
-- NewE REGISTER BEGIN
NewE_wr <= dfc_newE_wr;
NewE_comb <= std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(E_reg) + 3) when E_reg > B_reg else
std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(B_reg) + 7);
NEWEREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
NewE_reg <= kWamStackStart;
elsif NewE_wr = '1' then
NewE_reg <= NewE_comb;
end if;
end if;
end process;
-- B REGISTER BEGIN
B_wr <= dfc_B_wr;
B_comb <= NewB_reg when dfc_B_input = BRI_newB_t else
mem_output_1(kWamAddressWidth -1 downto 0) when dfc_B_input = BRI_mem_port1_t else
mem_output_2(kWamAddressWidth -1 downto 0);
BREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
B_reg <= kWamStackStart;
elsif B_wr = '1' then
B_reg <= B_comb;
end if;
end if;
end process;
-- NewB REGISTER BEGIN
NewB_wr <= dfc_newB_wr;
NewB_comb <= std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(E_reg) + 3) when E_reg > B_reg else
std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(B_reg) + 7);
NEWBREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
NewB_reg <= kWamStackStart;
elsif NewB_wr = '1' then
NewB_reg <= NewB_comb;
end if;
end if;
end process;
HB_comb <= H_reg when dfc_hb_input = HBI_H_t else
mem_output_1(kWamAddressWidth -1 downto 0) when dfc_hb_input = HBI_mem_port1_t else
mem_output_2(kWamAddressWidth -1 downto 0);
HB_wr <= dfc_hb_wr;
HBREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
HB_reg <= kWamStackStart;
elsif HB_wr = '1' then
HB_reg <= HB_comb;
end if;
end if;
end process;
-- TR REGISTER
TR_wr <= trail_do or dfc_tr_wr;
TR_comb <= std_logic_vector(unsigned(TR_reg)+1) when dfc_tr_input = TRI_Trp1_t else
mem_output_1(kWamTrailAddressWidth -1 downto 0) when dfc_tr_input = TRI_mem_port1_t else
mem_output_2(kWamTrailAddressWidth -1 downto 0);
TRREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
TR_reg <= (others => '0');
elsif TR_wr = '1' then
TR_reg <= TR_comb;
end if;
end if;
end process;
LCLFAIL_comb <= unify_fail;
LCLFAIL_rst <= dfc_local_fail_rst;
LCLFAIL: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or LCLFAIL_rst = '1' then
LCLFAIL_reg <= '0';
else
LCLFAIL_reg <= LCLFAIL_reg or LCLFAIL_comb;
end if;
end if;
end process;
GLBFAIL_comb <= dfc_global_fail_out;
GLBFAIL_rst <= dfc_global_fail_rst;
GLBFAIL: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or GLBFAIL_rst = '1' then
GLBFAIL_reg <= '0';
else
GLBFAIL_reg <= GLBFAIL_reg or GLBFAIL_comb;
end if;
end if;
end process;
bsearch_laddr_comb <= dfc_instruction_in(kWamInstrMemWidth -1 downto 0);
bsearch_laddr_wr <= dfc_bladdr_wr;
BLADDR: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bsearch_laddr_reg <= (others => '0');
elsif bsearch_laddr_wr = '1' then
bsearch_laddr_reg <= bsearch_laddr_comb;
end if;
end if;
end process;
bsearch_haddr_comb <= dfc_instruction_in(kWamInstrMemWidth -1 downto 0);
bsearch_haddr_wr <= dfc_bhaddr_wr;
BHADDR: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bsearch_haddr_reg <= (others => '0');
elsif bsearch_haddr_wr = '1' then
bsearch_haddr_reg <= bsearch_haddr_comb;
end if;
end if;
end process;
-- STACK AND HEAP MEMORY BEGIN
mem_port1_rd <= deref1_mem_port1_rd
or unify_mem_port1_rd
or dfc_mem_port1_rd
or mem_port1_wr;
mem_port2_rd <= deref2_mem_port2_rd
or unify_mem_port2_rd
or dfc_mem_port2_rd
or mem_port2_wr;
mem_port1_wr <= bind_mem_port1_wr
or dfc_mem_port1_wr
or untrail_mem_port_1_wr;
mem_port2_wr <= bind_mem_port2_wr
or dfc_mem_port2_wr
or untrail_mem_port_2_wr;
ADDR1MUX: process(deref1_res_out,dfc_mem_addr1, H_reg, deref1_mem_addr1, bind_mem_addr1, bind_mem_addr2, unifyComb_mem_addr1, S_reg,
E_reg, dfc_instruction_in, B_reg, NewE_reg, NewB_reg, NRARGS_reg, dfc_i, untrail_mem_addr_1, mem_output_1, dfc_mem_addr1_out)
begin
mem_addr1 <= (others => '0');
case dfc_mem_addr1 is
when MA_H_t =>
mem_addr1 <= H_reg;
when MA_Hplus1_t =>
mem_addr1 <= std_logic_vector(unsigned(H_reg)+1);
when MA_deref_unit_t =>
mem_addr1 <= deref1_mem_addr1;
when MA_bind_unit_1_t =>
mem_addr1 <= bind_mem_addr1;
when MA_bind_unit_2_t =>
mem_addr1 <= bind_mem_addr2;
when MA_unify_unit_t =>
mem_addr1 <= unifyComb_mem_addr1;
when MA_stack_addr_t => -- TODO
mem_addr1 <= fpwam_var_stack_addr(dfc_instruction_in, E_reg);
when MA_S_t =>
mem_addr1 <= S_reg;
when MA_untag_deref_t =>
mem_addr1 <= fpwam_value(deref1_res_out);
when MA_Ep2orB_t =>
if E_reg > B_reg then
mem_addr1 <= std_logic_vector(unsigned(E_reg)+2);
else
mem_addr1 <= B_reg;
end if;
when MA_newE_t =>
mem_addr1 <= NewE_reg;
when MA_newEp1_t =>
mem_addr1 <= std_logic_vector(unsigned(NewE_reg)+1);
when MA_newEp2_t =>
mem_addr1 <= std_logic_vector(unsigned(NewE_reg)+2);
when MA_E_t =>
mem_addr1 <= E_reg;
when MA_Ep1_t =>
mem_addr1 <= std_logic_vector(unsigned(E_reg)+1);
when MA_newB_t =>
mem_addr1 <= NewB_reg;
when MA_B_t =>
mem_addr1 <= B_reg;
when MA_unwind_trail_t =>
mem_addr1 <= untrail_mem_addr_1;
when MA_DFC_t =>
mem_addr1 <= dfc_mem_addr1_out;
when others =>
null;
end case;
end process;
ADDR2MUX: process(deref1_res_out, dfc_mem_addr2, H_reg, deref1_mem_addr1, bind_mem_addr1, bind_mem_addr2, unifyComb_mem_addr2, S_reg,
E_reg, dfc_instruction_in, B_reg, NewE_reg, NewB_reg, NRARGS_reg, dfc_i, untrail_mem_addr_2, dfc_mem_addr2_out)
begin
mem_addr2 <= (others => '0');
case dfc_mem_addr2 is
when MA_H_t =>
mem_addr2 <= H_reg;
when MA_Hplus1_t =>
mem_addr2 <= std_logic_vector(unsigned(H_reg)+1);
when MA_deref_unit_t =>
mem_addr2 <= deref1_mem_addr1;
when MA_bind_unit_1_t =>
mem_addr2 <= bind_mem_addr1;
when MA_bind_unit_2_t =>
mem_addr2 <= bind_mem_addr2;
when MA_unify_unit_t =>
mem_addr2 <= unifyComb_mem_addr2;
when MA_stack_addr_t => -- TODO
mem_addr2 <= fpwam_var_stack_addr(dfc_instruction_in, E_reg);
when MA_S_t =>
mem_addr2 <= S_reg;
when MA_untag_deref_t =>
mem_addr2 <= fpwam_value(deref1_res_out);
when MA_Ep2orB_t =>
if E_reg > B_reg then
mem_addr2 <= std_logic_vector(unsigned(E_reg)+2);
else
mem_addr2 <= B_reg;
end if;
when MA_newE_t =>
mem_addr2 <= NewE_reg;
when MA_newEp1_t =>
mem_addr2 <= std_logic_vector(unsigned(NewE_reg)+1);
when MA_newEp2_t =>
mem_addr2 <= std_logic_vector(unsigned(NewE_reg)+2);
when MA_E_t =>
mem_addr2 <= E_reg;
when MA_Ep1_t =>
mem_addr2 <= std_logic_vector(unsigned(E_reg)+1);
when MA_newB_t =>
mem_addr2 <= NewB_reg;
when MA_B_t =>
mem_addr2 <= B_reg;
when MA_unwind_trail_t =>
mem_addr2 <= untrail_mem_addr_2;
when MA_DFC_t =>
mem_addr2 <= dfc_mem_addr2_out;
when others =>
null;
end case;
end process;
PORT1MUX: process(dfc_mem_input1, mem_output_2,H_reg, dfc_instruction_in, gpr_output1, bind_mem_word1, bind_mem_word2, unifyComb_mem_word1, mem_input_2,
gpr_output1, gpr_output2, E_reg, CP_reg, B_reg, TR_reg, NRARGS_reg, untrail_mem_port_1, dfc_mem_out1, deref1_res_out, P_reg)
begin
mem_input_1 <= (others => '0');
case dfc_mem_input1 is
when MI_str_Hplus1_t =>
mem_input_1 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_str_t);
when MI_constant_t =>
mem_input_1 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when MI_GPR_t =>
mem_input_1 <= gpr_output1;
when MI_GPR2_t =>
mem_input_1 <= gpr_output2;
when MI_bind_unit_1_t =>
mem_input_1 <= bind_mem_word1;
when MI_bind_unit_2_t =>
mem_input_1 <= bind_mem_word2;
when MI_unify_unit_t =>
mem_input_1 <= unifyComb_mem_word1;
when MI_ref_H_t =>
mem_input_1 <= fpwam_word(H_reg, tag_ref_t);
when MI_mem_port2_t =>
mem_input_1 <= mem_output_2;
when MI_E_t =>
mem_input_1 <= "00"&E_reg; -- TEMPORARY FIX
when MI_CP_t =>
mem_input_1 <= "00000000"&CP_reg; -- TEMPORARY FIX
when MI_ref_addr_t =>
mem_input_1 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when MI_B_t =>
mem_input_1 <= "00"&B_reg; -- TEMPORARY FIX
when MI_TR_t =>
mem_input_1 <= "00000000"&TR_reg; -- TEMPORARY FIX
when MI_NRAGRGS_t =>
mem_input_1 <= "00000000000000"&NRARGS_reg; -- TEMPORARY FIX
when MI_unwind_trail_t =>
mem_input_1 <= untrail_mem_port_1;
when MI_H_t =>
mem_input_1 <= "00"&H_reg;
when MI_dfc_t =>
mem_input_1 <= dfc_mem_out1;
when MI_deref_t =>
mem_input_1 <= deref1_res_out;
when MI_lis_Hplus1_t =>
mem_input_1 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_lis_t);
when MI_P_t =>
mem_input_1 <= "00000000"&std_logic_vector(unsigned(P_reg));
when others =>
null;
end case;
end process;
PORT2MUX: process(dfc_mem_input2, H_reg, mem_output_1, dfc_instruction_in, gpr_output1, bind_mem_word1, bind_mem_word2, unifyComb_mem_word2, mem_input_1,
gpr_output1, gpr_output2, E_reg, CP_reg, B_reg, TR_reg, NRARGS_reg, untrail_mem_port_2, dfc_mem_out2, deref1_res_out, P_reg )
begin
mem_input_2 <= (others => '0');
case dfc_mem_input2 is
when MI_str_Hplus1_t =>
mem_input_2 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_str_t);
when MI_constant_t =>
mem_input_2 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when MI_GPR_t =>
mem_input_2 <= gpr_output1;
when MI_GPR2_t =>
mem_input_2 <= gpr_output2;
when MI_bind_unit_1_t =>
mem_input_2 <= bind_mem_word1;
when MI_bind_unit_2_t =>
mem_input_2 <= bind_mem_word2;
when MI_unify_unit_t =>
mem_input_2 <= unifyComb_mem_word2;
when MI_ref_H_t =>
mem_input_2 <= fpwam_word(H_reg, tag_ref_t);
when MI_mem_port1_t =>
mem_input_2 <= mem_output_1;
when MI_E_t =>
mem_input_2 <= "00"&E_reg; -- TEMPORARY FIX
when MI_CP_t =>
mem_input_2 <= "00000000"&CP_reg; -- TEMPORARY FIX
when MI_ref_addr_t =>
mem_input_2 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when MI_B_t =>
mem_input_2 <= "00"&B_reg; -- TEMPORARY FIX
when MI_TR_t =>
mem_input_2 <= "00000000"&TR_reg; -- TEMPORARY FIX
when MI_NRAGRGS_t =>
mem_input_2 <= "00000000000000"&NRARGS_reg; -- TEMPORARY FIX
when MI_unwind_trail_t =>
mem_input_2 <= untrail_mem_port_2;
when MI_H_t =>
mem_input_2 <= "00"&H_reg;
when MI_dfc_t =>
mem_input_2 <= dfc_mem_out2;
when MI_deref_t =>
mem_input_2 <= deref1_res_out;
when MI_lis_Hplus1_t =>
mem_input_2 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_lis_t);
when MI_P_t =>
mem_input_2 <= "00000000"&std_logic_vector(unsigned(P_reg));
when others =>
null;
end case;
end process;
HEAPSTACK: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,addr_port_1 => mem_addr1
,word_port_1_o => mem_output_1
,word_port_1_i => mem_input_1
,wr_port_1 => mem_port1_wr
,rd_port_1 => mem_port1_rd
,addr_port_2 => mem_addr2
,word_port_2_o => mem_output_2
,word_port_2_i => mem_input_2
,wr_port_2 => mem_port2_wr
,rd_port_2 => mem_port2_rd
);
-- STACK AND HEAP MEMORY END
-- GPRs BEGIN
gpr_address1 <= dfc_instruction_in(kGPRAddressWidth-1 + kWamWordWidth downto kWamWordWidth) when dfc_gpr_addr1 = GPRA_instr_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0)) when dfc_gpr_addr1 = GPRA_I_t else
std_logic_vector(to_unsigned(1, kGPRAddressWidth)) when dfc_gpr_addr1 = GPRA_1_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0) + 1);
gpr_wr1 <= dfc_gpr_wr1;
GPRINMUX: process(dfc_gpr_input1, H_reg, mem_output_1, mem_output_2, E_reg, deref1_res_out, dfc_instruction_in)
begin
gpr_input1 <= (others => '0');
case dfc_gpr_input1 is
when GPRI_ref_H_t =>
gpr_input1 <= fpwam_word(H_reg, tag_ref_t);
when GPRI_mem_port1_t =>
gpr_input1 <= mem_output_1;
when GPRI_mem_port2_t =>
gpr_input1 <= mem_output_2;
when GPRI_str_H_t =>
gpr_input1 <= fpwam_word(H_reg, tag_str_t);
when GPRI_ref_addr_t =>
gpr_input1 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when GPRI_lis_H_t =>
gpr_input1 <= fpwam_word(H_reg, tag_lis_t);
when GPRI_con_t =>
gpr_input1 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when GPRI_deref_t =>
gpr_input1 <= deref1_res_out;
when GPRI_constant_t =>
gpr_input1 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when GPRI_gpr2_t =>
gpr_input1 <= gpr_output2;
when others =>
null;
end case;
end process;
gpr_address2 <= dfc_instruction_in(kGPRAddressWidth-1 downto 0) when dfc_gpr_addr2 = GPRA_instr_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0)) when dfc_gpr_addr2 = GPRA_I_t else
std_logic_vector(to_unsigned(1, kGPRAddressWidth)) when dfc_gpr_addr2 = GPRA_1_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0) + 1);
gpr_wr2 <= dfc_gpr_wr2;
GPRINMUX2: process(dfc_gpr_input2, H_reg, mem_output_1, mem_output_2, E_reg, deref1_res_out, dfc_instruction_in)
begin
gpr_input2 <= (others => '0');
case dfc_gpr_input2 is
when GPRI_ref_H_t =>
gpr_input2 <= fpwam_word(H_reg, tag_ref_t);
when GPRI_mem_port1_t =>
gpr_input2 <= mem_output_1;
when GPRI_mem_port2_t =>
gpr_input2 <= mem_output_2;
when GPRI_ref_addr_t =>
gpr_input2 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when GPRI_lis_H_t =>
gpr_input2 <= fpwam_word(H_reg, tag_lis_t);
when GPRI_con_t =>
gpr_input2 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when GPRI_deref_t =>
gpr_input2 <= deref1_res_out;
when GPRI_gpr1_t =>
gpr_input2 <= gpr_output1;
when GPRI_constant_t =>
gpr_input2 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when others =>
null;
end case;
end process;
GPRS: entity work.GPR(Behavioral)
generic map
(
kAddressWidth => kGPRAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,address1 => gpr_address1
,wr1 => gpr_wr1
,input_word1 => gpr_input1
,output_word1 => gpr_output1
,address2 => gpr_address2
,wr2 => gpr_wr2
,input_word2 => gpr_input2
,output_word2 => gpr_output2
);
-- GPRs END
-- BIND START
bind_start <= dfc_bind_start
or unify_bind_start;
BINDINPUT1MUX: process(dfc_bind_port1, deref1_res_out, mem_output_1, unify_bind_word1)
begin
bind_word1 <= (others => '0');
case dfc_bind_port1 is
when BI_deref_unit_t =>
bind_word1 <= deref1_res_out;
when BI_mem_port1_t =>
bind_word1 <= mem_output_1;
when BI_unify_unit_t =>
bind_word1 <= unify_bind_word1;
when others =>
null;
end case;
end process;
BINDINPUT2MUX: process(dfc_bind_port2, deref1_res_out, mem_output_1, unify_bind_word2)
begin
bind_word2 <= (others => '0');
case dfc_bind_port2 is
when BI_deref_unit_t =>
bind_word2 <= deref1_res_out;
when BI_mem_port1_t =>
bind_word2 <= mem_output_1;
when BI_unify_unit_t =>
bind_word2 <= unify_bind_word2;
when others =>
null;
end case;
end process;
BINDUNIT: entity work.BindUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,rst => rst
,start_bind => bind_start
,start_word1 => bind_word1
,start_word2 => bind_word2
,mem_addr1 => bind_mem_addr1
,mem_out1 => bind_mem_word1
,mem_wr_1 => bind_mem_port1_wr
,mem_addr2 => bind_mem_addr2
,mem_out2 => bind_mem_word2
,mem_wr_2 => bind_mem_port2_wr
,trail_input => bind_trail_input
,trail => bind_trail
,bind_done => bind_done
);
-- BIND end
-- DEREF1 START
deref1_start <= dfc_deref1_start
or unify_deref1_start;
deref1_mem_word1 <= mem_output_1;
DEREFINPUTMUX: process(dfc_deref1_input, gpr_output1, mem_output_1, mem_output_2, unify_deref1_out, dfc_instruction_in, E_reg)
begin
deref1_word <= (others => '0');
case dfc_deref1_input is
when DI_GPR_t =>
deref1_word <= gpr_output1;
when DI_unify_unit_t =>
deref1_word <= unify_deref1_out;
when DI_EYnp2_t =>
deref1_word <= fpwam_word(std_logic_vector(unsigned(E_reg)+
unsigned(dfc_instruction_in(kGPRAddressWidth-1 + kWamWordWidth downto kWamWordWidth))+2), tag_ref_t);
when DI_mem_port1_t =>
deref1_word <= mem_output_1;
when others =>
null;
end case;
end process;
deref1_addr <= fpwam_value(deref1_addr_word);
DEREF1: entity work.DerefUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,rst => rst
,start_deref => deref1_start
,start_word => deref1_word
,memory_in => deref1_mem_word1
,addr_out => deref1_mem_addr1
,rd_mem => deref1_mem_port1_rd
,res_out => deref1_res_out
,res_addr => deref1_addr_word
,done => deref1_done
);
-- DEREF1 END
-- DEREF2 START
deref2_start <= unify_deref2_start;
deref2_mem_word2 <= mem_output_2;
deref2_word <= unify_deref2_out;
DEREF2: entity work.DerefUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,rst => rst
,start_deref => deref2_start
,start_word => deref2_word
,memory_in => deref2_mem_word2
,addr_out => deref2_mem_addr2
,rd_mem => deref2_mem_port2_rd
,res_out => deref2_res_out
,res_addr => open
,done => deref2_done
);
-- DEREF2 END
-- UNIFYUNIT START
unify_start <= dfc_unify_start;
UNIFY1MUX: process(dfc_unify_input_a, gpr_output1, mem_output_1, mem_output_2)
begin
unify_word1 <= (others => '0');
case dfc_unify_input_a is
when UI_GPR_t =>
unify_word1 <= gpr_output1;
when UI_mem_port1_t =>
unify_word1 <= mem_output_1;
when UI_mem_port2_t =>
unify_word1 <= mem_output_2;
when others =>
null;
end case;
end process;
UNIFY2MUX: process(dfc_unify_input_b, gpr_output1, mem_output_1, mem_output_2, gpr_output2)
begin
unify_word2 <= (others => '0');
case dfc_unify_input_b is
when UI_GPR_t =>
unify_word2 <= gpr_output2;
when UI_mem_port1_t =>
unify_word2 <= mem_output_1;
when UI_mem_port2_t =>
unify_word2 <= mem_output_2;
when others =>
null;
end case;
end process;
UNIFYMEMSEL: process(unify_mem_sel, unify_mem_addr1, unify_mem_addr2, deref1_mem_addr1, deref2_mem_addr2, deref1_mem_word1, deref2_mem_word2, bind_mem_word1, bind_mem_word2, bind_mem_addr1, bind_mem_addr2)
begin
unifyComb_mem_addr1 <= (others => '0');
unifyComb_mem_addr2 <= (others => '0');
unifyComb_mem_word1 <= (others => '0');
unifyComb_mem_word2 <= (others => '0');
case unify_mem_sel is
when sel_unify_t =>
unifyComb_mem_addr1 <= unify_mem_addr1;
unifyComb_mem_addr2 <= unify_mem_addr2;
when sel_deref_t =>
unifyComb_mem_addr1 <= deref1_mem_addr1;
unifyComb_mem_addr2 <= deref2_mem_addr2;
unifyComb_mem_word1 <= deref1_mem_word1;
unifyComb_mem_word2 <= deref2_mem_word2;
when sel_bind_t =>
unifyComb_mem_addr1 <= bind_mem_addr1;
unifyComb_mem_addr2 <= bind_mem_addr2;
unifyComb_mem_word1 <= bind_mem_word1;
unifyComb_mem_word2 <= bind_mem_word2;
when others =>
null;
end case;
end process;
unify_mem_word1 <= mem_output_1;
unify_mem_word2 <= mem_output_2;
UNIFYU: entity work.UnifyUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
,kPdlAddressWidth => kWamPdlAddressWidth
)
port map
(
clk => clk
,rst => rst
,start_unify => unify_start
,word1 => unify_word1
,word2 => unify_word2
,mem1_input => unify_mem_word1
,mem2_input => unify_mem_word2
,deref1_input => deref1_res_out
,deref1_done => deref1_done
,deref2_input => deref2_res_out
,deref2_done => deref2_done
,bind_done => bind_done
,unify_done => unify_done
,fail => unify_fail
,mem1_output => unify_mem_addr1
,rd_mem_port1 => unify_mem_port1_rd
,mem2_output => unify_mem_addr2
,rd_mem_port2 => unify_mem_port2_rd
,deref1_output => unify_deref1_out
,deref1_start => unify_deref1_start
,deref2_output => unify_deref2_out
,deref2_start => unify_deref2_start
,bind1_output => unify_bind_word1
,bind2_output => unify_bind_word2
,bind_start => unify_bind_start
,mem_sel => unify_mem_sel
);
-- UNIFYUNIT END
-- DFC BEGIN
dfc_instruction_valid <= instruction_valid;
dfc_mem_word1 <= mem_output_2;
dfc_deref1_done <= deref1_done;
dfc_mode_reg <= M_reg;
dfc_nr_args <= NRARGS_reg;
dfc_unify_done <= unify_done;
dfc_bind_done <= bind_done;
dfc_local_fail <= LCLFAIL_reg;
dfc_global_fail <= GLBFAIL_reg;
dfc_b_reg <= B_reg;
dfc_new_b_reg <= NewB_reg;
dfc_unwind_done <= untrail_done;
dfc_deref_addr <= deref1_addr;
dfc_deref_word <= deref1_res_out;
dfc_h_reg <= H_reg;
dfc_e_reg <= E_reg;
dfc_bsearch_done <= bsearch_done;
dfc_bsearch_found <= bsearch_found;
DFC: entity work.DataFlowControl(Behavioral)
port map
(
clk => clk
,rst => rst
,instruction => dfc_instruction_in
,instruction_valid => dfc_instruction_valid
,mem_obj => dfc_mem_word1
,deref_done => dfc_deref1_done
,mode_reg => dfc_mode_reg
,unify_done => dfc_unify_done
,bind_done => dfc_bind_done
,nr_args => dfc_nr_args
,unwind_done => dfc_unwind_done
,local_fail => dfc_local_fail
,global_fail => dfc_global_fail
,b_reg => dfc_b_reg
,new_b_reg => dfc_new_b_reg
,deref_addr => dfc_deref_addr
,deref_word => dfc_deref_word
,H_reg => dfc_h_reg
,E_reg => dfc_e_reg
,bsearch_done => dfc_bsearch_done
,bsearch_found => dfc_bsearch_found
,local_fail_rst => dfc_local_fail_rst
,global_fail_out => dfc_global_fail_out
,global_fail_rst => dfc_global_fail_rst
,get_instruction => dfc_get_instruction
,start_deref => dfc_deref1_start
,deref_input => dfc_deref1_input
,wr_s_reg => dfc_S_wr
,s_reg_input => dfc_S_input
,wr_mode_reg => dfc_mode_wr
,mode_value => dfc_mode_value
,rd_mem_port1 => dfc_mem_port1_rd
,wr_mem_port1 => dfc_mem_port1_wr
,mem_input1 => dfc_mem_input1
,mem_addr_input1 => dfc_mem_addr1
,rd_mem_port2 => dfc_mem_port2_rd
,wr_mem_port2 => dfc_mem_port2_wr
,mem_input2 => dfc_mem_input2
,mem_addr_input2 => dfc_mem_addr2
,bind => dfc_bind_start
,bind_port1 => dfc_bind_port1
,bind_port2 => dfc_bind_port2
,trail_input => dfc_trail_input
,wr_h_reg => dfc_H_wr
,h_input => dfc_H_input
,wr_gpr1 => dfc_gpr_wr1
,gpr_addr1 => dfc_gpr_addr1
,gpr_input1 => dfc_gpr_input1
,wr_gpr2 => dfc_gpr_wr2
,gpr_addr2 => dfc_gpr_addr2
,gpr_input2 => dfc_gpr_input2
,start_unify => dfc_unify_start
,unify_input_a => dfc_unify_input_a
,unify_input_b => dfc_unify_input_b
,p_input => dfc_P_input
,p_wr => dfc_P_wr
,cp_wr => dfc_CP_wr
,cp_input => dfc_CP_input
,nrargs_wr => dfc_nr_wr
,nrargs_input => dfc_nr_input
,newE_wr => dfc_newE_wr
,E_wr => dfc_E_wr
,e_input => dfc_E_input
,b_input => dfc_B_input
,b_wr => dfc_B_wr
,newB_wr => dfc_newB_wr
,tr_wr => dfc_tr_wr
,tr_input => dfc_tr_input
,hb_wr => dfc_hb_wr
,hb_input => dfc_hb_input
,i => dfc_i
,start_unwind => dfc_start_unwind
,mem_addr1 => dfc_mem_addr1_out
,mem_addr2 => dfc_mem_addr2_out
,mem_out1 => dfc_mem_out1
,mem_out2 => dfc_mem_out2
,trail_do => dfc_trail_do
,bladdr_wr => dfc_bladdr_wr
,bhaddr_wr => dfc_bhaddr_wr
,bsearch_start => dfc_bsearch_start
);
-- DFC END
-- TRAIL BEGIN
trail_start <= bind_trail or dfc_trail_do;
trail_address <= bind_trail_input when dfc_trail_input = TI_bind_output_t else
fpwam_value(deref1_res_out) when dfc_trail_input = TI_deref_t else
bind_trail_input;
trail_H <= H_reg;
trail_HB <= HB_reg;
trail_B <= B_reg;
TRAILUNIT: entity work.TrailUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
)
port map
(
trail => trail_start
,trail_address => trail_address
,H => trail_H
,HB => trail_HB
,B => trail_B
,a => trail_a
,do_trail => trail_do
);
trailm_addr_1 <= TR_reg when dfc_trail_input = TI_bind_output_t else
untrail_addr_1 when dfc_trail_input = TI_unwind_trail_t else
TR_reg;
trailm_input_1 <= trail_a;
trailm_wr_1 <= trail_do;
trailm_rd_1 <= untrail_port_1_rd or trailm_wr_1;
trailm_addr_2 <= untrail_addr_2;
trailm_wr_2 <= '0';
trailm_rd_2 <= untrail_port_2_rd;
TRAIL: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kWamTrailAddressWidth
,kWordWidth => kWamAddressWidth
)
port map
(
clk => clk
,addr_port_1 => trailm_addr_1
,word_port_1_o => trailm_output_1
,word_port_1_i => trailm_input_1
,wr_port_1 => trailm_wr_1
,rd_port_1 => trailm_rd_1
,addr_port_2 => trailm_addr_2
,word_port_2_o => trailm_output_2
,word_port_2_i => trailm_input_2
,wr_port_2 => trailm_wr_2
,rd_port_2 => trailm_rd_2
);
untrail_start <= dfc_start_unwind;
untrail_a1 <= mem_output_1(kWamTrailAddressWidth -1 downto 0);
untrail_a2 <= TR_reg;
untrail_port_1 <= trailm_output_1;
untrail_port_2 <= trailm_output_2;
UNWINDTRAIL: entity work.UnwindTrailUnit(Behavioral)
port map
(
clk => clk
,rst => rst
,start_unwind => untrail_start
,a1 => untrail_a1
,a2 => untrail_a2
,trail_port_1 => untrail_port_1
,trail_port_1_rd => untrail_port_1_rd
,trail_addr_1 => untrail_addr_1
,trail_port_2 => untrail_port_2
,trail_port_2_rd => untrail_port_2_rd
,trail_addr_2 => untrail_addr_2
,mem_port_1 => untrail_mem_port_1
,mem_port_1_wr => untrail_mem_port_1_wr
,mem_addr_1 => untrail_mem_addr_1
,mem_port_2 => untrail_mem_port_2
,mem_port_2_wr => untrail_mem_port_2_wr
,mem_addr_2 => untrail_mem_addr_2
,done => untrail_done
);
bsearch_word <= deref1_res_out;
bsearch_low_addr <= bsearch_laddr_reg;
bsearch_high_addr <= bsearch_haddr_reg;
bsearch_start <= dfc_bsearch_start;
bsearch_memory_in <= bmem_port_1_out(kWamWordWidth+kWamInstrMemWidth -1 downto kWamInstrMemWidth);
BSEARCH: entity work.BinarySearch(Behavioral)
generic map
(
kWordWidth => kWamWordWidth
,kMemAddressWidth => kWamInstrMemWidth
)
port map
(
clk => clk
,rst => rst
,search_word => bsearch_word
,low_address => bsearch_low_addr
,high_address => bsearch_high_addr
,start_search => bsearch_start
,done => bsearch_done
,found => bsearch_found
,memory_in => bsearch_memory_in
,memory_address_out => bsearch_addr_out
,memory_read => bsearch_memory_read
);
bmem_addr_port_1 <= bsearch_addr_out;
bmem_port_1_rd <= bsearch_memory_read;
BMEM: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kWamInstrMemWidth
,kWordWidth => kWamWordWidth+kWamInstrMemWidth
)
port map
(
clk => clk
,addr_port_1 => bmem_addr_port_1
,word_port_1_o => bmem_port_1_out
,word_port_1_i => bmem_port_1_in
,wr_port_1 => bmem_port_1_wr
,rd_port_1 => bmem_port_1_rd
,addr_port_2 => bmem_addr_port_2
,word_port_2_o => bmem_port_2_out
,word_port_2_i => bmem_port_2_in
,wr_port_2 => bmem_port_2_wr
,rd_port_2 => bmem_port_2_rd
);
end Structural;
|
apache-2.0
|
3da3a045578b1c2cf3d0722855174772
| 0.633046 | 3.202482 | false | false | false | false |
kevintownsend/convey_spmv
|
rtl/mac/FPMultiplier_11_52_11_52_11_52_uid2.vhdl
| 1 | 206,136 |
-- flopoco multiplier pipeline: 11 clock cycles
--TODO: verilog instantiation
--------------------------------------------------------------------------------
-- IntAdder_42_f400_uid11
-- (IntAdderClassical_42_f400_uid13)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_42_f400_uid11 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(41 downto 0);
Y : in std_logic_vector(41 downto 0);
Cin : in std_logic;
R : out std_logic_vector(41 downto 0) );
end entity;
architecture arch of IntAdder_42_f400_uid11 is
signal X_d1 : std_logic_vector(41 downto 0);
signal Y_d1 : std_logic_vector(41 downto 0);
signal Cin_d1 : std_logic;
begin
process(clk)
begin
if clk'event and clk = '1' then
X_d1 <= X;
Y_d1 <= Y;
Cin_d1 <= Cin;
end if;
end process;
--Classical
----------------Synchro barrier, entering cycle 1----------------
R <= X_d1 + Y_d1 + Cin_d1;
end architecture;
--------------------------------------------------------------------------------
-- IntMultiAdder_42_op4_f400_uid7
-- (IntCompressorTree_42_4_uid9)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca (2009-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntMultiAdder_42_op4_f400_uid7 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(41 downto 0);
X1 : in std_logic_vector(41 downto 0);
X2 : in std_logic_vector(41 downto 0);
X3 : in std_logic_vector(41 downto 0);
R : out std_logic_vector(41 downto 0) );
end entity;
architecture arch of IntMultiAdder_42_op4_f400_uid7 is
component IntAdder_42_f400_uid11 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(41 downto 0);
Y : in std_logic_vector(41 downto 0);
Cin : in std_logic;
R : out std_logic_vector(41 downto 0) );
end component;
signal l_0_s_0, l_0_s_0_d1 : std_logic_vector(41 downto 0);
signal l_0_s_1, l_0_s_1_d1 : std_logic_vector(41 downto 0);
signal l_0_s_2, l_0_s_2_d1 : std_logic_vector(41 downto 0);
signal l_0_s_3, l_0_s_3_d1 : std_logic_vector(41 downto 0);
signal sell_1_c_0_cl_0 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_0 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_1 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_1 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_2 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_2 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_3 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_3 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_4 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_4 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_5 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_5 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_6 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_6 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_7 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_7 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_8 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_8 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_9 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_9 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_10 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_10 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_11 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_11 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_12 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_12 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_13 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_13 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_14 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_14 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_15 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_15 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_16 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_16 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_17 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_17 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_18 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_18 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_19 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_19 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_20 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_20 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_21 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_21 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_22 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_22 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_23 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_23 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_24 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_24 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_25 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_25 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_26 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_26 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_27 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_27 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_28 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_28 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_29 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_29 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_30 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_30 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_31 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_31 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_32 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_32 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_33 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_33 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_34 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_34 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_35 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_35 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_36 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_36 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_37 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_37 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_38 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_38 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_39 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_39 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_40 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_40 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_41 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_41 : std_logic_vector(2 downto 0);
signal l_1_s_0 : std_logic_vector(41 downto 0);
signal l_1_s_1 : std_logic_vector(41 downto 0);
signal l_1_s_2 : std_logic_vector(41 downto 0);
signal sell_2_c_0_cl_0 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_0 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_1 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_1 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_2 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_2 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_3 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_3 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_4 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_4 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_5 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_5 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_6 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_6 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_7 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_7 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_8 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_8 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_9 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_9 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_10 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_10 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_11 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_11 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_12 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_12 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_13 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_13 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_14 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_14 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_15 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_15 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_16 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_16 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_17 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_17 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_18 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_18 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_19 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_19 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_20 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_20 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_21 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_21 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_22 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_22 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_23 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_23 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_24 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_24 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_25 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_25 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_26 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_26 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_27 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_27 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_28 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_28 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_29 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_29 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_30 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_30 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_31 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_31 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_32 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_32 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_33 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_33 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_34 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_34 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_35 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_35 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_36 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_36 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_37 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_37 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_38 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_38 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_39 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_39 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_40 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_40 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_41 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_41 : std_logic_vector(1 downto 0);
signal l_2_s_0 : std_logic_vector(41 downto 0);
signal l_2_s_1 : std_logic_vector(41 downto 0);
signal myR : std_logic_vector(41 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
l_0_s_0_d1 <= l_0_s_0;
l_0_s_1_d1 <= l_0_s_1;
l_0_s_2_d1 <= l_0_s_2;
l_0_s_3_d1 <= l_0_s_3;
end if;
end process;
l_0_s_0 <= X0;
l_0_s_1 <= X1;
l_0_s_2 <= X2;
l_0_s_3 <= X3;
----------------Synchro barrier, entering cycle 1----------------
sell_1_c_0_cl_0 <= l_0_s_0_d1(0) & l_0_s_1_d1(0) & l_0_s_2_d1(0) & l_0_s_3_d1(0);
with sell_1_c_0_cl_0 select
l_1_c_0_cl_0 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_1 <= l_0_s_0_d1(1) & l_0_s_1_d1(1) & l_0_s_2_d1(1) & l_0_s_3_d1(1);
with sell_1_c_0_cl_1 select
l_1_c_0_cl_1 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_2 <= l_0_s_0_d1(2) & l_0_s_1_d1(2) & l_0_s_2_d1(2) & l_0_s_3_d1(2);
with sell_1_c_0_cl_2 select
l_1_c_0_cl_2 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_3 <= l_0_s_0_d1(3) & l_0_s_1_d1(3) & l_0_s_2_d1(3) & l_0_s_3_d1(3);
with sell_1_c_0_cl_3 select
l_1_c_0_cl_3 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_4 <= l_0_s_0_d1(4) & l_0_s_1_d1(4) & l_0_s_2_d1(4) & l_0_s_3_d1(4);
with sell_1_c_0_cl_4 select
l_1_c_0_cl_4 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_5 <= l_0_s_0_d1(5) & l_0_s_1_d1(5) & l_0_s_2_d1(5) & l_0_s_3_d1(5);
with sell_1_c_0_cl_5 select
l_1_c_0_cl_5 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_6 <= l_0_s_0_d1(6) & l_0_s_1_d1(6) & l_0_s_2_d1(6) & l_0_s_3_d1(6);
with sell_1_c_0_cl_6 select
l_1_c_0_cl_6 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_7 <= l_0_s_0_d1(7) & l_0_s_1_d1(7) & l_0_s_2_d1(7) & l_0_s_3_d1(7);
with sell_1_c_0_cl_7 select
l_1_c_0_cl_7 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_8 <= l_0_s_0_d1(8) & l_0_s_1_d1(8) & l_0_s_2_d1(8) & l_0_s_3_d1(8);
with sell_1_c_0_cl_8 select
l_1_c_0_cl_8 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_9 <= l_0_s_0_d1(9) & l_0_s_1_d1(9) & l_0_s_2_d1(9) & l_0_s_3_d1(9);
with sell_1_c_0_cl_9 select
l_1_c_0_cl_9 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_10 <= l_0_s_0_d1(10) & l_0_s_1_d1(10) & l_0_s_2_d1(10) & l_0_s_3_d1(10);
with sell_1_c_0_cl_10 select
l_1_c_0_cl_10 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_11 <= l_0_s_0_d1(11) & l_0_s_1_d1(11) & l_0_s_2_d1(11) & l_0_s_3_d1(11);
with sell_1_c_0_cl_11 select
l_1_c_0_cl_11 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_12 <= l_0_s_0_d1(12) & l_0_s_1_d1(12) & l_0_s_2_d1(12) & l_0_s_3_d1(12);
with sell_1_c_0_cl_12 select
l_1_c_0_cl_12 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_13 <= l_0_s_0_d1(13) & l_0_s_1_d1(13) & l_0_s_2_d1(13) & l_0_s_3_d1(13);
with sell_1_c_0_cl_13 select
l_1_c_0_cl_13 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_14 <= l_0_s_0_d1(14) & l_0_s_1_d1(14) & l_0_s_2_d1(14) & l_0_s_3_d1(14);
with sell_1_c_0_cl_14 select
l_1_c_0_cl_14 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_15 <= l_0_s_0_d1(15) & l_0_s_1_d1(15) & l_0_s_2_d1(15) & l_0_s_3_d1(15);
with sell_1_c_0_cl_15 select
l_1_c_0_cl_15 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_16 <= l_0_s_0_d1(16) & l_0_s_1_d1(16) & l_0_s_2_d1(16) & l_0_s_3_d1(16);
with sell_1_c_0_cl_16 select
l_1_c_0_cl_16 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_17 <= l_0_s_0_d1(17) & l_0_s_1_d1(17) & l_0_s_2_d1(17) & l_0_s_3_d1(17);
with sell_1_c_0_cl_17 select
l_1_c_0_cl_17 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_18 <= l_0_s_0_d1(18) & l_0_s_1_d1(18) & l_0_s_2_d1(18) & l_0_s_3_d1(18);
with sell_1_c_0_cl_18 select
l_1_c_0_cl_18 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_19 <= l_0_s_0_d1(19) & l_0_s_1_d1(19) & l_0_s_2_d1(19) & l_0_s_3_d1(19);
with sell_1_c_0_cl_19 select
l_1_c_0_cl_19 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_20 <= l_0_s_0_d1(20) & l_0_s_1_d1(20) & l_0_s_2_d1(20) & l_0_s_3_d1(20);
with sell_1_c_0_cl_20 select
l_1_c_0_cl_20 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_21 <= l_0_s_0_d1(21) & l_0_s_1_d1(21) & l_0_s_2_d1(21) & l_0_s_3_d1(21);
with sell_1_c_0_cl_21 select
l_1_c_0_cl_21 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_22 <= l_0_s_0_d1(22) & l_0_s_1_d1(22) & l_0_s_2_d1(22) & l_0_s_3_d1(22);
with sell_1_c_0_cl_22 select
l_1_c_0_cl_22 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_23 <= l_0_s_0_d1(23) & l_0_s_1_d1(23) & l_0_s_2_d1(23) & l_0_s_3_d1(23);
with sell_1_c_0_cl_23 select
l_1_c_0_cl_23 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_24 <= l_0_s_0_d1(24) & l_0_s_1_d1(24) & l_0_s_2_d1(24) & l_0_s_3_d1(24);
with sell_1_c_0_cl_24 select
l_1_c_0_cl_24 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_25 <= l_0_s_0_d1(25) & l_0_s_1_d1(25) & l_0_s_2_d1(25) & l_0_s_3_d1(25);
with sell_1_c_0_cl_25 select
l_1_c_0_cl_25 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_26 <= l_0_s_0_d1(26) & l_0_s_1_d1(26) & l_0_s_2_d1(26) & l_0_s_3_d1(26);
with sell_1_c_0_cl_26 select
l_1_c_0_cl_26 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_27 <= l_0_s_0_d1(27) & l_0_s_1_d1(27) & l_0_s_2_d1(27) & l_0_s_3_d1(27);
with sell_1_c_0_cl_27 select
l_1_c_0_cl_27 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_28 <= l_0_s_0_d1(28) & l_0_s_1_d1(28) & l_0_s_2_d1(28) & l_0_s_3_d1(28);
with sell_1_c_0_cl_28 select
l_1_c_0_cl_28 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_29 <= l_0_s_0_d1(29) & l_0_s_1_d1(29) & l_0_s_2_d1(29) & l_0_s_3_d1(29);
with sell_1_c_0_cl_29 select
l_1_c_0_cl_29 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_30 <= l_0_s_0_d1(30) & l_0_s_1_d1(30) & l_0_s_2_d1(30) & l_0_s_3_d1(30);
with sell_1_c_0_cl_30 select
l_1_c_0_cl_30 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_31 <= l_0_s_0_d1(31) & l_0_s_1_d1(31) & l_0_s_2_d1(31) & l_0_s_3_d1(31);
with sell_1_c_0_cl_31 select
l_1_c_0_cl_31 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_32 <= l_0_s_0_d1(32) & l_0_s_1_d1(32) & l_0_s_2_d1(32) & l_0_s_3_d1(32);
with sell_1_c_0_cl_32 select
l_1_c_0_cl_32 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_33 <= l_0_s_0_d1(33) & l_0_s_1_d1(33) & l_0_s_2_d1(33) & l_0_s_3_d1(33);
with sell_1_c_0_cl_33 select
l_1_c_0_cl_33 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_34 <= l_0_s_0_d1(34) & l_0_s_1_d1(34) & l_0_s_2_d1(34) & l_0_s_3_d1(34);
with sell_1_c_0_cl_34 select
l_1_c_0_cl_34 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_35 <= l_0_s_0_d1(35) & l_0_s_1_d1(35) & l_0_s_2_d1(35) & l_0_s_3_d1(35);
with sell_1_c_0_cl_35 select
l_1_c_0_cl_35 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_36 <= l_0_s_0_d1(36) & l_0_s_1_d1(36) & l_0_s_2_d1(36) & l_0_s_3_d1(36);
with sell_1_c_0_cl_36 select
l_1_c_0_cl_36 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_37 <= l_0_s_0_d1(37) & l_0_s_1_d1(37) & l_0_s_2_d1(37) & l_0_s_3_d1(37);
with sell_1_c_0_cl_37 select
l_1_c_0_cl_37 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_38 <= l_0_s_0_d1(38) & l_0_s_1_d1(38) & l_0_s_2_d1(38) & l_0_s_3_d1(38);
with sell_1_c_0_cl_38 select
l_1_c_0_cl_38 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_39 <= l_0_s_0_d1(39) & l_0_s_1_d1(39) & l_0_s_2_d1(39) & l_0_s_3_d1(39);
with sell_1_c_0_cl_39 select
l_1_c_0_cl_39 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_40 <= l_0_s_0_d1(40) & l_0_s_1_d1(40) & l_0_s_2_d1(40) & l_0_s_3_d1(40);
with sell_1_c_0_cl_40 select
l_1_c_0_cl_40 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_41 <= l_0_s_0_d1(41) & l_0_s_1_d1(41) & l_0_s_2_d1(41) & l_0_s_3_d1(41);
with sell_1_c_0_cl_41 select
l_1_c_0_cl_41 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
l_1_s_0 <= l_1_c_0_cl_41(0 downto 0) & l_1_c_0_cl_40(0 downto 0) & l_1_c_0_cl_39(0 downto 0) & l_1_c_0_cl_38(0 downto 0) & l_1_c_0_cl_37(0 downto 0) & l_1_c_0_cl_36(0 downto 0) & l_1_c_0_cl_35(0 downto 0) & l_1_c_0_cl_34(0 downto 0) & l_1_c_0_cl_33(0 downto 0) & l_1_c_0_cl_32(0 downto 0) & l_1_c_0_cl_31(0 downto 0) & l_1_c_0_cl_30(0 downto 0) & l_1_c_0_cl_29(0 downto 0) & l_1_c_0_cl_28(0 downto 0) & l_1_c_0_cl_27(0 downto 0) & l_1_c_0_cl_26(0 downto 0) & l_1_c_0_cl_25(0 downto 0) & l_1_c_0_cl_24(0 downto 0) & l_1_c_0_cl_23(0 downto 0) & l_1_c_0_cl_22(0 downto 0) & l_1_c_0_cl_21(0 downto 0) & l_1_c_0_cl_20(0 downto 0) & l_1_c_0_cl_19(0 downto 0) & l_1_c_0_cl_18(0 downto 0) & l_1_c_0_cl_17(0 downto 0) & l_1_c_0_cl_16(0 downto 0) & l_1_c_0_cl_15(0 downto 0) & l_1_c_0_cl_14(0 downto 0) & l_1_c_0_cl_13(0 downto 0) & l_1_c_0_cl_12(0 downto 0) & l_1_c_0_cl_11(0 downto 0) & l_1_c_0_cl_10(0 downto 0) & l_1_c_0_cl_9(0 downto 0) & l_1_c_0_cl_8(0 downto 0) & l_1_c_0_cl_7(0 downto 0) & l_1_c_0_cl_6(0 downto 0) & l_1_c_0_cl_5(0 downto 0) & l_1_c_0_cl_4(0 downto 0) & l_1_c_0_cl_3(0 downto 0) & l_1_c_0_cl_2(0 downto 0) & l_1_c_0_cl_1(0 downto 0) & l_1_c_0_cl_0(0 downto 0);
l_1_s_1 <= l_1_c_0_cl_40(1 downto 1) & l_1_c_0_cl_39(1 downto 1) & l_1_c_0_cl_38(1 downto 1) & l_1_c_0_cl_37(1 downto 1) & l_1_c_0_cl_36(1 downto 1) & l_1_c_0_cl_35(1 downto 1) & l_1_c_0_cl_34(1 downto 1) & l_1_c_0_cl_33(1 downto 1) & l_1_c_0_cl_32(1 downto 1) & l_1_c_0_cl_31(1 downto 1) & l_1_c_0_cl_30(1 downto 1) & l_1_c_0_cl_29(1 downto 1) & l_1_c_0_cl_28(1 downto 1) & l_1_c_0_cl_27(1 downto 1) & l_1_c_0_cl_26(1 downto 1) & l_1_c_0_cl_25(1 downto 1) & l_1_c_0_cl_24(1 downto 1) & l_1_c_0_cl_23(1 downto 1) & l_1_c_0_cl_22(1 downto 1) & l_1_c_0_cl_21(1 downto 1) & l_1_c_0_cl_20(1 downto 1) & l_1_c_0_cl_19(1 downto 1) & l_1_c_0_cl_18(1 downto 1) & l_1_c_0_cl_17(1 downto 1) & l_1_c_0_cl_16(1 downto 1) & l_1_c_0_cl_15(1 downto 1) & l_1_c_0_cl_14(1 downto 1) & l_1_c_0_cl_13(1 downto 1) & l_1_c_0_cl_12(1 downto 1) & l_1_c_0_cl_11(1 downto 1) & l_1_c_0_cl_10(1 downto 1) & l_1_c_0_cl_9(1 downto 1) & l_1_c_0_cl_8(1 downto 1) & l_1_c_0_cl_7(1 downto 1) & l_1_c_0_cl_6(1 downto 1) & l_1_c_0_cl_5(1 downto 1) & l_1_c_0_cl_4(1 downto 1) & l_1_c_0_cl_3(1 downto 1) & l_1_c_0_cl_2(1 downto 1) & l_1_c_0_cl_1(1 downto 1) & l_1_c_0_cl_0(1 downto 1) & "0";
l_1_s_2 <= l_1_c_0_cl_39(2 downto 2) & l_1_c_0_cl_38(2 downto 2) & l_1_c_0_cl_37(2 downto 2) & l_1_c_0_cl_36(2 downto 2) & l_1_c_0_cl_35(2 downto 2) & l_1_c_0_cl_34(2 downto 2) & l_1_c_0_cl_33(2 downto 2) & l_1_c_0_cl_32(2 downto 2) & l_1_c_0_cl_31(2 downto 2) & l_1_c_0_cl_30(2 downto 2) & l_1_c_0_cl_29(2 downto 2) & l_1_c_0_cl_28(2 downto 2) & l_1_c_0_cl_27(2 downto 2) & l_1_c_0_cl_26(2 downto 2) & l_1_c_0_cl_25(2 downto 2) & l_1_c_0_cl_24(2 downto 2) & l_1_c_0_cl_23(2 downto 2) & l_1_c_0_cl_22(2 downto 2) & l_1_c_0_cl_21(2 downto 2) & l_1_c_0_cl_20(2 downto 2) & l_1_c_0_cl_19(2 downto 2) & l_1_c_0_cl_18(2 downto 2) & l_1_c_0_cl_17(2 downto 2) & l_1_c_0_cl_16(2 downto 2) & l_1_c_0_cl_15(2 downto 2) & l_1_c_0_cl_14(2 downto 2) & l_1_c_0_cl_13(2 downto 2) & l_1_c_0_cl_12(2 downto 2) & l_1_c_0_cl_11(2 downto 2) & l_1_c_0_cl_10(2 downto 2) & l_1_c_0_cl_9(2 downto 2) & l_1_c_0_cl_8(2 downto 2) & l_1_c_0_cl_7(2 downto 2) & l_1_c_0_cl_6(2 downto 2) & l_1_c_0_cl_5(2 downto 2) & l_1_c_0_cl_4(2 downto 2) & l_1_c_0_cl_3(2 downto 2) & l_1_c_0_cl_2(2 downto 2) & l_1_c_0_cl_1(2 downto 2) & l_1_c_0_cl_0(2 downto 2) & "00";
sell_2_c_0_cl_0 <= l_1_s_0(0) & l_1_s_1(0) & l_1_s_2(0);
with sell_2_c_0_cl_0 select
l_2_c_0_cl_0 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_1 <= l_1_s_0(1) & l_1_s_1(1) & l_1_s_2(1);
with sell_2_c_0_cl_1 select
l_2_c_0_cl_1 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_2 <= l_1_s_0(2) & l_1_s_1(2) & l_1_s_2(2);
with sell_2_c_0_cl_2 select
l_2_c_0_cl_2 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_3 <= l_1_s_0(3) & l_1_s_1(3) & l_1_s_2(3);
with sell_2_c_0_cl_3 select
l_2_c_0_cl_3 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_4 <= l_1_s_0(4) & l_1_s_1(4) & l_1_s_2(4);
with sell_2_c_0_cl_4 select
l_2_c_0_cl_4 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_5 <= l_1_s_0(5) & l_1_s_1(5) & l_1_s_2(5);
with sell_2_c_0_cl_5 select
l_2_c_0_cl_5 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_6 <= l_1_s_0(6) & l_1_s_1(6) & l_1_s_2(6);
with sell_2_c_0_cl_6 select
l_2_c_0_cl_6 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_7 <= l_1_s_0(7) & l_1_s_1(7) & l_1_s_2(7);
with sell_2_c_0_cl_7 select
l_2_c_0_cl_7 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_8 <= l_1_s_0(8) & l_1_s_1(8) & l_1_s_2(8);
with sell_2_c_0_cl_8 select
l_2_c_0_cl_8 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_9 <= l_1_s_0(9) & l_1_s_1(9) & l_1_s_2(9);
with sell_2_c_0_cl_9 select
l_2_c_0_cl_9 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_10 <= l_1_s_0(10) & l_1_s_1(10) & l_1_s_2(10);
with sell_2_c_0_cl_10 select
l_2_c_0_cl_10 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_11 <= l_1_s_0(11) & l_1_s_1(11) & l_1_s_2(11);
with sell_2_c_0_cl_11 select
l_2_c_0_cl_11 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_12 <= l_1_s_0(12) & l_1_s_1(12) & l_1_s_2(12);
with sell_2_c_0_cl_12 select
l_2_c_0_cl_12 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_13 <= l_1_s_0(13) & l_1_s_1(13) & l_1_s_2(13);
with sell_2_c_0_cl_13 select
l_2_c_0_cl_13 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_14 <= l_1_s_0(14) & l_1_s_1(14) & l_1_s_2(14);
with sell_2_c_0_cl_14 select
l_2_c_0_cl_14 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_15 <= l_1_s_0(15) & l_1_s_1(15) & l_1_s_2(15);
with sell_2_c_0_cl_15 select
l_2_c_0_cl_15 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_16 <= l_1_s_0(16) & l_1_s_1(16) & l_1_s_2(16);
with sell_2_c_0_cl_16 select
l_2_c_0_cl_16 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_17 <= l_1_s_0(17) & l_1_s_1(17) & l_1_s_2(17);
with sell_2_c_0_cl_17 select
l_2_c_0_cl_17 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_18 <= l_1_s_0(18) & l_1_s_1(18) & l_1_s_2(18);
with sell_2_c_0_cl_18 select
l_2_c_0_cl_18 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_19 <= l_1_s_0(19) & l_1_s_1(19) & l_1_s_2(19);
with sell_2_c_0_cl_19 select
l_2_c_0_cl_19 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_20 <= l_1_s_0(20) & l_1_s_1(20) & l_1_s_2(20);
with sell_2_c_0_cl_20 select
l_2_c_0_cl_20 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_21 <= l_1_s_0(21) & l_1_s_1(21) & l_1_s_2(21);
with sell_2_c_0_cl_21 select
l_2_c_0_cl_21 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_22 <= l_1_s_0(22) & l_1_s_1(22) & l_1_s_2(22);
with sell_2_c_0_cl_22 select
l_2_c_0_cl_22 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_23 <= l_1_s_0(23) & l_1_s_1(23) & l_1_s_2(23);
with sell_2_c_0_cl_23 select
l_2_c_0_cl_23 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_24 <= l_1_s_0(24) & l_1_s_1(24) & l_1_s_2(24);
with sell_2_c_0_cl_24 select
l_2_c_0_cl_24 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_25 <= l_1_s_0(25) & l_1_s_1(25) & l_1_s_2(25);
with sell_2_c_0_cl_25 select
l_2_c_0_cl_25 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_26 <= l_1_s_0(26) & l_1_s_1(26) & l_1_s_2(26);
with sell_2_c_0_cl_26 select
l_2_c_0_cl_26 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_27 <= l_1_s_0(27) & l_1_s_1(27) & l_1_s_2(27);
with sell_2_c_0_cl_27 select
l_2_c_0_cl_27 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_28 <= l_1_s_0(28) & l_1_s_1(28) & l_1_s_2(28);
with sell_2_c_0_cl_28 select
l_2_c_0_cl_28 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_29 <= l_1_s_0(29) & l_1_s_1(29) & l_1_s_2(29);
with sell_2_c_0_cl_29 select
l_2_c_0_cl_29 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_30 <= l_1_s_0(30) & l_1_s_1(30) & l_1_s_2(30);
with sell_2_c_0_cl_30 select
l_2_c_0_cl_30 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_31 <= l_1_s_0(31) & l_1_s_1(31) & l_1_s_2(31);
with sell_2_c_0_cl_31 select
l_2_c_0_cl_31 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_32 <= l_1_s_0(32) & l_1_s_1(32) & l_1_s_2(32);
with sell_2_c_0_cl_32 select
l_2_c_0_cl_32 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_33 <= l_1_s_0(33) & l_1_s_1(33) & l_1_s_2(33);
with sell_2_c_0_cl_33 select
l_2_c_0_cl_33 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_34 <= l_1_s_0(34) & l_1_s_1(34) & l_1_s_2(34);
with sell_2_c_0_cl_34 select
l_2_c_0_cl_34 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_35 <= l_1_s_0(35) & l_1_s_1(35) & l_1_s_2(35);
with sell_2_c_0_cl_35 select
l_2_c_0_cl_35 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_36 <= l_1_s_0(36) & l_1_s_1(36) & l_1_s_2(36);
with sell_2_c_0_cl_36 select
l_2_c_0_cl_36 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_37 <= l_1_s_0(37) & l_1_s_1(37) & l_1_s_2(37);
with sell_2_c_0_cl_37 select
l_2_c_0_cl_37 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_38 <= l_1_s_0(38) & l_1_s_1(38) & l_1_s_2(38);
with sell_2_c_0_cl_38 select
l_2_c_0_cl_38 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_39 <= l_1_s_0(39) & l_1_s_1(39) & l_1_s_2(39);
with sell_2_c_0_cl_39 select
l_2_c_0_cl_39 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_40 <= l_1_s_0(40) & l_1_s_1(40) & l_1_s_2(40);
with sell_2_c_0_cl_40 select
l_2_c_0_cl_40 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_41 <= l_1_s_0(41) & l_1_s_1(41) & l_1_s_2(41);
with sell_2_c_0_cl_41 select
l_2_c_0_cl_41 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
l_2_s_0 <= l_2_c_0_cl_41(0 downto 0) & l_2_c_0_cl_40(0 downto 0) & l_2_c_0_cl_39(0 downto 0) & l_2_c_0_cl_38(0 downto 0) & l_2_c_0_cl_37(0 downto 0) & l_2_c_0_cl_36(0 downto 0) & l_2_c_0_cl_35(0 downto 0) & l_2_c_0_cl_34(0 downto 0) & l_2_c_0_cl_33(0 downto 0) & l_2_c_0_cl_32(0 downto 0) & l_2_c_0_cl_31(0 downto 0) & l_2_c_0_cl_30(0 downto 0) & l_2_c_0_cl_29(0 downto 0) & l_2_c_0_cl_28(0 downto 0) & l_2_c_0_cl_27(0 downto 0) & l_2_c_0_cl_26(0 downto 0) & l_2_c_0_cl_25(0 downto 0) & l_2_c_0_cl_24(0 downto 0) & l_2_c_0_cl_23(0 downto 0) & l_2_c_0_cl_22(0 downto 0) & l_2_c_0_cl_21(0 downto 0) & l_2_c_0_cl_20(0 downto 0) & l_2_c_0_cl_19(0 downto 0) & l_2_c_0_cl_18(0 downto 0) & l_2_c_0_cl_17(0 downto 0) & l_2_c_0_cl_16(0 downto 0) & l_2_c_0_cl_15(0 downto 0) & l_2_c_0_cl_14(0 downto 0) & l_2_c_0_cl_13(0 downto 0) & l_2_c_0_cl_12(0 downto 0) & l_2_c_0_cl_11(0 downto 0) & l_2_c_0_cl_10(0 downto 0) & l_2_c_0_cl_9(0 downto 0) & l_2_c_0_cl_8(0 downto 0) & l_2_c_0_cl_7(0 downto 0) & l_2_c_0_cl_6(0 downto 0) & l_2_c_0_cl_5(0 downto 0) & l_2_c_0_cl_4(0 downto 0) & l_2_c_0_cl_3(0 downto 0) & l_2_c_0_cl_2(0 downto 0) & l_2_c_0_cl_1(0 downto 0) & l_2_c_0_cl_0(0 downto 0);
l_2_s_1 <= l_2_c_0_cl_40(1 downto 1) & l_2_c_0_cl_39(1 downto 1) & l_2_c_0_cl_38(1 downto 1) & l_2_c_0_cl_37(1 downto 1) & l_2_c_0_cl_36(1 downto 1) & l_2_c_0_cl_35(1 downto 1) & l_2_c_0_cl_34(1 downto 1) & l_2_c_0_cl_33(1 downto 1) & l_2_c_0_cl_32(1 downto 1) & l_2_c_0_cl_31(1 downto 1) & l_2_c_0_cl_30(1 downto 1) & l_2_c_0_cl_29(1 downto 1) & l_2_c_0_cl_28(1 downto 1) & l_2_c_0_cl_27(1 downto 1) & l_2_c_0_cl_26(1 downto 1) & l_2_c_0_cl_25(1 downto 1) & l_2_c_0_cl_24(1 downto 1) & l_2_c_0_cl_23(1 downto 1) & l_2_c_0_cl_22(1 downto 1) & l_2_c_0_cl_21(1 downto 1) & l_2_c_0_cl_20(1 downto 1) & l_2_c_0_cl_19(1 downto 1) & l_2_c_0_cl_18(1 downto 1) & l_2_c_0_cl_17(1 downto 1) & l_2_c_0_cl_16(1 downto 1) & l_2_c_0_cl_15(1 downto 1) & l_2_c_0_cl_14(1 downto 1) & l_2_c_0_cl_13(1 downto 1) & l_2_c_0_cl_12(1 downto 1) & l_2_c_0_cl_11(1 downto 1) & l_2_c_0_cl_10(1 downto 1) & l_2_c_0_cl_9(1 downto 1) & l_2_c_0_cl_8(1 downto 1) & l_2_c_0_cl_7(1 downto 1) & l_2_c_0_cl_6(1 downto 1) & l_2_c_0_cl_5(1 downto 1) & l_2_c_0_cl_4(1 downto 1) & l_2_c_0_cl_3(1 downto 1) & l_2_c_0_cl_2(1 downto 1) & l_2_c_0_cl_1(1 downto 1) & l_2_c_0_cl_0(1 downto 1) & "0";
FinalAdder_CompressorTree: IntAdder_42_f400_uid11 -- pipelineDepth=1 maxInDelay=1.59336e-09
port map ( clk => clk,
rst => rst,
Cin => '0',
R => myR,
X => l_2_s_0,
Y => l_2_s_1);
----------------Synchro barrier, entering cycle 2----------------
R <= myR;
-- delay at adder output 1.634e-09
end architecture;
--------------------------------------------------------------------------------
-- LogicIntMultiplier_5_34_uid5_0
-- (LogicIntMultiplier_5_34_uid5)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Sebastian Banescu (2008-2009)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity LogicIntMultiplier_5_34_uid5_0 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(4 downto 0);
Y : in std_logic_vector(33 downto 0);
R : out std_logic_vector(38 downto 0) );
end entity;
architecture arch of LogicIntMultiplier_5_34_uid5_0 is
attribute multstyle : string;
attribute multstyle of arch : architecture is "logic";
component IntMultiAdder_42_op4_f400_uid7 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(41 downto 0);
X1 : in std_logic_vector(41 downto 0);
X2 : in std_logic_vector(41 downto 0);
X3 : in std_logic_vector(41 downto 0);
R : out std_logic_vector(41 downto 0) );
end component;
signal sX : std_logic_vector(5 downto 0);
signal sY : std_logic_vector(35 downto 0);
signal x0, x0_d1 : std_logic_vector(2 downto 0);
signal x1, x1_d1 : std_logic_vector(2 downto 0);
signal y0, y0_d1 : std_logic_vector(2 downto 0);
signal y1, y1_d1 : std_logic_vector(2 downto 0);
signal y2, y2_d1 : std_logic_vector(2 downto 0);
signal y3, y3_d1 : std_logic_vector(2 downto 0);
signal y4, y4_d1 : std_logic_vector(2 downto 0);
signal y5, y5_d1 : std_logic_vector(2 downto 0);
signal y6, y6_d1 : std_logic_vector(2 downto 0);
signal y7, y7_d1 : std_logic_vector(2 downto 0);
signal y8, y8_d1 : std_logic_vector(2 downto 0);
signal y9, y9_d1 : std_logic_vector(2 downto 0);
signal y10, y10_d1 : std_logic_vector(2 downto 0);
signal y11, y11_d1 : std_logic_vector(2 downto 0);
signal px0y0 : std_logic_vector(5 downto 0);
signal px1y0 : std_logic_vector(5 downto 0);
signal px0y1 : std_logic_vector(5 downto 0);
signal px1y1 : std_logic_vector(5 downto 0);
signal px0y2 : std_logic_vector(5 downto 0);
signal px1y2 : std_logic_vector(5 downto 0);
signal px0y3 : std_logic_vector(5 downto 0);
signal px1y3 : std_logic_vector(5 downto 0);
signal px0y4 : std_logic_vector(5 downto 0);
signal px1y4 : std_logic_vector(5 downto 0);
signal px0y5 : std_logic_vector(5 downto 0);
signal px1y5 : std_logic_vector(5 downto 0);
signal px0y6 : std_logic_vector(5 downto 0);
signal px1y6 : std_logic_vector(5 downto 0);
signal px0y7 : std_logic_vector(5 downto 0);
signal px1y7 : std_logic_vector(5 downto 0);
signal px0y8 : std_logic_vector(5 downto 0);
signal px1y8 : std_logic_vector(5 downto 0);
signal px0y9 : std_logic_vector(5 downto 0);
signal px1y9 : std_logic_vector(5 downto 0);
signal px0y10 : std_logic_vector(5 downto 0);
signal px1y10 : std_logic_vector(5 downto 0);
signal px0y11 : std_logic_vector(5 downto 0);
signal px1y11 : std_logic_vector(5 downto 0);
signal cp00 : std_logic_vector(41 downto 0);
signal cp01 : std_logic_vector(41 downto 0);
signal cp10 : std_logic_vector(41 downto 0);
signal cp11 : std_logic_vector(41 downto 0);
signal addRes : std_logic_vector(41 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x0_d1 <= x0;
x1_d1 <= x1;
y0_d1 <= y0;
y1_d1 <= y1;
y2_d1 <= y2;
y3_d1 <= y3;
y4_d1 <= y4;
y5_d1 <= y5;
y6_d1 <= y6;
y7_d1 <= y7;
y8_d1 <= y8;
y9_d1 <= y9;
y10_d1 <= y10;
y11_d1 <= y11;
end if;
end process;
sX <= X & "0";
sY <= Y & "00";
x0 <= sX(2 downto 0);
x1 <= sX(5 downto 3);
y0 <= sY(2 downto 0);
y1 <= sY(5 downto 3);
y2 <= sY(8 downto 6);
y3 <= sY(11 downto 9);
y4 <= sY(14 downto 12);
y5 <= sY(17 downto 15);
y6 <= sY(20 downto 18);
y7 <= sY(23 downto 21);
y8 <= sY(26 downto 24);
y9 <= sY(29 downto 27);
y10 <= sY(32 downto 30);
y11 <= sY(35 downto 33);
----------------Synchro barrier, entering cycle 1----------------
px0y0 <= x0_d1 * y0_d1;
px1y0 <= x1_d1 * y0_d1;
px0y1 <= x0_d1 * y1_d1;
px1y1 <= x1_d1 * y1_d1;
px0y2 <= x0_d1 * y2_d1;
px1y2 <= x1_d1 * y2_d1;
px0y3 <= x0_d1 * y3_d1;
px1y3 <= x1_d1 * y3_d1;
px0y4 <= x0_d1 * y4_d1;
px1y4 <= x1_d1 * y4_d1;
px0y5 <= x0_d1 * y5_d1;
px1y5 <= x1_d1 * y5_d1;
px0y6 <= x0_d1 * y6_d1;
px1y6 <= x1_d1 * y6_d1;
px0y7 <= x0_d1 * y7_d1;
px1y7 <= x1_d1 * y7_d1;
px0y8 <= x0_d1 * y8_d1;
px1y8 <= x1_d1 * y8_d1;
px0y9 <= x0_d1 * y9_d1;
px1y9 <= x1_d1 * y9_d1;
px0y10 <= x0_d1 * y10_d1;
px1y10 <= x1_d1 * y10_d1;
px0y11 <= x0_d1 * y11_d1;
px1y11 <= x1_d1 * y11_d1;
cp00 <= "000" & px0y11 & px0y9 & px0y7 & px0y5 & px0y3 & px0y1 & "000";
cp01 <= "" & px1y11 & px1y9 & px1y7 & px1y5 & px1y3 & px1y1 & "000000";
cp10 <= "000000" & px0y10 & px0y8 & px0y6 & px0y4 & px0y2 & px0y0 & "";
cp11 <= "000" & px1y10 & px1y8 & px1y6 & px1y4 & px1y2 & px1y0 & "000";
adder: IntMultiAdder_42_op4_f400_uid7 -- pipelineDepth=2 maxInDelay=2.5e-09
port map ( clk => clk,
rst => rst,
R => addRes,
X0 => cp00,
X1 => cp01,
X2 => cp10,
X3 => cp11);
----------------Synchro barrier, entering cycle 3----------------
R<=addRes(41 downto 3);
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_26_f400_uid19
-- (IntAdderAlternative_26_f400_uid23)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_26_f400_uid19 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(25 downto 0);
Y : in std_logic_vector(25 downto 0);
Cin : in std_logic;
R : out std_logic_vector(25 downto 0) );
end entity;
architecture arch of IntAdder_26_f400_uid19 is
begin
process(clk)
begin
if clk'event and clk = '1' then
end if;
end process;
--Alternative
R <= X + Y + Cin;
end architecture;
--------------------------------------------------------------------------------
-- LogicIntMultiplier_24_2_uid17_1
-- (LogicIntMultiplier_24_2_uid17)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Sebastian Banescu (2008-2009)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity LogicIntMultiplier_24_2_uid17_1 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(23 downto 0);
Y : in std_logic_vector(1 downto 0);
R : out std_logic_vector(25 downto 0) );
end entity;
architecture arch of LogicIntMultiplier_24_2_uid17_1 is
attribute multstyle : string;
attribute multstyle of arch : architecture is "logic";
component IntAdder_26_f400_uid19 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(25 downto 0);
Y : in std_logic_vector(25 downto 0);
Cin : in std_logic;
R : out std_logic_vector(25 downto 0) );
end component;
signal R0 : std_logic_vector(25 downto 0);
signal R1 : std_logic_vector(25 downto 0);
signal RAdder : std_logic_vector(25 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
end if;
end process;
R0 <= ("00" & X) when Y(0)='1' else "00000000000000000000000000";
R1 <= ( "0" & X & "0") when Y(1)='1' else "00000000000000000000000000";
ResultAdder: IntAdder_26_f400_uid19 -- pipelineDepth=0 maxInDelay=9.7544e-10
port map ( clk => clk,
rst => rst,
Cin => '0',
R => RAdder ,
X => R0,
Y => R1);
R <= RAdder;
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_106_f400_uid29
-- (IntAdderClassical_106_f400_uid31)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 3 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_106_f400_uid29 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(105 downto 0);
Y : in std_logic_vector(105 downto 0);
Cin : in std_logic;
R : out std_logic_vector(105 downto 0) );
end entity;
architecture arch of IntAdder_106_f400_uid29 is
signal x0 : std_logic_vector(41 downto 0);
signal y0 : std_logic_vector(41 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(21 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(21 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(42 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(22 downto 0);
signal X_d1 : std_logic_vector(105 downto 0);
signal Y_d1 : std_logic_vector(105 downto 0);
signal Cin_d1 : std_logic;
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
X_d1 <= X;
Y_d1 <= Y;
Cin_d1 <= Cin;
end if;
end process;
--Classical
----------------Synchro barrier, entering cycle 1----------------
x0 <= X_d1(41 downto 0);
y0 <= Y_d1(41 downto 0);
x1 <= X_d1(83 downto 42);
y1 <= Y_d1(83 downto 42);
x2 <= X_d1(105 downto 84);
y2 <= Y_d1(105 downto 84);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin_d1;
----------------Synchro barrier, entering cycle 2----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(42);
----------------Synchro barrier, entering cycle 3----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(21 downto 0) & sum1_d1(41 downto 0) & sum0_d2(41 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- IntMultiAdder_106_op4_f400_uid25
-- (IntCompressorTree_106_4_uid27)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca (2009-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 3 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntMultiAdder_106_op4_f400_uid25 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(105 downto 0);
X1 : in std_logic_vector(105 downto 0);
X2 : in std_logic_vector(105 downto 0);
X3 : in std_logic_vector(105 downto 0);
R : out std_logic_vector(105 downto 0) );
end entity;
architecture arch of IntMultiAdder_106_op4_f400_uid25 is
component IntAdder_106_f400_uid29 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(105 downto 0);
Y : in std_logic_vector(105 downto 0);
Cin : in std_logic;
R : out std_logic_vector(105 downto 0) );
end component;
signal l_0_s_0 : std_logic_vector(105 downto 0);
signal l_0_s_1 : std_logic_vector(105 downto 0);
signal l_0_s_2 : std_logic_vector(105 downto 0);
signal l_0_s_3 : std_logic_vector(105 downto 0);
signal sell_1_c_0_cl_0 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_0 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_1 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_1 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_2 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_2 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_3 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_3 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_4 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_4 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_5 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_5 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_6 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_6 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_7 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_7 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_8 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_8 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_9 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_9 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_10 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_10 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_11 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_11 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_12 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_12 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_13 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_13 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_14 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_14 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_15 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_15 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_16 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_16 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_17 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_17 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_18 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_18 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_19 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_19 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_20 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_20 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_21 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_21 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_22 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_22 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_23 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_23 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_24 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_24 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_25 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_25 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_26 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_26 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_27 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_27 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_28 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_28 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_29 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_29 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_30 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_30 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_31 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_31 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_32 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_32 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_33 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_33 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_34 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_34 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_35 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_35 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_36 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_36 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_37 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_37 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_38 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_38 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_39 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_39 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_40 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_40 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_41 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_41 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_42 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_42 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_43 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_43 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_44 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_44 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_45 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_45 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_46 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_46 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_47 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_47 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_48 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_48 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_49 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_49 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_50 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_50 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_51 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_51 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_52 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_52 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_53 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_53 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_54 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_54 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_55 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_55 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_56 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_56 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_57 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_57 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_58 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_58 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_59 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_59 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_60 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_60 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_61 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_61 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_62 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_62 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_63 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_63 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_64 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_64 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_65 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_65 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_66 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_66 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_67 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_67 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_68 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_68 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_69 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_69 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_70 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_70 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_71 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_71 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_72 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_72 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_73 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_73 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_74 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_74 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_75 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_75 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_76 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_76 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_77 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_77 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_78 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_78 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_79 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_79 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_80 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_80 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_81 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_81 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_82 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_82 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_83 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_83 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_84 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_84 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_85 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_85 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_86 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_86 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_87 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_87 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_88 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_88 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_89 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_89 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_90 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_90 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_91 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_91 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_92 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_92 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_93 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_93 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_94 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_94 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_95 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_95 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_96 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_96 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_97 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_97 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_98 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_98 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_99 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_99 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_100 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_100 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_101 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_101 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_102 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_102 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_103 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_103 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_104 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_104 : std_logic_vector(2 downto 0);
signal sell_1_c_0_cl_105 : std_logic_vector(3 downto 0);
signal l_1_c_0_cl_105 : std_logic_vector(2 downto 0);
signal l_1_s_0 : std_logic_vector(105 downto 0);
signal l_1_s_1 : std_logic_vector(105 downto 0);
signal l_1_s_2 : std_logic_vector(105 downto 0);
signal sell_2_c_0_cl_0 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_0 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_1 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_1 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_2 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_2 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_3 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_3 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_4 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_4 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_5 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_5 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_6 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_6 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_7 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_7 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_8 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_8 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_9 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_9 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_10 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_10 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_11 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_11 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_12 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_12 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_13 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_13 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_14 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_14 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_15 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_15 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_16 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_16 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_17 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_17 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_18 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_18 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_19 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_19 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_20 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_20 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_21 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_21 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_22 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_22 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_23 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_23 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_24 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_24 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_25 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_25 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_26 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_26 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_27 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_27 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_28 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_28 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_29 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_29 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_30 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_30 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_31 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_31 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_32 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_32 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_33 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_33 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_34 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_34 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_35 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_35 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_36 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_36 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_37 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_37 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_38 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_38 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_39 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_39 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_40 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_40 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_41 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_41 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_42 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_42 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_43 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_43 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_44 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_44 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_45 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_45 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_46 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_46 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_47 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_47 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_48 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_48 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_49 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_49 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_50 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_50 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_51 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_51 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_52 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_52 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_53 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_53 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_54 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_54 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_55 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_55 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_56 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_56 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_57 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_57 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_58 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_58 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_59 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_59 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_60 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_60 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_61 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_61 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_62 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_62 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_63 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_63 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_64 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_64 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_65 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_65 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_66 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_66 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_67 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_67 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_68 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_68 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_69 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_69 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_70 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_70 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_71 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_71 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_72 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_72 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_73 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_73 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_74 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_74 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_75 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_75 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_76 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_76 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_77 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_77 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_78 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_78 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_79 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_79 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_80 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_80 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_81 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_81 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_82 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_82 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_83 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_83 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_84 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_84 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_85 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_85 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_86 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_86 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_87 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_87 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_88 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_88 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_89 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_89 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_90 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_90 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_91 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_91 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_92 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_92 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_93 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_93 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_94 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_94 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_95 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_95 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_96 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_96 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_97 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_97 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_98 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_98 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_99 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_99 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_100 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_100 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_101 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_101 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_102 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_102 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_103 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_103 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_104 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_104 : std_logic_vector(1 downto 0);
signal sell_2_c_0_cl_105 : std_logic_vector(2 downto 0);
signal l_2_c_0_cl_105 : std_logic_vector(1 downto 0);
signal l_2_s_0 : std_logic_vector(105 downto 0);
signal l_2_s_1 : std_logic_vector(105 downto 0);
signal myR : std_logic_vector(105 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
end if;
end process;
l_0_s_0 <= X0;
l_0_s_1 <= X1;
l_0_s_2 <= X2;
l_0_s_3 <= X3;
sell_1_c_0_cl_0 <= l_0_s_0(0) & l_0_s_1(0) & l_0_s_2(0) & l_0_s_3(0);
with sell_1_c_0_cl_0 select
l_1_c_0_cl_0 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_1 <= l_0_s_0(1) & l_0_s_1(1) & l_0_s_2(1) & l_0_s_3(1);
with sell_1_c_0_cl_1 select
l_1_c_0_cl_1 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_2 <= l_0_s_0(2) & l_0_s_1(2) & l_0_s_2(2) & l_0_s_3(2);
with sell_1_c_0_cl_2 select
l_1_c_0_cl_2 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_3 <= l_0_s_0(3) & l_0_s_1(3) & l_0_s_2(3) & l_0_s_3(3);
with sell_1_c_0_cl_3 select
l_1_c_0_cl_3 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_4 <= l_0_s_0(4) & l_0_s_1(4) & l_0_s_2(4) & l_0_s_3(4);
with sell_1_c_0_cl_4 select
l_1_c_0_cl_4 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_5 <= l_0_s_0(5) & l_0_s_1(5) & l_0_s_2(5) & l_0_s_3(5);
with sell_1_c_0_cl_5 select
l_1_c_0_cl_5 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_6 <= l_0_s_0(6) & l_0_s_1(6) & l_0_s_2(6) & l_0_s_3(6);
with sell_1_c_0_cl_6 select
l_1_c_0_cl_6 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_7 <= l_0_s_0(7) & l_0_s_1(7) & l_0_s_2(7) & l_0_s_3(7);
with sell_1_c_0_cl_7 select
l_1_c_0_cl_7 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_8 <= l_0_s_0(8) & l_0_s_1(8) & l_0_s_2(8) & l_0_s_3(8);
with sell_1_c_0_cl_8 select
l_1_c_0_cl_8 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_9 <= l_0_s_0(9) & l_0_s_1(9) & l_0_s_2(9) & l_0_s_3(9);
with sell_1_c_0_cl_9 select
l_1_c_0_cl_9 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_10 <= l_0_s_0(10) & l_0_s_1(10) & l_0_s_2(10) & l_0_s_3(10);
with sell_1_c_0_cl_10 select
l_1_c_0_cl_10 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_11 <= l_0_s_0(11) & l_0_s_1(11) & l_0_s_2(11) & l_0_s_3(11);
with sell_1_c_0_cl_11 select
l_1_c_0_cl_11 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_12 <= l_0_s_0(12) & l_0_s_1(12) & l_0_s_2(12) & l_0_s_3(12);
with sell_1_c_0_cl_12 select
l_1_c_0_cl_12 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_13 <= l_0_s_0(13) & l_0_s_1(13) & l_0_s_2(13) & l_0_s_3(13);
with sell_1_c_0_cl_13 select
l_1_c_0_cl_13 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_14 <= l_0_s_0(14) & l_0_s_1(14) & l_0_s_2(14) & l_0_s_3(14);
with sell_1_c_0_cl_14 select
l_1_c_0_cl_14 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_15 <= l_0_s_0(15) & l_0_s_1(15) & l_0_s_2(15) & l_0_s_3(15);
with sell_1_c_0_cl_15 select
l_1_c_0_cl_15 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_16 <= l_0_s_0(16) & l_0_s_1(16) & l_0_s_2(16) & l_0_s_3(16);
with sell_1_c_0_cl_16 select
l_1_c_0_cl_16 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_17 <= l_0_s_0(17) & l_0_s_1(17) & l_0_s_2(17) & l_0_s_3(17);
with sell_1_c_0_cl_17 select
l_1_c_0_cl_17 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_18 <= l_0_s_0(18) & l_0_s_1(18) & l_0_s_2(18) & l_0_s_3(18);
with sell_1_c_0_cl_18 select
l_1_c_0_cl_18 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_19 <= l_0_s_0(19) & l_0_s_1(19) & l_0_s_2(19) & l_0_s_3(19);
with sell_1_c_0_cl_19 select
l_1_c_0_cl_19 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_20 <= l_0_s_0(20) & l_0_s_1(20) & l_0_s_2(20) & l_0_s_3(20);
with sell_1_c_0_cl_20 select
l_1_c_0_cl_20 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_21 <= l_0_s_0(21) & l_0_s_1(21) & l_0_s_2(21) & l_0_s_3(21);
with sell_1_c_0_cl_21 select
l_1_c_0_cl_21 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_22 <= l_0_s_0(22) & l_0_s_1(22) & l_0_s_2(22) & l_0_s_3(22);
with sell_1_c_0_cl_22 select
l_1_c_0_cl_22 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_23 <= l_0_s_0(23) & l_0_s_1(23) & l_0_s_2(23) & l_0_s_3(23);
with sell_1_c_0_cl_23 select
l_1_c_0_cl_23 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_24 <= l_0_s_0(24) & l_0_s_1(24) & l_0_s_2(24) & l_0_s_3(24);
with sell_1_c_0_cl_24 select
l_1_c_0_cl_24 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_25 <= l_0_s_0(25) & l_0_s_1(25) & l_0_s_2(25) & l_0_s_3(25);
with sell_1_c_0_cl_25 select
l_1_c_0_cl_25 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_26 <= l_0_s_0(26) & l_0_s_1(26) & l_0_s_2(26) & l_0_s_3(26);
with sell_1_c_0_cl_26 select
l_1_c_0_cl_26 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_27 <= l_0_s_0(27) & l_0_s_1(27) & l_0_s_2(27) & l_0_s_3(27);
with sell_1_c_0_cl_27 select
l_1_c_0_cl_27 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_28 <= l_0_s_0(28) & l_0_s_1(28) & l_0_s_2(28) & l_0_s_3(28);
with sell_1_c_0_cl_28 select
l_1_c_0_cl_28 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_29 <= l_0_s_0(29) & l_0_s_1(29) & l_0_s_2(29) & l_0_s_3(29);
with sell_1_c_0_cl_29 select
l_1_c_0_cl_29 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_30 <= l_0_s_0(30) & l_0_s_1(30) & l_0_s_2(30) & l_0_s_3(30);
with sell_1_c_0_cl_30 select
l_1_c_0_cl_30 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_31 <= l_0_s_0(31) & l_0_s_1(31) & l_0_s_2(31) & l_0_s_3(31);
with sell_1_c_0_cl_31 select
l_1_c_0_cl_31 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_32 <= l_0_s_0(32) & l_0_s_1(32) & l_0_s_2(32) & l_0_s_3(32);
with sell_1_c_0_cl_32 select
l_1_c_0_cl_32 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_33 <= l_0_s_0(33) & l_0_s_1(33) & l_0_s_2(33) & l_0_s_3(33);
with sell_1_c_0_cl_33 select
l_1_c_0_cl_33 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_34 <= l_0_s_0(34) & l_0_s_1(34) & l_0_s_2(34) & l_0_s_3(34);
with sell_1_c_0_cl_34 select
l_1_c_0_cl_34 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_35 <= l_0_s_0(35) & l_0_s_1(35) & l_0_s_2(35) & l_0_s_3(35);
with sell_1_c_0_cl_35 select
l_1_c_0_cl_35 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_36 <= l_0_s_0(36) & l_0_s_1(36) & l_0_s_2(36) & l_0_s_3(36);
with sell_1_c_0_cl_36 select
l_1_c_0_cl_36 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_37 <= l_0_s_0(37) & l_0_s_1(37) & l_0_s_2(37) & l_0_s_3(37);
with sell_1_c_0_cl_37 select
l_1_c_0_cl_37 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_38 <= l_0_s_0(38) & l_0_s_1(38) & l_0_s_2(38) & l_0_s_3(38);
with sell_1_c_0_cl_38 select
l_1_c_0_cl_38 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_39 <= l_0_s_0(39) & l_0_s_1(39) & l_0_s_2(39) & l_0_s_3(39);
with sell_1_c_0_cl_39 select
l_1_c_0_cl_39 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_40 <= l_0_s_0(40) & l_0_s_1(40) & l_0_s_2(40) & l_0_s_3(40);
with sell_1_c_0_cl_40 select
l_1_c_0_cl_40 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_41 <= l_0_s_0(41) & l_0_s_1(41) & l_0_s_2(41) & l_0_s_3(41);
with sell_1_c_0_cl_41 select
l_1_c_0_cl_41 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_42 <= l_0_s_0(42) & l_0_s_1(42) & l_0_s_2(42) & l_0_s_3(42);
with sell_1_c_0_cl_42 select
l_1_c_0_cl_42 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_43 <= l_0_s_0(43) & l_0_s_1(43) & l_0_s_2(43) & l_0_s_3(43);
with sell_1_c_0_cl_43 select
l_1_c_0_cl_43 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_44 <= l_0_s_0(44) & l_0_s_1(44) & l_0_s_2(44) & l_0_s_3(44);
with sell_1_c_0_cl_44 select
l_1_c_0_cl_44 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_45 <= l_0_s_0(45) & l_0_s_1(45) & l_0_s_2(45) & l_0_s_3(45);
with sell_1_c_0_cl_45 select
l_1_c_0_cl_45 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_46 <= l_0_s_0(46) & l_0_s_1(46) & l_0_s_2(46) & l_0_s_3(46);
with sell_1_c_0_cl_46 select
l_1_c_0_cl_46 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_47 <= l_0_s_0(47) & l_0_s_1(47) & l_0_s_2(47) & l_0_s_3(47);
with sell_1_c_0_cl_47 select
l_1_c_0_cl_47 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_48 <= l_0_s_0(48) & l_0_s_1(48) & l_0_s_2(48) & l_0_s_3(48);
with sell_1_c_0_cl_48 select
l_1_c_0_cl_48 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_49 <= l_0_s_0(49) & l_0_s_1(49) & l_0_s_2(49) & l_0_s_3(49);
with sell_1_c_0_cl_49 select
l_1_c_0_cl_49 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_50 <= l_0_s_0(50) & l_0_s_1(50) & l_0_s_2(50) & l_0_s_3(50);
with sell_1_c_0_cl_50 select
l_1_c_0_cl_50 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_51 <= l_0_s_0(51) & l_0_s_1(51) & l_0_s_2(51) & l_0_s_3(51);
with sell_1_c_0_cl_51 select
l_1_c_0_cl_51 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_52 <= l_0_s_0(52) & l_0_s_1(52) & l_0_s_2(52) & l_0_s_3(52);
with sell_1_c_0_cl_52 select
l_1_c_0_cl_52 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_53 <= l_0_s_0(53) & l_0_s_1(53) & l_0_s_2(53) & l_0_s_3(53);
with sell_1_c_0_cl_53 select
l_1_c_0_cl_53 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_54 <= l_0_s_0(54) & l_0_s_1(54) & l_0_s_2(54) & l_0_s_3(54);
with sell_1_c_0_cl_54 select
l_1_c_0_cl_54 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_55 <= l_0_s_0(55) & l_0_s_1(55) & l_0_s_2(55) & l_0_s_3(55);
with sell_1_c_0_cl_55 select
l_1_c_0_cl_55 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_56 <= l_0_s_0(56) & l_0_s_1(56) & l_0_s_2(56) & l_0_s_3(56);
with sell_1_c_0_cl_56 select
l_1_c_0_cl_56 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_57 <= l_0_s_0(57) & l_0_s_1(57) & l_0_s_2(57) & l_0_s_3(57);
with sell_1_c_0_cl_57 select
l_1_c_0_cl_57 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_58 <= l_0_s_0(58) & l_0_s_1(58) & l_0_s_2(58) & l_0_s_3(58);
with sell_1_c_0_cl_58 select
l_1_c_0_cl_58 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_59 <= l_0_s_0(59) & l_0_s_1(59) & l_0_s_2(59) & l_0_s_3(59);
with sell_1_c_0_cl_59 select
l_1_c_0_cl_59 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_60 <= l_0_s_0(60) & l_0_s_1(60) & l_0_s_2(60) & l_0_s_3(60);
with sell_1_c_0_cl_60 select
l_1_c_0_cl_60 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_61 <= l_0_s_0(61) & l_0_s_1(61) & l_0_s_2(61) & l_0_s_3(61);
with sell_1_c_0_cl_61 select
l_1_c_0_cl_61 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_62 <= l_0_s_0(62) & l_0_s_1(62) & l_0_s_2(62) & l_0_s_3(62);
with sell_1_c_0_cl_62 select
l_1_c_0_cl_62 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_63 <= l_0_s_0(63) & l_0_s_1(63) & l_0_s_2(63) & l_0_s_3(63);
with sell_1_c_0_cl_63 select
l_1_c_0_cl_63 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_64 <= l_0_s_0(64) & l_0_s_1(64) & l_0_s_2(64) & l_0_s_3(64);
with sell_1_c_0_cl_64 select
l_1_c_0_cl_64 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_65 <= l_0_s_0(65) & l_0_s_1(65) & l_0_s_2(65) & l_0_s_3(65);
with sell_1_c_0_cl_65 select
l_1_c_0_cl_65 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_66 <= l_0_s_0(66) & l_0_s_1(66) & l_0_s_2(66) & l_0_s_3(66);
with sell_1_c_0_cl_66 select
l_1_c_0_cl_66 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_67 <= l_0_s_0(67) & l_0_s_1(67) & l_0_s_2(67) & l_0_s_3(67);
with sell_1_c_0_cl_67 select
l_1_c_0_cl_67 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_68 <= l_0_s_0(68) & l_0_s_1(68) & l_0_s_2(68) & l_0_s_3(68);
with sell_1_c_0_cl_68 select
l_1_c_0_cl_68 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_69 <= l_0_s_0(69) & l_0_s_1(69) & l_0_s_2(69) & l_0_s_3(69);
with sell_1_c_0_cl_69 select
l_1_c_0_cl_69 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_70 <= l_0_s_0(70) & l_0_s_1(70) & l_0_s_2(70) & l_0_s_3(70);
with sell_1_c_0_cl_70 select
l_1_c_0_cl_70 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_71 <= l_0_s_0(71) & l_0_s_1(71) & l_0_s_2(71) & l_0_s_3(71);
with sell_1_c_0_cl_71 select
l_1_c_0_cl_71 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_72 <= l_0_s_0(72) & l_0_s_1(72) & l_0_s_2(72) & l_0_s_3(72);
with sell_1_c_0_cl_72 select
l_1_c_0_cl_72 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_73 <= l_0_s_0(73) & l_0_s_1(73) & l_0_s_2(73) & l_0_s_3(73);
with sell_1_c_0_cl_73 select
l_1_c_0_cl_73 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_74 <= l_0_s_0(74) & l_0_s_1(74) & l_0_s_2(74) & l_0_s_3(74);
with sell_1_c_0_cl_74 select
l_1_c_0_cl_74 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_75 <= l_0_s_0(75) & l_0_s_1(75) & l_0_s_2(75) & l_0_s_3(75);
with sell_1_c_0_cl_75 select
l_1_c_0_cl_75 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_76 <= l_0_s_0(76) & l_0_s_1(76) & l_0_s_2(76) & l_0_s_3(76);
with sell_1_c_0_cl_76 select
l_1_c_0_cl_76 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_77 <= l_0_s_0(77) & l_0_s_1(77) & l_0_s_2(77) & l_0_s_3(77);
with sell_1_c_0_cl_77 select
l_1_c_0_cl_77 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_78 <= l_0_s_0(78) & l_0_s_1(78) & l_0_s_2(78) & l_0_s_3(78);
with sell_1_c_0_cl_78 select
l_1_c_0_cl_78 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_79 <= l_0_s_0(79) & l_0_s_1(79) & l_0_s_2(79) & l_0_s_3(79);
with sell_1_c_0_cl_79 select
l_1_c_0_cl_79 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_80 <= l_0_s_0(80) & l_0_s_1(80) & l_0_s_2(80) & l_0_s_3(80);
with sell_1_c_0_cl_80 select
l_1_c_0_cl_80 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_81 <= l_0_s_0(81) & l_0_s_1(81) & l_0_s_2(81) & l_0_s_3(81);
with sell_1_c_0_cl_81 select
l_1_c_0_cl_81 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_82 <= l_0_s_0(82) & l_0_s_1(82) & l_0_s_2(82) & l_0_s_3(82);
with sell_1_c_0_cl_82 select
l_1_c_0_cl_82 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_83 <= l_0_s_0(83) & l_0_s_1(83) & l_0_s_2(83) & l_0_s_3(83);
with sell_1_c_0_cl_83 select
l_1_c_0_cl_83 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_84 <= l_0_s_0(84) & l_0_s_1(84) & l_0_s_2(84) & l_0_s_3(84);
with sell_1_c_0_cl_84 select
l_1_c_0_cl_84 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_85 <= l_0_s_0(85) & l_0_s_1(85) & l_0_s_2(85) & l_0_s_3(85);
with sell_1_c_0_cl_85 select
l_1_c_0_cl_85 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_86 <= l_0_s_0(86) & l_0_s_1(86) & l_0_s_2(86) & l_0_s_3(86);
with sell_1_c_0_cl_86 select
l_1_c_0_cl_86 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_87 <= l_0_s_0(87) & l_0_s_1(87) & l_0_s_2(87) & l_0_s_3(87);
with sell_1_c_0_cl_87 select
l_1_c_0_cl_87 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_88 <= l_0_s_0(88) & l_0_s_1(88) & l_0_s_2(88) & l_0_s_3(88);
with sell_1_c_0_cl_88 select
l_1_c_0_cl_88 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_89 <= l_0_s_0(89) & l_0_s_1(89) & l_0_s_2(89) & l_0_s_3(89);
with sell_1_c_0_cl_89 select
l_1_c_0_cl_89 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_90 <= l_0_s_0(90) & l_0_s_1(90) & l_0_s_2(90) & l_0_s_3(90);
with sell_1_c_0_cl_90 select
l_1_c_0_cl_90 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_91 <= l_0_s_0(91) & l_0_s_1(91) & l_0_s_2(91) & l_0_s_3(91);
with sell_1_c_0_cl_91 select
l_1_c_0_cl_91 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_92 <= l_0_s_0(92) & l_0_s_1(92) & l_0_s_2(92) & l_0_s_3(92);
with sell_1_c_0_cl_92 select
l_1_c_0_cl_92 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_93 <= l_0_s_0(93) & l_0_s_1(93) & l_0_s_2(93) & l_0_s_3(93);
with sell_1_c_0_cl_93 select
l_1_c_0_cl_93 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_94 <= l_0_s_0(94) & l_0_s_1(94) & l_0_s_2(94) & l_0_s_3(94);
with sell_1_c_0_cl_94 select
l_1_c_0_cl_94 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_95 <= l_0_s_0(95) & l_0_s_1(95) & l_0_s_2(95) & l_0_s_3(95);
with sell_1_c_0_cl_95 select
l_1_c_0_cl_95 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_96 <= l_0_s_0(96) & l_0_s_1(96) & l_0_s_2(96) & l_0_s_3(96);
with sell_1_c_0_cl_96 select
l_1_c_0_cl_96 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_97 <= l_0_s_0(97) & l_0_s_1(97) & l_0_s_2(97) & l_0_s_3(97);
with sell_1_c_0_cl_97 select
l_1_c_0_cl_97 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_98 <= l_0_s_0(98) & l_0_s_1(98) & l_0_s_2(98) & l_0_s_3(98);
with sell_1_c_0_cl_98 select
l_1_c_0_cl_98 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_99 <= l_0_s_0(99) & l_0_s_1(99) & l_0_s_2(99) & l_0_s_3(99);
with sell_1_c_0_cl_99 select
l_1_c_0_cl_99 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_100 <= l_0_s_0(100) & l_0_s_1(100) & l_0_s_2(100) & l_0_s_3(100);
with sell_1_c_0_cl_100 select
l_1_c_0_cl_100 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_101 <= l_0_s_0(101) & l_0_s_1(101) & l_0_s_2(101) & l_0_s_3(101);
with sell_1_c_0_cl_101 select
l_1_c_0_cl_101 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_102 <= l_0_s_0(102) & l_0_s_1(102) & l_0_s_2(102) & l_0_s_3(102);
with sell_1_c_0_cl_102 select
l_1_c_0_cl_102 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_103 <= l_0_s_0(103) & l_0_s_1(103) & l_0_s_2(103) & l_0_s_3(103);
with sell_1_c_0_cl_103 select
l_1_c_0_cl_103 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_104 <= l_0_s_0(104) & l_0_s_1(104) & l_0_s_2(104) & l_0_s_3(104);
with sell_1_c_0_cl_104 select
l_1_c_0_cl_104 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
sell_1_c_0_cl_105 <= l_0_s_0(105) & l_0_s_1(105) & l_0_s_2(105) & l_0_s_3(105);
with sell_1_c_0_cl_105 select
l_1_c_0_cl_105 <=
"000" when "0000", "001" when "0001", "001" when "0010", "010" when "0011", "001" when "0100", "010" when "0101", "010" when "0110", "011" when "0111", "001" when "1000", "010" when "1001", "010" when "1010", "011" when "1011", "010" when "1100", "011" when "1101", "011" when "1110", "100" when "1111", "000" when others;
l_1_s_0 <= l_1_c_0_cl_105(0 downto 0) & l_1_c_0_cl_104(0 downto 0) & l_1_c_0_cl_103(0 downto 0) & l_1_c_0_cl_102(0 downto 0) & l_1_c_0_cl_101(0 downto 0) & l_1_c_0_cl_100(0 downto 0) & l_1_c_0_cl_99(0 downto 0) & l_1_c_0_cl_98(0 downto 0) & l_1_c_0_cl_97(0 downto 0) & l_1_c_0_cl_96(0 downto 0) & l_1_c_0_cl_95(0 downto 0) & l_1_c_0_cl_94(0 downto 0) & l_1_c_0_cl_93(0 downto 0) & l_1_c_0_cl_92(0 downto 0) & l_1_c_0_cl_91(0 downto 0) & l_1_c_0_cl_90(0 downto 0) & l_1_c_0_cl_89(0 downto 0) & l_1_c_0_cl_88(0 downto 0) & l_1_c_0_cl_87(0 downto 0) & l_1_c_0_cl_86(0 downto 0) & l_1_c_0_cl_85(0 downto 0) & l_1_c_0_cl_84(0 downto 0) & l_1_c_0_cl_83(0 downto 0) & l_1_c_0_cl_82(0 downto 0) & l_1_c_0_cl_81(0 downto 0) & l_1_c_0_cl_80(0 downto 0) & l_1_c_0_cl_79(0 downto 0) & l_1_c_0_cl_78(0 downto 0) & l_1_c_0_cl_77(0 downto 0) & l_1_c_0_cl_76(0 downto 0) & l_1_c_0_cl_75(0 downto 0) & l_1_c_0_cl_74(0 downto 0) & l_1_c_0_cl_73(0 downto 0) & l_1_c_0_cl_72(0 downto 0) & l_1_c_0_cl_71(0 downto 0) & l_1_c_0_cl_70(0 downto 0) & l_1_c_0_cl_69(0 downto 0) & l_1_c_0_cl_68(0 downto 0) & l_1_c_0_cl_67(0 downto 0) & l_1_c_0_cl_66(0 downto 0) & l_1_c_0_cl_65(0 downto 0) & l_1_c_0_cl_64(0 downto 0) & l_1_c_0_cl_63(0 downto 0) & l_1_c_0_cl_62(0 downto 0) & l_1_c_0_cl_61(0 downto 0) & l_1_c_0_cl_60(0 downto 0) & l_1_c_0_cl_59(0 downto 0) & l_1_c_0_cl_58(0 downto 0) & l_1_c_0_cl_57(0 downto 0) & l_1_c_0_cl_56(0 downto 0) & l_1_c_0_cl_55(0 downto 0) & l_1_c_0_cl_54(0 downto 0) & l_1_c_0_cl_53(0 downto 0) & l_1_c_0_cl_52(0 downto 0) & l_1_c_0_cl_51(0 downto 0) & l_1_c_0_cl_50(0 downto 0) & l_1_c_0_cl_49(0 downto 0) & l_1_c_0_cl_48(0 downto 0) & l_1_c_0_cl_47(0 downto 0) & l_1_c_0_cl_46(0 downto 0) & l_1_c_0_cl_45(0 downto 0) & l_1_c_0_cl_44(0 downto 0) & l_1_c_0_cl_43(0 downto 0) & l_1_c_0_cl_42(0 downto 0) & l_1_c_0_cl_41(0 downto 0) & l_1_c_0_cl_40(0 downto 0) & l_1_c_0_cl_39(0 downto 0) & l_1_c_0_cl_38(0 downto 0) & l_1_c_0_cl_37(0 downto 0) & l_1_c_0_cl_36(0 downto 0) & l_1_c_0_cl_35(0 downto 0) & l_1_c_0_cl_34(0 downto 0) & l_1_c_0_cl_33(0 downto 0) & l_1_c_0_cl_32(0 downto 0) & l_1_c_0_cl_31(0 downto 0) & l_1_c_0_cl_30(0 downto 0) & l_1_c_0_cl_29(0 downto 0) & l_1_c_0_cl_28(0 downto 0) & l_1_c_0_cl_27(0 downto 0) & l_1_c_0_cl_26(0 downto 0) & l_1_c_0_cl_25(0 downto 0) & l_1_c_0_cl_24(0 downto 0) & l_1_c_0_cl_23(0 downto 0) & l_1_c_0_cl_22(0 downto 0) & l_1_c_0_cl_21(0 downto 0) & l_1_c_0_cl_20(0 downto 0) & l_1_c_0_cl_19(0 downto 0) & l_1_c_0_cl_18(0 downto 0) & l_1_c_0_cl_17(0 downto 0) & l_1_c_0_cl_16(0 downto 0) & l_1_c_0_cl_15(0 downto 0) & l_1_c_0_cl_14(0 downto 0) & l_1_c_0_cl_13(0 downto 0) & l_1_c_0_cl_12(0 downto 0) & l_1_c_0_cl_11(0 downto 0) & l_1_c_0_cl_10(0 downto 0) & l_1_c_0_cl_9(0 downto 0) & l_1_c_0_cl_8(0 downto 0) & l_1_c_0_cl_7(0 downto 0) & l_1_c_0_cl_6(0 downto 0) & l_1_c_0_cl_5(0 downto 0) & l_1_c_0_cl_4(0 downto 0) & l_1_c_0_cl_3(0 downto 0) & l_1_c_0_cl_2(0 downto 0) & l_1_c_0_cl_1(0 downto 0) & l_1_c_0_cl_0(0 downto 0);
l_1_s_1 <= l_1_c_0_cl_104(1 downto 1) & l_1_c_0_cl_103(1 downto 1) & l_1_c_0_cl_102(1 downto 1) & l_1_c_0_cl_101(1 downto 1) & l_1_c_0_cl_100(1 downto 1) & l_1_c_0_cl_99(1 downto 1) & l_1_c_0_cl_98(1 downto 1) & l_1_c_0_cl_97(1 downto 1) & l_1_c_0_cl_96(1 downto 1) & l_1_c_0_cl_95(1 downto 1) & l_1_c_0_cl_94(1 downto 1) & l_1_c_0_cl_93(1 downto 1) & l_1_c_0_cl_92(1 downto 1) & l_1_c_0_cl_91(1 downto 1) & l_1_c_0_cl_90(1 downto 1) & l_1_c_0_cl_89(1 downto 1) & l_1_c_0_cl_88(1 downto 1) & l_1_c_0_cl_87(1 downto 1) & l_1_c_0_cl_86(1 downto 1) & l_1_c_0_cl_85(1 downto 1) & l_1_c_0_cl_84(1 downto 1) & l_1_c_0_cl_83(1 downto 1) & l_1_c_0_cl_82(1 downto 1) & l_1_c_0_cl_81(1 downto 1) & l_1_c_0_cl_80(1 downto 1) & l_1_c_0_cl_79(1 downto 1) & l_1_c_0_cl_78(1 downto 1) & l_1_c_0_cl_77(1 downto 1) & l_1_c_0_cl_76(1 downto 1) & l_1_c_0_cl_75(1 downto 1) & l_1_c_0_cl_74(1 downto 1) & l_1_c_0_cl_73(1 downto 1) & l_1_c_0_cl_72(1 downto 1) & l_1_c_0_cl_71(1 downto 1) & l_1_c_0_cl_70(1 downto 1) & l_1_c_0_cl_69(1 downto 1) & l_1_c_0_cl_68(1 downto 1) & l_1_c_0_cl_67(1 downto 1) & l_1_c_0_cl_66(1 downto 1) & l_1_c_0_cl_65(1 downto 1) & l_1_c_0_cl_64(1 downto 1) & l_1_c_0_cl_63(1 downto 1) & l_1_c_0_cl_62(1 downto 1) & l_1_c_0_cl_61(1 downto 1) & l_1_c_0_cl_60(1 downto 1) & l_1_c_0_cl_59(1 downto 1) & l_1_c_0_cl_58(1 downto 1) & l_1_c_0_cl_57(1 downto 1) & l_1_c_0_cl_56(1 downto 1) & l_1_c_0_cl_55(1 downto 1) & l_1_c_0_cl_54(1 downto 1) & l_1_c_0_cl_53(1 downto 1) & l_1_c_0_cl_52(1 downto 1) & l_1_c_0_cl_51(1 downto 1) & l_1_c_0_cl_50(1 downto 1) & l_1_c_0_cl_49(1 downto 1) & l_1_c_0_cl_48(1 downto 1) & l_1_c_0_cl_47(1 downto 1) & l_1_c_0_cl_46(1 downto 1) & l_1_c_0_cl_45(1 downto 1) & l_1_c_0_cl_44(1 downto 1) & l_1_c_0_cl_43(1 downto 1) & l_1_c_0_cl_42(1 downto 1) & l_1_c_0_cl_41(1 downto 1) & l_1_c_0_cl_40(1 downto 1) & l_1_c_0_cl_39(1 downto 1) & l_1_c_0_cl_38(1 downto 1) & l_1_c_0_cl_37(1 downto 1) & l_1_c_0_cl_36(1 downto 1) & l_1_c_0_cl_35(1 downto 1) & l_1_c_0_cl_34(1 downto 1) & l_1_c_0_cl_33(1 downto 1) & l_1_c_0_cl_32(1 downto 1) & l_1_c_0_cl_31(1 downto 1) & l_1_c_0_cl_30(1 downto 1) & l_1_c_0_cl_29(1 downto 1) & l_1_c_0_cl_28(1 downto 1) & l_1_c_0_cl_27(1 downto 1) & l_1_c_0_cl_26(1 downto 1) & l_1_c_0_cl_25(1 downto 1) & l_1_c_0_cl_24(1 downto 1) & l_1_c_0_cl_23(1 downto 1) & l_1_c_0_cl_22(1 downto 1) & l_1_c_0_cl_21(1 downto 1) & l_1_c_0_cl_20(1 downto 1) & l_1_c_0_cl_19(1 downto 1) & l_1_c_0_cl_18(1 downto 1) & l_1_c_0_cl_17(1 downto 1) & l_1_c_0_cl_16(1 downto 1) & l_1_c_0_cl_15(1 downto 1) & l_1_c_0_cl_14(1 downto 1) & l_1_c_0_cl_13(1 downto 1) & l_1_c_0_cl_12(1 downto 1) & l_1_c_0_cl_11(1 downto 1) & l_1_c_0_cl_10(1 downto 1) & l_1_c_0_cl_9(1 downto 1) & l_1_c_0_cl_8(1 downto 1) & l_1_c_0_cl_7(1 downto 1) & l_1_c_0_cl_6(1 downto 1) & l_1_c_0_cl_5(1 downto 1) & l_1_c_0_cl_4(1 downto 1) & l_1_c_0_cl_3(1 downto 1) & l_1_c_0_cl_2(1 downto 1) & l_1_c_0_cl_1(1 downto 1) & l_1_c_0_cl_0(1 downto 1) & "0";
l_1_s_2 <= l_1_c_0_cl_103(2 downto 2) & l_1_c_0_cl_102(2 downto 2) & l_1_c_0_cl_101(2 downto 2) & l_1_c_0_cl_100(2 downto 2) & l_1_c_0_cl_99(2 downto 2) & l_1_c_0_cl_98(2 downto 2) & l_1_c_0_cl_97(2 downto 2) & l_1_c_0_cl_96(2 downto 2) & l_1_c_0_cl_95(2 downto 2) & l_1_c_0_cl_94(2 downto 2) & l_1_c_0_cl_93(2 downto 2) & l_1_c_0_cl_92(2 downto 2) & l_1_c_0_cl_91(2 downto 2) & l_1_c_0_cl_90(2 downto 2) & l_1_c_0_cl_89(2 downto 2) & l_1_c_0_cl_88(2 downto 2) & l_1_c_0_cl_87(2 downto 2) & l_1_c_0_cl_86(2 downto 2) & l_1_c_0_cl_85(2 downto 2) & l_1_c_0_cl_84(2 downto 2) & l_1_c_0_cl_83(2 downto 2) & l_1_c_0_cl_82(2 downto 2) & l_1_c_0_cl_81(2 downto 2) & l_1_c_0_cl_80(2 downto 2) & l_1_c_0_cl_79(2 downto 2) & l_1_c_0_cl_78(2 downto 2) & l_1_c_0_cl_77(2 downto 2) & l_1_c_0_cl_76(2 downto 2) & l_1_c_0_cl_75(2 downto 2) & l_1_c_0_cl_74(2 downto 2) & l_1_c_0_cl_73(2 downto 2) & l_1_c_0_cl_72(2 downto 2) & l_1_c_0_cl_71(2 downto 2) & l_1_c_0_cl_70(2 downto 2) & l_1_c_0_cl_69(2 downto 2) & l_1_c_0_cl_68(2 downto 2) & l_1_c_0_cl_67(2 downto 2) & l_1_c_0_cl_66(2 downto 2) & l_1_c_0_cl_65(2 downto 2) & l_1_c_0_cl_64(2 downto 2) & l_1_c_0_cl_63(2 downto 2) & l_1_c_0_cl_62(2 downto 2) & l_1_c_0_cl_61(2 downto 2) & l_1_c_0_cl_60(2 downto 2) & l_1_c_0_cl_59(2 downto 2) & l_1_c_0_cl_58(2 downto 2) & l_1_c_0_cl_57(2 downto 2) & l_1_c_0_cl_56(2 downto 2) & l_1_c_0_cl_55(2 downto 2) & l_1_c_0_cl_54(2 downto 2) & l_1_c_0_cl_53(2 downto 2) & l_1_c_0_cl_52(2 downto 2) & l_1_c_0_cl_51(2 downto 2) & l_1_c_0_cl_50(2 downto 2) & l_1_c_0_cl_49(2 downto 2) & l_1_c_0_cl_48(2 downto 2) & l_1_c_0_cl_47(2 downto 2) & l_1_c_0_cl_46(2 downto 2) & l_1_c_0_cl_45(2 downto 2) & l_1_c_0_cl_44(2 downto 2) & l_1_c_0_cl_43(2 downto 2) & l_1_c_0_cl_42(2 downto 2) & l_1_c_0_cl_41(2 downto 2) & l_1_c_0_cl_40(2 downto 2) & l_1_c_0_cl_39(2 downto 2) & l_1_c_0_cl_38(2 downto 2) & l_1_c_0_cl_37(2 downto 2) & l_1_c_0_cl_36(2 downto 2) & l_1_c_0_cl_35(2 downto 2) & l_1_c_0_cl_34(2 downto 2) & l_1_c_0_cl_33(2 downto 2) & l_1_c_0_cl_32(2 downto 2) & l_1_c_0_cl_31(2 downto 2) & l_1_c_0_cl_30(2 downto 2) & l_1_c_0_cl_29(2 downto 2) & l_1_c_0_cl_28(2 downto 2) & l_1_c_0_cl_27(2 downto 2) & l_1_c_0_cl_26(2 downto 2) & l_1_c_0_cl_25(2 downto 2) & l_1_c_0_cl_24(2 downto 2) & l_1_c_0_cl_23(2 downto 2) & l_1_c_0_cl_22(2 downto 2) & l_1_c_0_cl_21(2 downto 2) & l_1_c_0_cl_20(2 downto 2) & l_1_c_0_cl_19(2 downto 2) & l_1_c_0_cl_18(2 downto 2) & l_1_c_0_cl_17(2 downto 2) & l_1_c_0_cl_16(2 downto 2) & l_1_c_0_cl_15(2 downto 2) & l_1_c_0_cl_14(2 downto 2) & l_1_c_0_cl_13(2 downto 2) & l_1_c_0_cl_12(2 downto 2) & l_1_c_0_cl_11(2 downto 2) & l_1_c_0_cl_10(2 downto 2) & l_1_c_0_cl_9(2 downto 2) & l_1_c_0_cl_8(2 downto 2) & l_1_c_0_cl_7(2 downto 2) & l_1_c_0_cl_6(2 downto 2) & l_1_c_0_cl_5(2 downto 2) & l_1_c_0_cl_4(2 downto 2) & l_1_c_0_cl_3(2 downto 2) & l_1_c_0_cl_2(2 downto 2) & l_1_c_0_cl_1(2 downto 2) & l_1_c_0_cl_0(2 downto 2) & "00";
sell_2_c_0_cl_0 <= l_1_s_0(0) & l_1_s_1(0) & l_1_s_2(0);
with sell_2_c_0_cl_0 select
l_2_c_0_cl_0 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_1 <= l_1_s_0(1) & l_1_s_1(1) & l_1_s_2(1);
with sell_2_c_0_cl_1 select
l_2_c_0_cl_1 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_2 <= l_1_s_0(2) & l_1_s_1(2) & l_1_s_2(2);
with sell_2_c_0_cl_2 select
l_2_c_0_cl_2 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_3 <= l_1_s_0(3) & l_1_s_1(3) & l_1_s_2(3);
with sell_2_c_0_cl_3 select
l_2_c_0_cl_3 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_4 <= l_1_s_0(4) & l_1_s_1(4) & l_1_s_2(4);
with sell_2_c_0_cl_4 select
l_2_c_0_cl_4 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_5 <= l_1_s_0(5) & l_1_s_1(5) & l_1_s_2(5);
with sell_2_c_0_cl_5 select
l_2_c_0_cl_5 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_6 <= l_1_s_0(6) & l_1_s_1(6) & l_1_s_2(6);
with sell_2_c_0_cl_6 select
l_2_c_0_cl_6 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_7 <= l_1_s_0(7) & l_1_s_1(7) & l_1_s_2(7);
with sell_2_c_0_cl_7 select
l_2_c_0_cl_7 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_8 <= l_1_s_0(8) & l_1_s_1(8) & l_1_s_2(8);
with sell_2_c_0_cl_8 select
l_2_c_0_cl_8 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_9 <= l_1_s_0(9) & l_1_s_1(9) & l_1_s_2(9);
with sell_2_c_0_cl_9 select
l_2_c_0_cl_9 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_10 <= l_1_s_0(10) & l_1_s_1(10) & l_1_s_2(10);
with sell_2_c_0_cl_10 select
l_2_c_0_cl_10 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_11 <= l_1_s_0(11) & l_1_s_1(11) & l_1_s_2(11);
with sell_2_c_0_cl_11 select
l_2_c_0_cl_11 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_12 <= l_1_s_0(12) & l_1_s_1(12) & l_1_s_2(12);
with sell_2_c_0_cl_12 select
l_2_c_0_cl_12 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_13 <= l_1_s_0(13) & l_1_s_1(13) & l_1_s_2(13);
with sell_2_c_0_cl_13 select
l_2_c_0_cl_13 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_14 <= l_1_s_0(14) & l_1_s_1(14) & l_1_s_2(14);
with sell_2_c_0_cl_14 select
l_2_c_0_cl_14 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_15 <= l_1_s_0(15) & l_1_s_1(15) & l_1_s_2(15);
with sell_2_c_0_cl_15 select
l_2_c_0_cl_15 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_16 <= l_1_s_0(16) & l_1_s_1(16) & l_1_s_2(16);
with sell_2_c_0_cl_16 select
l_2_c_0_cl_16 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_17 <= l_1_s_0(17) & l_1_s_1(17) & l_1_s_2(17);
with sell_2_c_0_cl_17 select
l_2_c_0_cl_17 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_18 <= l_1_s_0(18) & l_1_s_1(18) & l_1_s_2(18);
with sell_2_c_0_cl_18 select
l_2_c_0_cl_18 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_19 <= l_1_s_0(19) & l_1_s_1(19) & l_1_s_2(19);
with sell_2_c_0_cl_19 select
l_2_c_0_cl_19 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_20 <= l_1_s_0(20) & l_1_s_1(20) & l_1_s_2(20);
with sell_2_c_0_cl_20 select
l_2_c_0_cl_20 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_21 <= l_1_s_0(21) & l_1_s_1(21) & l_1_s_2(21);
with sell_2_c_0_cl_21 select
l_2_c_0_cl_21 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_22 <= l_1_s_0(22) & l_1_s_1(22) & l_1_s_2(22);
with sell_2_c_0_cl_22 select
l_2_c_0_cl_22 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_23 <= l_1_s_0(23) & l_1_s_1(23) & l_1_s_2(23);
with sell_2_c_0_cl_23 select
l_2_c_0_cl_23 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_24 <= l_1_s_0(24) & l_1_s_1(24) & l_1_s_2(24);
with sell_2_c_0_cl_24 select
l_2_c_0_cl_24 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_25 <= l_1_s_0(25) & l_1_s_1(25) & l_1_s_2(25);
with sell_2_c_0_cl_25 select
l_2_c_0_cl_25 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_26 <= l_1_s_0(26) & l_1_s_1(26) & l_1_s_2(26);
with sell_2_c_0_cl_26 select
l_2_c_0_cl_26 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_27 <= l_1_s_0(27) & l_1_s_1(27) & l_1_s_2(27);
with sell_2_c_0_cl_27 select
l_2_c_0_cl_27 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_28 <= l_1_s_0(28) & l_1_s_1(28) & l_1_s_2(28);
with sell_2_c_0_cl_28 select
l_2_c_0_cl_28 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_29 <= l_1_s_0(29) & l_1_s_1(29) & l_1_s_2(29);
with sell_2_c_0_cl_29 select
l_2_c_0_cl_29 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_30 <= l_1_s_0(30) & l_1_s_1(30) & l_1_s_2(30);
with sell_2_c_0_cl_30 select
l_2_c_0_cl_30 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_31 <= l_1_s_0(31) & l_1_s_1(31) & l_1_s_2(31);
with sell_2_c_0_cl_31 select
l_2_c_0_cl_31 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_32 <= l_1_s_0(32) & l_1_s_1(32) & l_1_s_2(32);
with sell_2_c_0_cl_32 select
l_2_c_0_cl_32 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_33 <= l_1_s_0(33) & l_1_s_1(33) & l_1_s_2(33);
with sell_2_c_0_cl_33 select
l_2_c_0_cl_33 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_34 <= l_1_s_0(34) & l_1_s_1(34) & l_1_s_2(34);
with sell_2_c_0_cl_34 select
l_2_c_0_cl_34 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_35 <= l_1_s_0(35) & l_1_s_1(35) & l_1_s_2(35);
with sell_2_c_0_cl_35 select
l_2_c_0_cl_35 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_36 <= l_1_s_0(36) & l_1_s_1(36) & l_1_s_2(36);
with sell_2_c_0_cl_36 select
l_2_c_0_cl_36 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_37 <= l_1_s_0(37) & l_1_s_1(37) & l_1_s_2(37);
with sell_2_c_0_cl_37 select
l_2_c_0_cl_37 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_38 <= l_1_s_0(38) & l_1_s_1(38) & l_1_s_2(38);
with sell_2_c_0_cl_38 select
l_2_c_0_cl_38 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_39 <= l_1_s_0(39) & l_1_s_1(39) & l_1_s_2(39);
with sell_2_c_0_cl_39 select
l_2_c_0_cl_39 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_40 <= l_1_s_0(40) & l_1_s_1(40) & l_1_s_2(40);
with sell_2_c_0_cl_40 select
l_2_c_0_cl_40 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_41 <= l_1_s_0(41) & l_1_s_1(41) & l_1_s_2(41);
with sell_2_c_0_cl_41 select
l_2_c_0_cl_41 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_42 <= l_1_s_0(42) & l_1_s_1(42) & l_1_s_2(42);
with sell_2_c_0_cl_42 select
l_2_c_0_cl_42 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_43 <= l_1_s_0(43) & l_1_s_1(43) & l_1_s_2(43);
with sell_2_c_0_cl_43 select
l_2_c_0_cl_43 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_44 <= l_1_s_0(44) & l_1_s_1(44) & l_1_s_2(44);
with sell_2_c_0_cl_44 select
l_2_c_0_cl_44 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_45 <= l_1_s_0(45) & l_1_s_1(45) & l_1_s_2(45);
with sell_2_c_0_cl_45 select
l_2_c_0_cl_45 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_46 <= l_1_s_0(46) & l_1_s_1(46) & l_1_s_2(46);
with sell_2_c_0_cl_46 select
l_2_c_0_cl_46 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_47 <= l_1_s_0(47) & l_1_s_1(47) & l_1_s_2(47);
with sell_2_c_0_cl_47 select
l_2_c_0_cl_47 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_48 <= l_1_s_0(48) & l_1_s_1(48) & l_1_s_2(48);
with sell_2_c_0_cl_48 select
l_2_c_0_cl_48 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_49 <= l_1_s_0(49) & l_1_s_1(49) & l_1_s_2(49);
with sell_2_c_0_cl_49 select
l_2_c_0_cl_49 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_50 <= l_1_s_0(50) & l_1_s_1(50) & l_1_s_2(50);
with sell_2_c_0_cl_50 select
l_2_c_0_cl_50 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_51 <= l_1_s_0(51) & l_1_s_1(51) & l_1_s_2(51);
with sell_2_c_0_cl_51 select
l_2_c_0_cl_51 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_52 <= l_1_s_0(52) & l_1_s_1(52) & l_1_s_2(52);
with sell_2_c_0_cl_52 select
l_2_c_0_cl_52 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_53 <= l_1_s_0(53) & l_1_s_1(53) & l_1_s_2(53);
with sell_2_c_0_cl_53 select
l_2_c_0_cl_53 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_54 <= l_1_s_0(54) & l_1_s_1(54) & l_1_s_2(54);
with sell_2_c_0_cl_54 select
l_2_c_0_cl_54 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_55 <= l_1_s_0(55) & l_1_s_1(55) & l_1_s_2(55);
with sell_2_c_0_cl_55 select
l_2_c_0_cl_55 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_56 <= l_1_s_0(56) & l_1_s_1(56) & l_1_s_2(56);
with sell_2_c_0_cl_56 select
l_2_c_0_cl_56 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_57 <= l_1_s_0(57) & l_1_s_1(57) & l_1_s_2(57);
with sell_2_c_0_cl_57 select
l_2_c_0_cl_57 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_58 <= l_1_s_0(58) & l_1_s_1(58) & l_1_s_2(58);
with sell_2_c_0_cl_58 select
l_2_c_0_cl_58 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_59 <= l_1_s_0(59) & l_1_s_1(59) & l_1_s_2(59);
with sell_2_c_0_cl_59 select
l_2_c_0_cl_59 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_60 <= l_1_s_0(60) & l_1_s_1(60) & l_1_s_2(60);
with sell_2_c_0_cl_60 select
l_2_c_0_cl_60 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_61 <= l_1_s_0(61) & l_1_s_1(61) & l_1_s_2(61);
with sell_2_c_0_cl_61 select
l_2_c_0_cl_61 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_62 <= l_1_s_0(62) & l_1_s_1(62) & l_1_s_2(62);
with sell_2_c_0_cl_62 select
l_2_c_0_cl_62 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_63 <= l_1_s_0(63) & l_1_s_1(63) & l_1_s_2(63);
with sell_2_c_0_cl_63 select
l_2_c_0_cl_63 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_64 <= l_1_s_0(64) & l_1_s_1(64) & l_1_s_2(64);
with sell_2_c_0_cl_64 select
l_2_c_0_cl_64 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_65 <= l_1_s_0(65) & l_1_s_1(65) & l_1_s_2(65);
with sell_2_c_0_cl_65 select
l_2_c_0_cl_65 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_66 <= l_1_s_0(66) & l_1_s_1(66) & l_1_s_2(66);
with sell_2_c_0_cl_66 select
l_2_c_0_cl_66 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_67 <= l_1_s_0(67) & l_1_s_1(67) & l_1_s_2(67);
with sell_2_c_0_cl_67 select
l_2_c_0_cl_67 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_68 <= l_1_s_0(68) & l_1_s_1(68) & l_1_s_2(68);
with sell_2_c_0_cl_68 select
l_2_c_0_cl_68 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_69 <= l_1_s_0(69) & l_1_s_1(69) & l_1_s_2(69);
with sell_2_c_0_cl_69 select
l_2_c_0_cl_69 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_70 <= l_1_s_0(70) & l_1_s_1(70) & l_1_s_2(70);
with sell_2_c_0_cl_70 select
l_2_c_0_cl_70 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_71 <= l_1_s_0(71) & l_1_s_1(71) & l_1_s_2(71);
with sell_2_c_0_cl_71 select
l_2_c_0_cl_71 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_72 <= l_1_s_0(72) & l_1_s_1(72) & l_1_s_2(72);
with sell_2_c_0_cl_72 select
l_2_c_0_cl_72 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_73 <= l_1_s_0(73) & l_1_s_1(73) & l_1_s_2(73);
with sell_2_c_0_cl_73 select
l_2_c_0_cl_73 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_74 <= l_1_s_0(74) & l_1_s_1(74) & l_1_s_2(74);
with sell_2_c_0_cl_74 select
l_2_c_0_cl_74 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_75 <= l_1_s_0(75) & l_1_s_1(75) & l_1_s_2(75);
with sell_2_c_0_cl_75 select
l_2_c_0_cl_75 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_76 <= l_1_s_0(76) & l_1_s_1(76) & l_1_s_2(76);
with sell_2_c_0_cl_76 select
l_2_c_0_cl_76 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_77 <= l_1_s_0(77) & l_1_s_1(77) & l_1_s_2(77);
with sell_2_c_0_cl_77 select
l_2_c_0_cl_77 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_78 <= l_1_s_0(78) & l_1_s_1(78) & l_1_s_2(78);
with sell_2_c_0_cl_78 select
l_2_c_0_cl_78 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_79 <= l_1_s_0(79) & l_1_s_1(79) & l_1_s_2(79);
with sell_2_c_0_cl_79 select
l_2_c_0_cl_79 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_80 <= l_1_s_0(80) & l_1_s_1(80) & l_1_s_2(80);
with sell_2_c_0_cl_80 select
l_2_c_0_cl_80 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_81 <= l_1_s_0(81) & l_1_s_1(81) & l_1_s_2(81);
with sell_2_c_0_cl_81 select
l_2_c_0_cl_81 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_82 <= l_1_s_0(82) & l_1_s_1(82) & l_1_s_2(82);
with sell_2_c_0_cl_82 select
l_2_c_0_cl_82 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_83 <= l_1_s_0(83) & l_1_s_1(83) & l_1_s_2(83);
with sell_2_c_0_cl_83 select
l_2_c_0_cl_83 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_84 <= l_1_s_0(84) & l_1_s_1(84) & l_1_s_2(84);
with sell_2_c_0_cl_84 select
l_2_c_0_cl_84 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_85 <= l_1_s_0(85) & l_1_s_1(85) & l_1_s_2(85);
with sell_2_c_0_cl_85 select
l_2_c_0_cl_85 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_86 <= l_1_s_0(86) & l_1_s_1(86) & l_1_s_2(86);
with sell_2_c_0_cl_86 select
l_2_c_0_cl_86 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_87 <= l_1_s_0(87) & l_1_s_1(87) & l_1_s_2(87);
with sell_2_c_0_cl_87 select
l_2_c_0_cl_87 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_88 <= l_1_s_0(88) & l_1_s_1(88) & l_1_s_2(88);
with sell_2_c_0_cl_88 select
l_2_c_0_cl_88 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_89 <= l_1_s_0(89) & l_1_s_1(89) & l_1_s_2(89);
with sell_2_c_0_cl_89 select
l_2_c_0_cl_89 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_90 <= l_1_s_0(90) & l_1_s_1(90) & l_1_s_2(90);
with sell_2_c_0_cl_90 select
l_2_c_0_cl_90 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_91 <= l_1_s_0(91) & l_1_s_1(91) & l_1_s_2(91);
with sell_2_c_0_cl_91 select
l_2_c_0_cl_91 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_92 <= l_1_s_0(92) & l_1_s_1(92) & l_1_s_2(92);
with sell_2_c_0_cl_92 select
l_2_c_0_cl_92 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_93 <= l_1_s_0(93) & l_1_s_1(93) & l_1_s_2(93);
with sell_2_c_0_cl_93 select
l_2_c_0_cl_93 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_94 <= l_1_s_0(94) & l_1_s_1(94) & l_1_s_2(94);
with sell_2_c_0_cl_94 select
l_2_c_0_cl_94 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_95 <= l_1_s_0(95) & l_1_s_1(95) & l_1_s_2(95);
with sell_2_c_0_cl_95 select
l_2_c_0_cl_95 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_96 <= l_1_s_0(96) & l_1_s_1(96) & l_1_s_2(96);
with sell_2_c_0_cl_96 select
l_2_c_0_cl_96 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_97 <= l_1_s_0(97) & l_1_s_1(97) & l_1_s_2(97);
with sell_2_c_0_cl_97 select
l_2_c_0_cl_97 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_98 <= l_1_s_0(98) & l_1_s_1(98) & l_1_s_2(98);
with sell_2_c_0_cl_98 select
l_2_c_0_cl_98 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_99 <= l_1_s_0(99) & l_1_s_1(99) & l_1_s_2(99);
with sell_2_c_0_cl_99 select
l_2_c_0_cl_99 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_100 <= l_1_s_0(100) & l_1_s_1(100) & l_1_s_2(100);
with sell_2_c_0_cl_100 select
l_2_c_0_cl_100 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_101 <= l_1_s_0(101) & l_1_s_1(101) & l_1_s_2(101);
with sell_2_c_0_cl_101 select
l_2_c_0_cl_101 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_102 <= l_1_s_0(102) & l_1_s_1(102) & l_1_s_2(102);
with sell_2_c_0_cl_102 select
l_2_c_0_cl_102 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_103 <= l_1_s_0(103) & l_1_s_1(103) & l_1_s_2(103);
with sell_2_c_0_cl_103 select
l_2_c_0_cl_103 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_104 <= l_1_s_0(104) & l_1_s_1(104) & l_1_s_2(104);
with sell_2_c_0_cl_104 select
l_2_c_0_cl_104 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
sell_2_c_0_cl_105 <= l_1_s_0(105) & l_1_s_1(105) & l_1_s_2(105);
with sell_2_c_0_cl_105 select
l_2_c_0_cl_105 <=
"00" when "000", "01" when "001", "01" when "010", "10" when "011", "01" when "100", "10" when "101", "10" when "110", "11" when "111", "00" when others;
l_2_s_0 <= l_2_c_0_cl_105(0 downto 0) & l_2_c_0_cl_104(0 downto 0) & l_2_c_0_cl_103(0 downto 0) & l_2_c_0_cl_102(0 downto 0) & l_2_c_0_cl_101(0 downto 0) & l_2_c_0_cl_100(0 downto 0) & l_2_c_0_cl_99(0 downto 0) & l_2_c_0_cl_98(0 downto 0) & l_2_c_0_cl_97(0 downto 0) & l_2_c_0_cl_96(0 downto 0) & l_2_c_0_cl_95(0 downto 0) & l_2_c_0_cl_94(0 downto 0) & l_2_c_0_cl_93(0 downto 0) & l_2_c_0_cl_92(0 downto 0) & l_2_c_0_cl_91(0 downto 0) & l_2_c_0_cl_90(0 downto 0) & l_2_c_0_cl_89(0 downto 0) & l_2_c_0_cl_88(0 downto 0) & l_2_c_0_cl_87(0 downto 0) & l_2_c_0_cl_86(0 downto 0) & l_2_c_0_cl_85(0 downto 0) & l_2_c_0_cl_84(0 downto 0) & l_2_c_0_cl_83(0 downto 0) & l_2_c_0_cl_82(0 downto 0) & l_2_c_0_cl_81(0 downto 0) & l_2_c_0_cl_80(0 downto 0) & l_2_c_0_cl_79(0 downto 0) & l_2_c_0_cl_78(0 downto 0) & l_2_c_0_cl_77(0 downto 0) & l_2_c_0_cl_76(0 downto 0) & l_2_c_0_cl_75(0 downto 0) & l_2_c_0_cl_74(0 downto 0) & l_2_c_0_cl_73(0 downto 0) & l_2_c_0_cl_72(0 downto 0) & l_2_c_0_cl_71(0 downto 0) & l_2_c_0_cl_70(0 downto 0) & l_2_c_0_cl_69(0 downto 0) & l_2_c_0_cl_68(0 downto 0) & l_2_c_0_cl_67(0 downto 0) & l_2_c_0_cl_66(0 downto 0) & l_2_c_0_cl_65(0 downto 0) & l_2_c_0_cl_64(0 downto 0) & l_2_c_0_cl_63(0 downto 0) & l_2_c_0_cl_62(0 downto 0) & l_2_c_0_cl_61(0 downto 0) & l_2_c_0_cl_60(0 downto 0) & l_2_c_0_cl_59(0 downto 0) & l_2_c_0_cl_58(0 downto 0) & l_2_c_0_cl_57(0 downto 0) & l_2_c_0_cl_56(0 downto 0) & l_2_c_0_cl_55(0 downto 0) & l_2_c_0_cl_54(0 downto 0) & l_2_c_0_cl_53(0 downto 0) & l_2_c_0_cl_52(0 downto 0) & l_2_c_0_cl_51(0 downto 0) & l_2_c_0_cl_50(0 downto 0) & l_2_c_0_cl_49(0 downto 0) & l_2_c_0_cl_48(0 downto 0) & l_2_c_0_cl_47(0 downto 0) & l_2_c_0_cl_46(0 downto 0) & l_2_c_0_cl_45(0 downto 0) & l_2_c_0_cl_44(0 downto 0) & l_2_c_0_cl_43(0 downto 0) & l_2_c_0_cl_42(0 downto 0) & l_2_c_0_cl_41(0 downto 0) & l_2_c_0_cl_40(0 downto 0) & l_2_c_0_cl_39(0 downto 0) & l_2_c_0_cl_38(0 downto 0) & l_2_c_0_cl_37(0 downto 0) & l_2_c_0_cl_36(0 downto 0) & l_2_c_0_cl_35(0 downto 0) & l_2_c_0_cl_34(0 downto 0) & l_2_c_0_cl_33(0 downto 0) & l_2_c_0_cl_32(0 downto 0) & l_2_c_0_cl_31(0 downto 0) & l_2_c_0_cl_30(0 downto 0) & l_2_c_0_cl_29(0 downto 0) & l_2_c_0_cl_28(0 downto 0) & l_2_c_0_cl_27(0 downto 0) & l_2_c_0_cl_26(0 downto 0) & l_2_c_0_cl_25(0 downto 0) & l_2_c_0_cl_24(0 downto 0) & l_2_c_0_cl_23(0 downto 0) & l_2_c_0_cl_22(0 downto 0) & l_2_c_0_cl_21(0 downto 0) & l_2_c_0_cl_20(0 downto 0) & l_2_c_0_cl_19(0 downto 0) & l_2_c_0_cl_18(0 downto 0) & l_2_c_0_cl_17(0 downto 0) & l_2_c_0_cl_16(0 downto 0) & l_2_c_0_cl_15(0 downto 0) & l_2_c_0_cl_14(0 downto 0) & l_2_c_0_cl_13(0 downto 0) & l_2_c_0_cl_12(0 downto 0) & l_2_c_0_cl_11(0 downto 0) & l_2_c_0_cl_10(0 downto 0) & l_2_c_0_cl_9(0 downto 0) & l_2_c_0_cl_8(0 downto 0) & l_2_c_0_cl_7(0 downto 0) & l_2_c_0_cl_6(0 downto 0) & l_2_c_0_cl_5(0 downto 0) & l_2_c_0_cl_4(0 downto 0) & l_2_c_0_cl_3(0 downto 0) & l_2_c_0_cl_2(0 downto 0) & l_2_c_0_cl_1(0 downto 0) & l_2_c_0_cl_0(0 downto 0);
l_2_s_1 <= l_2_c_0_cl_104(1 downto 1) & l_2_c_0_cl_103(1 downto 1) & l_2_c_0_cl_102(1 downto 1) & l_2_c_0_cl_101(1 downto 1) & l_2_c_0_cl_100(1 downto 1) & l_2_c_0_cl_99(1 downto 1) & l_2_c_0_cl_98(1 downto 1) & l_2_c_0_cl_97(1 downto 1) & l_2_c_0_cl_96(1 downto 1) & l_2_c_0_cl_95(1 downto 1) & l_2_c_0_cl_94(1 downto 1) & l_2_c_0_cl_93(1 downto 1) & l_2_c_0_cl_92(1 downto 1) & l_2_c_0_cl_91(1 downto 1) & l_2_c_0_cl_90(1 downto 1) & l_2_c_0_cl_89(1 downto 1) & l_2_c_0_cl_88(1 downto 1) & l_2_c_0_cl_87(1 downto 1) & l_2_c_0_cl_86(1 downto 1) & l_2_c_0_cl_85(1 downto 1) & l_2_c_0_cl_84(1 downto 1) & l_2_c_0_cl_83(1 downto 1) & l_2_c_0_cl_82(1 downto 1) & l_2_c_0_cl_81(1 downto 1) & l_2_c_0_cl_80(1 downto 1) & l_2_c_0_cl_79(1 downto 1) & l_2_c_0_cl_78(1 downto 1) & l_2_c_0_cl_77(1 downto 1) & l_2_c_0_cl_76(1 downto 1) & l_2_c_0_cl_75(1 downto 1) & l_2_c_0_cl_74(1 downto 1) & l_2_c_0_cl_73(1 downto 1) & l_2_c_0_cl_72(1 downto 1) & l_2_c_0_cl_71(1 downto 1) & l_2_c_0_cl_70(1 downto 1) & l_2_c_0_cl_69(1 downto 1) & l_2_c_0_cl_68(1 downto 1) & l_2_c_0_cl_67(1 downto 1) & l_2_c_0_cl_66(1 downto 1) & l_2_c_0_cl_65(1 downto 1) & l_2_c_0_cl_64(1 downto 1) & l_2_c_0_cl_63(1 downto 1) & l_2_c_0_cl_62(1 downto 1) & l_2_c_0_cl_61(1 downto 1) & l_2_c_0_cl_60(1 downto 1) & l_2_c_0_cl_59(1 downto 1) & l_2_c_0_cl_58(1 downto 1) & l_2_c_0_cl_57(1 downto 1) & l_2_c_0_cl_56(1 downto 1) & l_2_c_0_cl_55(1 downto 1) & l_2_c_0_cl_54(1 downto 1) & l_2_c_0_cl_53(1 downto 1) & l_2_c_0_cl_52(1 downto 1) & l_2_c_0_cl_51(1 downto 1) & l_2_c_0_cl_50(1 downto 1) & l_2_c_0_cl_49(1 downto 1) & l_2_c_0_cl_48(1 downto 1) & l_2_c_0_cl_47(1 downto 1) & l_2_c_0_cl_46(1 downto 1) & l_2_c_0_cl_45(1 downto 1) & l_2_c_0_cl_44(1 downto 1) & l_2_c_0_cl_43(1 downto 1) & l_2_c_0_cl_42(1 downto 1) & l_2_c_0_cl_41(1 downto 1) & l_2_c_0_cl_40(1 downto 1) & l_2_c_0_cl_39(1 downto 1) & l_2_c_0_cl_38(1 downto 1) & l_2_c_0_cl_37(1 downto 1) & l_2_c_0_cl_36(1 downto 1) & l_2_c_0_cl_35(1 downto 1) & l_2_c_0_cl_34(1 downto 1) & l_2_c_0_cl_33(1 downto 1) & l_2_c_0_cl_32(1 downto 1) & l_2_c_0_cl_31(1 downto 1) & l_2_c_0_cl_30(1 downto 1) & l_2_c_0_cl_29(1 downto 1) & l_2_c_0_cl_28(1 downto 1) & l_2_c_0_cl_27(1 downto 1) & l_2_c_0_cl_26(1 downto 1) & l_2_c_0_cl_25(1 downto 1) & l_2_c_0_cl_24(1 downto 1) & l_2_c_0_cl_23(1 downto 1) & l_2_c_0_cl_22(1 downto 1) & l_2_c_0_cl_21(1 downto 1) & l_2_c_0_cl_20(1 downto 1) & l_2_c_0_cl_19(1 downto 1) & l_2_c_0_cl_18(1 downto 1) & l_2_c_0_cl_17(1 downto 1) & l_2_c_0_cl_16(1 downto 1) & l_2_c_0_cl_15(1 downto 1) & l_2_c_0_cl_14(1 downto 1) & l_2_c_0_cl_13(1 downto 1) & l_2_c_0_cl_12(1 downto 1) & l_2_c_0_cl_11(1 downto 1) & l_2_c_0_cl_10(1 downto 1) & l_2_c_0_cl_9(1 downto 1) & l_2_c_0_cl_8(1 downto 1) & l_2_c_0_cl_7(1 downto 1) & l_2_c_0_cl_6(1 downto 1) & l_2_c_0_cl_5(1 downto 1) & l_2_c_0_cl_4(1 downto 1) & l_2_c_0_cl_3(1 downto 1) & l_2_c_0_cl_2(1 downto 1) & l_2_c_0_cl_1(1 downto 1) & l_2_c_0_cl_0(1 downto 1) & "0";
FinalAdder_CompressorTree: IntAdder_106_f400_uid29 -- pipelineDepth=3 maxInDelay=2.03808e-09
port map ( clk => clk,
rst => rst,
Cin => '0',
R => myR,
X => l_2_s_0,
Y => l_2_s_1);
----------------Synchro barrier, entering cycle 3----------------
R <= myR;
-- delay at adder output 1.174e-09
end architecture;
--------------------------------------------------------------------------------
-- IntTruncMultiplier_53_53_106_unsigned
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Sebastian Banescu, Bogdan Pasca, Radu Tudoran (2010-2011)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
library work;
entity IntTruncMultiplier_53_53_106_unsigned is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
Y : in std_logic_vector(52 downto 0);
R : out std_logic_vector(105 downto 0) );
end entity;
architecture arch of IntTruncMultiplier_53_53_106_unsigned is
component IntMultiAdder_106_op4_f400_uid25 is
port ( clk, rst : in std_logic;
X0 : in std_logic_vector(105 downto 0);
X1 : in std_logic_vector(105 downto 0);
X2 : in std_logic_vector(105 downto 0);
X3 : in std_logic_vector(105 downto 0);
R : out std_logic_vector(105 downto 0) );
end component;
component LogicIntMultiplier_24_2_uid17_1 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(23 downto 0);
Y : in std_logic_vector(1 downto 0);
R : out std_logic_vector(25 downto 0) );
end component;
component LogicIntMultiplier_5_34_uid5_0 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(4 downto 0);
Y : in std_logic_vector(33 downto 0);
R : out std_logic_vector(38 downto 0) );
end component;
signal x0_0 : std_logic_vector(17 downto 0);
signal y0_0 : std_logic_vector(24 downto 0);
signal pxy00, pxy00_d1, pxy00_d2, pxy00_d3, pxy00_d4 : std_logic_vector(42 downto 0);
signal x0_1, x0_1_d1 : std_logic_vector(17 downto 0);
signal y0_1, y0_1_d1 : std_logic_vector(24 downto 0);
signal txy01 : std_logic_vector(42 downto 0);
signal pxy01, pxy01_d1, pxy01_d2, pxy01_d3 : std_logic_vector(42 downto 0);
signal x0_2, x0_2_d1, x0_2_d2 : std_logic_vector(24 downto 0);
signal y0_2, y0_2_d1, y0_2_d2 : std_logic_vector(17 downto 0);
signal txy02 : std_logic_vector(42 downto 0);
signal pxy02, pxy02_d1, pxy02_d2 : std_logic_vector(42 downto 0);
signal x0_3, x0_3_d1, x0_3_d2, x0_3_d3 : std_logic_vector(24 downto 0);
signal y0_3, y0_3_d1, y0_3_d2, y0_3_d3 : std_logic_vector(17 downto 0);
signal txy03 : std_logic_vector(42 downto 0);
signal pxy03, pxy03_d1 : std_logic_vector(42 downto 0);
signal addOpDSP0 : std_logic_vector(105 downto 0);
signal x3_0 : std_logic_vector(24 downto 0);
signal y3_0 : std_logic_vector(17 downto 0);
signal pxy30, pxy30_d1, pxy30_d2, pxy30_d3 : std_logic_vector(42 downto 0);
signal x3_1, x3_1_d1 : std_logic_vector(24 downto 0);
signal y3_1, y3_1_d1 : std_logic_vector(17 downto 0);
signal txy31 : std_logic_vector(42 downto 0);
signal pxy31, pxy31_d1, pxy31_d2 : std_logic_vector(42 downto 0);
signal x3_2, x3_2_d1, x3_2_d2 : std_logic_vector(24 downto 0);
signal y3_2, y3_2_d1, y3_2_d2 : std_logic_vector(17 downto 0);
signal txy32 : std_logic_vector(42 downto 0);
signal pxy32, pxy32_d1 : std_logic_vector(42 downto 0);
signal addOpDSP1, addOpDSP1_d1 : std_logic_vector(105 downto 0);
signal x_0 : std_logic_vector(4 downto 0);
signal y_0 : std_logic_vector(33 downto 0);
signal result0 : std_logic_vector(38 downto 0);
signal addOpSlice0, addOpSlice0_d1 : std_logic_vector(105 downto 0);
signal x_1 : std_logic_vector(23 downto 0);
signal y_1 : std_logic_vector(1 downto 0);
signal result1 : std_logic_vector(25 downto 0);
signal addOpSlice1, addOpSlice1_d1, addOpSlice1_d2, addOpSlice1_d3, addOpSlice1_d4 : std_logic_vector(105 downto 0);
signal addRes : std_logic_vector(105 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
pxy00_d1 <= pxy00;
pxy00_d2 <= pxy00_d1;
pxy00_d3 <= pxy00_d2;
pxy00_d4 <= pxy00_d3;
x0_1_d1 <= x0_1;
y0_1_d1 <= y0_1;
pxy01_d1 <= pxy01;
pxy01_d2 <= pxy01_d1;
pxy01_d3 <= pxy01_d2;
x0_2_d1 <= x0_2;
x0_2_d2 <= x0_2_d1;
y0_2_d1 <= y0_2;
y0_2_d2 <= y0_2_d1;
pxy02_d1 <= pxy02;
pxy02_d2 <= pxy02_d1;
x0_3_d1 <= x0_3;
x0_3_d2 <= x0_3_d1;
x0_3_d3 <= x0_3_d2;
y0_3_d1 <= y0_3;
y0_3_d2 <= y0_3_d1;
y0_3_d3 <= y0_3_d2;
pxy03_d1 <= pxy03;
pxy30_d1 <= pxy30;
pxy30_d2 <= pxy30_d1;
pxy30_d3 <= pxy30_d2;
x3_1_d1 <= x3_1;
y3_1_d1 <= y3_1;
pxy31_d1 <= pxy31;
pxy31_d2 <= pxy31_d1;
x3_2_d1 <= x3_2;
x3_2_d2 <= x3_2_d1;
y3_2_d1 <= y3_2;
y3_2_d2 <= y3_2_d1;
pxy32_d1 <= pxy32;
addOpDSP1_d1 <= addOpDSP1;
addOpSlice0_d1 <= addOpSlice0;
addOpSlice1_d1 <= addOpSlice1;
addOpSlice1_d2 <= addOpSlice1_d1;
addOpSlice1_d3 <= addOpSlice1_d2;
addOpSlice1_d4 <= addOpSlice1_d3;
end if;
end process;
----------------Synchro barrier, entering cycle 0----------------
----------------Synchro barrier, entering cycle 0----------------
x0_0 <= "0" & "" & X(11 downto 0) & "00000";
y0_0 <= "0" & "" & Y(18 downto 0) & "00000";
pxy00 <= x0_0(17 downto 0) * y0_0(24 downto 0); --0
----------------Synchro barrier, entering cycle 0----------------
x0_1 <= "0" & "" & X(28 downto 12) & "";
y0_1 <= "0" & "" & Y(18 downto 0) & "00000";
----------------Synchro barrier, entering cycle 1----------------
txy01 <= x0_1_d1(17 downto 0) * y0_1_d1(24 downto 0);
pxy01 <= (txy01(42 downto 0)) + ("00000000000000000" &pxy00_d1(42 downto 17));
----------------Synchro barrier, entering cycle 4----------------
----------------Synchro barrier, entering cycle 0----------------
x0_2 <= "0" & "" & X(28 downto 5) & "";
y0_2 <= "0" & "" & Y(35 downto 19) & "";
----------------Synchro barrier, entering cycle 2----------------
txy02 <= x0_2_d2(24 downto 0) * y0_2_d2(17 downto 0);
pxy02 <= (txy02(42 downto 0)) + ("00000000000000000" &pxy01_d1(42 downto 17));
----------------Synchro barrier, entering cycle 4----------------
----------------Synchro barrier, entering cycle 0----------------
x0_3 <= "0" & "" & X(28 downto 5) & "";
y0_3 <= "0" & "" & Y(52 downto 36) & "";
----------------Synchro barrier, entering cycle 3----------------
txy03 <= x0_3_d3(24 downto 0) * y0_3_d3(17 downto 0);
pxy03 <= (txy03(42 downto 0)) + ("00000000000000000" &pxy02_d1(42 downto 17));
----------------Synchro barrier, entering cycle 4----------------
addOpDSP0 <= "000000000000000000000000" & pxy03_d1(40 downto 0) & pxy02_d2(16 downto 0) & pxy01_d3(16 downto 0) & pxy00_d4(16 downto 10) & "" & "";--3 bpadX 5 bpadY 5
----------------Synchro barrier, entering cycle 0----------------
----------------Synchro barrier, entering cycle 0----------------
x3_0 <= "0" & "" & X(52 downto 29) & "";
y3_0 <= "0" & "" & Y(18 downto 2) & "";
pxy30 <= x3_0(24 downto 0) * y3_0(17 downto 0); --0
----------------Synchro barrier, entering cycle 0----------------
x3_1 <= "0" & "" & X(52 downto 29) & "";
y3_1 <= "0" & "" & Y(35 downto 19) & "";
----------------Synchro barrier, entering cycle 1----------------
txy31 <= x3_1_d1(24 downto 0) * y3_1_d1(17 downto 0);
pxy31 <= (txy31(42 downto 0)) + ("00000000000000000" &pxy30_d1(42 downto 17));
----------------Synchro barrier, entering cycle 3----------------
----------------Synchro barrier, entering cycle 0----------------
x3_2 <= "0" & "" & X(52 downto 29) & "";
y3_2 <= "0" & "" & Y(52 downto 36) & "";
----------------Synchro barrier, entering cycle 2----------------
txy32 <= x3_2_d2(24 downto 0) * y3_2_d2(17 downto 0);
pxy32 <= (txy32(42 downto 0)) + ("00000000000000000" &pxy31_d1(42 downto 17));
----------------Synchro barrier, entering cycle 3----------------
addOpDSP1 <= "" & pxy32_d1(40 downto 0) & pxy31_d2(16 downto 0) & pxy30_d3(16 downto 0) & "0000000000000000000000000000000" & "";--3 bpadX 0 bpadY 0
----------------Synchro barrier, entering cycle 0----------------
x_0 <= X(4 downto 0);
y_0 <= Y(52 downto 19);
Mult0: LogicIntMultiplier_5_34_uid5_0 -- pipelineDepth=3 maxInDelay=0
port map ( clk => clk,
rst => rst,
R => result0,
X => x_0,
Y => y_0);
----------------Synchro barrier, entering cycle 3----------------
addOpSlice0 <= "000000000000000000000000000000000000000000000000" & result0 & "0000000000000000000";
----------------Synchro barrier, entering cycle 0----------------
x_1 <= X(52 downto 29);
y_1 <= Y(1 downto 0);
Mult1: LogicIntMultiplier_24_2_uid17_1 -- pipelineDepth=0 maxInDelay=0
port map ( clk => clk,
rst => rst,
R => result1,
X => x_1,
Y => y_1);
addOpSlice1 <= "000000000000000000000000000000000000000000000000000" & result1 & "00000000000000000000000000000";
----------------Synchro barrier, entering cycle 4----------------
adder: IntMultiAdder_106_op4_f400_uid25 -- pipelineDepth=3 maxInDelay=4.4472e-10
port map ( clk => clk,
rst => rst,
R => addRes,
X0 => addOpDSP0,
X1 => addOpDSP1_d1,
X2 => addOpSlice0_d1,
X3 => addOpSlice1_d4);
----------------Synchro barrier, entering cycle 7----------------
R <= addRes(105 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- IntAdder_65_f400_uid35
-- (IntAdderClassical_65_f400_uid37)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 2 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity IntAdder_65_f400_uid35 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(64 downto 0);
Y : in std_logic_vector(64 downto 0);
Cin : in std_logic;
R : out std_logic_vector(64 downto 0) );
end entity;
architecture arch of IntAdder_65_f400_uid35 is
signal x0 : std_logic_vector(10 downto 0);
signal y0 : std_logic_vector(10 downto 0);
signal x1, x1_d1 : std_logic_vector(41 downto 0);
signal y1, y1_d1 : std_logic_vector(41 downto 0);
signal x2, x2_d1, x2_d2 : std_logic_vector(11 downto 0);
signal y2, y2_d1, y2_d2 : std_logic_vector(11 downto 0);
signal sum0, sum0_d1, sum0_d2 : std_logic_vector(11 downto 0);
signal sum1, sum1_d1 : std_logic_vector(42 downto 0);
signal sum2 : std_logic_vector(12 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
x1_d1 <= x1;
y1_d1 <= y1;
x2_d1 <= x2;
x2_d2 <= x2_d1;
y2_d1 <= y2;
y2_d2 <= y2_d1;
sum0_d1 <= sum0;
sum0_d2 <= sum0_d1;
sum1_d1 <= sum1;
end if;
end process;
--Classical
x0 <= X(10 downto 0);
y0 <= Y(10 downto 0);
x1 <= X(52 downto 11);
y1 <= Y(52 downto 11);
x2 <= X(64 downto 53);
y2 <= Y(64 downto 53);
sum0 <= ( "0" & x0) + ( "0" & y0) + Cin;
----------------Synchro barrier, entering cycle 1----------------
sum1 <= ( "0" & x1_d1) + ( "0" & y1_d1) + sum0_d1(11);
----------------Synchro barrier, entering cycle 2----------------
sum2 <= ( "0" & x2_d2) + ( "0" & y2_d2) + sum1_d1(42);
R <= sum2(11 downto 0) & sum1_d1(41 downto 0) & sum0_d2(10 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- FPMultiplier_11_52_11_52_11_52_uid2
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Bogdan Pasca, Florent de Dinechin 2008-2011
--------------------------------------------------------------------------------
-- Pipeline depth: 11 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity FPMultiplier_11_52_11_52_11_52_uid2 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(11+52+2 downto 0);
Y : in std_logic_vector(11+52+2 downto 0);
R : out std_logic_vector(11+52+2 downto 0) );
end entity;
architecture arch of FPMultiplier_11_52_11_52_11_52_uid2 is
component IntAdder_65_f400_uid35 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(64 downto 0);
Y : in std_logic_vector(64 downto 0);
Cin : in std_logic;
R : out std_logic_vector(64 downto 0) );
end component;
component IntTruncMultiplier_53_53_106_unsigned is
port ( clk, rst : in std_logic;
X : in std_logic_vector(52 downto 0);
Y : in std_logic_vector(52 downto 0);
R : out std_logic_vector(105 downto 0) );
end component;
signal sign, sign_d1, sign_d2, sign_d3, sign_d4, sign_d5, sign_d6, sign_d7, sign_d8, sign_d9, sign_d10, sign_d11 : std_logic;
signal expX : std_logic_vector(10 downto 0);
signal expY : std_logic_vector(10 downto 0);
signal expSumPreSub, expSumPreSub_d1 : std_logic_vector(12 downto 0);
signal bias, bias_d1 : std_logic_vector(12 downto 0);
signal expSum, expSum_d1, expSum_d2, expSum_d3, expSum_d4, expSum_d5, expSum_d6, expSum_d7 : std_logic_vector(12 downto 0);
signal sigX : std_logic_vector(52 downto 0);
signal sigY : std_logic_vector(52 downto 0);
signal sigProd : std_logic_vector(105 downto 0);
signal excSel : std_logic_vector(3 downto 0);
signal exc, exc_d1, exc_d2, exc_d3, exc_d4, exc_d5, exc_d6, exc_d7, exc_d8, exc_d9, exc_d10, exc_d11 : std_logic_vector(1 downto 0);
signal norm, norm_d1 : std_logic;
signal expPostNorm : std_logic_vector(12 downto 0);
signal sigProdExt, sigProdExt_d1, sigProdExt_d2 : std_logic_vector(105 downto 0);
signal expSig, expSig_d1 : std_logic_vector(64 downto 0);
signal sticky, sticky_d1 : std_logic;
signal guard : std_logic;
signal round : std_logic;
signal expSigPostRound : std_logic_vector(64 downto 0);
signal excPostNorm : std_logic_vector(1 downto 0);
signal finalExc : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
sign_d1 <= sign;
sign_d2 <= sign_d1;
sign_d3 <= sign_d2;
sign_d4 <= sign_d3;
sign_d5 <= sign_d4;
sign_d6 <= sign_d5;
sign_d7 <= sign_d6;
sign_d8 <= sign_d7;
sign_d9 <= sign_d8;
sign_d10 <= sign_d9;
sign_d11 <= sign_d10;
expSumPreSub_d1 <= expSumPreSub;
bias_d1 <= bias;
expSum_d1 <= expSum;
expSum_d2 <= expSum_d1;
expSum_d3 <= expSum_d2;
expSum_d4 <= expSum_d3;
expSum_d5 <= expSum_d4;
expSum_d6 <= expSum_d5;
expSum_d7 <= expSum_d6;
exc_d1 <= exc;
exc_d2 <= exc_d1;
exc_d3 <= exc_d2;
exc_d4 <= exc_d3;
exc_d5 <= exc_d4;
exc_d6 <= exc_d5;
exc_d7 <= exc_d6;
exc_d8 <= exc_d7;
exc_d9 <= exc_d8;
exc_d10 <= exc_d9;
exc_d11 <= exc_d10;
norm_d1 <= norm;
sigProdExt_d1 <= sigProdExt;
sigProdExt_d2 <= sigProdExt_d1;
expSig_d1 <= expSig;
sticky_d1 <= sticky;
end if;
end process;
sign <= X(63) xor Y(63);
expX <= X(62 downto 52);
expY <= Y(62 downto 52);
expSumPreSub <= ("00" & expX) + ("00" & expY);
bias <= CONV_STD_LOGIC_VECTOR(1023,13);
----------------Synchro barrier, entering cycle 1----------------
expSum <= expSumPreSub_d1 - bias_d1;
----------------Synchro barrier, entering cycle 0----------------
sigX <= "1" & X(51 downto 0);
sigY <= "1" & Y(51 downto 0);
SignificandMultiplication: IntTruncMultiplier_53_53_106_unsigned -- pipelineDepth=7 maxInDelay=0
port map ( clk => clk,
rst => rst,
R => sigProd,
X => sigX,
Y => sigY);
----------------Synchro barrier, entering cycle 7----------------
----------------Synchro barrier, entering cycle 0----------------
excSel <= X(65 downto 64) & Y(65 downto 64);
with excSel select
exc <= "00" when "0000" | "0001" | "0100",
"01" when "0101",
"10" when "0110" | "1001" | "1010" ,
"11" when others;
----------------Synchro barrier, entering cycle 7----------------
norm <= sigProd(105);
----------------Synchro barrier, entering cycle 8----------------
-- exponent update
expPostNorm <= expSum_d7 + ("000000000000" & norm_d1);
----------------Synchro barrier, entering cycle 7----------------
-- significand normalization shift
sigProdExt <= sigProd(104 downto 0) & "0" when norm='1' else
sigProd(103 downto 0) & "00";
----------------Synchro barrier, entering cycle 8----------------
expSig <= expPostNorm & sigProdExt_d1(105 downto 54);
sticky <= sigProdExt_d1(53);
----------------Synchro barrier, entering cycle 9----------------
guard <= '0' when sigProdExt_d2(52 downto 0)="00000000000000000000000000000000000000000000000000000" else '1';
round <= sticky_d1 and ( (guard and not(sigProdExt_d2(54))) or (sigProdExt_d2(54) )) ;
RoundingAdder: IntAdder_65_f400_uid35 -- pipelineDepth=2 maxInDelay=1.57344e-09
port map ( clk => clk,
rst => rst,
Cin => round,
R => expSigPostRound ,
X => expSig_d1,
Y => "00000000000000000000000000000000000000000000000000000000000000000");
----------------Synchro barrier, entering cycle 11----------------
with expSigPostRound(64 downto 63) select
excPostNorm <= "01" when "00",
"10" when "01",
"00" when "11"|"10",
"11" when others;
with exc_d11 select
finalExc <= exc_d11 when "11"|"10"|"00",
excPostNorm when others;
R <= finalExc & sign_d11 & expSigPostRound(62 downto 0);
end architecture;
|
apache-2.0
|
3a45fe83b0ab6dd8edd0feb8783eeeaa
| 0.544097 | 2.214445 | false | false | false | false |
hoangt/PoC
|
src/io/ddrio/ddrio_in_xilinx.vhdl
| 2 | 2,291 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiates Chip-Specific DDR Input Registers for Xilinx FPGAs.
--
-- Description:
-- ------------------------------------
-- See PoC.io.ddrio.in for interface description.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
library UniSim;
use UniSim.vComponents.all;
entity ddrio_in_xilinx is
generic (
BITS : POSITIVE;
INIT_VALUE_HIGH : BIT_VECTOR := "1";
INIT_VALUE_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : in STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_in_xilinx is
begin
gen : for i in 0 to WIDTH - 1 generate
iff : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT_Q1 => INIT_VALUE_HIGH(i),
INIT_Q2 => INIT_VALUE_LOW(i),
SRTYPE => "SYNC"
)
port map (
C => Clock,
CE => ClockEnable,
D => Pad(i),
Q1 => DataIn_high(i),
Q2 => DataIn_low(i),
R => '0',
S => '0'
);
end generate;
end architecture;
|
apache-2.0
|
62f066830f8ccaed2a0b722e6b855b7e
| 0.573985 | 3.460725 | false | false | false | false |
hoangt/PoC
|
tb/common/my_config_VC707.vhdl
| 2 | 1,760 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "VC707"; -- VC707 - Xilinx Virtex 7 reference design board: XC7V485T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
|
apache-2.0
|
d91738d6e9c6edecf4ddb39859655e79
| 0.580682 | 4.433249 | false | true | false | false |
olofk/oh
|
xilibs/ip/fifo_async_104x32/fifo_async_104x32_funcsim.vhdl
| 1 | 209,982 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
-- Date : Fri Sep 18 12:15:17 2015
-- Host : parallella running 64-bit Ubuntu 14.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/aolofsson/Work_all/oh/xilibs/ip/fifo_async_104x32/fifo_async_104x32_funcsim.vhdl
-- Design : fifo_async_104x32
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z015clg485-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_dmem is
port (
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_pntr_plus1_pad : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 103 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_dmem : entity is "dmem";
end fifo_async_104x32_dmem;
architecture STRUCTURE of fifo_async_104x32_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 103 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_103_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_103_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_103_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_102_103: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(103 downto 102),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(103 downto 102),
DOB(1 downto 0) => NLW_RAM_reg_0_31_102_103_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_102_103_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_102_103_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1 downto 0) => din(65 downto 64),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1 downto 0) => p_0_out(65 downto 64),
DOD(1 downto 0) => NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(67 downto 66),
DIB(1 downto 0) => din(69 downto 68),
DIC(1 downto 0) => din(71 downto 70),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(67 downto 66),
DOB(1 downto 0) => p_0_out(69 downto 68),
DOC(1 downto 0) => p_0_out(71 downto 70),
DOD(1 downto 0) => NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(73 downto 72),
DIB(1 downto 0) => din(75 downto 74),
DIC(1 downto 0) => din(77 downto 76),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(73 downto 72),
DOB(1 downto 0) => p_0_out(75 downto 74),
DOC(1 downto 0) => p_0_out(77 downto 76),
DOD(1 downto 0) => NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(79 downto 78),
DIB(1 downto 0) => din(81 downto 80),
DIC(1 downto 0) => din(83 downto 82),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(79 downto 78),
DOB(1 downto 0) => p_0_out(81 downto 80),
DOC(1 downto 0) => p_0_out(83 downto 82),
DOD(1 downto 0) => NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(85 downto 84),
DIB(1 downto 0) => din(87 downto 86),
DIC(1 downto 0) => din(89 downto 88),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(85 downto 84),
DOB(1 downto 0) => p_0_out(87 downto 86),
DOC(1 downto 0) => p_0_out(89 downto 88),
DOD(1 downto 0) => NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(91 downto 90),
DIB(1 downto 0) => din(93 downto 92),
DIC(1 downto 0) => din(95 downto 94),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(91 downto 90),
DOB(1 downto 0) => p_0_out(93 downto 92),
DOC(1 downto 0) => p_0_out(95 downto 94),
DOD(1 downto 0) => NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
RAM_reg_0_31_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
ADDRD(4 downto 0) => Q(4 downto 0),
DIA(1 downto 0) => din(97 downto 96),
DIB(1 downto 0) => din(99 downto 98),
DIC(1 downto 0) => din(101 downto 100),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(97 downto 96),
DOB(1 downto 0) => p_0_out(99 downto 98),
DOC(1 downto 0) => p_0_out(101 downto 100),
DOD(1 downto 0) => NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => wr_pntr_plus1_pad(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(0),
Q => dout(0)
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(100),
Q => dout(100)
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(101),
Q => dout(101)
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(102),
Q => dout(102)
);
\gpr1.dout_i_reg[103]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(103),
Q => dout(103)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(10),
Q => dout(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(11),
Q => dout(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(12),
Q => dout(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(13),
Q => dout(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(14),
Q => dout(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(15),
Q => dout(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(16),
Q => dout(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(17),
Q => dout(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(18),
Q => dout(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(19),
Q => dout(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(1),
Q => dout(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(20),
Q => dout(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(21),
Q => dout(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(22),
Q => dout(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(23),
Q => dout(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(24),
Q => dout(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(25),
Q => dout(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(26),
Q => dout(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(27),
Q => dout(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(28),
Q => dout(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(29),
Q => dout(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(2),
Q => dout(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(30),
Q => dout(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(31),
Q => dout(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(32),
Q => dout(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(33),
Q => dout(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(34),
Q => dout(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(35),
Q => dout(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(36),
Q => dout(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(37),
Q => dout(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(38),
Q => dout(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(39),
Q => dout(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(3),
Q => dout(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(40),
Q => dout(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(41),
Q => dout(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(42),
Q => dout(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(43),
Q => dout(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(44),
Q => dout(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(45),
Q => dout(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(46),
Q => dout(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(47),
Q => dout(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(48),
Q => dout(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(49),
Q => dout(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(4),
Q => dout(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(50),
Q => dout(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(51),
Q => dout(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(52),
Q => dout(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(53),
Q => dout(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(54),
Q => dout(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(55),
Q => dout(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(56),
Q => dout(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(57),
Q => dout(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(58),
Q => dout(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(59),
Q => dout(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(5),
Q => dout(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(60),
Q => dout(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(61),
Q => dout(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(62),
Q => dout(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(63),
Q => dout(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(64),
Q => dout(64)
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(65),
Q => dout(65)
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(66),
Q => dout(66)
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(67),
Q => dout(67)
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(68),
Q => dout(68)
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(69),
Q => dout(69)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(6),
Q => dout(6)
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(70),
Q => dout(70)
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(71),
Q => dout(71)
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(72),
Q => dout(72)
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(73),
Q => dout(73)
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(74),
Q => dout(74)
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(75),
Q => dout(75)
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(76),
Q => dout(76)
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(77),
Q => dout(77)
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(78),
Q => dout(78)
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(79),
Q => dout(79)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(7),
Q => dout(7)
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(80),
Q => dout(80)
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(81),
Q => dout(81)
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(82),
Q => dout(82)
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(83),
Q => dout(83)
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(84),
Q => dout(84)
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(85),
Q => dout(85)
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(86),
Q => dout(86)
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(87),
Q => dout(87)
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(88),
Q => dout(88)
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(89),
Q => dout(89)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(8),
Q => dout(8)
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(90),
Q => dout(90)
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(91),
Q => dout(91)
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(92),
Q => dout(92)
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(93),
Q => dout(93)
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(94),
Q => dout(94)
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(95),
Q => dout(95)
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(96),
Q => dout(96)
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(97),
Q => dout(97)
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(98),
Q => dout(98)
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(99),
Q => dout(99)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_pntr_gc_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC;
\wr_pntr_bin_reg[4]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_async_104x32_rd_bin_cntr;
architecture STRUCTURE of fifo_async_104x32_rd_bin_cntr is
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal \^rd_pntr_gc_reg[4]\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ram_empty_i_i_4 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
begin
\rd_pntr_gc_reg[4]\(4 downto 0) <= \^rd_pntr_gc_reg[4]\(4 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => \plusOp__0\(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => rd_pntr_plus1(0),
Q => \^rd_pntr_gc_reg[4]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => rd_pntr_plus1(1),
Q => \^rd_pntr_gc_reg[4]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => rd_pntr_plus1(2),
Q => \^rd_pntr_gc_reg[4]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => rd_pntr_plus1(3),
Q => \^rd_pntr_gc_reg[4]\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => rd_pntr_plus1(4),
Q => \^rd_pntr_gc_reg[4]\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => rd_rst,
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \plusOp__0\(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \plusOp__0\(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \plusOp__0\(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \plusOp__0\(4),
Q => rd_pntr_plus1(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF82000082"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => rd_pntr_plus1(2),
I2 => Q(2),
I3 => rd_pntr_plus1(3),
I4 => Q(3),
I5 => \wr_pntr_bin_reg[4]\,
O => ram_empty_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"90090000"
)
port map (
I0 => Q(4),
I1 => rd_pntr_plus1(4),
I2 => Q(1),
I3 => rd_pntr_plus1(1),
I4 => ram_empty_i_i_4_n_0,
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0900"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => Q(0),
I2 => p_18_out,
I3 => rd_en,
O => ram_empty_i_i_4_n_0
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^rd_pntr_gc_reg[4]\(0),
I1 => \^rd_pntr_gc_reg[4]\(1),
O => D(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^rd_pntr_gc_reg[4]\(1),
I1 => \^rd_pntr_gc_reg[4]\(2),
O => D(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^rd_pntr_gc_reg[4]\(2),
I1 => \^rd_pntr_gc_reg[4]\(3),
O => D(2)
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^rd_pntr_gc_reg[4]\(3),
I1 => \^rd_pntr_gc_reg[4]\(4),
O => D(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_rd_handshaking_flags is
port (
valid : out STD_LOGIC;
ram_empty_i_reg : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_rd_handshaking_flags : entity is "rd_handshaking_flags";
end fifo_async_104x32_rd_handshaking_flags;
architecture STRUCTURE of fifo_async_104x32_rd_handshaking_flags is
begin
\gv.ram_valid_d1_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => ram_empty_i_reg,
Q => valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gv.ram_valid_d1_reg\ : out STD_LOGIC;
\gc0.count_d1_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_async_104x32_rd_status_flags_as;
architecture STRUCTURE of fifo_async_104x32_rd_status_flags_as is
signal \^empty\ : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gpr1.dout_i[103]_i_1\ : label is "soft_lutpair2";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= \^empty\;
p_18_out <= \^p_18_out\;
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => \gc0.count_d1_reg[4]\(0)
);
\gpr1.dout_i[103]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
\gv.ram_valid_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^empty\,
O => \gv.ram_valid_d1_reg\
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gc0.count_reg[2]\,
PRE => rd_rst,
Q => \^p_18_out\
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gc0.count_reg[2]\,
PRE => rd_rst,
Q => \^empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_synchronizer_ff : entity is "synchronizer_ff";
end fifo_async_104x32_synchronizer_ff;
architecture STRUCTURE of fifo_async_104x32_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
begin
D(4 downto 0) <= Q_reg(4 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => Q(4),
Q => Q_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_synchronizer_ff_0 is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_async_104x32_synchronizer_ff_0;
architecture STRUCTURE of fifo_async_104x32_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
begin
D(4 downto 0) <= Q_reg(4 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => Q(4),
Q => Q_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_async_104x32_synchronizer_ff_1;
architecture STRUCTURE of fifo_async_104x32_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
begin
\out\(0) <= Q_reg(4);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(4),
Q => Q_reg(4)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(0),
I2 => Q_reg(1),
I3 => Q_reg(4),
I4 => Q_reg(3),
O => \wr_pntr_bin_reg[3]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(4),
I3 => Q_reg(3),
O => \wr_pntr_bin_reg[3]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(2),
I2 => Q_reg(4),
O => \wr_pntr_bin_reg[3]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(4),
O => \wr_pntr_bin_reg[3]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_synchronizer_ff_2 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_async_104x32_synchronizer_ff_2;
architecture STRUCTURE of fifo_async_104x32_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
begin
\out\(0) <= Q_reg(4);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => D(4),
Q => Q_reg(4)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(0),
I2 => Q_reg(1),
I3 => Q_reg(4),
I4 => Q_reg(3),
O => \rd_pntr_bin_reg[3]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(4),
I3 => Q_reg(3),
O => \rd_pntr_bin_reg[3]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(2),
I2 => Q_reg(4),
O => \rd_pntr_bin_reg[3]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(4),
O => \rd_pntr_bin_reg[3]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_wr_bin_cntr is
port (
S : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wr_pntr_gc_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_full_i : out STD_LOGIC;
comp2 : out STD_LOGIC;
\gaf.ram_almost_full_i_reg\ : out STD_LOGIC;
\rd_pntr_bin_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_2_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_async_104x32_wr_bin_cntr;
architecture STRUCTURE of fifo_async_104x32_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^comp2\ : STD_LOGIC;
signal \gaf.ram_almost_full_i_i_3_n_0\ : STD_LOGIC;
signal \gaf.ram_almost_full_i_i_4_n_0\ : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 4 to 4 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_plus3 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gaf.ram_almost_full_i_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc1.count[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc1.count[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gic0.gc1.count[4]_i_1\ : label is "soft_lutpair7";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
comp2 <= \^comp2\;
\gaf.ram_almost_full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000100100000000"
)
port map (
I0 => \gaf.ram_almost_full_i_i_3_n_0\,
I1 => \gaf.ram_almost_full_i_i_4_n_0\,
I2 => \rd_pntr_bin_reg[4]\(3),
I3 => wr_pntr_plus3(3),
I4 => p_2_out,
I5 => wr_en,
O => \gaf.ram_almost_full_i_reg\
);
\gaf.ram_almost_full_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus3(4),
I1 => \rd_pntr_bin_reg[4]\(4),
I2 => wr_pntr_plus3(2),
I3 => \rd_pntr_bin_reg[4]\(2),
O => \gaf.ram_almost_full_i_i_3_n_0\
);
\gaf.ram_almost_full_i_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus3(1),
I1 => \rd_pntr_bin_reg[4]\(1),
I2 => wr_pntr_plus3(0),
I3 => \rd_pntr_bin_reg[4]\(0),
O => \gaf.ram_almost_full_i_i_4_n_0\
);
\gdiff.diff_pntr_pad[5]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_8_out(4),
I1 => \rd_pntr_bin_reg[4]\(4),
O => \gdiff.diff_pntr_pad_reg[5]\(1)
);
\gdiff.diff_pntr_pad[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \rd_pntr_bin_reg[4]\(3),
O => \gdiff.diff_pntr_pad_reg[5]\(0)
);
\gdiff.diff_pntr_pad[5]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \rd_pntr_bin_reg[4]\(2),
O => S(2)
);
\gdiff.diff_pntr_pad[5]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \rd_pntr_bin_reg[4]\(1),
O => S(1)
);
\gdiff.diff_pntr_pad[5]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => \rd_pntr_bin_reg[4]\(0),
O => S(0)
);
\gic0.gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus3(0),
O => \plusOp__1\(0)
);
\gic0.gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
O => \plusOp__1\(1)
);
\gic0.gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(2),
O => \plusOp__1\(2)
);
\gic0.gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus3(1),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(2),
I3 => wr_pntr_plus3(3),
O => \plusOp__1\(3)
);
\gic0.gc1.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus3(2),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(1),
I3 => wr_pntr_plus3(3),
I4 => wr_pntr_plus3(4),
O => \plusOp__1\(4)
);
\gic0.gc1.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus3(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc1.count_d1_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus3(1),
PRE => wr_rst,
Q => wr_pntr_plus2(1)
);
\gic0.gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus3(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus3(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc1.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus3(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc1.count_d2_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => wr_rst,
Q => \^q\(0)
);
\gic0.gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc1.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(4),
Q => p_8_out(4)
);
\gic0.gc1.count_d3_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(0),
Q => \wr_pntr_gc_reg[4]\(0)
);
\gic0.gc1.count_d3_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(1),
Q => \wr_pntr_gc_reg[4]\(1)
);
\gic0.gc1.count_d3_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(2),
Q => \wr_pntr_gc_reg[4]\(2)
);
\gic0.gc1.count_d3_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(3),
Q => \wr_pntr_gc_reg[4]\(3)
);
\gic0.gc1.count_d3_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => p_8_out(4),
Q => \wr_pntr_gc_reg[4]\(4)
);
\gic0.gc1.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(0),
PRE => wr_rst,
Q => wr_pntr_plus3(0)
);
\gic0.gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => wr_rst,
Q => wr_pntr_plus3(1)
);
\gic0.gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__1\(2),
Q => wr_pntr_plus3(2)
);
\gic0.gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__1\(3),
Q => wr_pntr_plus3(3)
);
\gic0.gc1.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__1\(4),
Q => wr_pntr_plus3(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"4141FF4141414141"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => \rd_pntr_bin_reg[4]\(3),
I2 => \^q\(3),
I3 => wr_en,
I4 => p_2_out,
I5 => \^comp2\,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => \rd_pntr_bin_reg[4]\(2),
I1 => \^q\(2),
I2 => \rd_pntr_bin_reg[4]\(4),
I3 => p_8_out(4),
I4 => ram_full_i_i_4_n_0,
O => ram_full_i_i_2_n_0
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0009"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => \rd_pntr_bin_reg[4]\(3),
I2 => ram_full_i_i_5_n_0,
I3 => ram_full_i_i_6_n_0,
O => \^comp2\
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(1),
I1 => \rd_pntr_bin_reg[4]\(1),
I2 => \^q\(0),
I3 => \rd_pntr_bin_reg[4]\(0),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => \rd_pntr_bin_reg[4]\(1),
I2 => wr_pntr_plus2(0),
I3 => \rd_pntr_bin_reg[4]\(0),
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => \rd_pntr_bin_reg[4]\(4),
I2 => wr_pntr_plus2(2),
I3 => \rd_pntr_bin_reg[4]\(2),
O => ram_full_i_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
p_2_out : in STD_LOGIC;
wr_pntr_plus1_pad : in STD_LOGIC_VECTOR ( 4 downto 0 );
S : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc1.count_d2_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_wr_pf_as : entity is "wr_pf_as";
end fifo_async_104x32_wr_pf_as;
architecture STRUCTURE of fifo_async_104x32_wr_pf_as is
signal \gdiff.diff_pntr_pad_reg[5]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[5]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[5]_i_2_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[5]_i_2_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[5]_i_2_n_3\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^prog_full\ : STD_LOGIC;
signal prog_full_i : STD_LOGIC;
signal \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => plusOp(5),
Q => prog_full_i
);
\gdiff.diff_pntr_pad_reg[5]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[5]_i_2_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[5]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => wr_pntr_plus1_pad(4),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => plusOp(5 downto 4),
S(3) => '0',
S(2) => '0',
S(1 downto 0) => \gic0.gc1.count_d2_reg[4]\(1 downto 0)
);
\gdiff.diff_pntr_pad_reg[5]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[5]_i_2_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[5]_i_2_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[5]_i_2_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[5]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => wr_pntr_plus1_pad(3 downto 0),
O(3 downto 0) => plusOp(3 downto 0),
S(3 downto 1) => S(2 downto 0),
S(0) => '0'
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^prog_full\,
I1 => p_2_out,
I2 => prog_full_i,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gpf1.prog_full_i_i_1_n_0\,
Q => \^prog_full\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_2_out : out STD_LOGIC;
almost_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_pntr_plus1_pad : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp2 : in STD_LOGIC;
\rd_pntr_bin_reg[3]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_async_104x32_wr_status_flags_as;
architecture STRUCTURE of fifo_async_104x32_wr_status_flags_as is
signal \^almost_full\ : STD_LOGIC;
signal \gaf.ram_almost_full_i_i_1_n_0\ : STD_LOGIC;
signal \^p_2_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
almost_full <= \^almost_full\;
p_2_out <= \^p_2_out\;
\gaf.ram_almost_full_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBB8"
)
port map (
I0 => \^almost_full\,
I1 => \^p_2_out\,
I2 => comp2,
I3 => \rd_pntr_bin_reg[3]\,
O => \gaf.ram_almost_full_i_i_1_n_0\
);
\gaf.ram_almost_full_i_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gaf.ram_almost_full_i_i_1_n_0\,
Q => \^almost_full\
);
\gdiff.diff_pntr_pad[5]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_2_out\,
O => wr_pntr_plus1_pad(0)
);
\gic0.gc1.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_2_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => ram_full_i,
Q => \^p_2_out\
);
ram_full_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => ram_full_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_clk_x_pntrs is
port (
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gdiff.diff_pntr_pad_reg[5]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gic0.gc1.count_d3_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_async_104x32_clk_x_pntrs;
architecture STRUCTURE of fifo_async_104x32_clk_x_pntrs is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gsync_stage[2].rd_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].rd_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
signal p_0_in3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_1_out : STD_LOGIC_VECTOR ( 4 to 4 );
signal p_2_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_empty_i_i_5_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_async_104x32_synchronizer_ff
port map (
D(4 downto 0) => p_3_out(4 downto 0),
Q(4 downto 0) => wr_pntr_gc(4 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_async_104x32_synchronizer_ff_0
port map (
D(4 downto 0) => p_2_out(4 downto 0),
Q(4 downto 0) => rd_pntr_gc(4 downto 0),
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_async_104x32_synchronizer_ff_1
port map (
D(4 downto 0) => p_3_out(4 downto 0),
\out\(0) => p_1_out(4),
rd_clk => rd_clk,
rd_rst => rd_rst,
\wr_pntr_bin_reg[3]\(3) => p_0_in0,
\wr_pntr_bin_reg[3]\(2) => \gsync_stage[2].rd_stg_inst_n_2\,
\wr_pntr_bin_reg[3]\(1) => \gsync_stage[2].rd_stg_inst_n_3\,
\wr_pntr_bin_reg[3]\(0) => \gsync_stage[2].rd_stg_inst_n_4\
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_async_104x32_synchronizer_ff_2
port map (
D(4 downto 0) => p_2_out(4 downto 0),
\out\(0) => p_0_out(4),
\rd_pntr_bin_reg[3]\(3) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[3]\(2) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[3]\(1) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[3]\(0) => \gsync_stage[2].wr_stg_inst_n_4\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
ram_empty_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"82000082"
)
port map (
I0 => ram_empty_i_i_5_n_0,
I1 => \^q\(4),
I2 => \gc0.count_d1_reg[4]\(4),
I3 => \^q\(3),
I4 => \gc0.count_d1_reg[4]\(3),
O => ram_empty_i_reg
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[4]\(2),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[4]\(1),
I4 => \gc0.count_d1_reg[4]\(0),
I5 => \^q\(0),
O => ram_empty_i_i_5_n_0
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => \gdiff.diff_pntr_pad_reg[5]\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => \gdiff.diff_pntr_pad_reg[5]\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => \gdiff.diff_pntr_pad_reg[5]\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => \gdiff.diff_pntr_pad_reg[5]\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_out(4),
Q => \gdiff.diff_pntr_pad_reg[5]\(4)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(3),
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => \gc0.count_d1_reg[4]\(4),
Q => rd_pntr_gc(4)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => \gsync_stage[2].rd_stg_inst_n_4\,
Q => \^q\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => \gsync_stage[2].rd_stg_inst_n_3\,
Q => \^q\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => \gsync_stage[2].rd_stg_inst_n_2\,
Q => \^q\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in0,
Q => \^q\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_1_out(4),
Q => \^q\(4)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[4]\(0),
I1 => \gic0.gc1.count_d3_reg[4]\(1),
O => p_0_in3_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[4]\(1),
I1 => \gic0.gc1.count_d3_reg[4]\(2),
O => p_0_in3_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[4]\(2),
I1 => \gic0.gc1.count_d3_reg[4]\(3),
O => p_0_in3_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[4]\(3),
I1 => \gic0.gc1.count_d3_reg[4]\(4),
O => p_0_in3_out(3)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in3_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in3_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in3_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in3_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \gic0.gc1.count_d3_reg[4]\(4),
Q => wr_pntr_gc(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_memory is
port (
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_pntr_plus1_pad : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 103 downto 0 );
\gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_memory : entity is "memory";
end fifo_async_104x32_memory;
architecture STRUCTURE of fifo_async_104x32_memory is
begin
\gdm.dm\: entity work.fifo_async_104x32_dmem
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
din(103 downto 0) => din(103 downto 0),
dout(103 downto 0) => dout(103 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_pntr_plus1_pad(0) => wr_pntr_plus1_pad(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_rd_logic is
port (
empty : out STD_LOGIC;
valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rd_pntr_gc_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\wr_pntr_bin_reg[4]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_rd_logic : entity is "rd_logic";
end fifo_async_104x32_rd_logic;
architecture STRUCTURE of fifo_async_104x32_rd_logic is
signal \gras.rsts_n_3\ : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rpntr_n_9 : STD_LOGIC;
begin
\gras.rsts\: entity work.fifo_async_104x32_rd_status_flags_as
port map (
E(0) => E(0),
empty => empty,
\gc0.count_d1_reg[4]\(0) => p_14_out,
\gc0.count_reg[2]\ => rpntr_n_9,
\gv.ram_valid_d1_reg\ => \gras.rsts_n_3\,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst
);
\grhf.rhf\: entity work.fifo_async_104x32_rd_handshaking_flags
port map (
ram_empty_i_reg => \gras.rsts_n_3\,
rd_clk => rd_clk,
rd_rst => rd_rst,
valid => valid
);
rpntr: entity work.fifo_async_104x32_rd_bin_cntr
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => p_14_out,
Q(4 downto 0) => Q(4 downto 0),
p_18_out => p_18_out,
ram_empty_i_reg => rpntr_n_9,
rd_clk => rd_clk,
rd_en => rd_en,
\rd_pntr_gc_reg[4]\(4 downto 0) => \rd_pntr_gc_reg[4]\(4 downto 0),
rd_rst => rd_rst,
\wr_pntr_bin_reg[4]\ => \wr_pntr_bin_reg[4]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_wr_logic is
port (
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
\rd_pntr_bin_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_wr_logic : entity is "wr_logic";
end fifo_async_104x32_wr_logic;
architecture STRUCTURE of fifo_async_104x32_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal comp2 : STD_LOGIC;
signal \gwas.wsts_n_4\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i : STD_LOGIC;
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_16 : STD_LOGIC;
signal wpntr_n_2 : STD_LOGIC;
signal wpntr_n_7 : STD_LOGIC;
signal wpntr_n_8 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.gpf.wrpf\: entity work.fifo_async_104x32_wr_pf_as
port map (
S(2) => wpntr_n_0,
S(1) => wpntr_n_1,
S(0) => wpntr_n_2,
\gic0.gc1.count_d2_reg[4]\(1) => wpntr_n_7,
\gic0.gc1.count_d2_reg[4]\(0) => wpntr_n_8,
p_2_out => p_2_out,
prog_full => prog_full,
wr_clk => wr_clk,
wr_pntr_plus1_pad(4 downto 1) => p_8_out(3 downto 0),
wr_pntr_plus1_pad(0) => \gwas.wsts_n_4\,
wr_rst => wr_rst
);
\gwas.wsts\: entity work.fifo_async_104x32_wr_status_flags_as
port map (
E(0) => \^e\(0),
almost_full => almost_full,
comp2 => comp2,
full => full,
p_2_out => p_2_out,
ram_full_i => ram_full_i,
\rd_pntr_bin_reg[3]\ => wpntr_n_16,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pad(0) => \gwas.wsts_n_4\,
wr_rst => wr_rst
);
wpntr: entity work.fifo_async_104x32_wr_bin_cntr
port map (
E(0) => \^e\(0),
Q(3 downto 0) => p_8_out(3 downto 0),
S(2) => wpntr_n_0,
S(1) => wpntr_n_1,
S(0) => wpntr_n_2,
comp2 => comp2,
\gaf.ram_almost_full_i_reg\ => wpntr_n_16,
\gdiff.diff_pntr_pad_reg[5]\(1) => wpntr_n_7,
\gdiff.diff_pntr_pad_reg[5]\(0) => wpntr_n_8,
p_2_out => p_2_out,
ram_full_i => ram_full_i,
\rd_pntr_bin_reg[4]\(4 downto 0) => \rd_pntr_bin_reg[4]\(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en,
\wr_pntr_gc_reg[4]\(4 downto 0) => Q(4 downto 0),
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
valid : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_async_104x32_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_async_104x32_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_async_104x32_clk_x_pntrs
port map (
D(3) => \gntv_or_sync_fifo.gl0.rd_n_3\,
D(2) => \gntv_or_sync_fifo.gl0.rd_n_4\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
Q(4 downto 0) => p_1_out(4 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
\gdiff.diff_pntr_pad_reg[5]\(4 downto 0) => p_0_out(4 downto 0),
\gic0.gc1.count_d3_reg[4]\(4 downto 0) => p_9_out(4 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
rd_clk => rd_clk,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_async_104x32_rd_logic
port map (
D(3) => \gntv_or_sync_fifo.gl0.rd_n_3\,
D(2) => \gntv_or_sync_fifo.gl0.rd_n_4\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(4 downto 0) => p_1_out(4 downto 0),
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en,
\rd_pntr_gc_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
rd_rst => rd_rst,
valid => valid,
\wr_pntr_bin_reg[4]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_async_104x32_wr_logic
port map (
E(0) => \gntv_or_sync_fifo.gl0.wr_n_3\,
Q(4 downto 0) => p_9_out(4 downto 0),
almost_full => almost_full,
full => full,
prog_full => prog_full,
\rd_pntr_bin_reg[4]\(4 downto 0) => p_0_out(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.mem\: entity work.fifo_async_104x32_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(4 downto 0) => p_9_out(4 downto 0),
din(103 downto 0) => din(103 downto 0),
dout(103 downto 0) => dout(103 downto 0),
\gc0.count_d1_reg[4]\(4 downto 0) => p_20_out(4 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_pntr_plus1_pad(0) => \gntv_or_sync_fifo.gl0.wr_n_3\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_fifo_generator_top is
port (
empty : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
valid : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_fifo_generator_top : entity is "fifo_generator_top";
end fifo_async_104x32_fifo_generator_top;
architecture STRUCTURE of fifo_async_104x32_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_async_104x32_fifo_generator_ramfifo
port map (
almost_full => almost_full,
din(103 downto 0) => din(103 downto 0),
dout(103 downto 0) => dout(103 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_fifo_generator_v12_0_synth is
port (
empty : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
valid : out STD_LOGIC;
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_async_104x32_fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_async_104x32_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_async_104x32_fifo_generator_top
port map (
almost_full => almost_full,
din(103 downto 0) => din(103 downto 0),
dout(103 downto 0) => dout(103 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_async_104x32_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 104;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 104;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_async_104x32_fifo_generator_v12_0 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_async_104x32_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 16;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_async_104x32_fifo_generator_v12_0 : entity is 15;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_async_104x32_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_async_104x32_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_async_104x32_fifo_generator_v12_0 : entity is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_async_104x32_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_async_104x32_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_async_104x32_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_async_104x32_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_104x32_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end fifo_async_104x32_fifo_generator_v12_0;
architecture STRUCTURE of fifo_async_104x32_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_async_104x32_fifo_generator_v12_0_synth
port map (
almost_full => almost_full,
din(103 downto 0) => din(103 downto 0),
dout(103 downto 0) => dout(103 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_104x32 is
port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC;
prog_full : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_async_104x32 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_async_104x32 : entity is "fifo_async_104x32,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_async_104x32 : entity is "fifo_async_104x32,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=104,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=104,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=1,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=16,C_PROG_FULL_THRESH_NEGATE_VAL=15,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_async_104x32 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_async_104x32 : entity is "fifo_generator_v12_0,Vivado 2015.1";
end fifo_async_104x32;
architecture STRUCTURE of fifo_async_104x32 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 104;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 104;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 1;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 16;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 15;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.fifo_async_104x32_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => almost_full,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(103 downto 0) => din(103 downto 0),
dout(103 downto 0) => dout(103 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => prog_full,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0),
rd_en => rd_en,
rd_rst => rd_rst,
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => valid,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(4 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(4 downto 0),
wr_en => wr_en,
wr_rst => wr_rst,
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
gpl-3.0
|
bb8c5904626d3beb8252e01ede4b8e9b
| 0.584241 | 2.75296 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/synth/design_1_ilmb_bram_if_cntlr_0.vhd
| 2 | 13,327 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_ilmb_bram_if_cntlr_0;
ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"20000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_ilmb_bram_if_cntlr_0_arch;
|
gpl-3.0
|
406a47f736d0b8066dbea71bf0d582db
| 0.661514 | 3.148358 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/synth/design_1_microblaze_0_0.vhd
| 2 | 64,536 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:9.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v9_5;
USE microblaze_v9_5.MicroBlaze;
ENTITY design_1_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END design_1_microblaze_0_0;
ARCHITECTURE design_1_microblaze_0_0_arch OF design_1_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_0_arch : ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.5,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=design_1_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x60000000,C_ICACHE_HIGHADDR=0x60ffffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=10,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x60000000,C_DCACHE_HIGHADDR=0x60ffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=10,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTANCE => "design_1_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"00000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"60000000",
C_ICACHE_HIGHADDR => X"60ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 10,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"60000000",
C_DCACHE_HIGHADDR => X"60ffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 10,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
Dbg_Disable => '0',
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END design_1_microblaze_0_0_arch;
|
gpl-3.0
|
b3bb2c91ce415fbd90a3995ae9bad709
| 0.643594 | 2.848517 | false | false | false | false |
hoangt/PoC
|
src/fifo/fifo_cc_got.vhdl
| 2 | 12,879 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Module: FIFO, Common Clock (cc), Pipelined Interface
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- DATA_REG (=true) is a hint, that distributed memory or registers should be
-- used as data storage. The actual memory type depends on the device
-- architecture. See implementation for details.
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.all;
entity fifo_cc_got is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0)
);
end fifo_cc_got;
architecture rtl of fifo_cc_got is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read
if re = '1' then
OP0 <= OP1;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(IP0, OP0, fulli)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
estate_wr <= (others => 'X');
fstate_rd <= (others => 'X');
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
-- Fix assignment to outputs
if ESTATE_WR_BITS > 0 then
-- one's complement is pessimistically low by one but
-- benefits optimization by synthesis
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
end if;
if FSTATE_RD_BITS > 0 then
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
-- Cheapest implementation using a direction flag DF to determine
-- full or empty condition on equal input and output pointers.
-- Both conditions are derived combinationally involving a comparison
-- of the two pointers.
genStateCmb: if not STATE_REG generate
signal DF : std_logic := '0'; -- Direction Flag
signal Peq : std_logic; -- Pointer Comparison
begin
-- Direction Flag remembering the last Operation
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
DF <= '0'; -- get => empty
elsif we /= re then
DF <= we;
end if;
end if;
end process;
-- Fill Conditions
Peq <= '1' when IP0 = OP0 else '0';
fulli <= Peq and DF;
empti <= Peq and not DF;
end generate genStateCmb;
-- Implementation investing another comparator so as to provide both full and
-- empty indications from registers.
genStateReg: if STATE_REG generate
signal Ful : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Avl <= '0';
elsif we /= re then
-- Update Full Indicator
if we = '0' or IP1 /= OP0 then
Ful <= '0';
else
Ful <= '1';
end if;
-- Update Empty Indicator
if re = '0' or OP1 /= IP0 then
Avl <= '1';
else
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end generate genStateReg;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
apache-2.0
|
cfcd23eac38375a1ae9b240ebaa5549b
| 0.532262 | 3.946981 | false | false | false | false |
hoangt/PoC
|
src/mem/lut/lut_Sine.vhdl
| 2 | 6,082 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity lut_Sine is
generic (
REG_OUTPUT : BOOLEAN := TRUE;
MAX_AMPLITUDE : POSITIVE := 255;
POINTS : POSITIVE := 4096;
OFFSET_DEG : REAL := 0.0;
QUARTERS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR(log2ceilnz(POINTS) - 1 downto 0);
Output : out STD_LOGIC_VECTOR(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0)
);
end entity;
architecture rtl of lut_Sine is
signal Output_nxt : STD_LOGIC_VECTOR(Output'range);
begin
-- ===========================================================================
-- 1 Qudrant LUT
-- ===========================================================================
genQ1 : if (QUARTERS = 1) generate
subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (90.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := 0.0;
variable y : REAL;
begin
for i in Result'range loop
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE;
Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- 2 Qudrant LUT
-- ===========================================================================
genQ12 : if (QUARTERS = 2) generate
subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (180.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := 0.0;
variable y : REAL;
begin
for i in Result'range loop
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE;
Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- 3 Qudrant LUT -> ERROR
-- ===========================================================================
genQ13 : if (QUARTERS = 3) generate
assert false report "QUARTERS=3 is not supported." severity FAILURE;
end generate;
-- ===========================================================================
-- 4 Qudrant LUT
-- ===========================================================================
genQ14 : if (QUARTERS = 4) generate
subtype T_RESULT is INTEGER range -MAX_AMPLITUDE to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (360.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := OFFSET_DEG * MATH_DEG_TO_RAD;
variable y : REAL;
begin
for i in Result'range loop
report "x=" & str_format(x, 3) & " y=" & str_format((sin(x) * AMPLITUDE_I), 3) severity note;
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
Output_nxt <= std_logic_vector(to_signed(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- No output registers
-- ===========================================================================
genNoReg : if (REG_OUTPUT = FALSE) generate
begin
Output <= Output_nxt;
end generate;
-- ===========================================================================
-- Output registers
-- ===========================================================================
genReg : if (REG_OUTPUT = TRUE) generate
signal Output_d : STD_LOGIC_VECTOR(Output'range) := (others => '0');
begin
Output_d <= Output_nxt when rising_edge(Clock);
Output <= Output_d;
end generate;
end;
|
apache-2.0
|
1806b3cf04e61611f21b3e6637952745
| 0.522854 | 3.624553 | false | false | false | false |
s-kostyuk/vhdl_samples
|
up_counter2/tc_trig.vhd
| 2 | 428 |
library IEEE;
use ieee.std_logic_1164.all;
entity tc_trig is
port(T: in std_logic;
C: in std_logic;
R: in std_logic;
Q, notQ: out std_logic);
end entity;
architecture tc_trig of tc_trig is
begin
process(C, R) is
variable vQ: std_logic;
begin
if R = '0' then
vQ := '0';
elsif rising_edge(C) then
vQ := not vQ;
end if;
Q <= vQ;
notQ <= not vQ;
end process;
end architecture;
|
mit
|
f24473af18450851f90b922bb69adca9
| 0.598131 | 2.609756 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/srl_fifo.vhd
| 4 | 10,681 |
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
|
gpl-3.0
|
67a99e1874c0aa5946da26d73e5f8f7a
| 0.437693 | 4.347171 | false | false | false | false |
IAIK/ascon_hardware
|
asconv1/top.vhdl
| 1 | 2,525 |
-------------------------------------------------------------------------------
-- Title : Top module that instantiates ascon
-- Project :
-------------------------------------------------------------------------------
-- File : top.vhdl
-- Author : Erich Wenger <[email protected]>
-- Company : Graz University of Technology
-- Created : 2014-03-24
-- Last update: 2014-03-24
-- Platform : ASIC design
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-24 1.0 erichwenger Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
generic (
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic;
WExSI : in std_logic;
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity top;
architecture structural of top is
begin -- architecture structural
ascon_1: entity work.ascon
generic map (
DATA_BUS_WIDTH => DATA_BUS_WIDTH,
ADDR_BUS_WIDTH => ADDR_BUS_WIDTH)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
CSxSI => CSxSI,
WExSI => WExSI,
AddressxDI => AddressxDI,
DataWritexDI => DataWritexDI,
DataReadxDO => DataReadxDO);
end architecture structural;
|
apache-2.0
|
35cedbbf193e81b176779a9f4b3eb230
| 0.529109 | 4.508929 | false | false | false | false |
BogdanArdelean/FPWAM
|
hardware/src/hdl/UnwindTrailUnit.vhd
| 1 | 4,963 |
-------------------------------------------------------------------------------
-- FILE NAME : UnwindTrailUnit.vhd
-- MODULE NAME : UnwindTrailUnit
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that executes the unwind_trail(a1, a2) WAM ancillary
-- operation
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity UnwindTrailUnit is
port
(
clk : in std_logic
; rst : in std_logic
; start_unwind : in std_logic
; a1 : in std_logic_vector(kWamTrailAddressWidth -1 downto 0)
; a2 : in std_logic_vector(kWamTrailAddressWidth -1 downto 0)
; trail_port_1 : in std_logic_vector(kWamAddressWidth -1 downto 0)
; trail_port_1_rd : out std_logic
; trail_addr_1 : out std_logic_vector(kWamTrailAddressWidth -1 downto 0)
; trail_port_2 : in std_logic_vector(kWamAddressWidth -1 downto 0)
; trail_port_2_rd : out std_logic
; trail_addr_2 : out std_logic_vector(kWamTrailAddressWidth -1 downto 0)
; mem_port_1 : out std_logic_vector(kWamWordWidth -1 downto 0)
; mem_port_1_wr : out std_logic
; mem_addr_1 : out std_logic_vector(kWamAddressWidth -1 downto 0)
; mem_port_2 : out std_logic_vector(kWamWordWidth -1 downto 0)
; mem_port_2_wr : out std_logic
; mem_addr_2 : out std_logic_vector(kWamAddressWidth -1 downto 0)
; done : out std_logic
);
end UnwindTrailUnit;
architecture Behavioral of UnwindTrailUnit is
type state_t is (idle_t, first_read_t, read_write_t, done_t);
signal cr_state, nx_state : state_t;
signal counter : unsigned(kWamTrailAddressWidth -1 downto 0);
signal count : std_logic;
signal goal : unsigned(kWamTrailAddressWidth -1 downto 0);
begin
CNTR: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter <= to_unsigned(0, counter'length);
elsif start_unwind = '1' then
counter <= unsigned(a1);
elsif count = '1' then
counter <= counter + 2;
end if;
end if;
end process;
GOALR: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
goal <= to_unsigned(0, goal'length);
elsif start_unwind = '1' then
goal <= unsigned(a2);
end if;
end if;
end process;
FSM: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cr_state <= idle_t;
else
cr_state <= nx_state;
end if;
end if;
end process;
NXSTATE: process(cr_state, start_unwind, counter, goal)
begin
nx_state <= cr_state;
case cr_state is
when idle_t =>
if start_unwind = '1' then
nx_state <= first_read_t;
end if;
when first_read_t =>
nx_state <= read_write_t;
when read_write_t =>
if counter+1 > goal then
nx_state <= done_t;
end if;
when done_t =>
nx_state <= idle_t;
when others =>
nx_state <= idle_t;
end case;
end process;
OUTPUT: process(cr_state, counter, goal, trail_port_1, trail_port_2)
begin
trail_port_1_rd <= '0';
trail_addr_1 <= (others => '0');
trail_port_2_rd <= '0';
trail_addr_2 <= (others => '0');
mem_port_1 <= (others => '0');
mem_port_1_wr <= '0';
mem_addr_1 <= (others => '0');
mem_port_2 <= (others => '0');
mem_port_2_wr <= '0';
mem_addr_2 <= (others => '0');
done <= '0';
count <= '0';
case cr_state is
when idle_t =>
null;
when first_read_t =>
trail_port_1_rd <= to_std_logic(counter < goal);
trail_addr_1 <= std_logic_vector(counter);
trail_port_2_rd <= to_std_logic(counter+1 < goal);
trail_addr_2 <= std_logic_vector(counter+1);
when read_write_t =>
count <= '1';
trail_port_1_rd <= to_std_logic(counter+2 < goal);
trail_addr_1 <= std_logic_vector(counter+2);
trail_port_2_rd <= to_std_logic(counter+3 < goal);
trail_addr_2 <= std_logic_vector(counter+3);
mem_port_1 <= fpwam_word(trail_port_1, tag_ref_t);
mem_port_2 <= fpwam_word(trail_port_2, tag_ref_t);
mem_port_1_wr <= to_std_logic(counter < goal);
mem_port_2_wr <= to_std_logic(counter+1 < goal);
mem_addr_1 <= trail_port_1;
mem_addr_2 <= trail_port_2;
when done_t =>
done <= '1';
when others =>
null;
end case;
end process;
end Behavioral;
|
apache-2.0
|
bdc3a661b55b817c23fcf33f7c2b4e8b
| 0.53778 | 3.448923 | false | false | false | false |
speters/mprfgen
|
test1.vhd
| 1 | 7,350 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 2;
NRP : integer := 3;
AW : integer := 10;
DW : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
component regfile_core
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end component;
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal banksel_v : std_logic_vector(NRP*log2c(NWP)-1 downto 0);
signal ia_sel : banksel_type;
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(0),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0))
);
nwp_nrp_bram_instance_3 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(1),
re => re_v(0),
waddr => waddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(1+1)-1 downto DW*1),
ram_output => ram_output_i(DW*((1*NRP+0)+1)-1 downto DW*(1*NRP+0))
);
nwp_nrp_bram_instance_1 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(1),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+1)+1)-1 downto DW*(0*NRP+1))
);
nwp_nrp_bram_instance_4 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(1),
re => re_v(1),
waddr => waddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
raddr => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
input_data => input_data_v(DW*(1+1)-1 downto DW*1),
ram_output => ram_output_i(DW*((1*NRP+1)+1)-1 downto DW*(1*NRP+1))
);
nwp_nrp_bram_instance_2 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(2),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(2+1)-log2c(NWP)-1 downto AW*2),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+2)+1)-1 downto DW*(0*NRP+2))
);
nwp_nrp_bram_instance_5 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(1),
re => re_v(2),
waddr => waddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
raddr => raddr_v(AW*(2+1)-log2c(NWP)-1 downto AW*2),
input_data => input_data_v(DW*(1+1)-1 downto DW*1),
ram_output => ram_output_i(DW*((1*NRP+2)+1)-1 downto DW*(1*NRP+2))
);
banksel_v(log2c(NWP)*(0+1)-1 downto log2c(NWP)*0) <= raddr_v(AW*(0+1)-1 downto AW*(0+1)-log2c(NWP));
banksel_v(log2c(NWP)*(1+1)-1 downto log2c(NWP)*1) <= raddr_v(AW*(1+1)-1 downto AW*(1+1)-log2c(NWP));
banksel_v(log2c(NWP)*(2+1)-1 downto log2c(NWP)*2) <= raddr_v(AW*(2+1)-1 downto AW*(2+1)-log2c(NWP));
process (ram_output_i, banksel_v)
variable ia_sel_part : integer range 0 to NWP-1;
begin
ia_sel(0) <= banksel_v(log2c(NWP)*(0+1)-1 downto log2c(NWP)*0);
ia_sel_part := conv_integer(ia_sel(0));
case ia_sel_part is
when 0 => ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+0*NRP+1)-1 downto DW*(0+0*NRP));
when 1 => ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1*NRP+1)-1 downto DW*(0+1*NRP));
when others => ram_output_v(DW*(0+1)-1 downto DW*0) <= (others => '0');
end case;
end process;
process (ram_output_i, banksel_v)
variable ia_sel_part : integer range 0 to NWP-1;
begin
ia_sel(1) <= banksel_v(log2c(NWP)*(1+1)-1 downto log2c(NWP)*1);
ia_sel_part := conv_integer(ia_sel(1));
case ia_sel_part is
when 0 => ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+0*NRP+1)-1 downto DW*(1+0*NRP));
when 1 => ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+1*NRP+1)-1 downto DW*(1+1*NRP));
when others => ram_output_v(DW*(1+1)-1 downto DW*1) <= (others => '0');
end case;
end process;
process (ram_output_i, banksel_v)
variable ia_sel_part : integer range 0 to NWP-1;
begin
ia_sel(2) <= banksel_v(log2c(NWP)*(2+1)-1 downto log2c(NWP)*2);
ia_sel_part := conv_integer(ia_sel(2));
case ia_sel_part is
when 0 => ram_output_v(DW*(2+1)-1 downto DW*2) <= ram_output_i(DW*(2+0*NRP+1)-1 downto DW*(2+0*NRP));
when 1 => ram_output_v(DW*(2+1)-1 downto DW*2) <= ram_output_i(DW*(2+1*NRP+1)-1 downto DW*(2+1*NRP));
when others => ram_output_v(DW*(2+1)-1 downto DW*2) <= (others => '0');
end case;
end process;
end rtl;
|
gpl-3.0
|
1d8a90573c26d2a1bfa116c7aad89fb0
| 0.50585 | 2.886881 | false | false | false | false |
hoangt/PoC
|
src/misc/sync/sync_Command.vhdl
| 2 | 5,594 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Steffen Koehler
--
-- Module: Synchronizes a command signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes a vector of bits from clock-domain 'Clock1' to
-- clock-domain 'Clock2'. The clock-domain boundary crossing is done by a
-- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive
-- XOR indicating a value change on the input. This changed signal is used
-- to capture the input for the new output. A busy flag is additionally
-- calculated for the input clock-domain. The output has strobe character
-- and is reset to it's INIT value after one clock cycle.
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrained. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Command IS
generic (
BITS : POSITIVE := 8; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" --
);
PORT (
Clock1 : in STD_LOGIC; -- <Clock> input clock
Clock2 : in STD_LOGIC; -- <Clock> output clock
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input vector
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output vector
Busy : out STD_LOGIC; -- @Clock1: busy bit
Changed : out STD_LOGIC -- @Clock2: changed bit
);
end;
architecture rtl OF sync_Command is
attribute SHREG_EXTRACT : STRING;
constant INIT_I : STD_LOGIC_VECTOR := descend(INIT)(BITS - 1 downto 0);
signal D0 : STD_LOGIC := '0';
signal D1 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I;
signal T2 : STD_LOGIC := '0';
signal D3 : STD_LOGIC := '0';
signal D4 : STD_LOGIC := '0';
signal D5 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I;
signal IsCommand_Clk1 : STD_LOGIC;
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of D0 : signal IS "NO";
attribute SHREG_EXTRACT of T2 : signal IS "NO";
attribute SHREG_EXTRACT of D3 : signal IS "NO";
attribute SHREG_EXTRACT of D4 : signal IS "NO";
attribute SHREG_EXTRACT of D5 : signal IS "NO";
signal syncClk1_In : STD_LOGIC;
signal syncClk1_Out : STD_LOGIC;
signal syncClk2_In : STD_LOGIC;
signal syncClk2_Out : STD_LOGIC;
begin
-- input D-FF @Clock1 -> changed detection
process(Clock1)
begin
if rising_edge(Clock1) then
if (Busy_i = '0') then
D0 <= IsCommand_Clk1; -- delay detected IsCommand signal for rising edge detection; gated by busy flag
D1 <= Input;
T2 <= T2 xor Changed_Clk1; -- toggle T2 if input vector has changed
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
process(Clock2)
begin
if rising_edge(Clock2) then
D3 <= syncClk2_Out;
D4 <= Changed_Clk2;
if (D4 = '1') then
D5 <= INIT_I;
elsif (Changed_Clk2 = '1') then
D5 <= D1;
end if;
end if;
end process;
-- assign syncClk*_In signals
syncClk2_In <= T2;
syncClk1_In <= D3;
IsCommand_Clk1 <= to_sl(Input /= INIT_I); -- input command detection
Changed_Clk1 <= not D0 and IsCommand_Clk1; -- input rising edge detection
Changed_Clk2 <= syncClk2_Out xor D3; -- level change detection; restore strobe signal from flag
Busy_i <= T2 xor syncClk1_Out; -- calculate busy signal
-- output signals
Output <= D5;
Busy <= Busy_i;
Changed <= D4;
syncClk2 : entity PoC.sync_Bits
generic map (
BITS => 1 -- number of bit to be synchronized
)
port map (
Clock => Clock2, -- <Clock> output clock domain
Input(0) => syncClk2_In, -- @async: input bits
Output(0) => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
generic map (
BITS => 1 -- number of bit to be synchronized
)
port map (
Clock => Clock1, -- <Clock> output clock domain
Input(0) => syncClk1_In, -- @async: input bits
Output(0) => syncClk1_Out -- @Clock: output bits
);
end;
|
apache-2.0
|
8799e35a37ba4204d95749d701b10526
| 0.599928 | 3.279015 | false | false | false | false |
lowRISC/greth-library
|
greth_library/commonlib/types_util.vhd
| 2 | 5,019 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
package types_util is
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
bsd-2-clause
|
6926699cc58789033e669c6add6a0693
| 0.579797 | 3.41661 | false | false | false | false |
hoangt/PoC
|
src/misc/sync/sync_Strobe.vhdl
| 2 | 5,000 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Steffen Koehler
--
-- Module: Synchronizes a strobe signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes multiple high-active bits from clock-domain
-- 'Clock1' to clock-domain 'Clock2'. The clock-domain boundary crossing is
-- done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy
-- flag is additionally calculated and can be used to block new inputs. All
-- bits are independent from each other. Multiple consecutive strobes are
-- suppressed by a rising edge detection.
--
-- ATTENTION:
-- Use this synchronizer only for one-cycle high-active signals (strobes).
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrained. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
entity sync_Strobe IS
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
GATED_INPUT_BY_BUSY : BOOLEAN := TRUE -- use gated input (by busy signal)
);
port (
Clock1 : in STD_LOGIC; -- <Clock> input clock domain
Clock2 : in STD_LOGIC; -- <Clock> output clock domain
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input bits
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output bits
Busy : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock1: busy bits
);
end;
architecture rtl of sync_Strobe is
attribute SHREG_EXTRACT : STRING;
signal syncClk1_In : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk1_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk2_In : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk2_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0);
BEGIN
gen : for i in 0 to BITS - 1 generate
signal D0 : STD_LOGIC := '0';
signal T1 : STD_LOGIC := '0';
signal D2 : STD_LOGIC := '0';
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT OF D0 : signal is "NO";
attribute SHREG_EXTRACT OF T1 : signal is "NO";
attribute SHREG_EXTRACT OF D2 : signal is "NO";
begin
process(Clock1)
begin
if rising_edge(Clock1) then
-- input delay for rising edge detection
D0 <= Input(I);
-- T-FF to converts a strobe to a flag signal
if (GATED_INPUT_BY_BUSY = TRUE) then
T1 <= (Changed_Clk1 and not Busy_i) xor T1;
else
T1 <= Changed_Clk1 xor T1;
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
D2 <= syncClk2_Out(I) when rising_edge(Clock2);
-- assign syncClk*_In signals
syncClk2_In(I) <= T1;
syncClk1_In(I) <= syncClk2_Out(I); -- D2
Changed_Clk1 <= not D0 and Input(I); -- rising edge detection
Changed_Clk2 <= syncClk2_Out(I) xor D2; -- level change detection; restore strobe signal from flag
Busy_i <= T1 xor syncClk1_Out(I); -- calculate busy signal
-- output signals
Output(I) <= Changed_Clk2;
Busy(I) <= Busy_i;
end generate;
syncClk2 : entity PoC.sync_Bits
generic map (
BITS => BITS -- number of bit to be synchronized
)
port map (
Clock => Clock2, -- <Clock> output clock domain
Input => syncClk2_In, -- @async: input bits
Output => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
generic map (
BITS => BITS -- number of bit to be synchronized
)
port map (
Clock => Clock1, -- <Clock> output clock domain
Input => syncClk1_In, -- @async: input bits
Output => syncClk1_Out -- @Clock: output bits
);
end;
|
apache-2.0
|
249cee6694bc95543bc35af93e390545
| 0.6142 | 3.342246 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/top.vhd
| 1 | 2,248 |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity top is
generic (
G_W : integer := 32;
G_SW : integer := 32;
G_ASYNC_RSTN : boolean := False;
G_ENABLE_PAD : boolean := True;
G_CIPH_EXP : boolean := False;
G_REVERSE_CIPH : boolean := False;
G_MERGE_TAG : boolean := False;
G_ABLK_SIZE : integer := 64; -- change this when changing Ascon version
G_DBLK_SIZE : integer := 64;
G_KEY_SIZE : integer := 32;
G_TAG_SIZE : integer := 128;
G_PAD_STYLE : integer := 1;
G_PAD_AD : integer := 3;
G_PAD_D : integer := 4);
port (
clk : in std_logic;
rst : in std_logic;
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic);
end entity top;
architecture structural of top is
begin -- architecture structural
AEAD_1: entity work.AEAD
generic map (
G_W => G_W,
G_SW => G_SW,
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_ENABLE_PAD => G_ENABLE_PAD,
G_CIPH_EXP => G_CIPH_EXP,
G_REVERSE_CIPH => G_REVERSE_CIPH,
G_MERGE_TAG => G_MERGE_TAG,
G_ABLK_SIZE => G_ABLK_SIZE,
G_DBLK_SIZE => G_DBLK_SIZE,
G_KEY_SIZE => G_KEY_SIZE,
G_TAG_SIZE => G_TAG_SIZE,
G_PAD_STYLE => G_PAD_STYLE,
G_PAD_AD => G_PAD_AD,
G_PAD_D => G_PAD_D)
port map (
clk => clk,
rst => rst,
pdi_data => pdi_data,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi_data => sdi_data,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do_data => do_data,
do_ready => do_ready,
do_valid => do_valid);
end architecture structural;
|
apache-2.0
|
d96c78285a3230de29b14da3c5217142
| 0.523132 | 3.066849 | false | false | false | false |
speters/mprfgen
|
regfile_core.vhd
| 1 | 3,226 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity regfile_core is
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end regfile_core;
architecture write_first of regfile_core is
type mem_type is array ((2**AW-1) downto 0) of std_logic_vector(DW-1 downto 0);
signal ram_name : mem_type := (others => (others => '0'));
begin
process (clock)
begin
if (clock'EVENT and clock = '1') then
if (enable = '1') then
if (we = '1') then
ram_name(conv_integer(waddr)) <= input_data;
end if;
end if;
end if;
end process;
process (clock)
begin
if (clock'EVENT and clock = '1') then
if (enable = '1') then
ram_output <= ram_name(conv_integer(raddr));
end if;
end if;
end process;
end write_first;
architecture read_async of regfile_core is
type mem_type is array ((2**AW-1) downto 0) of std_logic_vector(DW-1 downto 0);
signal ram_name : mem_type := (others => (others => '0'));
begin
process (clock)
begin
if (clock'EVENT and clock = '1') then
if (enable = '1') then
if (we = '1') then
ram_name(conv_integer(waddr)) <= input_data;
end if;
end if;
end if;
end process;
ram_output <= ram_name(conv_integer(raddr));
end read_async;
architecture read_first of regfile_core is
type mem_type is array ((2**AW-1) downto 0) of std_logic_vector(DW-1 downto 0);
shared variable ram_name : mem_type := (others => (others => '0'));
signal ram_output_b : std_logic_vector(DW-1 downto 0);
signal we_a : std_logic;
begin
process (clock)
begin
if (clock'EVENT and clock = '1') then
if (enable = '1') then
ram_output <= ram_name(conv_integer(raddr));
if (reset = '1') then
ram_name(conv_integer(raddr)) := input_data;
end if;
end if;
end if;
end process;
process (clock)
begin
if (clock'EVENT and clock = '1') then
if (enable = '1') then
if (we = '1') then
ram_name(conv_integer(waddr)) := input_data;
end if;
ram_output_b <= ram_name(conv_integer(waddr));
end if;
end if;
end process;
end read_first;
architecture read_through of regfile_core is
type mem_type is array ((2**AW-1) downto 0) of std_logic_vector(DW-1 downto 0);
signal ram_name : mem_type := (others => (others => '0'));
signal read_raddr : std_logic_vector(AW-1 downto 0);
begin
process (clock)
begin
if (clock'EVENT and clock = '1') then
if (enable = '1') then
if (we = '1') then
ram_name(conv_integer(waddr)) <= input_data;
end if;
read_raddr <= raddr;
end if;
end if;
end process;
ram_output <= ram_name(conv_integer(read_raddr));
end read_through;
|
gpl-3.0
|
5d79ac897d3bf57fd584c0d79570503e
| 0.584625 | 3.216351 | false | false | false | false |
hoangt/PoC
|
src/arith/arith_shifter_barrel.vhdl
| 2 | 3,650 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Universal Barrel-Shifter
--
-- Description:
-- ------------------------------------
-- This Barrel-Shifter supports:
-- - shifting and rotating
-- - right and left operations
-- - arithmetic and logic mode (only valid for shift operations)
-- This is equivalent to the CPU instructions: SLL, SLA, SRL, SRA, RL, RR
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity arith_shifter_barrel is
generic (
BITS : POSITIVE := 32
);
port (
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
ShiftAmount : in STD_LOGIC_VECTOR(log2ceilnz(BITS) - 1 downto 0);
ShiftRotate : in STD_LOGIC;
LeftRight : in STD_LOGIC;
ArithmeticLogic : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end;
architecture rtl of arith_shifter_barrel is
constant STAGES : POSITIVE := log2ceilnz(BITS);
subtype T_INTERMEDIATE_RESULT is STD_LOGIC_VECTOR(BITS - 1 downto 0);
type T_INTERMEDIATE_VECTOR is array (NATURAL range <>) of T_INTERMEDIATE_RESULT;
signal IntermediateResults : T_INTERMEDIATE_VECTOR(STAGES downto 0);
begin
IntermediateResults(0) <= Input;
Output <= IntermediateResults(STAGES);
genStage : for i in 0 to STAGES - 1 generate
process(IntermediateResults(i), ShiftRotate, LeftRight, ArithmeticLogic)
begin
if (ShiftAmount(i) = '0') then
IntermediateResults(i + 1) <= IntermediateResults(i); -- NOP
else
if (ShiftRotate = '0') then
if (LeftRight = '0') then
IntermediateResults(i + 1) <= IntermediateResults(i)((BITS - 2**i - 1) downto 0) & ((2**i - 1) downto 0 => '0'); -- SLA, SLL
else
if (ArithmeticLogic = '0') then
IntermediateResults(i + 1) <= ((2**i - 1) downto 0 => IntermediateResults(i)(BITS - 1)) & IntermediateResults(i)(BITS - 1 downto 2**i); -- SRA
else
IntermediateResults(i + 1) <= ((2**i - 1) downto 0 => '0') & IntermediateResults(i)(BITS - 1 downto 2**i); -- SRL
end if;
end if;
else
if (LeftRight = '0') then
IntermediateResults(i + 1) <= IntermediateResults(i)((BITS - 2**i - 1) downto 0) & IntermediateResults(i)(BITS - 1 downto (BITS - 2**i)); -- RL
else
IntermediateResults(i + 1) <= IntermediateResults(i)((2**i - 1) downto 0) & IntermediateResults(i)(BITS - 1 downto 2**i); -- RR
end if;
end if;
end if;
end process;
end generate;
end;
|
apache-2.0
|
c7504cb5000a01affe0c82ee3305797e
| 0.600548 | 3.621032 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm.vhd
| 4 | 178,472 |
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library mdm_v3_2;
use mdm_v3_2.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"0000_0000";
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
architecture IMP of MDM is
function int2std (val : integer) return std_logic is
begin -- function int2std
if (val = 0) then
return '0';
else
return '1';
end if;
end function int2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
(31 downto 5 => '0', 4 => int2std(C_DBG_REG_ACCESS), 3 downto 0 => '1');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
-- Registers Base Address (not used)
ZEROES & C_BASEADDR,
ZEROES & (C_BASEADDR or C_S_AXI_MIN_SIZE)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE-1);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector(((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 generate
begin
BSCANE2_I : BSCANE2
generic map (
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
BUFG_DRCK : BUFG
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFGCTRL_DRCK : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
BUFG_UPDATE : BUFG
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
BUFGCTRL_UPDATE : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 generate
begin
BUFG_DRCK : BUFG
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_BASEADDR => C_BASEADDR, -- [std_logic_vector(0 to 31)]
C_HIGHADDR => C_HIGHADDR, -- [std_logic_vector(0 to 31)]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE-1 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
gpl-3.0
|
a04a8122e689f3e4faab0a4e48bad912
| 0.521522 | 2.91826 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl_hs/wrappers/CipherCore_Wrapper.vhd
| 1 | 5,027 |
-------------------------------------------------------------------------------
--! @file CipherCore_Wrapper.vhd
--! @brief 5-bit Wrapper for CipherCore
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use work.AEAD_pkg.all;
entity CipherCore_Wrapper is
generic (
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128 --! Tag
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! SERDES signals
sin : in std_logic;
ssel : in std_logic;
sout : out std_logic
);
end entity CipherCore_Wrapper;
architecture structure of CipherCore_Wrapper is
constant LBS_BYTES : integer := log2_ceil(G_DBLK_SIZE/8);
signal sipo : std_logic_vector(G_KEY_SIZE+G_DBLK_SIZE+G_DBLK_SIZE/4+LBS_BYTES+12 downto 0);
signal piso : std_logic_vector(G_DBLK_SIZE+LBS_BYTES+6 -1 downto 0);
signal piso_data : std_logic_vector(G_DBLK_SIZE+LBS_BYTES+6 -1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
sipo <= sin & sipo(sipo'high downto 1);
if (ssel = '1') then
piso <= piso_data;
else
piso <= '0' & piso(piso'high downto 1);
end if;
end if;
end process;
sout <= piso(0);
u_ciphercore:
entity work.CipherCore(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_LBS_BYTES => LBS_BYTES
)
port map (
clk => clk,
rst => rst,
--! Input
key => sipo(G_KEY_SIZE -1 downto 0 ),
bdi => sipo(G_KEY_SIZE+G_DBLK_SIZE -1 downto G_KEY_SIZE ),
key_valid => sipo(G_KEY_SIZE+G_DBLK_SIZE+1 -1),
key_update => sipo(G_KEY_SIZE+G_DBLK_SIZE+2 -1),
decrypt => sipo(G_KEY_SIZE+G_DBLK_SIZE+3 -1),
bdo_ready => sipo(G_KEY_SIZE+G_DBLK_SIZE+4 -1),
bdi_valid => sipo(G_KEY_SIZE+G_DBLK_SIZE+5 -1),
bdi_type => sipo(G_KEY_SIZE+G_DBLK_SIZE+8 -1 downto G_KEY_SIZE+G_DBLK_SIZE+5),
bdi_eot => sipo(G_KEY_SIZE+G_DBLK_SIZE+9 -1),
bdi_eoi => sipo(G_KEY_SIZE+G_DBLK_SIZE+10 -1),
bdi_valid_bytes => sipo(G_KEY_SIZE+G_DBLK_SIZE+10+G_DBLK_SIZE/8 -1 downto G_KEY_SIZE+G_DBLK_SIZE+10),
bdi_pad_loc => sipo(G_KEY_SIZE+G_DBLK_SIZE+10+G_DBLK_SIZE/4 -1 downto G_KEY_SIZE+G_DBLK_SIZE+10+G_DBLK_SIZE/8),
bdi_size => sipo(G_KEY_SIZE+G_DBLK_SIZE+10+G_DBLK_SIZE/4+LBS_BYTES+1 -1 downto G_KEY_SIZE+G_DBLK_SIZE+10+G_DBLK_SIZE/4),
bdi_partial => sipo(G_KEY_SIZE+G_DBLK_SIZE+10+G_DBLK_SIZE/4+LBS_BYTES+2 -1),
--! Output
bdo => piso_data(G_DBLK_SIZE -1 downto 0),
key_ready => piso_data(G_DBLK_SIZE+1 -1),
bdi_ready => piso_data(G_DBLK_SIZE+2 -1),
bdo_valid => piso_data(G_DBLK_SIZE+3 -1),
msg_auth_done => piso_data(G_DBLK_SIZE+4 -1),
msg_auth_valid => piso_data(G_DBLK_SIZE+5 -1),
bdo_size => piso_data(G_DBLK_SIZE+5+LBS_BYTES+1 -1 downto G_DBLK_SIZE+5)
);
end structure;
|
apache-2.0
|
e92c68c3640089c6ac4a8a886db7b8e7
| 0.453134 | 3.824201 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/AEAD_Arch.vhd
| 1 | 8,798 |
-------------------------------------------------------------------------------
--! @file AEAD_Arch.vhd
--! @brief Architecture of authenticated encryption unit.
--! Note: This file should not be modified by a user.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
-------------------------------------------------------------------------------
--! @brief Architecture definition of AEAD
-------------------------------------------------------------------------------
architecture structure of AEAD is
constant LBS_BYTES : integer := log2_ceil(G_DBLK_SIZE/8);
--! Signals from input processor
signal key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal bdi : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal key_valid : std_logic;
signal key_ready : std_logic;
signal key_update : std_logic;
signal decrypt : std_logic;
signal bdi_valid : std_logic;
signal bdi_ready : std_logic;
signal bdi_partial : std_logic;
signal bdi_eot : std_logic;
signal bdi_eoi : std_logic;
signal bdi_type : std_logic_vector(3 -1 downto 0);
signal bdi_size : std_logic_vector(LBS_BYTES+1 -1 downto 0);
signal bdi_valid_bytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal bdi_pad_loc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! Signals to output processor
signal bdo_ready : std_logic;
signal bdo_valid : std_logic;
signal bdo : std_logic_vector(G_DBLK_SIZE -1 downto 0);
signal bdo_size : std_logic_vector(LBS_BYTES+1 -1 downto 0);
signal msg_auth_done : std_logic;
signal msg_auth_valid : std_logic;
--! FIFO
signal cmd_din : std_logic_vector(24 -1 downto 0);
signal cmd_dout : std_logic_vector(24 -1 downto 0);
signal cmd_rd_ready : std_logic;
signal cmd_wr_ready : std_logic;
signal cmd_wr_valid : std_logic;
signal cmd_rd_valid : std_logic;
begin
u_input:
entity work.PreProcessor(structure)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_ENABLE_PAD => G_ENABLE_PAD ,
G_CIPH_EXP => G_CIPH_EXP ,
G_REVERSE_CIPH => G_REVERSE_CIPH ,
G_MERGE_TAG => G_MERGE_TAG ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_LBS_BYTES => LBS_BYTES ,
G_PAD_STYLE => G_PAD_STYLE ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! External
pdi_data => pdi_data ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi_data => sdi_data ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
--! CipherCore (Data)
bdi => bdi ,
key => key ,
--! CipherCore (Control)
key_valid => key_valid ,
key_ready => key_ready ,
key_update => key_update ,
decrypt => decrypt ,
bdi_ready => bdi_ready ,
bdi_valid => bdi_valid ,
bdi_type => bdi_type ,
bdi_partial => bdi_partial ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! cmd FIFO
cmd => cmd_din ,
cmd_ready => cmd_wr_ready ,
cmd_valid => cmd_wr_valid
);
u_cc:
entity work.CipherCore(structure)
generic map (
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_LBS_BYTES => LBS_BYTES ,
G_MAX_LEN => G_MAX_LEN
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! PreProcessor (data)
key => key ,
bdi => bdi ,
--! PreProcessor (controls)
key_valid => key_valid ,
key_ready => key_ready ,
key_update => key_update ,
decrypt => decrypt ,
bdi_ready => bdi_ready ,
bdi_valid => bdi_valid ,
bdi_type => bdi_type ,
bdi_partial => bdi_partial ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_size => bdi_size ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! PostProcessor
bdo => bdo ,
bdo_ready => bdo_ready ,
bdo_valid => bdo_valid ,
bdo_size => bdo_size ,
msg_auth_valid => msg_auth_valid ,
msg_auth_done => msg_auth_done
);
u_output:
entity work.PostProcessor(structure)
generic map (
G_W => G_W ,
G_ASYNC_RSTN => G_ASYNC_RSTN ,
G_CIPH_EXP => G_CIPH_EXP ,
G_REVERSE_CIPH => G_REVERSE_CIPH ,
G_MERGE_TAG => G_MERGE_TAG ,
G_LBS_BYTES => LBS_BYTES ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! Global
clk => clk ,
rst => rst ,
--! External
do_data => do_data ,
do_ready => do_ready ,
do_valid => do_valid ,
--! CipherCore
bdo_ready => bdo_ready ,
bdo_valid => bdo_valid ,
bdo => bdo ,
bdo_size => bdo_size ,
msg_auth_valid => msg_auth_valid ,
msg_auth_done => msg_auth_done ,
--! cmd FIFOs
cmd => cmd_dout ,
cmd_ready => cmd_rd_ready ,
cmd_valid => cmd_rd_valid
);
u_hdr_buffer:
entity work.fwft_fifo(structure)
generic map (
G_W => 24 ,
G_LOG2DEPTH => 2 ,
G_ASYNC_RSTN => G_ASYNC_RSTN
)
port map (
clk => clk ,
rst => rst ,
din => cmd_din ,
din_valid => cmd_wr_valid ,
din_ready => cmd_wr_ready ,
dout => cmd_dout ,
dout_valid => cmd_rd_valid ,
dout_ready => cmd_rd_ready
);
end structure;
|
apache-2.0
|
0b47eecb20ddcf397bf025d2e4dcf6c0
| 0.390859 | 4.29702 | false | false | false | false |
hoangt/PoC
|
src/fifo/fifo.pkg.vhdl
| 2 | 9,491 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.fifo namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use PoC.utils.all;
package fifo is
-- Minimal FIFO with single clock to decouple enable domains.
component fifo_glue
generic (
D_BITS : positive -- Data Width
);
port (
-- Control
clk : in std_logic; -- Clock
rst : in std_logic; -- Synchronous Reset
-- Input
put : in std_logic; -- Put Value
di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input
ful : out std_logic; -- Full
-- Output
vld : out std_logic; -- Data Available
do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output
got : in std_logic -- Data Consumed
);
end component;
-- Minimal Local-Link-FIFO with single clock and first-word-fall-through mode.
component fifo_ll_glue
generic (
D_BITS : positive;
FRAME_USER_BITS : natural;
REGISTER_PATH : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
-- in port
sof_in : in std_logic;
data_in : in std_logic_vector(D_BITS downto 1);
frame_data_in : in std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_in : in std_logic;
src_rdy_in : in std_logic;
dst_rdy_in : out std_logic;
-- out port
sof_out : out std_logic;
data_out : out std_logic_vector(D_BITS downto 1);
frame_data_out : out std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_out : out std_logic;
src_rdy_out : out std_logic;
dst_rdy_out : in std_logic
);
end component;
-- Simple FIFO backed by a shift register.
component fifo_shift
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end component;
-- Full-fledged FIFO with single clock domain using on-chip RAM.
component fifo_cc_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_dc_got_sm
generic (
D_BITS : positive;
MIN_DEPTH : positive);
port (
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0));
end component;
component fifo_ic_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Write Interface
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS - 1, 0) downto 0);
-- Read Interface
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0);
fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS - 1, 0) downto 0)
);
end component;
component fifo_cc_got_tempput
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic;
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end component;
end package;
|
apache-2.0
|
67bda06307661dfdd51767a1aeebca5c
| 0.529344 | 3.944722 | false | false | false | false |
lowRISC/greth-library
|
greth_library/techmap/mem/sram8_inferred_init.vhd
| 2 | 2,273 |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
--! @details This module absolutely similar to the 'inferred' implementation
--! but it support initialization of the SRAM.
--! This feature is very useful during RTL simulation so that
--! current FW supports skipping of the copying FwImage state.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity sram8_inferred_init is
generic (
abits : integer := 12;
byte_idx : integer := 0;
init_file : string
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred_init of sram8_inferred_init is
constant FILE_IMAGE_LINES_TOTAL : integer := 16384;
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
impure function init_ram(file_name : in string) return ram_type is
file ram_file : text open read_mode is file_name;
variable ram_line : line;
variable temp_bv : std_logic_vector(127 downto 0);
variable temp_mem : ram_type;
begin
for i in 0 to (FILE_IMAGE_LINES_TOTAL-1) loop
readline(ram_file, ram_line);
hread(ram_line, temp_bv);
temp_mem(i) := temp_bv((byte_idx+1)*8-1 downto 8*byte_idx);
end loop;
return temp_mem;
end function;
--! @warning SIMULATION INITIALIZATION
signal ram : ram_type := init_ram(init_file);
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
|
bsd-2-clause
|
279ffeb9c2f9bb4560fced9d309bb7a0
| 0.613286 | 3.666129 | false | false | false | false |
hoangt/PoC
|
src/mem/ocram/ocram.pkg.vhdl
| 2 | 5,577 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.mem.ocram namespace
--
-- Description:
-- ------------------------------------
-- On-Chip RAMs and ROMs for FPGAs.
--
-- A detailed documentation is included in each module.
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package ocram is
-- RAMs (RWMs)
-- ===========================================================================
-- Single-Port
component ocram_sp
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
-- Simple-Dual-Port
component ocram_sdp
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
rclk : in std_logic;
rce : in std_logic;
wclk : in std_logic;
wce : in std_logic;
we : in std_logic;
ra : in unsigned(A_BITS-1 downto 0);
wa : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
-- Enhanced-Simple-Dual-Port
component ocram_esdp
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0));
end component;
-- True-Dual-Port
component ocram_tdp
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
we2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
d2 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0));
end component;
-- ROMs
-- ===========================================================================
-- Single-Port
component ocrom_sp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
-- Dual-Port
component ocrom_dp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
-- Wishbone Adapter
-- ===========================================================================
component ocram_wb
generic (
A_BITS : positive;
D_BITS : positive;
PIPE_STAGES : integer range 1 to 2);
port (
clk : in std_logic;
rst : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_cti_i : in std_logic_vector(2 downto 0);
wb_bte_i : in std_logic_vector(1 downto 0);
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(A_BITS-1 downto 0);
wb_dat_i : in std_logic_vector(D_BITS-1 downto 0);
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(D_BITS-1 downto 0);
ram_ce : out std_logic;
ram_we : out std_logic;
ram_a : out unsigned(A_BITS-1 downto 0);
ram_d : out std_logic_vector(D_BITS-1 downto 0);
ram_q : in std_logic_vector(D_BITS-1 downto 0));
end component;
end package;
|
apache-2.0
|
448f78b682e5f617a23fdb27d92eb073
| 0.535413 | 3.201493 | false | false | false | false |
lowRISC/greth-library
|
greth_library/work/rocket_soc_nexys4.vhd
| 1 | 7,480 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! GLIP interface inputs
i_glip : in std_logic_vector(31 downto 0);
--! GLIP interface outputs
o_glip : out std_logic_vector(31 downto 0);
--! Ethernet MAC PHY interface signals
o_erefclk : out std_ulogic; -- RMII clock out
i_gmiiclk_p : in std_ulogic; -- GMII clock in
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
wPllLocked : in std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
i_clk50_quad : in std_ulogic;
i_clk50 : in std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
diffclk: if CFG_RMII = 0 generate
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
end generate;
wClkBus <= i_clk50;
o_erefclk <= i_clk50_quad;
eth_i.rmii_clk <= i_clk50;
wSysReset <= i_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_glip => i_glip,
o_glip => o_glip
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth0_rmii_ena1 : if CFG_RMII = 1 generate
eth_i.rx_crs <= i_erx_dv;
end generate;
eth0_rmii_ena0 : if CFG_RMII = 0 generate -- plain MII
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_crs <= i_erx_crs;
end generate;
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rxd <= i_erxd;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 50, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518,
rmii => CFG_RMII
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
end arch_rocket_soc;
|
bsd-2-clause
|
40c8b6f867fed5c686521aaabdb09300
| 0.604144 | 3.462963 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/synth/design_1_ilmb_v10_0.vhd
| 2 | 9,041 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0;
USE lmb_v10_v3_0.lmb_v10;
ENTITY design_1_ilmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END design_1_ilmb_v10_0;
ARCHITECTURE design_1_ilmb_v10_0_arch OF design_1_ilmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_v10_0_arch : ARCHITECTURE IS "design_1_ilmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "design_1_ilmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END design_1_ilmb_v10_0_arch;
|
gpl-3.0
|
65959e6c0de3d7a0ba023101bc679190
| 0.694392 | 3.303252 | false | true | false | false |
BogdanArdelean/FPWAM
|
hardware/src/hdl/BinarySearch.vhd
| 1 | 6,223 |
-------------------------------------------------------------------------------
-- FILE NAME : BinarySearch.vhd
-- MODULE NAME : BinarySearch
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-03 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Module used for searching predicate and first argument
-- label
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BinarySearch is
generic
(
kWordWidth : natural := 16;
kMemAddressWidth : natural := 16
);
port
(
-- Common
clk : in std_logic;
rst : in std_logic;
-- Search interface
search_word : in std_logic_vector(kWordWidth - 1 downto 0);
low_address : in std_logic_vector(kMemAddressWidth - 1 downto 0);
high_address : in std_logic_vector(kMemAddressWidth - 1 downto 0);
start_search : in std_logic;
done : out std_logic;
found : out std_logic;
-- Memory interface
memory_in : in std_logic_vector(kWordWidth - 1 downto 0);
memory_address_out : out std_logic_vector(kMemAddressWidth - 1 downto 0);
memory_read : out std_logic
);
end BinarySearch;
architecture Behavioral of BinarySearch is
-- FSM
type state_t is (idle_t, decision_t, wait_mem_t, done_t);
signal cr_state, nx_state : state_t;
-- Registers
signal low_addr_reg : std_logic_vector(kMemAddressWidth - 1 downto 0);
signal high_addr_reg : std_logic_vector(kMemAddressWidth - 1 downto 0);
signal search_word_reg : std_logic_vector(kWordWidth - 1 downto 0);
signal mem_word : std_logic_vector(kWordWidth - 1 downto 0);
-- Control signals
signal wr_low : std_logic;
signal wr_high : std_logic;
signal wr_search_word : std_logic;
signal wr_mem_word : std_logic;
signal left_greater : std_logic;
-- Combinatorial
signal low_addr_comb : std_logic_vector(kMemAddressWidth - 1 downto 0);
signal high_addr_comb : std_logic_vector(kMemAddressWidth - 1 downto 0);
begin
LOWADDRREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
low_addr_reg <= (others => '0');
elsif wr_low = '1' then
low_addr_reg <= low_addr_comb;
end if;
end if;
end process LOWADDRREG;
HIGHADDRREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
high_addr_reg <= (others => '0');
elsif wr_high = '1' then
high_addr_reg <= high_addr_comb;
end if;
end if;
end process HIGHADDRREG;
SEARCHWORDREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
search_word_reg <= (others => '0');
elsif wr_search_word = '1' then
search_word_reg <= search_word;
end if;
end if;
end process SEARCHWORDREG;
MEMWORDREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mem_word <= (others => '0');
elsif wr_mem_word = '1' then
mem_word <= memory_in;
end if;
end if;
end process MEMWORDREG;
FSM: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cr_state <= idle_t;
else
cr_state <= nx_state;
end if;
end if;
end process FSM;
NEXT_STATE_DECODE: process(cr_state, start_search, memory_in, mem_word, search_word_reg, low_addr_reg, high_addr_Reg)
begin
nx_state <= cr_state;
case(cr_state) is
when idle_t =>
if start_search = '1' then
nx_state <= wait_mem_t;
else
nx_state <= idle_t;
end if;
when wait_mem_t =>
nx_state <= decision_t;
when decision_t =>
if mem_word = search_word_reg or low_addr_reg >= high_addr_reg then
nx_state <= done_t;
else
nx_state <= wait_mem_t;
end if;
when done_t =>
nx_state <= idle_t;
when others =>
nx_state <= idle_t;
end case;
end process NEXT_STATE_DECODE;
CONTROL_AND_OUTPUT: process(cr_state, start_search, low_addr_reg, high_addr_reg, low_address, high_address, search_word_reg, mem_word)
begin
wr_low <= '0';
wr_high <= '0';
wr_search_word <= '0';
wr_mem_word <= '0';
memory_read <= '0';
done <= '0';
found <= '0';
low_addr_comb <= (others => '0');
high_addr_comb <= (others => '0');
memory_address_out <= std_logic_vector((unsigned(low_addr_reg) + unsigned(high_addr_reg)) / 2);
case(cr_state) is
when idle_t =>
if start_search = '1' then
wr_low <= '1';
wr_high <= '1';
wr_search_word <= '1';
low_addr_comb <= low_address;
high_addr_comb <= high_address;
end if;
when wait_mem_t =>
memory_read <= '1';
when decision_t =>
wr_low <= '1';
wr_high <= '1';
if search_word_reg < mem_word then
low_addr_comb <= low_addr_reg;
high_addr_comb <= std_logic_vector((unsigned(low_addr_reg) + unsigned(high_addr_reg)) / 2 - 1);
else
high_addr_comb <= high_addr_reg;
low_addr_comb <= std_logic_vector((unsigned(low_addr_reg) + unsigned(high_addr_reg)) / 2 + 1);
end if;
when done_t =>
if mem_word = search_word_reg then
found <= '1';
else
found <= '0';
end if;
done <= '1';
when others =>
null;
end case;
end process CONTROL_AND_OUTPUT;
end Behavioral;
|
apache-2.0
|
ba4922833d9893c3aeb93c6fa9ec1b91
| 0.506187 | 3.808446 | false | false | false | false |
s-kostyuk/vhdl_samples
|
up_counter1/cnt.vhd
| 1 | 835 |
library IEEE;
use ieee.std_logic_1164.all;
entity cnt is
port(
rst: in std_logic;
T: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end entity;
architecture cnt of cnt is
component tc_trig is
port(T: in std_logic;
C: in std_logic;
R: in std_logic;
Q, notQ: out std_logic);
end component;
signal sQ: std_logic_vector(3 downto 0);
signal not_sQ: std_logic_vector(3 downto 0);
begin
tr0: tc_trig port map(C => T, T => '1', Q => sQ(0), notQ => not_sQ(0), R => rst);
tr1: tc_trig port map(C => not_sQ(0), T => '1', Q => sQ(1), notQ => not_sQ(1), R => rst);
tr2: tc_trig port map(C => not_sQ(1), T => '1', Q => sQ(2), notQ => not_sQ(2), R => rst);
tr3: tc_trig port map(C => not_sQ(2), T => '1', Q => sQ(3), notQ => not_sQ(3), R => rst);
Q <= sQ;
end architecture;
|
mit
|
43c8b8c4e2bccb4105dbd37bfceffcf6
| 0.555689 | 2.485119 | false | false | false | false |
lowRISC/greth-library
|
greth_library/rocketlib/types_rocket.vhd
| 1 | 24,731 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief System Top level modules and interconnect declarations.
-----------------------------------------------------------------------------
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
--! @brief Declaration of components visible on SoC top level.
package types_rocket is
--! @name Scala inherited constants.
--! @brief The following constants were define in Rocket-chip generator.
--! @{
--! @brief Bits allocated for the memory tag value.
--! @details This value is defined \i Config.scala and depends of others
--! configuration paramters, like number of master, clients, channels
--! and so on. It is not used in VHDL implemenation.
constant MEM_TAG_BITS : integer := 6;
--! @brief SCALA generated value. Not used in VHDL.
constant MEM_ADDR_BITS : integer := 26;
--! @brief Multiplexing HTIF bus data width.
--! @details Not used in a case of disabled L2 cache.
--! If L2 cached is enabled this value defines bitwise of the bus
--! between \i Uncore module and external transievers.
--! Standard message size for the HTID request is 128 bits, so this
--! value defines number of beats required to transmit/recieve such
--! message.
constant HTIF_WIDTH : integer := 16;
--! @}
--! @name HostIO modules unique IDs.
--! @{
--! Interrupt controller
constant CFG_HTIF_SRC_IRQCTRL : integer := 0;
--! Debug Support Unit (DSU)
constant CFG_HTIF_SRC_DSU : integer := CFG_HTIF_SRC_IRQCTRL + 1;
--! Total number of HostIO initiators.
constant CFG_HTIF_SRC_TOTAL : integer := CFG_HTIF_SRC_DSU + 1;
--! @}
--! @name Memory Transaction types.
--! @details TileLinkIO interface uses these constant to identify the payload
--! size of the transaction.
--! @{
constant MT_B : integer := 0; --! int8_t Memory Transaction.
constant MT_H : integer := 1; --! int16_t Memory Transaction.
constant MT_W : integer := 2; --! int32_t Memory Transaction.
constant MT_D : integer := 3; --! int64_t Memory Transaction.
constant MT_BU : integer := 4; --! uint8_t Memory Transaction.
constant MT_HU : integer := 5; --! uint16_t Memory Transaction.
constant MT_WU : integer := 6; --! uint32_t Memory Transaction.
constant MT_Q : integer := 7; --! AXI data-width Memory Transaction (default 128-bits).
--! @}
--! @brief Memory operation types
--! @details The union bits [5:1] contains information about current transaction
constant M_XRD : std_logic_vector(4 downto 0) := "00000"; --! int load
constant M_XWR : std_logic_vector(4 downto 0) := "00001"; --! int store
constant M_PFR : std_logic_vector(4 downto 0) := "00010"; --! prefetch with intent to read
constant M_PFW : std_logic_vector(4 downto 0) := "00011"; --! prefetch with intent to write
constant M_XA_SWAP : std_logic_vector(4 downto 0) := "00100";
constant M_NOP : std_logic_vector(4 downto 0) := "00101";
constant M_XLR : std_logic_vector(4 downto 0) := "00110";
constant M_XSC : std_logic_vector(4 downto 0) := "00111";
constant M_XA_ADD : std_logic_vector(4 downto 0) := "01000";
constant M_XA_XOR : std_logic_vector(4 downto 0) := "01001";
constant M_XA_OR : std_logic_vector(4 downto 0) := "01010";
constant M_XA_AND : std_logic_vector(4 downto 0) := "01011";
constant M_XA_MIN : std_logic_vector(4 downto 0) := "01100";
constant M_XA_MAX : std_logic_vector(4 downto 0) := "01101";
constant M_XA_MINU : std_logic_vector(4 downto 0) := "01110";
constant M_XA_MAXU : std_logic_vector(4 downto 0) := "01111";
constant M_FLUSH : std_logic_vector(4 downto 0) := "10000"; --! write back dirty data and cede R/W permissions
constant M_PRODUCE : std_logic_vector(4 downto 0) := "10001"; --! write back dirty data and cede W permissions
constant M_CLEAN : std_logic_vector(4 downto 0) := "10011"; --! write back dirty data and retain R/W permissions
function isAMO(cmd : std_logic_vector(4 downto 0)) return std_logic;
--def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
--def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
function isWrite(cmd : std_logic_vector(4 downto 0)) return std_logic;
--def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
--! <tilelink.scala> Object Acquire {}
constant ACQUIRE_GET_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "000";
constant ACQUIRE_GET_BLOCK_DATA : std_logic_vector(2 downto 0) := "001"; --
constant ACQUIRE_PUT_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "010"; -- Single beat data.
constant ACQUIRE_PUT_BLOCK_DATA : std_logic_vector(2 downto 0) := "011"; -- For acMultibeat data.
constant ACQUIRE_PUT_ATOMIC_DATA : std_logic_vector(2 downto 0) := "100"; -- Single beat data. 64 bits width
constant ACQUIRE_PREFETCH_BLOCK : std_logic_vector(2 downto 0) := "101";
--! <tilelink.scala> Object Grant {}
constant GRANT_ACK_RELEASE : std_logic_vector(3 downto 0) := "0000"; -- For acking Releases
constant GRANT_ACK_PREFETCH : std_logic_vector(3 downto 0) := "0001"; -- For acking any kind of Prefetch
constant GRANT_ACK_NON_PREFETCH_PUT : std_logic_vector(3 downto 0) := "0011"; -- For acking any kind of non-prfetch Put
constant GRANT_SINGLE_BEAT_GET : std_logic_vector(3 downto 0) := "0100"; -- Supplying a single beat of Get
constant GRANT_BLOCK_GET : std_logic_vector(3 downto 0) := "0101"; -- Supplying all beats of a GetBlock
--! MESI coherence
constant CACHED_ACQUIRE_SHARED : std_logic_vector(2 downto 0) := "000"; -- get
constant CACHED_ACQUIRE_EXCLUSIVE : std_logic_vector(2 downto 0) := "001"; -- put
constant CACHED_GRANT_SHARED : std_logic_vector(3 downto 0) := "0000";
constant CACHED_GRANT_EXCLUSIVE : std_logic_vector(3 downto 0) := "0001";
constant CACHED_GRANT_EXCLUSIVE_ACK : std_logic_vector(3 downto 0) := "0010";
--! @brief Memory Operation size decoder
--! @details TileLink bus has encoded Memory Operation size
--! in the union[8:6] bits of the acquire request.
constant MEMOP_XSIZE_TOTAL : integer := 8;
type memop_xsize_type is array (0 to MEMOP_XSIZE_TOTAL-1) of std_logic_vector(2 downto 0);
constant opSizeToXSize : memop_xsize_type := (
MT_B => "000",
MT_BU => "000",
MT_H => "001",
MT_HU => "001",
MT_W => "010",
MT_WU => "010", --! unimplemented in scala
MT_D => "011",
MT_Q => conv_std_logic_vector(log2(CFG_NASTI_DATA_BYTES),3)
);
type tile_cached_in_type is record
acquire_ready : std_logic;
grant_valid : std_logic;
grant_bits_addr_beat : std_logic_vector(1 downto 0);
--! client's transaction id
grant_bits_client_xact_id : std_logic_vector(1 downto 0);
grant_bits_manager_xact_id : std_logic_vector(3 downto 0);
grant_bits_is_builtin_type : std_logic;
grant_bits_g_type : std_logic_vector(3 downto 0);
grant_bits_data : std_logic_vector(127 downto 0);
probe_valid : std_logic;
probe_bits_addr_block : std_logic_vector(25 downto 0);
probe_bits_p_type : std_logic_vector(1 downto 0);
release_ready : std_logic;
end record;
type tile_cached_out_type is record
acquire_valid : std_logic;
acquire_bits_addr_block : std_logic_vector(25 downto 0);
acquire_bits_client_xact_id : std_logic_vector(1 downto 0);
acquire_bits_addr_beat : std_logic_vector(1 downto 0);
acquire_bits_is_builtin_type : std_logic;
acquire_bits_a_type : std_logic_vector(2 downto 0);
acquire_bits_union : std_logic_vector(16 downto 0);
acquire_bits_data : std_logic_vector(127 downto 0);
grant_ready : std_logic;
probe_ready : std_logic;
release_valid : std_logic;
release_bits_addr_beat : std_logic_vector(1 downto 0);
release_bits_addr_block : std_logic_vector(25 downto 0);
release_bits_client_xact_id : std_logic_vector(1 downto 0);
release_bits_r_type : std_logic_vector(2 downto 0);
release_bits_voluntary : std_logic;
release_bits_data : std_logic_vector(127 downto 0);
end record;
--! HostIO tile input signals
type host_in_type is record
grant : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0);
csr_req_ready : std_logic;
csr_resp_valid : std_logic;
csr_resp_bits : std_logic_vector(63 downto 0);
debug_stats_csr : std_logic;
end record;
--! HostIO tile output signals
type host_out_type is record
reset : std_logic;
id : std_logic;
csr_req_valid : std_logic;
csr_req_bits_rw : std_logic;
csr_req_bits_addr : std_logic_vector(11 downto 0);
csr_req_bits_data : std_logic_vector(63 downto 0);
csr_resp_ready : std_logic;
end record;
--! Full stack of HostIO output signals from all devices.
type host_out_vector is array (0 to CFG_HTIF_SRC_TOTAL-1)
of host_out_type;
--! @brief Empty output signals of HostIO interface.
--! @details If device was included in the owners of the HostIO interface and
--! was disabled by configuration parameter (for example) then its
--! outputs must be assigned to this empty signals otherwise
--! RTL simulation will fail with undefined states of the processor.
constant host_out_none : host_out_type := (
'0', '0', '0', '0', (others => '0'), (others => '0'), '0');
--! @brief Decode Acquire request from the Cached/Uncached TileLink
--! @param[in] a_type Request type depends of the built_in flag
--! @param[in] built_in This flag defines cached or uncached request. For
--! the uncached this value is set to 1.
--! @param[in] u Union bits. This value is decoding depending of
--! types operation (rd/wr) and cached/uncached.
procedure procedureDecodeTileAcquire (
a_type : in std_logic_vector(2 downto 0);
built_in : in std_logic;
u : in std_logic_vector(16 downto 0);
write : out std_logic;
wmask : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
axi_sz : out std_logic_vector(2 downto 0);
byte_addr : out std_logic_vector(3 downto 0);
beat_cnt : out integer
);
--! @brief HostIO (HTIF) controller declaration.
--! @details This device provides multiplexing of the Host messages
--! from several sources (interrupt controller, ethernet MAC,
--! Debug Support Unit and others) on HostIO bus that is
--! specific for Rocket-chip implementation of RISC-V.
--! @todo Make htifii as a vector to support multi-cores
--! configuration.
component htifctrl is
port (
clk : in std_logic;
nrst : in std_logic;
srcsi : in host_out_vector;
srcso : out host_out_type;
htifii : in host_in_type;
htifio : out host_in_type
);
end component;
--! @brief HTIF serializer input.
--! @details In a case of using L2-cache, 'Uncore' module implements
--! additional layer of the transformation of 128-bits HTIF
--! messages into chunks of HTIF_WIDTH. So we have to
--! implement the same serdes on upper level.
type htif_serdes_in_type is record
--! Chunk was accepted by Uncore subsytem.
ready : std_logic;
--! Current chunk output is valid
valid : std_logic;
--! Chunk bits itself.
bits : std_logic_vector(HTIF_WIDTH-1 downto 0);
end record;
--! @brief HTIF serializer output.
type htif_serdes_out_type is record
valid : std_logic;
bits : std_logic_vector(HTIF_WIDTH-1 downto 0);
ready : std_logic;
end record;
--! @brief RocketTile component declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uncached Tile AXI master index
--! @param[in] rst Reset signal with active HIGH level.
--! @param[in] soft_rst Software Reset via DSU
--! @param[in] clk_sys System clock (BUS/CPU clock).
--! @param[in] slvo Bus-to-Slave device signals.
--! @param[in] msti Bus-to-Master device signals.
--! @param[out] msto1 CachedTile-to-Bus request signals.
--! @param[out] msto2 UncachedTile-to-Bus request signals.
--! @param[in] htifoi Requests from the HostIO-connected devices.
--! @param[out] htifio Response to HostIO-connected devices.
component rocket_l1only is
generic (
xindex1 : integer := 0;
xindex2 : integer := 1
);
port (
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
end component;
--! @brief RocketTile + Uncore component declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uncached Tile AXI master index
--! @param[in] rst Reset signal with active HIGH level.
--! @param[in] soft_rst Software Reset via DSU
--! @param[in] clk_sys System clock (BUS/CPU clock).
--! @param[in] slvo Bus-to-Slave device signals.
--! @param[in] msti Bus-to-Master device signals.
--! @param[out] msto1 CachedTile-to-Bus request signals.
--! @param[out] msto2 UncachedTile-to-Bus request signals.
--! @param[in] htifoi Requests from the HostIO-connected devices.
--! @param[out] htifio Response to HostIO-connected devices.
component rocket_l2cache is
generic (
xindex1 : integer := 0;
xindex2 : integer := 1
);
port (
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
end component;
--! @brief SOC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[in] inPllLock PLL status.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
component reset_global
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
inPllLock : in std_ulogic;
outReset : out std_ulogic );
end component;
--! Boot ROM with AXI4 interface declaration.
component nasti_bootrom is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
--! AXI4 ROM with the default FW version declaration.
component nasti_romimage is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
--! Internal RAM with AXI4 interface declaration.
component nasti_sram is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for 'inferred'
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
--! @brief NASTI (AXI4) GPIO controller
component nasti_gpio is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type;
i_glip : in std_logic_vector(31 downto 0);
o_glip : out std_logic_vector(31 downto 0)
);
end component;
type uart_in_type is record
rd : std_ulogic;
cts : std_ulogic;
end record;
type uart_out_type is record
td : std_ulogic;
rts : std_ulogic;
end record;
--! UART with the AXI4 interface declaration.
component nasti_uart is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
o_irq : out std_logic);
end component;
--! @brief Interrupt controller with the AXI4 interface declaration.
--! @details To rise interrupt on certain CPU HostIO interface is used.
component nasti_irqctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type
);
end component;
--! @brief Declaration of the Debug Support Unit with the AXI interface.
--! @details This module provides access to processors CSRs via HostIO bus.
component nasti_dsu is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type;
o_soft_reset : out std_logic
);
end component;
--! @brief General Purpose Timers with the AXI interface.
--! @details This module provides high precision counter and
--! generic number of GP timers.
component nasti_gptimers is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
o_irq : out std_logic
);
end component;
--! @brief Plug-n-Play support module with AXI4 interface declaration.
--! @details Each device in a system hase to implements sideband signal
--! structure 'nasti_slave_config_type' that allows FW to
--! detect Hardware configuration in a run-time.
--! @todo Implements PnP signals for all Masters devices.
component nasti_pnp is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in nasti_master_cfg_vector;
slvcfg : in nasti_slave_cfg_vector;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
end; -- package declaration
--! -----------------
package body types_rocket is
function isAMO(cmd : std_logic_vector(4 downto 0))
return std_logic is
variable t1 : std_logic;
begin
t1 := '0';
if cmd = M_XA_SWAP then
t1 := '1';
end if;
return (cmd(3) or t1);
end;
function isWrite(cmd : std_logic_vector(4 downto 0))
return std_logic is
variable ret : std_logic;
begin
ret := isAMO(cmd);
if cmd = M_XWR then ret := '1'; end if;
if cmd = M_XSC then ret := '1'; end if;
return (ret);
end;
--! @brief Decode Acquire request from the Cached/Uncached TileLink
--! @param[in] a_type Request type depends of the built_in flag
--! @param[in] built_in This flag defines cached or uncached request. For
--! the uncached this value is set to 1.
--! @param[in] u Union bits. This value is decoding depending of
--! types operation (rd/wr) and cached/uncached.
procedure procedureDecodeTileAcquire(
a_type : in std_logic_vector(2 downto 0);
built_in : in std_logic;
u : in std_logic_vector(16 downto 0);
write : out std_logic;
wmask : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
axi_sz : out std_logic_vector(2 downto 0);
byte_addr : out std_logic_vector(3 downto 0);
beat_cnt : out integer
) is
begin
if built_in = '1' then
-- Cached request
case a_type is
when ACQUIRE_GET_SINGLE_DATA_BEAT =>
write := '0';
wmask := (others => '0');
byte_addr := u(12 downto 9);--tst.block.byte_addr;
axi_sz := opSizeToXSize(conv_integer(u(8 downto 6)));
beat_cnt := 0;
when ACQUIRE_PREFETCH_BLOCK |
ACQUIRE_GET_BLOCK_DATA =>
-- cache line size / data bits width
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 3;--tlDataBeats-1;
when ACQUIRE_PUT_SINGLE_DATA_BEAT =>
-- Single beat data.
write := '1';
wmask := u(CFG_NASTI_DATA_BYTES downto 1);
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 0;
when ACQUIRE_PUT_BLOCK_DATA =>
-- Multibeat data.
write := '1';
wmask := (others => '1');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 3;--tlDataBeats-1;
when ACQUIRE_PUT_ATOMIC_DATA =>
-- Single beat data. 64 bits width
write := '1';
if CFG_NASTI_DATA_BITS = 128 then
if u(12) = '0' then
wmask(7 downto 0) := (others => '1');
wmask(15 downto 8) := (others => '0');
else
wmask(7 downto 0) := (others => '0');
wmask(15 downto 8) := (others => '1');
end if;
else
wmask := (others => '1');
end if;
byte_addr := (others => '0');
axi_sz := opSizeToXSize(conv_integer(u(8 downto 6)));
beat_cnt := 0;
when others =>
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := (others => '0');
beat_cnt := 0;
end case;
else --! built_in = '0'
-- Cached request
case a_type is
when CACHED_ACQUIRE_SHARED =>
write := '0';
wmask := (others => '0');
byte_addr := u(12 downto 9);--tst.block.byte_addr;
axi_sz := opSizeToXSize(conv_integer(u(8 downto 6)));
beat_cnt := 0;
when CACHED_ACQUIRE_EXCLUSIVE =>
-- Single beat data.
write := '1';
wmask := u(CFG_NASTI_DATA_BYTES downto 1);
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 0;
when others =>
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := (others => '0');
beat_cnt := 0;
end case;
end if;
end procedure;
end; -- package body
|
bsd-2-clause
|
2d4dcf51d243be789d9395db46109adb
| 0.615826 | 3.496536 | false | false | false | false |
hoangt/PoC
|
src/mem/ocrom/ocrom_dp.vhdl
| 2 | 5,738 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: True dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating dual-port read-only memory, with:
--
-- * dual clock, clock enable,
-- * 2 read ports.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocrom_dp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocrom_dp is
constant DEPTH : positive := 2**A_BITS;
begin
gXilinx: if DEVICE = DEVICE_SPARTAN6 or DEVICE = DEVICE_VIRTEX6 or
DEVICE=DEVICE_ARTIX7 or DEVICE=DEVICE_KINTEX7 or DEVICE=DEVICE_VIRTEX7
generate
-- RAM can be inferred correctly only for newer FPGAs!
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type rom_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocrom_ReadMemFile(FileName : STRING) return rom_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : rom_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
constant rom : rom_t := ocrom_ReadMemFile(FILENAME);
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1, clk2)
begin -- process
if rising_edge(clk1) then
if ce1 = '1' then
a1_reg <= a1;
end if;
end if;
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
q1 <= rom(to_integer(a1_reg)); -- returns new data
q2 <= rom(to_integer(a2_reg)); -- returns new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
assert FALSE report "Do you really want to generate a block of zeros?" severity FAILURE;
end generate;
end generate gXilinx;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_tdp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
we2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
d2 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_tdp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk1 => clk1,
clk2 => clk2,
ce1 => ce1,
ce2 => ce2,
we1 => '0',
we2 => '0',
a1 => a1,
a2 => a2,
d1 => (others => '0'),
d2 => (others => '0'),
q1 => q1,
q2 => q2
);
end generate gAltera;
assert VENDOR = VENDOR_ALTERA or
DEVICE = DEVICE_SPARTAN6 or DEVICE = DEVICE_VIRTEX6 or
DEVICE = DEVICE_ARTIX7 or DEVICE = DEVICE_KINTEX7 or DEVICE = DEVICE_VIRTEX7
report "Device not yet supported."
severity failure;
end rtl;
|
apache-2.0
|
941eaf940a3ee2af65c842caa0982f9c
| 0.617637 | 3.142388 | false | false | false | false |
hoangt/PoC
|
tb/io/uart/uart_rx_tb.vhdl
| 1 | 3,783 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: uart_rx_tb
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
use PoC.uart.all;
entity uart_rx_tb is
end entity;
architecture tb of uart_rx_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant BAUDRATE : BAUD := 4.2 MBd;
signal Clock : STD_LOGIC;
signal Reset : STD_LOGIC;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal RX_Strobe : STD_LOGIC;
signal RX_Data : T_SLV_8;
function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
constant BIT_TIME : TIME := to_time(to_freq(Baudrate));
variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-'));
begin
Result(0).Value := '0';
for i in Data'range loop
Result(i + 1).Value := Data(i);
end loop;
Result(9).Value := '1';
return Result;
end function;
function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1);
begin
for i in Data'range loop
Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE);
end loop;
return Result;
end function;
constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02");
begin
simGenerateClock(Clock, CLOCK_FREQ);
simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns));
simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1');
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
RX : entity PoC.uart_rx
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
rx => UART_RX,
do => RX_Data,
stb => RX_Strobe
);
process
begin
for i in DATA_STREAM'range loop
wait until rising_edge(Clock) and (RX_Strobe = '1');
report TIME'image(NOW) severity NOTE;
tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h'));
end loop;
wait for 1 us;
simStop;
tbPrintResult;
wait;
end process;
end architecture;
|
apache-2.0
|
12871455fde0a515679f96ef38ba082d
| 0.607454 | 3.205932 | false | false | false | false |
hoangt/PoC
|
src/comm/comm_scramble.vhdl
| 2 | 3,332 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: Computes XOR masks for stream scrambling from an LFSR generator.
--
-- Description:
-- ------------------------------------
-- The LFSR computation is unrolled to generate an arbitrary number of mask
-- bits in parallel. The mask are output in little endian. The generated bit
-- sequence is independent from the chosen output width.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity comm_scramble is
generic (
GEN : bit_vector; -- Generator Polynomial (little endian)
BITS : positive -- Width of Mask Bits to be computed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Set LFSR to provided Value
din : in std_logic_vector(GEN'length-2 downto 0);
step : in std_logic; -- Compute a Mask Output
mask : out std_logic_vector(BITS-1 downto 0)
);
end comm_scramble;
architecture rtl of comm_scramble is
-----------------------------------------------------------------------------
-- Normalizes a generator representation:
-- - into a 'downto 0' index range and
-- - truncating it just below the most significant and so hidden '1'.
function normalize(G : bit_vector) return bit_vector is
variable GN : bit_vector(G'length-1 downto 0);
begin
GN := G;
for i in GN'left downto 1 loop
if GN(i) = '1' then
return GN(i-1 downto 0);
end if;
end loop;
report "Cannot use absolute constant as generator."
severity failure;
end normalize;
-- Normalized Generator
constant GN : bit_vector := normalize(GEN);
-- LFSR Value
signal lfsr : std_logic_vector(GN'range);
begin
process(clk)
-- Intermediate LFSR Values for single-bit Steps
variable v : std_logic_vector(lfsr'range);
begin
if rising_edge(clk) then
if set = '1' then
lfsr <= din(lfsr'range);
elsif step = '1' then
v := lfsr;
for i in 0 to BITS-1 loop
mask(i) <= v(v'left);
v := (v(v'left-1 downto 0) & '0') xor
(to_stdlogicvector(GN) and (GN'range => v(v'left)));
end loop;
lfsr <= v;
end if;
end if;
end process;
end rtl;
|
apache-2.0
|
5e051925e37159f11caa8225f27b8b5e
| 0.580732 | 4.088344 | false | false | false | false |
hoangt/PoC
|
src/io/uart/uart.pkg.vhdl
| 1 | 5,825 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Package: UART (RS232) Components for PoC.io.uart
--
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patrick Lehmann
--
-- License:
-- ===========================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
package uart is
type T_IO_UART_FLOWCONTROL_KIND is (
UART_FLOWCONTROL_NONE,
UART_FLOWCONTROL_XON_XOFF,
UART_FLOWCONTROL_RTS_CTS,
UART_FLOWCONTROL_RTR_CTS
);
constant C_IO_UART_TYPICAL_BAUDRATES : T_BAUDVEC := (
0 => 300 Bd, 1 => 600 Bd, 2 => 1200 Bd, 3 => 1800 Bd, 4 => 2400 Bd,
5 => 4000 Bd, 6 => 4800 Bd, 7 => 7200 Bd, 8 => 9600 Bd, 9 => 14400 Bd,
10 => 16000 Bd, 11 => 19200 Bd, 12 => 28800 Bd, 13 => 38400 BD, 14 => 51200 Bd,
15 => 56000 Bd, 16 => 57600 Bd, 17 => 64000 Bd, 18 => 76800 Bd, 19 => 115200 Bd,
20 => 128000 Bd, 21 => 153600 Bd, 22 => 230400 Bd, 23 => 250000 Bd, 24 => 256000 BD,
25 => 460800 Bd, 26 => 500000 Bd, 27 => 576000 Bd, 28 => 921600 Bd
);
function io_UART_IsTypicalBaudRate(br : BAUD) return BOOLEAN;
-- Bit Clock Generator: 8 Ticks per Bit
component uart_bclk
generic (
CLK_FREQ : positive;
BAUDRATE : positive
);
port (
clk : in std_logic;
rst : in std_logic;
bclk : out std_logic;
bclk_x8 : out std_logic
);
end component;
-- Receiver
component uart_rx is
generic (
SYNC_DEPTH : natural := 2 -- use zero for already clock-synchronous rx
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Bit Clock and RX Line
bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length
rx : in std_logic;
-- Byte Stream Output
do : out std_logic_vector(7 downto 0);
stb : out std_logic
);
end component;
-- Transmitter
component uart_tx is
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Bit Clock and TX Line
bclk : in std_logic; -- bit clock, one strobe each bit length
tx : out std_logic;
-- Byte Stream Input
di : in std_logic_vector(7 downto 0);
put : in std_logic;
ful : out std_logic
);
end component;
-- Wrappers
-- ===========================================================================
-- UART with FIFOs and optional flow control
component uart_fifo is
generic (
-- Communication Parameters
CLOCK_FREQ : FREQ;
BAUDRATE : BAUD;
-- Buffer Dimensioning
TX_MIN_DEPTH : positive := 16;
TX_ESTATE_BITS : natural := 0;
RX_MIN_DEPTH : positive := 16;
RX_FSTATE_BITS : natural := 0;
-- Flow Control
FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE;
SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q
SWFC_XON_TRIGGER : real := 0.0625;
SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S
SWFC_XOFF_TRIGGER : real := 0.75
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- FIFO interface
TX_put : in STD_LOGIC;
TX_Data : in STD_LOGIC_VECTOR(7 downto 0);
TX_Full : out STD_LOGIC;
TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0);
RX_Valid : out STD_LOGIC;
RX_Data : out STD_LOGIC_VECTOR(7 downto 0);
RX_got : in STD_LOGIC;
RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0);
RX_Overflow : out std_logic;
-- External Pins
UART_RX : in std_logic;
UART_TX : out std_logic
);
end component;
-- USB-UART
component ft245_uart is
generic (
CLK_FREQ : positive
);
port (
-- common signals
clk : in std_logic;
reset : in std_logic;
-- send data
snd_ready : out std_logic;
snd_strobe : in std_logic;
snd_data : in std_logic_vector(7 downto 0);
-- receive data
rec_strobe : out std_logic;
rec_data : out std_logic_vector(7 downto 0);
-- connection to ft245
ft245_data : inout std_logic_vector (7 downto 0);
ft245_rdn : out std_logic;
ft245_wrn : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic
);
end component;
end package;
package body uart is
function io_UART_IsTypicalBaudRate(br : BAUD) return BOOLEAN is
begin
for i in C_IO_UART_TYPICAL_BAUDRATES'range loop
next when (br /= C_IO_UART_TYPICAL_BAUDRATES(i));
return TRUE;
end loop;
return FALSE;
end function;
end package body;
|
apache-2.0
|
ccc36e23b4f44e2b8c28a246fa25bc37
| 0.559313 | 3.456973 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/synth/design_1_rst_clk_wiz_1_100M_0.vhd
| 2 | 6,714 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_clk_wiz_1_100M_0;
ARCHITECTURE design_1_rst_clk_wiz_1_100M_0_arch OF design_1_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_clk_wiz_1_100M_0_arch : ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_clk_wiz_1_100M_0_arch;
|
gpl-3.0
|
7c3fe00d834de397a4b35fda1f0aaaf5
| 0.712541 | 3.394338 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/mem_steer.vhd
| 4 | 121,972 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: mem_steer.vhd
-- Description: This file contains the logic for steering the read data,
-- write data and memory controls to the appropriate memory
-- and data byte lane.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Removed the unused part of code (not supporting C_MAX_MEM_WIDTH = 64): -
-- 1. Deleted the generate block lebelled "WRITE_DATABE_MUX_64_GEN".
-- 2. Deleted the generate block lebelled "READ_DATA_64_GEN".
-- Removed the unused part of code (not supporting C_IPIF_DWIDTH = 64): -
-- 1. Deleted the generate block lebelled "READ_DATA_CE_64_GEN".
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- ~~~~~~
-- SK 25/10/10
-- ^^^^^^^^
-- 1. Added "parity_error_mem" in default condition in "MEM_CEN_STEER_PROCESS".
-- 2. In "PARITY_ACK_SYNC",
-- a.added "MEM2BUS_PARITY_ERR_P" by replacing priority logic
-- b.added "MEM2BUS_RD_ACK_P" by replacing priority logic
-- c.added "ADDR_ALIGN_READ_P" by replacing priority logic for addr_align_read
-- ~~~~~~
-- SK 24/11/10
-- ^^^^^^^^
-- 1. Added "ns_idle" signal to reset the address counter in mem_steer.vhd
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDS, FDR and FDCE
-- component declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- Number of Memory Banks
-- C_MAX_MEM_WIDTH -- Maximum memory width of all memory banks
-- C_MIN_MEM_WIDTH -- Minimum memory width (set to 8 bits)
-- C_IPIF_DWIDTH -- Width of IPIF data bus
-- C_ADDR_CNTR_WIDTH -- Width of address counter
-- C_GLOBAL_DATAWIDTH_MATCH -- Indicates if datawidth matching is
-- implemented in any memory bank
-- C_GLOBAL_SYNC_MEM -- Indicates if any memory bank is
-- synchronous
--
-- Definition of Ports:
-- EMC signals
-- Bus2IP_Data -- Processor Data Bus
-- Bus2IP_BE -- Processor Byte Enable
-- Bus2IP_Mem_CS -- Memory Channel Chip Select
--
-- Memory state machine signals
-- Write_req_ack -- Memory Write Acknowledge
-- Read_req_ack -- Memory Read Address Acknowledge
-- Read_ack -- Memory Read Acknowledge
-- Read_data_en -- Read Data Enable for read registers
-- Data_strobe -- Data Strobe signal
-- MSM_Mem_CEN -- Memory Chip Enable
-- MSM_Mem_OEN -- Memory Output Enable
-- MSM_Mem_WEN -- Memory Write Enable
-- Mem2Bus_WrAddrAck -- Memory Write Address Acknowledge
-- Mem2Bus_WrAck -- Memory Write Data Acknowledge
-- Mem2Bus_RdAddrAck -- Memory Read Address Acknowledge
-- Mem2Bus_RdAck -- Memory Read Data Acknowledge
-- Mem2Bus_Data -- Memory Read Data
-- Select Param signals
-- Mem_width_bytes -- Memory Device Width in Bytes
-- Synch_mem -- Synchronous Memory Control
-- Two_pipe_delay -- Synchronous pipeline stages
-- Addr counter mux signals
-- Addr_cnt -- Address Count
-- IO Register signals
-- MemSteer_Mem_DQ_I -- Memory Device Data In
-- MemSteer_Mem_DQ_O -- Memory Device Data Out
-- MemSteer_Mem_DQ_T -- Memory Device FPGA Impedance Control
-- MemSteer_Mem_DQ_prty_I -- Memory Device Parity Input
-- MemSteer_Mem_DQ_prty_O -- Memory Device Parity Output
-- MemSteer_Mem_DQ_prty_T -- Memory Device Parity Impedance Control
-- MemSteer_Mem_CEN -- Memory Device Chip Enable (Active Low)
-- MemSteer_Mem_OEN -- Memory Device Output Enable
-- MemSteer_Mem_WEN -- Memory Device Write Enable
-- MemSteer_Mem_QWEN -- Memory Device Qualified Write Enabled
-- MemSteer_Mem_BEN -- Memory Device Byte Enable
-- MemSteer_Mem_CE -- Memory Device Chip Enable (Active High)
-- MemSteer_Mem_RNW -- Memory Device Read/Write
--
-- Clock and reset
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity mem_steer is
generic (
C_NUM_BANKS_MEM : integer;
C_MAX_MEM_WIDTH : integer;
C_MIN_MEM_WIDTH : integer;
C_IPIF_DWIDTH : integer;
C_IPIF_AWIDTH : integer;
C_PARITY_TYPE_MEMORY : integer range 0 to 1;
C_ADDR_CNTR_WIDTH : integer range 1 to 5;
C_GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1;
C_GLOBAL_SYNC_MEM : integer range 0 to 1
);
port (
-- Clock and reset
Clk : in std_logic;
Rst : in std_logic;
-- EMC signals
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_Burst : in std_logic;
-- Memory state machine signals
Write_req_ack : in std_logic;
Read_req_ack : in std_logic;
Read_ack : in std_logic;
Read_data_en : in std_logic;
-- Data_strobe : in std_logic;09-12-2012
MSM_Mem_CEN : in std_logic;
MSM_Mem_OEN : in std_logic;
MSM_Mem_WEN : in std_logic;
Mem2Bus_WrAddrAck : out std_logic;
Mem2Bus_WrAck : out std_logic;
Mem2Bus_RdAddrAck : out std_logic;
Mem2Bus_RdAck : out std_logic;
Mem2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH -1);
-- Select param signals
Mem_width_bytes : in std_logic_vector(0 to 3);
Synch_mem : in std_logic;
Two_pipe_delay : in std_logic;
single_transaction : in std_logic;
-- Parity logic
parity_error_mem : out std_logic_vector(0 to 1);
Parity_enable : in std_logic;
Parity_type : in std_logic;
Parity_err : out std_logic;
-- Addr counter mux signal
Addr_cnt : in std_logic_vector(0 to
C_ADDR_CNTR_WIDTH-1);
Addr_align : in std_logic;
Addr_align_rd : in std_logic;
-- IO register signals
MemSteer_Mem_DQ_I : in std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_O : out std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_T : out std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_prty_I : in std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_DQ_prty_O : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_DQ_prty_T : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_CEN : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_OEN : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_WEN : out std_logic;
MemSteer_Mem_QWEN : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_BEN : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_CE : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_RNW : out std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
Write_req_data_ack : in std_logic;
Write_req_addr_ack : in std_logic;
address_strobe_c : in std_logic;
be_strobe_c : in std_logic;
data_strobe_c : in std_logic;
ns_idle : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Linear_flash_brst_rd_flag : in std_logic;
last_addr : in std_logic; -- stop_oen
stop_oen : in std_logic;
cycle_end: in std_logic;
axi_arsize: in std_logic_vector(2 downto 0);
axi_trans_size_reg : in std_logic_vector(1 downto 0)
);
end entity mem_steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of mem_steer is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal mem_cen_cmb : std_logic;
signal mem_oen_cmb : std_logic;
signal read_ack_d : std_logic_vector(0 to 5);
signal read_parity_d : std_logic_vector(0 to 5);
signal addr_align_d : std_logic_vector(0 to 5);
signal addr_align_read : std_logic;
signal write_data : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal write_data_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_parity : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal write_data_parity_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal read_data : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal read_parity : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal write_data_d1 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_d2 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_parity_d1 : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal write_data_parity_d2 : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_be_i : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_t_cmb : std_logic_vector(0 to 3);
signal mem_dq_parity_t_cmb : std_logic_vector(0 to 3);
signal addr_cnt_d1 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d2 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d3 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d4 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_sel : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal mem_dqt_t_d : std_logic;
signal mem_dqt_t_async : std_logic;
signal mem_dqt_parity_t_d : std_logic;
signal mem_dqt_parity_t_async : std_logic;
signal Read_req_ack_reg : std_logic;
signal readreq_th_reset : std_logic;
signal read_data_ce : std_logic_vector(0 to 7);
signal read_data_en_d : std_logic_vector(0 to 4);
signal read_data_en_sel : std_logic;
signal read_data_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal read_data_parity : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal read_data_parity_cmb : std_logic_vector(0 to C_IPIF_DWIDTH/8-1) := (OTHERS => '0');
signal read_data_parity_int : std_logic_vector(0 to C_IPIF_DWIDTH/8-1) := (OTHERS => '0');
signal Bus2IP_Mem_CS_del : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal single_par_err : std_logic;
signal single_par_err_int : std_logic;
signal Mem2Bus_RdAck_int : std_logic;
signal Parity_err_int : std_logic;
signal cmb_ored,comp_int : std_logic;
signal arsize_int,arsize_int_e,mem_bytes_int: integer range 0 to 64;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others => r);
return( l and rex );
end function "and";
function calc_parity ( data_in : std_logic_vector (0 to 7);
Parity_type : std_logic
)
return std_logic is
variable parity_out_temp: std_logic;
begin
if Parity_type = '0' then
parity_out_temp := '0';
for j in 0 to 7 loop
parity_out_temp := parity_out_temp XOR data_in(j);
end loop;
elsif Parity_type = '1' then
parity_out_temp := '1';
for j in 0 to 7 loop
parity_out_temp := NOT(parity_out_temp XOR data_in(j));
end loop;
else
parity_out_temp := '0';
end if;
return parity_out_temp;
end function calc_parity;
function check_parity ( data_in : std_logic_vector (0 to 7);
parity_bit : std_logic;
Parity_type : std_logic
)
return std_logic is
variable parity_result : std_logic;
variable parity_out_temp : std_logic;
begin
if Parity_type = '0' then
parity_out_temp := '0';
for j in 0 to 7 loop
parity_out_temp := parity_out_temp XOR data_in(j);
end loop;
elsif Parity_type = '1' then
parity_out_temp := '1';
for j in 0 to 7 loop
parity_out_temp := NOT(parity_out_temp XOR data_in(j));
end loop;
else
parity_out_temp := '0';
end if;
if parity_bit= parity_out_temp then
return '0';
else
return '1';
end if;
end function check_parity;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
signal addr_cnt_numonyx : std_logic;
--attribute IOB : string;
--attribute IOB of mem_dqt_t_d : signal is "true";
begin -- architecture imp
read_ack_d (5) <= '0';
addr_align_d (5) <= '0';
MemSteer_Mem_BEN <= not mem_be_i;
MemSteer_Mem_RNW <= MSM_Mem_WEN;
MemSteer_Mem_QWEN <= not(mem_be_i and (not MSM_Mem_WEN));
MemSteer_Mem_WEN <= MSM_Mem_WEN;
Mem2Bus_RdAck <= Mem2Bus_RdAck_int;
ADDR_CNT_SYNCH_MODE : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
addr_cnt_numonyx <= '0';
elsif(Linear_flash_brst_rd_flag = '1') then
if(Read_ack = '1') then
addr_cnt_numonyx <= not(addr_cnt_numonyx);
end if;
end if;
end if;
end process ADDR_CNT_SYNCH_MODE;
-------------------------------------------------------------------------------
-- Memory chip enable control generation.
-------------------------------------------------------------------------------
mem_cen_cmb <= MSM_Mem_CEN;
MEM_CEN_SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
MemSteer_Mem_CEN(0) <= mem_cen_cmb; -- 10-12-2012
--CEN_P: process (stop_oen, synch_mem,mem_cen_cmb) is -- 10-12-2012
--begin
-- if(synch_mem = '1') then
-- MemSteer_Mem_CEN(0) <= mem_cen_cmb or stop_oen;
-- else
-- MemSteer_Mem_CEN(0) <= mem_cen_cmb;
-- end if;
--end process CEN_P;
MemSteer_Mem_CE(0) <= not mem_cen_cmb;
parity_error_mem <= "00";
end generate MEM_CEN_SINGLE_BANK_GEN;
-------------------------------------------------------------------------------
-- Generate chip enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_CEN_MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
-------------------------------------------------------------------------------
-- Chip enable steer process steers the chip enable to the corresponding memory
-- bank.
-------------------------------------------------------------------------------
MEM_CEN_STEER_PROCESS: process(mem_cen_cmb, Bus2IP_Mem_CS)
begin
MemSteer_Mem_CEN <= (others => '1');
MemSteer_Mem_CE <= (others => '0');
parity_error_mem <= (others => '0');
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1')then
MemSteer_Mem_CEN(i) <= mem_cen_cmb;
MemSteer_Mem_CE(i) <= not mem_cen_cmb;
parity_error_mem <= conv_std_logic_vector
(i,2);
end if;
end loop;
end process MEM_CEN_STEER_PROCESS;
end generate MEM_CEN_MULTI_BANK_GEN;
-------------------------------------------------------------------------------
-- Memory output enable control generation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_OEN : if C_GLOBAL_SYNC_MEM = 1 generate
signal mem_oen_d : std_logic_vector(0 to 2);
signal mem_oen_sync : std_logic;
begin
mem_oen_d(0) <= MSM_Mem_OEN;
-------------------------------------------------------------------------------
-- FDS primitive is used for output enable pipe generation.
-------------------------------------------------------------------------------
OEN_PIPE_GEN : for i in 0 to 1 generate
begin
OEN_PIPE: FDS
port map (
Q => mem_oen_d(i+1), --[out]
C => Clk, --[in]
D => mem_oen_d(i), --[in]
S => Rst --[in]
);
end generate OEN_PIPE_GEN;
mem_oen_sync <= mem_oen_d(2) and mem_oen_d(1) when (Two_pipe_delay = '1') -- 1/3/2013
--mem_oen_d(2) when (Two_pipe_delay = '1') -- 1/3/2013
else
mem_oen_d(1) and mem_oen_d(0);
mem_oen_cmb <= mem_oen_d(0) when (Synch_mem = '0')
else
mem_oen_sync;
end generate SYNC_MEM_OEN;
-------------------------------------------------------------------------------
-- Generate output enable signals when C_GLOBAL_STNC_MEM = 0.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_OEN : if C_GLOBAL_SYNC_MEM = 0 generate
begin
mem_oen_cmb <= MSM_Mem_OEN;
end generate ASYNC_MEM_OEN;
-------------------------------------------------------------------------------
-- Generate output enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_OEN_SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
--OEN_P: process (stop_oen, synch_mem,mem_oen_cmb) is -- 10-12-2012
--begin
-- if(synch_mem = '1') then
-- MemSteer_Mem_OEN(0) <= mem_oen_cmb or stop_oen;
-- else
-- MemSteer_Mem_OEN(0) <= mem_oen_cmb;
-- end if;
--end process OEN_P;
MemSteer_Mem_OEN(0) <= mem_oen_cmb; -- 10-12-2012
end generate MEM_OEN_SINGLE_BANK_GEN;
-------------------------------------------------------------------------------
-- Generate output enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_OEN_MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
-------------------------------------------------------------------------------
-- Output enable steer process is used to steer the output enable to the
-- corresponding memory bank.
-------------------------------------------------------------------------------
MEM_OEN_STEER_PROCESS: process(mem_oen_cmb, Bus2IP_Mem_CS)
begin
MemSteer_Mem_OEN <= (others => '1');
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1')then
MemSteer_Mem_OEN(i) <= mem_oen_cmb;
end if;
end loop;
end process MEM_OEN_STEER_PROCESS;
end generate MEM_OEN_MULTI_BANK_GEN;
-------------------------------------------------------------------------------
-- Address and Data ack generation.
-------------------------------------------------------------------------------
--Mem2Bus_WrAddrAck <= Write_req_ack and (Bus2IP_WrReq_emc or single_transaction);
--Mem2Bus_WrAck <= Write_req_ack ;
Mem2Bus_WrAddrAck <= Write_req_addr_ack and
(Bus2IP_WrReq_emc or single_transaction or last_addr);
Mem2Bus_WrAck <= Write_req_data_ack;
Mem2Bus_RdAddrAck <= Read_req_ack;-- and Bus2IP_RdReq_emc;
read_ack_d(0) <= Read_ack;
addr_align_d(0) <= Addr_align_rd;
-------------------------------------------------------------------------------
-- Geneartion of Mem2Bus_RdAck signal when external memory bank has at least
-- one synchronous memory
-------------------------------------------------------------------------------
GSYNC_MEM_RDACK_GEN : if C_GLOBAL_SYNC_MEM = 1 generate
begin
---------------------------------------------------------------------------
-- Read ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_GEN_SYNC : for i in 0 to 3 generate
begin
readreq_th_reset <= ((not Bus2IP_RdReq) and ( not single_transaction))
or Rst;
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_SYNC: FDR
port map (
Q => read_ack_d(i+1), --[out]
C => Clk, --[in]
D => read_ack_d(i), --[in]
R => readreq_th_reset --[in]
);
end generate RDACK_PIPE_GEN_SYNC;
NO_PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY=0) generate
Parity_err <= '0';
end generate NO_PARITY_ACK_SYNC;
PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY/=0) generate
---------------------------------------------------------------------------
-- ERR ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_GEN_SYNC : for i in 0 to 3 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_SYNC: FDR
port map (
Q => read_parity_d(i+1), --[out]
C => Clk, --[in]
D => read_parity_d(i), --[in]
R => Rst --[in]
);
end generate ERRACK_PIPE_GEN_SYNC;
--Parity_err_int <= read_parity_d(2) when (Synch_mem = '0') else
-- read_parity_d(3) when (Synch_mem = '1' and
-- Two_pipe_delay = '0') else
-- read_parity_d(4) when (Two_pipe_delay = '1')
--
-- else '0'; --10/25/2010
COMP_INT_S:process (clk)
begin
if clk'event and clk = '1' then
if arsize_int >= mem_bytes_int then
comp_int <= '0';
else
comp_int <= '1';
end if;
end if;
end process COMP_INT_S;
MEM2BUS_PARITY_ERR_P: process(read_parity_d(1),
read_parity_d(2),--10/25/2010
read_parity_d(3),
read_parity_d(4),
Synch_mem,
comp_int,
Two_pipe_delay) is
variable parity_sync_mem_pipe_delay: std_logic_vector(2 downto 0);
begin
parity_sync_mem_pipe_delay := comp_int & Synch_mem & Two_pipe_delay;
case parity_sync_mem_pipe_delay is
when "000" => Parity_err_int <= read_parity_d(2); -- async mem
when "001" => Parity_err_int <= read_parity_d(2); -- async mem
when "010" => Parity_err_int <= read_parity_d(2); -- and read_ack_d(3);--(3); -- sync mem + pipe delay
when "011" => Parity_err_int <= read_parity_d(4); -- sync mem + pipe delay 2
when "100" => Parity_err_int <= read_parity_d(1); -- async mem
when "101" => Parity_err_int <= read_parity_d(1); -- async mem
when "110" => Parity_err_int <= read_parity_d(1); -- and read_ack_d(3);--(3); -- sync mem + pipe delay
when "111" => Parity_err_int <= read_parity_d(3); -- sync mem + pipe delay 2
-- coverage off
when others => Parity_err_int <= '0';
-- coverage on
end case;
end process MEM2BUS_PARITY_ERR_P;
arsize_int_e <= conv_integer(axi_arsize);
PARITY_CALC_32 : if (C_IPIF_DWIDTH = 32) generate
SIZE_SYN_32: process(CLK)
begin
if (clk'event and clk = '1') then
case axi_arsize is
when "000" =>
cmb_ored <= read_data_parity_cmb(0);
when "001" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 1));
when "010" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 3));
when OTHERS =>
cmb_ored <= read_data_parity_cmb(0);
end case;
end if;
end process SIZE_SYN_32;
end generate PARITY_CALC_32;
PARITY_CALC_64 : if (C_IPIF_DWIDTH = 64) generate
SIZE_SYN_64: process(CLK)
begin
if (clk'event and clk = '1') then
case axi_arsize is
when "000" =>
cmb_ored <= read_data_parity_cmb(0);
when "001" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 1));
when "010" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 3));
when "011" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 7));
when OTHERS =>
cmb_ored <= read_data_parity_cmb(0);
end case;
end if;
end process SIZE_SYN_64;
end generate PARITY_CALC_64;
--SIZE_CONV: process(arsize_int)
--begin
-- case arsize_int is
-- when 0 =>
-- arsize_bytes <= 1;
-- when 1 =>
-- arsize_bytes <= 2;
-- when 2 =>
-- arsize_bytes <= 4;
-- when 3 =>
-- arsize_bytes <= 8;
-- when 4 =>
-- arsize_bytes <= 16;
-- when 5 =>
-- arsize_bytes <= 32;
-- when 6 =>
-- arsize_bytes <= 64;
-- when OTHERS =>
-- arsize_bytes <= 1;
-- end case;
--end process SIZE_CONV;
INT_CONV_SIZE: process(arsize_int_e)
begin
case arsize_int_e is
when 0 =>
arsize_int <= 1;
when 1 =>
arsize_int <= 2;
when 2 =>
arsize_int <= 4;
when 3 =>
arsize_int <= 8;
when OTHERS =>
arsize_int <= 1;
end case;
end process INT_CONV_SIZE;
INT_CONV: process(Mem_width_bytes)
begin
case Mem_width_bytes is
when "0001" =>
mem_bytes_int <= 1;
when "0010" =>
mem_bytes_int <= 2;
when "0100" =>
mem_bytes_int <= 4;
when "1000" =>
mem_bytes_int <= 8;
when OTHERS =>
mem_bytes_int <= 1;
end case;
end process INT_CONV;
-------------------------
--process (read_data_parity_cmb)
--begin
-- for i in 0 to arsize_int loop
-- read_data_parity_int(i) <= read_data_parity_cmb(i);
-- end loop;
--end process;
process (Clk)
begin
if (clk'event and clk = '1') then
if (Rst = '1') then
single_par_err <= '0';
else
if (arsize_int >= mem_bytes_int) then
single_par_err <= or_reduce(read_data_parity_cmb) and single_transaction;
else
--single_par_err <= or_reduce(read_data_parity_cmb(0 to arsize_int)) and single_transaction;
single_par_err <= cmb_ored;
end if;
end if;
end if;
end process;
process (Clk)
begin
if (clk'event and clk = '1') then
if (Rst = '1') then
single_par_err_int <= '0';
else
single_par_err_int <= Mem2Bus_RdAck_int and single_par_err;
end if;
end if;
end process;
Parity_err <= Parity_err_int or single_par_err_int;
---------------------------
--read_parity_d(0) <= -- or_reduce(read_data_parity_cmb) and Read_ack;
-- (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) -- read_ack_d(3))
-- when Two_pipe_delay = '0'
-- else
-- (or_reduce(read_data_parity_cmb) and read_ack_d(4));
--read_parity_d(0) <=
-- (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) when Two_pipe_delay = '0' else (or_reduce(read_data_parity_cmb) and read_ack_d(4))
-- when arsize_int >= mem_bytes_int else
-- ((cmb_ored) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq)) when Two_pipe_delay = '0' else ((cmb_ored) and read_ack_d(4));
read_parity_d(0) <=
(or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) when arsize_int >= mem_bytes_int else ((cmb_ored) and (or_reduce(read_data_ce)) and (Read_ack))
when Two_pipe_delay = '0' else
(or_reduce(read_data_parity_cmb) and read_ack_d(4)) when arsize_int >= mem_bytes_int else ((cmb_ored) and read_ack_d(4));
--process (read_data_ce,
-- read_data_parity_cmb,
-- Bus2IP_RdReq,
-- read_ack_d,
-- Two_pipe_delay,
-- read_data_parity_int
-- )
--begin
-- if (arsize_int >= mem_bytes_int) then
-- if (Two_pipe_delay = '0') then
-- read_parity_d(0) <= (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq); -- read_ack_d(3))
-- else
-- read_parity_d(0) <= (or_reduce(read_data_parity_cmb) and read_ack_d(4));
-- end if;
-- else
-- if (Two_pipe_delay = '0') then
-- read_parity_d(0) <= (cmb_ored) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq); -- read_ack_d(3))
-- else
-- read_parity_d(0) <= (cmb_ored) and read_ack_d(4);
-- end if;
-- end if;
--end process;
end generate PARITY_ACK_SYNC;
--Mem2Bus_RdAck <= -- read_ack_d(2) when (Synch_mem = '0') else
-- read_ack_d(3) when (Synch_mem = '1' and
-- Two_pipe_delay = '0') else
-- read_ack_d(4) when (Two_pipe_delay = '1')
-- else '0'; -- 10/25/2010
MEM2BUS_RD_ACK_P: process(read_ack_d(2), -- 10/25/2010
read_ack_d(3),
read_ack_d(4),
Synch_mem,
addr_cnt_numonyx,
Read_ack,
Linear_flash_brst_rd_flag,
Two_pipe_delay) is
variable sync_mem_pipe_delay: std_logic_vector(1 downto 0);
begin
sync_mem_pipe_delay := Synch_mem & Two_pipe_delay;
case sync_mem_pipe_delay is
when "00" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "01" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "10" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(3);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "11" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(4);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
-- coverage off
when others => Mem2Bus_RdAck_int <= '0';
-- coverage on
end case;
end process MEM2BUS_RD_ACK_P;
ADDR_ALIGN_PIPE_GEN : for i in 0 to 3 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for Address align pipe generation.
---------------------------------------------------------------------------
ALIGN_PIPE: FDR
port map (
Q => addr_align_d(i+1), --[out]
C => Clk, --[in]
D => addr_align_d(i), --[in]
R => Rst --[in]
);
end generate ADDR_ALIGN_PIPE_GEN;
--addr_align_read <= addr_align_d(0)when Synch_mem = '0'
-- else
-- addr_align_d(1) when Synch_mem = '1' and Two_pipe_delay = '0'
-- else
-- addr_align_d(2);--10/25/2010
ADDR_ALIGN_READ_P: process(addr_align_d(0), -- 10/25/2010
addr_align_d(1),
addr_align_d(2),
Synch_mem,
Two_pipe_delay) is
variable addr_align_syn_pipe_dly: std_logic_vector(1 downto 0);
begin
addr_align_syn_pipe_dly := Synch_mem & Two_pipe_delay;
case addr_align_syn_pipe_dly is
when "00" => addr_align_read <= addr_align_d(0);
when "01" => addr_align_read <= addr_align_d(0);
when "10" => addr_align_read <= addr_align_d(1);
when "11" => addr_align_read <= addr_align_d(2);
-- coverage off
when others => addr_align_read <=addr_align_d(2);
-- coverage on
end case;
end process ADDR_ALIGN_READ_P;
------------------------------
end generate GSYNC_MEM_RDACK_GEN;
-------------------------------------------------------------------------------
-- Geneartion of Mem2Bus_RdAck signal when external memory bank has only
-- asynchronous memory
-------------------------------------------------------------------------------
ASYNC_MEM_RDACK_GEN : if (C_GLOBAL_SYNC_MEM = 0) generate
begin
---------------------------------------------------------------------------
-- Read ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_GEN_ASYNC : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
readreq_th_reset <= ((not Bus2IP_RdReq) and ( not single_transaction))
or Rst;
RDACK_PIPE_ASYNC: FDR
port map (
Q => read_ack_d(i+1), --[out]
C => Clk, --[in]
D => read_ack_d(i), --[in]
R => readreq_th_reset --[in]
);
end generate RDACK_PIPE_GEN_ASYNC;
NO_ASYN_PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY=0) generate
Parity_err <= '0';
end generate NO_ASYN_PARITY_ACK_SYNC;
PARITY_ACK : if (C_PARITY_TYPE_MEMORY/=0) generate
---------------------------------------------------------------------------
-- ERR ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_GEN_ASYNC : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_ASYNC: FDR
port map (
Q => read_parity_d(i+1), --[out]
C => Clk, --[in]
D => read_parity_d(i), --[in]
R => Rst --[in]
);
end generate ERRACK_PIPE_GEN_ASYNC;
Parity_err <= read_parity_d(2);
end generate PARITY_ACK;
-- Mem2Bus_RdAck <= read_ack_d(2) when (Linear_flash_brst_rd_flag = '0') else (addr_cnt_numonyx and Read_ack) ;
ASYNC_MEM_MEM2BUS_RDACK_P: process(read_ack_d(2),
Linear_flash_brst_rd_flag,
cycle_end,
Read_ack,
axi_trans_size_reg,
addr_cnt_numonyx )is
begin
if(Linear_flash_brst_rd_flag = '0')then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
if(axi_trans_size_reg(1) = '0')then -- half word access
Mem2Bus_RdAck_int <= cycle_end and Read_ack;
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
end if;
end process ASYNC_MEM_MEM2BUS_RDACK_P;
---------------------------------------------------------------------------
-- ADDR ALLIGN pipe generation.
---------------------------------------------------------------------------
AALIGN_PIPE_GEN : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for Address align pipe generation.
---------------------------------------------------------------------------
AALIGN_PIPE: FDR
port map (
Q => addr_align_d(i+1), --[out]
C => Clk, --[in]
D => addr_align_d(i), --[in]
R => Rst --[in]
);
end generate AALIGN_PIPE_GEN;
addr_align_read <= addr_align_d(0);
end generate ASYNC_MEM_RDACK_GEN;
-------------------------------------------------------------------------------
-- Store the data coming from bus, as address ack and data ack is issued early,
-- and to make burst appear as continuous on memory side.
-------------------------------------------------------------------------------
DATA_STORE_GEN: for i in 0 to C_IPIF_DWIDTH - 1 generate
begin
-------------------------------------------------------------------------------
-- FDCE primitive is used for latching Bus2IP_Data when Data_strobe = 1.
-------------------------------------------------------------------------------
WRDATA_REG: FDRE
port map (
Q => write_data(i), --[out]
C => Clk, --[in]
CE => data_strobe_c,--Data_strobe, --[in]
D => Bus2IP_Data(i), --[in]
R => Rst --[in]
);
end generate DATA_STORE_GEN;
-------------------------------------------------------------------------------
-- When one of the memory bank has different data width than OPB/MCH data
-- width, data steering logic is required.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 ------------------------
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-------------------------------------------------------------------------------
-- Write data path
-------------------------------------------------------------------------------
-- Write data mux is used to multiplex write_data out to memories. This will
-- vary on whether the max memory data width is 8, 16, 32 or 64. Separate
-- generate statements are used for each of them. If the memory is synchronous,
-- the BEs assert at the same time. However, the write data goes out one or
-- two clocks later (depending on Two_pipe_delay). Therefore, separate
-- processes are used for the write data and byte enables.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_64_GEN: if (C_MAX_MEM_WIDTH=64 and C_IPIF_DWIDTH=64) generate
begin
-------------------------------------------------------------------------------
-- Write data path for 64 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_64: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
write_data_parity_cmb <= (others => '0');
case Mem_width_bytes is
when "0001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "0010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "0100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 4*C_MIN_MEM_WIDTH-1) <=
write_data(i*4*C_MIN_MEM_WIDTH to
i*4*C_MIN_MEM_WIDTH + 4*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "1000" =>
if Addr_cnt = conv_std_logic_vector(0, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MAX_MEM_WIDTH-1) <=
write_data(0 to C_MAX_MEM_WIDTH-1);
end if;
when others =>
write_data_cmb <= (others => '0');
end case;
end process WRITE_DATA_MUX_PROCESS_64;
-------------------------------------------------------------------------------
-- Write data path for 64 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_64: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes is
when "0001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "0010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "0100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 4*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*4*C_MIN_MEM_WIDTH/8 to
i*4*C_MIN_MEM_WIDTH/8 + 4*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "1000" =>
if Addr_cnt = conv_std_logic_vector(0, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH-1) <=
Bus2IP_BE(0 to C_MIN_MEM_WIDTH-1);
end if;
when others =>
mem_be_i <= (others => '0');
end case;
end process WRITE_BE_MUX_PROCESS_64;
WRITE_PARITY_EN_64_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
--
-- WRITE_PARITY_MUX_PROCESS_64: process(Parity_type,
-- Addr_cnt,
-- write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
--
-- for i in 0 to 7 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
--
--
-- end process WRITE_PARITY_MUX_PROCESS_64;
WRITE_DATA_PARITY_PROCESS_64: process(Mem_width_bytes,
Addr_cnt,
write_data_parity_cmb,
Parity_type,
write_data,
write_data_cmb
) is
begin
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes is
when "0001" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
write_data_parity_cmb(0) <= calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
when "0010" => -- 16 bit memory (need only two Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 1 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
when "0100" => -- 32 bit memory (need four Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 3 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
when "1000" => -- 64 bit memory (need eight Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 7 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_64;
end generate WRITE_PARITY_EN_64_MAX;
end generate WRITE_DATABE_MUX_64_GEN;
-------------------------------------------------------------------------------
-- Write data path
-------------------------------------------------------------------------------
-- Write data mux is used to multiplex write_data out to memories. This will
-- vary on whether the max memory data width is 8, 16, 32 or 64. Separate
-- generate statements are used for each of them. If the memory is synchronous,
-- the BEs assert at the same time. However, the write data goes out one or
-- two clocks later (depending on Two_pipe_delay). Therefore, separate
-- processes are used for the write data and byte enables.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Write data byte enable generation for 32 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_32_GEN: if (C_MAX_MEM_WIDTH=32) generate
begin
-------------------------------------------------------------------------------
-- Write data path for 32 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_32: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 4*C_MIN_MEM_WIDTH-1) <=
write_data(i*4*C_MIN_MEM_WIDTH to
i*4*C_MIN_MEM_WIDTH + 4*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when others =>
write_data_cmb <= (others => '0');
end case;
end process WRITE_DATA_MUX_PROCESS_32;
-------------------------------------------------------------------------------
-- Write data path for 32 Bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_32: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 4*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*4*C_MIN_MEM_WIDTH/8 to
i*4*C_MIN_MEM_WIDTH/8 + 4*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when others =>
mem_be_i <= (others => '0');
end case;
end process WRITE_BE_MUX_PROCESS_32;
-----------------------------------**--
WRITE_PARITY_EN_32_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
--
-- WRITE_PARITY_MUX_PROCESS_32: process(Parity_type, Addr_cnt, write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
-- ----------
-- for i in 0 to 3 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- ----------
-- end process WRITE_PARITY_MUX_PROCESS_32;
-- WRITE_DATA_PARITY_PROCESS_32: process(Mem_width_bytes,
-- Addr_cnt,
-- write_data_parity_cmb,
-- Parity_type
-- ) is
-- begin
-- write_data_parity_cmb <= (others => '0');
-- --------------
-- case Mem_width_bytes(1 to 3) is
-- when "001" => -- 8 bit memory (need only one Parity Enable bit to active)
-- for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
--
-- when "010" => -- 16 bit memory (need only two Parity Enable bits to active)
-- for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- when "100" => -- 32 bit memory (need four Parity Enable bits to active)
-- for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- -- coverage off
-- when others =>
-- write_data_parity_cmb <= (others => '0');
-- -- coverage on
-- end case;
-- --------------
-- end process WRITE_DATA_PARITY_PROCESS_32;
WRITE_DATA_PARITY_PROCESS_32: process(Mem_width_bytes,
Addr_cnt,
write_data_cmb,
Parity_type,
write_data
) is
-----
begin
-----
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes(1 to 3) is
------------
when "001" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- for j in 0 to 1 loop
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
-- end loop;
--end if;
--end loop;
write_data_parity_cmb(0) <= calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
------------
when "010" => -- 16 bit memory (need only two Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- for j in 0 to 1 loop
-- write_data_parity_cmb(j) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--
-- end loop;
-- end if;
--end loop;
for i in 0 to 1 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
------------
when "100" => -- 32 bit memory (need four Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- --for j in 0 to 3 loop
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--
-- --end loop;
-- end if;
--end loop;
for i in 0 to 3 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
------------
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
------------
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_32;
--------------------------------------
end generate WRITE_PARITY_EN_32_MAX;
-----------------------------------**--
end generate WRITE_DATABE_MUX_32_GEN;
-------------------------------------------------------------------------------
-- Write data byte enable generation for 16 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_16_GEN: if C_MAX_MEM_WIDTH=16 generate
begin
-------------------------------------------------------------------------------
-- Write data path for 16 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_16: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
--------------
case Mem_width_bytes(2 to 3) is
when "01" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "10" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
-- coverage off
when others =>
write_data_cmb <= (others => '0');
-- coverage on
end case;
--------------
end process WRITE_DATA_MUX_PROCESS_16;
-------------------------------------------------------------------------------
-- Write data path for 16 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_16: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "10" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
-- coverage off
when others =>
mem_be_i <= (others => '0');
-- coverage on
end case;
end process WRITE_BE_MUX_PROCESS_16;
WRITE_PARITY_EN_16_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
-- WRITE_PARITY_MUX_PROCESS_16: process(Parity_type, Addr_cnt, write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
-- --------------------
-- for i in 0 to 1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
---- ------------------
-- end process WRITE_PARITY_MUX_PROCESS_16;
WRITE_DATA_PARITY_PROCESS_16: process(Mem_width_bytes,
Addr_cnt,
write_data_cmb,
Parity_type,
write_data
) is
begin
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes(2 to 3) is
------------
when "01" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
--for j in 0 to 1 loop
write_data_parity_cmb(0) <=
--calc_parity(write_data_cmb((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
--end loop;
--end if;
--end loop;
------------
when "10" => -- 16 bit memory (need only two Parity Enable bits to active)
for i in 0 to 1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
--for j in 0 to 1 loop
--write_data_parity_cmb(j) <=
--calc_parity(write_data_cmb((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--end loop;
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
--end if;
end loop;
------------
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
------------
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_16;
-- for j in 0 to 1 loop
-- write_data_parity_cmb(j)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end loop;
end generate WRITE_PARITY_EN_16_MAX;
end generate WRITE_DATABE_MUX_16_GEN;
-------------------------------------------------------------------------------
-- Write data byte enable generation for 8 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_8_GEN: if C_MAX_MEM_WIDTH=8 generate
begin
-------------------------------------------------------------------------------
-- Write data path for 8 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_8: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
--------------
case Mem_width_bytes(3) is
when '1' =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
-- coverage off
when others =>
write_data_cmb <= (others => '0');
-- coverage on
end case;
---------------
end process WRITE_DATA_MUX_PROCESS_8;
-------------------------------------------------------------------------------
-- Write data path for 8 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_8: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
--------------------------
case Mem_width_bytes(3) is
when '1' =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
-- coverage off
when others =>
mem_be_i <= (others => '0');
-- coverage on
end case;
--------------------------
end process WRITE_BE_MUX_PROCESS_8;
WRITE_PARITY_EN_8_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
WRITE_PARITY_MUX_PROCESS_8: process(Parity_type,
Addr_cnt,
write_data_parity_cmb,
write_data_cmb
) is
begin
write_data_parity_cmb <= (others => '0');
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_parity_cmb (0) <=
calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);--(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
--end if;
--end loop;
end process WRITE_PARITY_MUX_PROCESS_8;
end generate WRITE_PARITY_EN_8_MAX;
end generate WRITE_DATABE_MUX_8_GEN;
end generate WRITE_DATABE_MUX_GEN;
-------------------------------------------------------------------------------
-- When all the memory banks has same data width as OPB/MCH data width,
-- data steering logic is not required.
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 ------------------------
-------------------------------------------------------------------------------
WRITE_DATABE_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
write_data_cmb <= write_data(0 to C_MAX_MEM_WIDTH-1);
mem_be_i <= Bus2IP_BE(0 to C_MAX_MEM_WIDTH/8-1);
---------**--
WRITE_PARITY_EN : if (C_PARITY_TYPE_MEMORY/=0) generate
begin
WRITE_PARITY: process(Parity_type,
write_data_cmb
) is
begin
for i in 0 to C_MAX_MEM_WIDTH/8 -1 loop
write_data_parity_cmb (i)<= calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
end process WRITE_PARITY;
end generate WRITE_PARITY_EN;
---------**--
end generate WRITE_DATABE_GEN;
-------------------------------------------------------------------------------
-- Write data generation for synchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_WRITE_DATA : if C_GLOBAL_SYNC_MEM = 1 generate
begin
-------------------------------------------------------------------------------
-- Write data pipeline process is used to pipeline write_data_cmb.
-------------------------------------------------------------------------------
WRITE_DATA_PIPE_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
write_data_d1 <= (others => '0');
write_data_d2 <= (others => '0');
Read_req_ack_reg <= '0';
else
write_data_d1 <= write_data_cmb;
write_data_d2 <= write_data_d1;
Read_req_ack_reg <= Read_req_ack;
end if;
end if;
end process WRITE_DATA_PIPE_PROCESS;
-- PARITY_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
-- begin
---------------------------------------------------------------------------
-- Write Parity pipeline process is used to pipeline write_data_cmb
---------------------------------------------------------------------------
WRITE_PARITY_PIPE_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
write_data_parity_d1 <= (others => '0');
write_data_parity_d2 <= (others => '0');
else
write_data_parity_d1 <= write_data_parity_cmb;
write_data_parity_d2 <= write_data_parity_d1;
end if;
end if;
end process WRITE_PARITY_PIPE_PROCESS;
-- end generate PARITY_GEN;
-------------------------------------------------------------------------------
-- Write data process is used to multiplex the write data on the memory
-- depending on the type of memory.
-------------------------------------------------------------------------------
WRITE_DATA_PROCESS: process(write_data_cmb, Synch_mem, Two_pipe_delay,
write_data_parity_cmb, write_data_parity_d2,
write_data_parity_d1, write_data_d1,
write_data_d2)
begin
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
MemSteer_Mem_DQ_O <= write_data_d2;
MemSteer_Mem_DQ_prty_O <= write_data_parity_d2;
else
MemSteer_Mem_DQ_O <= write_data_d1;
MemSteer_Mem_DQ_prty_O <= write_data_parity_d1;
end if;
else
MemSteer_Mem_DQ_O <= write_data_cmb;
MemSteer_Mem_DQ_prty_O <= write_data_parity_cmb;
end if;
end process WRITE_DATA_PROCESS;
end generate SYNC_MEM_WRITE_DATA;
-------------------------------------------------------------------------------
-- Memory write data generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_WRITE_DATA : if C_GLOBAL_SYNC_MEM = 0 generate
begin
MemSteer_Mem_DQ_O <= write_data_cmb;
MemSteer_Mem_DQ_prty_O <= write_data_parity_cmb;
end generate ASYNC_MEM_WRITE_DATA;
-------------------------------------------------------------------------------
-- Memory data bus high impedance buffer control.
-------------------------------------------------------------------------------
mem_dq_t_cmb(0) <= MSM_Mem_WEN;
mem_dqt_t_async <= MSM_Mem_WEN and mem_dqt_t_d;
ASYNC_PARITY_MEM_WRITE: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
mem_dq_parity_t_cmb(0) <= MSM_Mem_WEN;
mem_dqt_parity_t_async <= MSM_Mem_WEN and mem_dqt_parity_t_d;
end generate ASYNC_PARITY_MEM_WRITE;
-------------------------------------------------------------------------------
-- Asynchronous memory DQT process is used to generate impedance control
-- signal.
-------------------------------------------------------------------------------
MEM_DQT_D_ASYNC_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
mem_dqt_t_d <= '1';
mem_dqt_parity_t_d <= '1';
else
mem_dqt_t_d <= MSM_Mem_WEN;
mem_dqt_parity_t_d <= MSM_Mem_WEN;
end if;
end if;
end process MEM_DQT_D_ASYNC_PROCESS;
-------------------------------------------------------------------------------
-- Impedance generation for synchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_DQT : if C_GLOBAL_SYNC_MEM = 1 generate
begin
REG_DQT_GEN : for i in 0 to 2 generate
begin
-------------------------------------------------------------------------------
-- FDS primitive is used for mem_dq_t_cmb pipe generation.
-------------------------------------------------------------------------------
DQT_REG: FDS
port map (
Q => mem_dq_t_cmb(i+1), --[out]
C => Clk, --[in]
D => mem_dq_t_cmb(i), --[in]
S => Rst --[in]
);
end generate REG_DQT_GEN;
-------------------------------------------------------------------------------
-- Memory dqt process is used to multiplex the impeadance control signal on to
-- the memory depending on the type of memory.
-------------------------------------------------------------------------------
MEM_DQT_PROCESS_SYNC: process(Synch_mem, Two_pipe_delay, mem_dq_t_cmb,
mem_dqt_t_async)
begin
MemSteer_Mem_DQ_T <= (others => '1');
for i in 0 to C_MAX_MEM_WIDTH-1 loop
if(Synch_mem = '1')then
if(Two_pipe_delay = '1')then
MemSteer_Mem_DQ_T(i) <= mem_dq_t_cmb(2);
else
MemSteer_Mem_DQ_T(i) <= mem_dq_t_cmb(1);
end if;
else
MemSteer_Mem_DQ_T(i) <= mem_dqt_t_async;
end if;
end loop;
end process MEM_DQT_PROCESS_SYNC;
SYNC_PARITY_MEM_WRITE_DQT: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
REG_DQT_PARITY_GEN : for i in 0 to 2 generate
begin
-------------------------------------------------------------------------------
-- FDS primitive is used for mem_dq_t_cmb pipe generation.
-------------------------------------------------------------------------------
DQT_REG: FDS
port map (
Q => mem_dq_parity_t_cmb(i+1), --[out]
C => Clk, --[in]
D => mem_dq_parity_t_cmb(i), --[in]
S => Rst --[in]
);
end generate REG_DQT_PARITY_GEN;
-------------------------------------------------------------------------------
-- Memory dqt process is used to multiplex the impeadance control signal on to
-- the memory depending on the type of memory.
-------------------------------------------------------------------------------
MEM_DQT_PARITY_PROCESS_SYNC: process(Synch_mem,
Two_pipe_delay,
mem_dq_parity_t_cmb,
mem_dqt_parity_t_async
) is
begin
MemSteer_Mem_DQ_prty_T <= (others => '1');
for i in 0 to C_MAX_MEM_WIDTH/8-1 loop
if(Synch_mem = '1')then
if(Two_pipe_delay = '1')then
MemSteer_Mem_DQ_prty_T(i) <= mem_dq_parity_t_cmb(2);
else
MemSteer_Mem_DQ_prty_T(i) <= mem_dq_parity_t_cmb(1);
end if;
else
MemSteer_Mem_DQ_prty_T(i) <= mem_dqt_parity_t_async;
end if;
end loop;
end process MEM_DQT_PARITY_PROCESS_SYNC;
end generate SYNC_PARITY_MEM_WRITE_DQT;
end generate SYNC_MEM_DQT;
-------------------------------------------------------------------------------
-- Impedance generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_DQT : if C_GLOBAL_SYNC_MEM = 0 generate
begin
-------------------------------------------------------------------------------
-- Memory dqt process is used to generate impeadance control signal on to
-- the memory.
-------------------------------------------------------------------------------
MEM_DQT_PROCESS_ASYNC: process(mem_dqt_t_async)
begin
for i in 0 to C_MAX_MEM_WIDTH-1 loop
MemSteer_Mem_DQ_T(i) <= mem_dqt_t_async;
end loop;
end process MEM_DQT_PROCESS_ASYNC;
-------------------------------------------------------------------------------
-- Memory PARITY dqt process is used to generate impeadance control signal on
-- to the memory.
-------------------------------------------------------------------------------
ASYNC_PARITY_MEM_WRITE_DQT: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
MEM_PARITY_DQT_PROCESS_ASYNC: process(mem_dqt_parity_t_async)
begin
for i in 0 to C_MAX_MEM_WIDTH/8-1 loop
MemSteer_Mem_DQ_prty_T(i) <= mem_dqt_parity_t_async;
end loop;
end process MEM_PARITY_DQT_PROCESS_ASYNC;
end generate ASYNC_PARITY_MEM_WRITE_DQT;
end generate ASYNC_MEM_DQT;
-------------------------------------------------------------------------------
-- Read data path.
-- Read data and byte enable generation.
-------------------------------------------------------------------------------
RDDATA_GEN: for j in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH - 1 generate
begin
RDDATA_BYTE_GEN:for i in 0 to C_MIN_MEM_WIDTH - 1 generate
begin
-------------------------------------------------------------------------------
-- FDCE primitive is used for latching read_data when read_data_ce = 1.
-------------------------------------------------------------------------------
RDDATA_REG: FDRE
port map (
Q => Mem2Bus_Data(C_MIN_MEM_WIDTH*j+i), --[out]
C => Clk, --[in]
CE => read_data_ce(j), --[in]
D => read_data(C_MIN_MEM_WIDTH*j+i), --[in]
R => RST --[in]
);
end generate RDDATA_BYTE_GEN;
end generate RDDATA_GEN;
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 ------------------------
-------------------------------------------------------------------------------
RDDATA_PATH_GEN : if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
read_data <= MemSteer_Mem_DQ_I;
read_data_ce <= (others=>'1');
READ_PARITY_EN : if (C_PARITY_TYPE_MEMORY/=0) generate
begin
READ_PARITY: process(MemSteer_Mem_DQ_I,
Parity_type,
read_ack_d,
MemSteer_Mem_DQ_prty_I
) is
begin
-- default assignment
--read_parity <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to C_MAX_MEM_WIDTH/8 -1 loop
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY;
end generate READ_PARITY_EN;
end generate RDDATA_PATH_GEN;
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 ------------------------
-------------------------------------------------------------------------------
RDDATA_PATH_MUX_GEN : if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_ADDR_CNT_GEN: if C_GLOBAL_SYNC_MEM = 1 generate
begin
-------------------------------------------------------------------------------
-- Address count pipeline process is used to pipeline address count.
-------------------------------------------------------------------------------
ADDR_CNT_PIPE_PROCESS_SYN: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
addr_cnt_d3 <= (others => '0');
addr_cnt_d4 <= (others => '0');
else
if Bus2IP_RdReq = '1' or single_transaction = '1' then
addr_cnt_d1 <= Addr_cnt;
addr_cnt_d2 <= addr_cnt_d1;
addr_cnt_d3 <= addr_cnt_d2;
addr_cnt_d4 <= addr_cnt_d3;
else
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
addr_cnt_d3 <= (others => '0');
addr_cnt_d4 <= (others => '0');
end if;
end if;
end if;
end process ADDR_CNT_PIPE_PROCESS_SYN;
-------------------------------------------------------------------------------
-- Synchonous address counter process is used to multiplex the address counter
-- select signal depending on the type of memory.
-------------------------------------------------------------------------------
SYNC_ADDR_CNT_PROCESS: process(ns_idle,
Synch_mem,
Two_pipe_delay,
addr_cnt_d2,
addr_cnt_d3,
addr_cnt_d4)
begin
if (ns_idle='0') then
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
addr_cnt_sel <= addr_cnt_d4;
else
addr_cnt_sel <= addr_cnt_d3;
end if;
else
addr_cnt_sel <= addr_cnt_d2;
end if;
else
addr_cnt_sel <= (others => '0');
end if;
end process SYNC_ADDR_CNT_PROCESS;
---------------------------- Read Data Enable Logic ---------------------------
read_data_en_d(0) <= Read_data_en;
RDDATA_EN_GEN_SYNC: for i in 0 to 3 generate
begin
-------------------------------------------------------------------------------
-- FDR primitive is used for read_data_en_d pipe generation.
-------------------------------------------------------------------------------
RDDATA_EN_REG_SYNC: FDR
port map (
Q => read_data_en_d(i+1), --[out]
C => Clk, --[in]
D => read_data_en_d(i), --[in]
R => Rst --[in]
);
end generate RDDATA_EN_GEN_SYNC;
-------------------------------------------------------------------------------
-- Read data enable select process is used to multiplex the read data enable
-- depending on the type of memory.
-------------------------------------------------------------------------------
READ_DATA_EN_SEL_PROCESS: process(read_data_en_d, Synch_mem,
Two_pipe_delay)
begin
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
read_data_en_sel <= read_data_en_d(3);
else
read_data_en_sel <= read_data_en_d(2);
end if;
else
read_data_en_sel <= read_data_en_d(1);
end if;
end process READ_DATA_EN_SEL_PROCESS;
end generate SYNC_ADDR_CNT_GEN;
-------------------------------------------------------------------------------
-- Address count select generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_ADDR_CNT_GEN: if C_GLOBAL_SYNC_MEM = 0 generate
begin
-------------------------------------------------------------------------------
-- Address count pipeline process is used to pipeline address count.
-------------------------------------------------------------------------------
ADDR_CNT_PIPE_PROCESS_ASYNC: process(Clk)
begin
if Clk'event and Clk = '1' then
if ((Rst = '1') or (ns_idle='1')) then
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
else
addr_cnt_d1 <= Addr_cnt;
addr_cnt_d2 <= addr_cnt_d1;
end if;
end if;
end process ADDR_CNT_PIPE_PROCESS_ASYNC;
addr_cnt_sel <= addr_cnt_d2;
---------------------------- Read Data Enable Logic ---------------------------
read_data_en_d(0) <= Read_data_en;
read_data_en_sel <= read_data_en_d(1);
RDDATA_EN_GEN_ASYNC: for i in 0 to 3 generate
begin
-------------------------------------------------------------------------------
-- FDR primitive is used for read_data_en_d pipe generation.
-------------------------------------------------------------------------------
RDDATA_EN_REG_ASYNC: FDR
port map (
Q => read_data_en_d(i+1), --[out]
C => Clk, --[in]
D => read_data_en_d(i), --[in]
R => Rst --[in]
);
end generate RDDATA_EN_GEN_ASYNC;
end generate ASYNC_ADDR_CNT_GEN;
-------------------------------------------------------------------------------
-- Read Data CE generation For 64 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_64_GEN: if C_IPIF_DWIDTH = 64 generate
begin
--signal test :std_logic_vector(0 downto 7);
--test <= read_data_ce(conv_integer(addr_cnt_sel)*4+i);
-------------------------------------------------------------------------------
-- Read data CE process is used to generate read data chip enable for 64 Bit
-- DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_PROCESS_64: process(read_data_en_sel,
addr_cnt_sel,
single_transaction,
Bus2IP_RdReq,
Mem_width_bytes,
Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack,
addr_cnt_numonyx
) is
begin
read_data_ce <= (others => '0');
if Bus2IP_RdReq = '1' or single_transaction = '1' then
case Mem_width_bytes is
when "0001" =>
read_data_ce(conv_integer(addr_cnt_sel))
<= read_data_en_sel;
when "0010" =>
for i in 0 to 1 loop
--read_data_ce(conv_integer(addr_cnt_sel)*2+i)
-- <= read_data_en_sel;
if(Linear_flash_brst_rd_flag = '0') then
read_data_ce(conv_integer(addr_cnt_sel)*2+i)
<= read_data_en_sel;
else
read_data_ce(conv_integer(addr_cnt_numonyx)*2+i)
<= Linear_flash_rd_data_ack;--read_data_en_sel;
end if;
end loop;
when "0100" =>
for i in 0 to 3 loop
read_data_ce(conv_integer(addr_cnt_sel)*4+i)
<= read_data_en_sel;
end loop;
when "1000" =>
for i in 0 to 7 loop
read_data_ce(i) <= read_data_en_sel;
end loop;
-- coverage off
when others =>
read_data_ce <= (others => '0');
-- coverage on
end case;
end if;
end process READ_DATA_CE_PROCESS_64;
end generate READ_DATA_CE_64_GEN;
-------------------------------------------------------------------------------
-- Read data CE generation For 32 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_32_GEN: if C_IPIF_DWIDTH = 32 generate
begin
-------------------------------------------------------------------------------
-- Read data CE process is used to generate read data chip enable for 32 Bit
-- DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_PROCESS_32: process(Mem_width_bytes,
addr_cnt_sel,
addr_cnt_numonyx,
read_data_en_sel,
Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack
) is
begin
read_data_ce <= (others => '0');
case Mem_width_bytes is
when "0001" =>
read_data_ce(conv_integer(addr_cnt_sel))
<= read_data_en_sel ; -- and not(Linear_flash_brst_rd_flag)) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);
when "0010" =>
for i in 0 to 1 loop
if(Linear_flash_brst_rd_flag = '0') then
read_data_ce(conv_integer(addr_cnt_sel)*2+i)
<= read_data_en_sel;
else
read_data_ce(conv_integer(addr_cnt_numonyx)*2+i)
<= Linear_flash_rd_data_ack;--read_data_en_sel;
end if;
end loop;
when "0100" =>
for i in 0 to 3 loop
read_data_ce(i) <= read_data_en_sel ;--and not(Linear_flash_brst_rd_flag)) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);--read_data_en_sel;
end loop;
-- coverage off
when others =>
read_data_ce <= (others => '0');
-- coverage on
end case;
end process READ_DATA_CE_PROCESS_32;
end generate READ_DATA_CE_32_GEN;
-------------------------------------------------------------------------------
-- Read Data Path For 64 Bit Maximum Memory Width.
-------------------------------------------------------------------------------
READ_DATA_64_GEN: if (C_MAX_MEM_WIDTH=64 and C_IPIF_DWIDTH=64) generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 64 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_64_64: process(Mem_width_bytes, MemSteer_Mem_DQ_I )
begin
read_data <= (others => '0');
case Mem_width_bytes is
when "0001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "0010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
when "0100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
read_data(i*C_MIN_MEM_WIDTH*4 to
i*C_MIN_MEM_WIDTH*4+C_MIN_MEM_WIDTH*4-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*4-1);
end loop;
when "1000" =>
read_data <= MemSteer_Mem_DQ_I;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_64_64;
READ_PARITY_EN_64_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_PRTY_PROCESS_64: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes is
when "0001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "0010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
when "0100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
read_parity(i*C_MIN_MEM_WIDTH*4/8 to
i*C_MIN_MEM_WIDTH*4/8+C_MIN_MEM_WIDTH*4/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*4/8-1);
end loop;
when "1000" =>
read_parity <= MemSteer_Mem_DQ_prty_I;
when others =>
read_parity <= (others => '0');
end case;
end process READ_PRTY_PROCESS_64;
READ_PARITY_MUX_PROCESS_64: process(MemSteer_Mem_DQ_I,
Parity_type,
Bus2IP_BE,
read_ack_d,
MemSteer_Mem_DQ_prty_I)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 7 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I
(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH
+ C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_64;
end generate READ_PARITY_EN_64_MAX;
end generate READ_DATA_64_GEN;
-------------------------------------------------------------------------------
-- Read data path For 32 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_32_GEN: if (C_MAX_MEM_WIDTH=32) generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 32 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_32: process(Mem_width_bytes, MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
when "100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4)-1 loop
read_data(i*C_MIN_MEM_WIDTH*4 to
i*C_MIN_MEM_WIDTH*4+C_MIN_MEM_WIDTH*4-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*4-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_32;
READ_PARITY_EN_32_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_PRTY_PROCESS_32: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
when "100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*4/8 to
i*C_MIN_MEM_WIDTH*4/8+C_MIN_MEM_WIDTH*4/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*4/8-1);
end loop;
-- coverage off
when others =>
read_parity <= (others => '0');
-- coverage on
end case;
end process READ_PRTY_PROCESS_32;
READ_PARITY_MUX_PROCESS_32: process(MemSteer_Mem_DQ_I,
Parity_type,
MemSteer_Mem_DQ_prty_I,
read_ack_d,
Bus2IP_BE)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 3 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I
(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH
+ C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_32;
end generate READ_PARITY_EN_32_MAX;
end generate READ_DATA_32_GEN;
-------------------------------------------------------------------------------
-- Read data path for 16 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_16_GEN: if C_MAX_MEM_WIDTH=16 generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 16 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_16: process(Mem_width_bytes, MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "10" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_16;
READ_PARITY_EN_16_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_DATA_PROCESS_16: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "10" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
-- coverage off
when others =>
read_parity <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_16;
READ_PARITY_MUX_PROCESS_16: process(MemSteer_Mem_DQ_I,
Parity_type,
MemSteer_Mem_DQ_prty_I,
read_ack_d,
Bus2IP_BE)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 1 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_16;
end generate READ_PARITY_EN_16_MAX;
end generate READ_DATA_16_GEN;
-------------------------------------------------------------------------------
-- Read data path for 8 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_8_GEN: if C_MAX_MEM_WIDTH=8 generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 8 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_8: process(Mem_width_bytes,
MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(3) is
when '1' =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_8;
READ_PARITY_EN_8_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_DATA_PROCESS_8: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(3) is
when '1' =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when others =>
read_parity <= (others => '0');
end case;
end process READ_DATA_PROCESS_8;
READ_PARITY_MUX_PROCESS_8: process(MemSteer_Mem_DQ_I,
Parity_type,
Bus2IP_BE,
read_ack_d,
MemSteer_Mem_DQ_prty_I)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 0 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_8;
end generate READ_PARITY_EN_8_MAX;
end generate READ_DATA_8_GEN;
end generate RDDATA_PATH_MUX_GEN;
end imp;
-------------------------------------------------------------------------------
-- End of file mem_steer.vhd.
-------------------------------------------------------------------------------
|
gpl-3.0
|
e15f4ea6b3b6ebfb129a0076f4705e85
| 0.414193 | 4.226334 | false | false | false | false |
lowRISC/greth-library
|
greth_library/work/simple_soc2.vhd
| 2 | 10,639 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! @}
--! @name ADC channel A inputs (1575.4 GHz):
--! @{
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name ADC channel B inputs (1602 GHz):
--! @{
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name MAX2769 SPIs and antenna controls signals:
--! @{
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;
mst_cfg(CFG_NASTI_MASTER_CACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_CACHED) <= nasti_master_out_none;
mst_cfg(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip,
o_led => o_led
);
axiso(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => wReset,
i_clk => ib_gmiiclk,
o_clk => eth_i.gtx_clk,
o_clkp90 => eth_i.tx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
end arch_rocket_soc;
|
bsd-2-clause
|
f5de76f2bb3f97413e7fef07138a61a0
| 0.600244 | 3.294828 | false | false | false | false |
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