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BogdanArdelean/FPWAM
|
hardware/src/hdl/UnifyUnit.vhd
| 1 | 15,353 |
-------------------------------------------------------------------------------
-- FILE NAME : UnifyUnit.vhd
-- MODULE NAME : UnifyUnit
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that executes the unify(a1, a2) WAM ancillary operation
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity UnifyUnit is
generic
(
kAddressWidth : natural := kWamAddressWidth;
kWordWidth : natural := kWamWordWidth;
kPdlAddressWidth : natural := 10
);
port
(
clk : in std_logic;
rst : in std_logic;
start_unify : in std_logic;
word1 : in std_logic_vector(kWordWidth -1 downto 0);
word2 : in std_logic_vector(kWordWidth -1 downto 0);
mem1_input : in std_logic_vector(kWordWidth -1 downto 0);
mem2_input : in std_logic_vector(kWordWidth -1 downto 0);
deref1_input : in std_logic_vector(kWordWidth -1 downto 0);
deref1_done : in std_logic;
deref2_input : in std_logic_vector(kWordWidth -1 downto 0);
deref2_done : in std_logic;
bind_done : in std_logic;
unify_done : out std_logic;
fail : out std_logic;
mem1_output : out std_logic_vector(kAddressWidth -1 downto 0);
rd_mem_port1 : out std_logic;
mem2_output : out std_logic_vector(kAddressWidth -1 downto 0);
rd_mem_port2 : out std_logic;
deref1_output : out std_logic_vector(kWordWidth -1 downto 0);
deref1_start : out std_logic;
deref2_output : out std_logic_vector(kWordWidth -1 downto 0);
deref2_start : out std_logic;
bind1_output : out std_logic_vector(kWordWidth -1 downto 0);
bind2_output : out std_logic_vector(kWordWidth -1 downto 0);
bind_start : out std_logic;
mem_sel : out unify_mem_sel_t
);
end UnifyUnit;
architecture Behavioral of UnifyUnit is
type state_t is (idle_t, check_stop_pop_t, done_t, check_equal_read_t, deref_t, bind_t, push_list_t,
check_structure_t, check_structure_t2, structure_iterate_t);
signal cr_state, nx_state : state_t;
--Interface with PDL memory
signal pdl_in_1 : std_logic_vector(kWordWidth -1 downto 0);
signal pdl_in_2 : std_logic_vector(kWordWidth -1 downto 0);
signal pdl_out_1 : std_logic_vector(kWordWidth -1 downto 0);
signal pdl_out_2 : std_logic_vector(kWordWidth -1 downto 0);
signal pdl_adr_1 : std_logic_vector(kPdlAddressWidth -1 downto 0);
signal pdl_adr_2 : std_logic_vector(kPdlAddressWidth -1 downto 0);
signal wr_pdl : std_logic;
signal rd_pdl : std_logic;
signal pdl_addr_reg : std_logic_vector(kPdlAddressWidth -1 downto 0);
signal pdl_addr_comb : std_logic_vector(kPdlAddressWidth -1 downto 0);
signal wr_pdl_reg : std_logic;
signal pdl_empty : boolean;
signal fail_reg : std_logic;
signal fail_comb : std_logic;
signal reset_fail_reg : std_logic;
signal deref1_done_reg : std_logic;
signal deref2_done_reg : std_logic;
signal reset_deref_reg : std_logic;
signal iterate : std_logic;
signal iterate_done : std_logic;
signal current_reg : unsigned(kGPRAddressWidth downto 0);
signal wr_curr_reg : std_logic;
signal rst_curr_reg : std_logic;
signal goal_reg : unsigned(kGPRAddressWidth downto 0);
signal wr_goal_reg : std_logic;
signal mem1_input_reg : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem2_input_reg : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_reg_wr : std_logic;
signal local_reset : std_logic;
begin
fail <= fail_reg or fail_comb;
pdl_empty <= unsigned(pdl_addr_reg) = 0;
INPUTRGS: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or local_reset = '1' then
mem1_input_reg <= (others => '0');
mem2_input_reg <= (others => '0');
elsif mem_reg_wr = '1' then
mem1_input_reg <= mem1_input;
mem2_input_reg <= mem2_input;
end if;
end if;
end process;
PDLREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or local_reset = '1' then
pdl_addr_reg <= (others => '0');
elsif wr_pdl_reg = '1' then
pdl_addr_reg <= pdl_addr_comb;
end if;
end if;
end process;
PDLIST: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kPdlAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,addr_port_1 => pdl_adr_1
,word_port_1_o => pdl_out_1
,word_port_1_i => pdl_in_1
,wr_port_1 => wr_pdl
,rd_port_1 => rd_pdl
,addr_port_2 => pdl_adr_2
,word_port_2_o => pdl_out_2
,word_port_2_i => pdl_in_2
,wr_port_2 => wr_pdl
,rd_port_2 => rd_pdl
);
CURRERG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or rst_curr_reg = '1' or local_reset = '1' then
current_reg <= to_unsigned(1, kGPRAddressWidth+1);
elsif wr_curr_reg = '1' then
current_reg <= current_reg + 1;
end if;
end if;
end process;
GOALREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or local_reset = '1' then
goal_reg <= (others => '0');
elsif wr_goal_reg = '1' then
goal_reg <= "0" & unsigned(fpwam_arity(mem1_input_reg));
end if;
end if;
end process;
STR_IT: process(current_reg, goal_reg, iterate)
begin
iterate_done <= '0';
wr_curr_reg <= '0';
if iterate = '1' then
if current_reg > goal_reg then
iterate_done <= '1';
else
wr_curr_reg <= '1';
end if;
end if;
end process;
DEREFREGS: process(clk)
begin
if rising_edge(clk) then
if reset_deref_reg = '1' or rst = '1' or local_reset = '1' then
deref1_done_reg <= '0';
deref2_done_reg <= '0';
else
deref1_done_reg <= deref1_done or deref1_done_reg;
deref2_done_reg <= deref2_done or deref2_done_reg;
end if;
end if;
end process;
FAILREG: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' or reset_fail_reg = '1' or local_reset = '1' then
fail_reg <= '0';
else
fail_reg <= fail_comb or fail_reg;
end if;
end if;
end process;
FSM: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
cr_state <= idle_t;
else
cr_state <= nx_state;
end if;
end if;
end process;
NEXT_STATE: process(cr_state, start_unify, pdl_empty, fail_reg, deref1_done_reg,
deref2_done_reg, deref1_input, deref2_input, bind_done, mem1_input, mem2_input,
iterate_done, mem1_input_reg, mem2_input_reg)
begin
nx_state <= cr_state;
case cr_state is
when idle_t =>
if start_unify = '1' then
nx_state <= check_stop_pop_t;
end if;
when check_stop_pop_t =>
if not pdl_empty and fail_reg = '0' then
nx_state <= deref_t;
else
nx_state <= done_t;
end if;
when deref_t =>
if deref1_done_reg = '1' and deref2_done_reg = '1' then
nx_state <= check_equal_read_t;
end if;
when check_equal_read_t =>
if fpwam_value(deref1_input) = fpwam_value(deref2_input) then
nx_state <= check_stop_pop_t;
else
if fpwam_tag(deref1_input) = tag_ref_t or fpwam_tag(deref2_input) = tag_ref_t then
nx_state <= bind_t;
else
case fpwam_tag(deref2_input) is
when tag_int_t =>
nx_state <= check_stop_pop_t;
when tag_lis_t =>
if fpwam_tag(deref1_input) /= tag_lis_t then
nx_state <= check_stop_pop_t; -- move directly to end?
else
nx_state <= push_list_t;
end if;
when tag_str_t =>
if fpwam_tag(deref1_input) /= tag_str_t then
nx_state <= check_stop_pop_t; -- move directly to end?
else
nx_state <= check_structure_t;
end if;
when others =>
null;
end case;
end if;
end if;
when bind_t =>
if bind_done = '1' then
nx_state <= check_stop_pop_t;
end if;
when push_list_t =>
nx_state <= check_stop_pop_t;
when check_structure_t =>
nx_state <= check_structure_t2;
when check_structure_t2 =>
if fpwam_functor(mem1_input_reg) /= fpwam_functor(mem2_input_reg) or
fpwam_arity(mem1_input_reg) /= fpwam_arity(mem2_input_reg) then
nx_state <= check_stop_pop_t;
else
nx_state <= structure_iterate_t;
end if;
when structure_iterate_t =>
if iterate_done = '1' then
nx_state <= check_stop_pop_t;
end if;
when done_t =>
nx_state <= idle_t;
when others =>
null;
end case;
end process;
OUTPUT_DECODE: process(cr_state, pdl_out_1, pdl_out_2, start_unify, word1, word2, pdl_addr_reg, pdl_empty, fail_reg, deref1_done_reg,
deref2_done_reg, mem1_input, mem2_input, deref1_input, deref2_input, iterate_done, current_reg, mem1_input_reg, mem2_input_reg)
begin
-- Port outputs
unify_done <= '0';
fail_comb <= '0';
mem1_output <= (others => '0');
rd_mem_port1 <= '0';
mem2_output <= (others => '0');
rd_mem_port2 <= '0';
deref1_output <= (others => '0');
deref1_start <= '0';
deref2_output <= (others => '0');
deref2_start <= '0';
bind1_output <= (others => '0');
bind2_output <= (others => '0');
bind_start <= '0';
mem_sel <= sel_unify_t;
-- Internal control signals
pdl_in_1 <= (others => '0');
pdl_in_2 <= (others => '0');
wr_pdl <= '0';
rd_pdl <= '0';
pdl_addr_comb <= (others => '0');
pdl_adr_1 <= (others => '0');
pdl_adr_2 <= (others => '0');
wr_pdl_reg <= '0';
fail_comb <= '0';
reset_fail_reg <= '0';
reset_deref_reg<= '1';
iterate <= '0';
rst_curr_reg <= '0';
wr_goal_reg <= '0';
mem_reg_wr <= '0';
local_reset <= '0';
case cr_state is
when idle_t =>
if start_unify = '1' then
pdl_in_1 <= word1;
pdl_in_2 <= word2;
pdl_adr_1 <= pdl_addr_reg;
pdl_adr_2 <= std_logic_vector(unsigned(pdl_addr_reg) + 1);
wr_pdl <= '1';
rd_pdl <= '1';
pdl_addr_comb <= std_logic_vector(unsigned(pdl_addr_reg) + 2);
wr_pdl_reg <= '1';
reset_fail_reg <= '1';
end if;
when check_stop_pop_t =>
if not pdl_empty and fail_reg = '0' then
pdl_adr_1 <= std_logic_vector(unsigned(pdl_addr_reg) - 2);
pdl_adr_2 <= std_logic_vector(unsigned(pdl_addr_reg) - 1);
rd_pdl <= '1';
pdl_addr_comb <= std_logic_vector(unsigned(pdl_addr_reg) - 2);
wr_pdl_reg <= '1';
end if;
when deref_t =>
reset_deref_reg <= '0';
deref1_start <= '1' and not deref1_done_reg;
deref2_start <= '1' and not deref2_done_reg;
deref1_output <= pdl_out_1;
deref2_output <= pdl_out_2;
mem_sel <= sel_deref_t;
when check_equal_read_t =>
if (fpwam_tag(deref1_input) = tag_ref_t or fpwam_tag(deref2_input) = tag_ref_t)
and not(fpwam_value(deref1_input) = fpwam_value(deref2_input)) then
bind1_output <= deref1_input;
bind2_output <= deref2_input;
bind_start <= '1';
mem_sel <= sel_bind_t;
else
case fpwam_tag(deref2_input) is
when tag_int_t =>
if fpwam_value(deref1_input) /= fpwam_value(deref2_input) then
fail_comb <= '1';
else
fail_comb <= '0';
end if;
when tag_lis_t =>
if fpwam_tag(deref1_input) /= tag_lis_t then
fail_comb <= '1';
else
pdl_in_1 <= fpwam_word(std_logic_vector(fpwam_value(deref1_input)), tag_ref_t);
pdl_in_2 <= fpwam_word(std_logic_vector(fpwam_value(deref2_input)), tag_ref_t);
pdl_adr_1 <= pdl_addr_reg;
pdl_adr_2 <= std_logic_vector(unsigned(pdl_addr_reg) + 1);
wr_pdl <= '1';
rd_pdl <= '1';
pdl_addr_comb <= std_logic_vector(unsigned(pdl_addr_reg) + 2);
wr_pdl_reg <= '1';
end if;
when tag_str_t =>
if fpwam_tag(deref1_input) /= tag_str_t then
fail_comb <= '1';
else
mem1_output <= fpwam_value(deref1_input);
rd_mem_port1 <= '1';
mem2_output <= fpwam_value(deref2_input);
rd_mem_port2 <= '1';
mem_sel <= sel_unify_t;
end if;
when others =>
null;
end case;
end if;
when bind_t =>
mem_sel <= sel_bind_t;
when push_list_t =>
pdl_in_1 <= fpwam_word(std_logic_vector(unsigned(fpwam_value(deref1_input))+1), tag_ref_t);
pdl_in_2 <= fpwam_word(std_logic_vector(unsigned(fpwam_value(deref2_input))+1), tag_ref_t);
pdl_adr_1 <= pdl_addr_reg;
pdl_adr_2 <= std_logic_vector(unsigned(pdl_addr_reg) + 1);
wr_pdl <= '1';
rd_pdl <= '1';
pdl_addr_comb <= std_logic_vector(unsigned(pdl_addr_reg) + 2);
wr_pdl_reg <= '1';
when check_structure_t =>
mem_reg_wr <= '1';
when check_structure_t2 =>
if fpwam_functor(mem1_input_reg) /= fpwam_functor(mem2_input_reg) or
fpwam_arity(mem1_input_reg) /= fpwam_arity(mem2_input_reg) then
fail_comb <= '1';
else
rst_curr_reg <= '1';
wr_goal_reg <= '1';
iterate <= '1';
end if;
when structure_iterate_t =>
iterate <= '1';
if not iterate_done = '1' then
pdl_in_1 <= fpwam_word(std_logic_vector(unsigned(fpwam_value(deref1_input))+current_reg), tag_ref_t);
pdl_in_2 <= fpwam_word(std_logic_vector(unsigned(fpwam_value(deref2_input))+current_reg), tag_ref_t);
pdl_adr_1 <= pdl_addr_reg;
pdl_adr_2 <= std_logic_vector(unsigned(pdl_addr_reg) + 1);
wr_pdl <= '1';
rd_pdl <= '1';
pdl_addr_comb <= std_logic_vector(unsigned(pdl_addr_reg) + 2);
wr_pdl_reg <= '1';
end if;
when done_t =>
unify_done <= '1';
reset_fail_reg <= '1';
local_reset <= '1';
when others =>
null;
end case;
end process;
end Behavioral;
|
apache-2.0
|
08b261706977b6228d953e17fffe0c32
| 0.527063 | 3.290399 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/axi_interface.vhd
| 4 | 9,764 |
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_interface.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity axi_interface is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_interface;
architecture IMP of axi_interface is
component MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component MB_FDRE;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : MB_FDRE
generic map (
C_TARGET => C_TARGET)
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
|
gpl-3.0
|
4e7a0872e95113a4e7e28a5ba88591fe
| 0.5466 | 3.877681 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_clk_wiz.vhd
| 2 | 8,017 |
-- file: design_1_clk_wiz_1_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2____50.000______0.000______50.0______151.636_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity design_1_clk_wiz_1_0_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end design_1_clk_wiz_1_0_clk_wiz;
architecture xilinx of design_1_clk_wiz_1_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_design_1_clk_wiz_1_0 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_design_1_clk_wiz_1_0 : std_logic;
signal clkfbout_buf_design_1_clk_wiz_1_0 : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_design_1_clk_wiz_1_0 : std_logic;
signal clkout0b_unused : std_logic;
signal clk_out2_design_1_clk_wiz_1_0 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
signal reset_high : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_in1_design_1_clk_wiz_1_0,
I => clk_in1);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 10.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 20,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_design_1_clk_wiz_1_0,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_out1_design_1_clk_wiz_1_0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clk_out2_design_1_clk_wiz_1_0,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_design_1_clk_wiz_1_0,
CLKIN1 => clk_in1_design_1_clk_wiz_1_0,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => reset_high);
reset_high <= not resetn;
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_design_1_clk_wiz_1_0,
I => clkfbout_design_1_clk_wiz_1_0);
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_out1_design_1_clk_wiz_1_0);
clkout2_buf : BUFG
port map
(O => clk_out2,
I => clk_out2_design_1_clk_wiz_1_0);
end xilinx;
|
gpl-3.0
|
c11ef0288dda7b2a117da459e0a4a01f
| 0.568043 | 3.957058 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl_hs/AEAD_pkg.vhd
| 1 | 4,497 |
-------------------------------------------------------------------------------
--! @file AEAD_pkg.vhd
--! @brief Package used for authenticated encyryption
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! βunrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package AEAD_pkg is
--! =======================================================================
--! BDI Type Encoding for CipherCore (based on SegmentType(3 downto 1))
constant BDI_TYPE_ASS0 : std_logic_vector(3 -1 downto 0) := "000";
constant BDI_TYPE_ASS1 : std_logic_vector(3 -1 downto 0) := "001";
constant BDI_TYPE_DAT0 : std_logic_vector(3 -1 downto 0) := "010";
constant BDI_TYPE_DAT1 : std_logic_vector(3 -1 downto 0) := "011";
constant BDI_TYPE_TAG : std_logic_vector(3 -1 downto 0) := "100";
constant BDI_TYPE_LEN : std_logic_vector(3 -1 downto 0) := "101";
constant BDI_TYPE_NPUB : std_logic_vector(3 -1 downto 0) := "110";
constant BDI_TYPE_NSEC : std_logic_vector(3 -1 downto 0) := "111";
--! =======================================================================
--! Opcode (used by Pre- and Post-Processors)
constant OP_ENCDEC : std_logic_vector(3 -1 downto 0) := "001";
constant OP_ENC : std_logic_vector(4 -1 downto 0) := "0010";
constant OP_DEC : std_logic_vector(4 -1 downto 0) := "0011";
constant OP_LDKEY : std_logic_vector(4 -1 downto 0) := "0100";
constant OP_ACTKEY : std_logic_vector(4 -1 downto 0) := "0111";
--! =======================================================================
--! Status (used by Pre- and Post-Processors)
constant STAT_SUCCESS : std_logic_vector(4 -1 downto 0) := "1110";
constant STAT_FAILURE : std_logic_vector(4 -1 downto 0) := "1111";
--! =======================================================================
--! Segment Type Encoding (used by Pre- and Post-Processors)
--! 00XX
constant ST_A : std_logic_vector(2 -1 downto 0) := "00";
constant ST_AD : std_logic_vector(4 -1 downto 0) := "0001";
constant ST_NPUB_AD : std_logic_vector(4 -1 downto 0) := "0010";
constant ST_AD_NPUB : std_logic_vector(4 -1 downto 0) := "0011";
--! 01XX
constant ST_D : std_logic_vector(2 -1 downto 0) := "01";
constant ST_PT : std_logic_vector(4 -1 downto 0) := "0100";
constant ST_CT : std_logic_vector(4 -1 downto 0) := "0101";
constant ST_CT_TAG : std_logic_vector(4 -1 downto 0) := "0110";
--! 10XX
constant ST_TAG : std_logic_vector(4 -1 downto 0) := "1000";
constant ST_LEN : std_logic_vector(4 -1 downto 0) := "1010";
--! 11XX
constant ST_KEY : std_logic_vector(4 -1 downto 0) := "1100";
constant ST_NPUB : std_logic_vector(4 -1 downto 0) := "1101";
constant ST_NSEC : std_logic_vector(3 -1 downto 0) := "111";
constant ST_NSEC_PT : std_logic_vector(4 -1 downto 0) := "1110";
constant ST_NSEC_CT : std_logic_vector(4 -1 downto 0) := "1111";
--! =======================================================================
--! Functions
function log2_ceil (N: natural) return natural; --! Log(2) ceil
end AEAD_pkg;
package body AEAD_pkg is
--! Log of base 2
function log2_ceil (N: natural) return natural is
begin
if ( N = 0 ) then
return 0;
elsif N <= 2 then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
end package body AEAD_pkg;
|
apache-2.0
|
f5f1e2ff09fd4e0927f60909b305bd93
| 0.509455 | 3.739601 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/lmb_bram_if_funcs.vhd
| 4 | 8,212 |
-------------------------------------------------------------------------------
-- lmb_bram_if_funcs.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: lmb_bram_if_funcs.vhd
--
-- Description: Support functions for lmb_bram_if_cntlr
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package lmb_bram_if_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
VIRTEX7,
KINTEX7,
ARTIX7,
ZYNQ,
VIRTEXU,
KINTEXU,
ZYNQUE,
VIRTEXUM,
KINTEXUM,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
end package lmb_bram_if_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body lmb_bram_if_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
return VIRTEX7;
elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or
Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
return KINTEX7;
elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or
Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
return ARTIX7;
elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
return ZYNQ;
elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
return VIRTEXU;
elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or
Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
return KINTEXU;
elsif Equal_String(S, "zynque") then
return ZYNQUE;
elsif Equal_String(S, "virtexum") then
return VIRTEXUM;
elsif Equal_String(S, "kintexum") then
return KINTEXUM;
else
-- assert (false) report "No known target family" severity failure;
return RTL;
end if;
end function String_To_Family;
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
begin
return 6;
end function Family_To_LUT_Size;
end package body lmb_bram_if_funcs;
|
gpl-3.0
|
e2582fc4596f72eaa435f2c8a9fb76b4
| 0.560399 | 4.22428 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/a73caf46/hdl/src/vhdl/sync_fifo_fg.vhd
| 4 | 69,995 |
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the userΒs sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
gpl-3.0
|
6ee6ca8613f8d02e22fc482e35fa4947
| 0.42423 | 3.871833 | false | false | false | false |
hoangt/PoC
|
tb/fifo/fifo_cc_got_tb.vhdl
| 2 | 4,603 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO with Common Clock (cc) and Pipelined Interface
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
entity fifo_cc_got_tb is
end entity;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture tb of fifo_cc_got_tb is
-- component generics
constant D_BITS : positive := 8;
constant MIN_DEPTH : positive := 30;
constant ESTATE_WR_BITS : natural := 2;
constant FSTATE_RD_BITS : natural := 2;
-- Clock Control
signal rst : std_logic;
signal clk : std_logic := '0';
signal done : std_logic_vector(0 to 7) := (others => '0');
begin
clk <= not clk after 5 ns when done /= (done'range => '1') else '0';
rst <= '1', '0' after 10 ns;
genDUTs: for c in 0 to 7 generate
constant DATA_REG : boolean := c mod 2 > 0;
constant STATE_REG : boolean := c mod 4 > 1;
constant OUTPUT_REG : boolean := c mod 8 > 3;
-- Local Component Ports
signal put : std_logic;
signal din : std_logic_vector(D_BITS-1 downto 0);
signal full : std_logic;
signal estate_wr : std_logic_vector(ESTATE_WR_BITS - 1 downto 0);
signal got : std_logic;
signal dout : std_logic_vector(D_BITS-1 downto 0);
signal valid : std_logic;
signal fstate_rd : std_logic_vector(FSTATE_RD_BITS - 1 downto 0);
begin
DUT : entity PoC.fifo_cc_got
generic map (
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
STATE_REG => STATE_REG,
DATA_REG => DATA_REG,
OUTPUT_REG => OUTPUT_REG,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
rst => rst,
clk => clk,
put => put,
din => din,
full => full,
estate_wr => estate_wr,
got => got,
dout => dout,
valid => valid,
fstate_rd => fstate_rd
);
-- Writer
process
begin
din <= (others => '-');
put <= '0';
wait until rising_edge(clk) and rst = '0';
for i in 0 to 2**(D_BITS-1)-1 loop
din <= std_logic_vector(to_unsigned(i, D_BITS));
put <= '1';
wait until rising_edge(clk) and full = '0';
end loop;
for i in 2**(D_BITS-1) to 2**D_BITS-1 loop
din <= (others => '-');
put <= '0';
wait until rising_edge(clk) and valid = '0';
din <= std_logic_vector(to_unsigned(i, D_BITS));
put <= '1';
wait until rising_edge(clk);
end loop;
din <= (others => '-');
put <= '0';
wait; -- forever
end process;
-- Reader
process
begin
got <= '0';
for i in 0 to 2**D_BITS-1 loop
wait until rising_edge(clk) and valid = '1';
assert dout = std_logic_vector(to_unsigned(i, D_BITS))
report
"Output Failure in Configuration "&integer'image(c)&
" @ Pos "&integer'image(i)
severity failure;
got <= '1';
wait until rising_edge(clk);
got <= '0';
wait until rising_edge(clk);
end loop;
done(c) <= '1';
report "Test "&integer'image(c)&" completed." severity note;
wait; -- forever
end process;
end generate genDUTs;
end;
|
apache-2.0
|
a4836cbe8cf7404a8a1c9b9f8db2aeb6
| 0.525092 | 3.745321 | false | false | false | false |
hoangt/PoC
|
tb/misc/misc_bit_lz_tb.vhdl
| 2 | 4,204 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Testbench: Basic testbench for LZ-based bitstream compressor misc_bit_lz.
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------
-- Basic testbench for PoC.misc_bit_lz.
--
-- License:
-- ===========================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
entity misc_bit_lz_tb is
end entity;
use std.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture tb of misc_bit_lz_tb is
constant COUNT_BITS : positive := 7;
constant OFFSET_BITS : positive := 8;
constant DATA : std_logic_vector := x"72B6C9B5_25D92DCA_DB26DFFF";
component misc_bit_lz is
generic(
COUNT_BITS : positive;
OFFSET_BITS : positive
);
port(
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Data Input
din : in std_logic;
put : in std_logic;
flush : in std_logic;
-- Data Output
odat : out std_logic_vector(COUNT_BITS+OFFSET_BITS downto 0);
ostb : out std_logic
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal put : std_logic;
signal flush : std_logic;
signal odat : std_logic_vector(COUNT_BITS+OFFSET_BITS downto 0);
signal ostb : std_logic;
begin
DUT: misc_bit_lz
generic map (
COUNT_BITS => COUNT_BITS,
OFFSET_BITS => OFFSET_BITS
)
port map (
clk => clk,
rst => rst,
din => din,
put => put,
flush => flush,
odat => odat,
ostb => ostb
);
-- Stimuli
process
procedure cycle is
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end procedure cycle;
begin
rst <= '1';
cycle;
rst <= '0';
put <= '0';
flush <= '0';
cycle;
put <= '1';
for i in DATA'range loop
din <= DATA(i);
cycle;
end loop;
put <= '0';
flush <= '1';
cycle;
flush <= '0';
cycle;
cycle;
wait; -- forever
end process;
-- Output Parsing
process
variable l : line;
begin
wait until rising_edge(clk);
assert rst = '1' or not Is_X(ostb)
report "Unknown ostb output."
severity error;
if ostb = '1' then
if odat(odat'left) = '1' then
-- Literal
write(l, string'("L: "));
for i in odat'left-1 downto 0 loop
write(l, to_bit(odat(i)));
end loop;
elsif odat(odat'left-1 downto OFFSET_BITS) /= (1 to COUNT_BITS => '1') then
-- Repetition
write(l, string'("R: "));
write(l, to_integer(unsigned(odat(odat'left-1 downto OFFSET_BITS)))+COUNT_BITS+OFFSET_BITS);
write(l, string'(" @"));
write(l, to_integer(unsigned(odat(OFFSET_BITS-1 downto 0))));
else
-- End Marker
write(l, string'("E: "));
if odat(OFFSET_BITS-1) = '0' then
write(l, std_logic'image(odat(0)));
else
write(l, '<');
write(l, to_integer(unsigned(not odat(OFFSET_BITS-1 downto 0))));
end if;
end if;
writeline(output, l);
end if;
end process;
end architecture tb;
|
apache-2.0
|
8ccca3f4f3548733328361ecd76f3f5b
| 0.549952 | 3.73357 | false | false | false | false |
kevintownsend/convey_spmv
|
rtl/mac/InputIEEE_11_52_to_11_52.vhdl
| 1 | 2,829 |
--------------------------------------------------------------------------------
-- InputIEEE_11_52_to_11_52
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors: Florent de Dinechin (2008)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity InputIEEE_11_52_to_11_52 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(63 downto 0);
R : out std_logic_vector(11+52+2 downto 0) );
end entity;
architecture arch of InputIEEE_11_52_to_11_52 is
signal expX, expX_d1 : std_logic_vector(10 downto 0);
signal fracX : std_logic_vector(51 downto 0);
signal sX, sX_d1 : std_logic;
signal expZero, expZero_d1 : std_logic;
signal expInfty, expInfty_d1 : std_logic;
signal fracZero, fracZero_d1 : std_logic;
signal reprSubNormal, reprSubNormal_d1 : std_logic;
signal sfracX, sfracX_d1 : std_logic_vector(51 downto 0);
signal fracR : std_logic_vector(51 downto 0);
signal expR : std_logic_vector(10 downto 0);
signal infinity : std_logic;
signal zero : std_logic;
signal NaN : std_logic;
signal exnR : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
expX_d1 <= expX;
sX_d1 <= sX;
expZero_d1 <= expZero;
expInfty_d1 <= expInfty;
fracZero_d1 <= fracZero;
reprSubNormal_d1 <= reprSubNormal;
sfracX_d1 <= sfracX;
end if;
end process;
expX <= X(62 downto 52);
fracX <= X(51 downto 0);
sX <= X(63);
expZero <= '1' when expX = (10 downto 0 => '0') else '0';
expInfty <= '1' when expX = (10 downto 0 => '1') else '0';
fracZero <= '1' when fracX = (51 downto 0 => '0') else '0';
reprSubNormal <= fracX(51);
-- since we have one more exponent value than IEEE (field 0...0, value emin-1),
-- we can represent subnormal numbers whose mantissa field begins with a 1
sfracX <= fracX(50 downto 0) & '0' when (expZero='1' and reprSubNormal='1') else fracX;
----------------Synchro barrier, entering cycle 1----------------
fracR <= sfracX_d1;
-- copy exponent. This will be OK even for subnormals, zero and infty since in such cases the exn bits will prevail
expR <= expX_d1;
infinity <= expInfty_d1 and fracZero_d1;
zero <= expZero_d1 and not reprSubNormal_d1;
NaN <= expInfty_d1 and not fracZero_d1;
exnR <=
"00" when zero='1'
else "10" when infinity='1'
else "11" when NaN='1'
else "01" ; -- normal number
R <= exnR & sX_d1 & expR & fracR;
end architecture;
|
apache-2.0
|
1313b564b6e2cb29bf0b3f8dcbb3fe1c
| 0.587487 | 3.340024 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_tx_agile.vhd
| 4 | 17,992 |
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_tx_agile.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_tx_agile is
generic (
C_RESET_ACTIVE : std_logic := '0'
);
port (
Tx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Mac2Rmii_tx_en : in std_logic;
Mac2Rmii_txd : in std_logic_vector(3 downto 0);
Mac2Rmii_tx_er : in std_logic;
Rmii2Mac_tx_clk : out std_logic;
------------------ RMII <--> PHY --------------------------------
Rmii2Phy_txd : out std_logic_vector(1 downto 0);
Rmii2Phy_tx_en : out std_logic
);
end rmii_tx_agile;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_tx_agile is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_CLK_L,
IDLE_CLK_H,
TX100_DIBIT_0_CLK_L,
TX100_DIBIT_1_CLK_H,
TX10_DIBIT_0_CLK_L0,
TX10_DIBIT_0_CLK_L1,
TX10_DIBIT_0_CLK_L2,
TX10_DIBIT_0_CLK_L3,
TX10_DIBIT_0_CLK_L4,
TX10_DIBIT_0_CLK_L5,
TX10_DIBIT_0_CLK_L6,
TX10_DIBIT_0_CLK_L7,
TX10_DIBIT_0_CLK_L8,
TX10_DIBIT_0_CLK_L9,
TX10_DIBIT_1_CLK_H0,
TX10_DIBIT_1_CLK_H1,
TX10_DIBIT_1_CLK_H2,
TX10_DIBIT_1_CLK_H3,
TX10_DIBIT_1_CLK_H4,
TX10_DIBIT_1_CLK_H5,
TX10_DIBIT_1_CLK_H6,
TX10_DIBIT_1_CLK_H7,
TX10_DIBIT_1_CLK_H8,
TX10_DIBIT_1_CLK_H9
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
signal mac2Rmii_tx_en_d : std_logic;
signal mac2Rmii_txd_d : std_logic_vector(3 downto 0);
signal mac2Rmii_tx_er_d : std_logic;
signal tx_in_reg_en : std_logic;
signal txd_dibit : std_logic;
signal txd_error : std_logic;
begin
------------------------------------------------------------------------------
-- TX_IN_REG_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
mac2Rmii_tx_en_d <= '0';
mac2Rmii_txd_d <= (others => '0');
mac2Rmii_tx_er_d <= '0';
elsif (tx_in_reg_en = '1') then
mac2Rmii_tx_en_d <= Mac2Rmii_tx_en;
mac2Rmii_txd_d <= Mac2Rmii_txd;
mac2Rmii_tx_er_d <= Mac2Rmii_tx_er;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_OUT_REG_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Phy_txd(0) <= '0';
Rmii2Phy_txd(1) <= '0';
Rmii2Phy_tx_en <= '0';
elsif (txd_dibit = '0') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(0) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(1) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
elsif (txd_dibit = '1') then
Rmii2Phy_txd(0) <= mac2Rmii_txd_d(2) xor txd_error;
Rmii2Phy_txd(1) <= mac2Rmii_txd_d(3) or txd_error;
Rmii2Phy_tx_en <= mac2Rmii_tx_en_d;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_CONTROL_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_CLK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- TX_CONTROL_NEXT_STATE_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
TX_CONTROL_NEXT_STATE_PROCESS : process (
present_state,
mac2Rmii_tx_er_d,
Tx_speed_100--new addition of signals
)
begin
case present_state is
when IDLE_CLK_L =>
next_state <= IDLE_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '0';
txd_error <= '0';
when IDLE_CLK_H =>
if (Tx_speed_100 = '1') then
next_state <= TX100_DIBIT_0_CLK_L;
else
next_state <= TX10_DIBIT_0_CLK_L0;
end if;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX100_DIBIT_0_CLK_L =>
next_state <= TX100_DIBIT_1_CLK_H;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= mac2Rmii_tx_er_d;
when TX100_DIBIT_1_CLK_H =>
next_state <= TX100_DIBIT_0_CLK_L;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= mac2Rmii_tx_er_d;
when TX10_DIBIT_0_CLK_L0 =>
next_state <= TX10_DIBIT_0_CLK_L1;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L1 =>
next_state <= TX10_DIBIT_0_CLK_L2;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L2 =>
next_state <= TX10_DIBIT_0_CLK_L3;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L3 =>
next_state <= TX10_DIBIT_0_CLK_L4;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L4 =>
next_state <= TX10_DIBIT_0_CLK_L5;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L5 =>
next_state <= TX10_DIBIT_0_CLK_L6;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L6 =>
next_state <= TX10_DIBIT_0_CLK_L7;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L7 =>
next_state <= TX10_DIBIT_0_CLK_L8;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L8 =>
next_state <= TX10_DIBIT_0_CLK_L9;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '0';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_0_CLK_L9 =>
next_state <= TX10_DIBIT_1_CLK_H0;
Rmii2Mac_tx_clk <= '0';
tx_in_reg_en <= '1';
txd_dibit <= '1';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H0 =>
next_state <= TX10_DIBIT_1_CLK_H1;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H1 =>
next_state <= TX10_DIBIT_1_CLK_H2;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H2 =>
next_state <= TX10_DIBIT_1_CLK_H3;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H3 =>
next_state <= TX10_DIBIT_1_CLK_H4;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H4 =>
next_state <= TX10_DIBIT_1_CLK_H5;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H5 =>
next_state <= TX10_DIBIT_1_CLK_H6;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H6 =>
next_state <= TX10_DIBIT_1_CLK_H7;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H7 =>
next_state <= TX10_DIBIT_1_CLK_H8;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H8 =>
next_state <= TX10_DIBIT_1_CLK_H9;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
when TX10_DIBIT_1_CLK_H9 =>
next_state <= TX10_DIBIT_0_CLK_L0;
Rmii2Mac_tx_clk <= '1';
tx_in_reg_en <= '0';
txd_dibit <= '0';
txd_error <= '0';
end case;
end process;
end simulation;
|
gpl-3.0
|
e11b498d11eda3901ba9e7e058168aa9
| 0.411572 | 4.014279 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/synth/design_1_mdm_1_0.vhd
| 2 | 62,907 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2;
USE mdm_v3_2.MDM;
ENTITY design_1_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC
);
END design_1_mdm_1_0;
ARCHITECTURE design_1_mdm_1_0_arch OF design_1_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "MDM,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mdm_1_0_arch : ARCHITECTURE IS "design_1_mdm_1_0,MDM,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "design_1_mdm_1_0,MDM,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mdm,x_ipVersion=3.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_JTAG_CHAIN=2,C_USE_BSCAN=0,C_USE_CONFIG_RESET=0,C_INTERCONNECT=2,C_MB_DBG_PORTS=1,C_USE_UART=0,C_DBG_REG_ACCESS=0,C_DBG_MEM_ACCESS=0,C_USE_CROSS_TRIGGER=0,C_TRACE_OUTPUT=0,C_TRACE_DATA_WIDTH=32,C_TRACE_CLK_FREQ_HZ=200000000,C_TRACE_CLK_OUT_PHASE=90,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_FREQ_HZ=100000000,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_THREAD_ID_WIDTH=1,C_DATA_SIZE=32,C_M_AXIS_DATA_WIDTH=32,C_M_AXIS_ID_WIDTH=7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END design_1_mdm_1_0_arch;
|
gpl-3.0
|
012d771416489bd83e1e095994614fd9
| 0.588424 | 2.823727 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/xor18.vhd
| 4 | 7,111 |
-------------------------------------------------------------------------------
-- xor18.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- xor18.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Using_RTL;
end architecture IMP;
|
gpl-3.0
|
d5aaa6bbbf923ac0419ef8a349f77d27
| 0.528196 | 3.909291 | false | false | false | false |
wrousseau/a14-2-vhdl
|
Filter.vhd
| 1 | 2,245 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:18 10/20/2014
-- Design Name:
-- Module Name: filter - arc1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY Filter is
PORT ( clk : in STD_LOGIC;
R0 : in STD_LOGIC_VECTOR (31 downto 0);
R1 : in STD_LOGIC_VECTOR (31 downto 0);
R2 : in STD_LOGIC_VECTOR (31 downto 0);
R3 : out STD_LOGIC_VECTOR (31 downto 0)
);
end Filter;
architecture arc1 of Filter is
signal ready : STD_LOGIC := '0';
signal k0, k1, k2, k3, k4, k5, k6, k7, k8 : STD_LOGIC_VECTOR(7 downto 0);
signal result : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
COMPONENT Mask is
PORT (
ready : in STD_LOGIC;
k0, k1, k2, k3, k4, k5, k6, k7, k8 : in STD_LOGIC_VECTOR (7 downto 0);
result : out STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT Mask;
BEGIN theMask : Mask PORT MAP (
ready => ready,
result => result,
k0 => k0,
k1 => k1,
k2 => k2,
k3 => k3,
k4 => k4,
k5 => k5,
k6 => k6,
k7 => k7,
k8 => k8
);
PROCESS(R2) is
BEGIN
R3 <= (others=>'0');
for j in 3 downto 0 loop
k0 <= R0(j*8 + 7 downto j*8);
k1 <= R0(j*8 + 7 downto j*8);
k2 <= R0(j*8 + 7 downto j*8);
k3 <= R1(j*8 + 7 downto j*8);
k4 <= R1(j*8 + 7 downto j*8);
k5 <= R1(j*8 + 7 downto j*8);
k6 <= R2(j*8 + 7 downto j*8);
k7 <= R2(j*8 + 7 downto j*8);
k8 <= R2(j*8 + 7 downto j*8);
end loop;
END PROCESS;
PROCESS is
BEGIN
for j in 3 downto 0 loop
wait on result;
R3( j*8 + 7 downto j*8 ) <= result;
end loop;
END PROCESS;
end arc1;
|
apache-2.0
|
9016fef0c2f4d8507150f5298577c8c5
| 0.546548 | 2.827456 | false | false | false | false |
s-kostyuk/vhdl_samples
|
up_counter2/cnt.vhd
| 1 | 849 |
library IEEE;
use ieee.std_logic_1164.all;
entity cnt is
port(
rst: in std_logic;
clk: in std_logic;
T: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end entity;
architecture cnt of cnt is
component tc_trig is
port(T: in std_logic;
C: in std_logic;
R: in std_logic;
Q, notQ: out std_logic);
end component;
signal sQ: std_logic_vector(3 downto 0);
signal not_sQ: std_logic_vector(3 downto 0);
begin
tr0: tc_trig port map(C => clk, T => T, Q => sQ(0), notQ => not_sQ(0), R => rst);
tr1: tc_trig port map(C => not_sQ(0), T => T, Q => sQ(1), notQ => not_sQ(1), R => rst);
tr2: tc_trig port map(C => not_sQ(1), T => T, Q => sQ(2), notQ => not_sQ(2), R => rst);
tr3: tc_trig port map(C => not_sQ(2), T => T, Q => sQ(3), notQ => not_sQ(3), R => rst);
Q <= sQ;
end architecture;
|
mit
|
a71de1080aeab084cd28a8042f518177
| 0.564193 | 2.489736 | false | false | false | false |
hoangt/PoC
|
src/io/uart/uart_ft245.vhdl
| 1 | 7,680 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- ===========================================================================
--
-- Authors: Peter Reichel
-- Jan Schirok
-- Steffen Koehler
--
-- Module: UART controller for FTDI FT245M UART-over-USB converter.
--
-- License:
-- ===========================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity uart_ft245 is
generic (
CLK_FREQ : positive
);
port (
-- common signals
clk : in std_logic;
rst : in std_logic;
-- send data
snd_ready : out std_logic;
snd_strobe : in std_logic;
snd_data : in std_logic_vector(7 downto 0);
-- receive data
rec_strobe : out std_logic;
rec_data : out std_logic_vector(7 downto 0);
-- connection to ft245
ft245_data : inout std_logic_vector(7 downto 0);
ft245_rdn : out std_logic;
ft245_wrn : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic
);
end entity;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of uart_ft245 is
-- clock frequency (MHz)
constant CLK_FREQ_MHZ : integer := CLK_FREQ / 1000000;
-- FT245 communication delay cycles (minimum delay is 50 ns = 1/20 us)
constant DELAY_CYCLES : integer := CLK_FREQ_MHZ / 20;
-- delay register width
constant DELAY_WIDTH : integer := log2ceilnz(DELAY_CYCLES + 1);
-- delay register load value
constant DELAY_LOAD : unsigned(DELAY_WIDTH-1 downto 0) :=
to_unsigned(DELAY_CYCLES, DELAY_WIDTH);
-- delay register
signal reg_delay : unsigned(DELAY_WIDTH-1 downto 0);
-- FSM
type tState is ( IDLE, RD1, RD2, RD3, RD4, WR1, WR2, WR3, WR4 );
signal fsm_state : tState := IDLE;
signal fsm_nextstate : tState;
-- registers
signal reg_data_snd : std_logic_vector(7 downto 0);
signal reg_data_rec : std_logic_vector(7 downto 0);
signal reg_ld_rec : std_logic;
signal reg_dto_b : std_logic := '1'; -- low-active
signal reg_wr_b : std_logic := '1'; -- low-active
signal reg_rd_b : std_logic := '1'; -- low-active
signal ff_susp : std_logic := '1'; -- low-active
signal ff_rxf : std_logic := '1'; -- low-active
signal ff_txe : std_logic := '1'; -- low-active
-- control signals
signal ctrl_ld_rec : std_logic;
signal ctrl_delay : std_logic;
signal ctrl_rd : std_logic;
signal ctrl_wr : std_logic;
signal ctrl_dto : std_logic;
signal data_in : std_logic_vector(7 downto 0);
begin
----------------------------------------------
-- Synchronize Inputs
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- Neutral PowerUp / Reset
ff_susp <= '1';
ff_rxf <= '1';
ff_txe <= '1';
else
-- Wait for Initilization to Complete
ff_susp <= ft245_pwrenn;
-- Now forward Fill Signals
ff_rxf <= ft245_rxfn;
ff_txe <= ft245_txen;
end if;
end if;
end process;
process(fsm_state, snd_strobe, reg_delay, ff_susp, ff_rxf, ff_txe)
begin
fsm_nextstate <= fsm_state;
ctrl_ld_rec <= '0';
ctrl_rd <= '0';
ctrl_wr <= '0';
ctrl_dto <= '0';
ctrl_delay <= '0';
case fsm_state is
when IDLE =>
if ff_susp = '0' then
if ff_rxf = '0' then
-- receive data
fsm_nextstate <= RD1;
elsif ff_txe = '0' and snd_strobe = '1' then
-- ok, send...
fsm_nextstate <= WR1;
end if;
end if;
when RD1 =>
-- load delay counter
ctrl_rd <= '1';
ctrl_delay <= '1';
fsm_nextstate <= RD2;
when RD2 =>
-- wait until delay counter has expired
ctrl_rd <= '1';
if reg_delay = 0 then
fsm_nextstate <= RD3;
end if;
when RD3 =>
-- data is valid now => load
ctrl_rd <= '1';
ctrl_ld_rec <= '1';
-- load delay counter again
ctrl_delay <= '1';
fsm_nextstate <= RD4;
when RD4 =>
-- wait until delay counter has expired
if reg_delay = 0 then
fsm_nextstate <= IDLE;
end if;
when WR1 =>
-- load delay counter
ctrl_dto <= '1';
ctrl_delay <= '1';
fsm_nextstate <= WR2;
when WR2 =>
-- set wr (active pulse)
ctrl_dto <= '1';
ctrl_wr <= '1';
-- wait until delay counter has expired
if reg_delay = 0 then
fsm_nextstate <= WR3;
end if;
when WR3 =>
-- clear wr (pre-charge time)
ctrl_dto <= '1';
-- load delay counter again
ctrl_delay <= '1';
fsm_nextstate <= WR4;
when WR4 =>
-- wait until delay counter has expired
if reg_delay = 0 then
fsm_nextstate <= IDLE;
end if;
end case;
end process;
----------------------------------------------
-- registers
process(clk)
begin
if rising_edge(clk) then
-- control signals
if rst = '1' then
fsm_state <= IDLE;
reg_rd_b <= '1';
reg_wr_b <= '1';
reg_dto_b <= '1';
reg_ld_rec <= '0';
else
fsm_state <= fsm_nextstate;
reg_rd_b <= not ctrl_rd;
reg_wr_b <= not ctrl_wr;
reg_dto_b <= not ctrl_dto;
reg_ld_rec <= ctrl_ld_rec;
end if;
-- delay counter
if ctrl_delay = '1' then
reg_delay <= DELAY_LOAD;
else
reg_delay <= reg_delay - 1;
end if;
-- received data
if ctrl_ld_rec = '1' then
reg_data_rec <= data_in;
end if;
-- data to send
if snd_strobe = '1' then
reg_data_snd <= snd_data;
end if;
end if;
end process;
----------------------------------------------
-- tristate driver and output assignments
ft245_data <= reg_data_snd when reg_dto_b = '0' else (others => 'Z');
data_in <= ft245_data;
ft245_rdn <= reg_rd_b;
ft245_wrn <= reg_wr_b;
rec_data <= reg_data_rec;
rec_strobe <= reg_ld_rec;
snd_ready <= ff_rxf and not ff_txe and not ff_susp
when fsm_state = IDLE else '0';
end rtl;
|
apache-2.0
|
3e620aee7636296c10f44aec52e8f74b
| 0.496875 | 3.851555 | false | false | false | false |
Koppermann/mod-mul-mersenne
|
example/vhdl/dsp_mul.vhd
| 1 | 6,812 |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dsp_mul is
port(
clk: in std_ulogic;
a_i: in std_ulogic_vector(23 downto 0);
b_i: in std_ulogic_vector(16 downto 0);
p_o: out std_ulogic_vector(40 downto 0)
);
end dsp_mul;
architecture behav of dsp_mul is
signal a_lv: std_logic_vector(29 downto 0);
signal b_lv: std_logic_vector(17 downto 0);
signal p_lv: std_logic_vector(47 downto 0);
signal clk_lv: std_logic;
begin
a_lv <= std_logic_vector("000000" & a_i);
b_lv <= std_logic_vector('0'& b_i);
clk_lv <= clk;
DSP48E1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 0, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 0, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => p_lv, -- 48-bit output: Primary data output -- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => (others => '0'), -- 4-bit input: ALU control input
CARRYINSEL => (others => '0'), -- 3-bit input: Carry select input
CLK => clk_lv, -- 1-bit input: Clock input
INMODE => (others => '0'), -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => a_lv, -- 30-bit input: A data input
B => b_lv, -- 18-bit input: B data input
C => (others => '0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others => '0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '0', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '1', -- 1-bit input: Clock enable input for DREG
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
-- End of DSP48E1_inst instantiation
p_o <= std_ulogic_vector(p_lv(40 downto 0));
end behav;
|
mit
|
f69cd71806cb08bc47a3598986f287c6
| 0.586905 | 3.801339 | false | false | false | false |
hoangt/PoC
|
src/io/ddrio/ddrio.pkg.vhdl
| 2 | 3,249 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the PoC.io.ddrio namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
package ddrio is
component ddrio_in is
generic (
INIT_VALUES : BIT_VECTOR := ('1', '1');
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
i : in std_logic_vector(WIDTH-1 downto 0);
dh : out std_logic_vector(WIDTH-1 downto 0);
dl : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_out is
generic (
NO_OE : boolean := false;
INIT_VALUE : BIT := '1';
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
dh : in std_logic_vector(WIDTH-1 downto 0);
dl : in std_logic_vector(WIDTH-1 downto 0);
oe : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_in_xilinx is
generic (
INIT_VALUES : BIT_VECTOR := ('1', '1');
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
i : in std_logic_vector(WIDTH-1 downto 0);
dh : out std_logic_vector(WIDTH-1 downto 0);
dl : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_out_xilinx is
generic (
NO_OE : boolean := false;
INIT_VALUE : BIT := '1';
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
dh : in std_logic_vector(WIDTH-1 downto 0);
dl : in std_logic_vector(WIDTH-1 downto 0);
oe : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_out_altera is
generic (
INIT_VALUE : BIT := '1';
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
dh : in std_logic_vector(WIDTH-1 downto 0);
dl : in std_logic_vector(WIDTH-1 downto 0);
oe : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
end package;
|
apache-2.0
|
104022a08d4ba4ad27186ac23fc38cf9
| 0.580486 | 3.076705 | false | false | false | false |
JoseHawk/Signal_Generator
|
Generador de seΓ±ales/Generador_seniales.vhd
| 1 | 6,612 |
-- GENERADOR DE SENIALES
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Definimos la entidad
ENTITY Generador_seniales IS
PORT (
-- Entradas de las distintas opciones seleccionables y el reloj
reloj : IN STD_LOGIC;
formaOnda : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- Tomara valor 00 para senoidal, 01 para triangular y 10 para dientes de sierra
amplitud : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- Tomara valor 00 para 5 V, 01 para 2.5 V y 10 para 1.25
frecuencia : IN STD_LOGIC_VECTOR (1 DOWNTO 0);-- Tomara valor 00 para 100 Hz, 01 para 200 y 10 para 500
-- Convertidor D/A
AB : OUT STD_LOGIC; -- Seleccion de canal
D : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Palabra digital
CS : OUT STD_LOGIC; -- Activo en bajo
WR : OUT STD_LOGIC; -- Activo en bajo, escritura de palabra digital
CLR : OUT STD_LOGIC; -- Pone a 0 la palabra digital de ambos convertidores D/A, y la salida de ambos se pone a 0
LDAC : OUT STD_LOGIC -- Con un flanco descendente ambos convertidores toman el valor de los registros
);
END Generador_seniales;
-- Definimos la arquitectura
ARCHITECTURE arquitectura_Generador_seniales OF Generador_seniales IS
SIGNAL valorFormaOnda : INTEGER RANGE 0 TO 255; -- Posicion en la amplitud (tenemos 8 bits)
SIGNAL valorFormaOndaSeno : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Utilizado para obtener de la memoria el vector con el valor de la amplitud del seno
SIGNAL frecuenciaMuestreo : STD_LOGIC; -- Simula los pulsos de reloj segun la frecuencia seleccionada
SIGNAL valorAmplitud : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Para el valor de la amplitud
SIGNAL posicionMemoria : INTEGER RANGE 0 TO 255 :=0; -- Para la posicion de memoria en el seno
SIGNAL posicionMemoriaVector : STD_lOGIC_VECTOR (7 DOWNTO 0); -- Conversion a vector de la posicion de memoria para la ROM instanciada
-- Instanciamos la memoria del seno
COMPONENT ROM_Seno
PORT(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Mapeo de la memoria del seno
Memoria_Seno : ROM_Seno
PORT MAP (posicionMemoriaVector, -- Direccion de la memoria <= Address
frecuenciaMuestreo, -- Sincronizacion de acceso <= Inclock
valorFormaOndaSeno); -- Salida de la memoria <= q
-- Ponemos LDAC a 0 permanente y CLR a 1 permanente
LDAC <= '0';
CLR <= '1';
-- Seleccionamos el DAC
AB <= '0';
-- Sincronizamos CS y WR con nuestra frecuencia de muestreo
CS <= frecuenciaMuestreo;
WR <= frecuenciaMuestreo;
-- Escritura de la palabra digital
D <= valorAmplitud;
-- Proceso utilizado para obtener la posicion de la amplitud (valores desde 0 a 255), a los cuales ya le asignaremos
-- posteriormente en valor en voltios segun la amplitud seleccionada, en funcion de la forma de onda seleccionada
seleccionFormaOnda : PROCESS (formaOnda, frecuenciaMuestreo)
VARIABLE subida : STD_LOGIC := '1'; -- Para marcar la subida y bajada en las seniales
VARIABLE i : INTEGER RANGE 0 TO 255 := 0; -- Para ir contando los 255 valores de amplitud (8 bits)
BEGIN
IF frecuenciaMuestreo'EVENT AND frecuenciaMuestreo = '1' THEN
IF formaOnda = "00" THEN -- Si hemos seleccionado seno
posicionMemoria <= posicionMemoria + 1; -- Aumentamos en 1 la posicion de la memoria a leer y la pasamos a vector
posicionMemoriaVector <= conv_std_logic_vector(posicionMemoria,8);
valorFormaOnda <= conv_integer(valorFormaOndaSeno); -- Guardamos el valor obtenido de la memoria convertido a entero
END IF;
IF formaOnda = "01" THEN -- Si hemos seleccionado triangular
IF subida = '1' THEN -- Si subida esta activado
IF i >= 255 THEN -- Si hemos llegado a la maxima amplitud
subida := '0'; -- Activamos el descenso
ELSE
i := i + 1; -- En caso contrario, continuamos ascendiendo en amplitud
END IF;
ELSE -- Si bajada esta activado
IF i <= 0 THEN -- Si hemos llegado a la minima amplitud
subida := '1'; -- Activamos el ascenso
ELSE
i := i - 1; -- En caso contrario, continuamos descendiendo en amplitud
END IF;
END IF;
valorFormaOnda <= i; -- Almacenamos el valor
END IF;
IF formaOnda = "10" THEN -- Si hemos seleccionado triangular
IF i = 255 THEN -- Si hemos llegado a la maxima amplitud
i := 0; -- Bajamos al primer valor
ELSE
i := i + 1; -- En caso contrario continuamos ascendiendo
END IF;
valorFormaOnda <= i; -- Almacenamos el valor
END IF;
END IF;
END PROCESS;
-- Proceso para obtener la amplitud segun el valor de la senial de seleccion de amplitud y el valor de la muestra en la forma de onda
seleccionAmplitud : PROCESS (amplitud, valorFormaOnda)
VARIABLE valor : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
valor := conv_std_logic_vector (valorFormaOnda,8); -- Nuestro valor almacenado de la posicion de amplitud lo pasamos a vector
IF amplitud = "00" THEN -- Amplitud de 5 V
valorAmplitud <= valor (7 DOWNTO 0);
END IF;
IF amplitud = "01" THEN -- Amplitud de 2.5 V
valorAmplitud <= '0'&valor (7 DOWNTO 1);
END IF;
IF amplitud = "10" THEN -- Amplitud de 1.25 V
valorAmplitud <= "00"&valor (7 DOWNTO 2);
END IF;
END PROCESS;
-- Proceso para obtener la frecuencia segun el valor de la senial de seleccion de frecuencia de salida
seleccionFrecuencia : PROCESS (frecuencia)
VARIABLE maximoPulsos : INTEGER RANGE 0 TO 300000;
VARIABLE pulsos : INTEGER RANGE 0 TO 300000 := 0;
BEGIN
-- Seleccionamos el numero de pulsos necesario en nuestro reloj interno para que se produzca uno
-- en nuestra frecuencia de salida seleccionada
IF frecuencia = "00" THEN -- Frecuencia de 100 Hz
maximoPulsos := 492;
END IF;
IF frecuencia = "01" THEN -- Frecuencia de 200 Hz
maximoPulsos := 246;
END IF;
IF frecuencia = "10" THEN -- Frecuencia de 500 Hz
maximoPulsos := 98;
END IF;
-- Obtenemos la frecuencia de muestreo
IF reloj'EVENT AND reloj = '1' THEN
IF pulsos = maximoPulsos THEN
frecuenciaMuestreo <= NOT frecuenciaMuestreo;
pulsos := 0;
ELSE
pulsos := pulsos + 1;
END IF;
END IF;
END PROCESS;
END arquitectura_Generador_seniales;
|
gpl-2.0
|
e926c67e1094234ec3d78385b9ac0362
| 0.665003 | 3.577922 | false | false | false | false |
hoangt/PoC
|
src/mem/ocram/ocram_sp.vhdl
| 2 | 5,117 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Single-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating single-port RAM
--
-- - single clock, clock enable
-- - 1 read/write port
--
-- Written data is passed through the memory and output again as read-data 'q'.
-- This is the normal behaviour of a single-port RAM and also known as
-- write-first mode or read-through-write behaviour.
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocram_sp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates single-port memory as expected.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we = '1' then
ram(to_integer(a)) <= d;
end if;
a_reg <= a;
end if;
end if;
end process;
q <= ram(to_integer(a_reg)); -- gets new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we = '1' then
ram(to_integer(a)) <= d;
end if;
a_reg <= a;
end if;
end if;
end process;
q <= ram(to_integer(a_reg)); -- gets new data
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_sp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_sp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk => clk,
ce => ce,
we => we,
a => a,
d => d,
q => q
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
apache-2.0
|
a31a091d10493a9fb3cdfe51c59c211d
| 0.605433 | 3.244769 | false | false | false | false |
hoangt/PoC
|
src/arith/arith_sqrt.vhdl
| 2 | 3,744 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: Iterative Square Root Extractor.
-- Its computation requires (N+1)/2 steps for an argument bit width of N.
--
-- Authors: Thomas B. PreuΓer
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische UniversitΓ€t Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity arith_sqrt is
generic (
N : positive -- := 8 -- Bit Width of Argument
);
port (
-- Global Control
rst : in std_logic; -- Reset (synchronous)
clk : in std_logic; -- Clock
-- Inputs
arg : in std_logic_vector(N-1 downto 0); -- Radicand
start : in std_logic; -- Start Strobe
-- Outputs
sqrt : out std_logic_vector((N-1)/2 downto 0); -- Result
rdy : out std_logic -- Ready / Done
);
end arith_sqrt;
architecture rtl of arith_sqrt is
-- Number of Iteration Steps = Number of Result Digits
constant STEPS : positive := (N+1)/2;
-- Intern Registers
signal Rmd : unsigned(N+STEPS-1 downto 0); -- Remainder / Result
signal Vld : unsigned(STEPS-1 downto 0); -- Result Flags
signal Res : unsigned(STEPS-1 downto 0); -- Extracted Result
-- Tentative Difference
signal diff : unsigned(STEPS+1 downto 0);
begin -- rtl
-- Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- Only clear Ready, everything else: '-'
Rmd <= (others => '-');
Vld <= (others => '-');
Vld(Vld'left) <= '0';
else
if start = '1' then
-- Initilize Computation
Rmd <= (Rmd'left downto N => '0') & unsigned(arg);
Vld <= (others => '1');
elsif Vld(Vld'left) = '1' then
-- Computation Step
-- New Residue
Rmd(N-1 downto 0) <= Rmd(N-3 downto 0) & '-' & not diff(diff'left); -- just shift lower bits
if diff(diff'left) = '1' then
-- Sub failed: just shift upper Part
Rmd(Rmd'left downto N) <= Rmd(Rmd'left-2 downto N-2);
else
-- Sub succeeded: replace by shifted Difference
Rmd(Rmd'left downto N) <= diff(diff'left-2 downto 0);
end if;
-- Validate Result Digit
Vld <= Vld(Vld'left-1 downto 0) & '0';
end if;
end if;
end if;
end process;
-- Extract Result
genRes: for i in Res'range generate
Res(i) <= Rmd(2*i) and not Vld(i);
end generate;
-- Tentative Subtraction: 4*rmd - (4*res+1)
diff <= Rmd(Rmd'left downto N-2) + ('1' & not Res(STEPS-2 downto 0) & "11");
-- Ouputs
sqrt <= std_logic_vector(Res);
rdy <= not Vld(Vld'left);
end rtl;
|
apache-2.0
|
cca4e8f34a28b6560b8537b4c45bd03d
| 0.551042 | 3.668627 | false | false | false | false |
IAIK/ascon_hardware
|
asconv1/ascon_128_xlow_area/ascon_shift_register.vhdl
| 1 | 2,758 |
-------------------------------------------------------------------------------
-- Title : Ascon Shift Register
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_shift_register.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2014-05-20
-- Last update: 2014-05-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-20 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon_shift_register is
generic (
RESET_VALUE : std_logic_vector(63 downto 0) := x"0000000000000000";
DATA_WIDTH : integer := 64);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ShiftEnablexSI : in std_logic;
ShiftRegINxDI : in std_logic;
ShiftRegOUTxDO : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity ascon_shift_register;
architecture structural of ascon_shift_register is
signal DataxDP : std_logic_vector(DATA_WIDTH-1 downto 0);
begin -- architecture structural
ShiftRegOUTxDO <= DataxDP;
-- purpose: Left shift each cycle
-- type : sequential
-- inputs : ClkxCI, RstxRBI
-- outputs: DataOUTxDO
shift_p: process (ClkxCI, RstxRBI) is
begin -- process shift_p
if RstxRBI = '0' then -- asynchronous reset (active low)
DataxDP <= RESET_VALUE;
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if ShiftEnablexSI = '1' then
DataxDP <= DataxDP(DATA_WIDTH-2 downto 0) & ShiftRegINxDI; -- shift left
end if;
end if;
end process shift_p;
end architecture structural;
|
apache-2.0
|
163691aec2bbed533758cf8f458ab9a1
| 0.539521 | 4.682513 | false | false | false | false |
hoangt/PoC
|
src/misc/stat/stat_Maximum.vhdl
| 2 | 5,263 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Counts the most significant data words
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
entity stat_Maximum is
generic (
DEPTH : POSITIVE := 8;
DATA_BITS : POSITIVE := 16;
COUNTER_BITS : POSITIVE := 16
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Valids : out STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
Maximums : out T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0);
Counts : out T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0)
);
end entity;
architecture rtl of stat_Maximum is
type T_TAG_MEMORY is array(NATURAL range <>) of UNSIGNED(DATA_BITS - 1 downto 0);
type T_COUNTER_MEMORY is array(NATURAL range <>) of UNSIGNED(COUNTER_BITS - 1 downto 0);
-- create matrix from vector-vector
function to_slm(usv : T_TAG_MEMORY) return t_slm is
variable slm : t_slm(usv'range, DATA_BITS - 1 downto 0);
begin
for i in usv'range loop
for j in DATA_BITS - 1 downto 0 loop
slm(i, j) := usv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(usv : T_COUNTER_MEMORY) return t_slm is
variable slm : t_slm(usv'range, COUNTER_BITS - 1 downto 0);
begin
for i in usv'range loop
for j in COUNTER_BITS - 1 downto 0 loop
slm(i, j) := usv(i)(j);
end loop;
end loop;
return slm;
end function;
signal DataIn_us : UNSIGNED(DataIn'range);
signal TagHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal MaximumHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal TagMemory : T_TAG_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0'));
signal CounterMemory : T_COUNTER_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0'));
signal MaximumIndex : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := ((DEPTH - 1) => '1', others => '0');
signal ValidMemory : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := (others => '0');
begin
DataIn_us <= unsigned(DataIn);
genTagHit : for i in 0 to DEPTH - 1 generate
TagHit(i) <= to_sl(TagMemory(i) = DataIn_us);
MaximumHit(i) <= to_sl(TagMemory(i) < DataIn_us);
end generate;
process(Clock)
variable NewMaximum_nxt : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
variable NewMaximum_idx : NATURAL;
variable TagHit_idx : NATURAL;
begin
NewMaximum_nxt := MaximumIndex(MaximumIndex'high - 1 downto 0) & MaximumIndex(MaximumIndex'high);
NewMaximum_idx := to_index(onehot2bin(NewMaximum_nxt));
TagHit_idx := to_index(onehot2bin(TagHit));
if rising_edge(Clock) then
if (Reset = '1') then
ValidMemory <= (others => '0');
elsif ((slv_nand(ValidMemory) and slv_nor(TagHit) and Enable) = '1') then
for i in DEPTH - 1 downto 1 loop
if (MaximumHit(i) = '1') then
TagMemory(i) <= TagMemory(i - 1);
ValidMemory(i) <= ValidMemory(i - 1);
CounterMemory(i) <= CounterMemory(i - 1);
end if;
end loop;
for i in 0 to DEPTH - 1 loop
if (MaximumHit(i) = '1') then
TagMemory(i) <= DataIn_us;
ValidMemory(i) <= '1';
CounterMemory(i) <= to_unsigned(1, COUNTER_BITS);
exit;
end if;
end loop;
elsif ((slv_or(MaximumHit) and slv_nor(TagHit) and Enable) = '1') then
for i in DEPTH - 1 downto 1 loop
if (MaximumHit(i) = '1') then
TagMemory(i) <= TagMemory(i - 1);
ValidMemory(i) <= ValidMemory(i - 1);
CounterMemory(i) <= CounterMemory(i - 1);
end if;
end loop;
for i in 0 to DEPTH - 1 loop
if (MaximumHit(i) = '1') then
TagMemory(i) <= DataIn_us;
ValidMemory(i) <= '1';
CounterMemory(i) <= to_unsigned(1, COUNTER_BITS);
exit;
end if;
end loop;
elsif ((slv_or(TagHit) and Enable)= '1') then
CounterMemory(TagHit_idx) <= CounterMemory(TagHit_idx) + 1;
end if;
end if;
end process;
Valids <= ValidMemory;
Maximums <= to_slm(TagMemory);
Counts <= to_slm(CounterMemory);
end architecture;
|
apache-2.0
|
026705e9f56b74a653e772f277cd0010
| 0.605738 | 3.138342 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl/old/CipherCore_Control.vhd
| 1 | 10,068 |
-------------------------------------------------------------------------------
--! @file CipherCore_Control.vhd
--! @author Ekawat (ice) Homsirikamol
--! @brief Control unit for ASCON
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CipherCore_Control is
port (
clk : in std_logic;
rst : in std_logic;
--! Input
bdi : in std_logic_vector(64 -1 downto 0);
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(4 -1 downto 0);
--! Datapath
en_key : out std_logic;
en_state : out std_logic;
en_npub : out std_logic;
en_cmp : out std_logic;
is_last_ad : out std_logic;
clr_rc : out std_logic;
en_rc : out std_logic;
sel_key_hi : out std_logic;
sel_key_lo : out std_logic;
sel_decrypt : out std_logic;
sel_state : out std_logic_vector(2 -1 downto 0);
sel_tag : out std_logic_vector(2 -1 downto 0);
--! Output
msg_auth_done : out std_logic;
bdo_ready : in std_logic;
bdo_valid : out std_logic
);
end entity CipherCore_Control;
architecture behavior of CipherCore_Control is
type state_type is (S_WAIT_KEY, S_LD_KEY, S_LD_LEN,
S_LD_NPUB0, S_LD_NPUB1,
S_PROCESS, S_WAIT, S_WAIT_OUT_TAG2);
signal state : state_type;
signal nstate : state_type;
constant TOT_ROUND_HI : integer := 12;
constant TOT_ROUND_LO : integer := 6;
signal set_compute_hi : std_logic;
signal set_compute_lo : std_logic;
signal clr_last_ad : std_logic;
signal set_last_ad : std_logic;
signal clr_round : std_logic;
signal en_round : std_logic;
signal clr_tag : std_logic;
signal set_tag : std_logic;
signal is_tag : std_logic;
signal is_decrypt : std_logic;
signal rndcmp : std_logic_vector( 4 -1 downto 0);
signal round : std_logic_vector( 4 -1 downto 0);
begin
p_reg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
is_last_ad <= '0';
round <= (others => '0');
state <= S_WAIT_KEY;
is_tag <= '0';
is_last_ad <= '0';
sel_key_lo <= '0';
else
state <= nstate;
if (clr_round = '1') then
round <= (others => '0');
elsif (en_round = '1') then
round <= std_logic_vector(unsigned(round) + 1);
end if;
if (clr_last_ad = '1') then
is_last_ad <= '0';
elsif (set_last_ad = '1') then
is_last_ad <= '1';
end if;
if (set_compute_hi = '1') then
rndcmp <= std_logic_vector(to_unsigned((TOT_ROUND_HI-1), 4));
elsif (set_compute_lo = '1') then
rndcmp <= std_logic_vector(to_unsigned((TOT_ROUND_LO-1), 4));
end if;
if (clr_tag = '1' or set_tag = '1') then
sel_key_lo <= '1';
elsif (set_compute_lo = '1') then
sel_key_lo <= '0';
end if;
if (clr_tag = '1') then
is_tag <= '0';
elsif (set_tag = '1') then
is_tag <= '1';
end if;
if (state = S_LD_LEN) then
is_decrypt <= decrypt;
end if;
end if;
end if;
end process;
clr_rc <= clr_round;
en_rc <= en_round;
sel_key_hi <= set_tag;
sel_tag <= is_tag & round(0);
p_state:
process( state, bdi_valid, bdi_type, is_decrypt,
bdi_eot, bdo_ready, bdi, bdi_size,
key_valid, key_update, round, rndcmp, is_tag
)
begin
--! External
key_ready <= '0';
bdi_ready <= '0';
bdo_valid <= '0';
msg_auth_done <= '0';
--! Datapath
en_key <= '0';
en_state <= '0';
en_npub <= '0';
en_cmp <= '0';
set_compute_hi <= '0';
set_compute_lo <= '0';
sel_decrypt <= '0';
sel_state <= "00";
set_tag <= '0';
--! Internal
clr_round <= '0';
clr_tag <= '0';
clr_last_ad <= '0';
set_last_ad <= '0';
en_round <= '0';
nstate <= state;
case state is
when S_WAIT_KEY =>
clr_round <= '1';
clr_tag <= '1';
set_compute_hi <= '1';
if (key_update = '1' or bdi_valid = '1') then
if (key_update = '1') then
nstate <= S_LD_KEY;
else
nstate <= S_LD_LEN;
end if;
end if;
when S_LD_KEY =>
key_ready <= '1';
if (key_valid = '1') then
en_key <= '1';
en_round <= '1';
if (unsigned(round) = 3) then
nstate <= S_LD_LEN;
clr_round <= '1';
end if;
end if;
when S_LD_LEN =>
--! Determine if AD is empty
if (unsigned(bdi(63 downto 32)) = 0) then
set_last_ad <= '1';
else
clr_last_ad <= '1';
end if;
bdi_ready <= '1';
if (bdi_valid = '1') then
nstate <= S_LD_NPUB0;
end if;
when S_LD_NPUB0 =>
--! Store the first Npub block in the register
bdi_ready <= '1';
en_npub <= '1';
if (bdi_valid = '1') then
nstate <= S_LD_NPUB1;
end if;
when S_LD_NPUB1 =>
--! Get the second Npub and start processing
bdi_ready <= '1';
en_state <= '1';
sel_state <= "10";
if (bdi_valid = '1') then
nstate <= S_PROCESS;
end if;
when S_PROCESS =>
--! Process
en_round <= '1';
en_state <= '1';
if (round = rndcmp) then
clr_round <= '1';
nstate <= S_WAIT;
end if;
when S_WAIT =>
--! Load/Output data
sel_state <= "01";
if (is_tag = '1') then
if (is_decrypt = '0' and bdo_ready = '1') then
bdo_valid <= '1';
en_round <= '1';
nstate <= S_WAIT_OUT_TAG2;
elsif (is_decrypt = '1' and bdi_valid = '1') then
bdi_ready <= '1';
en_round <= '1';
en_cmp <= '1';
nstate <= S_WAIT_OUT_TAG2;
end if;
else
if (bdi_valid = '1'
and (bdi_type(2 downto 1) = "00"
or bdo_ready = '1'
or not unsigned(bdi_size) /= 0))
then
bdi_ready <= '1';
en_state <= '1';
if (bdi_type(2 downto 1) = "00") then
set_compute_lo <= '1';
if (bdi_eot = '1') then
set_last_ad <= '1';
end if;
else
if (unsigned(bdi_size) /= 0) then
bdo_valid <= '1';
end if;
clr_last_ad <= '1';
if (is_decrypt = '1'
and unsigned(bdi_size) /= 0)
then
sel_decrypt <= '1';
end if;
if (bdi_eot = '1') then
set_compute_hi <= '1';
set_tag <= '1';
else
set_compute_lo <= '1';
end if;
end if;
nstate <= S_PROCESS;
end if;
end if;
when S_WAIT_OUT_TAG2 =>
if (is_decrypt = '0') then
bdo_valid <= '1';
if (bdo_ready = '1') then
nstate <= S_WAIT_KEY;
end if;
else
bdi_ready <= '1';
if (bdi_valid = '1') then
msg_auth_done <= '1';
nstate <= S_WAIT_KEY;
end if;
end if;
end case;
end process;
end behavior;
|
apache-2.0
|
742019a34e8a59f13ef334ec4cea68b4
| 0.35002 | 4.224927 | false | false | false | false |
hoangt/PoC
|
tb/misc/sync/sync_Command_tb.vhdl
| 2 | 3,303 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: testbench for a command signal synchronizer
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Command_tb is
end;
architecture test of sync_Command_tb is
constant CLOCK_1_PERIOD : TIME := 10 ns;
constant CLOCK_2_PERIOD : TIME := 17 ns;
constant CLOCK_2_OFFSET : TIME := 2 ps;
signal Clock1 : STD_LOGIC := '1';
signal Clock2_i : STD_LOGIC := '1';
signal Clock2 : STD_LOGIC;
signal Sync_in : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal Sync_out : STD_LOGIC_VECTOR(1 downto 0);
signal Sync_Busy : STD_LOGIC;
signal Sync_Changed : STD_LOGIC;
begin
ClockProcess1 : process(Clock1)
begin
Clock1 <= not Clock1 after CLOCK_1_PERIOD / 2;
end process;
ClockProcess2 : process(Clock2_i)
begin
Clock2_i <= not Clock2_i after CLOCK_2_PERIOD / 2;
end process;
Clock2 <= Clock2_i'delayed(CLOCK_2_OFFSET);
process
begin
wait for 4 * CLOCK_1_PERIOD;
Sync_in <= "01";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "XX";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 2 * CLOCK_1_PERIOD;
Sync_in <= "01";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 6 * CLOCK_1_PERIOD;
Sync_in <= "10";
wait for 16 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "01";
wait for 1 * CLOCK_1_PERIOD;
Sync_in <= "00";
wait for 6 * CLOCK_1_PERIOD;
wait;
end process;
syncCmd : entity PoC.sync_Command
generic map (
BITS => 2, -- number of bit to be synchronized
INIT => "00" --
)
port map (
Clock1 => Clock1, -- input clock domain
Clock2 => Clock2, -- output clock domain
Input => Sync_in, -- input bits
Output => Sync_out, -- output bits
Busy => Sync_Busy, -- busy bits
Changed => Sync_Changed -- busy bits
);
end;
|
apache-2.0
|
be6e42f1a634957067d928605269f3d2
| 0.561913 | 3.28004 | false | false | false | false |
IAIK/ascon_hardware
|
asconv1/ascon_128_xlow_area/ascon_xlow_area.vhdl
| 1 | 26,812 |
-------------------------------------------------------------------------------
-- Title : A low-area implementation of Ascon, using shift registers
-- Project :
-- Description: Implements Ascon Encryption and Decryption with < 4kGE area
-- and a power consumption of 93 uW @ 4 MHz (WC, 25Β°C) for the
-- 90nm technology.
-------------------------------------------------------------------------------
-- File : ascon_low_area.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2014-05-20
-- Last update: 2014-05-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-20 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity ascon is
generic (
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic; -- active-high chip select
WExSI : in std_logic; -- active-high write enable
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity ascon;
architecture structural of ascon is
constant CONTROL_STATE_SIZE : integer := 4;
constant STATE_WORD_SIZE : integer := 64;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
-- Data path functions
constant FUNCTION_PREPARE : std_logic_vector(2 downto 0) := "000";
constant FUNCTION_SBOX : std_logic_vector(2 downto 0) := "001";
constant FUNCTION_LINLAYER0 : std_logic_vector(2 downto 0) := "010";
constant FUNCTION_LINLAYER1 : std_logic_vector(2 downto 0) := "011";
constant FUNCTION_LINLAYER2 : std_logic_vector(2 downto 0) := "100";
constant FUNCTION_LINLAYER3 : std_logic_vector(2 downto 0) := "101";
constant FUNCTION_LINLAYER4 : std_logic_vector(2 downto 0) := "110";
constant FUNCTION_POSTPROC : std_logic_vector(2 downto 0) := "111";
signal KeyxDP, KeyxDN : std_logic_vector(KEY_SIZE-1 downto 0);
signal IODataxDP, IODataxDN : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
signal DP_WriteNoncexS : std_logic;
signal DP_WriteIODataxS : std_logic;
signal CP_InitxSP, CP_InitxSN : std_logic;
signal CP_AssociatexSP, CP_AssociatexSN : std_logic;
signal CP_EncryptxSP, CP_EncryptxSN : std_logic;
signal CP_DecryptxSP, CP_DecryptxSN : std_logic;
signal CP_FinalAssociatexSP, CP_FinalAssociatexSN : std_logic;
signal CP_FinalEncryptxSP, CP_FinalEncryptxSN : std_logic;
signal CP_FinalDecryptxSP, CP_FinalDecryptxSN : std_logic;
signal CP_DonexSN, CP_DonexSP : std_logic;
signal SboxINxS : std_logic_vector(4 downto 0);
signal SboxOUTxS : std_logic_vector(4 downto 0);
signal CountEnablexS : std_logic;
signal CounterRoundxD : std_logic_vector(3 downto 0);
signal CounterFunctSelxD : std_logic_vector(2 downto 0);
signal CounterSubIterationxD : std_logic_vector(5 downto 0);
signal CounterResetxS : std_logic;
-- State and Temp registers
signal X0INxD, X1INxD, X2INxD, X3INxD, X4INxD, TempShiftRegINxD : std_logic;
signal X0OUTxD, X1OUTxD, X2OUTxD, X3OUTxD, X4OUTxD, TempShiftRegOUTxD : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal ShiftEnablexS : std_logic_vector (5 downto 0);
signal OverwriteENxS : std_logic;
signal OverwriteDataxS : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal ResetX0xSB : std_logic;
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ONES (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ONES
x := (others => '1');
return x;
end ONES;
begin -- architecture structural
---- Instances
-- State registers
x4: entity work.ascon_shift_register
generic map (
DATA_WIDTH => STATE_WORD_SIZE)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
ShiftEnablexSI => ShiftEnablexS(4),
ShiftRegINxDI => X4INxD,
ShiftRegOUTxDO => X4OUTxD);
x3: entity work.ascon_shift_register
generic map (
DATA_WIDTH => STATE_WORD_SIZE)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
ShiftEnablexSI => ShiftEnablexS(3),
ShiftRegINxDI => X3INxD,
ShiftRegOUTxDO => X3OUTxD);
x2: entity work.ascon_shift_register
generic map (
DATA_WIDTH => STATE_WORD_SIZE)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
ShiftEnablexSI => ShiftEnablexS(2),
ShiftRegINxDI => X2INxD,
ShiftRegOUTxDO => X2OUTxD);
x1: entity work.ascon_shift_register
generic map (
DATA_WIDTH => STATE_WORD_SIZE)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
ShiftEnablexSI => ShiftEnablexS(1),
ShiftRegINxDI => X1INxD,
ShiftRegOUTxDO => X1OUTxD);
x0: entity work.ascon_shift_register
generic map (
RESET_VALUE => CONST_KEY_SIZE & CONST_ROUNDS_A & CONST_ROUNDS_B & ZEROS(64-3*8),
DATA_WIDTH => STATE_WORD_SIZE)
port map (
ClkxCI => ClkxCI,
RstxRBI => ResetX0xSB,
ShiftEnablexSI => ShiftEnablexS(0),
ShiftRegINxDI => X0INxD,
ShiftRegOUTxDO => X0OUTxD);
-- Temp shift register
temp_shift_reg: entity work.ascon_shift_register_w_overwrite
generic map (
DATA_WIDTH => STATE_WORD_SIZE)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
OverwriteENxSI => OverwriteENxS,
OverwriteDataxSI => OverwriteDataxS,
ShiftEnablexSI => ShiftEnablexS(5),
ShiftRegINxDI => TempShiftRegINxD,
ShiftRegOUTxDO => TempShiftRegOUTxD);
-- Sbox
SboxINxS <= X4OUTxD(STATE_WORD_SIZE-1) & X3OUTxD(STATE_WORD_SIZE-1) & X2OUTxD(STATE_WORD_SIZE-1) & X1OUTxD(STATE_WORD_SIZE-1) & X0OUTxD(STATE_WORD_SIZE-1);
ascon_sbox5_1: entity work.ascon_sbox5
port map (
SboxINxDI => SboxINxS,
SboxOUTxDO => SboxOUTxS);
-- Counter
ascon_counter_1: entity work.ascon_counter
port map (
ClkxCI => ClkxCI,
RstxRBI => CounterResetxS,
CountEnablexSI => CountEnablexS,
CounterRoundxDO => CounterRoundxD,
CounterFunctSelxDO => CounterFunctSelxD,
CounterSubIterationxDO => CounterSubIterationxD);
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
KeyxDP <= (others => '0');
IODataxDP <= (others => '0');
CP_InitxSP <= '0';
CP_AssociatexSP <= '0';
CP_EncryptxSP <= '0';
CP_DecryptxSP <= '0';
CP_FinalAssociatexSP <= '0';
CP_FinalEncryptxSP <= '0';
CP_FinalDecryptxSP <= '0';
CP_DonexSP <= '1';
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
KeyxDP <= KeyxDN;
IODataxDP <= IODataxDN;
CP_InitxSP <= CP_InitxSN;
CP_AssociatexSP <= CP_AssociatexSN;
CP_EncryptxSP <= CP_EncryptxSN;
CP_DecryptxSP <= CP_DecryptxSN;
CP_FinalAssociatexSP <= CP_FinalAssociatexSN;
CP_FinalEncryptxSP <= CP_FinalEncryptxSN;
CP_FinalDecryptxSP <= CP_FinalDecryptxSN;
CP_DonexSP <= CP_DonexSN;
end if;
end process RegisterProc;
-- purpose: Glue the internal registers with the bus
-- type : combinational
DataBusLogicProc : process (AddressxDI, CP_AssociatexSP,
CP_DecryptxSP, CP_DonexSP, CP_EncryptxSP,
CP_FinalAssociatexSP, CP_FinalDecryptxSP,
CP_FinalEncryptxSP, CP_InitxSP, CSxSI,
DataWritexDI, IODataxDP, KeyxDP,
WExSI,
X3OUTxD,
X4OUTxD) is
variable AddressxDV : integer;
variable index : integer;
begin -- process DataBusLogicProc
KeyxDN <= KeyxDP;
AddressxDV := to_integer(unsigned(AddressxDI));
index := 0;
DataReadxDO <= (others => '0');
DP_WriteNoncexS <= '0';
DP_WriteIODataxS <= '0';
CP_InitxSN <= CP_InitxSP;
CP_AssociatexSN <= CP_AssociatexSP;
CP_EncryptxSN <= CP_EncryptxSP;
CP_DecryptxSN <= CP_DecryptxSP;
CP_FinalEncryptxSN <= CP_FinalEncryptxSP;
CP_FinalDecryptxSN <= CP_FinalDecryptxSP;
CP_FinalAssociatexSN <= CP_FinalAssociatexSP;
-- Reset signals when done with calculation
if CP_DonexSP = '1' then
CP_InitxSN <= '0';
CP_AssociatexSN <= '0';
CP_EncryptxSN <= '0';
CP_DecryptxSN <= '0';
CP_FinalEncryptxSN <= '0';
CP_FinalDecryptxSN <= '0';
CP_FinalAssociatexSN <= '0';
end if;
-- TODO: only designed for DATA_BUS_WIDTH=32
if CSxSI = '1' then
if WExSI = '1' then
-- synchronous write
if AddressxDV = 2 then
-- command register
CP_InitxSN <= DataWritexDI(0);
CP_AssociatexSN <= DataWritexDI(1);
CP_EncryptxSN <= DataWritexDI(2);
CP_DecryptxSN <= DataWritexDI(3);
CP_FinalEncryptxSN <= DataWritexDI(4);
CP_FinalDecryptxSN <= DataWritexDI(5);
CP_FinalAssociatexSN <= DataWritexDI(6);
elsif (AddressxDV >= 4) and (AddressxDV < 8) then
-- write the key
index := to_integer(unsigned(AddressxDI(1 downto 0)));
KeyxDN((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH) <= DataWritexDI;
elsif (AddressxDV >= 8) and (AddressxDV < 12) then
-- write the nonce
DP_WriteNoncexS <= '1';
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- write the data to de/encrypt and associated data
DP_WriteIODataxS <= '1';
end if;
else
-- asynchronous read
if AddressxDV = 0 then
DataReadxDO <= x"deadbeef";
elsif AddressxDV = 1 then
-- status register
-- returns 1 if busy
DataReadxDO(0) <= CP_InitxSP or CP_AssociatexSP or CP_FinalAssociatexSP or CP_EncryptxSP or CP_DecryptxSP or CP_FinalEncryptxSP or CP_FinalDecryptxSP;
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- read the de/encrypted data and associated data
index := to_integer(unsigned(AddressxDI(0 downto 0)));
DataReadxDO <= IODataxDP((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH);
elsif (AddressxDV >= 16) and (AddressxDV < 20) then
-- read the tag
if AddressxDI(1 downto 0) = "00" then
DataReadxDO <= X4OUTxD(31 downto 0);
elsif AddressxDI(1 downto 0) = "01" then
DataReadxDO <= X4OUTxD(63 downto 32);
elsif AddressxDI(1 downto 0) = "10" then
DataReadxDO <= X3OUTxD(31 downto 0);
else
DataReadxDO <= X3OUTxD(63 downto 32);
end if;
end if;
end if;
end if;
end process DataBusLogicProc;
-- purpose: Controlpath of Ascon
-- type : combinational
ControlProc : process (CP_AssociatexSP, CP_DecryptxSP, CP_DonexSP,
CP_EncryptxSP, CP_FinalAssociatexSP,
CP_FinalDecryptxSP, CP_FinalEncryptxSP, CP_InitxSP,
CounterFunctSelxD, CounterRoundxD,
CounterRoundxD(3 downto 0), CounterSubIterationxD,
IODataxDP,
KeyxDP,
RstxRBI, SboxOUTxS,
TempShiftRegOUTxD, X0OUTxD,
X1OUTxD,
X2OUTxD,
X3OUTxD,
X4OUTxD) is
variable RoundCounterxDV : integer;
variable RoundConstxDV : std_logic_vector(63 downto 0);
variable ZerosOnexDV : std_logic_vector(63 downto 0);
begin -- process ControlProc
RoundConstxDV := ZEROS(64-8) & not CounterRoundxD(3 downto 0) & CounterRoundxD(3 downto 0);
ZerosOnexDV := ZEROS(64-1) & '1';
RoundCounterxDV := to_integer(unsigned(CounterRoundxD));
CountEnablexS <= '0';
CounterResetxS <= '1';
ShiftEnablexS <= "000000";
ResetX0xSB <= RstxRBI;
---- State shift register input
X0INxD <= X0OUTxD(STATE_WORD_SIZE-1); -- Per default, shift MSB in
X1INxD <= X1OUTxD(STATE_WORD_SIZE-1);
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1);
X3INxD <= X3OUTxD(STATE_WORD_SIZE-1);
X4INxD <= X4OUTxD(STATE_WORD_SIZE-1);
TempShiftRegINxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1);
-- Enable counter when there is work to do
if (CP_DonexSP = '0') and ((CP_InitxSP = '1') or (CP_AssociatexSP = '1') or (CP_FinalAssociatexSP = '1') or
(CP_EncryptxSP = '1') or (CP_DecryptxSP = '1') or (CP_FinalEncryptxSP = '1') or (CP_FinalDecryptxSP = '1')) then
CountEnablexS <= '1';
end if;
-- Reset Counter when finished with work cycle
if (CP_DonexSP = '1') or (RstxRBI = '0') then
CounterResetxS <= '0'; -- active low
ShiftEnablexS <= "000000";
else
-- Function Select Multiplexers
if CounterFunctSelxD = FUNCTION_PREPARE then -- Preprocessing
if(RoundCounterxDV = 0) then -- Initialization
if (CP_InitxSP = '1') then
ResetX0xSB <= '0';
-- Prepare state k||a||b||0* (already done with reset) || K || N
ShiftEnablexS <= "111111";
X1INxD <= KeyxDP(to_integer(127 - unsigned('0' & CounterSubIterationxD)));
X2INxD <= KeyxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD))) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
X3INxD <= IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
X4INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1); --to_integer(63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_AssociatexSP = '1') or (CP_FinalAssociatexSP = '1') then
-- XOR Associate Data with X0
ShiftEnablexS(0) <= '1';
X0INxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Add Round Constant
ShiftEnablexS(2) <= '1';
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_EncryptxSP = '1') then
-- Shift in Plaintext => x0
ShiftEnablexS(0) <= '1';
X0INxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Shift Encryption result into Temp Register
ShiftEnablexS(5) <= '1';
TempShiftRegINxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Add Round Constant
ShiftEnablexS(2) <= '1';
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_DecryptxSP = '1') then
-- Shift in Cyphertext => x0
ShiftEnablexS(0) <= '1';
X0INxD <= IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Shift Decryption result into Temp Register
ShiftEnablexS(5) <= '1';
TempShiftRegINxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Add Round Constant
ShiftEnablexS(2) <= '1';
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_FinalEncryptxSP = '1') then
-- Shift in Plaintext => x0
ShiftEnablexS(0) <= '1';
X0INxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Shift Encryption result into Temp Register
ShiftEnablexS(5) <= '1';
TempShiftRegINxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Add Round Constant and Key
ShiftEnablexS(1) <= '1';
ShiftEnablexS(2) <= '1';
X1INxD <= X1OUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer(127 - unsigned('0' & CounterSubIterationxD)));
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD))) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_FinalDecryptxSP = '1') then
-- Shift in Cyphertext => x0
ShiftEnablexS(0) <= '1';
X0INxD <= IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Shift Decryption result into Temp Register
ShiftEnablexS(5) <= '1';
TempShiftRegINxD <= X0OUTxD(STATE_WORD_SIZE-1) xor IODataxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
-- Add Round Constant and Key
ShiftEnablexS(1) <= '1';
ShiftEnablexS(2) <= '1';
X1INxD <= X1OUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer(127 - unsigned('0' & CounterSubIterationxD)));
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer(63 - unsigned('0' & CounterSubIterationxD))) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
end if;
else
ShiftEnablexS(2) <= '1';
X2INxD <= X2OUTxD(STATE_WORD_SIZE-1) xor RoundConstxDV(to_integer(63 - unsigned('0' & CounterSubIterationxD)));
end if;
elsif CounterFunctSelxD = FUNCTION_SBOX then -- SBOX
ShiftEnablexS <= "011111"; -- Shift all registers except Temp
X0INxD <= SboxOUTxS(0);
X1INxD <= SboxOUTxS(1);
X2INxD <= SboxOUTxS(2);
X3INxD <= SboxOUTxS(3);
X4INxD <= SboxOUTxS(4);
elsif CounterFunctSelxD = FUNCTION_LINLAYER0 then -- Linear Layer X0
ShiftEnablexS(0) <= '1'; -- x0
ShiftEnablexS(5) <= '1'; -- temp <= x0 xor ...
TempShiftRegINxD <= X0OUTxD(STATE_WORD_SIZE-1) xor X0OUTxD(19 -1) xor X0OUTxD(28 -1);
elsif CounterFunctSelxD = FUNCTION_LINLAYER1 then -- Linear Layer X1
ShiftEnablexS(0) <= '1'; -- x0 <= temp
ShiftEnablexS(1) <= '1'; -- x1
ShiftEnablexS(5) <= '1'; -- temp <= x1 xor....
TempShiftRegINxD <= X1OUTxD(STATE_WORD_SIZE-1) xor X1OUTxD(61 -1) xor X1OUTxD(39 -1);
X0INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1);
elsif CounterFunctSelxD = FUNCTION_LINLAYER2 then -- Linear Layer X2
ShiftEnablexS(1) <= '1'; -- x1 <= temp
ShiftEnablexS(2) <= '1'; -- x2
ShiftEnablexS(5) <= '1'; -- temp <= x2 xor....
TempShiftRegINxD <= X2OUTxD(STATE_WORD_SIZE-1) xor X2OUTxD(1 -1) xor X2OUTxD(6 -1);
X1INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1);
elsif CounterFunctSelxD = FUNCTION_LINLAYER3 then -- Linear Layer X3
ShiftEnablexS(2) <= '1'; -- x2 <= temp
ShiftEnablexS(3) <= '1'; -- x3
ShiftEnablexS(5) <= '1'; -- temp <= x3 xor....
TempShiftRegINxD <= X3OUTxD(STATE_WORD_SIZE-1) xor X3OUTxD(10 -1) xor X3OUTxD(17 -1);
X2INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1);
elsif CounterFunctSelxD = FUNCTION_LINLAYER4 then -- Linear Layer X4
ShiftEnablexS(3) <= '1'; -- x3 <= temp
ShiftEnablexS(4) <= '1'; -- x4
ShiftEnablexS(5) <= '1'; -- temp <= x4 xor....
TempShiftRegINxD <= X4OUTxD(STATE_WORD_SIZE-1) xor X4OUTxD(7 -1) xor X4OUTxD(41 -1);
X3INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1);
elsif CounterFunctSelxD = FUNCTION_POSTPROC then -- Post Processing
ShiftEnablexS(4) <= '1'; -- x4 <= temp
ShiftEnablexS(5) <= '1';
X4INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1);
-- Add Key or Constants
if (CP_InitxSP = '1') and (RoundCounterxDV = ROUNDS_A-1) then
-- Add 0*||K
ShiftEnablexS(3) <= '1';
ShiftEnablexS(4) <= '1';
X3INxD <= X3OUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer(127 - unsigned('0' & CounterSubIterationxD)));
X4INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer( 63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_FinalAssociatexSP = '1') and (RoundCounterxDV = ROUNDS_B-1) then
-- Add 0* || 1
ShiftEnablexS(4) <= '1';
X4INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1) xor ZerosOnexDV(to_integer( 63 - unsigned('0' & CounterSubIterationxD)));
elsif (CP_FinalEncryptxSP = '1' or CP_FinalDecryptxSP = '1') and (RoundCounterxDV = ROUNDS_A-1) then
-- Add K => Tag
ShiftEnablexS(3) <= '1';
ShiftEnablexS(4) <= '1';
X3INxD <= X3OUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer(127 - unsigned('0' & CounterSubIterationxD)));
X4INxD <= TempShiftRegOUTxD(STATE_WORD_SIZE-1) xor KeyxDP(to_integer( 63 - unsigned('0' & CounterSubIterationxD)));
end if;
end if;
end if;
-- Done with calculation cycle
if ((CP_InitxSP = '1') or (CP_FinalEncryptxSP = '1') or (CP_FinalDecryptxSP = '1')) and (RoundCounterxDV = ROUNDS_A-1)
and CounterFunctSelxD = "111" and CounterSubIterationxD = "111111" then -- Finished
CP_DonexSN <= '1';
elsif ((CP_AssociatexSP = '1') or (CP_FinalAssociatexSP = '1') or (CP_EncryptxSP = '1') or (CP_DecryptxSP = '1')) and (RoundCounterxDV = ROUNDS_B-1)
and CounterFunctSelxD = "111" and CounterSubIterationxD = "111111" then -- Finished
CP_DonexSN <= '1';
else
CP_DonexSN <= '0';
end if;
end process ControlProc;
--purpose: Datapath of Ascon
--type : combinational
DatapathProc : process (AddressxDI(0), AddressxDI(1 downto 0), CP_DecryptxSP,
CP_EncryptxSP, CP_FinalDecryptxSP,
CP_FinalEncryptxSP, CounterFunctSelxD,
CounterRoundxD, CounterSubIterationxD,
DP_WriteIODataxS, DP_WriteNoncexS, DataWritexDI,
IODataxDP, TempShiftRegOUTxD,
TempShiftRegOUTxD(31 downto 0),
TempShiftRegOUTxD(63 downto 32)) is
-- Variables
begin -- process DatapathProc
---------------------------------------------------------------------------
-- part of bus interface
---------------------------------------------------------------------------
IODataxDN <= IODataxDP;
OverwriteENxS <= '0'; -- Controlls the temp registers overwrite function
OverwriteDataxS <= DataWritexDI & TempShiftRegOUTxD(31 downto 0);
-- Sample data when Encryption is selected
if((CP_EncryptxSP = '1') or (CP_FinalEncryptxSP = '1') or (CP_DecryptxSP = '1') or (CP_FinalDecryptxSP = '1')) then
if (CounterRoundxD = ZEROS(4)) and (CounterFunctSelxD = FUNCTION_SBOX) and (CounterSubIterationxD = ZEROS(6)) then
IODataxDN <= TempShiftRegOUTxD;
end if;
end if;
-- Write Nonce
if DP_WriteNoncexS = '1' then
if DATA_BUS_WIDTH = 32 then
if AddressxDI(1 downto 0) = "00" then
OverwriteENxS <= '1';
OverwriteDataxS <= TempShiftRegOUTxD(63 downto 32) & DataWritexDI;
elsif AddressxDI(1 downto 0) = "01" then
OverwriteENxS <= '1';
OverwriteDataxS <= DataWritexDI & TempShiftRegOUTxD(31 downto 0);
elsif AddressxDI(1 downto 0) = "10" then
IODataxDN(31 downto 0) <= DataWritexDI;
else
IODataxDN(63 downto 32) <= DataWritexDI;
end if;
else
-- TODO: implement for 16-bit, and 8-bit bus width
end if;
end if;
-- Write IO Data = Associated Data or Plain/Cypher
if DP_WriteIODataxS = '1' then
if DATA_BUS_WIDTH = 32 then
if AddressxDI(0) = '0' then
IODataxDN(31 downto 0) <= DataWritexDI;
else
IODataxDN(63 downto 32) <= DataWritexDI;
end if;
elsif DATA_BUS_WIDTH = 64 then
IODataxDN <= DataWritexDI;
else
-- TODO: implement for 16-bit, and 8-bit bus width
end if;
end if;
end process DatapathProc;
end architecture structural;
|
apache-2.0
|
f48a94664d92f0d85e1a7969f4940ce0
| 0.577316 | 4.215723 | false | false | false | false |
Rookfighter/aes-ss17
|
ex04/lcd.vhd
| 2 | 7,613 |
-- lcd.vhd
--
-- Created on: 14 May 2017
-- Author: Fabian Meyer
--
-- Component to write characters on the LCD display of the Spartan 6
-- FPGA.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lcd is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic_vector(7 downto 0); -- data in, 8 bit ASCII char
posx: in std_logic_vector(3 downto 0); -- x position within a line of LCD
posy: in std_logic; -- y position (line number)
flush: in std_logic; -- flush input, high active
rdy: out std_logic; -- ready, high active
en: out std_logic; -- enable, high active
rw: out std_logic;
rs: out std_logic;
bl: out std_logic; -- backlight, high active
data: inout std_logic_vector(3 downto 0)); -- data, dual direction
end entity;
architecture behavioral of lcd is
-- state for internal state machine of LCD screen
type TState is (SINIT, SREADY, SFLUSH);
signal state: TState := SINIT;
-- constants to define cycles per time unit
constant CLKPERMS: natural := 24000;
constant CLKPERUS: natural := 24;
-- counter for applying enable signal for 300ns (8 cycles)
constant ENCNTLEN: natural := 4;
signal en_cnt: std_logic_vector(ENCNTLEN-1 downto 0) := (others => '0');
-- counter for measuring time
constant CNTLEN: natural := 20;
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
-- instruction signal that splits into "rs + data"
signal ins: std_logic_vector(4 downto 0);
begin
-- carry bit of en_cnt defines enable signal
en <= en_cnt(ENCNTLEN-1);
-- map instruction signal to out ports
rs <= ins(4);
data <= ins(3 downto 0);
-- in commands used here rw always stays 0
rw <= '0';
bl <= '1';
process(rst, clk)
begin
if rst = RSTDEF then
state <= SINIT;
cnt <= (others => '0');
en_cnt <= (others => '0');
ins <= (others => '0');
rdy <= '0';
elsif rising_edge(clk) then
cnt <= cnt + 1;
-- always set enable to 0 again
-- enable will always only last 2**ENCNTLEN cycles
if en_cnt(ENCNTLEN-1) = '1' then
en_cnt <= en_cnt + 1;
end if;
case state is
-- init state computes initialization sequence
when SINIT =>
case conv_integer(cnt) is
when 0 =>
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00000";
when 20 * CLKPERMS =>
-- after 20ms
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00011";
when 30 * CLKPERMS =>
-- after 10ms
en_cnt(ENCNTLEN-1) <= '1';
when 30 * CLKPERMS + 100 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
when 30 * CLKPERMS + 200 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00010";
when 30 * CLKPERMS + 300 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
when 30 * CLKPERMS + 400 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "01100";
when 30 * CLKPERMS + 500 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00000";
when 30 * CLKPERMS + 600 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "01100";
when 30 * CLKPERMS + 700 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00000";
when 30 * CLKPERMS + 800 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00001";
when 40 * CLKPERMS + 800 * CLKPERUS =>
-- after 10ms
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00000";
when 40 * CLKPERMS + 900 * CLKPERUS =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "00110";
when 40 * CLKPERMS + 1000 * CLKPERUS - 1 =>
-- after 100us - 1 cycle
-- save a cycle, because we will stay at least 1
-- cycle in ready state before we set a new write
-- instruction
state <= SREADY;
rdy <= '1';
when others =>
end case;
-- READY state waits for a write command
when SREADY =>
if flush = '1' then
state <= SFLUSH;
rdy <= '0';
cnt <= (others => '0');
-- set already first instruction for writing data to save a cycle
en_cnt(ENCNTLEN-1) <= '1';
ins <= "01" & posy & "00";
end if;
-- FLUSH state writes current char din at position (posx/posy)
when SFLUSH =>
-- because enable signal was set when counter was reset
-- all times have to be decreased by one cycle
case conv_integer(cnt) is
when 100 * CLKPERUS - 1 =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "0" & posx;
when 200 * CLKPERUS - 1 =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "1" & din(7 downto 4);
when 300 * CLKPERUS - 1 =>
-- after 100us
en_cnt(ENCNTLEN-1) <= '1';
ins <= "1" & din(3 downto 0);
when 400 * CLKPERUS - 2 =>
-- after 100us - 1 cycle
-- save a cycle, because we will stay at least 1
-- cycle in ready state before we set a new write
-- instruction
state <= SREADY;
rdy <= '1';
when others =>
end case;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
e465a427b9a2b04adb28c8ad06270448
| 0.394063 | 5.088904 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_dmul_64ns_64ns_64_6_max_dsp.vhd
| 2 | 3,375 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dmul_64ns_64ns_64_6_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dmul_64ns_64ns_64_6_max_dsp is
--------------------- Component ---------------------
component feedforward_ap_dmul_4_max_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dmul_4_max_dsp_64_u : component feedforward_ap_dmul_4_max_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
cf43abc400dcd838f3c2158a2ea3c530
| 0.489778 | 3.511967 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_ddiv_29_no_dsp_64/synth/ANN_ap_ddiv_29_no_dsp_64.vhd
| 1 | 12,685 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_ddiv_29_no_dsp_64;
ARCHITECTURE ANN_ap_ddiv_29_no_dsp_64_arch OF ANN_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_ddiv_29_no_dsp_64_arch;
|
gpl-3.0
|
109d72dd5548822ff37eb24c0fb3c863
| 0.64935 | 3.000946 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward.vhd
| 1 | 183,322 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
P_config_V_TVALID : IN STD_LOGIC;
P_config_V_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
P_netOut_V_TVALID : OUT STD_LOGIC;
P_netOut_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=39,HLS_SYN_FF=8096,HLS_SYN_LUT=11564}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (148 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (148 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (148 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (148 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (148 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (148 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (148 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (148 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (148 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (148 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (148 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (148 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_8B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001011";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_5E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011110";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
constant ap_const_lv32_71 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_4A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001010";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_77 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110111";
constant ap_const_lv32_88 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001000";
constant ap_const_lv32_8A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001010";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_89 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001001";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_72 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110010";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_59 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011001";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv15_23 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv9_1FF : STD_LOGIC_VECTOR (8 downto 0) := "111111111";
constant ap_const_lv16_23 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000100011";
constant ap_const_lv9_1FE : STD_LOGIC_VECTOR (8 downto 0) := "111111110";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv14_23 : STD_LOGIC_VECTOR (13 downto 0) := "00000000100011";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (148 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_167 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode_V : STD_LOGIC_VECTOR (7 downto 0);
signal ST_numLayer_V : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_565 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_249 : BOOLEAN;
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_256 : BOOLEAN;
signal ap_sig_cseq_ST_st121_fsm_120 : STD_LOGIC;
signal ap_sig_bdd_264 : BOOLEAN;
signal ap_sig_cseq_ST_st140_fsm_139 : STD_LOGIC;
signal ap_sig_bdd_272 : BOOLEAN;
signal reg_572 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_281 : BOOLEAN;
signal ap_sig_cseq_ST_st89_fsm_88 : STD_LOGIC;
signal ap_sig_bdd_290 : BOOLEAN;
signal grp_fu_513_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_578 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_300 : BOOLEAN;
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_307 : BOOLEAN;
signal grp_fu_506_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_317 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_324 : BOOLEAN;
signal reg_589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_333 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_340 : BOOLEAN;
signal grp_fu_527_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_594 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_350 : BOOLEAN;
signal ap_sig_cseq_ST_st95_fsm_94 : STD_LOGIC;
signal ap_sig_bdd_357 : BOOLEAN;
signal grp_fu_544_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_599 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st39_fsm_38 : STD_LOGIC;
signal ap_sig_bdd_367 : BOOLEAN;
signal ap_sig_cseq_ST_st113_fsm_112 : STD_LOGIC;
signal ap_sig_bdd_374 : BOOLEAN;
signal grp_fu_524_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_605 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st76_fsm_75 : STD_LOGIC;
signal ap_sig_bdd_384 : BOOLEAN;
signal ap_sig_cseq_ST_st114_fsm_113 : STD_LOGIC;
signal ap_sig_bdd_391 : BOOLEAN;
signal P_mode_V_read_reg_1437 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_611_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_404 : BOOLEAN;
signal tmp_reg_1442 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_V_load_reg_1446 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_621_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1454 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_V_0_load_reg_1458 : STD_LOGIC_VECTOR (7 downto 0);
signal P_config_V_read_reg_1463 : STD_LOGIC_VECTOR (7 downto 0);
signal i_8_fu_638_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_428 : BOOLEAN;
signal exitcond1_fu_633_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_434 : BOOLEAN;
signal tmp_62_cast_fu_664_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_cast_reg_1479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_444 : BOOLEAN;
signal tmp_7_fu_649_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_668_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_6_reg_1484 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_16_fu_682_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_16_reg_1489 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_20_fu_688_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_20_reg_1494 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_fu_711_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_24_reg_1499 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_cast_fu_715_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_64_cast_reg_1506 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_26_fu_719_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_26_reg_1511 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_33_fu_729_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_reg_1516 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_fu_735_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_35_reg_1521 : STD_LOGIC_VECTOR (1 downto 0);
signal j_5_fu_762_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_474 : BOOLEAN;
signal tmp_19_fu_768_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_reg_1534 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_fu_756_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_815_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_60_reg_1540 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_1_reg_1546 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_821_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_fu_832_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_reg_1559 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_496 : BOOLEAN;
signal exitcond2_fu_827_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_534_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_30_reg_1579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st44_fsm_43 : STD_LOGIC;
signal ap_sig_bdd_516 : BOOLEAN;
signal grp_fu_539_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_reg_1584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st75_fsm_74 : STD_LOGIC;
signal ap_sig_bdd_525 : BOOLEAN;
signal tmp_15_fu_894_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_reg_1589 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_534 : BOOLEAN;
signal i_12_fu_917_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1598 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_923_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_23_reg_1603 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_974_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_64_reg_1609 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_3_reg_1615 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_985_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_reg_1623 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_555 : BOOLEAN;
signal exitcond3_fu_980_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_574 : BOOLEAN;
signal i_11_fu_1037_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_11_reg_1651 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st120_fsm_119 : STD_LOGIC;
signal ap_sig_bdd_583 : BOOLEAN;
signal p_uOut_addr_5_reg_1656 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond4_fu_1032_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_41_fu_1057_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_41_reg_1661 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_519_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_reg_1665 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st137_fsm_136 : STD_LOGIC;
signal ap_sig_bdd_601 : BOOLEAN;
signal ap_sig_cseq_ST_st139_fsm_138 : STD_LOGIC;
signal ap_sig_bdd_610 : BOOLEAN;
signal tmp_44_fu_1062_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_V_TREADY : STD_LOGIC;
signal tmp_74_fu_1095_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_reg_1683 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1099_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal next_mul_reg_1688 : STD_LOGIC_VECTOR (13 downto 0);
signal i_14_fu_1110_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_14_reg_1696 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_fu_1116_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_75_reg_1701 : STD_LOGIC_VECTOR (1 downto 0);
signal exitcond_fu_1105_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_reg_1706 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_56_fu_1197_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_reg_1712 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_654 : BOOLEAN;
signal p_netOut_V_1_fu_1203_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_663 : BOOLEAN;
signal i_15_fu_1210_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_7_fu_1239_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_7_reg_1730 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_674 : BOOLEAN;
signal tmp_59_fu_1233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_fu_1259_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_1740 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_689 : BOOLEAN;
signal tmp_61_cast_fu_1274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_cast_reg_1744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_1278_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_4_reg_1749 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_t_fu_1282_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_7_t_reg_1753 : STD_LOGIC_VECTOR (1 downto 0);
signal j_4_fu_1288_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_4_reg_1758 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_707 : BOOLEAN;
signal tmp_46_fu_1333_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_46_reg_1781 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_732 : BOOLEAN;
signal tmp_11_fu_1298_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1339_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_2_fu_1392_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_748 : BOOLEAN;
signal tmp_22_fu_1386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_755 : BOOLEAN;
signal exitcond5_fu_1398_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond5_reg_1799 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_765 : BOOLEAN;
signal ap_sig_bdd_769 : BOOLEAN;
signal i_7_fu_1403_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_277 : STD_LOGIC_VECTOR (7 downto 0);
signal i_3_reg_288 : STD_LOGIC_VECTOR (7 downto 0);
signal j_1_reg_300 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_800 : BOOLEAN;
signal sum_reg_311 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_323 : STD_LOGIC_VECTOR (7 downto 0);
signal sumsoft_reg_334 : STD_LOGIC_VECTOR (31 downto 0);
signal i_4_reg_346 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_357 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_369 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_380 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st138_fsm_137 : STD_LOGIC;
signal ap_sig_bdd_821 : BOOLEAN;
signal p_s_reg_391 : STD_LOGIC_VECTOR (7 downto 0);
signal p_netOut_V_reg_404 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_reg_416 : STD_LOGIC_VECTOR (7 downto 0);
signal phi_mul_reg_427 : STD_LOGIC_VECTOR (13 downto 0);
signal j_3_reg_438 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_847 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_461 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_layerSize_V_load_1_phi_reg_473 : STD_LOGIC_VECTOR (7 downto 0);
signal k_reg_484 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_495 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_fu_644_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_70_cast_fu_786_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_80_cast_fu_851_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_861_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_79_cast_fu_874_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_74_cast_fu_945_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_83_cast_fu_1004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_84_cast_fu_1014_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_cast_fu_1027_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_1052_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_1076_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_1090_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1254_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_78_cast_fu_1354_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_fu_1409_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_V_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st115_fsm_114 : STD_LOGIC;
signal ap_sig_bdd_963 : BOOLEAN;
signal grp_fu_506_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_987 : BOOLEAN;
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_994 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_1002 : BOOLEAN;
signal ap_sig_cseq_ST_st90_fsm_89 : STD_LOGIC;
signal ap_sig_bdd_1009 : BOOLEAN;
signal grp_fu_524_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_527_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_889_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_658_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_fu_658_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_3_fu_672_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_682_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_1_cast_fu_692_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_1_fu_695_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_705_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_fu_705_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_2_fu_723_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_739_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_fu_752_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_fu_781_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_791_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_fu_803_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_795_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_807_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast_fu_842_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_69_fu_846_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast7_fu_838_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_856_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_cast_fu_866_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_68_fu_869_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_35_to_int_fu_879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_neg_fu_883_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_907_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_cast_fu_936_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_61_fu_940_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_62_fu_950_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_63_fu_962_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_954_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_966_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_39_cast_fu_995_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_72_fu_999_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_39_cast6_fu_991_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_73_fu_1009_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_cast_fu_1019_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_fu_1022_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_42_cast_fu_1043_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_67_fu_1047_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_cast_fu_1067_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_76_fu_1071_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_47_cast_fu_1081_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1085_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal p_uOut_load_3_to_int_fu_1120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_to_int_fu_1138_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_48_fu_1124_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_fu_1134_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_1161_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_1141_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_1151_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs1_fu_1179_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1173_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_1167_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_53_fu_1185_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_1191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_55_fu_530_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_57_fu_1216_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_58_fu_1229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_fu_1245_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_fu_1249_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_1268_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_s_fu_1268_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_10_fu_1294_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_1304_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_42_fu_1309_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_45_fu_1321_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl_cast_fu_1313_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_1325_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_65_fu_1345_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_66_fu_1349_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_25_fu_1359_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_cast_fu_1372_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_1376_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_21_cast_fu_1382_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_ce : STD_LOGIC;
signal grp_fu_513_ce : STD_LOGIC;
signal grp_fu_519_ce : STD_LOGIC;
signal tmp_55_fu_530_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_534_ce : STD_LOGIC;
signal grp_fu_539_ce : STD_LOGIC;
signal grp_fu_544_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (148 downto 0);
signal tmp_16_fu_682_p10 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_5_fu_658_p10 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_s_fu_1268_p10 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_sig_bdd_724 : BOOLEAN;
signal ap_sig_bdd_942 : BOOLEAN;
component feedforward_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mux_4to1_sel2_8_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (7 downto 0);
din3 : IN STD_LOGIC_VECTOR (7 downto 0);
din4 : IN STD_LOGIC_VECTOR (7 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode_V : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode_V => P_mode_V);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 32,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0 : component feedforward_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_506_p0,
din1 => grp_fu_506_p1,
ce => grp_fu_506_ce,
dout => grp_fu_506_p2);
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1 : component feedforward_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => p_uOut_q0,
din1 => ST_WandB_q0,
ce => grp_fu_513_ce,
dout => grp_fu_513_p2);
feedforward_fdiv_32ns_32ns_32_16_U2 : component feedforward_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_565,
din1 => sumsoft_reg_334,
ce => grp_fu_519_ce,
dout => grp_fu_519_p2);
feedforward_fptrunc_64ns_32_1_U3 : component feedforward_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_524_p0,
dout => grp_fu_524_p1);
feedforward_fpext_32ns_64_1_U4 : component feedforward_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_527_p0,
dout => grp_fu_527_p1);
feedforward_fcmp_32ns_32ns_1_1_U5 : component feedforward_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_565,
din1 => p_uOut_load_4_reg_1706,
opcode => tmp_55_fu_530_opcode,
dout => tmp_55_fu_530_p2);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_599,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_534_ce,
dout => grp_fu_534_p2);
feedforward_ddiv_64ns_64ns_64_31_U7 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_30_reg_1579,
ce => grp_fu_539_ce,
dout => grp_fu_539_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_594,
ce => grp_fu_544_ce,
dout => grp_fu_544_p2);
feedforward_mux_4to1_sel2_8_1_U9 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_6_reg_1484,
dout => tmp_12_fu_739_p6);
feedforward_mux_4to1_sel2_8_1_U10 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_20_reg_1494,
dout => tmp_19_fu_768_p6);
feedforward_mux_4to1_sel2_8_1_U11 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_26_reg_1511,
dout => tmp_15_fu_894_p6);
feedforward_mux_4to1_sel2_8_1_U12 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_35_reg_1521,
dout => tmp_23_fu_923_p6);
feedforward_mux_4to1_sel2_8_1_U13 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_75_reg_1701,
dout => tmp_57_fu_1216_p6);
feedforward_mux_4to1_sel2_8_1_U14 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_7_t_reg_1753,
dout => tmp_25_fu_1359_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_V_TREADY assign process. --
ap_reg_ioackin_P_netOut_V_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_942) then
if (not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_V_TREADY)) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ST_layerSize_V_load_1_phi_reg_473 assign process. --
ST_layerSize_V_load_1_phi_reg_473_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
if (ap_sig_bdd_724) then
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_3;
elsif ((tmp_4_reg_1749 = ap_const_lv2_2)) then
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_2;
elsif ((tmp_4_reg_1749 = ap_const_lv2_1)) then
ST_layerSize_V_load_1_phi_reg_473 <= ST_layerSize_V_1;
end if;
end if;
end if;
end process;
-- i_1_reg_449 assign process. --
i_1_reg_449_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and not((ap_const_lv1_0 = tmp_1_fu_621_p2)))) then
i_1_reg_449 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_11_fu_1298_p2))) then
i_1_reg_449 <= i_9_fu_1339_p2;
end if;
end if;
end process;
-- i_2_reg_277 assign process. --
i_2_reg_277_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and (ap_const_lv1_0 = tmp_1_fu_621_p2))) then
i_2_reg_277 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434))) then
i_2_reg_277 <= i_8_fu_638_p2;
end if;
end if;
end process;
-- i_3_reg_288 assign process. --
i_3_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_434) and not((ap_const_lv1_0 = exitcond1_fu_633_p2)))) then
i_3_reg_288 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (ap_const_lv1_0 = tmp_14_fu_756_p2))) then
i_3_reg_288 <= i_10_fu_821_p2;
end if;
end if;
end process;
-- i_4_reg_346 assign process. --
i_4_reg_346_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_649_p2))) then
i_4_reg_346 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
i_4_reg_346 <= i_12_reg_1598;
end if;
end if;
end process;
-- i_5_reg_380 assign process. --
i_5_reg_380_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and (ap_const_lv1_0 = tmp_18_fu_911_p2))) then
i_5_reg_380 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) then
i_5_reg_380 <= i_11_reg_1651;
end if;
end if;
end process;
-- i_6_reg_416 assign process. --
i_6_reg_416_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_59_fu_1233_p2))) then
i_6_reg_416 <= i_14_reg_1696;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and not((ap_const_lv1_0 = tmp_41_fu_1057_p2)))) then
i_6_reg_416 <= ap_const_lv8_0;
end if;
end if;
end process;
-- i_reg_495 assign process. --
i_reg_495_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769))) then
i_reg_495 <= i_7_fu_1403_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404))) then
i_reg_495 <= ap_const_lv8_0;
end if;
end if;
end process;
-- j_1_reg_300 assign process. --
j_1_reg_300_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_649_p2)))) then
j_1_reg_300 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
j_1_reg_300 <= j_5_reg_1529;
end if;
end if;
end process;
-- j_2_reg_369 assign process. --
j_2_reg_369_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and not((ap_const_lv1_0 = tmp_18_fu_911_p2)))) then
j_2_reg_369 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
j_2_reg_369 <= j_6_reg_1623;
end if;
end if;
end process;
-- j_3_reg_438 assign process. --
j_3_reg_438_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and (ap_const_lv1_0 = exitcond_fu_1105_p2))) then
j_3_reg_438 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_438 <= j_7_reg_1730;
end if;
end if;
end process;
-- j_reg_461 assign process. --
j_reg_461_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and (ap_const_lv1_0 = tmp_22_fu_1386_p2) and not(ap_sig_bdd_755))) then
j_reg_461 <= j_4_reg_1758;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144) and not((ap_const_lv1_0 = tmp_9_fu_1259_p2)))) then
j_reg_461 <= ap_const_lv32_0;
end if;
end if;
end process;
-- k_1_reg_323 assign process. --
k_1_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_14_fu_756_p2)))) then
k_1_reg_323 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
k_1_reg_323 <= k_3_reg_1559;
end if;
end if;
end process;
-- k_reg_484 assign process. --
k_reg_484_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and not((ap_const_lv1_0 = tmp_11_fu_1298_p2)))) then
k_reg_484 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755))) then
k_reg_484 <= k_2_fu_1392_p2;
end if;
end if;
end process;
-- p_netOut_V_reg_404 assign process. --
p_netOut_V_reg_404_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and (ap_const_lv1_0 = tmp_41_fu_1057_p2))) then
p_netOut_V_reg_404 <= ap_const_lv8_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_netOut_V_reg_404 <= i_15_fu_1210_p2;
end if;
end if;
end process;
-- p_s_reg_391 assign process. --
p_s_reg_391_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and (ap_const_lv1_0 = tmp_41_fu_1057_p2))) then
p_s_reg_391 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_s_reg_391 <= p_netOut_V_1_fu_1203_p3;
end if;
end if;
end process;
-- phi_mul_reg_427 assign process. --
phi_mul_reg_427_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_59_fu_1233_p2))) then
phi_mul_reg_427 <= next_mul_reg_1688;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)) and not((ap_const_lv1_0 = tmp_41_fu_1057_p2)))) then
phi_mul_reg_427 <= ap_const_lv14_0;
end if;
end if;
end process;
-- sum_1_reg_357 assign process. --
sum_1_reg_357_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and not((ap_const_lv1_0 = tmp_18_fu_911_p2)))) then
sum_1_reg_357 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
sum_1_reg_357 <= grp_fu_506_p2;
end if;
end if;
end process;
-- sum_reg_311 assign process. --
sum_reg_311_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_14_fu_756_p2)))) then
sum_reg_311 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
sum_reg_311 <= grp_fu_506_p2;
end if;
end if;
end process;
-- sumsoft_reg_334 assign process. --
sumsoft_reg_334_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_649_p2))) then
sumsoft_reg_334 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
sumsoft_reg_334 <= grp_fu_506_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404))) then
P_config_V_read_reg_1463 <= P_config_V_TDATA;
ST_numLayer_V <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_404))) then
P_mode_V_read_reg_1437 <= P_mode_V;
ST_numLayer_V_load_reg_1446 <= ST_numLayer_V;
tmp_reg_1442 <= tmp_fu_611_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and (tmp_2_fu_1409_p1 = ap_const_lv2_0))) then
ST_layerSize_V_0 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and (ap_const_lv1_0 = tmp_1_fu_621_p2))) then
ST_layerSize_V_0_load_reg_1458 <= ST_layerSize_V_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and (ap_const_lv2_1 = tmp_2_fu_1409_p1))) then
ST_layerSize_V_1 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and (ap_const_lv2_2 = tmp_2_fu_1409_p1))) then
ST_layerSize_V_2 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769) and not((ap_const_lv2_2 = tmp_2_fu_1409_p1)) and not((ap_const_lv2_1 = tmp_2_fu_1409_p1)) and not((tmp_2_fu_1409_p1 = ap_const_lv2_0)))) then
ST_layerSize_V_3 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and not(ap_sig_bdd_769))) then
exitcond5_reg_1799 <= exitcond5_fu_1398_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
i_11_reg_1651 <= i_11_fu_1037_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
i_12_reg_1598 <= i_12_fu_917_p2;
tmp_15_reg_1589 <= tmp_15_fu_894_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)))) then
i_14_reg_1696 <= i_14_fu_1110_p2;
next_mul_reg_1688 <= next_mul_fu_1099_p2;
tmp_74_reg_1683 <= tmp_74_fu_1095_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
j_4_reg_1758 <= j_4_fu_1288_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
j_5_reg_1529 <= j_5_fu_762_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
j_6_reg_1623 <= j_6_fu_985_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
j_7_reg_1730 <= j_7_fu_1239_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
k_3_reg_1559 <= k_3_fu_832_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_14_fu_756_p2)))) then
p_uOut_addr_1_reg_1546 <= tmp_70_cast_fu_786_p1(8 - 1 downto 0);
tmp_19_reg_1534 <= tmp_19_fu_768_p6;
tmp_60_reg_1540(13 downto 2) <= tmp_60_fu_815_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) and not((ap_const_lv1_0 = tmp_18_fu_911_p2)))) then
p_uOut_addr_3_reg_1615 <= tmp_74_cast_fu_945_p1(8 - 1 downto 0);
tmp_23_reg_1603 <= tmp_23_fu_923_p6;
tmp_64_reg_1609(13 downto 2) <= tmp_64_fu_974_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and (ap_const_lv1_0 = exitcond4_fu_1032_p2))) then
p_uOut_addr_5_reg_1656 <= tmp_85_cast_fu_1052_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) then
p_uOut_load_4_reg_1706 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120) or (ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139))) then
reg_565 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88))) then
reg_572 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82))) then
reg_578 <= grp_fu_513_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
reg_589 <= grp_fu_506_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94))) then
reg_594 <= grp_fu_527_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38) or (ap_const_logic_1 = ap_sig_cseq_ST_st113_fsm_112))) then
reg_599 <= grp_fu_544_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75) or (ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113))) then
reg_605 <= grp_fu_524_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_649_p2)))) then
tmp_16_reg_1489 <= tmp_16_fu_682_p2;
tmp_20_reg_1494 <= tmp_20_fu_688_p1;
tmp_62_cast_reg_1479(14 downto 0) <= tmp_62_cast_fu_664_p1(14 downto 0);
tmp_6_reg_1484 <= tmp_6_fu_668_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404))) then
tmp_1_reg_1454 <= tmp_1_fu_621_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_649_p2))) then
tmp_24_reg_1499 <= tmp_24_fu_711_p1;
tmp_26_reg_1511 <= tmp_26_fu_719_p1;
tmp_33_reg_1516 <= tmp_33_fu_729_p2;
tmp_35_reg_1521 <= tmp_35_fu_735_p1;
tmp_64_cast_reg_1506 <= tmp_64_cast_fu_715_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) then
tmp_30_reg_1579 <= grp_fu_534_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) then
tmp_31_reg_1584 <= grp_fu_539_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) and not((ap_const_lv1_0 = exitcond4_fu_1032_p2)))) then
tmp_41_reg_1661 <= tmp_41_fu_1057_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st137_fsm_136)) then
tmp_43_reg_1665 <= grp_fu_519_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and not((ap_const_lv1_0 = tmp_11_fu_1298_p2)))) then
tmp_46_reg_1781(13 downto 2) <= tmp_46_fu_1333_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144) and not((ap_const_lv1_0 = tmp_9_fu_1259_p2)))) then
tmp_4_reg_1749 <= tmp_4_fu_1278_p1;
tmp_61_cast_reg_1744(14 downto 0) <= tmp_61_cast_fu_1274_p1(14 downto 0);
tmp_7_t_reg_1753 <= tmp_7_t_fu_1282_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
tmp_56_reg_1712 <= tmp_56_fu_1197_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and (ap_const_lv1_0 = exitcond_fu_1105_p2))) then
tmp_75_reg_1701 <= tmp_75_fu_1116_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) then
tmp_9_reg_1740 <= tmp_9_fu_1259_p2;
end if;
end if;
end process;
tmp_62_cast_reg_1479(31 downto 15) <= "00000000000000000";
tmp_60_reg_1540(1 downto 0) <= "00";
tmp_64_reg_1609(1 downto 0) <= "00";
tmp_61_cast_reg_1744(31 downto 15) <= "00000000000000000";
tmp_46_reg_1781(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_611_p2, ap_sig_bdd_404, tmp_reg_1442, tmp_1_fu_621_p2, tmp_1_reg_1454, exitcond1_fu_633_p2, ap_sig_bdd_434, tmp_7_fu_649_p2, tmp_14_fu_756_p2, exitcond2_fu_827_p2, tmp_18_fu_911_p2, exitcond3_fu_980_p2, exitcond4_fu_1032_p2, tmp_41_reg_1661, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond_fu_1105_p2, tmp_59_fu_1233_p2, tmp_9_fu_1259_p2, tmp_9_reg_1740, tmp_11_fu_1298_p2, tmp_22_fu_1386_p2, ap_sig_bdd_755, exitcond5_fu_1398_p2, exitcond5_reg_1799, ap_sig_bdd_769, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
elsif (((tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and (ap_const_lv1_0 = tmp_1_fu_621_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_611_p2 = ap_const_lv1_0) and not(ap_sig_bdd_404) and not((ap_const_lv1_0 = tmp_1_fu_621_p2)))) then
ap_NS_fsm <= ap_ST_st145_fsm_144;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (((ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not(ap_sig_bdd_434) and not((ap_const_lv1_0 = exitcond1_fu_633_p2)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_7_fu_649_p2)) then
ap_NS_fsm <= ap_ST_st78_fsm_77;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
if ((ap_const_lv1_0 = tmp_14_fu_756_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ap_const_lv1_0 = exitcond2_fu_827_p2))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st78_fsm_77 =>
if (not((ap_const_lv1_0 = tmp_18_fu_911_p2))) then
ap_NS_fsm <= ap_ST_st79_fsm_78;
else
ap_NS_fsm <= ap_ST_st120_fsm_119;
end if;
when ap_ST_st79_fsm_78 =>
if (not((ap_const_lv1_0 = exitcond3_fu_980_p2))) then
ap_NS_fsm <= ap_ST_st89_fsm_88;
else
ap_NS_fsm <= ap_ST_st80_fsm_79;
end if;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st93_fsm_92;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st120_fsm_119 =>
if (not((ap_const_lv1_0 = exitcond4_fu_1032_p2))) then
ap_NS_fsm <= ap_ST_st139_fsm_138;
else
ap_NS_fsm <= ap_ST_st121_fsm_120;
end if;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st139_fsm_138 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2)) or (not((ap_const_lv1_0 = tmp_reg_1442)) and not((ap_const_lv1_0 = exitcond5_reg_1799))) or ((ap_const_lv1_0 = tmp_reg_1442) and not((ap_const_lv1_0 = tmp_1_reg_1454)) and (ap_const_lv1_0 = tmp_9_reg_1740)) or ((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and not((ap_const_lv1_0 = exitcond_fu_1105_p2)))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and (ap_const_lv1_0 = exitcond_fu_1105_p2))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
elsif (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_44_fu_1062_p2)))) then
ap_NS_fsm <= ap_ST_st140_fsm_139;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st143_fsm_142 =>
if (not((ap_const_lv1_0 = tmp_59_fu_1233_p2))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st144_fsm_143 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st144_fsm_143;
end if;
when ap_ST_st145_fsm_144 =>
if (not((ap_const_lv1_0 = tmp_9_fu_1259_p2))) then
ap_NS_fsm <= ap_ST_st146_fsm_145;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st147_fsm_146;
when ap_ST_st147_fsm_146 =>
if ((ap_const_lv1_0 = tmp_11_fu_1298_p2)) then
ap_NS_fsm <= ap_ST_st145_fsm_144;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st148_fsm_147 =>
if ((not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
elsif (((ap_const_lv1_0 = tmp_22_fu_1386_p2) and not(ap_sig_bdd_755))) then
ap_NS_fsm <= ap_ST_st146_fsm_145;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (((ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
elsif ((not(ap_sig_bdd_769) and not((ap_const_lv1_0 = exitcond5_fu_1398_p2)))) then
ap_NS_fsm <= ap_ST_st139_fsm_138;
else
ap_NS_fsm <= ap_ST_st149_fsm_148;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, tmp_22_fu_1386_p2, ap_sig_bdd_755)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_V_TREADY assign process. --
P_config_V_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_611_p2, ap_sig_bdd_404, exitcond5_fu_1398_p2, ap_sig_cseq_ST_st149_fsm_148, ap_sig_bdd_769)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_611_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_404)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) and (ap_const_lv1_0 = exitcond5_fu_1398_p2) and not(ap_sig_bdd_769)))) then
P_config_V_TREADY <= ap_const_logic_1;
else
P_config_V_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_633_p2, ap_sig_bdd_434)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_V_TDATA <= p_s_reg_391;
-- P_netOut_V_TVALID assign process. --
P_netOut_V_TVALID_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY))) then
P_netOut_V_TVALID <= ap_const_logic_1;
else
P_netOut_V_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st144_fsm_143, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond2_fu_827_p2, ap_sig_cseq_ST_st79_fsm_78, exitcond3_fu_980_p2, ap_sig_cseq_ST_st148_fsm_147, tmp_80_cast_fu_851_p1, tmp_79_cast_fu_874_p1, tmp_83_cast_fu_1004_p1, tmp_82_cast_fu_1027_p1, tmp_78_cast_fu_1354_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
ST_WandB_address0 <= tmp_78_cast_fu_1354_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = exitcond3_fu_980_p2)))) then
ST_WandB_address0 <= tmp_82_cast_fu_1027_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and (ap_const_lv1_0 = exitcond3_fu_980_p2))) then
ST_WandB_address0 <= tmp_83_cast_fu_1004_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond2_fu_827_p2)))) then
ST_WandB_address0 <= tmp_79_cast_fu_874_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond2_fu_827_p2))) then
ST_WandB_address0 <= tmp_80_cast_fu_851_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond2_fu_827_p2, ap_sig_cseq_ST_st79_fsm_78, exitcond3_fu_980_p2, ap_sig_cseq_ST_st148_fsm_147, ap_sig_bdd_755)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond2_fu_827_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond2_fu_827_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and (ap_const_lv1_0 = exitcond3_fu_980_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = exitcond3_fu_980_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not(ap_sig_bdd_755)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, tmp_22_fu_1386_p2, ap_sig_bdd_755)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)) and not(ap_sig_bdd_755)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond_fu_1105_p2, tmp_9_reg_1740, exitcond5_reg_1799)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2)) or (not((ap_const_lv1_0 = tmp_reg_1442)) and not((ap_const_lv1_0 = exitcond5_reg_1799))) or ((ap_const_lv1_0 = tmp_reg_1442) and not((ap_const_lv1_0 = tmp_1_reg_1454)) and (ap_const_lv1_0 = tmp_9_reg_1740)) or ((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and not((ap_const_lv1_0 = exitcond_fu_1105_p2)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond_fu_1105_p2, tmp_9_reg_1740, exitcond5_reg_1799)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2)) or (not((ap_const_lv1_0 = tmp_reg_1442)) and not((ap_const_lv1_0 = exitcond5_reg_1799))) or ((ap_const_lv1_0 = tmp_reg_1442) and not((ap_const_lv1_0 = tmp_1_reg_1454)) and (ap_const_lv1_0 = tmp_9_reg_1740)) or ((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and not((ap_const_lv1_0 = tmp_41_reg_1661)) and not((ap_const_lv1_0 = exitcond_fu_1105_p2)))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1002 assign process. --
ap_sig_bdd_1002_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1002 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_1009 assign process. --
ap_sig_bdd_1009_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1009 <= (ap_const_lv1_1 = ap_CS_fsm(89 downto 89));
end process;
-- ap_sig_bdd_167 assign process. --
ap_sig_bdd_167_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_167 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_249 assign process. --
ap_sig_bdd_249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_249 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_256 assign process. --
ap_sig_bdd_256_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_256 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_264 assign process. --
ap_sig_bdd_264_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_264 <= (ap_const_lv1_1 = ap_CS_fsm(120 downto 120));
end process;
-- ap_sig_bdd_272 assign process. --
ap_sig_bdd_272_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_272 <= (ap_const_lv1_1 = ap_CS_fsm(139 downto 139));
end process;
-- ap_sig_bdd_281 assign process. --
ap_sig_bdd_281_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_281 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_290 assign process. --
ap_sig_bdd_290_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_290 <= (ap_const_lv1_1 = ap_CS_fsm(88 downto 88));
end process;
-- ap_sig_bdd_300 assign process. --
ap_sig_bdd_300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_300 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_307 assign process. --
ap_sig_bdd_307_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_307 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_317 assign process. --
ap_sig_bdd_317_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_317 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_324 assign process. --
ap_sig_bdd_324_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_324 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_333 assign process. --
ap_sig_bdd_333_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_333 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_340 assign process. --
ap_sig_bdd_340_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_340 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_350 assign process. --
ap_sig_bdd_350_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_350 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_357 assign process. --
ap_sig_bdd_357_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_357 <= (ap_const_lv1_1 = ap_CS_fsm(94 downto 94));
end process;
-- ap_sig_bdd_367 assign process. --
ap_sig_bdd_367_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_367 <= (ap_const_lv1_1 = ap_CS_fsm(38 downto 38));
end process;
-- ap_sig_bdd_374 assign process. --
ap_sig_bdd_374_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_374 <= (ap_const_lv1_1 = ap_CS_fsm(112 downto 112));
end process;
-- ap_sig_bdd_384 assign process. --
ap_sig_bdd_384_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_384 <= (ap_const_lv1_1 = ap_CS_fsm(75 downto 75));
end process;
-- ap_sig_bdd_391 assign process. --
ap_sig_bdd_391_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_391 <= (ap_const_lv1_1 = ap_CS_fsm(113 downto 113));
end process;
-- ap_sig_bdd_404 assign process. --
ap_sig_bdd_404_assign_proc : process(ap_start, P_config_V_TVALID, tmp_fu_611_p2)
begin
ap_sig_bdd_404 <= (((P_config_V_TVALID = ap_const_logic_0) and not((tmp_fu_611_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_428 assign process. --
ap_sig_bdd_428_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_428 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_434 assign process. --
ap_sig_bdd_434_assign_proc : process(P_netIn_TVALID, exitcond1_fu_633_p2)
begin
ap_sig_bdd_434 <= ((P_netIn_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond1_fu_633_p2));
end process;
-- ap_sig_bdd_444 assign process. --
ap_sig_bdd_444_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_444 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_474 assign process. --
ap_sig_bdd_474_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_474 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_496 assign process. --
ap_sig_bdd_496_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_496 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_516 assign process. --
ap_sig_bdd_516_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_516 <= (ap_const_lv1_1 = ap_CS_fsm(43 downto 43));
end process;
-- ap_sig_bdd_525 assign process. --
ap_sig_bdd_525_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_525 <= (ap_const_lv1_1 = ap_CS_fsm(74 downto 74));
end process;
-- ap_sig_bdd_534 assign process. --
ap_sig_bdd_534_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_534 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_555 assign process. --
ap_sig_bdd_555_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_555 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_574 assign process. --
ap_sig_bdd_574_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_574 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_bdd_583 assign process. --
ap_sig_bdd_583_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_583 <= (ap_const_lv1_1 = ap_CS_fsm(119 downto 119));
end process;
-- ap_sig_bdd_601 assign process. --
ap_sig_bdd_601_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_601 <= (ap_const_lv1_1 = ap_CS_fsm(136 downto 136));
end process;
-- ap_sig_bdd_610 assign process. --
ap_sig_bdd_610_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_610 <= (ap_const_lv1_1 = ap_CS_fsm(138 downto 138));
end process;
-- ap_sig_bdd_654 assign process. --
ap_sig_bdd_654_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_654 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_663 assign process. --
ap_sig_bdd_663_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_663 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_674 assign process. --
ap_sig_bdd_674_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_674 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_689 assign process. --
ap_sig_bdd_689_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_689 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_707 assign process. --
ap_sig_bdd_707_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_707 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_724 assign process. --
ap_sig_bdd_724_assign_proc : process(tmp_4_reg_1749)
begin
ap_sig_bdd_724 <= (not((tmp_4_reg_1749 = ap_const_lv2_2)) and not((tmp_4_reg_1749 = ap_const_lv2_1)));
end process;
-- ap_sig_bdd_732 assign process. --
ap_sig_bdd_732_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_732 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_748 assign process. --
ap_sig_bdd_748_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_748 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_755 assign process. --
ap_sig_bdd_755_assign_proc : process(P_WandB_TVALID, tmp_22_fu_1386_p2)
begin
ap_sig_bdd_755 <= ((P_WandB_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_22_fu_1386_p2)));
end process;
-- ap_sig_bdd_765 assign process. --
ap_sig_bdd_765_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_765 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_769 assign process. --
ap_sig_bdd_769_assign_proc : process(P_config_V_TVALID, exitcond5_fu_1398_p2)
begin
ap_sig_bdd_769 <= ((P_config_V_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond5_fu_1398_p2));
end process;
-- ap_sig_bdd_800 assign process. --
ap_sig_bdd_800_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_800 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_821 assign process. --
ap_sig_bdd_821_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_821 <= (ap_const_lv1_1 = ap_CS_fsm(137 downto 137));
end process;
-- ap_sig_bdd_847 assign process. --
ap_sig_bdd_847_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_847 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_942 assign process. --
ap_sig_bdd_942_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2)
begin
ap_sig_bdd_942 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and (ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2));
end process;
-- ap_sig_bdd_963 assign process. --
ap_sig_bdd_963_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_963 <= (ap_const_lv1_1 = ap_CS_fsm(114 downto 114));
end process;
-- ap_sig_bdd_987 assign process. --
ap_sig_bdd_987_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_987 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_994 assign process. --
ap_sig_bdd_994_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_994 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_987)
begin
if (ap_sig_bdd_987) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st113_fsm_112 assign process. --
ap_sig_cseq_ST_st113_fsm_112_assign_proc : process(ap_sig_bdd_374)
begin
if (ap_sig_bdd_374) then
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st114_fsm_113 assign process. --
ap_sig_cseq_ST_st114_fsm_113_assign_proc : process(ap_sig_bdd_391)
begin
if (ap_sig_bdd_391) then
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st115_fsm_114 assign process. --
ap_sig_cseq_ST_st115_fsm_114_assign_proc : process(ap_sig_bdd_963)
begin
if (ap_sig_bdd_963) then
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_574)
begin
if (ap_sig_bdd_574) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st120_fsm_119 assign process. --
ap_sig_cseq_ST_st120_fsm_119_assign_proc : process(ap_sig_bdd_583)
begin
if (ap_sig_bdd_583) then
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_120 assign process. --
ap_sig_cseq_ST_st121_fsm_120_assign_proc : process(ap_sig_bdd_264)
begin
if (ap_sig_bdd_264) then
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st137_fsm_136 assign process. --
ap_sig_cseq_ST_st137_fsm_136_assign_proc : process(ap_sig_bdd_601)
begin
if (ap_sig_bdd_601) then
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st138_fsm_137 assign process. --
ap_sig_cseq_ST_st138_fsm_137_assign_proc : process(ap_sig_bdd_821)
begin
if (ap_sig_bdd_821) then
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st139_fsm_138 assign process. --
ap_sig_cseq_ST_st139_fsm_138_assign_proc : process(ap_sig_bdd_610)
begin
if (ap_sig_bdd_610) then
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st140_fsm_139 assign process. --
ap_sig_cseq_ST_st140_fsm_139_assign_proc : process(ap_sig_bdd_272)
begin
if (ap_sig_bdd_272) then
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_654)
begin
if (ap_sig_bdd_654) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_663)
begin
if (ap_sig_bdd_663) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_674)
begin
if (ap_sig_bdd_674) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_847)
begin
if (ap_sig_bdd_847) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_689)
begin
if (ap_sig_bdd_689) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_707)
begin
if (ap_sig_bdd_707) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_732)
begin
if (ap_sig_bdd_732) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_748)
begin
if (ap_sig_bdd_748) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_765)
begin
if (ap_sig_bdd_765) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_317)
begin
if (ap_sig_bdd_317) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_281)
begin
if (ap_sig_bdd_281) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_994)
begin
if (ap_sig_bdd_994) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_167)
begin
if (ap_sig_bdd_167) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_333)
begin
if (ap_sig_bdd_333) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_350)
begin
if (ap_sig_bdd_350) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_428)
begin
if (ap_sig_bdd_428) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_38 assign process. --
ap_sig_cseq_ST_st39_fsm_38_assign_proc : process(ap_sig_bdd_367)
begin
if (ap_sig_bdd_367) then
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_444)
begin
if (ap_sig_bdd_444) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st44_fsm_43 assign process. --
ap_sig_cseq_ST_st44_fsm_43_assign_proc : process(ap_sig_bdd_516)
begin
if (ap_sig_bdd_516) then
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_474)
begin
if (ap_sig_bdd_474) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_496)
begin
if (ap_sig_bdd_496) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_249)
begin
if (ap_sig_bdd_249) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st75_fsm_74 assign process. --
ap_sig_cseq_ST_st75_fsm_74_assign_proc : process(ap_sig_bdd_525)
begin
if (ap_sig_bdd_525) then
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st76_fsm_75 assign process. --
ap_sig_cseq_ST_st76_fsm_75_assign_proc : process(ap_sig_bdd_384)
begin
if (ap_sig_bdd_384) then
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_800)
begin
if (ap_sig_bdd_800) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_534)
begin
if (ap_sig_bdd_534) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_256)
begin
if (ap_sig_bdd_256) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_307)
begin
if (ap_sig_bdd_307) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_1002)
begin
if (ap_sig_bdd_1002) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_324)
begin
if (ap_sig_bdd_324) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st89_fsm_88 assign process. --
ap_sig_cseq_ST_st89_fsm_88_assign_proc : process(ap_sig_bdd_290)
begin
if (ap_sig_bdd_290) then
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st90_fsm_89 assign process. --
ap_sig_cseq_ST_st90_fsm_89_assign_proc : process(ap_sig_bdd_1009)
begin
if (ap_sig_bdd_1009) then
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_340)
begin
if (ap_sig_bdd_340) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st95_fsm_94 assign process. --
ap_sig_cseq_ST_st95_fsm_94_assign_proc : process(ap_sig_bdd_357)
begin
if (ap_sig_bdd_357) then
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_300)
begin
if (ap_sig_bdd_300) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_V_TREADY assign process. --
ap_sig_ioackin_P_netOut_V_TREADY_assign_proc : process(P_netOut_V_TREADY, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY)) then
ap_sig_ioackin_P_netOut_V_TREADY <= P_netOut_V_TREADY;
else
ap_sig_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
exitcond1_fu_633_p2 <= "1" when (i_2_reg_277 = ST_layerSize_V_0_load_reg_1458) else "0";
exitcond2_fu_827_p2 <= "1" when (k_1_reg_323 = tmp_19_reg_1534) else "0";
exitcond3_fu_980_p2 <= "1" when (j_2_reg_369 = tmp_23_reg_1603) else "0";
exitcond4_fu_1032_p2 <= "1" when (i_5_reg_380 = tmp_15_reg_1589) else "0";
exitcond5_fu_1398_p2 <= "1" when (i_reg_495 = P_config_V_read_reg_1463) else "0";
exitcond_fu_1105_p2 <= "1" when (i_6_reg_416 = ST_numLayer_V_load_reg_1446) else "0";
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_506_ce <= ap_const_logic_1;
-- grp_fu_506_p0 assign process. --
grp_fu_506_p0_assign_proc : process(sum_reg_311, sumsoft_reg_334, sum_1_reg_357, ap_sig_cseq_ST_st115_fsm_114, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st84_fsm_83, ap_sig_cseq_ST_st90_fsm_89)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) then
grp_fu_506_p0 <= sumsoft_reg_334;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89))) then
grp_fu_506_p0 <= sum_1_reg_357;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then
grp_fu_506_p0 <= sum_reg_311;
else
grp_fu_506_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_506_p1 assign process. --
grp_fu_506_p1_assign_proc : process(reg_572, reg_578, reg_605, ap_sig_cseq_ST_st115_fsm_114, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st84_fsm_83, ap_sig_cseq_ST_st90_fsm_89)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) then
grp_fu_506_p1 <= reg_605;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) or (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89))) then
grp_fu_506_p1 <= reg_572;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83))) then
grp_fu_506_p1 <= reg_578;
else
grp_fu_506_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_513_ce <= ap_const_logic_1;
grp_fu_519_ce <= ap_const_logic_1;
-- grp_fu_524_p0 assign process. --
grp_fu_524_p0_assign_proc : process(reg_599, ap_sig_cseq_ST_st76_fsm_75, ap_sig_cseq_ST_st114_fsm_113, tmp_31_reg_1584)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113)) then
grp_fu_524_p0 <= reg_599;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75)) then
grp_fu_524_p0 <= tmp_31_reg_1584;
else
grp_fu_524_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_527_p0 assign process. --
grp_fu_527_p0_assign_proc : process(reg_589, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st95_fsm_94, tmp_27_fu_889_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94)) then
grp_fu_527_p0 <= reg_589;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then
grp_fu_527_p0 <= tmp_27_fu_889_p1;
else
grp_fu_527_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_534_ce <= ap_const_logic_1;
grp_fu_539_ce <= ap_const_logic_1;
grp_fu_544_ce <= ap_const_logic_1;
i_10_fu_821_p2 <= std_logic_vector(unsigned(i_3_reg_288) + unsigned(ap_const_lv8_1));
i_11_fu_1037_p2 <= std_logic_vector(unsigned(i_5_reg_380) + unsigned(ap_const_lv8_1));
i_12_fu_917_p2 <= std_logic_vector(unsigned(i_4_reg_346) + unsigned(ap_const_lv32_1));
i_14_fu_1110_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(i_6_reg_416));
i_15_fu_1210_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(p_netOut_V_reg_404));
i_7_fu_1403_p2 <= std_logic_vector(unsigned(i_reg_495) + unsigned(ap_const_lv8_1));
i_8_fu_638_p2 <= std_logic_vector(unsigned(i_2_reg_277) + unsigned(ap_const_lv8_1));
i_9_fu_1339_p2 <= std_logic_vector(unsigned(i_1_reg_449) + unsigned(ap_const_lv8_1));
j_4_fu_1288_p2 <= std_logic_vector(unsigned(j_reg_461) + unsigned(ap_const_lv32_1));
j_5_fu_762_p2 <= std_logic_vector(unsigned(j_1_reg_300) + unsigned(ap_const_lv32_1));
j_6_fu_985_p2 <= std_logic_vector(unsigned(j_2_reg_369) + unsigned(ap_const_lv8_1));
j_7_fu_1239_p2 <= std_logic_vector(unsigned(j_3_reg_438) + unsigned(ap_const_lv32_1));
k_2_fu_1392_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(k_reg_484));
k_3_fu_832_p2 <= std_logic_vector(unsigned(k_1_reg_323) + unsigned(ap_const_lv8_1));
lhs_V_1_cast_fu_692_p1 <= std_logic_vector(resize(unsigned(ST_numLayer_V_load_reg_1446),9));
lhs_V_cast_fu_1372_p1 <= std_logic_vector(resize(unsigned(tmp_25_fu_1359_p6),9));
next_mul_fu_1099_p2 <= std_logic_vector(unsigned(ap_const_lv14_23) + unsigned(phi_mul_reg_427));
notlhs1_fu_1173_p2 <= "0" when (tmp_50_fu_1141_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_1155_p2 <= "0" when (tmp_48_fu_1124_p4 = ap_const_lv8_FF) else "1";
notrhs1_fu_1179_p2 <= "1" when (tmp_79_fu_1151_p1 = ap_const_lv23_0) else "0";
notrhs_fu_1161_p2 <= "1" when (tmp_78_fu_1134_p1 = ap_const_lv23_0) else "0";
p_netOut_V_1_fu_1203_p3 <=
p_netOut_V_reg_404 when (tmp_56_reg_1712(0) = '1') else
p_s_reg_391;
p_shl1_cast_fu_1325_p3 <= (tmp_45_fu_1321_p1 & ap_const_lv2_0);
p_shl2_cast_fu_795_p3 <= (tmp_49_fu_791_p1 & ap_const_lv5_0);
p_shl3_cast_fu_807_p3 <= (tmp_51_fu_803_p1 & ap_const_lv2_0);
p_shl4_cast_fu_954_p3 <= (tmp_62_fu_950_p1 & ap_const_lv5_0);
p_shl5_cast_fu_966_p3 <= (tmp_63_fu_962_p1 & ap_const_lv2_0);
p_shl_cast_fu_1313_p3 <= (tmp_42_fu_1309_p1 & ap_const_lv5_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_1_reg_1546, ap_sig_cseq_ST_st5_fsm_4, p_uOut_addr_3_reg_1615, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st120_fsm_119, p_uOut_addr_5_reg_1656, ap_sig_cseq_ST_st139_fsm_138, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, tmp_8_fu_644_p1, tmp_81_cast_fu_861_p1, tmp_84_cast_fu_1014_p1, tmp_85_cast_fu_1052_p1, tmp_87_cast_fu_1076_p1, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1656;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) then
p_uOut_address0 <= p_uOut_addr_3_reg_1615;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
p_uOut_address0 <= p_uOut_addr_1_reg_1546;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_8_fu_644_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) then
p_uOut_address0 <= tmp_87_cast_fu_1076_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
p_uOut_address0 <= tmp_85_cast_fu_1052_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
p_uOut_address0 <= tmp_84_cast_fu_1014_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
p_uOut_address0 <= tmp_81_cast_fu_861_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st139_fsm_138, ap_sig_cseq_ST_st143_fsm_142, tmp_88_cast_fu_1090_p1, tmp_89_cast_fu_1254_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address1 <= tmp_89_cast_fu_1254_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) then
p_uOut_address1 <= tmp_88_cast_fu_1090_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_434, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st120_fsm_119, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_434)) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119) or ((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1442, tmp_1_reg_1454, tmp_41_reg_1661, ap_sig_cseq_ST_st139_fsm_138, tmp_44_fu_1062_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st143_fsm_142)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138) and not(((ap_const_lv1_0 = tmp_reg_1442) and (ap_const_lv1_0 = tmp_1_reg_1454) and (ap_const_lv1_0 = tmp_41_reg_1661) and (ap_const_lv1_0 = tmp_44_fu_1062_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_605, ap_sig_cseq_ST_st2_fsm_1, tmp_43_reg_1665, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) then
p_uOut_d0 <= tmp_43_reg_1665;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114))) then
p_uOut_d0 <= reg_605;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1120_p1 <= reg_565;
p_uOut_load_4_to_int_fu_1138_p1 <= p_uOut_load_4_reg_1706;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_633_p2, ap_sig_bdd_434, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st115_fsm_114)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_633_p2) and not(ap_sig_bdd_434)) or (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
r_V_1_fu_695_p2 <= std_logic_vector(signed(ap_const_lv9_1FF) + signed(lhs_V_1_cast_fu_692_p1));
r_V_2_fu_723_p2 <= std_logic_vector(signed(ap_const_lv9_1FE) + signed(lhs_V_1_cast_fu_692_p1));
r_V_fu_1376_p2 <= std_logic_vector(unsigned(ap_const_lv9_1) + unsigned(lhs_V_cast_fu_1372_p1));
tmp_10_fu_1294_p1 <= std_logic_vector(resize(unsigned(ST_layerSize_V_load_1_phi_reg_473),32));
tmp_11_fu_1298_p2 <= "1" when (signed(j_reg_461) < signed(tmp_10_fu_1294_p1)) else "0";
tmp_13_fu_752_p1 <= std_logic_vector(resize(unsigned(tmp_12_fu_739_p6),32));
tmp_14_fu_756_p2 <= "1" when (signed(j_1_reg_300) < signed(tmp_13_fu_752_p1)) else "0";
tmp_16_fu_682_p1 <= tmp_16_fu_682_p10(8 - 1 downto 0);
tmp_16_fu_682_p10 <= std_logic_vector(resize(unsigned(tmp_3_fu_672_p2),9));
tmp_16_fu_682_p2 <= std_logic_vector(resize(unsigned(ap_const_lv9_23) * unsigned(tmp_16_fu_682_p1), 9));
tmp_17_fu_907_p1 <= std_logic_vector(resize(unsigned(tmp_15_fu_894_p6),32));
tmp_18_fu_911_p2 <= "1" when (signed(i_4_reg_346) < signed(tmp_17_fu_907_p1)) else "0";
tmp_1_fu_621_p2 <= "1" when (P_mode_V = ap_const_lv8_2) else "0";
tmp_20_fu_688_p1 <= tmp_3_fu_672_p2(2 - 1 downto 0);
tmp_21_cast_fu_1382_p1 <= std_logic_vector(resize(unsigned(r_V_fu_1376_p2),32));
tmp_21_fu_705_p1 <= r_V_1_fu_695_p2;
tmp_21_fu_705_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv16_23) * signed(tmp_21_fu_705_p1))), 16));
tmp_22_fu_1386_p2 <= "1" when (signed(k_reg_484) < signed(tmp_21_cast_fu_1382_p1)) else "0";
tmp_24_cast_fu_936_p1 <= std_logic_vector(resize(signed(i_4_reg_346),33));
tmp_24_fu_711_p1 <= tmp_21_fu_705_p2(9 - 1 downto 0);
tmp_26_cast_fu_866_p1 <= std_logic_vector(resize(unsigned(tmp_19_reg_1534),14));
tmp_26_fu_719_p1 <= r_V_1_fu_695_p2(2 - 1 downto 0);
tmp_27_fu_889_p1 <= tmp_35_neg_fu_883_p2;
tmp_2_fu_1409_p1 <= i_reg_495(2 - 1 downto 0);
tmp_33_cast7_fu_838_p1 <= std_logic_vector(resize(unsigned(k_1_reg_323),9));
tmp_33_cast_fu_842_p1 <= std_logic_vector(resize(unsigned(k_1_reg_323),14));
tmp_33_fu_729_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(r_V_2_fu_723_p2))), 9));
tmp_35_cast_fu_1019_p1 <= std_logic_vector(resize(unsigned(tmp_23_reg_1603),14));
tmp_35_fu_735_p1 <= r_V_2_fu_723_p2(2 - 1 downto 0);
tmp_35_neg_fu_883_p2 <= (tmp_35_to_int_fu_879_p1 xor ap_const_lv32_80000000);
tmp_35_to_int_fu_879_p1 <= reg_589;
tmp_39_cast6_fu_991_p1 <= std_logic_vector(resize(unsigned(j_2_reg_369),9));
tmp_39_cast_fu_995_p1 <= std_logic_vector(resize(unsigned(j_2_reg_369),14));
tmp_39_fu_1304_p2 <= std_logic_vector(unsigned(j_reg_461) + unsigned(tmp_61_cast_reg_1744));
tmp_3_fu_672_p2 <= std_logic_vector(signed(ap_const_lv8_FF) + signed(i_3_reg_288));
tmp_41_fu_1057_p2 <= "1" when (P_mode_V_read_reg_1437 = ap_const_lv8_3) else "0";
tmp_42_cast_fu_1043_p1 <= std_logic_vector(resize(unsigned(i_5_reg_380),9));
tmp_42_fu_1309_p1 <= tmp_39_fu_1304_p2(9 - 1 downto 0);
tmp_44_fu_1062_p2 <= "1" when (unsigned(p_netOut_V_reg_404) < unsigned(tmp_15_reg_1589)) else "0";
tmp_45_fu_1321_p1 <= tmp_39_fu_1304_p2(12 - 1 downto 0);
tmp_46_cast_fu_1067_p1 <= std_logic_vector(resize(unsigned(p_netOut_V_reg_404),9));
tmp_46_fu_1333_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1313_p3) + unsigned(p_shl1_cast_fu_1325_p3));
tmp_47_cast_fu_1081_p1 <= std_logic_vector(resize(unsigned(p_s_reg_391),9));
tmp_47_fu_781_p2 <= std_logic_vector(unsigned(j_1_reg_300) + unsigned(tmp_62_cast_reg_1479));
tmp_48_fu_1124_p4 <= p_uOut_load_3_to_int_fu_1120_p1(30 downto 23);
tmp_49_fu_791_p1 <= tmp_47_fu_781_p2(9 - 1 downto 0);
tmp_4_fu_1278_p1 <= i_1_reg_449(2 - 1 downto 0);
tmp_50_fu_1141_p4 <= p_uOut_load_4_to_int_fu_1138_p1(30 downto 23);
tmp_51_fu_803_p1 <= tmp_47_fu_781_p2(12 - 1 downto 0);
tmp_52_fu_1167_p2 <= (notrhs_fu_1161_p2 or notlhs_fu_1155_p2);
tmp_53_fu_1185_p2 <= (notrhs1_fu_1179_p2 or notlhs1_fu_1173_p2);
tmp_54_fu_1191_p2 <= (tmp_52_fu_1167_p2 and tmp_53_fu_1185_p2);
tmp_55_fu_530_opcode <= ap_const_lv5_2;
tmp_56_fu_1197_p2 <= (tmp_54_fu_1191_p2 and tmp_55_fu_530_p2);
tmp_58_fu_1229_p1 <= std_logic_vector(resize(unsigned(tmp_57_fu_1216_p6),32));
tmp_59_fu_1233_p2 <= "1" when (signed(j_3_reg_438) < signed(tmp_58_fu_1229_p1)) else "0";
tmp_5_fu_658_p1 <= tmp_5_fu_658_p10(8 - 1 downto 0);
tmp_5_fu_658_p10 <= std_logic_vector(resize(unsigned(i_3_reg_288),15));
tmp_5_fu_658_p2 <= std_logic_vector(resize(unsigned(ap_const_lv15_23) * unsigned(tmp_5_fu_658_p1), 15));
tmp_60_fu_815_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_795_p3) + unsigned(p_shl3_cast_fu_807_p3));
tmp_61_cast_fu_1274_p1 <= std_logic_vector(resize(unsigned(tmp_s_fu_1268_p2),32));
tmp_61_fu_940_p2 <= std_logic_vector(signed(tmp_24_cast_fu_936_p1) + signed(tmp_64_cast_reg_1506));
tmp_62_cast_fu_664_p1 <= std_logic_vector(resize(unsigned(tmp_5_fu_658_p2),32));
tmp_62_fu_950_p1 <= tmp_61_fu_940_p2(9 - 1 downto 0);
tmp_63_fu_962_p1 <= tmp_61_fu_940_p2(12 - 1 downto 0);
tmp_64_cast_fu_715_p1 <= std_logic_vector(resize(signed(tmp_21_fu_705_p2),33));
tmp_64_fu_974_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_954_p3) + unsigned(p_shl5_cast_fu_966_p3));
tmp_65_fu_1345_p1 <= k_reg_484(14 - 1 downto 0);
tmp_66_fu_1349_p2 <= std_logic_vector(unsigned(tmp_46_reg_1781) + unsigned(tmp_65_fu_1345_p1));
tmp_67_fu_1047_p2 <= std_logic_vector(unsigned(tmp_24_reg_1499) + unsigned(tmp_42_cast_fu_1043_p1));
tmp_68_fu_869_p2 <= std_logic_vector(unsigned(tmp_60_reg_1540) + unsigned(tmp_26_cast_fu_866_p1));
tmp_69_fu_846_p2 <= std_logic_vector(unsigned(tmp_60_reg_1540) + unsigned(tmp_33_cast_fu_842_p1));
tmp_6_fu_668_p1 <= i_3_reg_288(2 - 1 downto 0);
tmp_70_cast_fu_786_p1 <= std_logic_vector(resize(signed(tmp_47_fu_781_p2),64));
tmp_70_fu_856_p2 <= std_logic_vector(unsigned(tmp_16_reg_1489) + unsigned(tmp_33_cast7_fu_838_p1));
tmp_71_fu_1022_p2 <= std_logic_vector(unsigned(tmp_64_reg_1609) + unsigned(tmp_35_cast_fu_1019_p1));
tmp_72_fu_999_p2 <= std_logic_vector(unsigned(tmp_64_reg_1609) + unsigned(tmp_39_cast_fu_995_p1));
tmp_73_fu_1009_p2 <= std_logic_vector(unsigned(tmp_33_reg_1516) + unsigned(tmp_39_cast6_fu_991_p1));
tmp_74_cast_fu_945_p1 <= std_logic_vector(resize(signed(tmp_61_fu_940_p2),64));
tmp_74_fu_1095_p1 <= phi_mul_reg_427(9 - 1 downto 0);
tmp_75_fu_1116_p1 <= i_6_reg_416(2 - 1 downto 0);
tmp_76_fu_1071_p2 <= std_logic_vector(unsigned(tmp_24_reg_1499) + unsigned(tmp_46_cast_fu_1067_p1));
tmp_77_fu_1085_p2 <= std_logic_vector(unsigned(tmp_24_reg_1499) + unsigned(tmp_47_cast_fu_1081_p1));
tmp_78_cast_fu_1354_p1 <= std_logic_vector(resize(unsigned(tmp_66_fu_1349_p2),64));
tmp_78_fu_1134_p1 <= p_uOut_load_3_to_int_fu_1120_p1(23 - 1 downto 0);
tmp_79_cast_fu_874_p1 <= std_logic_vector(resize(unsigned(tmp_68_fu_869_p2),64));
tmp_79_fu_1151_p1 <= p_uOut_load_4_to_int_fu_1138_p1(23 - 1 downto 0);
tmp_7_fu_649_p2 <= "1" when (unsigned(i_3_reg_288) < unsigned(ST_numLayer_V_load_reg_1446)) else "0";
tmp_7_t_fu_1282_p2 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_4_fu_1278_p1));
tmp_80_cast_fu_851_p1 <= std_logic_vector(resize(unsigned(tmp_69_fu_846_p2),64));
tmp_80_fu_1245_p1 <= j_3_reg_438(9 - 1 downto 0);
tmp_81_cast_fu_861_p1 <= std_logic_vector(resize(signed(tmp_70_fu_856_p2),64));
tmp_81_fu_1249_p2 <= std_logic_vector(unsigned(tmp_74_reg_1683) + unsigned(tmp_80_fu_1245_p1));
tmp_82_cast_fu_1027_p1 <= std_logic_vector(resize(unsigned(tmp_71_fu_1022_p2),64));
tmp_83_cast_fu_1004_p1 <= std_logic_vector(resize(unsigned(tmp_72_fu_999_p2),64));
tmp_84_cast_fu_1014_p1 <= std_logic_vector(resize(signed(tmp_73_fu_1009_p2),64));
tmp_85_cast_fu_1052_p1 <= std_logic_vector(resize(signed(tmp_67_fu_1047_p2),64));
tmp_87_cast_fu_1076_p1 <= std_logic_vector(resize(signed(tmp_76_fu_1071_p2),64));
tmp_88_cast_fu_1090_p1 <= std_logic_vector(resize(signed(tmp_77_fu_1085_p2),64));
tmp_89_cast_fu_1254_p1 <= std_logic_vector(resize(unsigned(tmp_81_fu_1249_p2),64));
tmp_8_fu_644_p1 <= std_logic_vector(resize(unsigned(i_2_reg_277),64));
tmp_9_fu_1259_p2 <= "1" when (unsigned(i_1_reg_449) < unsigned(ST_numLayer_V_load_reg_1446)) else "0";
tmp_fu_611_p2 <= "1" when (P_mode_V = ap_const_lv8_1) else "0";
tmp_s_fu_1268_p1 <= tmp_s_fu_1268_p10(8 - 1 downto 0);
tmp_s_fu_1268_p10 <= std_logic_vector(resize(unsigned(i_1_reg_449),15));
tmp_s_fu_1268_p2 <= std_logic_vector(resize(unsigned(ap_const_lv15_23) * unsigned(tmp_s_fu_1268_p1), 15));
end behav;
|
gpl-3.0
|
2d341b6369cc319ddd5c44e8fcd7d9bd
| 0.629575 | 3.156534 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
sdram/SDRAM_Controller.vhd
| 1 | 27,469 |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 14:09:12 09/15/2013
-- Module Name: SDRAM_Controller - Behavioral
-- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
-- or Micron 48LC4M16A2-7E @ 100MHz
-- Revision:
-- Revision 0.1 - Initial version
-- Revision 0.2 - Removed second clock signal that isn't needed.
-- Revision 0.3 - Added back-to-back reads and writes.
-- Revision 0.4 - Allow refeshes to be delayed till next PRECHARGE is issued,
-- Unless they get really, really delayed. If a delay occurs multiple
-- refreshes might get pushed out, but it will have avioded about
-- 50% of the refresh overhead
-- Revision 0.5 - Add more paramaters to the design, allowing it to work for both the
-- Papilio Pro and Logi-Pi
-- Revision 0.6 - Fixed bugs in back-to-back reads (thanks Scotty!)
--
-- Worst case performance (single accesses to different rows or banks) is:
-- Writes 16 cycles = 6,250,000 writes/sec = 25.0MB/s (excluding refresh overhead)
-- Reads 17 cycles = 5,882,352 reads/sec = 23.5MB/s (excluding refresh overhead)
--
-- For 1:1 mixed reads and writes into the same row it is around 88MB/s
-- For reads or wries to the same it is can be as high as 184MB/s
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.NUMERIC_STD.ALL;
entity SDRAM_Controller is
generic (
sdram_address_width : natural;
sdram_column_bits : natural;
sdram_startup_cycles: natural;
cycles_per_refresh : natural;
delay_line_length : natural := 5; -- TH: configure data capture delay line length in clock cycles
hold_row_open : boolean := true -- TH: Hold active row open after read/write until a refresh is needed
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Interface to issue reads or write data
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC; -- is new data ready?
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
end SDRAM_Controller;
architecture Behavioral of SDRAM_Controller is
-- From page 37 of MT48LC16M16A2 datasheet
-- Name (Function) CS# RAS# CAS# WE# DQM Addr Data
-- COMMAND INHIBIT (NOP) H X X X X X X
-- NO OPERATION (NOP) L H H H X X X
-- ACTIVE L L H H X Bank/row X
-- READ L H L H L/H Bank/col X
-- WRITE L H L L L/H Bank/col Valid
-- BURST TERMINATE L H H L X X Active
-- PRECHARGE L L H L X Code X
-- AUTO REFRESH L L L H X X X
-- LOAD MODE REGISTER L L L L X Op-code X
-- Write enable X X X X L X Active
-- Write inhibit X X X X H X High-Z
-- Here are the commands mapped to constants
constant CMD_UNSELECTED : std_logic_vector(3 downto 0) := "1000";
constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant CMD_TERMINATE : std_logic_vector(3 downto 0) := "0110";
constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
constant CMD_REFRESH : std_logic_vector(3 downto 0) := "0001";
constant CMD_LOAD_MODE_REG : std_logic_vector(3 downto 0) := "0000";
constant MODE_REG : std_logic_vector(12 downto 0) :=
-- Reserved, wr bust, OpMode, CAS Latency (2), Burst Type, Burst Length (2)
"000" & "0" & "00" & "010" & "0" & "001";
signal iob_command : std_logic_vector( 3 downto 0) := CMD_NOP;
signal iob_address : std_logic_vector(12 downto 0) := (others => '0');
signal iob_data : std_logic_vector(15 downto 0) := (others => '0');
signal iob_dqm : std_logic_vector( 1 downto 0) := (others => '0');
signal iob_cke : std_logic := '0';
signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
attribute IOB: string;
attribute IOB of iob_command: signal is "true";
attribute IOB of iob_address: signal is "true";
attribute IOB of iob_dqm : signal is "true";
attribute IOB of iob_cke : signal is "true";
attribute IOB of iob_bank : signal is "true";
attribute IOB of iob_data : signal is "true";
signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
signal sdram_din : std_logic_vector(15 downto 0);
attribute IOB of captured_data : signal is "true";
type fsm_state is (s_startup,
s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
s_idle,
s_open_in_2, s_open_in_1,
s_write_1, s_write_2, s_write_3,
s_read_1, s_read_2, s_read_3, s_read_4,
s_active_idle, -- TH: Idle Wait with row active until a new transaction or refresh comes in
s_precharge
);
signal state : fsm_state := s_startup;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of state : signal is "ONE-HOT";
-- dual purpose counter, it counts up during the startup phase, then is used to trigger refreshes.
constant startup_refresh_max : unsigned(13 downto 0) := (others => '1');
signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
-- logic to decide when to refresh
signal pending_refresh : std_logic := '0';
signal forcing_refresh : std_logic := '0';
-- The incoming address is split into these three values
signal addr_row : std_logic_vector(12 downto 0) := (others => '0');
signal addr_col : std_logic_vector(12 downto 0) := (others => '0');
signal addr_bank : std_logic_vector( 1 downto 0) := (others => '0');
signal dqm_sr : std_logic_vector( 3 downto 0) := (others => '1'); -- an extra two bits in case CAS=3
-- signals to hold the requested transaction before it is completed
signal save_wr : std_logic := '0';
signal save_row : std_logic_vector(12 downto 0);
signal save_bank : std_logic_vector( 1 downto 0);
signal save_col : std_logic_vector(12 downto 0);
signal save_data_in : std_logic_vector(31 downto 0);
signal save_byte_enable : std_logic_vector( 3 downto 0);
-- control when new transactions are accepted
signal ready_for_new : std_logic := '0';
signal got_transaction : std_logic := '0';
signal can_back_to_back : std_logic := '0';
-- signal to control the Hi-Z state of the DQ bus
signal iob_dq_hiz : std_logic := '1';
-- signals for when to read the data off of the bus
-- signal data_ready_delay : std_logic_vector( 4 downto 0);
--signal data_ready_delay : std_logic_vector( 3 downto 0);
-- TH: make this configurable
signal data_ready_delay : std_logic_vector( delay_line_length-1 downto 0);
-- bit indexes used when splitting the address into row/colum/bank.
constant start_of_col : natural := 0;
constant end_of_col : natural := sdram_column_bits-2;
constant start_of_bank : natural := sdram_column_bits-1;
constant end_of_bank : natural := sdram_column_bits;
constant start_of_row : natural := sdram_column_bits+1;
constant end_of_row : natural := sdram_address_width-2;
constant prefresh_cmd : natural := 10;
begin
-- Indicate the need to refresh when the counter is 2048,
-- Force a refresh when the counter is 4096 - (if a refresh is forced,
-- multiple refresshes will be forced until the counter is below 2048
pending_refresh <= startup_refresh_count(11);
forcing_refresh <= startup_refresh_count(12);
-- tell the outside world when we can accept a new transaction;
cmd_ready <= ready_for_new;
----------------------------------------------------------------------------
-- Seperate the address into row / bank / address
----------------------------------------------------------------------------
addr_row(end_of_row-start_of_row downto 0) <= cmd_address(end_of_row downto start_of_row); -- 12:0 <= 20:9
addr_bank <= cmd_address(end_of_bank downto start_of_bank); -- 1:0 <= 8:7
addr_col(sdram_column_bits-1 downto 0) <= cmd_address(end_of_col downto start_of_col) & '0'; -- 7:0 <= 6:0 & '0'
-----------------------------------------------------------
-- Forward the SDRAM clock to the SDRAM chip - 180 degress
-- out of phase with the control signals (ensuring setup and holdup
-----------------------------------------------------------
sdram_clk_forward : ODDR2
generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")
port map (Q => sdram_clk, C0 => clk, C1 => not clk, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1');
-----------------------------------------------
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--!! Ensure that all outputs are registered. !!
--!! Check the pinout report to be sure !!
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-----------------------------------------------
sdram_cke <= iob_cke;
sdram_CS <= iob_command(3);
sdram_RAS <= iob_command(2);
sdram_CAS <= iob_command(1);
sdram_WE <= iob_command(0);
sdram_dqm <= iob_dqm;
sdram_ba <= iob_bank;
sdram_addr <= iob_address;
---------------------------------------------------------------
-- Explicitly set up the tristate I/O buffers on the DQ signals
---------------------------------------------------------------
iob_dq_g: for i in 0 to 15 generate
begin
iob_dq_iob: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map ( O => sdram_din(i), IO => sdram_data(i), I => iob_data(i), T => iob_dq_hiz);
end generate;
capture_proc: process(clk)
begin
if rising_edge(clk) then
captured_data <= sdram_din;
end if;
end process;
main_proc: process(clk)
begin
if rising_edge(clk) then
captured_data_last <= captured_data;
------------------------------------------------
-- Default state is to do nothing
------------------------------------------------
iob_command <= CMD_NOP;
iob_address <= (others => '0');
iob_bank <= (others => '0');
------------------------------------------------
-- countdown for initialisation & refresh
------------------------------------------------
startup_refresh_count <= startup_refresh_count+1;
-------------------------------------------------------------------
-- It we are ready for a new tranasction and one is being presented
-- then accept it. Also remember what we are reading or writing,
-- and if it can be back-to-backed with the last transaction
-------------------------------------------------------------------
if ready_for_new = '1' and cmd_enable = '1' then
if save_bank = addr_bank and save_row = addr_row then
can_back_to_back <= '1';
else
can_back_to_back <= '0';
end if;
save_row <= addr_row;
save_bank <= addr_bank;
save_col <= addr_col;
save_wr <= cmd_wr;
save_data_in <= cmd_data_in;
save_byte_enable <= cmd_byte_enable;
got_transaction <= '1';
ready_for_new <= '0';
end if;
------------------------------------------------
-- Handle the data coming back from the
-- SDRAM for the Read transaction
------------------------------------------------
data_out_ready <= '0';
if data_ready_delay(0) = '1' then
data_out <= captured_data & captured_data_last;
data_out_ready <= '1';
end if;
----------------------------------------------------------------------------
-- update shift registers used to choose when to present data to/from memory
----------------------------------------------------------------------------
data_ready_delay <= '0' & data_ready_delay(data_ready_delay'high downto 1);
iob_dqm <= dqm_sr(1 downto 0);
dqm_sr <= "11" & dqm_sr(dqm_sr'high downto 2);
case state is
when s_startup =>
------------------------------------------------------------------------
-- This is the initial startup state, where we wait for at least 100us
-- before starting the start sequence
--
-- The initialisation is sequence is
-- * de-assert SDRAM_CKE
-- * 100us wait,
-- * assert SDRAM_CKE
-- * wait at least one cycle,
-- * PRECHARGE
-- * wait 2 cycles
-- * REFRESH,
-- * tREF wait
-- * REFRESH,
-- * tREF wait
-- * LOAD_MODE_REG
-- * 2 cycles wait
------------------------------------------------------------------------
iob_CKE <= '1';
-- All the commands during the startup are NOPS, except these
if startup_refresh_count = startup_refresh_max-31 then
-- ensure all rows are closed
iob_command <= CMD_PRECHARGE;
iob_address(prefresh_cmd) <= '1'; -- all banks
iob_bank <= (others => '0');
elsif startup_refresh_count = startup_refresh_max-23 then
-- these refreshes need to be at least tREF (66ns) apart
iob_command <= CMD_REFRESH;
elsif startup_refresh_count = startup_refresh_max-15 then
iob_command <= CMD_REFRESH;
elsif startup_refresh_count = startup_refresh_max-7 then
-- Now load the mode register
iob_command <= CMD_LOAD_MODE_REG;
iob_address <= MODE_REG;
end if;
------------------------------------------------------
-- if startup is coomplete then go into idle mode,
-- get prepared to accept a new command, and schedule
-- the first refresh cycle
------------------------------------------------------
if startup_refresh_count = 0 then
state <= s_idle;
ready_for_new <= '1';
got_transaction <= '0';
startup_refresh_count <= to_unsigned(2048 - cycles_per_refresh+1,14);
end if;
when s_idle_in_6 => state <= s_idle_in_5;
when s_idle_in_5 => state <= s_idle_in_4;
when s_idle_in_4 => state <= s_idle_in_3;
when s_idle_in_3 => state <= s_idle_in_2;
when s_idle_in_2 => state <= s_idle_in_1;
when s_idle_in_1 => state <= s_idle;
when s_idle =>
-- Priority is to issue a refresh if one is outstanding
if pending_refresh = '1' or forcing_refresh = '1' then
------------------------------------------------------------------------
-- Start the refresh cycle.
-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
------------------------------------------------------------------------
state <= s_idle_in_6;
iob_command <= CMD_REFRESH;
startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
elsif got_transaction = '1' then
--------------------------------
-- Start the read or write cycle.
-- First task is to open the row
--------------------------------
state <= s_open_in_2;
iob_command <= CMD_ACTIVE;
iob_address <= save_row;
iob_bank <= save_bank;
end if;
--------------------------------------------
-- Opening the row ready for reads or writes
--------------------------------------------
when s_open_in_2 => state <= s_open_in_1;
when s_open_in_1 =>
-- still waiting for row to open
if save_wr = '1' then
state <= s_write_1;
iob_dq_hiz <= '0';
iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
else
iob_dq_hiz <= '1';
state <= s_read_1;
end if;
-- we will be ready for a new transaction next cycle!
ready_for_new <= '1';
got_transaction <= '0';
----------------------------------
-- Processing the read transaction
----------------------------------
when s_read_1 =>
state <= s_read_2;
iob_command <= CMD_READ;
iob_address <= save_col;
iob_bank <= save_bank;
iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
-- Schedule reading the data values off the bus
data_ready_delay(data_ready_delay'high) <= '1';
-- Set the data masks to read all bytes
iob_dqm <= (others => '0');
dqm_sr(1 downto 0) <= (others => '0');
when s_read_2 =>
state <= s_read_3;
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
end if;
when s_read_3 =>
state <= s_read_4;
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
end if;
when s_read_4 =>
-- can we do back-to-back read?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
else
state <= s_open_in_2; -- we have to wait for the read data to come back before we swutch the bus into HiZ
end if;
else
if hold_row_open then --NEW TH: Go in into s_active_ilde state
state <= s_active_idle;
else
state <= s_precharge;
end if;
end if;
------------------------------------------------------------------
-- Processing the write transaction
-------------------------------------------------------------------
when s_write_1 =>
state <= s_write_2;
iob_command <= CMD_WRITE;
iob_address <= save_col;
iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
iob_bank <= save_bank;
iob_dqm <= NOT save_byte_enable(1 downto 0);
dqm_sr(1 downto 0) <= NOT save_byte_enable(3 downto 2);
iob_data <= save_data_in(15 downto 0);
iob_data_next <= save_data_in(31 downto 16);
when s_write_2 =>
state <= s_write_3;
iob_data <= iob_data_next;
-- can we do a back-to-back write?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
end if;
-- Although it looks right in simulation you can't go write-to-read
-- here due to bus contention, as iob_dq_hiz takes a few ns.
end if;
when s_write_3 => -- must wait tRDL, hence the extra idle state
-- back to back transaction?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
else
-- write-to-read switch?
state <= s_read_1;
iob_dq_hiz <= '1';
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
else
iob_dq_hiz <= '1';
if hold_row_open then --NEW TH: Go in into s_active_ilde state
state <= s_active_idle;
else
state <= s_precharge;
end if;
end if;
-------------------------------------------------------------------
-- Closing the row off (this closes all banks)
-------------------------------------------------------------------
when s_precharge =>
state <= s_idle_in_3;
iob_command <= CMD_PRECHARGE;
iob_address(prefresh_cmd) <= '1'; -- A10 actually matters - it selects all banks or just one
-------------------------------------------------------------------
-- TH: Wait with open row
-------------------------------------------------------------------
when s_active_idle =>
if forcing_refresh='1' or pending_refresh='1' or
(got_transaction='1' and can_back_to_back='0') then
-- when either refresh is needed or next transaction is in a different row
-- go to precharge
state <= s_precharge;
elsif got_transaction='1' then -- Transaction in same row
if save_wr='1' then
state <= s_write_1;
iob_dq_hiz <= '0';
iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
else
state <= s_read_1;
iob_dq_hiz <= '1';
end if;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
-------------------------------------------------------------------
-- We should never get here, but if we do then reset the memory
-------------------------------------------------------------------
when others =>
state <= s_startup;
ready_for_new <= '0';
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
end case;
if reset = '1' then -- Sync reset
state <= s_startup;
ready_for_new <= '0';
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
8bd5017de2cb4d8f176c54eedd4f9430
| 0.440278 | 4.452748 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_ST_WandB.vhd
| 4 | 3,121 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
gpl-3.0
|
a7287ba288d255ce1ca38ce4cb7ad82b
| 0.54694 | 3.62907 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fadd_3_full_dsp_32.vhd
| 4 | 12,788 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fadd_3_full_dsp_32;
ARCHITECTURE feedforward_ap_fadd_3_full_dsp_32_arch OF feedforward_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fadd_3_full_dsp_32_arch;
|
gpl-3.0
|
dadbdff7a294480f903b3b7f4bf35dab
| 0.652174 | 3.023883 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
wishbone_burst_mem_interface.vhd
| 1 | 4,037 |
----------------------------------------------------------------------------------
-- Module Name: wbs_memory_interface - Behavioral
-- The Bonfire Processor Project, (c) 2016,2017 Thomas Hornschuh
-- License: See LICENSE or LICENSE.txt File in git project root.
--
--
-- Wishbone interface for Block RAMs with Wishbone Burst support
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wbs_memory_interface is
generic (
ram_adr_width : natural;
ram_size : natural;
wbs_adr_high : natural := 27;
RamFileName : string := "meminit.ram";
mode : string := "B";
Swapbytes : boolean := true -- SWAP Bytes in RAM word in low byte first order to use data2mem
-- UseBRAMPrimitives : boolean := TRUE
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(wbs_adr_high downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
wbs_cti_i: in std_logic_vector(2 downto 0)
);
end wbs_memory_interface;
architecture Behavioral of wbs_memory_interface is
constant slave_adr_high : natural := 29;
-- Slaves
-- RAM
signal ram_adr,ram_adr_o : std_logic_vector(ram_adr_width-1 downto 0);
signal ram_a_we: std_logic_vector(3 downto 0);
signal is_read,ack_read, ack_write : std_logic;
signal adr_reg : std_logic_vector(ram_adr_width-1 downto 0); -- for Burst mode support
begin
ram_adr <= wbs_adr_i(ram_adr_width+1 downto 2);
is_read <= wbs_cyc_i and wbs_stb_i and not wbs_we_i;
-- Wishbone ACK
process (clk_i) is
begin
if rising_edge(clk_i) then
if ack_read='1' and wbs_cti_i/="010" then -- clear ack at end of cycle
ack_read <= '0';
else
ack_read<= is_read;
end if;
end if;
end process;
ack_write<=wbs_cyc_i and wbs_stb_i and wbs_we_i;
wbs_ack_o<=ack_read or ack_write;
-- Burst Mode support
process(clk_i) is
begin
if rising_edge(clk_i) then
if is_read='1' and wbs_cti_i="010" then -- burst cycle ??
if ack_read='0' then -- begin of new cycle
adr_reg <= std_logic_vector(unsigned(ram_adr)+1);
else
adr_reg <= std_logic_vector(unsigned(adr_reg)+1);
end if;
end if;
end if;
end process;
-- adr multiplexer
process(ram_adr,adr_reg,is_read,ack_read,wbs_cti_i) is
begin
if is_read='1' and ack_read='1' and (wbs_cti_i="010" or wbs_cti_i="111") then
ram_adr_o <= adr_reg;
else
ram_adr_o <= ram_adr;
end if;
end process;
-- RAM WREN Signals
gen_ram_a_we: for i in 3 downto 0 generate
ram_a_we(i)<='1' when wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' and wbs_sel_i(i)='1'
else '0';
end generate;
-- genericMainMemory: if not UseBRAMPrimitives generate
ram: entity work.MainMemory
generic map (
ADDR_WIDTH =>ram_adr_width,
SIZE => ram_size,
RamFileName => RamFileName,
mode => mode,
Swapbytes => Swapbytes,
EnableSecondPort => false
)
PORT MAP(
DBOut =>wbs_dat_o,
DBIn => wbs_dat_i,
AdrBus => ram_adr_o,
ENA => wbs_cyc_i,
WREN => ram_a_we,
CLK => clk_i,
CLKB =>clk_i ,
ENB =>'0' ,
AdrBusB =>(others=>'0'),
DBOutB => open
);
end Behavioral;
|
gpl-3.0
|
080560ab02588b0db644ad5e76bda706
| 0.565767 | 3.412511 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
obsolete/papro_bus.vhd
| 1 | 4,285 |
---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Sun May 7 18:23:19 2017
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 3
-- Master address width: 32
-- Slave address width: 26
-- Port size: 32
-- Port granularity: 8
-- Entity name: papro_bus
-- Pipelined arbiter: no
-- Registered feedback: yes
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e papro_bus -r 1 3 32 26 32 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity papro_bus is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_sel_i: in std_logic_vector(3 downto 0);
s0_cti_i: in std_logic_vector(2 downto 0);
s0_bte_i: in std_logic_vector(1 downto 0);
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(31 downto 2);
s0_dat_i: in std_logic_vector(31 downto 0);
s0_dat_o: out std_logic_vector(31 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_sel_o: out std_logic_vector(3 downto 0);
m0_cti_o: out std_logic_vector(2 downto 0);
m0_bte_o: out std_logic_vector(1 downto 0);
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(25 downto 2);
m0_dat_o: out std_logic_vector(31 downto 0);
m0_dat_i: in std_logic_vector(31 downto 0);
m1_cyc_o: out std_logic;
m1_stb_o: out std_logic;
m1_we_o: out std_logic;
m1_sel_o: out std_logic_vector(3 downto 0);
m1_cti_o: out std_logic_vector(2 downto 0);
m1_bte_o: out std_logic_vector(1 downto 0);
m1_ack_i: in std_logic;
m1_adr_o: out std_logic_vector(25 downto 2);
m1_dat_o: out std_logic_vector(31 downto 0);
m1_dat_i: in std_logic_vector(31 downto 0);
m2_cyc_o: out std_logic;
m2_stb_o: out std_logic;
m2_we_o: out std_logic;
m2_sel_o: out std_logic_vector(3 downto 0);
m2_cti_o: out std_logic_vector(2 downto 0);
m2_bte_o: out std_logic_vector(1 downto 0);
m2_ack_i: in std_logic;
m2_adr_o: out std_logic_vector(25 downto 2);
m2_dat_o: out std_logic_vector(31 downto 0);
m2_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of papro_bus is
signal select_slave: std_logic_vector(3 downto 0);
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal sel_mux: std_logic_vector(3 downto 0);
signal cti_mux: std_logic_vector(2 downto 0);
signal bte_mux: std_logic_vector(1 downto 0);
signal adr_mux: std_logic_vector(31 downto 2);
signal wdata_mux: std_logic_vector(31 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(31 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
sel_mux<=s0_sel_i;
cti_mux<=s0_cti_i;
bte_mux<=s0_bte_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
select_slave<="0001" when adr_mux(31 downto 26)="000000" else
"0010" when adr_mux(31 downto 26)="000001" else
"0100" when adr_mux(31 downto 26)="000010" else
"1000"; -- fallback slave
m0_cyc_o<=cyc_mux and select_slave(0);
m0_stb_o<=stb_mux and select_slave(0);
m0_we_o<=we_mux;
m0_sel_o<=sel_mux;
m0_cti_o<=cti_mux;
m0_bte_o<=bte_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
m1_cyc_o<=cyc_mux and select_slave(1);
m1_stb_o<=stb_mux and select_slave(1);
m1_we_o<=we_mux;
m1_sel_o<=sel_mux;
m1_cti_o<=cti_mux;
m1_bte_o<=bte_mux;
m1_adr_o<=adr_mux(m1_adr_o'range);
m1_dat_o<=wdata_mux;
m2_cyc_o<=cyc_mux and select_slave(2);
m2_stb_o<=stb_mux and select_slave(2);
m2_we_o<=we_mux;
m2_sel_o<=sel_mux;
m2_cti_o<=cti_mux;
m2_bte_o<=bte_mux;
m2_adr_o<=adr_mux(m2_adr_o'range);
m2_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=(m0_ack_i and select_slave(0)) or
(m1_ack_i and select_slave(1)) or
(m2_ack_i and select_slave(2)) or
(cyc_mux and stb_mux and select_slave(3)); -- fallback slave
rdata_mux_gen: for i in rdata_mux'range generate
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
(m1_dat_i(i) and select_slave(1)) or
(m2_dat_i(i) and select_slave(2));
end generate;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
|
gpl-3.0
|
d7cc5352c64719f2fedba767cd3c56e3
| 0.636406 | 2.371334 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
busconnect.vhd
| 1 | 4,259 |
---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Tue Oct 18 18:55:26 2016
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 4
-- Master address width: 32
-- Slave address width: 28
-- Port size: 32
-- Port granularity: 8
-- Entity name: busconnect
-- Pipelined arbiter: no
-- Registered feedback: no
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e busconnect 1 4 32 28 32 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity busconnect is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_sel_i: in std_logic_vector(3 downto 0);
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(31 downto 2);
s0_dat_i: in std_logic_vector(31 downto 0);
s0_dat_o: out std_logic_vector(31 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_sel_o: out std_logic_vector(3 downto 0);
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(27 downto 2);
m0_dat_o: out std_logic_vector(31 downto 0);
m0_dat_i: in std_logic_vector(31 downto 0);
m1_cyc_o: out std_logic;
m1_stb_o: out std_logic;
m1_we_o: out std_logic;
m1_sel_o: out std_logic_vector(3 downto 0);
m1_ack_i: in std_logic;
m1_adr_o: out std_logic_vector(27 downto 2);
m1_dat_o: out std_logic_vector(31 downto 0);
m1_dat_i: in std_logic_vector(31 downto 0);
m2_cyc_o: out std_logic;
m2_stb_o: out std_logic;
m2_we_o: out std_logic;
m2_sel_o: out std_logic_vector(3 downto 0);
m2_ack_i: in std_logic;
m2_adr_o: out std_logic_vector(27 downto 2);
m2_dat_o: out std_logic_vector(31 downto 0);
m2_dat_i: in std_logic_vector(31 downto 0);
m3_cyc_o: out std_logic;
m3_stb_o: out std_logic;
m3_we_o: out std_logic;
m3_sel_o: out std_logic_vector(3 downto 0);
m3_ack_i: in std_logic;
m3_adr_o: out std_logic_vector(27 downto 2);
m3_dat_o: out std_logic_vector(31 downto 0);
m3_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of busconnect is
signal select_slave: std_logic_vector(4 downto 0);
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal sel_mux: std_logic_vector(3 downto 0);
signal adr_mux: std_logic_vector(31 downto 2);
signal wdata_mux: std_logic_vector(31 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(31 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
sel_mux<=s0_sel_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
select_slave<="00001" when adr_mux(31 downto 28)="0000" else
"00010" when adr_mux(31 downto 28)="0001" else
"00100" when adr_mux(31 downto 28)="0010" else
"01000" when adr_mux(31 downto 28)="0011" else
"10000"; -- fallback slave
m0_cyc_o<=cyc_mux and select_slave(0);
m0_stb_o<=stb_mux and select_slave(0);
m0_we_o<=we_mux;
m0_sel_o<=sel_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
m1_cyc_o<=cyc_mux and select_slave(1);
m1_stb_o<=stb_mux and select_slave(1);
m1_we_o<=we_mux;
m1_sel_o<=sel_mux;
m1_adr_o<=adr_mux(m1_adr_o'range);
m1_dat_o<=wdata_mux;
m2_cyc_o<=cyc_mux and select_slave(2);
m2_stb_o<=stb_mux and select_slave(2);
m2_we_o<=we_mux;
m2_sel_o<=sel_mux;
m2_adr_o<=adr_mux(m2_adr_o'range);
m2_dat_o<=wdata_mux;
m3_cyc_o<=cyc_mux and select_slave(3);
m3_stb_o<=stb_mux and select_slave(3);
m3_we_o<=we_mux;
m3_sel_o<=sel_mux;
m3_adr_o<=adr_mux(m3_adr_o'range);
m3_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=(m0_ack_i and select_slave(0)) or
(m1_ack_i and select_slave(1)) or
(m2_ack_i and select_slave(2)) or
(m3_ack_i and select_slave(3)) or
(cyc_mux and stb_mux and select_slave(4)); -- fallback slave
rdata_mux_gen: for i in rdata_mux'range generate
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
(m1_dat_i(i) and select_slave(1)) or
(m2_dat_i(i) and select_slave(2)) or
(m3_dat_i(i) and select_slave(3));
end generate;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
|
gpl-3.0
|
39d106658159ef2934558a3060688394
| 0.635595 | 2.376674 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
sdram/mt48lc16m16a2.vhd
| 1 | 67,309 |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
--library grlib;
--use grlib.stdlib.all;
--library gaisler;
--use gaisler.sim.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if true then
hread(l, recdata);
Bank_Load := to_bitvector ( recaddr(25 downto 24));
Rows_Load := to_bitvector(recaddr(23 downto 11));
Cols_Load := to_bitvector( recaddr(10 downto 2));
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & to_bitvector(recdata(i*32+index to i*32+index+15)));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & to_bitvector(recdata(i*32+index to i*32+index+15)));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & to_bitvector(recdata(i*32+index to i*32+index+15)));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & to_bitvector(recdata(i*32+index to i*32+index+15)));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
gpl-3.0
|
e55ddde017e71422dd9839340907947d
| 0.430596 | 4.099208 | false | false | false | false |
sharebrained/portapack-hackrf
|
hardware/portapack_h1/cpld/20150901/top.vhd
| 2 | 4,891 |
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
469a0ac4bda41547275f9f422969ad7d
| 0.647107 | 2.550052 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt
|
kr_fuzman_tb.vhd
| 1 | 2,928 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity kr_fuzman_tb is
end kr_fuzman_tb;
architecture behav of kr_fuzman_tb is
component kr_fuzman_system2 is
port
( clock : in std_logic;
V_mux_sel,Z_mux_sel : in std_logic;
V_load,V_load1,V_load2 : in std_logic;
Z_load,Z_load1,Z_load2 : in std_logic;
Vref_enable,Vref_load : in std_logic;
Ut_enable,Ut_load : in std_logic;
Vtminusone : in std_logic_vector(31 downto 0);
Ztminusone : in std_logic_vector(31 downto 0);
Vt : out std_logic_vector(31 downto 0);
Zt : out std_logic_vector(31 downto 0)
);
end component;
signal clock,V_mux_sel,Z_mux_sel,V_load,V_load1,V_load2,Z_load,Z_load1,Z_load2,Vref_enable,Vref_load,Ut_enable,Ut_load : std_logic := '0';
signal Vtminusone,Ztminusone : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal Vt,Zt : std_logic_vector(31 downto 0);
constant clk_period : time := 100 ps;
begin
uut: kr_fuzman_system2 port map
( clock => clock,
V_mux_sel => V_mux_sel,
Z_mux_sel => Z_mux_sel,
V_load => V_load,
V_load1 => V_load1,
V_load2 => V_load2,
Z_load => Z_load,
Z_load1 => Z_load1,
Z_load2 => Z_load2,
Vref_enable => Vref_enable,
Vref_load => Vref_load,
Ut_enable => Ut_enable,
Ut_load => Ut_load,
Vtminusone => Vtminusone,
Ztminusone => Ztminusone,
Vt => Vt,
Zt => Zt);
clk_process : process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
stim_proc : process
begin
wait for 100 ps;
Vtminusone <= "01000001101010000000000000000000";
Ztminusone <= "00111111011111010111000010100100";
Vref_enable <= '1';
Ut_enable <= '1';
wait for 100 ps;
V_load <= '1';
Z_load <= '1';
Vref_load <= '1';
Ut_load <= '1';
wait for 100 ps;
V_load1 <= '1';
Z_load1 <= '1';
V_load2 <= '1';
Z_load2 <= '1';
-- Vtminusone <= Vt;
-- Ztminusone <= Zt;
wait for 100 ps;
V_mux_sel <= '1';
Z_mux_sel <='1';
wait;
end process;
end;
|
mit
|
455b2cac3a0a16834a9e8f354c6ecb51
| 0.446721 | 4.005472 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
| 24 | 86,743 |
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62080)
`protect data_block
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eNG6P2yWrR+WNjU2bzCcT8Y5CM7oGrjxVC+jfll6Jgo9R/aqMjCLQNW/zOLqO3LUkmbCB/dNg4xb
rDoex4Kchbg6fkjn5kTEclp8w7R7j/Jptz8DcWSSASXGT3knKVIsXSGFEbIdRIlTewNFyAuO2hGl
ntt4kVM8W8wJZ7g49o3dGCN03vqHZ1b3SG646lSN6HX5lqbCOmzRe1R3NTor3Z0qbiWl8MUGMyHk
wXbYoHAUt8ZxbP4/kuEQgjjrT5aBFEeRO6wbd4SDU5T3+RQPp8PSG74WvzOVCUMQh8boZam36uTX
sHO086N89g==
`protect end_protected
|
gpl-3.0
|
3f4bcc213b67ab38850d6ff0488608b8
| 0.952134 | 1.834511 | false | false | false | false |
Rookfighter/aes-ss17
|
ex03/i2c_slave_write_tb.vhd
| 1 | 6,507 |
-- i2c_slave_tb.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity i2c_slave_write_tb is
end entity;
architecture behavior of i2c_slave_write_tb is
-- Component Declaration for the Unit Under Test (UUT)
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0); -- rx, data received
rx_recv: out std_logic; -- rx received, high active
busy: out std_logic; -- busy, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end component;
--Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal tx_data: std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal sda: std_logic := '1';
signal scl: std_logic := '1';
--Outputs
signal tx_sent: std_logic;
signal rx_data: std_logic_vector(7 downto 0);
signal rx_recv: std_logic;
signal busy: std_logic;
-- Clock period definitions
constant clk_period: time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave
generic map(RSTDEF => '0',
ADDRDEF => "0010111") -- address 0x17
port map(rst => rst,
clk => clk,
tx_data => tx_data,
tx_sent => tx_sent,
rx_data => rx_data,
rx_recv => rx_recv,
busy => busy,
sda => sda,
scl => scl);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- sends a single bit over I2C
procedure send_bit(tosend: std_logic) is
begin
scl <= '0';
sda <= tosend;
-- wait for delay element to take over new value
wait for 24*clk_period;
-- allow slave to read
scl <= '1';
wait for clk_period;
end procedure;
-- receive a single bit over I2C
procedure recv_bit is
begin
scl <= '0';
sda <= 'Z';
wait for clk_period;
scl <= '1';
wait for clk_period;
end procedure;
-- sends start / repeated start condition over I2C
procedure send_start is
begin
send_bit('1');
-- rise sda without changing clk
sda <= '0';
wait for 25*clk_period;
end procedure;
-- sends stop condition over I2C
procedure send_stop is
begin
send_bit('0');
-- rise sda without changing clk
sda <= '1';
wait for 25*clk_period;
end procedure;
-- wait for an ack from slave over I2C
procedure wait_ack is
begin
send_bit('Z');
-- wait additional cycle for slave to release SDA again
scl <= '0';
wait for clk_period;
end procedure;
-- send ack to slave
procedure send_ack is
begin
send_bit('0');
end procedure;
-- send nack to slave
procedure send_nack is
begin
send_bit('1');
end procedure;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
-- init transmission
send_start;
-- send correct address
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('0'); -- direction bit
-- slave should send ack
wait_ack;
-- send data
send_bit('1'); -- data bit 1
send_bit('1'); -- data bit 2
send_bit('0'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('1'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('0'); -- data bit 7
send_bit('1'); -- data bit 8
-- rx_data should be "11001101"
-- rx_recv should '1' for one cylce
-- slave should send ack
wait_ack;
-- send data
send_bit('1'); -- data bit 1
send_bit('0'); -- data bit 2
send_bit('1'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('0'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('1'); -- data bit 7
send_bit('0'); -- data bit 8
-- rx_data should be "10100110"
-- rx_recv should '1' for one cylce
-- slave should send ack
wait_ack;
-- terminate transmission
send_stop;
-- init next transmission
send_start;
-- send wrong address 0x13
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('0'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('0'); -- direction bit
-- slave should send no ack and go back to idle mode
wait_ack;
-- send data
-- slave should not record it
send_bit('0'); -- data bit 1
send_bit('0'); -- data bit 2
send_bit('1'); -- data bit 3
send_bit('0'); -- data bit 4
send_bit('0'); -- data bit 5
send_bit('1'); -- data bit 6
send_bit('0'); -- data bit 7
send_bit('1'); -- data bit 8
-- slave should send no ack and go back to idle mode
wait_ack;
-- terminate transmission
send_stop;
wait for clk_period*10;
wait;
end process;
end;
|
gpl-3.0
|
b24c20bce46ec5848c585212d148727c
| 0.487629 | 4.039106 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fadd_3_full_dsp_32/synth/ANN_ap_fadd_3_full_dsp_32.vhd
| 1 | 12,694 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
|
gpl-3.0
|
5fe5bd4dc0101819096794e7ae9a20c2
| 0.649598 | 3.003075 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fptrunc_64ns_32_1.vhd
| 6 | 1,942 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fptrunc_64ns_32_1 is
generic (
ID : integer := 4;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component ANN_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fptrunc_0_no_dsp_64_u : component ANN_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
|
gpl-3.0
|
cfe031d560aff91a40d96bcd3dc8b26f
| 0.490731 | 3.65725 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fpext_32ns_64_1.vhd
| 6 | 1,932 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fpext_32ns_64_1 is
generic (
ID : integer := 5;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 64
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fpext_32ns_64_1 is
--------------------- Component ---------------------
component ANN_ap_fpext_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fpext_0_no_dsp_32_u : component ANN_ap_fpext_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
|
gpl-3.0
|
10835974c25702a592d8ea85008c60bb
| 0.488095 | 3.638418 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt
|
kr_fuzman_Ut.vhd
| 1 | 1,585 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Ut is
port (clock : in std_logic;
Ut_enable : in std_logic;
Ut : out std_logic_vector(31 downto 0)
);
end kr_fuzman_Ut;
architecture behav of kr_fuzman_Ut is
signal i : integer range 0 to 19:=0; -- change the range value
signal enable : std_logic:='0';
type lut is array ( 0 to 3**3 - 8) of std_logic_vector(31 downto 0);
constant my_lut : lut := (
0 => "00111110110101110000101000111101",
1 => "01000001100011110111000010100100",
2 => "01000000111111000100111010100101",
3 => "01000001000001110001000011001011",
4 => "11000000001000010100011110101110",
5 => "01000000101101010111000010100100",
6 => "01000001000101101110000101001000",
7 => "01000001011111000011110101110001",
8 => "01000001001101100101110000101001",
9 => "01000000100100100011110101110001",
10 => "01000000010001101101010000101100",
11 => "01000000111001110000011000100101",
12 => "01000000101101000111000100001101",
13 => "01000000111101110101111010011110",
14 => "01000000100110001011100100100100",
15 => "01000001011011101011001011111111",
16 => "01000000110101100111111111001100",
17 => "11000001111001100111000010100100",
18 => "11000001001100001010110000001000",
19 => "01000010000111111010111000010100"
);
begin
process (Ut_enable)
begin
if Ut_enable'event and Ut_enable = '1' then
enable <= '1';
end if;
end process;
process (clock)
begin
if rising_edge (clock) then
if (enable = '1') then
if (i <= 19) then
Ut <= my_lut(i);
i <= i + 1;
end if;
end if;
end if;
end process;
end behav;
|
mit
|
c19207860332e41ec6ffc4c9c3c07efb
| 0.732492 | 3.577878 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/TEST_hls_example_1_0/hdl/vhdl/example_C.vhd
| 1 | 3,038 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity example_C_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 6;
mem_size : integer := 50
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of example_C_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity example_C is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 50;
AddressWidth : INTEGER := 6);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of example_C is
component example_C_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
example_C_ram_U : component example_C_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
gpl-3.0
|
1fba72f2a947ba58cef8dfa2e754f4b9
| 0.536866 | 3.591017 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
sdram/wbs_sdram_interface.vhd
| 1 | 7,380 |
----------------------------------------------------------------------------------
-- Module Name: wbs_sdram_interface - Behavioral
-- The Bonfire Processor Project, (c) 2016,2017 Thomas Hornschuh
--
-- License: See LICENSE or LICENSE.txt File in git project root.
--
-- Wishbone Interface for Hamsterworks SDRAM Controller, Supports Wishbone Burst mode extensions
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.log2.all;
entity wbs_sdram_interface is
generic (
wbs_adr_high : natural := 27;
sdram_address_width : natural := 22;
sdram_column_bits : natural := 8;
sdram_startup_cycles: natural := 10100; -- 100us, plus a little more
cycles_per_refresh : natural := (64000*100)/4196-1;
wbs_burst_length : natural := 4 -- length of wishbone burst cylces
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(wbs_adr_high downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
wbs_cti_i: in std_logic_vector(2 downto 0);
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0)
);
end wbs_sdram_interface;
architecture Behavioral of wbs_sdram_interface is
-- signals to interface with the memory controller
signal cmd_address : std_logic_vector(sdram_address_width-2 downto 0);
signal cmd_wr : std_logic;
signal cmd_enable : std_logic;
signal cmd_byte_enable : std_logic_vector(3 downto 0);
signal cmd_data_in : std_logic_vector(31 downto 0);
signal cmd_ready : std_logic;
signal data_out : std_logic_vector(31 downto 0);
signal data_out_ready : std_logic;
signal read_pending : std_logic := '0';
signal ram_adr : std_logic_vector(sdram_address_width-2 downto 0);
signal is_read : std_logic;
-- Wishbone Burst mode support
signal burst : std_logic := '0'; -- Wishbone burst active
signal burstfetch_enable : std_logic; -- prefetching enable in burst
signal adr_reg : std_logic_vector(sdram_address_width-2 downto 0); -- for Burst mode support
signal burst_counter : unsigned(log2(wbs_burst_length)-1 downto 0) := (others=>'0'); -- Countdown for WBS burst cycles
signal pending_read_counter : unsigned(log2(wbs_burst_length)-1 downto 0) := (others=>'0'); -- Outstanding reads
signal orphan_read : std_logic := '0'; -- Flag: outstanding reads after burst cycle has ended
signal burst_disable : boolean := true;
begin
Inst_SDRAM_Controller: entity work.SDRAM_Controller
generic map (
sdram_address_width =>sdram_address_width,
sdram_column_bits => sdram_column_bits,
sdram_startup_cycles => sdram_startup_cycles,
cycles_per_refresh => cycles_per_refresh
)
PORT MAP(
clk => clk_i,
reset => rst_i,
cmd_ready => cmd_ready,
cmd_enable =>cmd_enable ,
cmd_wr => cmd_wr,
cmd_address => cmd_address,
cmd_byte_enable =>cmd_byte_enable ,
cmd_data_in => cmd_data_in,
data_out => data_out,
data_out_ready =>data_out_ready ,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CS => SDRAM_CS,
SDRAM_RAS => SDRAM_RAS,
SDRAM_CAS => SDRAM_CAS,
SDRAM_WE => SDRAM_WE,
SDRAM_DQM => SDRAM_DQM,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_BA => SDRAM_BA,
SDRAM_DATA => SDRAM_DATA
);
ram_adr <= wbs_adr_i(cmd_address'high+2 downto 2);
cmd_byte_enable <= wbs_sel_i;
cmd_wr <= wbs_we_i;
cmd_enable <= wbs_cyc_i and wbs_stb_i and (not read_pending or burstfetch_enable);
cmd_data_in <= wbs_dat_i;
wbs_dat_o <= data_out;
wbs_ack_o <= (wbs_stb_i and wbs_we_i and cmd_ready) -- Immediatly ack write
or (wbs_stb_i and read_pending and data_out_ready and not orphan_read); -- Ack read when data ready and no orphan outstanding reads
is_read <= wbs_cyc_i and wbs_stb_i and not wbs_we_i;
-- adr multiplexer
process(ram_adr,adr_reg,is_read,burst,wbs_cti_i) is
begin
if is_read='1' and burst='1' and (wbs_cti_i="010" or wbs_cti_i="111") then
cmd_address <= adr_reg;
else
cmd_address <= ram_adr;
end if;
end process;
-- Burst Mode support
-- needs wbs_burst_length of 4 or gerater to be enabled
process(burst,burst_counter)
begin
if burst='1' and (burst_counter /= 0) then
burstfetch_enable <= '1';
else
burstfetch_enable <= '0';
end if;
end process;
burstread: if wbs_burst_length>= 4 generate
burst_disable <= false;
process(clk_i) is
begin
if rising_edge(clk_i) then
if rst_i = '1' then
burst <= '0';
elsif is_read='1' and wbs_cti_i="010" and cmd_ready='1' then -- burst cycle ??
if read_pending='0' then -- begin of new cycle
burst <= '1';
adr_reg <= std_logic_vector(unsigned(ram_adr)+1);
burst_counter <= to_unsigned(wbs_burst_length-1,burst_counter'length);
end if;
if burstfetch_enable='1' then
adr_reg <= std_logic_vector(unsigned(adr_reg)+1);
burst_counter <= burst_counter - 1;
end if;
elsif wbs_stb_i='0' or wbs_cti_i="111" then
burst <= '0';
end if;
end if;
end process;
end generate;
-- Pending read counter
process(clk_i) is
variable next_counter : unsigned(pending_read_counter'high downto 0);
begin
if rising_edge(clk_i) then
if rst_i = '1' then
next_counter := to_unsigned(0,pending_read_counter'length);
read_pending <= '0';
orphan_read <= '0';
else
next_counter := pending_read_counter;
if is_read='1' and cmd_ready='1' and cmd_enable='1' then
next_counter := next_counter + 1;
read_pending <= '1';
end if;
if read_pending = '1' and data_out_ready = '1' then
next_counter := next_counter - 1;
if next_counter = 0 or burst_disable then
read_pending <= '0';
orphan_read <= '0';
elsif wbs_stb_i='0' or wbs_cti_i="111" then -- WBS cycle ended while still pending reads
orphan_read <= '1'; -- set orphan read flag
end if;
end if;
end if;
pending_read_counter <= next_counter;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
4cbea6a7466d04ee894d3dd730ddd664
| 0.593496 | 3.432558 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fadd_32ns_32ns_32_5_full_dsp.vhd
| 7 | 3,340 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fadd_32ns_32ns_32_5_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fadd_32ns_32ns_32_5_full_dsp is
--------------------- Component ---------------------
component ANN_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fadd_3_full_dsp_32_u : component ANN_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
54d3e053589607f83023fd230f03c4d6
| 0.484431 | 3.475546 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt
|
kr_fuzman_Ztminus.vhd
| 1 | 769 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Ztminus is
port
( clock : in std_logic;
Ztminusone: in std_logic_vector (31 downto 0);
Ztminus : out std_logic_vector (31 downto 0)
);
end kr_fuzman_Ztminus;
architecture struct of kr_fuzman_Ztminus is
component kn_kalman_add is
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Q : std_logic_vector(31 downto 0) := "00111100001000111101011100001010";
begin
M1 : kn_kalman_add port map ( clock => clock, dataa => Ztminusone, datab => Q, result => Ztminus);
end struct;
|
mit
|
1254fecf9bf9664c0d53c20985225554
| 0.657997 | 3.358079 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
dram/clkgen.vhd
| 2 | 7,200 |
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk32Mhz_out: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_ulogic;
--signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clk3: std_ulogic;
signal clkin_i_2: std_logic;
-- signal clk_div: std_logic;
-- signal count: integer;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
--process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
process(dcmlocked, clkout_i, rstin)
begin
--if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
-- clkin_inst: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i
-- );
clkin_i <= clkin;
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
clk3_inst: BUFG port map ( I => clk3, O => clk32Mhz_out );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 30,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => clk3, -- TH 32Mhz clock
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
--DCM_inst_1mhz : DCM
-- generic map (
-- CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
-- CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
-- CLKIN_PERIOD => 31.25, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
-- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
-- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
-- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
-- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-- )
-- port map (
-- CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
-- CLK180 => open, -- 180 degree DCM CLK output
-- CLK270 => open, -- 270 degree DCM CLK output
-- CLK2X => open, -- 2X DCM CLK output
-- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-- CLK90 => open, -- 90 degree DCM CLK output
-- CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => open, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => open, -- 180 degree CLK synthesis out
-- LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
-- PSDONE => open, -- Dynamic phase adjust done output
-- STATUS => open, -- 8-bit DCM status bits output
-- CLKFB => clkfb_1mhz, -- DCM clock feedback
-- CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => '0', -- Dynamic phase adjust clock input
-- PSEN => '0', -- Dynamic phase adjust enable input
-- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
-- RST => '0' -- DCM asynchronous reset input
-- );
-- clkfx_inst_1mhz: BUFG
-- port map (
-- I => dcmclock_1mhz,
-- O => clk_1Mhz_out
-- );
--clkin_i_1mhz <= clkout_i;
end behave;
|
gpl-3.0
|
f954aea6266bc19264b2167b31172a04
| 0.602361 | 3.341067 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_dexp_64ns_64ns_64_18_full_dsp.vhd
| 1 | 2,769 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 8;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dexp_16_full_dsp_64_u : component ANN_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
ac0f2427fb949be6f7df558361eaefcc
| 0.474901 | 3.65786 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_ddiv_64ns_64ns_64_31.vhd
| 1 | 3,322 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
4ef09475438f6ae2251e74dbce079122
| 0.482842 | 3.485834 | false | false | false | false |
Rookfighter/aes-ss17
|
ex02/whole_design.vhd
| 1 | 3,523 |
-- whole_design.vhd
--
-- Created on: 21 May 2017
-- Author: Fabian Meyer
--
-- Integrates LCD display to show a custom text.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity whole_design is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
led: out std_logic; -- led, high active
en: out std_logic; -- enable, high active
rw: out std_logic;
rs: out std_logic;
bl: out std_logic; -- backlight, high active
data: inout std_logic_vector(3 downto 0)); -- data, dual direction
end whole_design;
architecture behavioral of whole_design is
-- import lcd component
component lcd
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic;
clk: in std_logic;
din: in std_logic_vector(7 downto 0);
posx: in std_logic_vector(3 downto 0);
posy: in std_logic;
flush: in std_logic;
rdy: out std_logic;
en: out std_logic;
rw: out std_logic;
rs: out std_logic;
bl: out std_logic;
data: inout std_logic_vector(3 downto 0));
end component;
-- counter defines which character is printed and at which position
signal cnt: std_logic_vector(4 downto 0) := (others => '0');
signal din: std_logic_vector(7 downto 0) := (others => '0');
signal posx: std_logic_vector(3 downto 0) := (others => '0');
signal posy: std_logic := '0';
signal flush: std_logic := '0';
signal rdy: std_logic := '0';
begin
mylcd: lcd
port map (rst => rst,
clk => clk,
din => din,
posx => posx,
posy => posy,
flush => flush,
rdy => rdy,
en => en,
rw => rw,
rs => rs,
bl => bl,
data => data);
led <= rst;
-- lower bits of cnt define x position of character to write
posx <= cnt(3 downto 0);
-- carry bit of cnt defines line
posy <= cnt(4);
-- map current cnt to a ASCII character
with conv_integer(cnt) select din <=
X"48" when 0, -- 'H'
X"65" when 1, -- 'e'
X"6c" when 2, -- 'l'
X"6c" when 3, -- 'l'
X"6f" when 4, -- 'o'
X"20" when 5, -- ' '
X"57" when 6, -- 'W'
X"6f" when 7, -- 'o'
X"72" when 8, -- 'r'
X"6c" when 9, -- 'l'
X"64" when 10, -- 'd'
X"21" when 11, -- '!'
X"46" when 16, -- 'F'
X"6f" when 17, -- 'o'
X"6f" when 18, -- 'o'
X"62" when 19, -- 'b'
X"61" when 20, -- 'a'
X"72" when 21, -- 'r'
X"20" when others;
process(rst, clk)
begin
if rst = RSTDEF then
cnt <= (others => '0');
flush <= '0';
elsif rising_edge(clk) then
-- disable flush every cycle
-- flush will always only stay enabled for one cycle
flush <= '0';
if rdy = '1' and flush = '0' then
-- increment counter whenever LCD is ready again
cnt <= cnt + 1;
-- flush input
flush <= '1';
end if;
end if;
end process;
end behavioral;
|
gpl-3.0
|
d74720a881e5dee0291bece8d39d0b3e
| 0.468067 | 3.565789 | false | false | false | false |
Cpt-Quantum/VHDL
|
FPGA_Intro/Clocks_nested_counters.vhd
| 1 | 4,020 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.08.2016 14:48:09
-- Design Name:
-- Module Name: Switches_LEDS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( switches_1 : in STD_LOGIC_VECTOR(7 downto 0);
switches_2 : in STD_LOGIC_VECTOR(3 downto 0);
LEDS_1 : out STD_LOGIC_VECTOR(7 downto 0);
LEDS_2 : out STD_LOGIC_VECTOR(3 downto 0);
clk : in STD_LOGIC
);
end counter;
architecture Behavioral of counter is
signal counter_1 : STD_LOGIC_VECTOR(6 downto 0);
signal counter_2 : STD_LOGIC_VECTOR(9 downto 0);
signal counter_3 : STD_LOGIC_VECTOR(9 downto 0);
signal LED_state : STD_LOGIC_VECTOR(3 downto 0);
-- Reset signals
signal reset : STD_LOGIC;
begin
--Reset block
reset_proc: process(clk)
begin
if rising_edge(clk) then
if switches_2(0) = '1' then
reset <= '1';
else
reset <= '0';
end if;
end if;
end process;
--End of reset block
--Counter block
counter_1_proc: process(clk)
begin
if rising_edge(clk) and reset = '0' then
counter_1 <= counter_1+1;
if counter_1 = STD_LOGIC_VECTOR(to_unsigned(100,7)) or reset = '1' then
counter_1 <= (others=>'0');
end if;
end if;
end process;
counter_2_proc: process(clk)
begin
if rising_edge(clk) then
if counter_1 = STD_LOGIC_VECTOR(to_unsigned(100,7)) then
counter_2 <= counter_2 + 1;
end if;
if counter_2 = STD_LOGIC_VECTOR(to_unsigned(1000,10)) or reset = '1' then
counter_2 <= (others=>'0');
end if;
end if;
end process;
counter_3_proc: process(clk)
begin
if rising_edge(clk)
if counter_2 = STD_LOGIC_VECTOR(to_unsigned(1000,10)) then
counter_3 <= counter_3 + 1;
end if;
if counter_3 = STD_LOGIC_VECTOR(to_unsigned(1000,10)) or reset = '1'then
counter_3 <= (others =>'0')
end if;
end if;
end process;
--End of counter block
--Display 1 second on each LED
LED_proc: process(clk)
begin
if rising_edge(clk) then
if reset= '1' then
LED_state <= "1000";
end if;
if counter_3 = STD_LOGIC_VECTOR(to_unsigned(1000,10)) then
--Assign LEDds to internal LED state
LEDS_1(7 downto 4) <= LED_state(3 downto 0);
-- Shift register to move along LED chain
LED_state(3 downto 0) <= LED_state(0) & LED_state(3 downto 1);
end if;
--Set lower bits for counter as this is all the counter will reach
LEDS_1(3 downto 0) <= counter_3(5 downto 2);
end if;
end process;
--Switch off LEDS on board, comment if you want to use these LEDs elesewhere
LEDS_2 <= (others=>'0');
end Behavioral;
|
mit
|
00610ab91bf96784803ecd6e350e0124
| 0.5 | 4.174455 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fdiv_14_no_dsp_32.vhd
| 6 | 12,691 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fdiv_14_no_dsp_32;
ARCHITECTURE ANN_ap_fdiv_14_no_dsp_32_arch OF ANN_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fdiv_14_no_dsp_32_arch;
|
gpl-3.0
|
2a6d4aa16b7f4688c1b72f0c55051aae
| 0.649515 | 3.000946 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
obsolete/gpio.vhd
| 1 | 1,778 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:05:00 09/05/2016
-- Design Name:
-- Module Name: gpio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gpio is
generic(
wbs_adr_high : natural := 27
);
port(
-- output
leds: out std_logic_vector(4 downto 0);
-- bus interface
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(wbs_adr_high downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0)
);
end gpio;
architecture Behavioral of gpio is
begin
wbs_dat_o <= (others=>'0');
process(clk_i) begin
if rising_edge(clk_i) then
if rst_i='1' then
leds<="00000";
end if;
if wbs_cyc_i='1' and wbs_stb_i='1' then
if wbs_we_i='1' and wbs_sel_i(0)='1' then
leds <= wbs_dat_i(4 downto 0);
end if;
wbs_ack_o<='1';
else
wbs_ack_o<='0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f451759d4f0bcc37d2b294c14e53deef
| 0.566929 | 3.238616 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_ddiv_29_no_dsp_64.vhd
| 6 | 12,691 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_ddiv_29_no_dsp_64;
ARCHITECTURE ANN_ap_ddiv_29_no_dsp_64_arch OF ANN_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_ddiv_29_no_dsp_64_arch;
|
gpl-3.0
|
23249df71d00e0f092f88d8495ce2301
| 0.649515 | 3.000946 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/hdl/design_SWandHW_standalone_wrapper.vhd
| 1 | 6,375 |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 16:06:03 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SWandHW_standalone_wrapper.bd
--Design : design_SWandHW_standalone_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_SWandHW_standalone_wrapper;
architecture STRUCTURE of design_SWandHW_standalone_wrapper is
component design_SWandHW_standalone is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SWandHW_standalone;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
design_SWandHW_standalone_i: component design_SWandHW_standalone
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),
leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),
leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),
leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),
leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),
leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),
leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),
leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),
leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),
leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),
leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),
leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_0: component IOBUF
port map (
I => leds_4bits_tri_o_0(0),
IO => leds_4bits_tri_io(0),
O => leds_4bits_tri_i_0(0),
T => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_1: component IOBUF
port map (
I => leds_4bits_tri_o_1(1),
IO => leds_4bits_tri_io(1),
O => leds_4bits_tri_i_1(1),
T => leds_4bits_tri_t_1(1)
);
leds_4bits_tri_iobuf_2: component IOBUF
port map (
I => leds_4bits_tri_o_2(2),
IO => leds_4bits_tri_io(2),
O => leds_4bits_tri_i_2(2),
T => leds_4bits_tri_t_2(2)
);
leds_4bits_tri_iobuf_3: component IOBUF
port map (
I => leds_4bits_tri_o_3(3),
IO => leds_4bits_tri_io(3),
O => leds_4bits_tri_i_3(3),
T => leds_4bits_tri_t_3(3)
);
end STRUCTURE;
|
gpl-3.0
|
f72ad058ec9cdfcf0503f91e7f696453
| 0.596392 | 2.788714 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_dma_3_0/synth/design_SWandHW_standalone_axi_dma_3_0.vhd
| 1 | 22,263 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_SWandHW_standalone_axi_dma_3_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_axi_dma_3_0;
ARCHITECTURE design_SWandHW_standalone_axi_dma_3_0_arch OF design_SWandHW_standalone_axi_dma_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_dma_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_dma_3_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_dma_3_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_3_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_dma_3_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_3_0,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=256,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 256,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => '0',
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_SWandHW_standalone_axi_dma_3_0_arch;
|
gpl-3.0
|
e9a91250e40bd0722b4f182b7451d0e5
| 0.673225 | 2.794051 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ip/design_TEST_axi_dma_0_0/synth/design_TEST_axi_dma_0_0.vhd
| 1 | 21,570 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_TEST_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_TEST_axi_dma_0_0;
ARCHITECTURE design_TEST_axi_dma_0_0_arch OF design_TEST_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_TEST_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_TEST_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_TEST_axi_dma_0_0_arch : ARCHITECTURE IS "design_TEST_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_TEST_axi_dma_0_0_arch: ARCHITECTURE IS "design_TEST_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=256,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=0,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 256,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_TEST_axi_dma_0_0_arch;
|
gpl-3.0
|
f1489eb196d0637bfebcd9f88caa4e47
| 0.670097 | 2.788623 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fdiv_14_no_dsp_32/synth/ANN_ap_fdiv_14_no_dsp_32.vhd
| 1 | 12,685 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fdiv_14_no_dsp_32;
ARCHITECTURE ANN_ap_fdiv_14_no_dsp_32_arch OF ANN_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fdiv_14_no_dsp_32_arch;
|
gpl-3.0
|
a47fdea929fda12711f04fc97fd731be
| 0.64935 | 3.000946 | false | false | false | false |
makestuff/spi-talk
|
templates/fx2min/vhdl/top_level.vhdl
| 1 | 4,552 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
NUM_DEVS : integer := 2
);
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2FifoSel_out : out std_logic; -- select FIFO: "0" for EP2OUT, "1" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Peripheral interface ----------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(NUM_DEVS-1 downto 0)
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
begin
-- CommFPGA module
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => open,
-- FX2LP interface
fx2FifoSel_out => fx2FifoSel_out,
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => fx2Clk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in,
spiCS_out => spiCS_out
);
end architecture;
|
gpl-3.0
|
6887e5c14c07a320533f7f7651116188
| 0.588313 | 3.480122 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SW_standalone/ip/design_SW_standalone_axi_gpio_0_0/synth/design_SW_standalone_axi_gpio_0_0.vhd
| 1 | 10,147 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SW_standalone_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SW_standalone_axi_gpio_0_0;
ARCHITECTURE design_SW_standalone_axi_gpio_0_0_arch OF design_SW_standalone_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SW_standalone_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SW_standalone_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SW_standalone_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SW_standalone_axi_gpio_0_0_arch;
|
gpl-3.0
|
d3764f112c4da08df47afb52dabb429e
| 0.689366 | 3.167968 | false | false | false | false |
Rookfighter/aes-ss17
|
ex03/delay.vhd
| 1 | 927 |
-- delay.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
--
-- Component that delays an input signal by
-- a given amount of cycles.
library ieee;
use ieee.std_logic_1164.all;
entity delay is
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic; -- data in
dout: out std_logic); -- data out
end entity;
architecture behavioral of delay is
-- vector through which signal is chained
signal dvec : std_logic_vector (DELAYLEN-1 downto 0) := (others => '0');
begin
dout <= dvec(DELAYLEN-1);
process (rst, clk)
begin
if rst = RSTDEF then
dvec <= (others => '0');
elsif rising_edge(clk) then
dvec <= dvec(DELAYLEN-2 downto 0) & din;
end if;
end process;
end architecture;
|
gpl-3.0
|
f68d67bb51ce4dc0e7b97ecf408158ef
| 0.592233 | 3.524715 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
tb_dramtest.vhd
| 1 | 6,002 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:29:26 12/18/2016
-- Design Name:
-- Module Name: tb_dramtest.vhd
-- Project Name: bonfire
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: papilio_pro_dram_toplevel
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dramtest IS
generic (
RamFileName : string := "compiled_code/monitor.hex";
--RamFileName : string :="../../../bonfire-soc/compiled_code/monitor.hex";
mode : string := "H"; -- only used when UseBRAMPrimitives is false
Swapbytes : boolean := false; -- SWAP Bytes in RAM word in low byte first order to use data2mem
FakeDRAM : boolean := false; -- Use Block RAM instead of DRAM
BurstSize : natural := 8;
CacheSizeWords : natural := 4096; -- 16KB Instruction Cache
EnableDCache : boolean := true;
DCacheSizeWords : natural := 2048;
MUL_ARCH: string := "spartandsp";
REG_RAM_STYLE : string := "block";
DRAM_INIT_FILE : string :=""
);
END tb_dramtest;
ARCHITECTURE behavior OF tb_dramtest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT papilio_pro_dram_toplevel
generic (
RamFileName : string;
mode : string;
Swapbytes : boolean := true;
FakeDRAM : boolean := false;
BurstSize : natural := 8;
CacheSizeWords : natural := 2048; -- 8KB Instruction Cache
EnableDCache : boolean := true;
DCacheSizeWords : natural := 2048;
MUL_ARCH: string := "spartandsp";
REG_RAM_STYLE : string := "block"
);
PORT(
sysclk_32m : IN std_logic;
I_RESET : IN std_logic;
uart0_rxd : IN std_logic;
flash_spi_miso : IN std_logic;
SDRAM_DATA : INOUT std_logic_vector(15 downto 0);
leds : OUT std_logic_vector(3 downto 0);
uart0_txd : OUT std_logic;
flash_spi_cs : OUT std_logic;
flash_spi_clk : OUT std_logic;
flash_spi_mosi : OUT std_logic;
led1 : OUT std_logic;
SDRAM_CLK : OUT std_logic;
SDRAM_CKE : OUT std_logic;
SDRAM_CS : OUT std_logic;
SDRAM_RAS : OUT std_logic;
SDRAM_CAS : OUT std_logic;
SDRAM_WE : OUT std_logic;
SDRAM_DQM : OUT std_logic_vector(1 downto 0);
SDRAM_ADDR : OUT std_logic_vector(12 downto 0);
SDRAM_BA : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
COMPONENT sdram_model
GENERIC (
mode : string := "H";
RamFileName : string
);
PORT(
CLK : IN std_logic;
CKE : IN std_logic;
CS_N : IN std_logic;
RAS_N : IN std_logic;
CAS_N : IN std_logic;
WE_N : IN std_logic;
BA : IN std_logic_vector(1 downto 0);
DQM : IN std_logic_vector(1 downto 0);
ADDR : IN std_logic_vector(12 downto 0);
DQ : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal sysclk_32m : std_logic := '0';
signal I_RESET : std_logic := '0';
signal uart0_rxd : std_logic := '0';
--BiDirs
signal SDRAM_DATA : std_logic_vector(15 downto 0);
--Outputs
signal leds : std_logic_vector(3 downto 0);
signal uart0_txd : std_logic;
signal led1 : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CS : std_logic;
signal SDRAM_RAS : std_logic;
signal SDRAM_CAS : std_logic;
signal SDRAM_WE : std_logic;
signal SDRAM_DQM : std_logic_vector(1 downto 0);
signal SDRAM_ADDR : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal flash_spi_cs,flash_spi_clk,flash_spi_loopback : std_logic;
-- Clock period definitions
constant clock_period : time := 31.25ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: papilio_pro_dram_toplevel
generic map (
RamFileName => RamFileName,
mode=>mode,
FakeDRAM=>FakeDRAM,
Swapbytes=>Swapbytes,
CacheSizeWords => CacheSizeWords,
BurstSize =>BurstSize,
EnableDCache => EnableDCache,
DCacheSizeWords=>DCacheSizeWords,
MUL_ARCH=>MUL_ARCH,
REG_RAM_STYLE=>REG_RAM_STYLE
)
PORT MAP (
sysclk_32m => sysclk_32m,
I_RESET => I_RESET,
leds => leds,
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,
led1 => led1,
flash_spi_cs =>flash_spi_cs ,
flash_spi_clk => flash_spi_clk,
flash_spi_mosi => flash_spi_loopback,
flash_spi_miso => flash_spi_loopback,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CS => SDRAM_CS,
SDRAM_RAS => SDRAM_RAS,
SDRAM_CAS => SDRAM_CAS,
SDRAM_WE => SDRAM_WE,
SDRAM_DQM => SDRAM_DQM,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_BA => SDRAM_BA,
SDRAM_DATA => SDRAM_DATA
);
Inst_sdram_model: sdram_model
GENERIC MAP (
mode=>"H",
RamFileName => DRAM_INIT_FILE
)
PORT MAP(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
CS_N => SDRAM_CS,
RAS_N => SDRAM_RAS,
CAS_N => SDRAM_CAS,
WE_N => SDRAM_WE,
BA => SDRAM_BA,
DQM => SDRAM_DQM,
ADDR => SDRAM_ADDR,
DQ => SDRAM_DATA
);
-- Clock process definitions
clock_process :process
begin
sysclk_32m <= '0';
wait for clock_period/2;
sysclk_32m <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
fddeb97a63d0404be44f0298765f5741
| 0.566644 | 3.76537 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt
|
kn_kalman_sub.vhd
| 2 | 291,223 |
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: kn_kalman_sub.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="SUB" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_altfp_add_sub 2012:01:25:21:13:53:SJ cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_sub_altbarrel_shift_h0e;
ARCHITECTURE RTL OF kn_kalman_sub_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_sub_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 29
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altbarrel_shift_n3g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_sub_altbarrel_shift_n3g;
ARCHITECTURE RTL OF kn_kalman_sub_altbarrel_shift_n3g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range780w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range802w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range823w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range847w860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w872w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w791w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w794w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w815w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w834w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w856w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w859w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w878w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range865w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range801w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range821w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range830w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) AND wire_rbarrel_shift_w794w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) AND wire_rbarrel_shift_w791w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) AND wire_rbarrel_shift_w815w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) AND wire_rbarrel_shift_w812w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) AND wire_rbarrel_shift_w834w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) AND wire_rbarrel_shift_w859w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) AND wire_rbarrel_shift_w856w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) AND wire_rbarrel_shift_w878w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) AND wire_rbarrel_shift_w_sbit_w_range778w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) AND wire_rbarrel_shift_w_sbit_w_range801w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) AND wire_rbarrel_shift_w_sbit_w_range821w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) AND wire_rbarrel_shift_w_sbit_w_range843w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) AND wire_rbarrel_shift_w_sbit_w_range865w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0) <= NOT wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0) <= NOT wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0) <= NOT wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0) <= NOT wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) <= NOT wire_rbarrel_shift_w_sel_w_range783w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) <= NOT wire_rbarrel_shift_w_sel_w_range804w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) <= NOT wire_rbarrel_shift_w_sel_w_range826w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) <= NOT wire_rbarrel_shift_w_sel_w_range849w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) <= NOT wire_rbarrel_shift_w_sel_w_range868w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w799w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w820w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w842w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w864w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 3) & dir_pipe(0) & dir_w(1 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 78) & sbit_piper1d & smux_w(51 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r1d & sel_pipec3r1d & distance(2 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w883w & wire_rbarrel_shift_w864w & wire_rbarrel_shift_w842w & wire_rbarrel_shift_w820w & wire_rbarrel_shift_w799w);
wire_rbarrel_shift_w791w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w794w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w812w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w815w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w834w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w837w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w856w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w859w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w878w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range780w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range802w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range823w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range847w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range843w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range865w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range778w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range801w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range821w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range783w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range804w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range826w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range849w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range868w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range830w <= smux_w(77 DOWNTO 52);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(2));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range830w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_sub_altbarrel_shift_n3g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_3e8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --kn_kalman_sub_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_6e8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero919w920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero921w922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero919w & wire_altpriority_encoder14_w_lg_w_lg_zero921w922w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : kn_kalman_sub_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0) <= wire_altpriority_encoder14_w_lg_zero919w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero921w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero919w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero921w922w(0) <= wire_altpriority_encoder14_w_lg_zero921w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0);
altpriority_encoder14 : kn_kalman_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_be8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero909w910w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero909w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero911w912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero909w & wire_altpriority_encoder12_w_lg_w_lg_zero911w912w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : kn_kalman_sub_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i) <= wire_altpriority_encoder12_w_lg_zero909w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero911w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero909w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero911w912w(i) <= wire_altpriority_encoder12_w_lg_zero911w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i);
END GENERATE loop52;
altpriority_encoder12 : kn_kalman_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_3v7;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --kn_kalman_sub_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_6v7;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero944w945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero946w947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero944w & wire_altpriority_encoder18_w_lg_w_lg_zero946w947w);
altpriority_encoder17 : kn_kalman_sub_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0) <= wire_altpriority_encoder18_w_lg_zero944w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero946w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero944w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero946w947w(0) <= wire_altpriority_encoder18_w_lg_zero946w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0);
altpriority_encoder18 : kn_kalman_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_bv7;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero935w936w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero937w938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero935w & wire_altpriority_encoder16_w_lg_w_lg_zero937w938w);
altpriority_encoder15 : kn_kalman_sub_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i) <= wire_altpriority_encoder16_w_lg_zero935w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero937w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero935w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero937w938w(i) <= wire_altpriority_encoder16_w_lg_zero937w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i);
END GENERATE loop55;
altpriority_encoder16 : kn_kalman_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_uv8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero900w901w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero902w903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero900w & wire_altpriority_encoder10_w_lg_w_lg_zero902w903w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i) <= wire_altpriority_encoder10_w_lg_zero900w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero902w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero900w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero902w903w(i) <= wire_altpriority_encoder10_w_lg_zero902w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i);
END GENERATE loop58;
altpriority_encoder10 : kn_kalman_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : kn_kalman_sub_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --kn_kalman_sub_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_ue9;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero956w957w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero958w959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero956w & wire_altpriority_encoder20_w_lg_w_lg_zero958w959w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : kn_kalman_sub_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i) <= wire_altpriority_encoder20_w_lg_zero956w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero958w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero956w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero958w959w(i) <= wire_altpriority_encoder20_w_lg_zero958w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i);
END GENERATE loop61;
altpriority_encoder20 : kn_kalman_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_ou8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero890w891w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_sub_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder8_w_lg_zero890w & wire_altpriority_encoder8_w_lg_w_lg_zero892w893w);
altpriority_encoder7 : kn_kalman_sub_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i) <= wire_altpriority_encoder8_w_lg_zero890w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero892w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero890w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i);
END GENERATE loop64;
altpriority_encoder8 : kn_kalman_sub_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_sub_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_nh8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1006w1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1006w1008w(0) <= NOT wire_altpriority_encoder27_w_data_range1006w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1006w1008w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1006w(0) <= data(0);
END RTL; --kn_kalman_sub_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_qh8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero1000w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0) <= wire_altpriority_encoder27_w_lg_zero1000w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0);
altpriority_encoder27 : kn_kalman_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : kn_kalman_sub_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_vh8;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero990w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero990w991w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero990w991w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero990w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero988w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i) <= wire_altpriority_encoder25_w_lg_zero990w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i);
END GENERATE loop67;
altpriority_encoder25 : kn_kalman_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : kn_kalman_sub_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_ii9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_sub_altpriority_encoder_ii9;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_ii9 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero980w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero980w981w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT kn_kalman_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero980w981w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero980w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero978w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero980w981w(i) <= wire_altpriority_encoder23_w_lg_zero980w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i);
END GENERATE loop70;
altpriority_encoder23 : kn_kalman_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : kn_kalman_sub_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --kn_kalman_sub_altpriority_encoder_ii9
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_n28;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1040w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1040w1042w(0) <= NOT wire_altpriority_encoder34_w_data_range1040w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1040w1042w);
wire_altpriority_encoder34_w_data_range1040w(0) <= data(0);
END RTL; --kn_kalman_sub_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_q28;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w);
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1035w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w(0) <= wire_altpriority_encoder33_w_lg_zero1035w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0);
altpriority_encoder33 : kn_kalman_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : kn_kalman_sub_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --kn_kalman_sub_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_v28;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1026w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT kn_kalman_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1026w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1024w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w(i) <= wire_altpriority_encoder31_w_lg_zero1026w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i);
END GENERATE loop73;
altpriority_encoder31 : kn_kalman_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : kn_kalman_sub_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --kn_kalman_sub_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_i39 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_i39;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_i39 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1017w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1017w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1015w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i) <= wire_altpriority_encoder29_w_lg_zero1017w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i);
END GENERATE loop76;
altpriority_encoder29 : kn_kalman_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : kn_kalman_sub_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --kn_kalman_sub_altpriority_encoder_i39
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altpriority_encoder_cna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_sub_altpriority_encoder_cna;
ARCHITECTURE RTL OF kn_kalman_sub_altpriority_encoder_cna IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero966w967w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero968w969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_sub_altpriority_encoder_ii9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_i39
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop77 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w(i) <= NOT tmp_q_wire(i);
END GENERATE loop77;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero968w969w);
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i) <= wire_altpriority_encoder21_w_lg_zero966w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop78;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero968w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop79;
wire_altpriority_encoder21_w_lg_zero966w(0) <= NOT wire_altpriority_encoder21_zero;
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero968w969w(i) <= wire_altpriority_encoder21_w_lg_zero968w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i);
END GENERATE loop80;
altpriority_encoder21 : kn_kalman_sub_altpriority_encoder_ii9
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : kn_kalman_sub_altpriority_encoder_i39
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_sub_altpriority_encoder_cna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 716
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub_altfp_add_sub_23j IS
PORT
(
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_sub_altfp_add_sub_23j;
ARCHITECTURE RTL OF kn_kalman_sub_altfp_add_sub_23j IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL add_sub_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe25 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe27 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe27 : STD_LOGIC_VECTOR(27 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_rounding_add_sub_result_reg : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_datab_sign_dffe15_wo336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_sub_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_sub_altbarrel_shift_n3g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_sub_altpriority_encoder_cna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop81 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop90;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop94;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo338w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop97 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop97;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop98 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop112;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= input_datab_infinite_dffe15_wo AND wire_w_lg_aligned_datab_sign_dffe15_wo336w(0);
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop113 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop113;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop114 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop117;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_aligned_datab_sign_dffe15_wo336w(0) <= NOT aligned_datab_sign_dffe15_wo;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo338w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop118 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop121;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25;
add_sub_w2 <= (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo);
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25;
clk_en <= '1';
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) OR wire_w_lg_input_datab_infinite_dffe15_wo337w(0));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= man_res_rounding_add_sub_result_reg;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : kn_kalman_sub_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : kn_kalman_sub_altbarrel_shift_n3g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : kn_kalman_sub_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : kn_kalman_sub_altpriority_encoder_cna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN add_sub_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN add_sub_dffe25 <= add_sub_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe25 <= both_inputs_are_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe25 <= dataa_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe25 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe25 <= exp_res_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe27 <= exp_res_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe25 <= infinite_output_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe25 <= input_is_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe25 <= input_is_nan_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_rounding_add_sub_result_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_rounding_add_sub_result_reg <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe25 <= sticky_bit_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop123;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop124;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop125;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop126;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop127 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop127;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop128;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop129;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop130 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop130;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --kn_kalman_sub_altfp_add_sub_23j
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_sub;
ARCHITECTURE RTL OF kn_kalman_sub IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_sub_altfp_add_sub_23j
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_sub_altfp_add_sub_23j_component : kn_kalman_sub_altfp_add_sub_23j
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_sub.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_sub.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_sub.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_sub.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_sub_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_sub_syn.v TRUE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
5e3f35de609f8eb6a6803f220e409960
| 0.683191 | 2.509288 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_dadd_64ns_64ns_64_5_full_dsp.vhd
| 6 | 3,340 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 7;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dadd_3_full_dsp_64_u : component ANN_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
8171f3c42f9e40311e2bcc7e3146432b
| 0.484431 | 3.475546 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/synth/ANN_ap_fptrunc_0_no_dsp_64.vhd
| 1 | 12,159 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE ANN_ap_fptrunc_0_no_dsp_64_arch OF ANN_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fptrunc_0_no_dsp_64_arch;
|
gpl-3.0
|
cc113dad2a0affb128feb0e9745ec22d
| 0.646188 | 3.003706 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
| 24 | 73,491 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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zkhz98SR0w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
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3S28XWLsXlShK1Sv81skQrD+c6RvpxNlDG5EvjMJleCxOyRjgV8U8OlZZEQ0+cztT9vB60n6NUDK
y77ivtZh/Tr64ujQQVSwnFXFFRFO0JaqGyOAoT9oWDUUoxN35uVkGdSv+JP+UoiTwQ88NhH7tmnK
QPku
`protect end_protected
|
gpl-3.0
|
0ec9dcd066a7f1dbbffc57f9d1d58126
| 0.950239 | 1.836632 | false | false | false | false |
mjl152/usmt_uarch
|
smt_control_unit.vhd
| 1 | 14,227 |
-- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT control unit
-- Michael Lancaster <[email protected]>
-- 4 October 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity smt_control_unit is
Port ( CLOCK : in STD_LOGIC;
INSTRUCTION_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000110";
INSTRUCTION_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000111";
INSTRUCTION_POINTER_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
INSTRUCTION_POINTER_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG1_0 : out STD_LOGIC_VECTOR (7 downto 0) := "01000100";
ARG1_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG2_0 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG2_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
ARG3_0 : out STD_LOGIC_VECTOR (7 downto 0 ):= "00000000";
ARG3_1 : out STD_LOGIC_VECTOR (7 downto 0) := "00000000");
type smt_thread_register is array (1 downto 0) of std_logic_vector(7 downto 0);
function is_instruction(INSTRUCTION_REGISTER : in std_logic_vector(7 downto 0);
INSTRUCTION : in integer range 0 to 7)
return STD_LOGIC is
begin
if (INSTRUCTION_REGISTER = std_logic_vector(to_unsigned(INSTRUCTION, 8))) then
return '1';
end if;
return '0';
end is_instruction;
function initialize_register_1 return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(6, 8));
temp(1) := std_logic_vector(to_signed(7, 8));
return temp;
end initialize_register_1;
function initialize_register_2 return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(36, 8));
temp(1) := std_logic_vector(to_signed(0, 8));
return temp;
end initialize_register_2;
function initialize_zeros return smt_thread_register is
variable temp : smt_thread_register;
begin
temp(0) := std_logic_vector(to_signed(0, 8));
temp(1) := std_logic_vector(to_signed(0, 8));
return temp;
end initialize_zeros;
function increment_instruction_pointer(instruction_pointer : in std_logic_vector (7 downto 0))
return std_logic_vector is
begin
return std_logic_vector(signed(instruction_pointer) + 4);
end increment_instruction_pointer;
end smt_control_unit;
architecture Behavioral of smt_control_unit is
component smt_adder_unit
Port ( ADDER_A, ADDER_B : in STD_LOGIC_VECTOR (7 downto 0);
ADDER_S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component smt_multiplier_unit
Port (MULTIPLIER_A, MULTIPLIER_B : in STD_LOGIC_VECTOR (7 downto 0);
MULTIPLIER_C : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component smt_ram is
port
(
DATA0 : in std_logic_vector(7 downto 0);
DATA1 : in std_logic_vector(7 downto 0);
ADDR0 : in std_logic_vector(7 downto 0);
ADDR1 : in std_logic_vector(7 downto 0);
SET0 : in std_logic := '1';
SET1 : in std_logic := '1';
RAM_CLOCK : in std_logic;
OUT0 : out std_logic_vector(7 downto 0);
OUT1 : out std_logic_vector(7 downto 0);
OUT2 : out std_logic_vector(7 downto 0);
OUT3 : out std_logic_vector(7 downto 0);
OUT4 : out std_logic_vector(7 downto 0) := "00000111";
OUT5 : out std_logic_vector(7 downto 0);
OUT6 : out std_logic_vector(7 downto 0);
OUT7 : out std_logic_vector(7 downto 0);
OUTADDR0 : in std_logic_vector(7 downto 0);
OUTADDR1 : in std_logic_vector(7 downto 0)
);
end component;
component smt_instruction_handler
Port (HANDLER_INSTRUCTION : in std_logic_vector(7 downto 0);
HANDLER_INSTRUCTION_POINTER : in std_logic_vector(7 downto 0);
HANDLER_ADDR1 : in std_logic_vector(7 downto 0);
HANDLER_ADDR2 : in std_logic_vector(7 downto 0);
HANDLER_ADDR3 : in std_logic_vector(7 downto 0);
HANDLER_CLOCK : in std_logic;
HANDLER_OUTPUT : out std_logic_vector(7 downto 0);
HANDLER_INDEX : out std_logic_vector(7 downto 0);
HANDLER_SET : out std_logic;
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE : out std_logic_vector(7 downto 0));
end component;
shared variable smt_thread_instruction_pointer : smt_thread_register := initialize_zeros;
shared variable smt_thread_instruction : smt_thread_register := initialize_register_1;
shared variable smt_thread_arg1 : smt_thread_register := initialize_register_2;
shared variable smt_thread_arg2 : smt_thread_register := initialize_zeros;
shared variable smt_thread_arg3 : smt_thread_register := initialize_zeros;
shared variable starting : std_logic := '1';
signal ADDER_A, ADDER_B, ADDER_S, MULTIPLIER_A, MULTIPLIER_B, MULTIPLIER_C,
HANDLER_INSTRUCTION, HANDLER_INSTRUCTION_POINTER, HANDLER_ADDR1, HANDLER_ADDR2,
HANDLER_ADDR3, HANDLER_OUTPUT, HANDLER_INDEX, DATA0, DATA1, ADDR0, ADDR1, OUT0,
OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUTADDR0, OUTADDR1 : std_logic_vector(7 downto 0);
signal SET0, SET1, RAM_CLOCK, HANDLER_SET, MULTIPLIER_CLOCK, ADDER_C, HANDLER_CLOCK : std_logic;
signal HANDLER_INSTRUCTION_POINTER_INTERMEDIATE : std_logic_vector(7 downto 0);
begin
adder1 : smt_adder_unit Port Map (ADDER_A => ADDER_A, ADDER_B => ADDER_B, ADDER_S => ADDER_S);
multiplier1 : smt_multiplier_unit Port Map (MULTIPLIER_A => MULTIPLIER_A,
MULTIPLIER_B => MULTIPLIER_B,
MULTIPLIER_C => MULTIPLIER_C);
handler1 : smt_instruction_handler Port Map (HANDLER_INSTRUCTION => HANDLER_INSTRUCTION,
HANDLER_INSTRUCTION_POINTER => HANDLER_INSTRUCTION_POINTER,
HANDLER_ADDR1 => HANDLER_ADDR1,
HANDLER_ADDR2 => HANDLER_ADDR2,
HANDLER_ADDR3 => HANDLER_ADDR3,
HANDLER_CLOCK => HANDLER_CLOCK,
HANDLER_OUTPUT => HANDLER_OUTPUT,
HANDLER_INDEX => HANDLER_INDEX,
HANDLER_SET => HANDLER_SET,
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE =>
HANDLER_INSTRUCTION_POINTER_INTERMEDIATE);
ram1 : smt_ram Port Map (DATA0 => DATA0, DATA1=>DATA1, ADDR0 => ADDR0,
ADDR1 => ADDR1, SET0 => SET0, SET1 => SET1,
RAM_CLOCK => RAM_CLOCK, OUT0 => OUT0,
OUT1 => OUT1, OUT2 => OUT2, OUT3 => OUT3,
OUT4 => OUT4, OUT5 => OUT5, OUT6 => OUT6,
OUT7 => OUT7, OUTADDR0 => OUTADDR0,
OUTADDR1 => OUTADDR1);
process (CLOCK) is
begin
RAM_CLOCK <= CLOCK;
HANDLER_CLOCK <= CLOCK;
if rising_edge(CLOCK) then
if starting = '0' then
smt_thread_instruction(0) := OUT0;
smt_thread_instruction(1) := OUT4;
smt_thread_arg1(0) := OUT1;
smt_thread_arg2(0) := OUT2;
smt_thread_arg3(0) := OUT3;
smt_thread_arg1(1) := OUT5;
smt_thread_arg2(1) := OUT6;
smt_thread_arg3(1) := OUT7;
else
starting := '0';
end if;
INSTRUCTION_0 <= smt_thread_instruction(0);
INSTRUCTION_1 <= smt_thread_instruction(1);
INSTRUCTION_POINTER_0 <= smt_thread_instruction_pointer(0);
INSTRUCTION_POINTER_1 <= smt_thread_instruction_pointer(1);
ARG1_0 <= smt_thread_arg1(0);
ARG1_1 <= smt_thread_arg1(1);
ARG2_0 <= smt_thread_arg2(0);
ARG2_1 <= smt_thread_arg2(1);
ARG3_0 <= smt_thread_arg3(0);
ARG3_1 <= smt_thread_arg3(1);
case smt_thread_instruction(0) is
when "00000000" =>
ADDER_A <= smt_thread_arg1(0);
ADDER_B <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg3(0);
DATA0 <= ADDER_S;
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
case smt_thread_instruction(1) is
when "00000010" =>
-- thread 0 ifeq
if smt_thread_arg1(1) = smt_thread_arg2(1) then
smt_thread_instruction_pointer(1) := smt_thread_arg3(1);
else
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
when "00000011" =>
-- thread 0 ifgt
if smt_thread_arg1(1) > smt_thread_arg2(1) then
smt_thread_instruction_pointer(1) := smt_thread_arg3(1);
else
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
when "00000100" =>
-- thread 0 set
DATA1 <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg1(1);
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
when "00000101" =>
smt_thread_instruction_pointer(1) := smt_thread_arg1(1);
when others =>
end case;
when "00000001" =>
MULTIPLIER_A <= smt_thread_arg1(0);
MULTIPLIER_B <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg3(0);
DATA0 <= MULTIPLIER_C;
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when others =>
case smt_thread_instruction(0) is
when "00000010" =>
-- thread 0 ifeq
if smt_thread_arg1(0) = smt_thread_arg2(0) then
smt_thread_instruction_pointer(0) := smt_thread_arg3(0);
else
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
end if;
when "00000011" =>
-- thread 0 ifgt
if smt_thread_arg1(0) > smt_thread_arg2(0) then
smt_thread_instruction_pointer(0) := smt_thread_arg3(0);
else
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
end if;
when "00000100" =>
-- thread 0 set
DATA0 <= smt_thread_arg2(0);
ADDR0 <= smt_thread_arg1(0);
SET0 <= '1';
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when "00000101" =>
smt_thread_instruction_pointer(0) := smt_thread_arg1(0);
when "00000110" =>
smt_thread_instruction_pointer(1) := smt_thread_arg1(0);
smt_thread_instruction_pointer(0) := increment_instruction_pointer(smt_thread_instruction_pointer(0));
when "00000111" =>
when others =>
end case;
if smt_thread_instruction(1) = "00000000" then
ADDER_A <= smt_thread_arg1(1);
ADDER_B <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg3(1);
DATA1 <= ADDER_S;
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
elsif smt_thread_instruction(1) = "00000001" then
MULTIPLIER_A <= smt_thread_arg1(1);
MULTIPLIER_B <= smt_thread_arg2(1);
ADDR1 <= smt_thread_arg3(1);
DATA1 <= MULTIPLIER_C;
SET1 <= '1';
smt_thread_instruction_pointer(1) := increment_instruction_pointer(smt_thread_instruction_pointer(1));
end if;
end case;
end if;
OUTADDR0 <= smt_thread_instruction_pointer(0);
OUTADDR1 <= smt_thread_instruction_pointer(1);
end process;
end Behavioral;
|
mit
|
2bc50aadeefdef99fa9f3309976fc176
| 0.573979 | 3.904226 | false | false | false | false |
airlog/vhdl-rc4
|
src/rc4_crypto_tb.vhd
| 1 | 3,834 |
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY rc4_crypto_tb IS
END rc4_crypto_tb;
ARCHITECTURE behavior OF rc4_crypto_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc4_crypto
PORT(
enc_input : IN std_logic_vector(7 downto 0);
perm_input : IN std_logic_vector(7 downto 0);
go : IN std_logic;
clk : IN std_logic;
enc_output : OUT std_logic_vector(7 downto 0);
perm_ctrl : OUT std_logic;
perm_index : OUT std_logic_vector(7 downto 0);
perm_output : OUT std_logic_vector(7 downto 0);
rdy : OUT std_logic
);
END COMPONENT;
--Inputs
signal enc_input : std_logic_vector(7 downto 0) := (others => '0');
signal perm_input : std_logic_vector(7 downto 0);
signal go : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal enc_output : std_logic_vector(7 downto 0);
signal perm_ctrl : std_logic;
signal perm_index : std_logic_vector(7 downto 0);
signal perm_output : std_logic_vector(7 downto 0);
signal rdy : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
subtype rc4int is integer range 0 to 255;
type my_array is array (0 to 255) of rc4int;
shared variable sarr : my_array := (
185, 126, 115, 175, 200, 169, 108, 155,
013, 041, 091, 189, 046, 116, 109, 163,
120, 020, 078, 049, 012, 038, 213, 142,
096, 094, 001, 178, 206, 067, 105, 148,
156, 055, 158, 073, 081, 145, 009, 132,
002, 050, 039, 172, 244, 243, 139, 166,
040, 201, 063, 164, 165, 207, 170, 167,
159, 118, 061, 010, 222, 247, 104, 089,
223, 087, 193, 110, 099, 071, 031, 128,
203, 135, 034, 015, 161, 174, 029, 225,
019, 103, 080, 162, 056, 154, 058, 133,
234, 209, 236, 023, 151, 051, 060, 232,
090, 176, 113, 121, 230, 212, 251, 093,
026, 245, 097, 003, 035, 191, 238, 199,
249, 181, 188, 192, 205, 182, 027, 146,
184, 195, 119, 028, 112, 235, 079, 048,
086, 018, 171, 198, 007, 130, 043, 254,
092, 076, 025, 147, 054, 150, 014, 123,
030, 211, 084, 229, 037, 237, 000, 168,
044, 157, 083, 246, 088, 137, 253, 064,
075, 069, 017, 057, 047, 036, 059, 220,
242, 006, 153, 129, 004, 052, 202, 042,
085, 144, 106, 177, 190, 117, 187, 008,
204, 070, 226, 194, 186, 127, 033, 138,
136, 024, 100, 124, 180, 095, 173, 045,
239, 072, 005, 219, 066, 149, 228, 179,
210, 141, 143, 082, 208, 217, 215, 218,
053, 125, 021, 131, 214, 231, 022, 250,
074, 224, 252, 102, 107, 221, 077, 240,
140, 068, 062, 248, 255, 233, 227, 122,
114, 016, 065, 160, 111, 101, 196, 098,
197, 032, 183, 152, 216, 241, 011, 134);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc4_crypto PORT MAP (
enc_input => enc_input,
perm_input => perm_input,
go => go,
clk => clk,
enc_output => enc_output,
perm_ctrl => perm_ctrl,
perm_index => perm_index,
perm_output => perm_output,
rdy => rdy
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
array_proc: process(clk, perm_ctrl, perm_index, perm_output)
begin
if rising_edge(clk) then
if perm_ctrl = '1' then
sarr(conv_integer(unsigned(perm_index))) := conv_integer(unsigned(perm_output));
else
perm_input <= conv_std_logic_vector(sarr(conv_integer(unsigned(perm_index))), 8);
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
go <= '1';
wait;
end process;
END;
|
mit
|
6bc34418e46f0e89454f5020fa423783
| 0.574335 | 2.802632 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN.vhd
| 6 | 164,925 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ANN is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of ANN is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"ANN,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=37,HLS_SYN_FF=8935,HLS_SYN_LUT=12780}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (149 downto 0) := "000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (149 downto 0) := "000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (149 downto 0) := "000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (149 downto 0) := "000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (149 downto 0) := "000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (149 downto 0) := "000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (149 downto 0) := "000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (149 downto 0) := "000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (149 downto 0) := "000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (149 downto 0) := "001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (149 downto 0) := "010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (149 downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_81 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000001";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_66 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100110";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_67 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100111";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_54 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010100";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_BF800000 : STD_LOGIC_VECTOR (31 downto 0) := "10111111100000000000000000000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv14_29 : STD_LOGIC_VECTOR (13 downto 0) := "00000000101001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv32_95 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010101";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_168 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal P_index1 : STD_LOGIC_VECTOR (31 downto 0);
signal P_index2 : STD_LOGIC_VECTOR (31 downto 0);
signal P_intIn_index3 : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatIn : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce0 : STD_LOGIC;
signal ST_uOut_we0 : STD_LOGIC;
signal ST_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce1 : STD_LOGIC;
signal ST_uOut_we1 : STD_LOGIC;
signal ST_uOut_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal ANN_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal reg_490 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_253 : BOOLEAN;
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st89_fsm_88 : STD_LOGIC;
signal ap_sig_bdd_275 : BOOLEAN;
signal ap_sig_cseq_ST_st130_fsm_129 : STD_LOGIC;
signal ap_sig_bdd_283 : BOOLEAN;
signal reg_499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_292 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_301 : BOOLEAN;
signal grp_fu_428_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_311 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_318 : BOOLEAN;
signal grp_fu_421_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_328 : BOOLEAN;
signal ap_sig_cseq_ST_st97_fsm_96 : STD_LOGIC;
signal ap_sig_bdd_335 : BOOLEAN;
signal reg_516 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_344 : BOOLEAN;
signal ap_sig_cseq_ST_st103_fsm_102 : STD_LOGIC;
signal ap_sig_bdd_351 : BOOLEAN;
signal grp_fu_447_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_521 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_361 : BOOLEAN;
signal ap_sig_cseq_ST_st104_fsm_103 : STD_LOGIC;
signal ap_sig_bdd_368 : BOOLEAN;
signal grp_fu_464_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_526 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st48_fsm_47 : STD_LOGIC;
signal ap_sig_bdd_378 : BOOLEAN;
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_385 : BOOLEAN;
signal grp_fu_444_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st85_fsm_84 : STD_LOGIC;
signal ap_sig_bdd_395 : BOOLEAN;
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_402 : BOOLEAN;
signal P_floatIn_read_reg_1345 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer_load_reg_1353 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_609_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_76_reg_1378 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_1_fu_538_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_549_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_555_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_561_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_619_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_1384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_683_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_reg_1394 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_fu_721_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_reg_1399 : STD_LOGIC_VECTOR (13 downto 0);
signal max_2_cast_fu_761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal max_2_cast_reg_1407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_458 : BOOLEAN;
signal tmp_24_fu_765_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_798_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_4_reg_1425 : STD_LOGIC_VECTOR (30 downto 0);
signal ST_uOut_load_2_reg_1430 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_881_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_63_reg_1436 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_478 : BOOLEAN;
signal max_1_fu_887_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_487 : BOOLEAN;
signal grp_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_496 : BOOLEAN;
signal tmp_28_fu_926_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_28_reg_1454 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_505 : BOOLEAN;
signal tmp_3_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_932_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_reg_1459 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_38_fu_966_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_38_reg_1464 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_45_fu_972_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_45_reg_1469 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_56_fu_1000_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_56_reg_1474 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_58_fu_1006_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_58_reg_1479 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_fu_1010_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_64_reg_1484 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_69_fu_1043_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_reg_1489 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_1049_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_70_reg_1494 : STD_LOGIC_VECTOR (1 downto 0);
signal j_2_fu_1072_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_1502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_535 : BOOLEAN;
signal tmp_53_fu_1078_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_1507 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_80_fu_1333_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_reg_1513 : STD_LOGIC_VECTOR (13 downto 0);
signal ST_uOut_addr_5_reg_1519 : STD_LOGIC_VECTOR (7 downto 0);
signal i_3_fu_1105_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_fu_1120_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_reg_1532 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_557 : BOOLEAN;
signal tmp_33_fu_1115_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_454_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_reg_1552 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st53_fsm_52 : STD_LOGIC;
signal ap_sig_bdd_577 : BOOLEAN;
signal grp_fu_459_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_43_reg_1557 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_586 : BOOLEAN;
signal tmp_27_fu_1182_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_reg_1562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_595 : BOOLEAN;
signal i_5_fu_1201_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_5_reg_1570 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_1207_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_1575 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_1195_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_83_fu_1339_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_83_reg_1581 : STD_LOGIC_VECTOR (13 downto 0);
signal ST_uOut_addr_7_reg_1587 : STD_LOGIC_VECTOR (7 downto 0);
signal j_3_fu_1243_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_3_reg_1595 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_616 : BOOLEAN;
signal tmp_34_fu_1238_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st128_fsm_127 : STD_LOGIC;
signal ap_sig_bdd_635 : BOOLEAN;
signal i_6_fu_1299_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_1623 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st129_fsm_128 : STD_LOGIC;
signal ap_sig_bdd_644 : BOOLEAN;
signal ST_uOut_addr_8_reg_1628 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_35_fu_1294_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_435_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_reg_1634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_659 : BOOLEAN;
signal tmp_21_fu_1324_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_reg_1639 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_668 : BOOLEAN;
signal max_2_reg_266 : STD_LOGIC_VECTOR (30 downto 0);
signal max_reg_277 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_289 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_301 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st86_fsm_85 : STD_LOGIC;
signal ap_sig_bdd_690 : BOOLEAN;
signal sum_reg_312 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_324 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_335 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_347 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_358 : STD_LOGIC_VECTOR (31 downto 0);
signal j_1_reg_370 : STD_LOGIC_VECTOR (30 downto 0);
signal i_2_reg_381 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_712 : BOOLEAN;
signal p_0_reg_392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_728 : BOOLEAN;
signal tmp_66_cast_fu_673_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_678_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_779_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_793_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_cast_fu_1100_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_1139_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1149_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1162_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_84_cast_fu_1229_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1262_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_92_cast_fu_1272_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1285_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_94_cast_fu_1314_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_21_cast_fu_1329_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_727_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_818 : BOOLEAN;
signal grp_fu_421_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_421_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_837 : BOOLEAN;
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_844 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_852 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_859 : BOOLEAN;
signal grp_fu_428_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_444_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_447_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_1177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_74_fu_585_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_75_fu_597_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl12_cast_fu_589_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl13_cast_fu_601_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_619_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_72_fu_637_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_73_fu_649_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl10_cast_fu_641_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl11_cast_fu_653_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_71_fu_633_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_661_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_66_fu_667_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_691_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_703_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl_cast_fu_695_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_707_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_fu_687_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_715_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_94_fu_770_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_86_fu_774_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_95_fu_784_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_788_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ST_uOut_load_1_to_int_fu_804_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_load_2_to_int_fu_822_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_55_fu_808_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_818_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_839_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_57_fu_825_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_fu_835_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_863_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_869_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_875_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_450_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_cast_fu_893_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_902_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_fu_914_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl8_cast_fu_906_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl9_cast_fu_918_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_15_fu_936_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_30_fu_942_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_36_fu_954_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl6_cast_fu_946_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl7_cast_fu_958_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_47_fu_976_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_fu_988_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl4_cast_fu_980_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_992_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_fu_1014_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_67_fu_1019_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_68_fu_1031_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1023_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl3_cast_fu_1035_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_1053_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_1091_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_79_fu_1095_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_79_fu_1095_p2 : signal is "no";
signal k_cast_fu_1111_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_1130_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_88_fu_1134_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_88_fu_1134_p2 : signal is "no";
signal tmp_98_fu_1126_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_89_fu_1144_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_100_fu_1154_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_90_fu_1157_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_90_fu_1157_p2 : signal is "no";
signal tmp_39_to_int_fu_1167_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_neg_fu_1171_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_1220_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_fu_1224_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_82_fu_1224_p2 : signal is "no";
signal j_1_cast_fu_1234_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_102_fu_1253_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_91_fu_1257_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_91_fu_1257_p2 : signal is "no";
signal tmp_101_fu_1249_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_92_fu_1267_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_103_fu_1277_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_93_fu_1280_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_93_fu_1280_p2 : signal is "no";
signal i_2_cast_fu_1290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_84_fu_1305_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_fu_1309_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1319_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_fu_1333_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_83_fu_1339_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_421_ce : STD_LOGIC;
signal grp_fu_428_ce : STD_LOGIC;
signal grp_fu_435_ce : STD_LOGIC;
signal grp_fu_440_ce : STD_LOGIC;
signal tmp_62_fu_450_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_454_ce : STD_LOGIC;
signal grp_fu_459_ce : STD_LOGIC;
signal grp_fu_464_ce : STD_LOGIC;
signal ap_sig_cseq_ST_st150_fsm_149 : STD_LOGIC;
signal ap_sig_bdd_1429 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (149 downto 0);
component ANN_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_sitofp_32ns_32_6 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component ANN_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_mul_mul_7ns_14s_14_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component ANN_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_ST_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (31 downto 0);
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_return : IN STD_LOGIC_VECTOR (31 downto 0);
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index1 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index2 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_intIn_index3 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_floatIn : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ST_WandB_U : component ANN_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 6560,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
ST_uOut_U : component ANN_ST_uOut
generic map (
DataWidth => 32,
AddressRange => 160,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_uOut_address0,
ce0 => ST_uOut_ce0,
we0 => ST_uOut_we0,
d0 => ST_uOut_d0,
q0 => ST_uOut_q0,
address1 => ST_uOut_address1,
ce1 => ST_uOut_ce1,
we1 => ST_uOut_we1,
d1 => ST_uOut_d1,
q1 => ST_uOut_q1);
ANN_AXILiteS_s_axi_U : component ANN_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ANN_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
ap_return => ap_return,
P_mode => P_mode,
P_index1 => P_index1,
P_index2 => P_index2,
P_intIn_index3 => P_intIn_index3,
P_floatIn => P_floatIn);
ANN_fadd_32ns_32ns_32_5_full_dsp_U0 : component ANN_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_421_p0,
din1 => grp_fu_421_p1,
ce => grp_fu_421_ce,
dout => grp_fu_421_p2);
ANN_fmul_32ns_32ns_32_4_max_dsp_U1 : component ANN_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_428_p0,
din1 => ST_WandB_q0,
ce => grp_fu_428_ce,
dout => grp_fu_428_p2);
ANN_fdiv_32ns_32ns_32_16_U2 : component ANN_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_490,
din1 => sumsoft_reg_335,
ce => grp_fu_435_ce,
dout => grp_fu_435_p2);
ANN_sitofp_32ns_32_6_U3 : component ANN_sitofp_32ns_32_6
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => max_reg_277,
ce => grp_fu_440_ce,
dout => grp_fu_440_p1);
ANN_fptrunc_64ns_32_1_U4 : component ANN_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_444_p0,
dout => grp_fu_444_p1);
ANN_fpext_32ns_64_1_U5 : component ANN_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_447_p0,
dout => grp_fu_447_p1);
ANN_fcmp_32ns_32ns_1_1_U6 : component ANN_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_490,
din1 => ST_uOut_load_2_reg_1430,
opcode => tmp_62_fu_450_opcode,
dout => tmp_62_fu_450_p2);
ANN_dadd_64ns_64ns_64_5_full_dsp_U7 : component ANN_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_526,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_454_ce,
dout => grp_fu_454_p2);
ANN_ddiv_64ns_64ns_64_31_U8 : component ANN_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_42_reg_1552,
ce => grp_fu_459_ce,
dout => grp_fu_459_p2);
ANN_dexp_64ns_64ns_64_18_full_dsp_U9 : component ANN_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_521,
ce => grp_fu_464_ce,
dout => grp_fu_464_p2);
ANN_mux_4to1_sel2_32_1_U10 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_31_fu_619_p5,
dout => tmp_31_fu_619_p6);
ANN_mux_4to1_sel2_32_1_U11 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_29_reg_1459,
dout => tmp_fu_1053_p6);
ANN_mux_4to1_sel2_32_1_U12 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_45_reg_1469,
dout => tmp_53_fu_1078_p6);
ANN_mux_4to1_sel2_32_1_U13 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_64_reg_1484,
dout => tmp_27_fu_1182_p6);
ANN_mux_4to1_sel2_32_1_U14 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_70_reg_1494,
dout => tmp_54_fu_1207_p6);
ANN_mul_mul_7ns_14s_14_1_U15 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_80_fu_1333_p0,
din1 => tmp_79_fu_1095_p2,
dout => tmp_80_fu_1333_p2);
ANN_mul_mul_7ns_14s_14_1_U16 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_83_fu_1339_p0,
din1 => tmp_82_fu_1224_p2,
dout => tmp_83_fu_1339_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i_1_reg_347 assign process. --
i_1_reg_347_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = tmp_3_fu_897_p2))) then
i_1_reg_347 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) then
i_1_reg_347 <= i_5_reg_1570;
end if;
end if;
end process;
-- i_2_reg_381 assign process. --
i_2_reg_381_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and (ap_const_lv1_0 = tmp_22_fu_1195_p2))) then
i_2_reg_381 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
i_2_reg_381 <= i_6_reg_1623;
end if;
end if;
end process;
-- i_reg_289 assign process. --
i_reg_289_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and not((ap_const_lv1_0 = tmp_s_fu_567_p2)))) then
i_reg_289 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and (ap_const_lv1_0 = tmp_20_fu_1066_p2))) then
i_reg_289 <= i_3_fu_1105_p2;
end if;
end if;
end process;
-- j_1_reg_370 assign process. --
j_1_reg_370_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and not((ap_const_lv1_0 = tmp_22_fu_1195_p2)))) then
j_1_reg_370 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) then
j_1_reg_370 <= j_3_reg_1595;
end if;
end if;
end process;
-- j_reg_301 assign process. --
j_reg_301_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_3_fu_897_p2)))) then
j_reg_301 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) then
j_reg_301 <= j_2_reg_1502;
end if;
end if;
end process;
-- k_reg_324 assign process. --
k_reg_324_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = tmp_20_fu_1066_p2)))) then
k_reg_324 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
k_reg_324 <= k_1_reg_1532;
end if;
end if;
end process;
-- max_2_reg_266 assign process. --
max_2_reg_266_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
max_2_reg_266 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_2_reg_266 <= i_4_reg_1425;
end if;
end if;
end process;
-- max_reg_277 assign process. --
max_reg_277_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
max_reg_277 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_reg_277 <= max_1_fu_887_p3;
end if;
end if;
end process;
-- p_0_reg_392 assign process. --
p_0_reg_392_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and (ap_const_lv1_0 = tmp_14_fu_579_p2))) then
p_0_reg_392 <= ap_const_lv32_BF800000;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
p_0_reg_392 <= grp_fu_440_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
p_0_reg_392 <= ST_uOut_q0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_1_fu_538_p2 = ap_const_lv1_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128) and (ap_const_lv1_0 = tmp_35_fu_1294_p2)))) then
p_0_reg_392 <= ap_const_lv32_0;
end if;
end if;
end process;
-- reg_490 assign process. --
reg_490_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
reg_490 <= ST_uOut_q1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88) or (ap_const_logic_1 = ap_sig_cseq_ST_st130_fsm_129))) then
reg_490 <= ST_uOut_q0;
end if;
end if;
end process;
-- sum_1_reg_358 assign process. --
sum_1_reg_358_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and not((ap_const_lv1_0 = tmp_22_fu_1195_p2)))) then
sum_1_reg_358 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) then
sum_1_reg_358 <= grp_fu_421_p2;
end if;
end if;
end process;
-- sum_reg_312 assign process. --
sum_reg_312_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = tmp_20_fu_1066_p2)))) then
sum_reg_312 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
sum_reg_312 <= grp_fu_421_p2;
end if;
end if;
end process;
-- sumsoft_reg_335 assign process. --
sumsoft_reg_335_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = tmp_3_fu_897_p2))) then
sumsoft_reg_335 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) then
sumsoft_reg_335 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
P_floatIn_read_reg_1345 <= P_floatIn;
ST_numLayer_load_reg_1353 <= ST_numLayer;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and (tmp_5_fu_727_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and (tmp_5_fu_727_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and (tmp_5_fu_727_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and not((tmp_5_fu_727_p1 = ap_const_lv2_2)) and not((tmp_5_fu_727_p1 = ap_const_lv2_1)) and not((tmp_5_fu_727_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_1_fu_538_p2 = ap_const_lv1_0)))) then
ST_numLayer <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = tmp_20_fu_1066_p2)))) then
ST_uOut_addr_5_reg_1519 <= tmp_82_cast_fu_1100_p1(8 - 1 downto 0);
tmp_53_reg_1507 <= tmp_53_fu_1078_p6;
tmp_80_reg_1513 <= tmp_80_fu_1333_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and not((ap_const_lv1_0 = tmp_22_fu_1195_p2)))) then
ST_uOut_addr_7_reg_1587 <= tmp_84_cast_fu_1229_p1(8 - 1 downto 0);
tmp_54_reg_1575 <= tmp_54_fu_1207_p6;
tmp_83_reg_1581 <= tmp_83_fu_1339_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128) and not((ap_const_lv1_0 = tmp_35_fu_1294_p2)))) then
ST_uOut_addr_8_reg_1628 <= tmp_94_cast_fu_1314_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ST_uOut_load_2_reg_1430 <= ST_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_24_fu_765_p2)))) then
i_4_reg_1425 <= i_4_fu_798_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) then
i_5_reg_1570 <= i_5_fu_1201_p2;
tmp_27_reg_1562 <= tmp_27_fu_1182_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) then
i_6_reg_1623 <= i_6_fu_1299_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
j_2_reg_1502 <= j_2_fu_1072_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
j_3_reg_1595 <= j_3_fu_1243_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
k_1_reg_1532 <= k_1_fu_1120_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
max_2_cast_reg_1407(30 downto 0) <= max_2_cast_fu_761_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_499 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91))) then
reg_505 <= grp_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or (ap_const_logic_1 = ap_sig_cseq_ST_st103_fsm_102))) then
reg_516 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103))) then
reg_521 <= grp_fu_447_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47) or (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121))) then
reg_526 <= grp_fu_464_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84) or (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122))) then
reg_532 <= grp_fu_444_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and not((ap_const_lv1_0 = tmp_4_fu_555_p2)))) then
tmp_16_reg_1399 <= tmp_16_fu_721_p2;
tmp_6_reg_1394 <= tmp_6_fu_683_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
tmp_21_reg_1639 <= tmp_21_fu_1324_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_3_fu_897_p2)))) then
tmp_28_reg_1454(13 downto 3) <= tmp_28_fu_926_p2(13 downto 3);
tmp_29_reg_1459 <= tmp_29_fu_932_p1;
tmp_38_reg_1464(8 downto 3) <= tmp_38_fu_966_p2(8 downto 3);
tmp_45_reg_1469 <= tmp_45_fu_972_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
tmp_31_reg_1384 <= tmp_31_fu_619_p6;
tmp_76_reg_1378(8 downto 3) <= tmp_76_fu_609_p2(8 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52)) then
tmp_42_reg_1552 <= grp_fu_454_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83)) then
tmp_43_reg_1557 <= grp_fu_459_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
tmp_52_reg_1634 <= grp_fu_435_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = tmp_3_fu_897_p2))) then
tmp_56_reg_1474(13 downto 3) <= tmp_56_fu_1000_p2(13 downto 3);
tmp_58_reg_1479(8 downto 3) <= tmp_58_fu_1006_p1(8 downto 3);
tmp_64_reg_1484 <= tmp_64_fu_1010_p1;
tmp_69_reg_1489(8 downto 3) <= tmp_69_fu_1043_p2(8 downto 3);
tmp_70_reg_1494 <= tmp_70_fu_1049_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_63_reg_1436 <= tmp_63_fu_881_p2;
end if;
end if;
end process;
tmp_76_reg_1378(2 downto 0) <= "000";
max_2_cast_reg_1407(31) <= '0';
tmp_28_reg_1454(2 downto 0) <= "000";
tmp_38_reg_1464(2 downto 0) <= "000";
tmp_56_reg_1474(2 downto 0) <= "000";
tmp_58_reg_1479(2 downto 0) <= "000";
tmp_69_reg_1489(2 downto 0) <= "000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2, tmp_s_fu_567_p2, tmp_10_fu_573_p2, tmp_14_fu_579_p2, tmp_24_fu_765_p2, tmp_3_fu_897_p2, tmp_20_fu_1066_p2, tmp_33_fu_1115_p2, tmp_22_fu_1195_p2, tmp_34_fu_1238_p2, tmp_35_fu_1294_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((ap_start = ap_const_logic_0)) and (not((tmp_1_fu_538_p2 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_2_fu_549_p2)) or ((ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))) or ((ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and (ap_const_lv1_0 = tmp_14_fu_579_p2))))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and not((ap_const_lv1_0 = tmp_10_fu_573_p2)))) then
ap_NS_fsm <= ap_ST_st11_fsm_10;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and not((ap_const_lv1_0 = tmp_s_fu_567_p2)))) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and not((ap_const_lv1_0 = tmp_4_fu_555_p2)))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((ap_const_lv1_0 = tmp_24_fu_765_p2)) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st12_fsm_11 =>
if ((ap_const_lv1_0 = tmp_3_fu_897_p2)) then
ap_NS_fsm <= ap_ST_st87_fsm_86;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st13_fsm_12 =>
if ((ap_const_lv1_0 = tmp_20_fu_1066_p2)) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st14_fsm_13 =>
if ((ap_const_lv1_0 = tmp_33_fu_1115_p2)) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st15_fsm_14;
end if;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st80_fsm_79;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st87_fsm_86 =>
if (not((ap_const_lv1_0 = tmp_22_fu_1195_p2))) then
ap_NS_fsm <= ap_ST_st88_fsm_87;
else
ap_NS_fsm <= ap_ST_st129_fsm_128;
end if;
when ap_ST_st88_fsm_87 =>
if ((ap_const_lv1_0 = tmp_34_fu_1238_p2)) then
ap_NS_fsm <= ap_ST_st98_fsm_97;
else
ap_NS_fsm <= ap_ST_st89_fsm_88;
end if;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st93_fsm_92;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st129_fsm_128 =>
if ((ap_const_lv1_0 = tmp_35_fu_1294_p2)) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st130_fsm_129;
end if;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st143_fsm_142 =>
ap_NS_fsm <= ap_ST_st144_fsm_143;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st147_fsm_146;
when ap_ST_st147_fsm_146 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st148_fsm_147 =>
ap_NS_fsm <= ap_ST_st149_fsm_148;
when ap_ST_st149_fsm_148 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ANN_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13, tmp_33_fu_1115_p2, ap_sig_cseq_ST_st88_fsm_87, tmp_34_fu_1238_p2, ap_sig_cseq_ST_st149_fsm_148, tmp_88_cast_fu_1139_p1, tmp_90_cast_fu_1162_p1, tmp_91_cast_fu_1262_p1, tmp_93_cast_fu_1285_p1, tmp_21_cast_fu_1329_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) then
ST_WandB_address0 <= tmp_21_cast_fu_1329_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and (ap_const_lv1_0 = tmp_34_fu_1238_p2))) then
ST_WandB_address0 <= tmp_93_cast_fu_1285_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and not((ap_const_lv1_0 = tmp_34_fu_1238_p2)))) then
ST_WandB_address0 <= tmp_91_cast_fu_1262_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and (ap_const_lv1_0 = tmp_33_fu_1115_p2))) then
ST_WandB_address0 <= tmp_90_cast_fu_1162_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and not((ap_const_lv1_0 = tmp_33_fu_1115_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_1139_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13, tmp_33_fu_1115_p2, ap_sig_cseq_ST_st88_fsm_87, tmp_34_fu_1238_p2, ap_sig_cseq_ST_st149_fsm_148)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and not((ap_const_lv1_0 = tmp_33_fu_1115_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and (ap_const_lv1_0 = tmp_33_fu_1115_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and not((ap_const_lv1_0 = tmp_34_fu_1238_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and (ap_const_lv1_0 = tmp_34_fu_1238_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_floatIn_read_reg_1345;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st149_fsm_148)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_address0 assign process. --
ST_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2, tmp_s_fu_567_p2, tmp_10_fu_573_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st129_fsm_128, tmp_66_cast_fu_673_p1, tmp_9_fu_678_p1, tmp_86_cast_fu_779_p1, tmp_92_cast_fu_1272_p1, tmp_94_cast_fu_1314_p1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2)))) then
ST_uOut_address0 <= tmp_9_fu_678_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) then
ST_uOut_address0 <= tmp_94_cast_fu_1314_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
ST_uOut_address0 <= tmp_92_cast_fu_1272_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address0 <= tmp_86_cast_fu_779_p1(8 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and not((ap_const_lv1_0 = tmp_10_fu_573_p2)))) then
ST_uOut_address0 <= tmp_66_cast_fu_673_p1(8 - 1 downto 0);
else
ST_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_address1 assign process. --
ST_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ST_uOut_addr_5_reg_1519, ap_sig_cseq_ST_st14_fsm_13, ST_uOut_addr_7_reg_1587, ST_uOut_addr_8_reg_1628, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, tmp_87_cast_fu_793_p1, tmp_89_cast_fu_1149_p1, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
ST_uOut_address1 <= ST_uOut_addr_8_reg_1628;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
ST_uOut_address1 <= ST_uOut_addr_7_reg_1587;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) then
ST_uOut_address1 <= ST_uOut_addr_5_reg_1519;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
ST_uOut_address1 <= tmp_89_cast_fu_1149_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address1 <= tmp_87_cast_fu_793_p1(8 - 1 downto 0);
else
ST_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_ce0 assign process. --
ST_uOut_ce0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2, tmp_s_fu_567_p2, tmp_10_fu_573_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st129_fsm_128)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and not((ap_const_lv1_0 = tmp_10_fu_573_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))))) then
ST_uOut_ce0 <= ap_const_logic_1;
else
ST_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_ce1 assign process. --
ST_uOut_ce1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st124_fsm_123)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
ST_uOut_ce1 <= ap_const_logic_1;
else
ST_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
ST_uOut_d0 <= P_floatIn;
-- ST_uOut_d1 assign process. --
ST_uOut_d1_assign_proc : process(reg_532, tmp_52_reg_1634, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
ST_uOut_d1 <= tmp_52_reg_1634;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
ST_uOut_d1 <= reg_532;
else
ST_uOut_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
ST_uOut_load_1_to_int_fu_804_p1 <= reg_490;
ST_uOut_load_2_to_int_fu_822_p1 <= ST_uOut_load_2_reg_1430;
-- ST_uOut_we0 assign process. --
ST_uOut_we0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))))) then
ST_uOut_we0 <= ap_const_logic_1;
else
ST_uOut_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_we1 assign process. --
ST_uOut_we1_assign_proc : process(ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st124_fsm_123)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
ST_uOut_we1 <= ap_const_logic_1;
else
ST_uOut_we1 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st150_fsm_149)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st150_fsm_149)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_392;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1429 assign process. --
ap_sig_bdd_1429_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1429 <= (ap_const_lv1_1 = ap_CS_fsm(149 downto 149));
end process;
-- ap_sig_bdd_168 assign process. --
ap_sig_bdd_168_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_168 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_253 assign process. --
ap_sig_bdd_253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_253 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_275 assign process. --
ap_sig_bdd_275_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_275 <= (ap_const_lv1_1 = ap_CS_fsm(88 downto 88));
end process;
-- ap_sig_bdd_283 assign process. --
ap_sig_bdd_283_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_283 <= (ap_const_lv1_1 = ap_CS_fsm(129 downto 129));
end process;
-- ap_sig_bdd_292 assign process. --
ap_sig_bdd_292_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_292 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_301 assign process. --
ap_sig_bdd_301_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_301 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_311 assign process. --
ap_sig_bdd_311_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_311 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_318 assign process. --
ap_sig_bdd_318_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_318 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_328 assign process. --
ap_sig_bdd_328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_328 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_335 assign process. --
ap_sig_bdd_335_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_335 <= (ap_const_lv1_1 = ap_CS_fsm(96 downto 96));
end process;
-- ap_sig_bdd_344 assign process. --
ap_sig_bdd_344_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_344 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_351 assign process. --
ap_sig_bdd_351_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_351 <= (ap_const_lv1_1 = ap_CS_fsm(102 downto 102));
end process;
-- ap_sig_bdd_361 assign process. --
ap_sig_bdd_361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_361 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_368 assign process. --
ap_sig_bdd_368_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_368 <= (ap_const_lv1_1 = ap_CS_fsm(103 downto 103));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_378 <= (ap_const_lv1_1 = ap_CS_fsm(47 downto 47));
end process;
-- ap_sig_bdd_385 assign process. --
ap_sig_bdd_385_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_385 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_395 <= (ap_const_lv1_1 = ap_CS_fsm(84 downto 84));
end process;
-- ap_sig_bdd_402 assign process. --
ap_sig_bdd_402_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_402 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_458 assign process. --
ap_sig_bdd_458_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_458 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_478 assign process. --
ap_sig_bdd_478_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_478 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_487 assign process. --
ap_sig_bdd_487_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_487 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_496 assign process. --
ap_sig_bdd_496_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_496 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_505 assign process. --
ap_sig_bdd_505_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_505 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_535 assign process. --
ap_sig_bdd_535_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_535 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_557 assign process. --
ap_sig_bdd_557_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_557 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_577 assign process. --
ap_sig_bdd_577_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_577 <= (ap_const_lv1_1 = ap_CS_fsm(52 downto 52));
end process;
-- ap_sig_bdd_586 assign process. --
ap_sig_bdd_586_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_586 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_595 assign process. --
ap_sig_bdd_595_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_595 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_616 assign process. --
ap_sig_bdd_616_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_616 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_635 assign process. --
ap_sig_bdd_635_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_635 <= (ap_const_lv1_1 = ap_CS_fsm(127 downto 127));
end process;
-- ap_sig_bdd_644 assign process. --
ap_sig_bdd_644_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_644 <= (ap_const_lv1_1 = ap_CS_fsm(128 downto 128));
end process;
-- ap_sig_bdd_659 assign process. --
ap_sig_bdd_659_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_659 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_668 assign process. --
ap_sig_bdd_668_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_668 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_690 assign process. --
ap_sig_bdd_690_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_690 <= (ap_const_lv1_1 = ap_CS_fsm(85 downto 85));
end process;
-- ap_sig_bdd_712 assign process. --
ap_sig_bdd_712_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_712 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_728 assign process. --
ap_sig_bdd_728_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_728 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_818 assign process. --
ap_sig_bdd_818_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_818 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_837 assign process. --
ap_sig_bdd_837_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_837 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_844 assign process. --
ap_sig_bdd_844_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_844 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_852 assign process. --
ap_sig_bdd_852_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_852 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_859 assign process. --
ap_sig_bdd_859_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_859 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_cseq_ST_st103_fsm_102 assign process. --
ap_sig_cseq_ST_st103_fsm_102_assign_proc : process(ap_sig_bdd_351)
begin
if (ap_sig_bdd_351) then
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st104_fsm_103 assign process. --
ap_sig_cseq_ST_st104_fsm_103_assign_proc : process(ap_sig_bdd_368)
begin
if (ap_sig_bdd_368) then
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_496)
begin
if (ap_sig_bdd_496) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_385)
begin
if (ap_sig_bdd_385) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_402)
begin
if (ap_sig_bdd_402) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_818)
begin
if (ap_sig_bdd_818) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st128_fsm_127 assign process. --
ap_sig_cseq_ST_st128_fsm_127_assign_proc : process(ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) then
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st129_fsm_128 assign process. --
ap_sig_cseq_ST_st129_fsm_128_assign_proc : process(ap_sig_bdd_644)
begin
if (ap_sig_bdd_644) then
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_505)
begin
if (ap_sig_bdd_505) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st130_fsm_129 assign process. --
ap_sig_cseq_ST_st130_fsm_129_assign_proc : process(ap_sig_bdd_283)
begin
if (ap_sig_bdd_283) then
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_535)
begin
if (ap_sig_bdd_535) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_659)
begin
if (ap_sig_bdd_659) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_712)
begin
if (ap_sig_bdd_712) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_668)
begin
if (ap_sig_bdd_668) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_728)
begin
if (ap_sig_bdd_728) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_557)
begin
if (ap_sig_bdd_557) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st150_fsm_149 assign process. --
ap_sig_cseq_ST_st150_fsm_149_assign_proc : process(ap_sig_bdd_1429)
begin
if (ap_sig_bdd_1429) then
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_311)
begin
if (ap_sig_bdd_311) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_837)
begin
if (ap_sig_bdd_837) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_168)
begin
if (ap_sig_bdd_168) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_328)
begin
if (ap_sig_bdd_328) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_292)
begin
if (ap_sig_bdd_292) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_844)
begin
if (ap_sig_bdd_844) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_344)
begin
if (ap_sig_bdd_344) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_458)
begin
if (ap_sig_bdd_458) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_361)
begin
if (ap_sig_bdd_361) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st48_fsm_47 assign process. --
ap_sig_cseq_ST_st48_fsm_47_assign_proc : process(ap_sig_bdd_378)
begin
if (ap_sig_bdd_378) then
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_478)
begin
if (ap_sig_bdd_478) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st53_fsm_52 assign process. --
ap_sig_cseq_ST_st53_fsm_52_assign_proc : process(ap_sig_bdd_577)
begin
if (ap_sig_bdd_577) then
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_487)
begin
if (ap_sig_bdd_487) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_586)
begin
if (ap_sig_bdd_586) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st85_fsm_84 assign process. --
ap_sig_cseq_ST_st85_fsm_84_assign_proc : process(ap_sig_bdd_395)
begin
if (ap_sig_bdd_395) then
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st86_fsm_85 assign process. --
ap_sig_cseq_ST_st86_fsm_85_assign_proc : process(ap_sig_bdd_690)
begin
if (ap_sig_bdd_690) then
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_595)
begin
if (ap_sig_bdd_595) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_616)
begin
if (ap_sig_bdd_616) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st89_fsm_88 assign process. --
ap_sig_cseq_ST_st89_fsm_88_assign_proc : process(ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) then
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_318)
begin
if (ap_sig_bdd_318) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_852)
begin
if (ap_sig_bdd_852) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st97_fsm_96 assign process. --
ap_sig_cseq_ST_st97_fsm_96_assign_proc : process(ap_sig_bdd_335)
begin
if (ap_sig_bdd_335) then
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_301)
begin
if (ap_sig_bdd_301) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_859)
begin
if (ap_sig_bdd_859) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
grp_fu_421_ce <= ap_const_logic_1;
-- grp_fu_421_p0 assign process. --
grp_fu_421_p0_assign_proc : process(sum_reg_312, sumsoft_reg_335, sum_1_reg_358, ap_sig_cseq_ST_st124_fsm_123, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st93_fsm_92, ap_sig_cseq_ST_st99_fsm_98)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_421_p0 <= sumsoft_reg_335;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
grp_fu_421_p0 <= sum_1_reg_358;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
grp_fu_421_p0 <= sum_reg_312;
else
grp_fu_421_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_421_p1 assign process. --
grp_fu_421_p1_assign_proc : process(reg_499, reg_505, reg_532, ap_sig_cseq_ST_st124_fsm_123, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st93_fsm_92, ap_sig_cseq_ST_st99_fsm_98)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_421_p1 <= reg_532;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
grp_fu_421_p1 <= reg_499;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
grp_fu_421_p1 <= reg_505;
else
grp_fu_421_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_428_ce <= ap_const_logic_1;
-- grp_fu_428_p0 assign process. --
grp_fu_428_p0_assign_proc : process(ST_uOut_q0, ST_uOut_q1, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st89_fsm_88)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) then
grp_fu_428_p0 <= ST_uOut_q0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
grp_fu_428_p0 <= ST_uOut_q1;
else
grp_fu_428_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_435_ce <= ap_const_logic_1;
grp_fu_440_ce <= ap_const_logic_1;
-- grp_fu_444_p0 assign process. --
grp_fu_444_p0_assign_proc : process(reg_526, ap_sig_cseq_ST_st85_fsm_84, ap_sig_cseq_ST_st123_fsm_122, tmp_43_reg_1557)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
grp_fu_444_p0 <= reg_526;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84)) then
grp_fu_444_p0 <= tmp_43_reg_1557;
else
grp_fu_444_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_447_p0 assign process. --
grp_fu_447_p0_assign_proc : process(reg_516, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st104_fsm_103, tmp_39_fu_1177_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103)) then
grp_fu_447_p0 <= reg_516;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
grp_fu_447_p0 <= tmp_39_fu_1177_p1;
else
grp_fu_447_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_454_ce <= ap_const_logic_1;
grp_fu_459_ce <= ap_const_logic_1;
grp_fu_464_ce <= ap_const_logic_1;
-- grp_fu_469_p1 assign process. --
grp_fu_469_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ST_numLayer, ST_numLayer_load_reg_1353, ap_sig_cseq_ST_st12_fsm_11)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
grp_fu_469_p1 <= ST_numLayer_load_reg_1353;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_469_p1 <= ST_numLayer;
else
grp_fu_469_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_469_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(grp_fu_469_p1));
i_2_cast_fu_1290_p1 <= std_logic_vector(resize(unsigned(i_2_reg_381),32));
i_3_fu_1105_p2 <= std_logic_vector(unsigned(i_reg_289) + unsigned(ap_const_lv31_1));
i_4_fu_798_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(max_2_reg_266));
i_5_fu_1201_p2 <= std_logic_vector(unsigned(i_1_reg_347) + unsigned(ap_const_lv32_1));
i_6_fu_1299_p2 <= std_logic_vector(unsigned(i_2_reg_381) + unsigned(ap_const_lv31_1));
i_cast_fu_893_p1 <= std_logic_vector(resize(unsigned(i_reg_289),32));
j_1_cast_fu_1234_p1 <= std_logic_vector(resize(unsigned(j_1_reg_370),32));
j_2_fu_1072_p2 <= std_logic_vector(unsigned(j_reg_301) + unsigned(ap_const_lv32_1));
j_3_fu_1243_p2 <= std_logic_vector(unsigned(j_1_reg_370) + unsigned(ap_const_lv31_1));
k_1_fu_1120_p2 <= std_logic_vector(unsigned(k_reg_324) + unsigned(ap_const_lv31_1));
k_cast_fu_1111_p1 <= std_logic_vector(resize(unsigned(k_reg_324),32));
max_1_fu_887_p3 <=
max_2_cast_reg_1407 when (tmp_63_reg_1436(0) = '1') else
max_reg_277;
max_2_cast_fu_761_p1 <= std_logic_vector(resize(unsigned(max_2_reg_266),32));
notlhs1_fu_857_p2 <= "0" when (tmp_57_fu_825_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_839_p2 <= "0" when (tmp_55_fu_808_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_863_p2 <= "1" when (tmp_97_fu_835_p1 = ap_const_lv23_0) else "0";
notrhs_fu_845_p2 <= "1" when (tmp_96_fu_818_p1 = ap_const_lv23_0) else "0";
p_shl10_cast_fu_641_p3 <= (tmp_72_fu_637_p1 & ap_const_lv5_0);
p_shl11_cast_fu_653_p3 <= (tmp_73_fu_649_p1 & ap_const_lv3_0);
p_shl12_cast_fu_589_p3 <= (tmp_74_fu_585_p1 & ap_const_lv5_0);
p_shl13_cast_fu_601_p3 <= (tmp_75_fu_597_p1 & ap_const_lv3_0);
p_shl1_cast_fu_707_p3 <= (tmp_12_fu_703_p1 & ap_const_lv3_0);
p_shl2_cast_fu_1023_p3 <= (tmp_67_fu_1019_p1 & ap_const_lv5_0);
p_shl3_cast_fu_1035_p3 <= (tmp_68_fu_1031_p1 & ap_const_lv3_0);
p_shl4_cast_fu_980_p3 <= (tmp_47_fu_976_p1 & ap_const_lv5_0);
p_shl5_cast_fu_992_p3 <= (tmp_51_fu_988_p1 & ap_const_lv3_0);
p_shl6_cast_fu_946_p3 <= (tmp_30_fu_942_p1 & ap_const_lv5_0);
p_shl7_cast_fu_958_p3 <= (tmp_36_fu_954_p1 & ap_const_lv3_0);
p_shl8_cast_fu_906_p3 <= (tmp_25_fu_902_p1 & ap_const_lv5_0);
p_shl9_cast_fu_918_p3 <= (tmp_26_fu_914_p1 & ap_const_lv3_0);
p_shl_cast_fu_695_p3 <= (tmp_11_fu_691_p1 & ap_const_lv5_0);
tmp_100_fu_1154_p1 <= tmp_53_reg_1507(14 - 1 downto 0);
tmp_101_fu_1249_p1 <= j_1_reg_370(9 - 1 downto 0);
tmp_102_fu_1253_p1 <= j_1_reg_370(14 - 1 downto 0);
tmp_103_fu_1277_p1 <= tmp_54_reg_1575(14 - 1 downto 0);
tmp_10_fu_573_p2 <= "1" when (P_mode = ap_const_lv32_6) else "0";
tmp_11_fu_691_p1 <= P_index1(9 - 1 downto 0);
tmp_12_fu_703_p1 <= P_index1(11 - 1 downto 0);
tmp_13_fu_715_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_695_p3) + unsigned(p_shl1_cast_fu_707_p3));
tmp_14_fu_579_p2 <= "1" when (P_mode = ap_const_lv32_7) else "0";
tmp_15_fu_936_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_reg_289));
tmp_16_fu_721_p2 <= std_logic_vector(unsigned(tmp_7_fu_687_p1) + unsigned(tmp_13_fu_715_p2));
tmp_19_fu_1319_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv14_29) * signed(tmp_16_reg_1399))), 14));
tmp_1_fu_538_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_20_fu_1066_p2 <= "1" when (signed(j_reg_301) < signed(tmp_fu_1053_p6)) else "0";
tmp_21_cast_fu_1329_p1 <= std_logic_vector(resize(signed(tmp_21_reg_1639),64));
tmp_21_fu_1324_p2 <= std_logic_vector(unsigned(tmp_6_reg_1394) + unsigned(tmp_19_fu_1319_p2));
tmp_22_fu_1195_p2 <= "1" when (signed(i_1_reg_347) < signed(tmp_27_fu_1182_p6)) else "0";
tmp_23_fu_1014_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1353));
tmp_24_fu_765_p2 <= "1" when (signed(max_2_cast_fu_761_p1) < signed(tmp_31_reg_1384)) else "0";
tmp_25_fu_902_p1 <= i_reg_289(9 - 1 downto 0);
tmp_26_fu_914_p1 <= i_reg_289(11 - 1 downto 0);
tmp_28_fu_926_p2 <= std_logic_vector(unsigned(p_shl8_cast_fu_906_p3) + unsigned(p_shl9_cast_fu_918_p3));
tmp_29_fu_932_p1 <= i_reg_289(2 - 1 downto 0);
tmp_2_fu_549_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_30_fu_942_p1 <= tmp_15_fu_936_p2(4 - 1 downto 0);
tmp_31_fu_619_p5 <= grp_fu_469_p2(2 - 1 downto 0);
tmp_33_fu_1115_p2 <= "1" when (signed(k_cast_fu_1111_p1) < signed(tmp_53_reg_1507)) else "0";
tmp_34_fu_1238_p2 <= "1" when (signed(j_1_cast_fu_1234_p1) < signed(tmp_54_reg_1575)) else "0";
tmp_35_fu_1294_p2 <= "1" when (signed(i_2_cast_fu_1290_p1) < signed(tmp_27_reg_1562)) else "0";
tmp_36_fu_954_p1 <= tmp_15_fu_936_p2(6 - 1 downto 0);
tmp_38_fu_966_p2 <= std_logic_vector(unsigned(p_shl6_cast_fu_946_p3) + unsigned(p_shl7_cast_fu_958_p3));
tmp_39_fu_1177_p1 <= tmp_39_neg_fu_1171_p2;
tmp_39_neg_fu_1171_p2 <= (tmp_39_to_int_fu_1167_p1 xor ap_const_lv32_80000000);
tmp_39_to_int_fu_1167_p1 <= reg_516;
tmp_3_fu_897_p2 <= "1" when (signed(i_cast_fu_893_p1) < signed(ST_numLayer_load_reg_1353)) else "0";
tmp_45_fu_972_p1 <= tmp_15_fu_936_p2(2 - 1 downto 0);
tmp_47_fu_976_p1 <= grp_fu_469_p2(9 - 1 downto 0);
tmp_4_fu_555_p2 <= "1" when (P_mode = ap_const_lv32_3) else "0";
tmp_51_fu_988_p1 <= grp_fu_469_p2(11 - 1 downto 0);
tmp_55_fu_808_p4 <= ST_uOut_load_1_to_int_fu_804_p1(30 downto 23);
tmp_56_fu_1000_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_980_p3) + unsigned(p_shl5_cast_fu_992_p3));
tmp_57_fu_825_p4 <= ST_uOut_load_2_to_int_fu_822_p1(30 downto 23);
tmp_58_fu_1006_p1 <= tmp_56_fu_1000_p2(9 - 1 downto 0);
tmp_59_fu_851_p2 <= (notrhs_fu_845_p2 or notlhs_fu_839_p2);
tmp_5_fu_727_p1 <= P_index1(2 - 1 downto 0);
tmp_60_fu_869_p2 <= (notrhs2_fu_863_p2 or notlhs1_fu_857_p2);
tmp_61_fu_875_p2 <= (tmp_59_fu_851_p2 and tmp_60_fu_869_p2);
tmp_62_fu_450_opcode <= ap_const_lv5_2;
tmp_63_fu_881_p2 <= (tmp_61_fu_875_p2 and tmp_62_fu_450_p2);
tmp_64_fu_1010_p1 <= grp_fu_469_p2(2 - 1 downto 0);
tmp_65_fu_661_p2 <= std_logic_vector(unsigned(p_shl10_cast_fu_641_p3) + unsigned(p_shl11_cast_fu_653_p3));
tmp_66_cast_fu_673_p1 <= std_logic_vector(resize(signed(tmp_66_fu_667_p2),64));
tmp_66_fu_667_p2 <= std_logic_vector(unsigned(tmp_71_fu_633_p1) + unsigned(tmp_65_fu_661_p2));
tmp_67_fu_1019_p1 <= tmp_23_fu_1014_p2(4 - 1 downto 0);
tmp_68_fu_1031_p1 <= tmp_23_fu_1014_p2(6 - 1 downto 0);
tmp_69_fu_1043_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_1023_p3) + unsigned(p_shl3_cast_fu_1035_p3));
tmp_6_fu_683_p1 <= P_intIn_index3(14 - 1 downto 0);
tmp_70_fu_1049_p1 <= tmp_23_fu_1014_p2(2 - 1 downto 0);
tmp_71_fu_633_p1 <= P_index2(9 - 1 downto 0);
tmp_72_fu_637_p1 <= P_index1(4 - 1 downto 0);
tmp_73_fu_649_p1 <= P_index1(6 - 1 downto 0);
tmp_74_fu_585_p1 <= grp_fu_469_p2(4 - 1 downto 0);
tmp_75_fu_597_p1 <= grp_fu_469_p2(6 - 1 downto 0);
tmp_76_fu_609_p2 <= std_logic_vector(unsigned(p_shl12_cast_fu_589_p3) + unsigned(p_shl13_cast_fu_601_p3));
tmp_78_fu_1091_p1 <= j_reg_301(14 - 1 downto 0);
tmp_79_fu_1095_p2 <= std_logic_vector(unsigned(tmp_28_reg_1454) + unsigned(tmp_78_fu_1091_p1));
tmp_7_fu_687_p1 <= P_index2(14 - 1 downto 0);
tmp_80_fu_1333_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_81_fu_1220_p1 <= i_1_reg_347(14 - 1 downto 0);
tmp_82_cast_fu_1100_p1 <= std_logic_vector(resize(signed(tmp_79_fu_1095_p2),64));
tmp_82_fu_1224_p2 <= std_logic_vector(unsigned(tmp_56_reg_1474) + unsigned(tmp_81_fu_1220_p1));
tmp_83_fu_1339_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_84_cast_fu_1229_p1 <= std_logic_vector(resize(signed(tmp_82_fu_1224_p2),64));
tmp_84_fu_1305_p1 <= i_2_reg_381(9 - 1 downto 0);
tmp_85_fu_1309_p2 <= std_logic_vector(unsigned(tmp_58_reg_1479) + unsigned(tmp_84_fu_1305_p1));
tmp_86_cast_fu_779_p1 <= std_logic_vector(resize(signed(tmp_86_fu_774_p2),64));
tmp_86_fu_774_p2 <= std_logic_vector(unsigned(tmp_94_fu_770_p1) + unsigned(tmp_76_reg_1378));
tmp_87_cast_fu_793_p1 <= std_logic_vector(resize(signed(tmp_87_fu_788_p2),64));
tmp_87_fu_788_p2 <= std_logic_vector(unsigned(tmp_95_fu_784_p1) + unsigned(tmp_76_reg_1378));
tmp_88_cast_fu_1139_p1 <= std_logic_vector(resize(signed(tmp_88_fu_1134_p2),64));
tmp_88_fu_1134_p2 <= std_logic_vector(signed(tmp_80_reg_1513) + signed(tmp_99_fu_1130_p1));
tmp_89_cast_fu_1149_p1 <= std_logic_vector(resize(unsigned(tmp_89_fu_1144_p2),64));
tmp_89_fu_1144_p2 <= std_logic_vector(unsigned(tmp_38_reg_1464) + unsigned(tmp_98_fu_1126_p1));
tmp_8_fu_561_p2 <= "1" when (P_mode = ap_const_lv32_4) else "0";
tmp_90_cast_fu_1162_p1 <= std_logic_vector(resize(signed(tmp_90_fu_1157_p2),64));
tmp_90_fu_1157_p2 <= std_logic_vector(signed(tmp_80_reg_1513) + signed(tmp_100_fu_1154_p1));
tmp_91_cast_fu_1262_p1 <= std_logic_vector(resize(signed(tmp_91_fu_1257_p2),64));
tmp_91_fu_1257_p2 <= std_logic_vector(signed(tmp_83_reg_1581) + signed(tmp_102_fu_1253_p1));
tmp_92_cast_fu_1272_p1 <= std_logic_vector(resize(signed(tmp_92_fu_1267_p2),64));
tmp_92_fu_1267_p2 <= std_logic_vector(unsigned(tmp_69_reg_1489) + unsigned(tmp_101_fu_1249_p1));
tmp_93_cast_fu_1285_p1 <= std_logic_vector(resize(signed(tmp_93_fu_1280_p2),64));
tmp_93_fu_1280_p2 <= std_logic_vector(signed(tmp_83_reg_1581) + signed(tmp_103_fu_1277_p1));
tmp_94_cast_fu_1314_p1 <= std_logic_vector(resize(signed(tmp_85_fu_1309_p2),64));
tmp_94_fu_770_p1 <= max_2_reg_266(9 - 1 downto 0);
tmp_95_fu_784_p1 <= max_reg_277(9 - 1 downto 0);
tmp_96_fu_818_p1 <= ST_uOut_load_1_to_int_fu_804_p1(23 - 1 downto 0);
tmp_97_fu_835_p1 <= ST_uOut_load_2_to_int_fu_822_p1(23 - 1 downto 0);
tmp_98_fu_1126_p1 <= k_reg_324(9 - 1 downto 0);
tmp_99_fu_1130_p1 <= k_reg_324(14 - 1 downto 0);
tmp_9_fu_678_p1 <= std_logic_vector(resize(signed(P_index1),64));
tmp_s_fu_567_p2 <= "1" when (P_mode = ap_const_lv32_5) else "0";
end behav;
|
gpl-3.0
|
73f3858edb7bfbf96bf457d4ca55b35c
| 0.633967 | 3.198639 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SW_standalone/hdl/design_SW_standalone.vhd
| 1 | 61,867 |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Wed Aug 31 22:23:41 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SW_standalone.bd
--Design : design_SW_standalone
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_14CIMCM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_14CIMCM;
architecture STRUCTURE of s00_couplers_imp_14CIMCM is
component design_SW_standalone_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SW_standalone_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SW_standalone_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SW_standalone_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_SW_standalone_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_SW_standalone_processing_system7_0_axi_periph_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid <= s00_couplers_to_processing_system7_0_axi_periph_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid <= s00_couplers_to_processing_system7_0_axi_periph_AWVALID;
M00_AXI_bready <= s00_couplers_to_processing_system7_0_axi_periph_BREADY;
M00_AXI_rready <= s00_couplers_to_processing_system7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
processing_system7_0_axi_periph_ACLK_net <= M00_ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= M00_ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready;
s00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready;
s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid;
s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid;
s00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_14CIMCM
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => s00_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => s00_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => s00_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => s00_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SW_standalone is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_SW_standalone : entity is "design_SW_standalone,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_SW_standalone,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,da_axi4_cnt=1,da_board_cnt=1,da_ps7_cnt=3,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_SW_standalone : entity is "design_SW_standalone.hwdef";
end design_SW_standalone;
architecture STRUCTURE of design_SW_standalone is
component design_SW_standalone_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_SW_standalone_processing_system7_0_0;
component design_SW_standalone_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SW_standalone_axi_gpio_0_0;
component design_SW_standalone_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SW_standalone_rst_processing_system7_0_100M_0;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_gpio_0_GPIO_TRI_I(3 downto 0) <= leds_4bits_tri_i(3 downto 0);
leds_4bits_tri_o(3 downto 0) <= axi_gpio_0_GPIO_TRI_O(3 downto 0);
leds_4bits_tri_t(3 downto 0) <= axi_gpio_0_GPIO_TRI_T(3 downto 0);
axi_gpio_0: component design_SW_standalone_axi_gpio_0_0
port map (
gpio_io_i(3 downto 0) => axi_gpio_0_GPIO_TRI_I(3 downto 0),
gpio_io_o(3 downto 0) => axi_gpio_0_GPIO_TRI_O(3 downto 0),
gpio_io_t(3 downto 0) => axi_gpio_0_GPIO_TRI_T(3 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID
);
processing_system7_0: component design_SW_standalone_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_SW_standalone_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_SW_standalone_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
|
gpl-3.0
|
2bd7643ff3010d417e0743be5d3ae722
| 0.687087 | 2.830146 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_dexp_64ns_64ns_64_18_full_dsp.vhd
| 2 | 2,809 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 4;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
3bbffbb65c3de693c8e5be0d2779b4a6
| 0.482378 | 3.7107 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt
|
reg.vhd
| 1 | 614 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0) );
end reg;
architecture behav of reg is
begin
process ( clock, reset, load, I)
begin
if (reset = '1') then
Y <= "00000000000000000000000000000000";
elsif (clock'event and clock = '1') then
if (load = '1') then
Y <= I;
end if;
end if;
end process;
end behav;
|
mit
|
814ae30aab5a3b0a5738918af3f4ec76
| 0.570033 | 3.611765 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt
|
kr_fuzman_Vtminus.vhd
| 1 | 1,479 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Vtminus is
port
( clock : in std_logic;
Vtminusone : in std_logic_vector (31 downto 0);
Vref : in std_logic_vector (31 downto 0);
koft : in std_logic_vector (31 downto 0);
Vtminus : out std_logic_vector (31 downto 0)
);
end kr_fuzman_Vtminus;
architecture struct of kr_fuzman_Vtminus is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector (31 downto 0);
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => Vref, datab => Vtminusone, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => koft, datab => Z1, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Z2, datab => Vtminusone, result => Vtminus);
end struct;
|
mit
|
dfd42cfe57c36e8fd409c777add09425
| 0.638269 | 3.201299 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
obsolete/memory_interface.vhd
| 1 | 3,830 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:29:10 09/04/2016
-- Design Name:
-- Module Name: memory_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memory_interface is
generic (
ram_adr_width : natural;
ram_size : natural;
wbs_adr_high : natural := 27;
RamFileName : string := "meminit.ram";
mode : string := "B";
Swapbytes : boolean := true -- SWAP Bytes in RAM word in low byte first order to use data2mem
-- UseBRAMPrimitives : boolean := TRUE
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(wbs_adr_high downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
lli_re_i: in std_logic;
lli_adr_i: in std_logic_vector(29 downto 0);
lli_dat_o: out std_logic_vector(31 downto 0);
lli_busy_o: out std_logic
);
end memory_interface;
architecture Behavioral of memory_interface is
constant slave_adr_high : natural := 29;
-- Slaves
-- RAM
signal instr_ram_adr,data_ram_adr : std_logic_vector(ram_adr_width-1 downto 0);
signal ram_a_we: std_logic_vector(3 downto 0);
signal ack_read, ack_write : std_logic;
begin
instr_ram_adr <= lli_adr_i(ram_adr_width-1 downto 0);
data_ram_adr <= wbs_adr_i(ram_adr_width+1 downto 2);
lli_busy_o <= '0';
-- Wishbone ACK
process (clk_i) is
begin
if rising_edge(clk_i) then
ack_read<=wbs_cyc_i and wbs_stb_i and not wbs_we_i;
end if;
end process;
ack_write<=wbs_cyc_i and wbs_stb_i and wbs_we_i;
wbs_ack_o<=ack_read or ack_write;
-- RAM WREN Signals
gen_ram_a_we: for i in 3 downto 0 generate
ram_a_we(i)<='1' when wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' and wbs_sel_i(i)='1'
else '0';
end generate;
-- genericMainMemory: if not UseBRAMPrimitives generate
ram: entity work.MainMemory
generic map (
ADDR_WIDTH =>ram_adr_width,
SIZE => ram_size,
RamFileName => RamFileName,
mode => mode,
Swapbytes => Swapbytes
)
PORT MAP(
DBOut =>wbs_dat_o,
DBIn => wbs_dat_i,
AdrBus => data_ram_adr,
ENA => wbs_cyc_i,
WREN => ram_a_we,
CLK => clk_i,
CLKB =>clk_i ,
ENB =>lli_re_i ,
AdrBusB =>instr_ram_adr,
DBOutB => lli_dat_o
);
--end generate;
-- spartanMainMemory: if UseBRAMPrimitives generate
-- mem: entity work.MainMemorySpartan6
-- generic map (
-- NUMBANKS => 2
-- )
--
-- PORT MAP(
-- DBOut =>wbs_dat_o,
-- DBIn => wbs_dat_i,
-- AdrBus => data_ram_adr,
-- ENA => wbs_cyc_i,
-- WREN => ram_a_we,
-- CLK => clk_i,
-- CLKB =>clk_i ,
-- ENB =>lli_re_i ,
-- AdrBusB =>instr_ram_adr,
-- DBOutB => lli_dat_o
-- );
--
-- end generate;
--
end Behavioral;
|
gpl-3.0
|
e948861113811babe03b2d59a1444aa9
| 0.55248 | 3.281919 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward.vhd
| 3 | 192,142 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_config_TVALID : IN STD_LOGIC;
P_config_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
P_netOut_TVALID : OUT STD_LOGIC;
P_netOut_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=42,HLS_SYN_FF=8905,HLS_SYN_LUT=12500}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (153 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (153 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (153 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (153 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (153 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (153 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (153 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (153 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (153 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (153 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (153 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_7C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111100";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_96 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010110";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv37_0 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000000";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv38_23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100011";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv39_23 : STD_LOGIC_VECTOR (38 downto 0) := "000000000000000000000000000000000100011";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv37_23 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000100011";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (153 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_550 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_253 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal ap_sig_cseq_ST_st125_fsm_124 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal reg_557 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_285 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_294 : BOOLEAN;
signal grp_fu_498_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_563 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_304 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_311 : BOOLEAN;
signal grp_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_321 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_328 : BOOLEAN;
signal reg_574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_337 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_344 : BOOLEAN;
signal grp_fu_512_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_354 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_361 : BOOLEAN;
signal grp_fu_529_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_371 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_378 : BOOLEAN;
signal grp_fu_509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_388 : BOOLEAN;
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_395 : BOOLEAN;
signal P_mode_read_reg_1443 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_408 : BOOLEAN;
signal tmp_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_load_reg_1452 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1461 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_0_load_reg_1465 : STD_LOGIC_VECTOR (31 downto 0);
signal P_config_read_reg_1470 : STD_LOGIC_VECTOR (31 downto 0);
signal i_8_fu_627_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_432 : BOOLEAN;
signal tmp_7_fu_622_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_439 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_449 : BOOLEAN;
signal tmp_9_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_fu_672_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_52_reg_1496 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_31_fu_682_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_reg_1501 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_467 : BOOLEAN;
signal tmp_40_fu_686_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_40_reg_1506 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_651_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_24_reg_1511 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_478 : BOOLEAN;
signal tmp_27_fu_690_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_27_reg_1516 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_33_fu_694_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_reg_1521 : STD_LOGIC_VECTOR (8 downto 0);
signal j_5_fu_718_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_491 : BOOLEAN;
signal tmp_26_fu_724_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_reg_1534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_712_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_71_fu_775_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_71_reg_1540 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_2_reg_1546 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_781_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_fu_796_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_3_reg_1559 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_513 : BOOLEAN;
signal tmp_28_fu_791_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_519_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_37_reg_1579 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_533 : BOOLEAN;
signal grp_fu_524_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_reg_1584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_542 : BOOLEAN;
signal tmp_53_fu_863_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_reg_1589 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_551 : BOOLEAN;
signal tmp_58_fu_867_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_58_reg_1594 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_46_fu_871_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_reg_1599 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_562 : BOOLEAN;
signal tmp_51_fu_875_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_51_reg_1606 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_56_fu_879_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_56_reg_1611 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_fu_884_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_1616 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_575 : BOOLEAN;
signal i_12_fu_903_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1625 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_909_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_1630 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_75_fu_960_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_75_reg_1636 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_4_reg_1642 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_975_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_6_reg_1650 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_596 : BOOLEAN;
signal tmp_29_fu_970_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_615 : BOOLEAN;
signal i_11_fu_1031_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_11_reg_1678 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_624 : BOOLEAN;
signal p_uOut_addr_5_reg_1683 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_30_fu_1026_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_fu_1051_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_reg_1688 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_504_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_reg_1692 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_642 : BOOLEAN;
signal p_netOut_2_cast_fu_1056_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_cast_reg_1697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_651 : BOOLEAN;
signal tmp_50_fu_1060_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_TREADY : STD_LOGIC;
signal i_15_fu_1093_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_15_reg_1715 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_90_fu_1099_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_90_reg_1720 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1103_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal next_mul_reg_1725 : STD_LOGIC_VECTOR (36 downto 0);
signal i_14_fu_1118_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_14_reg_1733 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_91_fu_1124_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_91_reg_1738 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_49_fu_1113_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_reg_1743 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_fu_1205_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_65_reg_1749 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_701 : BOOLEAN;
signal p_netOut_1_fu_1211_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_710 : BOOLEAN;
signal j_7_fu_1236_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_7_reg_1762 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_719 : BOOLEAN;
signal tmp_55_fu_1230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_fu_1260_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1772 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_734 : BOOLEAN;
signal grp_fu_1269_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_8_reg_1781 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_cseq_ST_st151_fsm_150 : STD_LOGIC;
signal ap_sig_bdd_748 : BOOLEAN;
signal tmp_10_fu_1275_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_10_reg_1786 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_fu_1279_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_9_t_reg_1791 : STD_LOGIC_VECTOR (1 downto 0);
signal j_4_fu_1304_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_4_reg_1799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st152_fsm_151 : STD_LOGIC;
signal ap_sig_bdd_761 : BOOLEAN;
signal tmp_23_fu_1343_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_reg_1804 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_s_fu_1298_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1349_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_2_fu_1380_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st153_fsm_152 : STD_LOGIC;
signal ap_sig_bdd_779 : BOOLEAN;
signal tmp_17_fu_1374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_786 : BOOLEAN;
signal tmp_2_fu_1404_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_1822 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_796 : BOOLEAN;
signal ap_sig_bdd_801 : BOOLEAN;
signal i_7_fu_1409_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_275 : STD_LOGIC_VECTOR (30 downto 0);
signal i_3_reg_286 : STD_LOGIC_VECTOR (30 downto 0);
signal j_1_reg_298 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_832 : BOOLEAN;
signal sum_reg_309 : STD_LOGIC_VECTOR (31 downto 0);
signal k_1_reg_321 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_332 : STD_LOGIC_VECTOR (31 downto 0);
signal i_4_reg_344 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_355 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_367 : STD_LOGIC_VECTOR (30 downto 0);
signal i_5_reg_378 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_853 : BOOLEAN;
signal p_netOut_reg_389 : STD_LOGIC_VECTOR (31 downto 0);
signal p_netOut_2_reg_402 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_413 : STD_LOGIC_VECTOR (30 downto 0);
signal phi_mul_reg_424 : STD_LOGIC_VECTOR (36 downto 0);
signal j_3_reg_435 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_879 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_446 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_458 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_469 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_480 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_3_fu_633_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_746_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_825_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_838_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_931_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_994_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1017_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1046_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1074_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_94_cast_fu_1088_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_95_cast_fu_1251_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_1395_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_1415_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_997 : BOOLEAN;
signal grp_fu_491_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_1021 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_1028 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_1036 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_1043 : BOOLEAN;
signal grp_fu_509_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_512_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_fu_853_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_2_cast_fu_618_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_cast_fu_638_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_651_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_651_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_13_fu_657_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_11_fu_676_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_22_fu_699_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_cast_fu_737_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_68_fu_741_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_69_fu_751_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_763_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_755_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_767_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal k_1_cast_fu_787_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_806_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_fu_810_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_802_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_81_fu_820_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_82_fu_830_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_83_fu_833_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_34_to_int_fu_843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_neg_fu_847_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_858_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_666_p2 : STD_LOGIC_VECTOR (38 downto 0);
signal tmp_27_cast_fu_922_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_72_fu_926_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_73_fu_936_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_74_fu_948_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_940_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_952_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal j_2_cast_fu_966_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_985_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_86_fu_989_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_84_fu_981_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_999_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_88_fu_1009_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1012_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_5_cast_fu_1022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_1037_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_77_fu_1041_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_92_fu_1065_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_93_fu_1069_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_96_fu_1079_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_94_fu_1083_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_6_cast_fu_1109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_3_to_int_fu_1128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_uOut_load_4_to_int_fu_1146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_1132_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_fu_1142_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_1169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_1149_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_98_fu_1159_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_1187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_1175_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_1193_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_63_fu_1199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_64_fu_515_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_66_fu_1217_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_1242_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_95_fu_1246_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_1_cast_fu_1256_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1269_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_1269_p1 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_1285_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_cast_fu_1310_p1 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_12_fu_1314_p2 : STD_LOGIC_VECTOR (37 downto 0);
signal tmp_14_fu_1319_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1331_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl_cast_fu_1323_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_1335_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_fu_1355_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_1368_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_1386_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_67_fu_1390_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal i_cast_fu_1400_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_491_ce : STD_LOGIC;
signal grp_fu_498_ce : STD_LOGIC;
signal grp_fu_504_ce : STD_LOGIC;
signal tmp_64_fu_515_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_519_ce : STD_LOGIC;
signal grp_fu_524_ce : STD_LOGIC;
signal grp_fu_529_ce : STD_LOGIC;
signal grp_fu_651_ce : STD_LOGIC;
signal grp_fu_666_ce : STD_LOGIC;
signal grp_fu_1269_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (153 downto 0);
signal grp_fu_1269_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal grp_fu_651_p10 : STD_LOGIC_VECTOR (37 downto 0);
signal ap_sig_bdd_976 : BOOLEAN;
component feedforward_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mul_7ns_31ns_38_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (30 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (37 downto 0) );
end component;
component feedforward_mul_7ns_32s_39_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (38 downto 0) );
end component;
component feedforward_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode => P_mode);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 32,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_fadd_32ns_32ns_32_5_full_dsp_U0 : component feedforward_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_491_p0,
din1 => grp_fu_491_p1,
ce => grp_fu_491_ce,
dout => grp_fu_491_p2);
feedforward_fmul_32ns_32ns_32_4_max_dsp_U1 : component feedforward_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => p_uOut_q0,
din1 => ST_WandB_q0,
ce => grp_fu_498_ce,
dout => grp_fu_498_p2);
feedforward_fdiv_32ns_32ns_32_16_U2 : component feedforward_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_550,
din1 => sumsoft_reg_332,
ce => grp_fu_504_ce,
dout => grp_fu_504_p2);
feedforward_fptrunc_64ns_32_1_U3 : component feedforward_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_509_p0,
dout => grp_fu_509_p1);
feedforward_fpext_32ns_64_1_U4 : component feedforward_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_512_p0,
dout => grp_fu_512_p1);
feedforward_fcmp_32ns_32ns_1_1_U5 : component feedforward_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_550,
din1 => p_uOut_load_4_reg_1743,
opcode => tmp_64_fu_515_opcode,
dout => tmp_64_fu_515_p2);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U6 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_584,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_519_ce,
dout => grp_fu_519_p2);
feedforward_ddiv_64ns_64ns_64_31_U7 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_37_reg_1579,
ce => grp_fu_524_ce,
dout => grp_fu_524_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U8 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_579,
ce => grp_fu_529_ce,
dout => grp_fu_529_p2);
feedforward_mul_7ns_31ns_38_3_U9 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_651_p0,
din1 => grp_fu_651_p1,
ce => grp_fu_651_ce,
dout => grp_fu_651_p2);
feedforward_mul_7ns_32s_39_3_U10 : component feedforward_mul_7ns_32s_39_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 32,
dout_WIDTH => 39)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_666_p0,
din1 => tmp_13_fu_657_p2,
ce => grp_fu_666_ce,
dout => grp_fu_666_p2);
feedforward_mux_4to1_sel2_32_1_U11 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_27_reg_1516,
dout => tmp_22_fu_699_p6);
feedforward_mux_4to1_sel2_32_1_U12 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_40_reg_1506,
dout => tmp_26_fu_724_p6);
feedforward_mux_4to1_sel2_32_1_U13 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_52_reg_1496,
dout => tmp_25_fu_884_p6);
feedforward_mux_4to1_sel2_32_1_U14 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_58_reg_1594,
dout => tmp_54_fu_909_p6);
feedforward_mux_4to1_sel2_32_1_U15 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_91_reg_1738,
dout => tmp_66_fu_1217_p6);
feedforward_mul_7ns_31ns_38_3_U16 : component feedforward_mul_7ns_31ns_38_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 7,
din1_WIDTH => 31,
dout_WIDTH => 38)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1269_p0,
din1 => grp_fu_1269_p1,
ce => grp_fu_1269_ce,
dout => grp_fu_1269_p2);
feedforward_mux_4to1_sel2_32_1_U17 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_10_reg_1786,
dout => tmp_5_fu_1285_p6);
feedforward_mux_4to1_sel2_32_1_U18 : component feedforward_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_9_t_reg_1791,
dout => tmp_21_fu_1355_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_TREADY assign process. --
ap_reg_ioackin_P_netOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_976) then
if (not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_TREADY)) then
ap_reg_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_446 assign process. --
i_1_reg_446_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
i_1_reg_446 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and (ap_const_lv1_0 = tmp_s_fu_1298_p2))) then
i_1_reg_446 <= i_9_fu_1349_p2;
end if;
end if;
end process;
-- i_2_reg_275 assign process. --
i_2_reg_275_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
i_2_reg_275 <= ap_const_lv31_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
i_2_reg_275 <= i_8_fu_627_p2;
end if;
end if;
end process;
-- i_3_reg_286 assign process. --
i_3_reg_286_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
i_3_reg_286 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_18_fu_712_p2))) then
i_3_reg_286 <= i_10_fu_781_p2;
end if;
end if;
end process;
-- i_4_reg_344 assign process. --
i_4_reg_344_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
i_4_reg_344 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
i_4_reg_344 <= i_12_reg_1625;
end if;
end if;
end process;
-- i_5_reg_378 assign process. --
i_5_reg_378_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_20_fu_897_p2))) then
i_5_reg_378 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
i_5_reg_378 <= i_11_reg_1678;
end if;
end if;
end process;
-- i_6_reg_413 assign process. --
i_6_reg_413_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
i_6_reg_413 <= i_14_reg_1733;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
i_6_reg_413 <= ap_const_lv31_0;
end if;
end if;
end process;
-- i_reg_480 assign process. --
i_reg_480_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
i_reg_480 <= i_7_fu_1409_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
i_reg_480 <= ap_const_lv31_0;
end if;
end if;
end process;
-- j_1_reg_298 assign process. --
j_1_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
j_1_reg_298 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
j_1_reg_298 <= j_5_reg_1529;
end if;
end if;
end process;
-- j_2_reg_367 assign process. --
j_2_reg_367_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
j_2_reg_367 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
j_2_reg_367 <= j_6_reg_1650;
end if;
end if;
end process;
-- j_3_reg_435 assign process. --
j_3_reg_435_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
j_3_reg_435 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_435 <= j_7_reg_1762;
end if;
end if;
end process;
-- j_reg_458 assign process. --
j_reg_458_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and (ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
j_reg_458 <= j_4_reg_1799;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
j_reg_458 <= ap_const_lv32_0;
end if;
end if;
end process;
-- k_1_reg_321 assign process. --
k_1_reg_321_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
k_1_reg_321 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
k_1_reg_321 <= k_3_reg_1559;
end if;
end if;
end process;
-- k_reg_469 assign process. --
k_reg_469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
k_reg_469 <= ap_const_lv32_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
k_reg_469 <= k_2_fu_1380_p2;
end if;
end if;
end process;
-- p_netOut_2_reg_402 assign process. --
p_netOut_2_reg_402_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_2_reg_402 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_2_reg_402 <= i_15_reg_1715;
end if;
end if;
end process;
-- p_netOut_reg_389 assign process. --
p_netOut_reg_389_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and (ap_const_lv1_0 = tmp_48_fu_1051_p2))) then
p_netOut_reg_389 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
p_netOut_reg_389 <= p_netOut_1_fu_1211_p3;
end if;
end if;
end process;
-- phi_mul_reg_424 assign process. --
phi_mul_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) and (ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
phi_mul_reg_424 <= next_mul_reg_1725;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2) and not((ap_const_lv1_0 = tmp_48_fu_1051_p2)))) then
phi_mul_reg_424 <= ap_const_lv37_0;
end if;
end if;
end process;
-- sum_1_reg_355 assign process. --
sum_1_reg_355_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
sum_1_reg_355 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
sum_1_reg_355 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sum_reg_309 assign process. --
sum_reg_309_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
sum_reg_309 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then
sum_reg_309 <= grp_fu_491_p2;
end if;
end if;
end process;
-- sumsoft_reg_332 assign process. --
sumsoft_reg_332_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
sumsoft_reg_332 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
sumsoft_reg_332 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
P_config_read_reg_1470 <= P_config_TDATA;
ST_numLayer <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_408))) then
P_mode_read_reg_1443 <= P_mode;
ST_numLayer_load_reg_1452 <= ST_numLayer;
tmp_reg_1448 <= tmp_fu_596_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ST_layerSize_0_load_reg_1465 <= ST_layerSize_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and (tmp_4_fu_1415_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801) and not((tmp_4_fu_1415_p1 = ap_const_lv2_2)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_1)) and not((tmp_4_fu_1415_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_config_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
i_11_reg_1678 <= i_11_fu_1031_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
i_12_reg_1625 <= i_12_fu_903_p2;
tmp_25_reg_1616 <= tmp_25_fu_884_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)))) then
i_14_reg_1733 <= i_14_fu_1118_p2;
next_mul_reg_1725 <= next_mul_fu_1103_p2;
tmp_90_reg_1720 <= tmp_90_fu_1099_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
i_15_reg_1715 <= i_15_fu_1093_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) then
j_4_reg_1799 <= j_4_fu_1304_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
j_5_reg_1529 <= j_5_fu_718_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
j_6_reg_1650 <= j_6_fu_975_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
j_7_reg_1762 <= j_7_fu_1236_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
k_3_reg_1559 <= k_3_fu_796_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))))) then
p_netOut_2_cast_reg_1697(30 downto 0) <= p_netOut_2_cast_fu_1056_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_18_fu_712_p2)))) then
p_uOut_addr_2_reg_1546 <= tmp_77_cast_fu_746_p1(8 - 1 downto 0);
tmp_26_reg_1534 <= tmp_26_fu_724_p6;
tmp_71_reg_1540(13 downto 2) <= tmp_71_fu_775_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_20_fu_897_p2)))) then
p_uOut_addr_4_reg_1642 <= tmp_81_cast_fu_931_p1(8 - 1 downto 0);
tmp_54_reg_1630 <= tmp_54_fu_909_p6;
tmp_75_reg_1636(13 downto 2) <= tmp_75_fu_960_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and not((ap_const_lv1_0 = tmp_30_fu_1026_p2)))) then
p_uOut_addr_5_reg_1683 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) then
p_uOut_load_4_reg_1743 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124) or (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143))) then
reg_550 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
reg_557 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
reg_563 <= grp_fu_498_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_574 <= grp_fu_491_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
reg_579 <= grp_fu_512_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
reg_584 <= grp_fu_529_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
reg_590 <= grp_fu_509_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) then
tmp_10_reg_1786 <= tmp_10_fu_1275_p1;
tmp_8_reg_1781 <= grp_fu_1269_p2;
tmp_9_t_reg_1791 <= tmp_9_t_fu_1279_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408))) then
tmp_1_reg_1461 <= tmp_1_fu_606_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151) and not((ap_const_lv1_0 = tmp_s_fu_1298_p2)))) then
tmp_23_reg_1804(13 downto 2) <= tmp_23_fu_1343_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_24_reg_1511 <= grp_fu_651_p2;
tmp_27_reg_1516 <= tmp_27_fu_690_p1;
tmp_33_reg_1521 <= tmp_33_fu_694_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not(ap_sig_bdd_801))) then
tmp_2_reg_1822 <= tmp_2_fu_1404_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_31_reg_1501 <= tmp_31_fu_682_p1;
tmp_40_reg_1506 <= tmp_40_fu_686_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) then
tmp_37_reg_1579 <= grp_fu_519_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) then
tmp_38_reg_1584 <= grp_fu_524_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
tmp_46_reg_1599 <= tmp_46_fu_871_p1;
tmp_51_reg_1606 <= tmp_51_fu_875_p1;
tmp_56_reg_1611 <= tmp_56_fu_879_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
tmp_47_reg_1692 <= grp_fu_504_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) and (ap_const_lv1_0 = tmp_30_fu_1026_p2))) then
tmp_48_reg_1688 <= tmp_48_fu_1051_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_9_fu_642_p2))) then
tmp_52_reg_1496 <= tmp_52_fu_672_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
tmp_53_reg_1589 <= tmp_53_fu_863_p1;
tmp_58_reg_1594 <= tmp_58_fu_867_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) then
tmp_65_reg_1749 <= tmp_65_fu_1205_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) then
tmp_6_reg_1772 <= tmp_6_fu_1260_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
tmp_91_reg_1738 <= tmp_91_fu_1124_p1;
end if;
end if;
end process;
tmp_71_reg_1540(1 downto 0) <= "00";
tmp_75_reg_1636(1 downto 0) <= "00";
p_netOut_2_cast_reg_1697(31) <= '0';
tmp_23_reg_1804(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_596_p2, ap_sig_bdd_408, tmp_reg_1448, tmp_1_fu_606_p2, tmp_1_reg_1461, tmp_7_fu_622_p2, ap_sig_bdd_439, tmp_9_fu_642_p2, tmp_18_fu_712_p2, tmp_28_fu_791_p2, tmp_20_fu_897_p2, tmp_29_fu_970_p2, tmp_30_fu_1026_p2, tmp_48_reg_1688, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_55_fu_1230_p2, tmp_6_fu_1260_p2, tmp_6_reg_1772, tmp_s_fu_1298_p2, tmp_17_fu_1374_p2, ap_sig_bdd_786, tmp_2_fu_1404_p2, tmp_2_reg_1822, ap_sig_bdd_801, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and (ap_const_lv1_0 = tmp_1_fu_606_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_596_p2 = ap_const_lv1_0) and not(ap_sig_bdd_408) and not((ap_const_lv1_0 = tmp_1_fu_606_p2)))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((ap_const_lv1_0 = tmp_7_fu_622_p2) and not(ap_sig_bdd_439))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_9_fu_642_p2)) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = tmp_18_fu_712_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_28_fu_791_p2)) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
if (not((ap_const_lv1_0 = tmp_20_fu_897_p2))) then
ap_NS_fsm <= ap_ST_st83_fsm_82;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st83_fsm_82 =>
if ((ap_const_lv1_0 = tmp_29_fu_970_p2)) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st84_fsm_83;
end if;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st124_fsm_123 =>
if ((ap_const_lv1_0 = tmp_30_fu_1026_p2)) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st125_fsm_124;
end if;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st143_fsm_142 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and not((ap_const_lv1_0 = tmp_49_fu_1113_p2)))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
elsif (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and not((ap_const_lv1_0 = tmp_50_fu_1060_p2)))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st147_fsm_146 =>
if (not((ap_const_lv1_0 = tmp_55_fu_1230_p2))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st148_fsm_147 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (not((ap_const_lv1_0 = tmp_6_fu_1260_p2))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st151_fsm_150;
when ap_ST_st151_fsm_150 =>
ap_NS_fsm <= ap_ST_st152_fsm_151;
when ap_ST_st152_fsm_151 =>
if ((ap_const_lv1_0 = tmp_s_fu_1298_p2)) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st153_fsm_152 =>
if ((not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st153_fsm_152;
elsif (((ap_const_lv1_0 = tmp_17_fu_1374_p2) and not(ap_sig_bdd_786))) then
ap_NS_fsm <= ap_ST_st152_fsm_151;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st154_fsm_153 =>
if ((not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
elsif (((ap_const_lv1_0 = tmp_2_fu_1404_p2) and not(ap_sig_bdd_801))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st154_fsm_153;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_TREADY assign process. --
P_config_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_596_p2, ap_sig_bdd_408, tmp_2_fu_1404_p2, ap_sig_cseq_ST_st154_fsm_153, ap_sig_bdd_801)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_596_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_408)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)) and not(ap_sig_bdd_801)))) then
P_config_TREADY <= ap_const_logic_1;
else
P_config_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_TDATA <= p_netOut_reg_389;
-- P_netOut_TVALID assign process. --
P_netOut_TVALID_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_reg_ioackin_P_netOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY))) then
P_netOut_TVALID <= ap_const_logic_1;
else
P_netOut_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st148_fsm_147, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, tmp_85_cast_fu_815_p1, tmp_87_cast_fu_838_p1, tmp_88_cast_fu_994_p1, tmp_90_cast_fu_1017_p1, tmp_76_cast_fu_1395_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) then
ST_WandB_address0 <= tmp_76_cast_fu_1395_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2))) then
ST_WandB_address0 <= tmp_90_cast_fu_1017_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_994_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2))) then
ST_WandB_address0 <= tmp_87_cast_fu_838_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2)))) then
ST_WandB_address0 <= tmp_85_cast_fu_815_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6, tmp_28_fu_791_p2, ap_sig_cseq_ST_st83_fsm_82, tmp_29_fu_970_p2, ap_sig_cseq_ST_st153_fsm_152, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_28_fu_791_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_28_fu_791_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and not((ap_const_lv1_0 = tmp_29_fu_970_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) and (ap_const_lv1_0 = tmp_29_fu_970_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not(ap_sig_bdd_786)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st153_fsm_152, tmp_17_fu_1374_p2, ap_sig_bdd_786)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)) and not(ap_sig_bdd_786)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, tmp_49_fu_1113_p2, tmp_6_reg_1772, tmp_2_reg_1822)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2)) or (not((ap_const_lv1_0 = tmp_reg_1448)) and (ap_const_lv1_0 = tmp_2_reg_1822)) or ((ap_const_lv1_0 = tmp_reg_1448) and not((ap_const_lv1_0 = tmp_1_reg_1461)) and (ap_const_lv1_0 = tmp_6_reg_1772)) or ((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and not((ap_const_lv1_0 = tmp_48_reg_1688)) and (ap_const_lv1_0 = tmp_49_fu_1113_p2))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1021 assign process. --
ap_sig_bdd_1021_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1021 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_1028 assign process. --
ap_sig_bdd_1028_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1028 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_1036 assign process. --
ap_sig_bdd_1036_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1036 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_1043 assign process. --
ap_sig_bdd_1043_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1043 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_172 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_253 assign process. --
ap_sig_bdd_253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_253 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(124 downto 124));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_285 assign process. --
ap_sig_bdd_285_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_285 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_294 assign process. --
ap_sig_bdd_294_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_294 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_304 assign process. --
ap_sig_bdd_304_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_304 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_311 assign process. --
ap_sig_bdd_311_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_311 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_321 assign process. --
ap_sig_bdd_321_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_321 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_328 assign process. --
ap_sig_bdd_328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_328 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_337 assign process. --
ap_sig_bdd_337_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_337 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_344 assign process. --
ap_sig_bdd_344_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_344 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_354 assign process. --
ap_sig_bdd_354_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_354 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_361 assign process. --
ap_sig_bdd_361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_361 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_371 assign process. --
ap_sig_bdd_371_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_371 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_378 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_388 assign process. --
ap_sig_bdd_388_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_388 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_395 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_408 assign process. --
ap_sig_bdd_408_assign_proc : process(ap_start, P_config_TVALID, tmp_fu_596_p2)
begin
ap_sig_bdd_408 <= (((P_config_TVALID = ap_const_logic_0) and not((tmp_fu_596_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_432 assign process. --
ap_sig_bdd_432_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_432 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_439 assign process. --
ap_sig_bdd_439_assign_proc : process(P_netIn_TVALID, tmp_7_fu_622_p2)
begin
ap_sig_bdd_439 <= ((P_netIn_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)));
end process;
-- ap_sig_bdd_449 assign process. --
ap_sig_bdd_449_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_449 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_467 assign process. --
ap_sig_bdd_467_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_467 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_478 assign process. --
ap_sig_bdd_478_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_478 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_491 assign process. --
ap_sig_bdd_491_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_491 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_513 assign process. --
ap_sig_bdd_513_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_513 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_533 assign process. --
ap_sig_bdd_533_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_533 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_542 assign process. --
ap_sig_bdd_542_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_542 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_551 assign process. --
ap_sig_bdd_551_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_551 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_562 assign process. --
ap_sig_bdd_562_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_562 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_575 assign process. --
ap_sig_bdd_575_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_575 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_596 assign process. --
ap_sig_bdd_596_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_596 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_615 assign process. --
ap_sig_bdd_615_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_615 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_624 assign process. --
ap_sig_bdd_624_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_624 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_642 assign process. --
ap_sig_bdd_642_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_642 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_651 assign process. --
ap_sig_bdd_651_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_651 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_701 assign process. --
ap_sig_bdd_701_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_701 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_710 assign process. --
ap_sig_bdd_710_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_710 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_719 assign process. --
ap_sig_bdd_719_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_719 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_734 assign process. --
ap_sig_bdd_734_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_734 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_748 assign process. --
ap_sig_bdd_748_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_748 <= (ap_const_lv1_1 = ap_CS_fsm(150 downto 150));
end process;
-- ap_sig_bdd_761 assign process. --
ap_sig_bdd_761_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_761 <= (ap_const_lv1_1 = ap_CS_fsm(151 downto 151));
end process;
-- ap_sig_bdd_779 assign process. --
ap_sig_bdd_779_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_779 <= (ap_const_lv1_1 = ap_CS_fsm(152 downto 152));
end process;
-- ap_sig_bdd_786 assign process. --
ap_sig_bdd_786_assign_proc : process(P_WandB_TVALID, tmp_17_fu_1374_p2)
begin
ap_sig_bdd_786 <= ((P_WandB_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_17_fu_1374_p2)));
end process;
-- ap_sig_bdd_796 assign process. --
ap_sig_bdd_796_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_796 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_801 assign process. --
ap_sig_bdd_801_assign_proc : process(P_config_TVALID, tmp_2_fu_1404_p2)
begin
ap_sig_bdd_801 <= ((P_config_TVALID = ap_const_logic_0) and not((ap_const_lv1_0 = tmp_2_fu_1404_p2)));
end process;
-- ap_sig_bdd_832 assign process. --
ap_sig_bdd_832_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_832 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_853 assign process. --
ap_sig_bdd_853_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_853 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_879 assign process. --
ap_sig_bdd_879_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_879 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_976 assign process. --
ap_sig_bdd_976_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2)
begin
ap_sig_bdd_976 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and (ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2));
end process;
-- ap_sig_bdd_997 assign process. --
ap_sig_bdd_997_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_997 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_378)
begin
if (ap_sig_bdd_378) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_395)
begin
if (ap_sig_bdd_395) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_997)
begin
if (ap_sig_bdd_997) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_304)
begin
if (ap_sig_bdd_304) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_615)
begin
if (ap_sig_bdd_615) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_624)
begin
if (ap_sig_bdd_624) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st125_fsm_124 assign process. --
ap_sig_cseq_ST_st125_fsm_124_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_1021)
begin
if (ap_sig_bdd_1021) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_642)
begin
if (ap_sig_bdd_642) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_853)
begin
if (ap_sig_bdd_853) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_651)
begin
if (ap_sig_bdd_651) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_701)
begin
if (ap_sig_bdd_701) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_710)
begin
if (ap_sig_bdd_710) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_719)
begin
if (ap_sig_bdd_719) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_879)
begin
if (ap_sig_bdd_879) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st151_fsm_150 assign process. --
ap_sig_cseq_ST_st151_fsm_150_assign_proc : process(ap_sig_bdd_748)
begin
if (ap_sig_bdd_748) then
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st152_fsm_151 assign process. --
ap_sig_cseq_ST_st152_fsm_151_assign_proc : process(ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) then
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st153_fsm_152 assign process. --
ap_sig_cseq_ST_st153_fsm_152_assign_proc : process(ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) then
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_796)
begin
if (ap_sig_bdd_796) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_321)
begin
if (ap_sig_bdd_321) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_285)
begin
if (ap_sig_bdd_285) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_1028)
begin
if (ap_sig_bdd_1028) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_172)
begin
if (ap_sig_bdd_172) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_337)
begin
if (ap_sig_bdd_337) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_354)
begin
if (ap_sig_bdd_354) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_432)
begin
if (ap_sig_bdd_432) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_449)
begin
if (ap_sig_bdd_449) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_371)
begin
if (ap_sig_bdd_371) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_533)
begin
if (ap_sig_bdd_533) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_467)
begin
if (ap_sig_bdd_467) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_478)
begin
if (ap_sig_bdd_478) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_542)
begin
if (ap_sig_bdd_542) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_388)
begin
if (ap_sig_bdd_388) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_832)
begin
if (ap_sig_bdd_832) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_513)
begin
if (ap_sig_bdd_513) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_551)
begin
if (ap_sig_bdd_551) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_562)
begin
if (ap_sig_bdd_562) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_575)
begin
if (ap_sig_bdd_575) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_596)
begin
if (ap_sig_bdd_596) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_311)
begin
if (ap_sig_bdd_311) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_1036)
begin
if (ap_sig_bdd_1036) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_328)
begin
if (ap_sig_bdd_328) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_294)
begin
if (ap_sig_bdd_294) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_1043)
begin
if (ap_sig_bdd_1043) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_344)
begin
if (ap_sig_bdd_344) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_361)
begin
if (ap_sig_bdd_361) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_TREADY assign process. --
ap_sig_ioackin_P_netOut_TREADY_assign_proc : process(P_netOut_TREADY, ap_reg_ioackin_P_netOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_TREADY)) then
ap_sig_ioackin_P_netOut_TREADY <= P_netOut_TREADY;
else
ap_sig_ioackin_P_netOut_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_1269_ce <= ap_const_logic_1;
grp_fu_1269_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_1269_p1 <= grp_fu_1269_p10(31 - 1 downto 0);
grp_fu_1269_p10 <= std_logic_vector(resize(unsigned(i_1_reg_446),38));
grp_fu_491_ce <= ap_const_logic_1;
-- grp_fu_491_p0 assign process. --
grp_fu_491_p0_assign_proc : process(sum_reg_309, sumsoft_reg_332, sum_1_reg_355, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p0 <= sumsoft_reg_332;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p0 <= sum_1_reg_355;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
grp_fu_491_p0 <= sum_reg_309;
else
grp_fu_491_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_491_p1 assign process. --
grp_fu_491_p1_assign_proc : process(reg_557, reg_563, reg_590, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
grp_fu_491_p1 <= reg_590;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_491_p1 <= reg_557;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
grp_fu_491_p1 <= reg_563;
else
grp_fu_491_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_498_ce <= ap_const_logic_1;
grp_fu_504_ce <= ap_const_logic_1;
-- grp_fu_509_p0 assign process. --
grp_fu_509_p0_assign_proc : process(reg_584, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st118_fsm_117, tmp_38_reg_1584)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_509_p0 <= reg_584;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
grp_fu_509_p0 <= tmp_38_reg_1584;
else
grp_fu_509_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_512_p0 assign process. --
grp_fu_512_p0_assign_proc : process(reg_574, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st99_fsm_98, tmp_34_fu_853_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) then
grp_fu_512_p0 <= reg_574;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
grp_fu_512_p0 <= tmp_34_fu_853_p1;
else
grp_fu_512_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_519_ce <= ap_const_logic_1;
grp_fu_524_ce <= ap_const_logic_1;
grp_fu_529_ce <= ap_const_logic_1;
grp_fu_651_ce <= ap_const_logic_1;
grp_fu_651_p0 <= ap_const_lv38_23(7 - 1 downto 0);
grp_fu_651_p1 <= grp_fu_651_p10(31 - 1 downto 0);
grp_fu_651_p10 <= std_logic_vector(resize(unsigned(i_3_reg_286),38));
grp_fu_666_ce <= ap_const_logic_1;
grp_fu_666_p0 <= ap_const_lv39_23(7 - 1 downto 0);
i_10_fu_781_p2 <= std_logic_vector(unsigned(i_3_reg_286) + unsigned(ap_const_lv31_1));
i_11_fu_1031_p2 <= std_logic_vector(unsigned(i_5_reg_378) + unsigned(ap_const_lv31_1));
i_12_fu_903_p2 <= std_logic_vector(unsigned(i_4_reg_344) + unsigned(ap_const_lv32_1));
i_14_fu_1118_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(i_6_reg_413));
i_15_fu_1093_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(p_netOut_2_reg_402));
i_1_cast_fu_1256_p1 <= std_logic_vector(resize(unsigned(i_1_reg_446),32));
i_2_cast_fu_618_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),32));
i_3_cast_fu_638_p1 <= std_logic_vector(resize(unsigned(i_3_reg_286),32));
i_5_cast_fu_1022_p1 <= std_logic_vector(resize(unsigned(i_5_reg_378),32));
i_6_cast_fu_1109_p1 <= std_logic_vector(resize(unsigned(i_6_reg_413),32));
i_7_fu_1409_p2 <= std_logic_vector(unsigned(i_reg_480) + unsigned(ap_const_lv31_1));
i_8_fu_627_p2 <= std_logic_vector(unsigned(i_2_reg_275) + unsigned(ap_const_lv31_1));
i_9_fu_1349_p2 <= std_logic_vector(unsigned(i_1_reg_446) + unsigned(ap_const_lv31_1));
i_cast_fu_1400_p1 <= std_logic_vector(resize(unsigned(i_reg_480),32));
j_2_cast_fu_966_p1 <= std_logic_vector(resize(unsigned(j_2_reg_367),32));
j_4_fu_1304_p2 <= std_logic_vector(unsigned(j_reg_458) + unsigned(ap_const_lv32_1));
j_5_fu_718_p2 <= std_logic_vector(unsigned(j_1_reg_298) + unsigned(ap_const_lv32_1));
j_6_fu_975_p2 <= std_logic_vector(unsigned(j_2_reg_367) + unsigned(ap_const_lv31_1));
j_7_fu_1236_p2 <= std_logic_vector(unsigned(j_3_reg_435) + unsigned(ap_const_lv32_1));
k_1_cast_fu_787_p1 <= std_logic_vector(resize(unsigned(k_1_reg_321),32));
k_2_fu_1380_p2 <= std_logic_vector(unsigned(k_reg_469) + unsigned(ap_const_lv32_1));
k_3_fu_796_p2 <= std_logic_vector(unsigned(k_1_reg_321) + unsigned(ap_const_lv31_1));
next_mul_fu_1103_p2 <= std_logic_vector(unsigned(ap_const_lv37_23) + unsigned(phi_mul_reg_424));
notlhs1_fu_1181_p2 <= "0" when (tmp_59_fu_1149_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_1163_p2 <= "0" when (tmp_57_fu_1132_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_1187_p2 <= "1" when (tmp_98_fu_1159_p1 = ap_const_lv23_0) else "0";
notrhs_fu_1169_p2 <= "1" when (tmp_97_fu_1142_p1 = ap_const_lv23_0) else "0";
p_netOut_1_fu_1211_p3 <=
p_netOut_2_cast_reg_1697 when (tmp_65_reg_1749(0) = '1') else
p_netOut_reg_389;
p_netOut_2_cast_fu_1056_p1 <= std_logic_vector(resize(unsigned(p_netOut_2_reg_402),32));
p_shl1_cast_fu_1335_p3 <= (tmp_19_fu_1331_p1 & ap_const_lv2_0);
p_shl2_cast_fu_755_p3 <= (tmp_69_fu_751_p1 & ap_const_lv5_0);
p_shl3_cast_fu_767_p3 <= (tmp_70_fu_763_p1 & ap_const_lv2_0);
p_shl4_cast_fu_940_p3 <= (tmp_73_fu_936_p1 & ap_const_lv5_0);
p_shl5_cast_fu_952_p3 <= (tmp_74_fu_948_p1 & ap_const_lv2_0);
p_shl_cast_fu_1323_p3 <= (tmp_14_fu_1319_p1 & ap_const_lv5_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_2_reg_1546, ap_sig_cseq_ST_st7_fsm_6, p_uOut_addr_4_reg_1642, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, p_uOut_addr_5_reg_1683, ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, tmp_3_fu_633_p1, tmp_86_cast_fu_825_p1, tmp_89_cast_fu_1004_p1, tmp_91_cast_fu_1046_p1, tmp_93_cast_fu_1074_p1, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1683;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) then
p_uOut_address0 <= p_uOut_addr_4_reg_1642;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
p_uOut_address0 <= p_uOut_addr_2_reg_1546;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_3_fu_633_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address0 <= tmp_93_cast_fu_1074_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
p_uOut_address0 <= tmp_91_cast_fu_1046_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
p_uOut_address0 <= tmp_89_cast_fu_1004_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
p_uOut_address0 <= tmp_86_cast_fu_825_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st147_fsm_146, tmp_94_cast_fu_1088_p1, tmp_95_cast_fu_1251_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
p_uOut_address1 <= tmp_95_cast_fu_1251_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
p_uOut_address1 <= tmp_94_cast_fu_1088_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_439, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st124_fsm_123, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123) or ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1448, tmp_1_reg_1461, tmp_48_reg_1688, ap_sig_cseq_ST_st143_fsm_142, tmp_50_fu_1060_p2, ap_sig_ioackin_P_netOut_TREADY, ap_sig_cseq_ST_st147_fsm_146)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142) and not(((ap_const_lv1_0 = tmp_reg_1448) and (ap_const_lv1_0 = tmp_1_reg_1461) and (ap_const_lv1_0 = tmp_48_reg_1688) and (ap_const_lv1_0 = tmp_50_fu_1060_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_590, ap_sig_cseq_ST_st2_fsm_1, tmp_47_reg_1692, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
p_uOut_d0 <= tmp_47_reg_1692;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_d0 <= reg_590;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1128_p1 <= reg_550;
p_uOut_load_4_to_int_fu_1146_p1 <= p_uOut_load_4_reg_1743;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_7_fu_622_p2, ap_sig_bdd_439, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st119_fsm_118)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_7_fu_622_p2)) and not(ap_sig_bdd_439)) or (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_1275_p1 <= i_1_reg_446(2 - 1 downto 0);
tmp_11_fu_676_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_3_reg_286));
tmp_12_fu_1314_p2 <= std_logic_vector(signed(tmp_4_cast_fu_1310_p1) + signed(tmp_8_reg_1781));
tmp_13_fu_657_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(ST_numLayer_load_reg_1452));
tmp_14_fu_1319_p1 <= tmp_12_fu_1314_p2(9 - 1 downto 0);
tmp_15_fu_858_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1452));
tmp_16_fu_1368_p2 <= std_logic_vector(unsigned(tmp_21_fu_1355_p6) + unsigned(ap_const_lv32_1));
tmp_17_fu_1374_p2 <= "1" when (signed(k_reg_469) < signed(tmp_16_fu_1368_p2)) else "0";
tmp_18_fu_712_p2 <= "1" when (signed(j_1_reg_298) < signed(tmp_22_fu_699_p6)) else "0";
tmp_19_fu_1331_p1 <= tmp_12_fu_1314_p2(12 - 1 downto 0);
tmp_1_fu_606_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_20_fu_897_p2 <= "1" when (signed(i_4_reg_344) < signed(tmp_25_fu_884_p6)) else "0";
tmp_23_fu_1343_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1323_p3) + unsigned(p_shl1_cast_fu_1335_p3));
tmp_24_cast_fu_737_p1 <= std_logic_vector(resize(signed(j_1_reg_298),38));
tmp_27_cast_fu_922_p1 <= std_logic_vector(resize(signed(i_4_reg_344),38));
tmp_27_fu_690_p1 <= i_3_reg_286(2 - 1 downto 0);
tmp_28_fu_791_p2 <= "1" when (signed(k_1_cast_fu_787_p1) < signed(tmp_26_reg_1534)) else "0";
tmp_29_fu_970_p2 <= "1" when (signed(j_2_cast_fu_966_p1) < signed(tmp_54_reg_1630)) else "0";
tmp_2_fu_1404_p2 <= "1" when (signed(i_cast_fu_1400_p1) < signed(P_config_read_reg_1470)) else "0";
tmp_30_fu_1026_p2 <= "1" when (signed(i_5_cast_fu_1022_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_31_fu_682_p1 <= tmp_11_fu_676_p2(9 - 1 downto 0);
tmp_33_fu_694_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_31_reg_1501))), 9));
tmp_34_fu_853_p1 <= tmp_34_neg_fu_847_p2;
tmp_34_neg_fu_847_p2 <= (tmp_34_to_int_fu_843_p1 xor ap_const_lv32_80000000);
tmp_34_to_int_fu_843_p1 <= reg_574;
tmp_3_fu_633_p1 <= std_logic_vector(resize(unsigned(i_2_reg_275),64));
tmp_40_fu_686_p1 <= tmp_11_fu_676_p2(2 - 1 downto 0);
tmp_46_fu_871_p1 <= grp_fu_666_p2(9 - 1 downto 0);
tmp_48_fu_1051_p2 <= "1" when (P_mode_read_reg_1443 = ap_const_lv32_3) else "0";
tmp_49_fu_1113_p2 <= "1" when (signed(i_6_cast_fu_1109_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_4_cast_fu_1310_p1 <= std_logic_vector(resize(signed(j_reg_458),38));
tmp_4_fu_1415_p1 <= i_reg_480(2 - 1 downto 0);
tmp_50_fu_1060_p2 <= "1" when (signed(p_netOut_2_cast_fu_1056_p1) < signed(tmp_25_reg_1616)) else "0";
tmp_51_fu_875_p1 <= grp_fu_666_p2(38 - 1 downto 0);
tmp_52_fu_672_p1 <= tmp_13_fu_657_p2(2 - 1 downto 0);
tmp_53_fu_863_p1 <= tmp_15_fu_858_p2(9 - 1 downto 0);
tmp_55_fu_1230_p2 <= "1" when (signed(j_3_reg_435) < signed(tmp_66_fu_1217_p6)) else "0";
tmp_56_fu_879_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(tmp_53_reg_1589))), 9));
tmp_57_fu_1132_p4 <= p_uOut_load_3_to_int_fu_1128_p1(30 downto 23);
tmp_58_fu_867_p1 <= tmp_15_fu_858_p2(2 - 1 downto 0);
tmp_59_fu_1149_p4 <= p_uOut_load_4_to_int_fu_1146_p1(30 downto 23);
tmp_60_fu_1386_p1 <= k_reg_469(14 - 1 downto 0);
tmp_61_fu_1175_p2 <= (notrhs_fu_1169_p2 or notlhs_fu_1163_p2);
tmp_62_fu_1193_p2 <= (notrhs2_fu_1187_p2 or notlhs1_fu_1181_p2);
tmp_63_fu_1199_p2 <= (tmp_61_fu_1175_p2 and tmp_62_fu_1193_p2);
tmp_64_fu_515_opcode <= ap_const_lv5_2;
tmp_65_fu_1205_p2 <= (tmp_63_fu_1199_p2 and tmp_64_fu_515_p2);
tmp_67_fu_1390_p2 <= std_logic_vector(unsigned(tmp_23_reg_1804) + unsigned(tmp_60_fu_1386_p1));
tmp_68_fu_741_p2 <= std_logic_vector(signed(tmp_24_cast_fu_737_p1) + signed(tmp_24_reg_1511));
tmp_69_fu_751_p1 <= tmp_68_fu_741_p2(9 - 1 downto 0);
tmp_6_fu_1260_p2 <= "1" when (signed(i_1_cast_fu_1256_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_70_fu_763_p1 <= tmp_68_fu_741_p2(12 - 1 downto 0);
tmp_71_fu_775_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_755_p3) + unsigned(p_shl3_cast_fu_767_p3));
tmp_72_fu_926_p2 <= std_logic_vector(signed(tmp_27_cast_fu_922_p1) + signed(tmp_51_reg_1606));
tmp_73_fu_936_p1 <= tmp_72_fu_926_p2(9 - 1 downto 0);
tmp_74_fu_948_p1 <= tmp_72_fu_926_p2(12 - 1 downto 0);
tmp_75_fu_960_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_940_p3) + unsigned(p_shl5_cast_fu_952_p3));
tmp_76_cast_fu_1395_p1 <= std_logic_vector(resize(unsigned(tmp_67_fu_1390_p2),64));
tmp_76_fu_1037_p1 <= i_5_reg_378(9 - 1 downto 0);
tmp_77_cast_fu_746_p1 <= std_logic_vector(resize(signed(tmp_68_fu_741_p2),64));
tmp_77_fu_1041_p2 <= std_logic_vector(unsigned(tmp_46_reg_1599) + unsigned(tmp_76_fu_1037_p1));
tmp_78_fu_802_p1 <= k_1_reg_321(9 - 1 downto 0);
tmp_79_fu_806_p1 <= k_1_reg_321(14 - 1 downto 0);
tmp_7_fu_622_p2 <= "1" when (signed(i_2_cast_fu_618_p1) < signed(ST_layerSize_0_load_reg_1465)) else "0";
tmp_80_fu_810_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_79_fu_806_p1));
tmp_81_cast_fu_931_p1 <= std_logic_vector(resize(signed(tmp_72_fu_926_p2),64));
tmp_81_fu_820_p2 <= std_logic_vector(unsigned(tmp_33_reg_1521) + unsigned(tmp_78_fu_802_p1));
tmp_82_fu_830_p1 <= tmp_26_reg_1534(14 - 1 downto 0);
tmp_83_fu_833_p2 <= std_logic_vector(unsigned(tmp_71_reg_1540) + unsigned(tmp_82_fu_830_p1));
tmp_84_fu_981_p1 <= j_2_reg_367(9 - 1 downto 0);
tmp_85_cast_fu_815_p1 <= std_logic_vector(resize(unsigned(tmp_80_fu_810_p2),64));
tmp_85_fu_985_p1 <= j_2_reg_367(14 - 1 downto 0);
tmp_86_cast_fu_825_p1 <= std_logic_vector(resize(signed(tmp_81_fu_820_p2),64));
tmp_86_fu_989_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_85_fu_985_p1));
tmp_87_cast_fu_838_p1 <= std_logic_vector(resize(unsigned(tmp_83_fu_833_p2),64));
tmp_87_fu_999_p2 <= std_logic_vector(unsigned(tmp_56_reg_1611) + unsigned(tmp_84_fu_981_p1));
tmp_88_cast_fu_994_p1 <= std_logic_vector(resize(unsigned(tmp_86_fu_989_p2),64));
tmp_88_fu_1009_p1 <= tmp_54_reg_1630(14 - 1 downto 0);
tmp_89_cast_fu_1004_p1 <= std_logic_vector(resize(signed(tmp_87_fu_999_p2),64));
tmp_89_fu_1012_p2 <= std_logic_vector(unsigned(tmp_75_reg_1636) + unsigned(tmp_88_fu_1009_p1));
tmp_90_cast_fu_1017_p1 <= std_logic_vector(resize(unsigned(tmp_89_fu_1012_p2),64));
tmp_90_fu_1099_p1 <= phi_mul_reg_424(9 - 1 downto 0);
tmp_91_cast_fu_1046_p1 <= std_logic_vector(resize(signed(tmp_77_fu_1041_p2),64));
tmp_91_fu_1124_p1 <= i_6_reg_413(2 - 1 downto 0);
tmp_92_fu_1065_p1 <= p_netOut_2_reg_402(9 - 1 downto 0);
tmp_93_cast_fu_1074_p1 <= std_logic_vector(resize(signed(tmp_93_fu_1069_p2),64));
tmp_93_fu_1069_p2 <= std_logic_vector(unsigned(tmp_92_fu_1065_p1) + unsigned(tmp_46_reg_1599));
tmp_94_cast_fu_1088_p1 <= std_logic_vector(resize(signed(tmp_94_fu_1083_p2),64));
tmp_94_fu_1083_p2 <= std_logic_vector(unsigned(tmp_96_fu_1079_p1) + unsigned(tmp_46_reg_1599));
tmp_95_cast_fu_1251_p1 <= std_logic_vector(resize(unsigned(tmp_95_fu_1246_p2),64));
tmp_95_fu_1246_p2 <= std_logic_vector(unsigned(tmp_90_reg_1720) + unsigned(tmp_99_fu_1242_p1));
tmp_96_fu_1079_p1 <= p_netOut_reg_389(9 - 1 downto 0);
tmp_97_fu_1142_p1 <= p_uOut_load_3_to_int_fu_1128_p1(23 - 1 downto 0);
tmp_98_fu_1159_p1 <= p_uOut_load_4_to_int_fu_1146_p1(23 - 1 downto 0);
tmp_99_fu_1242_p1 <= j_3_reg_435(9 - 1 downto 0);
tmp_9_fu_642_p2 <= "1" when (signed(i_3_cast_fu_638_p1) < signed(ST_numLayer_load_reg_1452)) else "0";
tmp_9_t_fu_1279_p2 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_10_fu_1275_p1));
tmp_fu_596_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_s_fu_1298_p2 <= "1" when (signed(j_reg_458) < signed(tmp_5_fu_1285_p6)) else "0";
end behav;
|
gpl-3.0
|
88055de347fc1c7e79d4f0dd8d8c400b
| 0.629394 | 3.181791 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/blk_mem_gen_v8_3/hdl/blk_mem_gen_v8_3.vhd
| 4 | 21,293 |
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|
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ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/mult_gen_v12_0/hdl/mult_gen_v12_0.vhd
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`protect end_protected
|
gpl-3.0
|
ebb5651d6a717ec8ac5477acf413bbe7
| 0.92033 | 1.936441 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
uart/tb_soc_uart_xmodem.vhd
| 1 | 7,050 |
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
library STD;
use STD.textio.all;
use work.txt_util.all;
entity tb_soc_uart_xmodem is
end entity tb_soc_uart_xmodem;
architecture testbench of tb_soc_uart_xmodem is
-- constants
constant clk_period : time := 10.41 ns; --Clock 96Mhz
constant Teststr : string :="The quick brown fox";
constant xm_packsize : natural := 128;
constant numpacks : natural := 2;
constant baudrate : natural := 115200;
constant bit_time : time := 8.68 us;
-- Clock signal:
signal clk : std_logic := '0';
-- Reset signal:
signal reset : std_logic := '1';
-- UART ports:
signal txd : std_logic;
signal rxd : std_logic := '1';
-- interrupt signals:
signal irq : std_logic;
-- Wishbone ports:
signal wb_adr_in : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector( 7 downto 0) := (others => '0');
signal wb_dat_out : std_logic_vector( 7 downto 0);
signal wb_we_in : std_logic := '0';
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_ack_out : std_logic;
signal cbyte : std_logic_vector(7 downto 0);
signal bitref : integer :=0;
signal finish : boolean := false;
constant log_file : string := "receive.log";
type t_xm_state is (s_idle,s_h1,s_pack,s_chk);
signal xm_state : t_xm_state := s_idle;
begin
uut: entity work.wb_uart_interface
generic map(
FIFO_DEPTH => 32 )
port map(
clk => clk,
reset => reset,
txd => txd,
rxd => rxd,
irq => irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_we_in => wb_we_in,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_ack_out => wb_ack_out
);
clock: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process clock;
send: process
procedure send_byte(v: std_logic_vector(7 downto 0)) is
variable bi : natural;
variable t : std_logic_vector(7 downto 0);
begin
bi:=7;
for i in 0 to 7 loop
t(bi) := v(i); -- for debugging purposes
bi:=bi-1;
end loop;
cbyte <= t;
bitref<= 0;
rxd <= '0'; -- start bit
for i in 0 to 7 loop
wait for bit_time;
rxd<=v(i);
bitref<=bitref+1;
end loop;
wait for bit_time;
rxd <= '1'; -- stop bit
bitref<=bitref+1;
wait for bit_time;
end;
procedure sendstring(s:string) is
begin
for i in 1 to s'length loop
send_byte(std_logic_vector(to_unsigned(character'pos(s(i)),8)));
end loop;
end;
variable checksum : unsigned(7 downto 0);
variable byte : std_logic_vector(7 downto 0);
begin
wait for bit_time*10;
-- Calculate xmodem packet
for p in 0 to numpacks loop
-- Header
byte:=std_logic_vector(to_unsigned(p,8));
send_byte(byte);
send_byte(not byte);
checksum:=to_unsigned(0,checksum'length);
for i in 0 to xm_packsize-1 loop
byte := char_to_ascii_byte(Teststr(i mod Teststr'length +1));
send_byte(byte);
checksum:=checksum+unsigned(byte);
end loop;
send_byte(std_logic_vector(checksum));
end loop;
wait for bit_time*10;
finish<=true; -- signal end of send simulation
wait;
end process;
stimulus: process
procedure uart_write(address : in std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0)) is
begin
wb_adr_in <= address;
wait until rising_edge(clk);
wb_dat_in <= data;
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait until wb_ack_out = '1';
wait until rising_edge(clk);
wb_stb_in <= '0';
wb_cyc_in <= '0';
end procedure;
procedure uart_read(address : in std_logic_vector(7 downto 0);
data: out std_logic_vector(7 downto 0) ) is
begin
wb_adr_in <= address;
wait until rising_edge(clk);
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_we_in <= '0';
wait until wb_ack_out = '1';
data:= wb_dat_out;
wait until rising_edge(clk);
wb_stb_in <= '0';
wb_cyc_in <= '0';
--wait for clk_period;
end procedure;
variable status,rx_byte,h1 : std_logic_vector(7 downto 0);
variable cnt: natural;
file l_file: TEXT open write_mode is log_file;
variable chksum : unsigned(7 downto 0);
variable s: string(1 to 1);
begin
wait for clk_period * 2;
reset <= '0';
uart_write(x"0C",std_logic_vector(to_unsigned(51,8))); -- Divisor 51 for 115200 Baud
-- Enable the data received interrupt:
--uart_write(x"10", x"01");
while not finish loop
-- Check Status Register
status := X"01";
while (status and X"01") = X"01" and not finish loop
uart_read(X"08",status);
end loop;
-- Get byte
if (status and X"01") = X"00" then
uart_read(X"04",rx_byte);
case xm_state is
when s_idle=>
print(l_file,"Seq: " & hstr(rx_byte));
h1:=rx_byte;
xm_state<=s_h1;
when s_h1=>
print(l_file,"~Seq: " & hstr(rx_byte));
if rx_byte /= not h1 then
report "Packet header error" severity error;
end if;
xm_state<=s_pack;
cnt:=1;
chksum:=X"00";
when s_pack=>
s(1):=character'val(to_integer(unsigned(rx_byte)));
write(l_file,s);
--print(l_file,hstr(rx_byte));
chksum:=chksum+unsigned(rx_byte);
if cnt=xm_packsize then
print(l_file,"");
xm_state <= s_chk;
end if;
cnt := cnt + 1;
when s_chk=>
print(l_file,"Checksum: " & hstr(std_logic_vector(chksum)) & " <-> " & hstr(rx_byte));
if std_logic_vector(chksum) /= rx_byte then
report "Packet checksum error" severity error;
end if;
xm_state <= s_idle;
end case;
end if;
end loop;
print("Simulation finished");
wait;
end process stimulus;
end architecture testbench;
|
gpl-3.0
|
c9531a11d3486a607e83e4eb4a634449
| 0.516596 | 3.459274 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ip/design_TEST_axi_dma_1_0/synth/design_TEST_axi_dma_1_0.vhd
| 1 | 22,109 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_TEST_axi_dma_1_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_TEST_axi_dma_1_0;
ARCHITECTURE design_TEST_axi_dma_1_0_arch OF design_TEST_axi_dma_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_TEST_axi_dma_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_TEST_axi_dma_1_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_TEST_axi_dma_1_0_arch : ARCHITECTURE IS "design_TEST_axi_dma_1_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_TEST_axi_dma_1_0_arch: ARCHITECTURE IS "design_TEST_axi_dma_1_0,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=256,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 256,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => '0',
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_TEST_axi_dma_1_0_arch;
|
gpl-3.0
|
293f8c4af0cf91e869f982b111708a13
| 0.671446 | 2.782406 | false | false | false | false |
airlog/vhdl-rc4
|
src/reseter_tb.vhd
| 1 | 2,585 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
ENTITY reseter_tb IS
END reseter_tb;
ARCHITECTURE behavior OF reseter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reseter
generic (
size: integer := 256;
width: integer := 8;
addrwidth: integer := 8;
rstvalue : integer := 0
);
PORT(
CLK: in std_logic;
GO: in std_logic;
CTRL: out std_logic;
INDEX: out std_logic_vector((addrwidth - 1) downto 0);
VALUE: out std_logic_vector((width - 1) downto 0);
DONE: out std_logic
);
END COMPONENT;
-- Inputs
signal CLK : std_logic := '0';
signal GO : std_logic := '0';
-- Outputs
signal CTRL : std_logic := '0';
signal INDEX : std_logic_vector(7 downto 0);
signal VALUE : std_logic_vector(7 downto 0);
signal DONE : std_logic;
-- Constants
constant CLK_period : time := 10 ns;
constant width : integer := 8;
constant mem_size : integer := 16;
-- Types
subtype int8 is integer range 0 to (2 ** width - 1);
type int8_array is array (0 to mem_size - 1) of int8;
-- Variables
shared variable memory : int8_array := (
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reseter
generic map(
size => mem_size,
width => width
)
port map(
CLK => CLK,
GO => GO,
CTRL => CTRL,
INDEX => INDEX,
VALUE => VALUE,
DONE => DONE
);
-- Clock process definitions
CLK_process: process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
mem_writer: process (clk, ctrl, index, value)
begin
if rising_edge(clk) then
if ctrl = '1' then
memory(conv_integer(unsigned(index))) := conv_integer(unsigned(value));
else
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
for i in 0 to (mem_size - 1) loop
assert memory(i) /= 0
report "Zly stan poczatkowy pamieci!"
severity warning;
end loop;
wait for clk_period;
go <= '1';
wait for 2 * clk_period;
go <= '0';
while done = '0' loop
wait for clk_period/2;
end loop;
wait for 5 * clk_period;
assert done = '1'
report "Dzialanie urzadzenia powinno juz sie zakonczyc!"
severity failure;
for i in 0 to (mem_size - 1) loop
assert memory(i) = 0
report "Zly stan koncowy pamieci!"
severity failure;
end loop;
wait;
end process;
END;
|
mit
|
466836143f4bfb9d703ee2b40be9b261
| 0.600387 | 2.995365 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fcmp_32ns_32ns_1_1.vhd
| 4 | 4,486 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 5;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component feedforward_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fcmp_0_no_dsp_32_u : component feedforward_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
gpl-3.0
|
17c409c7766fdecde465acf57bc1e421
| 0.518502 | 3.469451 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/vhdl/feedforward.vhd
| 1 | 186,774 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
P_config_V_TVALID : IN STD_LOGIC;
P_config_V_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
P_netOut_V_TVALID : OUT STD_LOGIC;
P_netOut_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=9.395400,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=36,HLS_SYN_DSP=45,HLS_SYN_FF=7111,HLS_SYN_LUT=10472}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (164 downto 0) := "000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (164 downto 0) := "000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st155_fsm_154 : STD_LOGIC_VECTOR (164 downto 0) := "000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st156_fsm_155 : STD_LOGIC_VECTOR (164 downto 0) := "000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st157_fsm_156 : STD_LOGIC_VECTOR (164 downto 0) := "000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st158_fsm_157 : STD_LOGIC_VECTOR (164 downto 0) := "000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st159_fsm_158 : STD_LOGIC_VECTOR (164 downto 0) := "000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st160_fsm_159 : STD_LOGIC_VECTOR (164 downto 0) := "000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st161_fsm_160 : STD_LOGIC_VECTOR (164 downto 0) := "000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st162_fsm_161 : STD_LOGIC_VECTOR (164 downto 0) := "000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st163_fsm_162 : STD_LOGIC_VECTOR (164 downto 0) := "001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st164_fsm_163 : STD_LOGIC_VECTOR (164 downto 0) := "010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st165_fsm_164 : STD_LOGIC_VECTOR (164 downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_9C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011100";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_9B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011011";
constant ap_const_lv32_9D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011101";
constant ap_const_lv32_9E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011110";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100001";
constant ap_const_lv32_A2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100010";
constant ap_const_lv32_A3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100011";
constant ap_const_lv32_A4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100100";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_9A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011010";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv15_23 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv9_1FF : STD_LOGIC_VECTOR (8 downto 0) := "111111111";
constant ap_const_lv16_23 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000100011";
constant ap_const_lv9_1FE : STD_LOGIC_VECTOR (8 downto 0) := "111111110";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_8000000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv14_23 : STD_LOGIC_VECTOR (13 downto 0) := "00000000100011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
constant ap_const_lv52_0 : STD_LOGIC_VECTOR (51 downto 0) := "0000000000000000000000000000000000000000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv14_5 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000101";
constant ap_const_lv14_2 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000010";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (164 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_183 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode_V : STD_LOGIC_VECTOR (7 downto 0);
signal ST_numLayer_V : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_547 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_265 : BOOLEAN;
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_272 : BOOLEAN;
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_280 : BOOLEAN;
signal ap_sig_cseq_ST_st157_fsm_156 : STD_LOGIC;
signal ap_sig_bdd_288 : BOOLEAN;
signal reg_554 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_297 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_306 : BOOLEAN;
signal grp_fu_512_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_560 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_316 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_323 : BOOLEAN;
signal grp_fu_504_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_333 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_340 : BOOLEAN;
signal reg_571 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_349 : BOOLEAN;
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_356 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_364 : BOOLEAN;
signal grp_fu_526_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_577 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_374 : BOOLEAN;
signal ap_sig_cseq_ST_st116_fsm_115 : STD_LOGIC;
signal ap_sig_bdd_381 : BOOLEAN;
signal grp_fu_516_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_584 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_391 : BOOLEAN;
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_398 : BOOLEAN;
signal P_mode_V_read_reg_1418 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_589_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_411 : BOOLEAN;
signal tmp_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_V_load_reg_1427 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_599_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1435 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_V_0_load_reg_1439 : STD_LOGIC_VECTOR (7 downto 0);
signal P_config_V_read_reg_1444 : STD_LOGIC_VECTOR (7 downto 0);
signal i_8_fu_616_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_435 : BOOLEAN;
signal exitcond1_fu_611_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_441 : BOOLEAN;
signal tmp_59_cast_fu_642_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_cast_reg_1460 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_451 : BOOLEAN;
signal tmp_7_fu_627_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_646_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_reg_1465 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_fu_660_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_29_reg_1470 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_666_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_31_reg_1475 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_36_fu_689_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_reg_1480 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_61_cast_fu_693_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_61_cast_reg_1487 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_39_fu_697_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_39_reg_1492 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_41_fu_707_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_41_reg_1497 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_42_fu_713_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_42_reg_1502 : STD_LOGIC_VECTOR (1 downto 0);
signal j_5_fu_740_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1510 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_481 : BOOLEAN;
signal tmp_20_fu_746_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_20_reg_1515 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_734_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_793_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_54_reg_1521 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_1_reg_1527 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_799_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_fu_810_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_reg_1540 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_503 : BOOLEAN;
signal exitcond3_fu_805_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_867_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_523 : BOOLEAN;
signal tmp_17_fu_872_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_reg_1565 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_532 : BOOLEAN;
signal i_12_fu_895_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_901_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_22_reg_1579 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_fu_889_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_952_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_58_reg_1585 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_3_reg_1591 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_963_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_reg_1599 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_553 : BOOLEAN;
signal exitcond4_fu_958_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st121_fsm_120 : STD_LOGIC;
signal ap_sig_bdd_572 : BOOLEAN;
signal i_11_fu_1015_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_11_reg_1627 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_581 : BOOLEAN;
signal p_uOut_addr_5_reg_1632 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond5_fu_1010_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_1035_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_reg_1637 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st156_fsm_155 : STD_LOGIC;
signal ap_sig_bdd_599 : BOOLEAN;
signal tmp_38_fu_1040_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_V_TREADY : STD_LOGIC;
signal tmp_66_fu_1073_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_66_reg_1654 : STD_LOGIC_VECTOR (8 downto 0);
signal next_mul_fu_1077_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal next_mul_reg_1659 : STD_LOGIC_VECTOR (13 downto 0);
signal i_14_fu_1088_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_14_reg_1667 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_40_fu_1098_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_40_reg_1672 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond6_fu_1083_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_uOut_q1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_uOut_load_4_reg_1677 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_51_fu_1189_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_51_reg_1683 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st158_fsm_157 : STD_LOGIC;
signal ap_sig_bdd_643 : BOOLEAN;
signal p_netOut_V_1_fu_1195_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st159_fsm_158 : STD_LOGIC;
signal ap_sig_bdd_652 : BOOLEAN;
signal i_15_fu_1202_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_7_fu_1213_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_7_reg_1701 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st160_fsm_159 : STD_LOGIC;
signal ap_sig_bdd_663 : BOOLEAN;
signal exitcond_fu_1208_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_1233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_1711 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st162_fsm_161 : STD_LOGIC;
signal ap_sig_bdd_677 : BOOLEAN;
signal tmp_s_fu_1242_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_s_reg_1715 : STD_LOGIC_VECTOR (13 downto 0);
signal ST_layerSize_V_load_1_phi_fu_1272_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_layerSize_V_load_1_phi_reg_1720 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_fu_1304_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_10_reg_1725 : STD_LOGIC_VECTOR (8 downto 0);
signal j_4_fu_1315_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_4_reg_1733 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st163_fsm_162 : STD_LOGIC;
signal ap_sig_bdd_695 : BOOLEAN;
signal tmp_21_fu_1342_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_reg_1738 : STD_LOGIC_VECTOR (13 downto 0);
signal exitcond2_fu_1310_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1348_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_2_fu_1373_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st164_fsm_163 : STD_LOGIC;
signal ap_sig_bdd_713 : BOOLEAN;
signal exitcond8_fu_1368_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_719 : BOOLEAN;
signal exitcond7_fu_1379_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond7_reg_1756 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st165_fsm_164 : STD_LOGIC;
signal ap_sig_bdd_729 : BOOLEAN;
signal ap_sig_bdd_733 : BOOLEAN;
signal i_7_fu_1384_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_287 : STD_LOGIC_VECTOR (7 downto 0);
signal i_3_reg_298 : STD_LOGIC_VECTOR (7 downto 0);
signal j_1_reg_310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_764 : BOOLEAN;
signal sum_reg_321 : STD_LOGIC_VECTOR (63 downto 0);
signal k_1_reg_333 : STD_LOGIC_VECTOR (7 downto 0);
signal sumsoft_reg_344 : STD_LOGIC_VECTOR (63 downto 0);
signal i_4_reg_356 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_367 : STD_LOGIC_VECTOR (63 downto 0);
signal j_2_reg_379 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_390 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st155_fsm_154 : STD_LOGIC;
signal ap_sig_bdd_786 : BOOLEAN;
signal p_s_reg_401 : STD_LOGIC_VECTOR (7 downto 0);
signal p_netOut_V_reg_414 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_reg_426 : STD_LOGIC_VECTOR (7 downto 0);
signal phi_mul_reg_437 : STD_LOGIC_VECTOR (13 downto 0);
signal j_3_reg_448 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st161_fsm_160 : STD_LOGIC;
signal ap_sig_bdd_813 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_459 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_471 : STD_LOGIC_VECTOR (7 downto 0);
signal k_reg_482 : STD_LOGIC_VECTOR (8 downto 0);
signal i_reg_493 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_fu_622_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_64_cast_fu_764_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_73_cast_fu_829_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_74_cast_fu_839_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_72_cast_fu_852_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_68_cast_fu_923_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_982_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_992_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_75_cast_fu_1005_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_78_cast_fu_1030_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_80_cast_fu_1054_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_1068_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_cast_fu_1228_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_cast_fu_1363_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_1390_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_V_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_927 : BOOLEAN;
signal grp_fu_504_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_504_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_952 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_959 : BOOLEAN;
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_967 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_974 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_981 : BOOLEAN;
signal grp_fu_516_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_516_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_1010 : BOOLEAN;
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_1017 : BOOLEAN;
signal grp_fu_526_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_1027 : BOOLEAN;
signal tmp_23_fu_636_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_23_fu_636_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_4_fu_650_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_29_fu_660_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_1_cast_fu_670_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_673_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_683_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_683_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_1_fu_701_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_14_fu_717_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_fu_730_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_759_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_fu_769_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_fu_781_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl1_cast_fu_773_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl2_cast_fu_785_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_29_cast_fu_820_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_61_fu_824_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_29_cast1_fu_816_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_62_fu_834_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_24_cast_fu_844_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_60_fu_847_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_38_to_int_fu_857_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_neg_fu_861_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_fu_885_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_cast_fu_914_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_55_fu_918_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_56_fu_928_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_57_fu_940_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl3_cast_fu_932_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl4_cast_fu_944_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast_fu_973_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_64_fu_977_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast1_fu_969_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_987_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_cast_fu_997_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_63_fu_1000_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_36_cast_fu_1021_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_59_fu_1025_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_41_cast_fu_1045_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_68_fu_1049_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_42_cast_fu_1059_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_fu_1063_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_40_fu_1098_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal p_uOut_load_3_to_int_fu_1112_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_uOut_load_4_to_int_fu_1130_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_43_fu_1116_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_70_fu_1126_p1 : STD_LOGIC_VECTOR (51 downto 0);
signal notrhs_fu_1153_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1147_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_45_fu_1133_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_71_fu_1143_p1 : STD_LOGIC_VECTOR (51 downto 0);
signal notrhs1_fu_1171_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1165_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_47_fu_1159_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_fu_1177_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_fu_1183_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_522_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_52_cast_fu_1219_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_72_fu_1223_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_1242_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_fu_1248_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp_fu_1252_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_1266_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_1258_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_fu_1286_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_2_fu_1286_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_fu_1300_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_cast_fu_1321_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_11_fu_1325_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_12_fu_1330_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_1336_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_12_cast_fu_1354_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_44_fu_1358_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_504_ce : STD_LOGIC;
signal grp_fu_512_ce : STD_LOGIC;
signal grp_fu_516_ce : STD_LOGIC;
signal tmp_50_fu_522_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_526_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (164 downto 0);
signal tmp_23_fu_636_p10 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_29_fu_660_p10 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_1242_p10 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_bdd_906 : BOOLEAN;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dmul_64ns_64ns_64_6_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dcmp_64ns_64ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mux_4to1_sel2_8_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (7 downto 0);
din3 : IN STD_LOGIC_VECTOR (7 downto 0);
din4 : IN STD_LOGIC_VECTOR (7 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (63 downto 0);
q0 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (63 downto 0);
q0 : OUT STD_LOGIC_VECTOR (63 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode_V : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 64,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode_V => P_mode_V);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 64,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U0 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_504_p0,
din1 => grp_fu_504_p1,
ce => grp_fu_504_ce,
dout => grp_fu_504_p2);
feedforward_dmul_64ns_64ns_64_6_max_dsp_U1 : component feedforward_dmul_64ns_64ns_64_6_max_dsp
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_547,
din1 => reg_554,
ce => grp_fu_512_ce,
dout => grp_fu_512_p2);
feedforward_ddiv_64ns_64ns_64_31_U2 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_516_p0,
din1 => grp_fu_516_p1,
ce => grp_fu_516_ce,
dout => grp_fu_516_p2);
feedforward_dcmp_64ns_64ns_1_1_U3 : component feedforward_dcmp_64ns_64ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 1)
port map (
din0 => reg_547,
din1 => p_uOut_load_4_reg_1677,
opcode => tmp_50_fu_522_opcode,
dout => tmp_50_fu_522_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U4 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => grp_fu_526_p1,
ce => grp_fu_526_ce,
dout => grp_fu_526_p2);
feedforward_mux_4to1_sel2_8_1_U5 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_24_reg_1465,
dout => tmp_14_fu_717_p6);
feedforward_mux_4to1_sel2_8_1_U6 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_31_reg_1475,
dout => tmp_20_fu_746_p6);
feedforward_mux_4to1_sel2_8_1_U7 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_39_reg_1492,
dout => tmp_17_fu_872_p6);
feedforward_mux_4to1_sel2_8_1_U8 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_42_reg_1502,
dout => tmp_22_fu_901_p6);
feedforward_mux_4to1_sel2_8_1_U9 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_40_fu_1098_p5,
dout => tmp_40_fu_1098_p6);
feedforward_mux_4to1_sel2_8_1_U10 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_2_fu_1286_p5,
dout => tmp_2_fu_1286_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_V_TREADY assign process. --
ap_reg_ioackin_P_netOut_V_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_906) then
if (not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_V_TREADY)) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_459 assign process. --
i_1_reg_459_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_589_p2 = ap_const_lv1_0) and not(ap_sig_bdd_411) and not((ap_const_lv1_0 = tmp_1_fu_599_p2)))) then
i_1_reg_459 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162) and not((ap_const_lv1_0 = exitcond2_fu_1310_p2)))) then
i_1_reg_459 <= i_9_fu_1348_p2;
end if;
end if;
end process;
-- i_2_reg_287 assign process. --
i_2_reg_287_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_589_p2 = ap_const_lv1_0) and not(ap_sig_bdd_411) and (ap_const_lv1_0 = tmp_1_fu_599_p2))) then
i_2_reg_287 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_611_p2) and not(ap_sig_bdd_441))) then
i_2_reg_287 <= i_8_fu_616_p2;
end if;
end if;
end process;
-- i_3_reg_298 assign process. --
i_3_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_441) and not((ap_const_lv1_0 = exitcond1_fu_611_p2)))) then
i_3_reg_298 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (ap_const_lv1_0 = tmp_16_fu_734_p2))) then
i_3_reg_298 <= i_10_fu_799_p2;
end if;
end if;
end process;
-- i_4_reg_356 assign process. --
i_4_reg_356_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_627_p2))) then
i_4_reg_356 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) then
i_4_reg_356 <= i_12_reg_1574;
end if;
end if;
end process;
-- i_5_reg_390 assign process. --
i_5_reg_390_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and (ap_const_lv1_0 = tmp_19_fu_889_p2))) then
i_5_reg_390 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) then
i_5_reg_390 <= i_11_reg_1627;
end if;
end if;
end process;
-- i_6_reg_426 assign process. --
i_6_reg_426_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159) and not((ap_const_lv1_0 = exitcond_fu_1208_p2)))) then
i_6_reg_426 <= i_14_reg_1667;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1010_p2)) and not((ap_const_lv1_0 = tmp_35_fu_1035_p2)))) then
i_6_reg_426 <= ap_const_lv8_0;
end if;
end if;
end process;
-- i_reg_493 assign process. --
i_reg_493_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733))) then
i_reg_493 <= i_7_fu_1384_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_589_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_411))) then
i_reg_493 <= ap_const_lv8_0;
end if;
end if;
end process;
-- j_1_reg_310 assign process. --
j_1_reg_310_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_627_p2)))) then
j_1_reg_310 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
j_1_reg_310 <= j_5_reg_1510;
end if;
end if;
end process;
-- j_2_reg_379 assign process. --
j_2_reg_379_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = tmp_19_fu_889_p2)))) then
j_2_reg_379 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
j_2_reg_379 <= j_6_reg_1599;
end if;
end if;
end process;
-- j_3_reg_448 assign process. --
j_3_reg_448_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_35_reg_1637)) and (ap_const_lv1_0 = exitcond6_fu_1083_p2))) then
j_3_reg_448 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_448 <= j_7_reg_1701;
end if;
end if;
end process;
-- j_reg_471 assign process. --
j_reg_471_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and not(ap_sig_bdd_719) and not((ap_const_lv1_0 = exitcond8_fu_1368_p2)))) then
j_reg_471 <= j_4_reg_1733;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161) and not((ap_const_lv1_0 = tmp_8_fu_1233_p2)))) then
j_reg_471 <= ap_const_lv8_0;
end if;
end if;
end process;
-- k_1_reg_333 assign process. --
k_1_reg_333_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_16_fu_734_p2)))) then
k_1_reg_333 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
k_1_reg_333 <= k_3_reg_1540;
end if;
end if;
end process;
-- k_reg_482 assign process. --
k_reg_482_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162) and (ap_const_lv1_0 = exitcond2_fu_1310_p2))) then
k_reg_482 <= ap_const_lv9_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and (ap_const_lv1_0 = exitcond8_fu_1368_p2) and not(ap_sig_bdd_719))) then
k_reg_482 <= k_2_fu_1373_p2;
end if;
end if;
end process;
-- p_netOut_V_reg_414 assign process. --
p_netOut_V_reg_414_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1010_p2)) and (ap_const_lv1_0 = tmp_35_fu_1035_p2))) then
p_netOut_V_reg_414 <= ap_const_lv8_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) then
p_netOut_V_reg_414 <= i_15_fu_1202_p2;
end if;
end if;
end process;
-- p_s_reg_401 assign process. --
p_s_reg_401_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1010_p2)) and (ap_const_lv1_0 = tmp_35_fu_1035_p2))) then
p_s_reg_401 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) then
p_s_reg_401 <= p_netOut_V_1_fu_1195_p3;
end if;
end if;
end process;
-- phi_mul_reg_437 assign process. --
phi_mul_reg_437_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159) and not((ap_const_lv1_0 = exitcond_fu_1208_p2)))) then
phi_mul_reg_437 <= next_mul_reg_1659;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1010_p2)) and not((ap_const_lv1_0 = tmp_35_fu_1035_p2)))) then
phi_mul_reg_437 <= ap_const_lv14_0;
end if;
end if;
end process;
-- sum_1_reg_367 assign process. --
sum_1_reg_367_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = tmp_19_fu_889_p2)))) then
sum_1_reg_367 <= ap_const_lv64_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
sum_1_reg_367 <= grp_fu_504_p2;
end if;
end if;
end process;
-- sum_reg_321 assign process. --
sum_reg_321_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_16_fu_734_p2)))) then
sum_reg_321 <= ap_const_lv64_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
sum_reg_321 <= grp_fu_504_p2;
end if;
end if;
end process;
-- sumsoft_reg_344 assign process. --
sumsoft_reg_344_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_627_p2))) then
sumsoft_reg_344 <= ap_const_lv64_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) then
sumsoft_reg_344 <= grp_fu_504_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_589_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_411))) then
P_config_V_read_reg_1444 <= P_config_V_TDATA;
ST_numLayer_V <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_411))) then
P_mode_V_read_reg_1418 <= P_mode_V;
ST_numLayer_V_load_reg_1427 <= ST_numLayer_V;
tmp_reg_1423 <= tmp_fu_589_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733) and (tmp_3_fu_1390_p1 = ap_const_lv2_0))) then
ST_layerSize_V_0 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_589_p2 = ap_const_lv1_0) and not(ap_sig_bdd_411) and (ap_const_lv1_0 = tmp_1_fu_599_p2))) then
ST_layerSize_V_0_load_reg_1439 <= ST_layerSize_V_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733) and (tmp_3_fu_1390_p1 = ap_const_lv2_1))) then
ST_layerSize_V_1 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733) and (tmp_3_fu_1390_p1 = ap_const_lv2_2))) then
ST_layerSize_V_2 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733) and not((tmp_3_fu_1390_p1 = ap_const_lv2_2)) and not((tmp_3_fu_1390_p1 = ap_const_lv2_1)) and not((tmp_3_fu_1390_p1 = ap_const_lv2_0)))) then
ST_layerSize_V_3 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161) and not((ap_const_lv1_0 = tmp_8_fu_1233_p2)))) then
ST_layerSize_V_load_1_phi_reg_1720 <= ST_layerSize_V_load_1_phi_fu_1272_p3;
tmp_10_reg_1725 <= tmp_10_fu_1304_p2;
tmp_s_reg_1715 <= tmp_s_fu_1242_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and not(ap_sig_bdd_733))) then
exitcond7_reg_1756 <= exitcond7_fu_1379_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
i_11_reg_1627 <= i_11_fu_1015_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
i_12_reg_1574 <= i_12_fu_895_p2;
tmp_17_reg_1565 <= tmp_17_fu_872_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_35_reg_1637)))) then
i_14_reg_1667 <= i_14_fu_1088_p2;
next_mul_reg_1659 <= next_mul_fu_1077_p2;
tmp_66_reg_1654 <= tmp_66_fu_1073_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162)) then
j_4_reg_1733 <= j_4_fu_1315_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
j_5_reg_1510 <= j_5_fu_740_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
j_6_reg_1599 <= j_6_fu_963_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) then
j_7_reg_1701 <= j_7_fu_1213_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
k_3_reg_1540 <= k_3_fu_810_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_16_fu_734_p2)))) then
p_uOut_addr_1_reg_1527 <= tmp_64_cast_fu_764_p1(8 - 1 downto 0);
tmp_20_reg_1515 <= tmp_20_fu_746_p6;
tmp_54_reg_1521(13 downto 2) <= tmp_54_fu_793_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = tmp_19_fu_889_p2)))) then
p_uOut_addr_3_reg_1591 <= tmp_68_cast_fu_923_p1(8 - 1 downto 0);
tmp_22_reg_1579 <= tmp_22_fu_901_p6;
tmp_58_reg_1585(13 downto 2) <= tmp_58_fu_952_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and (ap_const_lv1_0 = exitcond5_fu_1010_p2))) then
p_uOut_addr_5_reg_1632 <= tmp_78_cast_fu_1030_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156)) then
p_uOut_load_4_reg_1677 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) or (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) or (ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156))) then
reg_547 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
reg_554 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
reg_560 <= grp_fu_512_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_571 <= grp_fu_504_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) or (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115))) then
reg_577 <= grp_fu_526_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153))) then
reg_584 <= grp_fu_516_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_589_p2 = ap_const_lv1_0) and not(ap_sig_bdd_411))) then
tmp_1_reg_1435 <= tmp_1_fu_599_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162) and (ap_const_lv1_0 = exitcond2_fu_1310_p2))) then
tmp_21_reg_1738(13 downto 2) <= tmp_21_fu_1342_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_627_p2)))) then
tmp_24_reg_1465 <= tmp_24_fu_646_p1;
tmp_29_reg_1470 <= tmp_29_fu_660_p2;
tmp_31_reg_1475 <= tmp_31_fu_666_p1;
tmp_59_cast_reg_1460(14 downto 0) <= tmp_59_cast_fu_642_p1(14 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1010_p2)))) then
tmp_35_reg_1637 <= tmp_35_fu_1035_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_627_p2))) then
tmp_36_reg_1480 <= tmp_36_fu_689_p1;
tmp_39_reg_1492 <= tmp_39_fu_697_p1;
tmp_41_reg_1497 <= tmp_41_fu_707_p2;
tmp_42_reg_1502 <= tmp_42_fu_713_p1;
tmp_61_cast_reg_1487 <= tmp_61_cast_fu_693_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_35_reg_1637)) and (ap_const_lv1_0 = exitcond6_fu_1083_p2))) then
tmp_40_reg_1672 <= tmp_40_fu_1098_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st158_fsm_157)) then
tmp_51_reg_1683 <= tmp_51_fu_1189_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161)) then
tmp_8_reg_1711 <= tmp_8_fu_1233_p2;
end if;
end if;
end process;
tmp_59_cast_reg_1460(31 downto 15) <= "00000000000000000";
tmp_54_reg_1521(1 downto 0) <= "00";
tmp_58_reg_1585(1 downto 0) <= "00";
tmp_21_reg_1738(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_589_p2, ap_sig_bdd_411, tmp_reg_1423, tmp_1_fu_599_p2, tmp_1_reg_1435, exitcond1_fu_611_p2, ap_sig_bdd_441, tmp_7_fu_627_p2, tmp_16_fu_734_p2, exitcond3_fu_805_p2, tmp_19_fu_889_p2, exitcond4_fu_958_p2, exitcond5_fu_1010_p2, tmp_35_reg_1637, tmp_38_fu_1040_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond6_fu_1083_p2, exitcond_fu_1208_p2, tmp_8_fu_1233_p2, tmp_8_reg_1711, exitcond2_fu_1310_p2, exitcond8_fu_1368_p2, ap_sig_bdd_719, exitcond7_fu_1379_p2, exitcond7_reg_1756, ap_sig_bdd_733, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_589_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_411))) then
ap_NS_fsm <= ap_ST_st165_fsm_164;
elsif (((tmp_fu_589_p2 = ap_const_lv1_0) and not(ap_sig_bdd_411) and (ap_const_lv1_0 = tmp_1_fu_599_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_589_p2 = ap_const_lv1_0) and not(ap_sig_bdd_411) and not((ap_const_lv1_0 = tmp_1_fu_599_p2)))) then
ap_NS_fsm <= ap_ST_st162_fsm_161;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (((ap_const_lv1_0 = exitcond1_fu_611_p2) and not(ap_sig_bdd_441))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not(ap_sig_bdd_441) and not((ap_const_lv1_0 = exitcond1_fu_611_p2)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_7_fu_627_p2)) then
ap_NS_fsm <= ap_ST_st79_fsm_78;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
if ((ap_const_lv1_0 = tmp_16_fu_734_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ap_const_lv1_0 = exitcond3_fu_805_p2))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st79_fsm_78 =>
if (not((ap_const_lv1_0 = tmp_19_fu_889_p2))) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st122_fsm_121;
end if;
when ap_ST_st80_fsm_79 =>
if (not((ap_const_lv1_0 = exitcond4_fu_958_p2))) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st81_fsm_80;
end if;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st80_fsm_79;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st122_fsm_121 =>
if (not((ap_const_lv1_0 = exitcond5_fu_1010_p2))) then
ap_NS_fsm <= ap_ST_st156_fsm_155;
else
ap_NS_fsm <= ap_ST_st123_fsm_122;
end if;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st143_fsm_142 =>
ap_NS_fsm <= ap_ST_st144_fsm_143;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st147_fsm_146;
when ap_ST_st147_fsm_146 =>
ap_NS_fsm <= ap_ST_st148_fsm_147;
when ap_ST_st148_fsm_147 =>
ap_NS_fsm <= ap_ST_st149_fsm_148;
when ap_ST_st149_fsm_148 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st151_fsm_150;
when ap_ST_st151_fsm_150 =>
ap_NS_fsm <= ap_ST_st152_fsm_151;
when ap_ST_st152_fsm_151 =>
ap_NS_fsm <= ap_ST_st153_fsm_152;
when ap_ST_st153_fsm_152 =>
ap_NS_fsm <= ap_ST_st154_fsm_153;
when ap_ST_st154_fsm_153 =>
ap_NS_fsm <= ap_ST_st155_fsm_154;
when ap_ST_st155_fsm_154 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st156_fsm_155 =>
if ((not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2)) or (not((ap_const_lv1_0 = tmp_reg_1423)) and not((ap_const_lv1_0 = exitcond7_reg_1756))) or ((ap_const_lv1_0 = tmp_reg_1423) and not((ap_const_lv1_0 = tmp_1_reg_1435)) and (ap_const_lv1_0 = tmp_8_reg_1711)) or ((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not((ap_const_lv1_0 = tmp_35_reg_1637)) and not((ap_const_lv1_0 = exitcond6_fu_1083_p2)))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_35_reg_1637)) and (ap_const_lv1_0 = exitcond6_fu_1083_p2))) then
ap_NS_fsm <= ap_ST_st160_fsm_159;
elsif (((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_38_fu_1040_p2)))) then
ap_NS_fsm <= ap_ST_st157_fsm_156;
else
ap_NS_fsm <= ap_ST_st156_fsm_155;
end if;
when ap_ST_st157_fsm_156 =>
ap_NS_fsm <= ap_ST_st158_fsm_157;
when ap_ST_st158_fsm_157 =>
ap_NS_fsm <= ap_ST_st159_fsm_158;
when ap_ST_st159_fsm_158 =>
ap_NS_fsm <= ap_ST_st156_fsm_155;
when ap_ST_st160_fsm_159 =>
if ((ap_const_lv1_0 = exitcond_fu_1208_p2)) then
ap_NS_fsm <= ap_ST_st161_fsm_160;
else
ap_NS_fsm <= ap_ST_st156_fsm_155;
end if;
when ap_ST_st161_fsm_160 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st160_fsm_159;
else
ap_NS_fsm <= ap_ST_st161_fsm_160;
end if;
when ap_ST_st162_fsm_161 =>
if (not((ap_const_lv1_0 = tmp_8_fu_1233_p2))) then
ap_NS_fsm <= ap_ST_st163_fsm_162;
else
ap_NS_fsm <= ap_ST_st156_fsm_155;
end if;
when ap_ST_st163_fsm_162 =>
if (not((ap_const_lv1_0 = exitcond2_fu_1310_p2))) then
ap_NS_fsm <= ap_ST_st162_fsm_161;
else
ap_NS_fsm <= ap_ST_st164_fsm_163;
end if;
when ap_ST_st164_fsm_163 =>
if (((ap_const_lv1_0 = exitcond8_fu_1368_p2) and not(ap_sig_bdd_719))) then
ap_NS_fsm <= ap_ST_st164_fsm_163;
elsif ((not(ap_sig_bdd_719) and not((ap_const_lv1_0 = exitcond8_fu_1368_p2)))) then
ap_NS_fsm <= ap_ST_st163_fsm_162;
else
ap_NS_fsm <= ap_ST_st164_fsm_163;
end if;
when ap_ST_st165_fsm_164 =>
if (((ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733))) then
ap_NS_fsm <= ap_ST_st165_fsm_164;
elsif ((not(ap_sig_bdd_733) and not((ap_const_lv1_0 = exitcond7_fu_1379_p2)))) then
ap_NS_fsm <= ap_ST_st156_fsm_155;
else
ap_NS_fsm <= ap_ST_st165_fsm_164;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st164_fsm_163, exitcond8_fu_1368_p2, ap_sig_bdd_719)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and (ap_const_lv1_0 = exitcond8_fu_1368_p2) and not(ap_sig_bdd_719))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_V_TREADY assign process. --
P_config_V_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_589_p2, ap_sig_bdd_411, exitcond7_fu_1379_p2, ap_sig_cseq_ST_st165_fsm_164, ap_sig_bdd_733)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_589_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_411)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond7_fu_1379_p2) and not(ap_sig_bdd_733)))) then
P_config_V_TREADY <= ap_const_logic_1;
else
P_config_V_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_611_p2, ap_sig_bdd_441)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_611_p2) and not(ap_sig_bdd_441))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_V_TDATA <= p_s_reg_401;
-- P_netOut_V_TVALID assign process. --
P_netOut_V_TVALID_assign_proc : process(tmp_reg_1423, tmp_1_reg_1435, tmp_35_reg_1637, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1040_p2, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY))) then
P_netOut_V_TVALID <= ap_const_logic_1;
else
P_netOut_V_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st161_fsm_160, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond3_fu_805_p2, ap_sig_cseq_ST_st80_fsm_79, exitcond4_fu_958_p2, ap_sig_cseq_ST_st164_fsm_163, tmp_73_cast_fu_829_p1, tmp_72_cast_fu_852_p1, tmp_76_cast_fu_982_p1, tmp_75_cast_fu_1005_p1, tmp_63_cast_fu_1363_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163)) then
ST_WandB_address0 <= tmp_63_cast_fu_1363_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and not((ap_const_lv1_0 = exitcond4_fu_958_p2)))) then
ST_WandB_address0 <= tmp_75_cast_fu_1005_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and (ap_const_lv1_0 = exitcond4_fu_958_p2))) then
ST_WandB_address0 <= tmp_76_cast_fu_982_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond3_fu_805_p2)))) then
ST_WandB_address0 <= tmp_72_cast_fu_852_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond3_fu_805_p2))) then
ST_WandB_address0 <= tmp_73_cast_fu_829_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond3_fu_805_p2, ap_sig_cseq_ST_st80_fsm_79, exitcond4_fu_958_p2, ap_sig_cseq_ST_st164_fsm_163, ap_sig_bdd_719)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond3_fu_805_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond3_fu_805_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and (ap_const_lv1_0 = exitcond4_fu_958_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and not((ap_const_lv1_0 = exitcond4_fu_958_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and not(ap_sig_bdd_719)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st164_fsm_163, exitcond8_fu_1368_p2, ap_sig_bdd_719)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and (ap_const_lv1_0 = exitcond8_fu_1368_p2) and not(ap_sig_bdd_719)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
ST_layerSize_V_load_1_phi_fu_1272_p3 <=
ST_layerSize_V_2 when (sel_tmp2_fu_1266_p2(0) = '1') else
sel_tmp1_fu_1258_p3;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_1423, tmp_1_reg_1435, tmp_35_reg_1637, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1040_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond6_fu_1083_p2, tmp_8_reg_1711, exitcond7_reg_1756)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2)) or (not((ap_const_lv1_0 = tmp_reg_1423)) and not((ap_const_lv1_0 = exitcond7_reg_1756))) or ((ap_const_lv1_0 = tmp_reg_1423) and not((ap_const_lv1_0 = tmp_1_reg_1435)) and (ap_const_lv1_0 = tmp_8_reg_1711)) or ((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not((ap_const_lv1_0 = tmp_35_reg_1637)) and not((ap_const_lv1_0 = exitcond6_fu_1083_p2)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_1423, tmp_1_reg_1435, tmp_35_reg_1637, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1040_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond6_fu_1083_p2, tmp_8_reg_1711, exitcond7_reg_1756)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and (((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2)) or (not((ap_const_lv1_0 = tmp_reg_1423)) and not((ap_const_lv1_0 = exitcond7_reg_1756))) or ((ap_const_lv1_0 = tmp_reg_1423) and not((ap_const_lv1_0 = tmp_1_reg_1435)) and (ap_const_lv1_0 = tmp_8_reg_1711)) or ((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and not((ap_const_lv1_0 = tmp_35_reg_1637)) and not((ap_const_lv1_0 = exitcond6_fu_1083_p2)))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1010 assign process. --
ap_sig_bdd_1010_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1010 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_1017 assign process. --
ap_sig_bdd_1017_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1017 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_1027 assign process. --
ap_sig_bdd_1027_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1027 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_183 assign process. --
ap_sig_bdd_183_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_183 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_265 assign process. --
ap_sig_bdd_265_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_265 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_272 assign process. --
ap_sig_bdd_272_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_272 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_280 assign process. --
ap_sig_bdd_280_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_280 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_288 assign process. --
ap_sig_bdd_288_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_288 <= (ap_const_lv1_1 = ap_CS_fsm(156 downto 156));
end process;
-- ap_sig_bdd_297 assign process. --
ap_sig_bdd_297_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_297 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_306 assign process. --
ap_sig_bdd_306_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_306 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_316 assign process. --
ap_sig_bdd_316_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_316 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_323 assign process. --
ap_sig_bdd_323_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_323 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_333 assign process. --
ap_sig_bdd_333_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_333 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_340 assign process. --
ap_sig_bdd_340_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_340 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_349 assign process. --
ap_sig_bdd_349_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_349 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_356 assign process. --
ap_sig_bdd_356_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_356 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_364 assign process. --
ap_sig_bdd_364_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_364 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_374 assign process. --
ap_sig_bdd_374_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_374 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_381 assign process. --
ap_sig_bdd_381_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_381 <= (ap_const_lv1_1 = ap_CS_fsm(115 downto 115));
end process;
-- ap_sig_bdd_391 assign process. --
ap_sig_bdd_391_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_391 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_398 assign process. --
ap_sig_bdd_398_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_398 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_411 assign process. --
ap_sig_bdd_411_assign_proc : process(ap_start, P_config_V_TVALID, tmp_fu_589_p2)
begin
ap_sig_bdd_411 <= (((P_config_V_TVALID = ap_const_logic_0) and not((tmp_fu_589_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_435 assign process. --
ap_sig_bdd_435_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_435 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_441 assign process. --
ap_sig_bdd_441_assign_proc : process(P_netIn_TVALID, exitcond1_fu_611_p2)
begin
ap_sig_bdd_441 <= ((P_netIn_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond1_fu_611_p2));
end process;
-- ap_sig_bdd_451 assign process. --
ap_sig_bdd_451_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_451 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_481 assign process. --
ap_sig_bdd_481_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_481 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_503 assign process. --
ap_sig_bdd_503_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_503 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_523 assign process. --
ap_sig_bdd_523_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_523 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_532 assign process. --
ap_sig_bdd_532_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_532 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_553 assign process. --
ap_sig_bdd_553_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_553 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_572 assign process. --
ap_sig_bdd_572_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_572 <= (ap_const_lv1_1 = ap_CS_fsm(120 downto 120));
end process;
-- ap_sig_bdd_581 assign process. --
ap_sig_bdd_581_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_581 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_599 assign process. --
ap_sig_bdd_599_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_599 <= (ap_const_lv1_1 = ap_CS_fsm(155 downto 155));
end process;
-- ap_sig_bdd_643 assign process. --
ap_sig_bdd_643_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_643 <= (ap_const_lv1_1 = ap_CS_fsm(157 downto 157));
end process;
-- ap_sig_bdd_652 assign process. --
ap_sig_bdd_652_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_652 <= (ap_const_lv1_1 = ap_CS_fsm(158 downto 158));
end process;
-- ap_sig_bdd_663 assign process. --
ap_sig_bdd_663_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_663 <= (ap_const_lv1_1 = ap_CS_fsm(159 downto 159));
end process;
-- ap_sig_bdd_677 assign process. --
ap_sig_bdd_677_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_677 <= (ap_const_lv1_1 = ap_CS_fsm(161 downto 161));
end process;
-- ap_sig_bdd_695 assign process. --
ap_sig_bdd_695_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_695 <= (ap_const_lv1_1 = ap_CS_fsm(162 downto 162));
end process;
-- ap_sig_bdd_713 assign process. --
ap_sig_bdd_713_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_713 <= (ap_const_lv1_1 = ap_CS_fsm(163 downto 163));
end process;
-- ap_sig_bdd_719 assign process. --
ap_sig_bdd_719_assign_proc : process(P_WandB_TVALID, exitcond8_fu_1368_p2)
begin
ap_sig_bdd_719 <= ((P_WandB_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond8_fu_1368_p2));
end process;
-- ap_sig_bdd_729 assign process. --
ap_sig_bdd_729_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_729 <= (ap_const_lv1_1 = ap_CS_fsm(164 downto 164));
end process;
-- ap_sig_bdd_733 assign process. --
ap_sig_bdd_733_assign_proc : process(P_config_V_TVALID, exitcond7_fu_1379_p2)
begin
ap_sig_bdd_733 <= ((P_config_V_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond7_fu_1379_p2));
end process;
-- ap_sig_bdd_764 assign process. --
ap_sig_bdd_764_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_764 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_786 assign process. --
ap_sig_bdd_786_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_786 <= (ap_const_lv1_1 = ap_CS_fsm(154 downto 154));
end process;
-- ap_sig_bdd_813 assign process. --
ap_sig_bdd_813_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_813 <= (ap_const_lv1_1 = ap_CS_fsm(160 downto 160));
end process;
-- ap_sig_bdd_906 assign process. --
ap_sig_bdd_906_assign_proc : process(tmp_reg_1423, tmp_1_reg_1435, tmp_35_reg_1637, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1040_p2)
begin
ap_sig_bdd_906 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2));
end process;
-- ap_sig_bdd_927 assign process. --
ap_sig_bdd_927_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_927 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_952 assign process. --
ap_sig_bdd_952_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_952 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_959 assign process. --
ap_sig_bdd_959_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_959 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_967 assign process. --
ap_sig_bdd_967_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_967 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_974 assign process. --
ap_sig_bdd_974_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_974 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_981 assign process. --
ap_sig_bdd_981_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_981 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_cseq_ST_st116_fsm_115 assign process. --
ap_sig_cseq_ST_st116_fsm_115_assign_proc : process(ap_sig_bdd_381)
begin
if (ap_sig_bdd_381) then
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_927)
begin
if (ap_sig_bdd_927) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_120 assign process. --
ap_sig_cseq_ST_st121_fsm_120_assign_proc : process(ap_sig_bdd_572)
begin
if (ap_sig_bdd_572) then
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_581)
begin
if (ap_sig_bdd_581) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_280)
begin
if (ap_sig_bdd_280) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_1017)
begin
if (ap_sig_bdd_1017) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_316)
begin
if (ap_sig_bdd_316) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_952)
begin
if (ap_sig_bdd_952) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_398)
begin
if (ap_sig_bdd_398) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st155_fsm_154 assign process. --
ap_sig_cseq_ST_st155_fsm_154_assign_proc : process(ap_sig_bdd_786)
begin
if (ap_sig_bdd_786) then
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st156_fsm_155 assign process. --
ap_sig_cseq_ST_st156_fsm_155_assign_proc : process(ap_sig_bdd_599)
begin
if (ap_sig_bdd_599) then
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st157_fsm_156 assign process. --
ap_sig_cseq_ST_st157_fsm_156_assign_proc : process(ap_sig_bdd_288)
begin
if (ap_sig_bdd_288) then
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st158_fsm_157 assign process. --
ap_sig_cseq_ST_st158_fsm_157_assign_proc : process(ap_sig_bdd_643)
begin
if (ap_sig_bdd_643) then
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st159_fsm_158 assign process. --
ap_sig_cseq_ST_st159_fsm_158_assign_proc : process(ap_sig_bdd_652)
begin
if (ap_sig_bdd_652) then
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st160_fsm_159 assign process. --
ap_sig_cseq_ST_st160_fsm_159_assign_proc : process(ap_sig_bdd_663)
begin
if (ap_sig_bdd_663) then
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st161_fsm_160 assign process. --
ap_sig_cseq_ST_st161_fsm_160_assign_proc : process(ap_sig_bdd_813)
begin
if (ap_sig_bdd_813) then
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st162_fsm_161 assign process. --
ap_sig_cseq_ST_st162_fsm_161_assign_proc : process(ap_sig_bdd_677)
begin
if (ap_sig_bdd_677) then
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st163_fsm_162 assign process. --
ap_sig_cseq_ST_st163_fsm_162_assign_proc : process(ap_sig_bdd_695)
begin
if (ap_sig_bdd_695) then
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st164_fsm_163 assign process. --
ap_sig_cseq_ST_st164_fsm_163_assign_proc : process(ap_sig_bdd_713)
begin
if (ap_sig_bdd_713) then
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st165_fsm_164 assign process. --
ap_sig_cseq_ST_st165_fsm_164_assign_proc : process(ap_sig_bdd_729)
begin
if (ap_sig_bdd_729) then
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_333)
begin
if (ap_sig_bdd_333) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_297)
begin
if (ap_sig_bdd_297) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_959)
begin
if (ap_sig_bdd_959) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_183)
begin
if (ap_sig_bdd_183) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_349)
begin
if (ap_sig_bdd_349) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_523)
begin
if (ap_sig_bdd_523) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_435)
begin
if (ap_sig_bdd_435) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_451)
begin
if (ap_sig_bdd_451) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_374)
begin
if (ap_sig_bdd_374) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_967)
begin
if (ap_sig_bdd_967) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_356)
begin
if (ap_sig_bdd_356) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_1010)
begin
if (ap_sig_bdd_1010) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_481)
begin
if (ap_sig_bdd_481) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_503)
begin
if (ap_sig_bdd_503) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_265)
begin
if (ap_sig_bdd_265) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_391)
begin
if (ap_sig_bdd_391) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_764)
begin
if (ap_sig_bdd_764) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_532)
begin
if (ap_sig_bdd_532) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_553)
begin
if (ap_sig_bdd_553) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_272)
begin
if (ap_sig_bdd_272) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_323)
begin
if (ap_sig_bdd_323) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_974)
begin
if (ap_sig_bdd_974) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_340)
begin
if (ap_sig_bdd_340) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_306)
begin
if (ap_sig_bdd_306) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_981)
begin
if (ap_sig_bdd_981) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_364)
begin
if (ap_sig_bdd_364) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_1027)
begin
if (ap_sig_bdd_1027) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_V_TREADY assign process. --
ap_sig_ioackin_P_netOut_V_TREADY_assign_proc : process(P_netOut_V_TREADY, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY)) then
ap_sig_ioackin_P_netOut_V_TREADY <= P_netOut_V_TREADY;
else
ap_sig_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
exitcond1_fu_611_p2 <= "1" when (i_2_reg_287 = ST_layerSize_V_0_load_reg_1439) else "0";
exitcond2_fu_1310_p2 <= "1" when (j_reg_471 = ST_layerSize_V_load_1_phi_reg_1720) else "0";
exitcond3_fu_805_p2 <= "1" when (k_1_reg_333 = tmp_20_reg_1515) else "0";
exitcond4_fu_958_p2 <= "1" when (j_2_reg_379 = tmp_22_reg_1579) else "0";
exitcond5_fu_1010_p2 <= "1" when (i_5_reg_390 = tmp_17_reg_1565) else "0";
exitcond6_fu_1083_p2 <= "1" when (i_6_reg_426 = ST_numLayer_V_load_reg_1427) else "0";
exitcond7_fu_1379_p2 <= "1" when (i_reg_493 = P_config_V_read_reg_1444) else "0";
exitcond8_fu_1368_p2 <= "1" when (k_reg_482 = tmp_10_reg_1725) else "0";
exitcond_fu_1208_p2 <= "1" when (j_3_reg_448 = tmp_40_reg_1672) else "0";
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_504_ce <= ap_const_logic_1;
-- grp_fu_504_p0 assign process. --
grp_fu_504_p0_assign_proc : process(reg_577, sum_reg_321, sumsoft_reg_344, sum_1_reg_367, ap_sig_cseq_ST_st117_fsm_116, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st42_fsm_41, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
grp_fu_504_p0 <= sumsoft_reg_344;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_504_p0 <= sum_1_reg_367;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) then
grp_fu_504_p0 <= reg_577;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
grp_fu_504_p0 <= sum_reg_321;
else
grp_fu_504_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_504_p1 assign process. --
grp_fu_504_p1_assign_proc : process(reg_554, reg_560, reg_577, ap_sig_cseq_ST_st117_fsm_116, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st42_fsm_41, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
grp_fu_504_p1 <= reg_577;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) then
grp_fu_504_p1 <= ap_const_lv64_3FF0000000000000;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_504_p1 <= reg_554;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
grp_fu_504_p1 <= reg_560;
else
grp_fu_504_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_512_ce <= ap_const_logic_1;
grp_fu_516_ce <= ap_const_logic_1;
-- grp_fu_516_p0 assign process. --
grp_fu_516_p0_assign_proc : process(reg_547, ap_sig_cseq_ST_st47_fsm_46, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_516_p0 <= reg_547;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) then
grp_fu_516_p0 <= ap_const_lv64_3FF0000000000000;
else
grp_fu_516_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_516_p1 assign process. --
grp_fu_516_p1_assign_proc : process(reg_571, sumsoft_reg_344, ap_sig_cseq_ST_st47_fsm_46, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_516_p1 <= sumsoft_reg_344;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) then
grp_fu_516_p1 <= reg_571;
else
grp_fu_516_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_526_ce <= ap_const_logic_1;
-- grp_fu_526_p1 assign process. --
grp_fu_526_p1_assign_proc : process(reg_571, tmp_25_fu_867_p1, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st99_fsm_98)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) then
grp_fu_526_p1 <= reg_571;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
grp_fu_526_p1 <= tmp_25_fu_867_p1;
else
grp_fu_526_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_10_fu_799_p2 <= std_logic_vector(unsigned(i_3_reg_298) + unsigned(ap_const_lv8_1));
i_11_fu_1015_p2 <= std_logic_vector(unsigned(i_5_reg_390) + unsigned(ap_const_lv8_1));
i_12_fu_895_p2 <= std_logic_vector(unsigned(i_4_reg_356) + unsigned(ap_const_lv32_1));
i_14_fu_1088_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(i_6_reg_426));
i_15_fu_1202_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(p_netOut_V_reg_414));
i_7_fu_1384_p2 <= std_logic_vector(unsigned(i_reg_493) + unsigned(ap_const_lv8_1));
i_8_fu_616_p2 <= std_logic_vector(unsigned(i_2_reg_287) + unsigned(ap_const_lv8_1));
i_9_fu_1348_p2 <= std_logic_vector(unsigned(i_1_reg_459) + unsigned(ap_const_lv8_1));
j_4_fu_1315_p2 <= std_logic_vector(unsigned(j_reg_471) + unsigned(ap_const_lv8_1));
j_5_fu_740_p2 <= std_logic_vector(unsigned(j_1_reg_310) + unsigned(ap_const_lv32_1));
j_6_fu_963_p2 <= std_logic_vector(unsigned(j_2_reg_379) + unsigned(ap_const_lv8_1));
j_7_fu_1213_p2 <= std_logic_vector(unsigned(j_3_reg_448) + unsigned(ap_const_lv8_1));
k_2_fu_1373_p2 <= std_logic_vector(unsigned(k_reg_482) + unsigned(ap_const_lv9_1));
k_3_fu_810_p2 <= std_logic_vector(unsigned(k_1_reg_333) + unsigned(ap_const_lv8_1));
lhs_V_1_cast_fu_670_p1 <= std_logic_vector(resize(unsigned(ST_numLayer_V_load_reg_1427),9));
next_mul_fu_1077_p2 <= std_logic_vector(unsigned(ap_const_lv14_23) + unsigned(phi_mul_reg_437));
notlhs1_fu_1165_p2 <= "0" when (tmp_45_fu_1133_p4 = ap_const_lv11_7FF) else "1";
notlhs_fu_1147_p2 <= "0" when (tmp_43_fu_1116_p4 = ap_const_lv11_7FF) else "1";
notrhs1_fu_1171_p2 <= "1" when (tmp_71_fu_1143_p1 = ap_const_lv52_0) else "0";
notrhs_fu_1153_p2 <= "1" when (tmp_70_fu_1126_p1 = ap_const_lv52_0) else "0";
p_netOut_V_1_fu_1195_p3 <=
p_netOut_V_reg_414 when (tmp_51_reg_1683(0) = '1') else
p_s_reg_401;
p_shl1_cast_fu_773_p3 <= (tmp_52_fu_769_p1 & ap_const_lv5_0);
p_shl2_cast_fu_785_p3 <= (tmp_53_fu_781_p1 & ap_const_lv2_0);
p_shl3_cast_fu_932_p3 <= (tmp_56_fu_928_p1 & ap_const_lv5_0);
p_shl4_cast_fu_944_p3 <= (tmp_57_fu_940_p1 & ap_const_lv2_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_1_reg_1527, ap_sig_cseq_ST_st5_fsm_4, p_uOut_addr_3_reg_1591, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st122_fsm_121, p_uOut_addr_5_reg_1632, ap_sig_cseq_ST_st156_fsm_155, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, tmp_6_fu_622_p1, tmp_74_cast_fu_839_p1, tmp_77_cast_fu_992_p1, tmp_78_cast_fu_1030_p1, tmp_80_cast_fu_1054_p1, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1632;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
p_uOut_address0 <= p_uOut_addr_3_reg_1591;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
p_uOut_address0 <= p_uOut_addr_1_reg_1527;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_6_fu_622_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) then
p_uOut_address0 <= tmp_80_cast_fu_1054_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
p_uOut_address0 <= tmp_78_cast_fu_1030_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
p_uOut_address0 <= tmp_77_cast_fu_992_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
p_uOut_address0 <= tmp_74_cast_fu_839_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st156_fsm_155, ap_sig_cseq_ST_st160_fsm_159, tmp_81_cast_fu_1068_p1, tmp_82_cast_fu_1228_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) then
p_uOut_address1 <= tmp_82_cast_fu_1228_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) then
p_uOut_address1 <= tmp_81_cast_fu_1068_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(tmp_reg_1423, tmp_1_reg_1435, ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_441, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st122_fsm_121, tmp_35_reg_1637, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1040_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_441)) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) or ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(tmp_reg_1423, tmp_1_reg_1435, tmp_35_reg_1637, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1040_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st160_fsm_159)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and not(((ap_const_lv1_0 = tmp_reg_1423) and (ap_const_lv1_0 = tmp_1_reg_1435) and (ap_const_lv1_0 = tmp_35_reg_1637) and (ap_const_lv1_0 = tmp_38_fu_1040_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_577, reg_584, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
p_uOut_d0 <= reg_577;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154))) then
p_uOut_d0 <= reg_584;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1112_p1 <= reg_547;
p_uOut_load_4_to_int_fu_1130_p1 <= p_uOut_load_4_reg_1677;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_611_p2, ap_sig_bdd_441, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_611_p2) and not(ap_sig_bdd_441)) or (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
r_V_1_fu_701_p2 <= std_logic_vector(signed(ap_const_lv9_1FE) + signed(lhs_V_1_cast_fu_670_p1));
r_V_fu_673_p2 <= std_logic_vector(signed(ap_const_lv9_1FF) + signed(lhs_V_1_cast_fu_670_p1));
sel_tmp1_fu_1258_p3 <=
ST_layerSize_V_1 when (sel_tmp_fu_1252_p2(0) = '1') else
ST_layerSize_V_3;
sel_tmp2_fu_1266_p2 <= "1" when (tmp_5_fu_1248_p1 = ap_const_lv2_2) else "0";
sel_tmp_fu_1252_p2 <= "1" when (tmp_5_fu_1248_p1 = ap_const_lv2_1) else "0";
tmp_10_fu_1304_p2 <= std_logic_vector(unsigned(ap_const_lv9_1) + unsigned(tmp_9_fu_1300_p1));
tmp_11_fu_1325_p2 <= std_logic_vector(unsigned(tmp_cast_fu_1321_p1) + unsigned(tmp_s_reg_1715));
tmp_12_cast_fu_1354_p1 <= std_logic_vector(resize(unsigned(k_reg_482),14));
tmp_12_fu_1330_p2 <= std_logic_vector(shift_left(unsigned(tmp_11_fu_1325_p2),to_integer(unsigned('0' & ap_const_lv14_5(14-1 downto 0)))));
tmp_13_fu_1336_p2 <= std_logic_vector(shift_left(unsigned(tmp_11_fu_1325_p2),to_integer(unsigned('0' & ap_const_lv14_2(14-1 downto 0)))));
tmp_15_fu_730_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_717_p6),32));
tmp_16_fu_734_p2 <= "1" when (signed(j_1_reg_310) < signed(tmp_15_fu_730_p1)) else "0";
tmp_18_fu_885_p1 <= std_logic_vector(resize(unsigned(tmp_17_fu_872_p6),32));
tmp_19_fu_889_p2 <= "1" when (signed(i_4_reg_356) < signed(tmp_18_fu_885_p1)) else "0";
tmp_1_fu_599_p2 <= "1" when (P_mode_V = ap_const_lv8_2) else "0";
tmp_21_fu_1342_p2 <= std_logic_vector(unsigned(tmp_12_fu_1330_p2) + unsigned(tmp_13_fu_1336_p2));
tmp_23_cast_fu_914_p1 <= std_logic_vector(resize(signed(i_4_reg_356),33));
tmp_23_fu_636_p1 <= tmp_23_fu_636_p10(8 - 1 downto 0);
tmp_23_fu_636_p10 <= std_logic_vector(resize(unsigned(i_3_reg_298),15));
tmp_23_fu_636_p2 <= std_logic_vector(resize(unsigned(ap_const_lv15_23) * unsigned(tmp_23_fu_636_p1), 15));
tmp_24_cast_fu_844_p1 <= std_logic_vector(resize(unsigned(tmp_20_reg_1515),14));
tmp_24_fu_646_p1 <= i_3_reg_298(2 - 1 downto 0);
tmp_25_fu_867_p1 <= tmp_38_neg_fu_861_p2;
tmp_29_cast1_fu_816_p1 <= std_logic_vector(resize(unsigned(k_1_reg_333),9));
tmp_29_cast_fu_820_p1 <= std_logic_vector(resize(unsigned(k_1_reg_333),14));
tmp_29_fu_660_p1 <= tmp_29_fu_660_p10(8 - 1 downto 0);
tmp_29_fu_660_p10 <= std_logic_vector(resize(unsigned(tmp_4_fu_650_p2),9));
tmp_29_fu_660_p2 <= std_logic_vector(resize(unsigned(ap_const_lv9_23) * unsigned(tmp_29_fu_660_p1), 9));
tmp_2_fu_1286_p5 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_5_fu_1248_p1));
tmp_31_cast_fu_997_p1 <= std_logic_vector(resize(unsigned(tmp_22_reg_1579),14));
tmp_31_fu_666_p1 <= tmp_4_fu_650_p2(2 - 1 downto 0);
tmp_33_cast1_fu_969_p1 <= std_logic_vector(resize(unsigned(j_2_reg_379),9));
tmp_33_cast_fu_973_p1 <= std_logic_vector(resize(unsigned(j_2_reg_379),14));
tmp_33_fu_683_p1 <= r_V_fu_673_p2;
tmp_33_fu_683_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv16_23) * signed(tmp_33_fu_683_p1))), 16));
tmp_35_fu_1035_p2 <= "1" when (P_mode_V_read_reg_1418 = ap_const_lv8_3) else "0";
tmp_36_cast_fu_1021_p1 <= std_logic_vector(resize(unsigned(i_5_reg_390),9));
tmp_36_fu_689_p1 <= tmp_33_fu_683_p2(9 - 1 downto 0);
tmp_38_fu_1040_p2 <= "1" when (unsigned(p_netOut_V_reg_414) < unsigned(tmp_17_reg_1565)) else "0";
tmp_38_neg_fu_861_p2 <= (tmp_38_to_int_fu_857_p1 xor ap_const_lv64_8000000000000000);
tmp_38_to_int_fu_857_p1 <= reg_571;
tmp_39_fu_697_p1 <= r_V_fu_673_p2(2 - 1 downto 0);
tmp_3_fu_1390_p1 <= i_reg_493(2 - 1 downto 0);
tmp_40_fu_1098_p5 <= i_6_reg_426(2 - 1 downto 0);
tmp_41_cast_fu_1045_p1 <= std_logic_vector(resize(unsigned(p_netOut_V_reg_414),9));
tmp_41_fu_707_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(r_V_1_fu_701_p2))), 9));
tmp_42_cast_fu_1059_p1 <= std_logic_vector(resize(unsigned(p_s_reg_401),9));
tmp_42_fu_713_p1 <= r_V_1_fu_701_p2(2 - 1 downto 0);
tmp_43_fu_1116_p4 <= p_uOut_load_3_to_int_fu_1112_p1(62 downto 52);
tmp_44_fu_1358_p2 <= std_logic_vector(unsigned(tmp_21_reg_1738) + unsigned(tmp_12_cast_fu_1354_p1));
tmp_45_fu_1133_p4 <= p_uOut_load_4_to_int_fu_1130_p1(62 downto 52);
tmp_46_fu_759_p2 <= std_logic_vector(unsigned(j_1_reg_310) + unsigned(tmp_59_cast_reg_1460));
tmp_47_fu_1159_p2 <= (notrhs_fu_1153_p2 or notlhs_fu_1147_p2);
tmp_48_fu_1177_p2 <= (notrhs1_fu_1171_p2 or notlhs1_fu_1165_p2);
tmp_49_fu_1183_p2 <= (tmp_47_fu_1159_p2 and tmp_48_fu_1177_p2);
tmp_4_fu_650_p2 <= std_logic_vector(signed(ap_const_lv8_FF) + signed(i_3_reg_298));
tmp_50_fu_522_opcode <= ap_const_lv5_2;
tmp_51_fu_1189_p2 <= (tmp_49_fu_1183_p2 and tmp_50_fu_522_p2);
tmp_52_cast_fu_1219_p1 <= std_logic_vector(resize(unsigned(j_3_reg_448),9));
tmp_52_fu_769_p1 <= tmp_46_fu_759_p2(9 - 1 downto 0);
tmp_53_fu_781_p1 <= tmp_46_fu_759_p2(12 - 1 downto 0);
tmp_54_fu_793_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_773_p3) + unsigned(p_shl2_cast_fu_785_p3));
tmp_55_fu_918_p2 <= std_logic_vector(signed(tmp_23_cast_fu_914_p1) + signed(tmp_61_cast_reg_1487));
tmp_56_fu_928_p1 <= tmp_55_fu_918_p2(9 - 1 downto 0);
tmp_57_fu_940_p1 <= tmp_55_fu_918_p2(12 - 1 downto 0);
tmp_58_fu_952_p2 <= std_logic_vector(unsigned(p_shl3_cast_fu_932_p3) + unsigned(p_shl4_cast_fu_944_p3));
tmp_59_cast_fu_642_p1 <= std_logic_vector(resize(unsigned(tmp_23_fu_636_p2),32));
tmp_59_fu_1025_p2 <= std_logic_vector(unsigned(tmp_36_reg_1480) + unsigned(tmp_36_cast_fu_1021_p1));
tmp_5_fu_1248_p1 <= i_1_reg_459(2 - 1 downto 0);
tmp_60_fu_847_p2 <= std_logic_vector(unsigned(tmp_54_reg_1521) + unsigned(tmp_24_cast_fu_844_p1));
tmp_61_cast_fu_693_p1 <= std_logic_vector(resize(signed(tmp_33_fu_683_p2),33));
tmp_61_fu_824_p2 <= std_logic_vector(unsigned(tmp_54_reg_1521) + unsigned(tmp_29_cast_fu_820_p1));
tmp_62_fu_834_p2 <= std_logic_vector(unsigned(tmp_29_reg_1470) + unsigned(tmp_29_cast1_fu_816_p1));
tmp_63_cast_fu_1363_p1 <= std_logic_vector(resize(unsigned(tmp_44_fu_1358_p2),64));
tmp_63_fu_1000_p2 <= std_logic_vector(unsigned(tmp_58_reg_1585) + unsigned(tmp_31_cast_fu_997_p1));
tmp_64_cast_fu_764_p1 <= std_logic_vector(resize(signed(tmp_46_fu_759_p2),64));
tmp_64_fu_977_p2 <= std_logic_vector(unsigned(tmp_58_reg_1585) + unsigned(tmp_33_cast_fu_973_p1));
tmp_65_fu_987_p2 <= std_logic_vector(unsigned(tmp_41_reg_1497) + unsigned(tmp_33_cast1_fu_969_p1));
tmp_66_fu_1073_p1 <= phi_mul_reg_437(9 - 1 downto 0);
tmp_68_cast_fu_923_p1 <= std_logic_vector(resize(signed(tmp_55_fu_918_p2),64));
tmp_68_fu_1049_p2 <= std_logic_vector(unsigned(tmp_36_reg_1480) + unsigned(tmp_41_cast_fu_1045_p1));
tmp_69_fu_1063_p2 <= std_logic_vector(unsigned(tmp_36_reg_1480) + unsigned(tmp_42_cast_fu_1059_p1));
tmp_6_fu_622_p1 <= std_logic_vector(resize(unsigned(i_2_reg_287),64));
tmp_70_fu_1126_p1 <= p_uOut_load_3_to_int_fu_1112_p1(52 - 1 downto 0);
tmp_71_fu_1143_p1 <= p_uOut_load_4_to_int_fu_1130_p1(52 - 1 downto 0);
tmp_72_cast_fu_852_p1 <= std_logic_vector(resize(unsigned(tmp_60_fu_847_p2),64));
tmp_72_fu_1223_p2 <= std_logic_vector(unsigned(tmp_66_reg_1654) + unsigned(tmp_52_cast_fu_1219_p1));
tmp_73_cast_fu_829_p1 <= std_logic_vector(resize(unsigned(tmp_61_fu_824_p2),64));
tmp_74_cast_fu_839_p1 <= std_logic_vector(resize(signed(tmp_62_fu_834_p2),64));
tmp_75_cast_fu_1005_p1 <= std_logic_vector(resize(unsigned(tmp_63_fu_1000_p2),64));
tmp_76_cast_fu_982_p1 <= std_logic_vector(resize(unsigned(tmp_64_fu_977_p2),64));
tmp_77_cast_fu_992_p1 <= std_logic_vector(resize(signed(tmp_65_fu_987_p2),64));
tmp_78_cast_fu_1030_p1 <= std_logic_vector(resize(signed(tmp_59_fu_1025_p2),64));
tmp_7_fu_627_p2 <= "1" when (unsigned(i_3_reg_298) < unsigned(ST_numLayer_V_load_reg_1427)) else "0";
tmp_80_cast_fu_1054_p1 <= std_logic_vector(resize(signed(tmp_68_fu_1049_p2),64));
tmp_81_cast_fu_1068_p1 <= std_logic_vector(resize(signed(tmp_69_fu_1063_p2),64));
tmp_82_cast_fu_1228_p1 <= std_logic_vector(resize(unsigned(tmp_72_fu_1223_p2),64));
tmp_8_fu_1233_p2 <= "1" when (unsigned(i_1_reg_459) < unsigned(ST_numLayer_V_load_reg_1427)) else "0";
tmp_9_fu_1300_p1 <= std_logic_vector(resize(unsigned(tmp_2_fu_1286_p6),9));
tmp_cast_fu_1321_p1 <= std_logic_vector(resize(unsigned(j_reg_471),14));
tmp_fu_589_p2 <= "1" when (P_mode_V = ap_const_lv8_1) else "0";
tmp_s_fu_1242_p1 <= tmp_s_fu_1242_p10(8 - 1 downto 0);
tmp_s_fu_1242_p10 <= std_logic_vector(resize(unsigned(i_1_reg_459),14));
tmp_s_fu_1242_p2 <= std_logic_vector(resize(unsigned(ap_const_lv14_23) * unsigned(tmp_s_fu_1242_p1), 14));
end behav;
|
gpl-3.0
|
89cf8c62de359c45589587341ff29242
| 0.641743 | 3.239904 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd
| 4 | 33,317 |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_3;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_9;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_3.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_9.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
gpl-3.0
|
759af2a519b431b6ac2a5e1ba6c7d659
| 0.471231 | 3.871819 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/sim_tbs/AESL_axi_slave_AXILiteS.vhd
| 1 | 96,316 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_slave_AXILiteS is
generic (
constant TV_IN_P_mode : STRING (1 to 27) := "./c.ANN.autotvin_P_mode.dat";
constant TV_IN_P_index1 : STRING (1 to 29) := "./c.ANN.autotvin_P_index1.dat";
constant TV_IN_P_index2 : STRING (1 to 29) := "./c.ANN.autotvin_P_index2.dat";
constant TV_IN_P_intIn_index3 : STRING (1 to 35) := "./c.ANN.autotvin_P_intIn_index3.dat";
constant TV_IN_P_floatIn : STRING (1 to 30) := "./c.ANN.autotvin_P_floatIn.dat";
constant TV_OUT_ap_return : STRING (1 to 38) := "./impl_rtl.ANN.autotvout_ap_return.dat";
constant ADDR_WIDTH : INTEGER := 7;
constant DATA_WIDTH : INTEGER := 32;
constant P_mode_DEPTH : INTEGER := 1;
constant P_mode_c_bitwidth : INTEGER := 32;
constant P_index1_DEPTH : INTEGER := 1;
constant P_index1_c_bitwidth : INTEGER := 32;
constant P_index2_DEPTH : INTEGER := 1;
constant P_index2_c_bitwidth : INTEGER := 32;
constant P_intIn_index3_DEPTH : INTEGER := 1;
constant P_intIn_index3_c_bitwidth : INTEGER := 32;
constant P_floatIn_DEPTH : INTEGER := 1;
constant P_floatIn_c_bitwidth : INTEGER := 32;
constant ap_return_DEPTH : INTEGER := 1;
constant ap_return_c_bitwidth : INTEGER := 32;
constant START_ADDR : INTEGER := 0;
constant ANN_continue_addr : INTEGER := 0;
constant ANN_auto_start_addr : INTEGER := 0;
constant P_mode_data_in_addr : INTEGER := 24;
constant P_index1_data_in_addr : INTEGER := 32;
constant P_index2_data_in_addr : INTEGER := 40;
constant P_intIn_index3_data_in_addr : INTEGER := 48;
constant P_floatIn_data_in_addr : INTEGER := 56;
constant ap_return_data_out_addr : INTEGER := 16;
constant STATUS_ADDR : INTEGER := 0;
constant INTERFACE_TYPE : STRING (1 to 8) := "AXILiteS"
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_AWADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_WREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WDATA : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_WSTRB : OUT STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0);
TRAN_s_axi_AXILiteS_ARADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_RDATA : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_RRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_s_axi_AXILiteS_BVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_BRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_AXILiteS_write_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_read_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_start_in : IN STD_LOGIC;
TRAN_AXILiteS_done_out : OUT STD_LOGIC;
TRAN_AXILiteS_ready_out : OUT STD_LOGIC;
TRAN_AXILiteS_ready_in : IN STD_LOGIC;
TRAN_AXILiteS_idle_out : OUT STD_LOGIC;
TRAN_AXILiteS_write_start_in : IN STD_LOGIC;
TRAN_AXILiteS_write_start_finish : OUT STD_LOGIC;
TRAN_AXILiteS_interrupt : IN STD_LOGIC;
TRAN_AXILiteS_transaction_done_in : IN STD_LOGIC
);
end AESL_axi_slave_AXILiteS;
architecture behav of AESL_axi_slave_AXILiteS is
------------------------Local signal-------------------
shared variable P_mode_OPERATE_DEPTH : INTEGER;
shared variable P_index1_OPERATE_DEPTH : INTEGER;
shared variable P_index2_OPERATE_DEPTH : INTEGER;
shared variable P_intIn_index3_OPERATE_DEPTH : INTEGER;
shared variable P_floatIn_OPERATE_DEPTH : INTEGER;
shared variable ap_return_OPERATE_DEPTH : INTEGER;
signal AWADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_2_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_3_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_4_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_5_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_6_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_7_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal AWVALID_reg : STD_LOGIC := '0';
signal process_0_AWVALID_var : STD_LOGIC := '0';
signal process_1_AWVALID_var : STD_LOGIC := '0';
signal process_2_AWVALID_var : STD_LOGIC := '0';
signal process_3_AWVALID_var : STD_LOGIC := '0';
signal process_4_AWVALID_var : STD_LOGIC := '0';
signal process_5_AWVALID_var : STD_LOGIC := '0';
signal process_6_AWVALID_var : STD_LOGIC := '0';
signal process_7_AWVALID_var : STD_LOGIC := '0';
signal WVALID_reg : STD_LOGIC := '0';
signal process_0_WVALID_var : STD_LOGIC := '0';
signal process_1_WVALID_var : STD_LOGIC := '0';
signal process_2_WVALID_var : STD_LOGIC := '0';
signal process_3_WVALID_var : STD_LOGIC := '0';
signal process_4_WVALID_var : STD_LOGIC := '0';
signal process_5_WVALID_var : STD_LOGIC := '0';
signal process_6_WVALID_var : STD_LOGIC := '0';
signal process_7_WVALID_var : STD_LOGIC := '0';
signal WDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_2_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_3_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_4_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_5_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_6_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_7_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal WSTRB_reg : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_0_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_1_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_2_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_3_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_4_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_5_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_6_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_7_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal ARADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_2_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_3_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_4_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_5_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_6_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_7_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal ARVALID_reg : STD_LOGIC := '0';
signal process_0_ARVALID_var : STD_LOGIC := '0';
signal process_1_ARVALID_var : STD_LOGIC := '0';
signal process_2_ARVALID_var : STD_LOGIC := '0';
signal process_3_ARVALID_var : STD_LOGIC := '0';
signal process_4_ARVALID_var : STD_LOGIC := '0';
signal process_5_ARVALID_var : STD_LOGIC := '0';
signal process_6_ARVALID_var : STD_LOGIC := '0';
signal process_7_ARVALID_var : STD_LOGIC := '0';
signal RREADY_reg : STD_LOGIC := '0';
signal process_0_RREADY_var : STD_LOGIC := '0';
signal process_1_RREADY_var : STD_LOGIC := '0';
signal process_2_RREADY_var : STD_LOGIC := '0';
signal process_3_RREADY_var : STD_LOGIC := '0';
signal process_4_RREADY_var : STD_LOGIC := '0';
signal process_5_RREADY_var : STD_LOGIC := '0';
signal process_6_RREADY_var : STD_LOGIC := '0';
signal process_7_RREADY_var : STD_LOGIC := '0';
signal RDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_2_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_3_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_4_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_5_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_6_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_7_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal BREADY_reg : STD_LOGIC := '0';
signal process_0_BREADY_var : STD_LOGIC := '0';
signal process_1_BREADY_var : STD_LOGIC := '0';
signal process_2_BREADY_var : STD_LOGIC := '0';
signal process_3_BREADY_var : STD_LOGIC := '0';
signal process_4_BREADY_var : STD_LOGIC := '0';
signal process_5_BREADY_var : STD_LOGIC := '0';
signal process_6_BREADY_var : STD_LOGIC := '0';
signal process_7_BREADY_var : STD_LOGIC := '0';
type mem_P_mode_arr2D is array(0 to P_mode_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_mode : mem_P_mode_arr2D;
signal P_mode_write_data_finish : STD_LOGIC := '0';
type mem_P_index1_arr2D is array(0 to P_index1_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_index1 : mem_P_index1_arr2D;
signal P_index1_write_data_finish : STD_LOGIC := '0';
type mem_P_index2_arr2D is array(0 to P_index2_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_index2 : mem_P_index2_arr2D;
signal P_index2_write_data_finish : STD_LOGIC := '0';
type mem_P_intIn_index3_arr2D is array(0 to P_intIn_index3_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_intIn_index3 : mem_P_intIn_index3_arr2D;
signal P_intIn_index3_write_data_finish : STD_LOGIC := '0';
type mem_P_floatIn_arr2D is array(0 to P_floatIn_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_floatIn : mem_P_floatIn_arr2D;
signal P_floatIn_write_data_finish : STD_LOGIC := '0';
type mem_ap_return_arr2D is array(0 to ap_return_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_ap_return : mem_ap_return_arr2D;
signal ap_return_read_data_finish : STD_LOGIC := '0';
signal AESL_ready_out_index_reg : STD_LOGIC := '0';
signal AESL_write_start_finish : STD_LOGIC := '0';
signal AESL_ready_reg : STD_LOGIC;
signal ready_initial : STD_LOGIC;
signal AESL_done_index_reg : STD_LOGIC := '0';
signal AESL_idle_index_reg : STD_LOGIC := '0';
signal AESL_auto_restart_index_reg : STD_LOGIC;
signal process_0_finish : STD_LOGIC := '0';
signal process_1_finish : STD_LOGIC := '0';
signal process_2_finish : STD_LOGIC := '0';
signal process_3_finish : STD_LOGIC := '0';
signal process_4_finish : STD_LOGIC := '0';
signal process_5_finish : STD_LOGIC := '0';
signal process_6_finish : STD_LOGIC := '0';
signal process_7_finish : STD_LOGIC := '0';
--write P_mode reg
shared variable write_P_mode_count : INTEGER;
signal write_P_mode_run_flag : STD_LOGIC := '0';
signal write_one_P_mode_data_done : STD_LOGIC := '0';
--write P_index1 reg
shared variable write_P_index1_count : INTEGER;
signal write_P_index1_run_flag : STD_LOGIC := '0';
signal write_one_P_index1_data_done : STD_LOGIC := '0';
--write P_index2 reg
shared variable write_P_index2_count : INTEGER;
signal write_P_index2_run_flag : STD_LOGIC := '0';
signal write_one_P_index2_data_done : STD_LOGIC := '0';
--write P_intIn_index3 reg
shared variable write_P_intIn_index3_count : INTEGER;
signal write_P_intIn_index3_run_flag : STD_LOGIC := '0';
signal write_one_P_intIn_index3_data_done : STD_LOGIC := '0';
--write P_floatIn reg
shared variable write_P_floatIn_count : INTEGER;
signal write_P_floatIn_run_flag : STD_LOGIC := '0';
signal write_one_P_floatIn_data_done : STD_LOGIC := '0';
--read ap_return reg
shared variable read_ap_return_count : INTEGER;
signal read_ap_return_run_flag : STD_LOGIC := '0';
signal read_one_ap_return_data_done : STD_LOGIC := '0';
shared variable write_start_count : INTEGER;
signal write_start_run_flag : STD_LOGIC := '0';
--===================process control=================
signal ongoing_process_number : INTEGER;
-- Process number depends on how much processes needed.
shared variable process_busy : STD_LOGIC := '0';
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
procedure count_c_data_four_byte_num_by_bitwidth (constant bitwidth : IN INTEGER; variable num : OUT INTEGER) is
variable factor : INTEGER;
variable i : INTEGER;
begin
factor := 32;
for i in 1 to 32 loop
if (bitwidth <= factor and bitwidth > factor - 32) then
num := i;
end if;
factor := factor + 32;
end loop;
end procedure;
procedure count_seperate_factor_by_bitwidth(bitwidth : in INTEGER; factor : out INTEGER) is
begin
if (bitwidth <= 8) then
factor := 4;
elsif (bitwidth <= 16 and bitwidth > 8 ) then
factor := 2;
elsif (bitwidth <= 32 and bitwidth > 16 ) then
factor := 1;
elsif (bitwidth <= 1024 and bitwidth > 32 ) then
factor := 1;
end if;
end procedure;
procedure count_operate_depth_by_bitwidth_and_depth(bitwidth : in INTEGER; depth : in INTEGER; operate_depth : out INTEGER) is
variable factor : INTEGER;
variable remain : INTEGER;
variable operate_depth_tmp : INTEGER;
begin
count_seperate_factor_by_bitwidth (bitwidth , factor);
operate_depth_tmp := depth / factor;
remain := depth mod factor;
if (remain > 0) then
operate_depth_tmp := operate_depth_tmp + 1;
end if;
operate_depth := operate_depth_tmp;
end procedure;
begin
--=================== signal connection ==============
TRAN_s_axi_AXILiteS_AWADDR <= AWADDR_reg;
TRAN_s_axi_AXILiteS_AWVALID <= AWVALID_reg;
TRAN_s_axi_AXILiteS_WVALID <= WVALID_reg;
TRAN_s_axi_AXILiteS_WDATA <= WDATA_reg;
TRAN_s_axi_AXILiteS_WSTRB <= WSTRB_reg;
TRAN_s_axi_AXILiteS_ARADDR <= ARADDR_reg;
TRAN_s_axi_AXILiteS_ARVALID <= ARVALID_reg;
TRAN_s_axi_AXILiteS_RREADY <= RREADY_reg;
TRAN_s_axi_AXILiteS_BREADY <= BREADY_reg;
TRAN_AXILiteS_done_out <= AESL_done_index_reg;
TRAN_AXILiteS_ready_out <= AESL_ready_out_index_reg;
TRAN_AXILiteS_write_start_finish <= AESL_write_start_finish;
TRAN_AXILiteS_idle_out <= AESL_idle_index_reg;
TRAN_AXILiteS_read_data_finish <= '1' and ap_return_read_data_finish;
TRAN_AXILiteS_write_data_finish <= '1' and P_mode_write_data_finish and P_index1_write_data_finish and P_index2_write_data_finish and P_intIn_index3_write_data_finish and P_floatIn_write_data_finish;
AESL_ready_reg_proc : process(TRAN_AXILiteS_ready_in, ready_initial)
begin
AESL_ready_reg <= TRAN_AXILiteS_ready_in or ready_initial;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until reset = '1';
wait until clk'event and clk = '1';
ready_initial <= '1';
wait until clk'event and clk = '1';
ready_initial <= '0';
wait;
end process;
ongoing_process_number_gen : process(reset , process_0_finish , process_1_finish , process_2_finish , process_3_finish , process_4_finish , process_5_finish , process_6_finish , process_7_finish )
begin
if (reset = '0') then
ongoing_process_number <= 0;
elsif (ongoing_process_number = 0 and process_0_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 1 and process_1_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 2 and process_2_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 3 and process_3_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 4 and process_4_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 5 and process_5_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 6 and process_6_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 7 and process_7_finish = '1') then
ongoing_process_number <= 0;
end if;
end process;
output_reg_write_value_function : process
begin
wait until reset = '1';
wait until clk'event and clk = '1';
while (true) loop
if (ongoing_process_number = 0 ) then
AWADDR_reg <= process_0_AWADDR_var;
AWVALID_reg <= process_0_AWVALID_var;
WVALID_reg <= process_0_WVALID_var;
WDATA_reg <= process_0_WDATA_var;
WSTRB_reg <= process_0_WSTRB_var;
ARADDR_reg <= process_0_ARADDR_var;
ARVALID_reg <= process_0_ARVALID_var;
RREADY_reg <= process_0_RREADY_var;
BREADY_reg <= process_0_BREADY_var;
elsif (ongoing_process_number = 1 ) then
AWADDR_reg <= process_1_AWADDR_var;
AWVALID_reg <= process_1_AWVALID_var;
WVALID_reg <= process_1_WVALID_var;
WDATA_reg <= process_1_WDATA_var;
WSTRB_reg <= process_1_WSTRB_var;
ARADDR_reg <= process_1_ARADDR_var;
ARVALID_reg <= process_1_ARVALID_var;
RREADY_reg <= process_1_RREADY_var;
BREADY_reg <= process_1_BREADY_var;
elsif (ongoing_process_number = 2 ) then
AWADDR_reg <= process_2_AWADDR_var;
AWVALID_reg <= process_2_AWVALID_var;
WVALID_reg <= process_2_WVALID_var;
WDATA_reg <= process_2_WDATA_var;
WSTRB_reg <= process_2_WSTRB_var;
ARADDR_reg <= process_2_ARADDR_var;
ARVALID_reg <= process_2_ARVALID_var;
RREADY_reg <= process_2_RREADY_var;
BREADY_reg <= process_2_BREADY_var;
elsif (ongoing_process_number = 3 ) then
AWADDR_reg <= process_3_AWADDR_var;
AWVALID_reg <= process_3_AWVALID_var;
WVALID_reg <= process_3_WVALID_var;
WDATA_reg <= process_3_WDATA_var;
WSTRB_reg <= process_3_WSTRB_var;
ARADDR_reg <= process_3_ARADDR_var;
ARVALID_reg <= process_3_ARVALID_var;
RREADY_reg <= process_3_RREADY_var;
BREADY_reg <= process_3_BREADY_var;
elsif (ongoing_process_number = 4 ) then
AWADDR_reg <= process_4_AWADDR_var;
AWVALID_reg <= process_4_AWVALID_var;
WVALID_reg <= process_4_WVALID_var;
WDATA_reg <= process_4_WDATA_var;
WSTRB_reg <= process_4_WSTRB_var;
ARADDR_reg <= process_4_ARADDR_var;
ARVALID_reg <= process_4_ARVALID_var;
RREADY_reg <= process_4_RREADY_var;
BREADY_reg <= process_4_BREADY_var;
elsif (ongoing_process_number = 5 ) then
AWADDR_reg <= process_5_AWADDR_var;
AWVALID_reg <= process_5_AWVALID_var;
WVALID_reg <= process_5_WVALID_var;
WDATA_reg <= process_5_WDATA_var;
WSTRB_reg <= process_5_WSTRB_var;
ARADDR_reg <= process_5_ARADDR_var;
ARVALID_reg <= process_5_ARVALID_var;
RREADY_reg <= process_5_RREADY_var;
BREADY_reg <= process_5_BREADY_var;
elsif (ongoing_process_number = 6 ) then
AWADDR_reg <= process_6_AWADDR_var;
AWVALID_reg <= process_6_AWVALID_var;
WVALID_reg <= process_6_WVALID_var;
WDATA_reg <= process_6_WDATA_var;
WSTRB_reg <= process_6_WSTRB_var;
ARADDR_reg <= process_6_ARADDR_var;
ARVALID_reg <= process_6_ARVALID_var;
RREADY_reg <= process_6_RREADY_var;
BREADY_reg <= process_6_BREADY_var;
elsif (ongoing_process_number = 7 ) then
AWADDR_reg <= process_7_AWADDR_var;
AWVALID_reg <= process_7_AWVALID_var;
WVALID_reg <= process_7_WVALID_var;
WDATA_reg <= process_7_WDATA_var;
WSTRB_reg <= process_7_WSTRB_var;
ARADDR_reg <= process_7_ARADDR_var;
ARVALID_reg <= process_7_ARVALID_var;
RREADY_reg <= process_7_RREADY_var;
BREADY_reg <= process_7_BREADY_var;
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
update_status_proc : process
variable process_num : INTEGER;
variable read_status_resp : INTEGER;
variable process_0_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 0;
while (true) loop
process_0_finish <= '0';
AESL_done_index_reg <= '0';
AESL_ready_out_index_reg <= '0';
if (ongoing_process_number = process_num and process_busy = '0') then
process_busy := '1';
--=======================one single read operate======================
read_status_resp := 0;
process_0_ARADDR_var <= STD_LOGIC_VECTOR(to_unsigned(STATUS_ADDR, ADDR_WIDTH));
process_0_ARVALID_var <= '1';
while (TRAN_s_axi_AXILiteS_ARREADY /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_ARVALID_var <= '0';
process_0_RREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_RVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_RDATA_tmp := TRAN_s_axi_AXILiteS_RDATA;
process_0_RREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_RRESP = (2 => '0') ) then
read_status_resp := 1;
--output success. in fact RRESP is always 2'b00
end if;
wait until clk'event and clk = '1';
--=======================one single read operate end======================
AESL_done_index_reg <= process_0_RDATA_tmp(1);
AESL_ready_out_index_reg <= process_0_RDATA_tmp(1);
AESL_idle_index_reg <= process_0_RDATA_tmp(2);
process_busy := '0';
process_0_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_mode_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_mode_write_data_finish <= '0';
write_P_mode_run_flag <= '0';
write_P_mode_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_mode_c_bitwidth, P_mode_DEPTH, P_mode_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_mode_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_mode_run_flag <= '1';
write_P_mode_count := 0;
end if;
if (write_one_P_mode_data_done = '1') then
write_P_mode_count := write_P_mode_count + 1;
if (write_P_mode_count = P_mode_OPERATE_DEPTH) then
write_P_mode_run_flag <= '0';
P_mode_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_mode_proc : process
variable write_P_mode_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_1_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_mode_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_mode_c_bitwidth;
process_num := 1;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_1_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_mode_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_mode data
for i in 0 to four_byte_num - 1 loop
if (P_mode_c_bitwidth < 32) then
P_mode_data_tmp_reg := mem_P_mode(write_P_mode_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_mode_c_bitwidth) then
P_mode_data_tmp_reg(j) := mem_P_mode(write_P_mode_count)(i*32 + j);
else
P_mode_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_mode_resp := 0;
aw_flag := '0';
w_flag := '0';
process_1_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_mode_data_in_addr + write_P_mode_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_1_AWVALID_var <= '1';
process_1_WDATA_var <= P_mode_data_tmp_reg;
process_1_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_1_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_1_AWVALID_var <= not aw_flag;
process_1_WVALID_var <= not w_flag;
end loop;
process_1_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_1_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_mode_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_mode_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_mode_data_done <= '0';
end if;
process_1_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_index1_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_index1_write_data_finish <= '0';
write_P_index1_run_flag <= '0';
write_P_index1_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_index1_c_bitwidth, P_index1_DEPTH, P_index1_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_index1_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_index1_run_flag <= '1';
write_P_index1_count := 0;
end if;
if (write_one_P_index1_data_done = '1') then
write_P_index1_count := write_P_index1_count + 1;
if (write_P_index1_count = P_index1_OPERATE_DEPTH) then
write_P_index1_run_flag <= '0';
P_index1_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_index1_proc : process
variable write_P_index1_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_2_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_index1_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_index1_c_bitwidth;
process_num := 2;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_2_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_index1_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_index1 data
for i in 0 to four_byte_num - 1 loop
if (P_index1_c_bitwidth < 32) then
P_index1_data_tmp_reg := mem_P_index1(write_P_index1_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_index1_c_bitwidth) then
P_index1_data_tmp_reg(j) := mem_P_index1(write_P_index1_count)(i*32 + j);
else
P_index1_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_index1_resp := 0;
aw_flag := '0';
w_flag := '0';
process_2_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_index1_data_in_addr + write_P_index1_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_2_AWVALID_var <= '1';
process_2_WDATA_var <= P_index1_data_tmp_reg;
process_2_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_2_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_2_AWVALID_var <= not aw_flag;
process_2_WVALID_var <= not w_flag;
end loop;
process_2_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_2_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_index1_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_index1_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_index1_data_done <= '0';
end if;
process_2_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_index2_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_index2_write_data_finish <= '0';
write_P_index2_run_flag <= '0';
write_P_index2_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_index2_c_bitwidth, P_index2_DEPTH, P_index2_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_index2_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_index2_run_flag <= '1';
write_P_index2_count := 0;
end if;
if (write_one_P_index2_data_done = '1') then
write_P_index2_count := write_P_index2_count + 1;
if (write_P_index2_count = P_index2_OPERATE_DEPTH) then
write_P_index2_run_flag <= '0';
P_index2_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_index2_proc : process
variable write_P_index2_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_3_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_index2_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_index2_c_bitwidth;
process_num := 3;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_3_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_index2_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_index2 data
for i in 0 to four_byte_num - 1 loop
if (P_index2_c_bitwidth < 32) then
P_index2_data_tmp_reg := mem_P_index2(write_P_index2_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_index2_c_bitwidth) then
P_index2_data_tmp_reg(j) := mem_P_index2(write_P_index2_count)(i*32 + j);
else
P_index2_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_index2_resp := 0;
aw_flag := '0';
w_flag := '0';
process_3_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_index2_data_in_addr + write_P_index2_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_3_AWVALID_var <= '1';
process_3_WDATA_var <= P_index2_data_tmp_reg;
process_3_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_3_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_3_AWVALID_var <= not aw_flag;
process_3_WVALID_var <= not w_flag;
end loop;
process_3_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_3_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_index2_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_index2_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_index2_data_done <= '0';
end if;
process_3_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_intIn_index3_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_intIn_index3_write_data_finish <= '0';
write_P_intIn_index3_run_flag <= '0';
write_P_intIn_index3_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_intIn_index3_c_bitwidth, P_intIn_index3_DEPTH, P_intIn_index3_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_intIn_index3_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_intIn_index3_run_flag <= '1';
write_P_intIn_index3_count := 0;
end if;
if (write_one_P_intIn_index3_data_done = '1') then
write_P_intIn_index3_count := write_P_intIn_index3_count + 1;
if (write_P_intIn_index3_count = P_intIn_index3_OPERATE_DEPTH) then
write_P_intIn_index3_run_flag <= '0';
P_intIn_index3_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_intIn_index3_proc : process
variable write_P_intIn_index3_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_4_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_intIn_index3_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_intIn_index3_c_bitwidth;
process_num := 4;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_4_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_intIn_index3_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_intIn_index3 data
for i in 0 to four_byte_num - 1 loop
if (P_intIn_index3_c_bitwidth < 32) then
P_intIn_index3_data_tmp_reg := mem_P_intIn_index3(write_P_intIn_index3_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_intIn_index3_c_bitwidth) then
P_intIn_index3_data_tmp_reg(j) := mem_P_intIn_index3(write_P_intIn_index3_count)(i*32 + j);
else
P_intIn_index3_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_intIn_index3_resp := 0;
aw_flag := '0';
w_flag := '0';
process_4_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_intIn_index3_data_in_addr + write_P_intIn_index3_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_4_AWVALID_var <= '1';
process_4_WDATA_var <= P_intIn_index3_data_tmp_reg;
process_4_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_4_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_4_AWVALID_var <= not aw_flag;
process_4_WVALID_var <= not w_flag;
end loop;
process_4_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_4_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_intIn_index3_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_intIn_index3_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_intIn_index3_data_done <= '0';
end if;
process_4_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_floatIn_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_floatIn_write_data_finish <= '0';
write_P_floatIn_run_flag <= '0';
write_P_floatIn_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_floatIn_c_bitwidth, P_floatIn_DEPTH, P_floatIn_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_floatIn_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_floatIn_run_flag <= '1';
write_P_floatIn_count := 0;
end if;
if (write_one_P_floatIn_data_done = '1') then
write_P_floatIn_count := write_P_floatIn_count + 1;
if (write_P_floatIn_count = P_floatIn_OPERATE_DEPTH) then
write_P_floatIn_run_flag <= '0';
P_floatIn_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_floatIn_proc : process
variable write_P_floatIn_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_5_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_floatIn_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_floatIn_c_bitwidth;
process_num := 5;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_5_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_floatIn_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_floatIn data
for i in 0 to four_byte_num - 1 loop
if (P_floatIn_c_bitwidth < 32) then
P_floatIn_data_tmp_reg := mem_P_floatIn(write_P_floatIn_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_floatIn_c_bitwidth) then
P_floatIn_data_tmp_reg(j) := mem_P_floatIn(write_P_floatIn_count)(i*32 + j);
else
P_floatIn_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_floatIn_resp := 0;
aw_flag := '0';
w_flag := '0';
process_5_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_floatIn_data_in_addr + write_P_floatIn_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_5_AWVALID_var <= '1';
process_5_WDATA_var <= P_floatIn_data_tmp_reg;
process_5_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_5_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_5_AWVALID_var <= not aw_flag;
process_5_WVALID_var <= not w_flag;
end loop;
process_5_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_5_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_floatIn_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_floatIn_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_floatIn_data_done <= '0';
end if;
process_5_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_start_run_flag : process (reset , clk)
begin
if (reset = '0') then
write_start_run_flag <= '0';
write_start_count := 0;
elsif (clk'event and clk = '1') then
if (write_start_count >= 265) then
write_start_run_flag <= '0';
elsif (TRAN_AXILiteS_write_start_in = '1') then
write_start_run_flag <= '1';
end if;
if (AESL_write_start_finish = '1') then
write_start_count := write_start_count + 1;
write_start_run_flag <= '0';
end if;
end if;
end process;
write_start_proc : process
variable process_num : INTEGER;
variable write_start_resp : INTEGER;
variable write_start_tmp : STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0) ;
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
variable i : INTEGER;
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 6;
while (true) loop
process_6_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
if (write_start_run_flag = '1') then
process_busy := '1';
write_start_tmp := (others => '0');
write_start_tmp(0) := '1';
--=======================one single write operate======================
write_start_resp := 0;
aw_flag := '0';
w_flag := '0';
process_6_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(START_ADDR, ADDR_WIDTH));
process_6_AWVALID_var <= '1';
process_6_WDATA_var <= write_start_tmp;
process_6_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_6_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_6_AWVALID_var <= not aw_flag;
process_6_WVALID_var <= not w_flag;
end loop;
process_6_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_6_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_start_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
process_busy := '0';
AESL_write_start_finish <= '1';
wait until clk'event and clk = '1';
AESL_write_start_finish <= '0';
end if;
process_6_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_read_ap_return_run_flag : process (reset , clk)
begin
if (reset = '0') then
ap_return_read_data_finish <= '0';
read_ap_return_run_flag <= '0';
read_ap_return_count := 0;
count_operate_depth_by_bitwidth_and_depth (ap_return_c_bitwidth, ap_return_DEPTH, ap_return_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (AESL_done_index_reg = '1') then
read_ap_return_run_flag <= '1';
end if;
if (TRAN_AXILiteS_transaction_done_in = '1') then
ap_return_read_data_finish <= '0';
read_ap_return_count := 0;
end if;
if (read_one_ap_return_data_done = '1') then
read_ap_return_count := read_ap_return_count + 1;
if (read_ap_return_count = ap_return_OPERATE_DEPTH) then
read_ap_return_run_flag <= '0';
ap_return_read_data_finish <= '1';
end if;
end if;
end if;
end process;
read_ap_return_proc : process
variable read_ap_return_resp : INTEGER;
variable process_num : INTEGER;
variable get_vld : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable process_7_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable i : INTEGER;
variable j : INTEGER;
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 ) := (others => '0');
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := ap_return_c_bitwidth;
process_num := 7;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_7_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
if (read_ap_return_run_flag = '1') then
process_busy := '1';
get_vld := 1;
if (get_vld = 1) then
--read ap_return data
for i in 0 to four_byte_num - 1 loop
--=======================one single read operate======================
read_ap_return_resp := 0;
process_7_ARADDR_var <= STD_LOGIC_VECTOR(to_unsigned(ap_return_data_out_addr + read_ap_return_count * four_byte_num * 4 + 4*i, ADDR_WIDTH));
process_7_ARVALID_var <= '1';
while (TRAN_s_axi_AXILiteS_ARREADY /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_7_ARVALID_var <= '0';
process_7_RREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_RVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_7_RDATA_tmp := TRAN_s_axi_AXILiteS_RDATA;
process_7_RREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_RRESP = (2 => '0') ) then
read_ap_return_resp := 1;
--output success. in fact RRESP is always 2'b00
end if;
wait until clk'event and clk = '1';
--=======================one single read operate end======================
if (ap_return_c_bitwidth < 32) then
mem_ap_return(read_ap_return_count) := process_7_RDATA_tmp;
else
for j in 0 to 32 - 1 loop
if (i*32 + j < ap_return_c_bitwidth) then
mem_ap_return(read_ap_return_count)(i*32 + j) := process_7_RDATA_tmp(j);
end if;
end loop;
end if;
end loop;
read_one_ap_return_data_done <= '1';
wait until clk'event and clk = '1';
read_one_ap_return_data_done <= '0';
end if;
process_busy := '0';
end if;
process_7_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_mode_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_mode_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_mode_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_mode , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_mode & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_mode_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_mode_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_mode_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_mode(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_mode_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_mode(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_mode_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_mode_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_mode(i)(31 downto 0) := mem_tmp_32;
else
mem_P_mode(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_mode(P_mode_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_mode(P_mode_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_index1_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_index1_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_index1_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_index1 , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_index1 & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_index1_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_index1_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_index1_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_index1(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_index1_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_index1(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_index1_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_index1_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_index1(i)(31 downto 0) := mem_tmp_32;
else
mem_P_index1(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_index1(P_index1_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_index1(P_index1_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_index2_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_index2_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_index2_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_index2 , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_index2 & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_index2_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_index2_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_index2_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_index2(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_index2_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_index2(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_index2_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_index2_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_index2(i)(31 downto 0) := mem_tmp_32;
else
mem_P_index2(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_index2(P_index2_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_index2(P_index2_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_intIn_index3_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_intIn_index3_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_intIn_index3_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_intIn_index3 , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_intIn_index3 & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_intIn_index3_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_intIn_index3_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_intIn_index3_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_intIn_index3(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_intIn_index3_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_intIn_index3(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_intIn_index3_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_intIn_index3_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_intIn_index3(i)(31 downto 0) := mem_tmp_32;
else
mem_P_intIn_index3(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_intIn_index3(P_intIn_index3_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_intIn_index3(P_intIn_index3_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_floatIn_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_floatIn_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_floatIn_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_floatIn , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_floatIn & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_floatIn_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_floatIn_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_floatIn_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_floatIn(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_floatIn_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_floatIn(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_floatIn_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_floatIn_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_floatIn(i)(31 downto 0) := mem_tmp_32;
else
mem_P_floatIn(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_floatIn(P_floatIn_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_floatIn(P_floatIn_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Write file-----------------------
-- Write data to file
write_ap_return_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable mem_tmp : STD_LOGIC_VECTOR(ap_return_c_bitwidth - 1 downto 0) := (others => '0');
variable factor : INTEGER;
variable remain : INTEGER;
variable mem_page : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (ap_return_c_bitwidth , factor);
while(true) loop
wait until clk'event and clk = '1';
while (TRAN_AXILiteS_transaction_done_in /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT_ap_return, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_ap_return & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to (ap_return_DEPTH - ap_return_DEPTH mod factor) - 1 loop
remain := i mod factor;
if (factor = 4) then
if (remain = 0) then
mem_tmp := mem_ap_return(i/factor)(7 downto 0);
elsif (remain = 1) then
mem_tmp := mem_ap_return(i/factor)(15 downto 8);
elsif (remain = 2) then
mem_tmp := mem_ap_return(i/factor)(23 downto 16);
elsif (remain = 3) then
mem_tmp := mem_ap_return(i/factor)(31 downto 24);
end if;
write(token_line, "0x" & esl_conv_string_hex(mem_tmp));
writeline(fp, token_line);
elsif (factor = 2) then
if (remain = 0) then
mem_tmp := mem_ap_return(i/factor)(15 downto 0);
elsif (remain = 1) then
mem_tmp := mem_ap_return(i/factor)(31 downto 16);
end if;
write(token_line, "0x" & esl_conv_string_hex(mem_tmp));
writeline(fp, token_line);
elsif (factor = 1) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(i)));
writeline(fp, token_line);
end if;
end loop;
remain := (ap_return_DEPTH - 1) mod factor;
if (factor = 4) then
if (remain = 2) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(7 downto 0)));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(15 downto 8)));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(23 downto 16)));
writeline(fp, token_line);
elsif (remain = 1) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(7 downto 0)));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(15 downto 8)));
writeline(fp, token_line);
elsif (remain = 0) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(7 downto 0)));
writeline(fp, token_line);
end if;
elsif (factor = 2) then
if (remain = 0) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(15 downto 0)));
writeline(fp, token_line);
end if;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
end process;
end behav;
|
gpl-3.0
|
518ba2a7850905afe782f905c11eb63a
| 0.513684 | 3.583985 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/ip/feedforward_ap_dmul_4_max_dsp_64.vhd
| 2 | 12,777 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dmul_4_max_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_dmul_4_max_dsp_64;
ARCHITECTURE feedforward_ap_dmul_4_max_dsp_64_arch OF feedforward_ap_dmul_4_max_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dmul_4_max_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dmul_4_max_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dmul_4_max_dsp_64_arch;
|
gpl-3.0
|
5a9a4837da16bf9c6d0c9274a06ea12a
| 0.651874 | 3.021282 | false | false | false | false |
yahniukov/AES-128_VHDL
|
Design Sources/SubBytes_module.vhd
| 1 | 9,916 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SubBytes_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end SubBytes_module;
architecture RTL of SubBytes_module is
-----------------------------
--------- CONSTANTS ---------
-----------------------------
constant BYTES_COUNT : integer := 16;
constant BYTE_LENGTH : integer := 8;
-----------------------------
----------- TYPES -----------
-----------------------------
type REG_SBOX_VALUES is array (BYTES_COUNT-1 downto 0) of std_logic_vector (BYTE_LENGTH-1 downto 0);
-----------------------------
---------- SIGNALS ----------
-----------------------------
-- Memory to store 16 bytes
signal bytes_memory_in : REG_SBOX_VALUES;
signal bytes_memory_out : REG_SBOX_VALUES;
-- Managed signal
signal start_sbox_module : std_logic;
signal finish_sbox_module_0 : std_logic;
signal finish_sbox_module_1 : std_logic;
signal finish_sbox_module_2 : std_logic;
signal finish_sbox_module_3 : std_logic;
signal finish_sbox_module_4 : std_logic;
signal finish_sbox_module_5 : std_logic;
signal finish_sbox_module_6 : std_logic;
signal finish_sbox_module_7 : std_logic;
signal finish_sbox_module_8 : std_logic;
signal finish_sbox_module_9 : std_logic;
signal finish_sbox_module_10 : std_logic;
signal finish_sbox_module_11 : std_logic;
signal finish_sbox_module_12 : std_logic;
signal finish_sbox_module_13 : std_logic;
signal finish_sbox_module_14 : std_logic;
signal finish_sbox_module_15 : std_logic;
signal finish_all_sbox : std_logic;
-----------------------------
--------- COMPONENTS --------
-----------------------------
component SBox_module is
Generic ( BYTE_LENGTH : integer := 8 );
Port ( data_out : out STD_LOGIC_VECTOR (BYTE_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (BYTE_LENGTH-1 downto 0);
start : in STD_LOGIC);
end component SBox_module;
begin
-- Initialize and Reset process
reset_n_init_process : process(reset)
begin
if(rising_edge(reset)) then
bytes_memory_in(BYTES_COUNT-1 downto 0) <= (others => X"0");
start_sbox_module <= '0';
finish_sbox_module_0 <= '0';
finish_sbox_module_1 <= '0';
finish_sbox_module_2 <= '0';
finish_sbox_module_3 <= '0';
finish_sbox_module_4 <= '0';
finish_sbox_module_5 <= '0';
finish_sbox_module_6 <= '0';
finish_sbox_module_7 <= '0';
finish_sbox_module_8 <= '0';
finish_sbox_module_9 <= '0';
finish_sbox_module_10 <= '0';
finish_sbox_module_11 <= '0';
finish_sbox_module_12 <= '0';
finish_sbox_module_13 <= '0';
finish_sbox_module_14 <= '0';
finish_sbox_module_15 <= '0';
end if;
end process reset_n_init_process;
-- Structure of signals transmission
bytes_memory_in(0) <= data_in(BYTE_LENGTH-1 downto BYTE_LENGTH-8) when rising_edge(start);
bytes_memory_in(1) <= data_in(BYTE_LENGTH*2-1 downto BYTE_LENGTH*2-8) when rising_edge(start);
bytes_memory_in(2) <= data_in(BYTE_LENGTH*3-1 downto BYTE_LENGTH*3-8) when rising_edge(start);
bytes_memory_in(3) <= data_in(BYTE_LENGTH*4-1 downto BYTE_LENGTH*4-8) when rising_edge(start);
bytes_memory_in(4) <= data_in(BYTE_LENGTH*5-1 downto BYTE_LENGTH*5-8) when rising_edge(start);
bytes_memory_in(5) <= data_in(BYTE_LENGTH*6-1 downto BYTE_LENGTH*6-8) when rising_edge(start);
bytes_memory_in(6) <= data_in(BYTE_LENGTH*7-1 downto BYTE_LENGTH*7-8) when rising_edge(start);
bytes_memory_in(7) <= data_in(BYTE_LENGTH*8-1 downto BYTE_LENGTH*8-8) when rising_edge(start);
bytes_memory_in(8) <= data_in(BYTE_LENGTH*9-1 downto BYTE_LENGTH*9-8) when rising_edge(start);
bytes_memory_in(9) <= data_in(BYTE_LENGTH*10-1 downto BYTE_LENGTH*10-8) when rising_edge(start);
bytes_memory_in(10) <= data_in(BYTE_LENGTH*11-1 downto BYTE_LENGTH*11-8) when rising_edge(start);
bytes_memory_in(11) <= data_in(BYTE_LENGTH*12-1 downto BYTE_LENGTH*12-8) when rising_edge(start);
bytes_memory_in(12) <= data_in(BYTE_LENGTH*13-1 downto BYTE_LENGTH*13-8) when rising_edge(start);
bytes_memory_in(13) <= data_in(BYTE_LENGTH*14-1 downto BYTE_LENGTH*14-8) when rising_edge(start);
bytes_memory_in(14) <= data_in(BYTE_LENGTH*15-1 downto BYTE_LENGTH*15-8) when rising_edge(start);
bytes_memory_in(15) <= data_in(BYTE_LENGTH*16-1 downto BYTE_LENGTH*16-8) when rising_edge(start);
start_sbox_module <= '1' when rising_edge(start);
data_out(BYTE_LENGTH-1 downto BYTE_LENGTH-8) <= bytes_memory_out(0) when clock = '1' and finish_sbox_module_0 = '1';
data_out(BYTE_LENGTH*2-1 downto BYTE_LENGTH*2-8) <= bytes_memory_out(1) when clock = '1' and finish_sbox_module_1 = '1';
data_out(BYTE_LENGTH*3-1 downto BYTE_LENGTH*3-8) <= bytes_memory_out(2) when clock = '1' and finish_sbox_module_2 = '1';
data_out(BYTE_LENGTH*4-1 downto BYTE_LENGTH*4-8) <= bytes_memory_out(3) when clock = '1' and finish_sbox_module_3 = '1';
data_out(BYTE_LENGTH*5-1 downto BYTE_LENGTH*5-8) <= bytes_memory_out(4) when clock = '1' and finish_sbox_module_4 = '1';
data_out(BYTE_LENGTH*6-1 downto BYTE_LENGTH*6-8) <= bytes_memory_out(5) when clock = '1' and finish_sbox_module_5 = '1';
data_out(BYTE_LENGTH*7-1 downto BYTE_LENGTH*7-8) <= bytes_memory_out(6) when clock = '1' and finish_sbox_module_6 = '1';
data_out(BYTE_LENGTH*8-1 downto BYTE_LENGTH*8-8) <= bytes_memory_out(7) when clock = '1' and finish_sbox_module_7 = '1';
data_out(BYTE_LENGTH*9-1 downto BYTE_LENGTH*9-8) <= bytes_memory_out(8) when clock = '1' and finish_sbox_module_8 = '1';
data_out(BYTE_LENGTH*10-1 downto BYTE_LENGTH*10-8) <= bytes_memory_out(9) when clock = '1' and finish_sbox_module_9 = '1';
data_out(BYTE_LENGTH*11-1 downto BYTE_LENGTH*11-8) <= bytes_memory_out(10) when clock = '1' and finish_sbox_module_10 = '1';
data_out(BYTE_LENGTH*12-1 downto BYTE_LENGTH*12-8) <= bytes_memory_out(11) when clock = '1' and finish_sbox_module_11 = '1';
data_out(BYTE_LENGTH*13-1 downto BYTE_LENGTH*13-8) <= bytes_memory_out(12) when clock = '1' and finish_sbox_module_12 = '1';
data_out(BYTE_LENGTH*14-1 downto BYTE_LENGTH*14-8) <= bytes_memory_out(13) when clock = '1' and finish_sbox_module_13 = '1';
data_out(BYTE_LENGTH*15-1 downto BYTE_LENGTH*15-8) <= bytes_memory_out(14) when clock = '1' and finish_sbox_module_14 = '1';
data_out(BYTE_LENGTH*16-1 downto BYTE_LENGTH*16-8) <= bytes_memory_out(15) when clock = '1' and finish_sbox_module_15 = '1';
SBox_module_0 : SBox_module
port map (bytes_memory_out(0), finish_sbox_module_0, bytes_memory_in(0), start_sbox_module);
SBox_module_1 : SBox_module
port map (bytes_memory_out(1), finish_sbox_module_1, bytes_memory_in(1), start_sbox_module);
SBox_module_2 : SBox_module
port map (bytes_memory_out(2), finish_sbox_module_2, bytes_memory_in(2), start_sbox_module);
SBox_module_3 : SBox_module
port map (bytes_memory_out(3), finish_sbox_module_3, bytes_memory_in(3), start_sbox_module);
SBox_module_4 : SBox_module
port map (bytes_memory_out(4), finish_sbox_module_4, bytes_memory_in(4), start_sbox_module);
SBox_module_5 : SBox_module
port map (bytes_memory_out(5), finish_sbox_module_5, bytes_memory_in(5), start_sbox_module);
SBox_module_6 : SBox_module
port map (bytes_memory_out(6), finish_sbox_module_6, bytes_memory_in(6), start_sbox_module);
SBox_module_7 : SBox_module
port map (bytes_memory_out(7), finish_sbox_module_7, bytes_memory_in(7), start_sbox_module);
SBox_module_8 : SBox_module
port map (bytes_memory_out(8), finish_sbox_module_8, bytes_memory_in(8), start_sbox_module);
SBox_module_9 : SBox_module
port map (bytes_memory_out(9), finish_sbox_module_9, bytes_memory_in(9), start_sbox_module);
SBox_module_10 : SBox_module
port map (bytes_memory_out(10), finish_sbox_module_10, bytes_memory_in(10), start_sbox_module);
SBox_module_11 : SBox_module
port map (bytes_memory_out(11), finish_sbox_module_11, bytes_memory_in(11), start_sbox_module);
SBox_module_12 : SBox_module
port map (bytes_memory_out(12), finish_sbox_module_12, bytes_memory_in(12), start_sbox_module);
SBox_module_13 : SBox_module
port map (bytes_memory_out(13), finish_sbox_module_13, bytes_memory_in(13), start_sbox_module);
SBox_module_14 : SBox_module
port map (bytes_memory_out(14), finish_sbox_module_14, bytes_memory_in(14), start_sbox_module);
SBox_module_15 : SBox_module
port map (bytes_memory_out(15), finish_sbox_module_15, bytes_memory_in(15), start_sbox_module);
finish_all_sbox <= finish_sbox_module_0 and finish_sbox_module_1 and finish_sbox_module_2 and
finish_sbox_module_3 and finish_sbox_module_4 and finish_sbox_module_5 and
finish_sbox_module_6 and finish_sbox_module_7 and finish_sbox_module_8 and
finish_sbox_module_9 and finish_sbox_module_10 and finish_sbox_module_11 and
finish_sbox_module_12 and finish_sbox_module_13 and finish_sbox_module_14 and
finish_sbox_module_15;
finish <= finish_all_sbox;
end RTL;
|
mit
|
bb65fbd9c3a5e693dade68ce93a960c5
| 0.616781 | 3.122166 | false | false | false | false |
makestuff/spi-talk
|
vhdl/fifo-gen/sim/fifo.vhdl
| 2 | 1,911 |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
depth_out : out std_logic_vector(7 downto 0);
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
begin
-- The encapsulated FIFO
fifo: entity work.fifo
generic map(
WIDTH => 8,
DEPTH => 7
)
port map(
clk_in => clk_in,
reset_in => '0',
depth_out => depth_out,
-- Input pipe
inputData_in => inputData_in,
inputValid_in => inputValid_in,
inputReady_out => inputReady_out,
-- Output pipe
outputData_out => outputData_out,
outputValid_out => outputValid_out,
outputReady_in => outputReady_in
);
end architecture;
|
gpl-3.0
|
daadad79cc1ea8c5cea8a821158023ce
| 0.684982 | 3.538889 | false | false | false | false |
minijackson/school-vhdl
|
E2/TP1.vhdl
| 1 | 2,036 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock is
port (
enable : in std_logic;
razs : in std_logic;
minuteUnits : out std_logic_vector(3 downto 0);
minuteTenths : out std_logic_vector(2 downto 0);
hoursUnits : out std_logic_vector(3 downto 0);
hoursTenths : out std_logic_vector(1 downto 0);
clk : in std_logic;
reset : in std_logic;
);
end clock;
architecture clockArch of clock is
begin
minuteUnitsComponent : entity clockCounter port map (
enable => enable,
razs => razs,
clk => clk,
reset => reset,
dataOut => minuteUnitsValue
);
minuteTenthsComponent : entity clockCounter
generic map (
n => 3,
max => 5
);
port map (
enable => enable,
razs => razs,
clk => clk,
reset => reset,
dataOut => minuteTenthsValue
);
hoursUnitsComponent : entity clockCounter
port map (
enable => enable,
razs => razs,
clk => clk,
reset => reset,
dataOut => hoursUnitsValue
);
hoursTenthsComponent : entity clockCounter
generic map (
n => 2,
max => 2
);
port map (
enable => enable,
razs => razs,
clk => clk,
reset => reset,
dataOut => hoursTenthsValue
);
end clockArch;
entity clockCounter is
generic (
n : natural := 4;
max : natural := 9;
);
port (
dataOut : out std_logic_vector(n-1 downto 0);
enable : in std_logic;
razs : in std_logic;
clk : in std_logic;
reset : in std_logic;
);
end clockCounter;
architecture clockCounterArch of clock is
signal inc, eno, D, Q : std_logic_vector(n-1 downto 0);
begin
dataOut <= Q
Q <= '0' when reset = '1' else
D when rising_edge(clk);
inc <= 0 when Q = max else
Q+1;
eno <= inc when enable = '1' else
Q;
D <= '0' when razs = '1' else
eno;
end clockCounterArch;
|
mit
|
d8f6586e7d270022728d5d6ba6e03f80
| 0.55501 | 3.310569 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ip/design_SWandHW_standalone_v2_axi_gpio_0_0/synth/design_SWandHW_standalone_v2_axi_gpio_0_0.vhd
| 1 | 9,881 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SWandHW_standalone_v2_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SWandHW_standalone_v2_axi_gpio_0_0;
ARCHITECTURE design_SWandHW_standalone_v2_axi_gpio_0_0_arch OF design_SWandHW_standalone_v2_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_v2_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_v2_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_v2_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SWandHW_standalone_v2_axi_gpio_0_0_arch;
|
gpl-3.0
|
0e686fc07a3a55eedd1bd48e5f2ca566
| 0.691833 | 3.179215 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_ddiv_29_no_dsp_64.vhd
| 6 | 12,779 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_ddiv_29_no_dsp_64;
ARCHITECTURE feedforward_ap_ddiv_29_no_dsp_64_arch OF feedforward_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_ddiv_29_no_dsp_64_arch;
|
gpl-3.0
|
aa5841b6c81dde3b56a56a9e26be9005
| 0.651929 | 3.021755 | false | false | false | false |
minijackson/school-vhdl
|
E2/TP2/controller.vhd
| 1 | 2,646 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- clk,
-- reset,ββββββββββββββββββββββββββββββββββββββ
-- speedβ βββββββββsegsβββββdatΓ4 ββββββββββ β
-- βββΏβ³β₯ ctrl βββββ±β€staββββββββ₯ basys2 βββΏββ
-- βββ β βββββββββββββ₯ displayβ β seg,
-- βββββββββββ βββββββββββββ₯ ctrl β β dp,
-- ββ β β β€staββββββββ₯ β β an
-- ββ You are ββββββ ββ ββββ°ββββββ β
-- ββ here ββββββ ββ β β
-- ββ β β€staββββ β β
-- ββ ββββββ β β β
-- ββ ββββββ β β β
-- ββ ββ€staββββ β β
-- ββ βββββ β β
-- ββββββββββββββββββββββββββββββ β
-- β β
-- β β
-- β β
-- ββββββββββββββββββββββββββββββββββββββ
--
-- Components:
-- ===========
--
-- controller (ctrl):
-- provides data for the foru 7-segments displayer considering
-- the clock and speed.
--
-- states (sta):
-- converts a data fragment provided by ctrl to actual bits for a
-- 7-segment displayer
--
-- basys2_display_controller (basys2 display ctrl)
-- converter that provides data directly usable by the basys2 card
--
-- Internal signals:
-- =================
--
-- segs is a bus containing the states for the four 7-segments displayer
--
-- dat contains data for a 7-segment displayer
entity controller is
port (
clk : in std_logic;
reset : in std_logic;
segmentStates : out std_logic_vector(7 downto 0);
);
end controller;
architecture controllerArch of controller is
segmentStatesEx : std_logic_vector(15 downto 0);
begin
segmentStates <= segmentStatesEx(7 downto 0);
process (clk, reset) is
begin
if reset = '1' then segmentStatesEx <= "12130000";
elsif rising_edge(clk) then segmentStatesEx <= segmentStatesEx ror 2;
end if
end process
end controllerArch;
|
mit
|
4003c6e1cb5f623e39c45336bf7ba6ae
| 0.422944 | 3.008889 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_ddiv_64ns_64ns_64_31.vhd
| 2 | 3,362 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
524447254cb760e4e2b490856c2f3fd3
| 0.488995 | 3.527807 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_mux_4to1_sel2_32_1.vhd
| 7 | 1,606 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
gpl-3.0
|
1b393422688aadbab38461782402d87c
| 0.558531 | 3.142857 | false | false | false | false |
bonfireprocessor/bonfire-soc
|
MainMemory.vhd
| 1 | 5,038 |
----------------------------------------------------------------------------------
-- Module Name: MainMemory - Behavioral
-- The Bonfire Processor Project, (c) 2016,2017 Thomas Hornschuh
-- Toplevel module for Papilio Pro with 8MB SDRAM
-- License: See LICENSE or LICENSE.txt File in git project root.
-- Memory module to be synthesized as block RAM
-- can be initalized with a file
-- New "single process" version as recommended by Xilinx XST user guide
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library STD;
use STD.textio.all;
entity MainMemory is
generic (RamFileName : string := "meminit.ram";
mode : string := "B";
ADDR_WIDTH: integer;
SIZE : integer;
Swapbytes : boolean; -- SWAP Bytes in RAM word in low byte first order to use data2mem
EnableSecondPort : boolean := true -- enable inference of the second port
);
Port ( DBOut : out STD_LOGIC_VECTOR (31 downto 0);
DBIn : in STD_LOGIC_VECTOR (31 downto 0);
AdrBus : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
ENA : in STD_LOGIC;
WREN : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
-- Second Port ( read only)
CLKB : in STD_LOGIC;
ENB : in STD_LOGIC;
AdrBusB : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
DBOutB : out STD_LOGIC_VECTOR (31 downto 0)
);
end MainMemory;
architecture Behavioral of MainMemory is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "TRUE";
type tRam is array (0 to SIZE-1) of STD_LOGIC_VECTOR (31 downto 0);
subtype tWord is std_logic_vector(31 downto 0);
signal DOA,DOB,DIA : tWord;
signal WEA : STD_LOGIC_VECTOR (3 downto 0);
function doSwapBytes(d : tWord) return tWord is
begin
return d(7 downto 0)&d(15 downto 8)&d(23 downto 16)&d(31 downto 24);
end;
-- Design time code...
-- Initalizes block RAM form memory file
-- The file does either contain hex values (mode = 'H') or binary values
impure function InitFromFile return tRam is
FILE RamFile : text; -- is in RamFileName;
variable RamFileLine : line;
variable word : tWord;
variable r : tRam;
begin
report "RamFileName is " & RamFileName;
file_open(RamFile,RamFileName,READ_MODE);
for I in tRam'range loop
if not endfile(RamFile) then
readline (RamFile, RamFileLine);
if mode="H" then
hread (RamFileLine, word); -- alternative: HEX read
else
read(RamFileLine,word); -- Binary read
end if;
if SwapBytes then
r(I) := DoSwapBytes(word);
else
r(I) := word;
end if;
else
r(I) := (others=>'0');
end if;
end loop;
file_close(RamFile);
return r;
end function;
signal ram : tRam:= InitFromFile;
attribute ram_style: string; -- for Xilinx
attribute ram_style of ram: signal is "block";
-- helper component
-- for byte swapping
COMPONENT byte_swapper
PORT(
din : IN std_logic_vector(31 downto 0);
dout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
begin
swap: if SwapBytes generate
-- The Data input bus is swapped with the helper component to avoid
-- confusing the xilinx synthesis tools which sometimes infer distributed
-- instead of block RAM
-- It is important that the byte swapper component has set the keep_hierarchy attribute to TRUE
-- this will make the byte swap of the input bus invisble for the RAM inference
bs: byte_swapper PORT MAP(
din => DBIn,
dout => DIA
);
DBOut<=DoSwapBytes(DOA);
DBOutB<=DoSwapBytes(DOB);
WEA(0)<=WREN(3);
WEA(1)<=WREN(2);
WEA(2)<=WREN(1);
WEA(3)<=WREN(0);
end generate;
noswap: if not SwapBytes generate
DIA<=DBIn;
DBOut<=DOA;
DBOutB<=DOB;
WEA<=WREN;
end generate;
process(clk)
variable adr : integer;
begin
if rising_edge(clk) then
if ena = '1' then
adr := to_integer(unsigned(AdrBus));
for i in 0 to 3 loop
if WEA(i) = '1' then
ram(adr)((i+1)*8-1 downto i*8)<= DIA((i+1)*8-1 downto i*8);
end if;
end loop;
DOA <= ram(adr);
end if;
end if;
end process;
portb: if EnableSecondPort generate
process(clkb) begin
if rising_edge(clkb) then
if ENB='1' then
DOB <= ram(to_integer(unsigned(AdrBusB)));
end if;
end if;
end process;
end generate;
end Behavioral;
|
gpl-3.0
|
8c733f1fb511df1d949aa7dd480dab12
| 0.602223 | 3.995242 | false | false | false | false |
airlog/vhdl-rc4
|
src/reseter.vhd
| 1 | 1,285 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity reseter is
generic (
size: integer := 256;
width: integer := 8;
addrwidth: integer := 8;
rstvalue : integer := 0
);
port (
CLK: in std_logic;
GO: in std_logic;
CTRL: out std_logic;
INDEX: out std_logic_vector((addrwidth - 1) downto 0);
VALUE: out std_logic_vector((width - 1) downto 0);
DONE: out std_logic
);
end reseter;
architecture Behavioral of reseter is
type reseter_state is (IDLE, WORKING);
begin
process (clk)
variable state : reseter_state := IDLE;
variable clk_ctr : integer := 0;
variable ctr : integer := 0;
begin
if rising_edge(clk) then
case state is
when IDLE =>
if go = '1' then
done <= '0';
clk_ctr := 0;
ctr := 0;
state := WORKING;
else
ctrl <= '0';
done <= '1';
end if;
when WORKING =>
if ctr >= size then
ctrl <= '0';
done <= '1';
state := IDLE;
else
ctrl <= '1';
index <= conv_std_logic_vector(ctr, addrwidth);
value <= conv_std_logic_vector(rstvalue, width);
ctr := ctr + 1;
state := WORKING;
end if;
end case;
end if;
end process;
end Behavioral;
|
mit
|
2196673cdc729528f851892eb0127b0a
| 0.551751 | 3.088942 | false | false | false | false |
brotatos/Whack-A-Mole
|
src/clk_div.vhd
| 1 | 1,788 |
----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: bryan mealy
--
-- Create Date: 15:27:40 12/27/2010
-- Design Name:
-- Module Name: clk_div.vhd
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This divides the input clock frequency into a slower
-- frequency. The frequency is set by the the MAX_COUNT
-- constant in the declarative region of the architecture.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------------
-- Module to divide the clock
-----------------------------------------------------------------------
entity clk_div2 is
Port ( clk : in std_logic;
sclk : out std_logic);
end clk_div2;
architecture my_clk_div of clk_div2 is
constant max_count : integer := (16000000);
-- original
--constant max_count : integer := (3000000);
signal tmp_clk : std_logic := '0';
begin
my_div: process (clk,tmp_clk)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = MAX_COUNT) then
tmp_clk <= not tmp_clk;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
sclk <= tmp_clk;
end process my_div;
end my_clk_div;
|
mit
|
74d493c93ca2b806e47467c71d980bea
| 0.444072 | 4.447761 | false | false | false | false |
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fpext_0_no_dsp_32/synth/ANN_ap_fpext_0_no_dsp_32.vhd
| 1 | 12,137 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_fpext_0_no_dsp_32;
ARCHITECTURE ANN_ap_fpext_0_no_dsp_32_arch OF ANN_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fpext_0_no_dsp_32_arch;
|
gpl-3.0
|
57060d1b1136a72d64f837a90c8e4599
| 0.645547 | 2.998271 | false | false | false | false |
Rookfighter/aes-ss17
|
ex03/i2c_slave.vhd
| 1 | 8,811 |
-- i2c_slave.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_slave is
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0); -- rx, data received
rx_recv: out std_logic; -- rx received, high active
busy: out std_logic; -- busy, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end entity;
architecture behavioral of i2c_slave is
component delay
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic; -- data in
dout: out std_logic); -- data out
end component;
-- states for FSM
type TState is (SIDLE, SADDR, SSEND_ACK1, SSEND_ACK2, SRECV_ACK, SREAD, SWRITE);
signal state: TState := SIDLE;
-- constant to define cycles per time unit
constant CLKPERMS: natural := 24000;
-- counter for measuring time to timeout after 1ms
constant TIMEOUTLEN: natural := 15;
signal cnt_timeout: unsigned(TIMEOUTLEN-1 downto 0) := (others => '0');
-- data vector for handling traffic internally
constant DATALEN: natural := 8;
signal data: std_logic_vector(DATALEN-1 downto 0) := (others => '0');
-- determines if master reqested read (high) or write (low)
signal rwbit: std_logic := '0';
-- sda signal delayed by 1us
signal sda_del: std_logic := '0';
-- i2c vectors to store previous and current signal
signal scl_vec: std_logic_vector(1 downto 0) := (others => '0');
signal sda_vec: std_logic_vector(1 downto 0) := (others => '0');
-- counter to count bits received / sent
signal cnt_bit: unsigned(2 downto 0) := (others => '0');
begin
-- always let master handle scl
scl <= 'Z';
-- lsb is current scl
scl_vec(0) <= scl;
-- lsb is delayed sda
sda_vec(0) <= sda_del;
-- always busy if not in idle mode
busy <= '0' when state = SIDLE else '1';
-- delay sda signal by 24 cylces (= 1us)
delay1: delay
generic map(RSTDEF => RSTDEF,
DELAYLEN => 24)
port map(rst => rst,
clk => clk,
din => sda,
dout => sda_del);
process(clk, rst)
begin
if rst = RSTDEF then
tx_sent <= '0';
rx_data <= (others => '0');
rx_recv <= '0';
sda <= 'Z';
state <= SIDLE;
cnt_timeout <= (others => '0');
data <= (others => '0');
rwbit <= '0';
scl_vec(1) <= '0';
sda_vec(1) <= '0';
cnt_bit <= (others => '0');
elsif rising_edge(clk) then
-- keep track of previous sda and scl (msb)
sda_vec(1) <= sda_vec(0);
scl_vec(1) <= scl_vec(0);
-- leave sent and recv signals high only one cylce
tx_sent <= '0';
rx_recv <= '0';
-- check for timeout
cnt_timeout <= cnt_timeout + 1;
if scl_vec = "01" then
-- reset timeout on rising scl
cnt_timeout <= (others => '0');
elsif to_integer(cnt_timeout) = CLKPERMS then
-- timeout is reached go into idle state
cnt_timeout <= (others => '0');
state <= SIDLE;
sda <= 'Z';
end if;
-- compute state machine for i2c slave
case state is
when SIDLE =>
-- do nothing
when SADDR =>
if scl_vec = "01" then
-- set data bit depending on cnt_bit
data(7-to_integer(cnt_bit)) <= sda_vec(0);
cnt_bit <= cnt_bit + 1;
-- if cnt_bit is full then we have just received last bit
if cnt_bit = "111" then
rwbit <= sda_vec(0);
if data(DATALEN-1 downto 1) = ADDRDEF then
-- address matches ours, acknowledge
state <= SSEND_ACK1;
else
-- address doesn't match ours, ignore
state <= SIDLE;
end if;
end if;
end if;
when SSEND_ACK1 =>
if scl_vec = "10" then
state <= SSEND_ACK2;
sda <= '0';
end if;
when SSEND_ACK2 =>
if scl_vec = "10" then
-- check if master requested read or write
if rwbit = '1' then
-- master wants to read
-- write first bit on bus
sda <= tx_data(7);
data <= tx_data;
-- start from one because we already wrote first bit
cnt_bit <= "001";
state <= SREAD;
else
-- master wants to write
-- release sda
sda <= 'Z';
cnt_bit <= (others => '0');
state <= SWRITE;
end if;
end if;
when SRECV_ACK =>
if scl_vec = "01" then
if sda_vec(0) /= '0' then
-- received nack: master will send stop cond, but we
-- can simply jump right to idle state
state <= SIDLE;
end if;
elsif scl_vec = "10" then
-- continue read
sda <= tx_data(7); -- write first bit on bus
data <= tx_data;
-- start from 1 because we alreay transmit first bit
cnt_bit <= "001";
state <= SREAD;
end if;
when SREAD =>
if scl_vec = "10" then
sda <= data(7-to_integer(cnt_bit));
cnt_bit <= cnt_bit + 1;
-- if cnt_bit overflowed we finished transmitting last bit
-- note: data is not allowed to contain any 1, only Z or 0
if cnt_bit = "000" then
-- release sda, because we need to listen for ack
-- from master
sda <= 'Z';
state <= SRECV_ACK;
-- notify that we have sent the byte
tx_sent <= '1';
end if;
end if;
when SWRITE =>
if scl_vec = "01" then
data(7-to_integer(cnt_bit)) <= sda_vec(0);
cnt_bit <= cnt_bit + 1;
-- if cnt_bit is full we have just revceived the last bit
if cnt_bit = "111" then
state <= SSEND_ACK1;
-- apply received byte to out port
rx_data <= data(DATALEN-1 downto 1) & sda_vec(0);
-- notify that we have received a new byte
rx_recv <= '1';
end if;
end if;
end case;
-- check for stop / start condition
if scl_vec = "11" and sda_vec = "01" then
-- i2c stop condition
state <= SIDLE;
sda <= 'Z';
elsif scl_vec = "11" and sda_vec = "10" then
-- i2c start condition / repeated start condition
state <= SADDR;
cnt_bit <= (others => '0');
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
4259c2397a224f994a6661a1eaf1cfb7
| 0.421178 | 4.630058 | false | false | false | false |
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