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// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "true";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_PP_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_mux_4to1_sel2_32_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
)(
input [31 : 0] din1,
input [31 : 0] din2,
input [31 : 0] din3,
input [31 : 0] din4,
input [1 : 0] din5,
output [31 : 0] dout);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [31 : 0] mux_1_0;
wire [31 : 0] mux_1_1;
// level 2 signals
wire [31 : 0] mux_2_0;
assign sel = din5;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
|
/*
* dyn_reconf_tb.v: Test bench for dyn_reconf.v
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef CLK_PERIOD
`define CLK_PERIOD 10
`endif
module dyn_reconf_tb ();
reg RST;
reg PWRDWN;
reg [31:0] vco_period_1000;
reg [6:0] DADDR;
reg DCLK;
reg DEN;
reg DWE;
reg [15:0] DI;
wire [15:0] DO;
output DRDY;
wire [31:0] CLKOUT0_DIVIDE;
wire [31:0] CLKOUT1_DIVIDE;
wire [31:0] CLKOUT2_DIVIDE;
wire [31:0] CLKOUT3_DIVIDE;
wire [31:0] CLKOUT4_DIVIDE;
wire [31:0] CLKOUT5_DIVIDE;
wire [31:0] CLKOUT6_DIVIDE;
wire [31:0] CLKOUT0_DUTY_CYCLE;
wire [31:0] CLKOUT1_DUTY_CYCLE;
wire [31:0] CLKOUT2_DUTY_CYCLE;
wire [31:0] CLKOUT3_DUTY_CYCLE;
wire [31:0] CLKOUT4_DUTY_CYCLE;
wire [31:0] CLKOUT5_DUTY_CYCLE;
wire [31:0] CLKOUT6_DUTY_CYCLE;
wire [31:0] CLKOUT0_PHASE;
wire [31:0] CLKOUT1_PHASE;
wire [31:0] CLKOUT2_PHASE;
wire [31:0] CLKOUT3_PHASE;
wire [31:0] CLKOUT4_PHASE;
wire [31:0] CLKOUT5_PHASE;
wire [31:0] CLKOUT6_PHASE;
wire [31:0] CLKFBOUT_MULT_F_1000;
wire [31:0] CLKFBOUT_PHASE;
wire [31:0] DIVCLK_DIVIDE;
integer duty_cycle;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 28;
dyn_reconf dut(
.RST(RST),
.PWRDWN(PWRDWN),
.vco_period_1000(vco_period_1000),
.DADDR(DADDR),
.DCLK(DCLK),
.DEN(DEN),
.DWE(DWE),
.DI(DI),
.DO(DO),
.DRDY(DRDY),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE_1000(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE_1000(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE_1000(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE_1000(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE_1000(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE_1000(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE_1000(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.CLKFBOUT_MULT_F_1000(CLKFBOUT_MULT_F_1000),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE));
initial begin
$dumpfile("dyn_reconf_tb.vcd");
$dumpvars(0, dyn_reconf_tb);
vco_period_1000 = 32 * 1000;
RST = 0;
DCLK = 0;
DADDR = 7'h00;
DEN = 0;
DWE = 0;
DI = 15'h0000;
pass_count = 0;
fail_count = 0;
#(`CLK_PERIOD * 2);
RST = 1;
#(`CLK_PERIOD * 2);
/* TEST CASES */
if (DO == 15'h0000 && DRDY == 1'b1) begin
$display("PASSED: RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST");
fail_count = fail_count + 1;
end
RST = 0;
#(`CLK_PERIOD * 2);
if (DRDY == 1'b1) begin
$display("PASSED: release RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: release RST");
fail_count = fail_count + 1;
end
/* ClkReg1/2 for CLKOUT0 */
DADDR = 7'h08;
DEN = 1'b1;
DWE = 1'b1;
/* PHASE MUX = 3
* RESERVED = 0
* HIGH TIME = 6
* LOW TIME = 3 */
DI = 16'b011_0_000110_000011;
#(`CLK_PERIOD * 2);
if (DRDY == 1'b0) begin
$display("PASSED: DRDY");
pass_count = pass_count + 1;
end else begin
$display("FAILED: DRDY");
fail_count = fail_count + 1;
end
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
if (DRDY == 1'b1) begin
$display("PASSED: DEN and DWE");
pass_count = pass_count + 1;
end else begin
$display("FAILED: DEN and DWE");
fail_count = fail_count + 1;
end
DEN = 1'b1;
#(`CLK_PERIOD * 2);
if (DRDY == 1'b0 && DO == DI) begin
$display("PASSED: DI and DO");
pass_count = pass_count + 1;
end else begin
$display("FAILED: DI and DO");
fail_count = fail_count + 1;
end
if (CLKOUT0_DIVIDE == 9) begin
$display("PASSED: CLKOUT0 ClkReg1 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT0 ClkReg1 DIVIDE calculation");
fail_count = fail_count + 1;
end
duty_cycle = (6.0 * 1000) / (6.0 + 3.0);
if (CLKOUT0_DUTY_CYCLE == duty_cycle) begin
$display("PASSED: CLKOUT0 ClkReg1 DUTY_CYCLE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT0 ClkReg1 DUTY_CYCLE calculation");
fail_count = fail_count + 1;
end
if (CLKOUT0_PHASE == (((vco_period_1000 / 1000) / 8) * 3)) begin
$display("PASSED: CLKOUT0 ClkReg1 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT0 ClkReg1 PHASE calculation");
fail_count = fail_count + 1;
end
DEN = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
DWE = 1'b1;
DADDR = 7'h09;
/* RESERVED = 0
* FRAC = 000
* FRAC_EN = 0
* FRAC_WF_R = 0
* MX = 2b'00
* EDGE = 0
* NO COUNT = 1
* DELAY TIME = 3 */
DI = 16'b0_000_0_0_00_1_0_00011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
if (CLKOUT0_DIVIDE == 1) begin
$display("PASSED: CLKOUT0 ClkReg2 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT0 ClkReg2 DIVIDE calculation");
fail_count = fail_count + 1;
end
if ((CLKOUT0_DUTY_CYCLE / 1000.0) == 0.5) begin
$display("PASSED: CLKOUT0 ClkReg2 DUTY_CYCLE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT0 ClkReg2 DUTY_CYCLE calculation");
fail_count = fail_count + 1;
end
if (CLKOUT0_PHASE == (((vco_period_1000 / 1000.0) / 8) * 3) + ((vco_period_1000 / 1000.0) * 3)) begin
$display("PASSED: CLKOUT0 ClkReg2 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT0 ClkReg2 PHASE calculation");
fail_count = fail_count + 1;
end
/* CLKOUT1 */
DADDR = 7'h0A;
DEN = 1'b1;
DWE = 1'b1;
/* PHASE MUX = 3
* RESERVED = 0
* HIGH TIME = 6
* LOW TIME = 3 */
DI = 16'b011_0_000110_000011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
#(`CLK_PERIOD * 2);
if (CLKOUT1_DIVIDE == 9) begin
$display("PASSED: CLKOUT1 ClkReg1 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT1 ClkReg1 DIVIDE calculation");
fail_count = fail_count + 1;
end
duty_cycle = (6.0 * 1000) / (6.0 + 3.0);
if (CLKOUT1_DUTY_CYCLE == duty_cycle) begin
$display("PASSED: CLKOUT1 ClkReg1 DUTY_CYCLE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT1 ClkReg1 DUTY_CYCLE calculation");
fail_count = fail_count + 1;
end
if (CLKOUT1_PHASE == (((vco_period_1000 / 1000) / 8) * 3)) begin
$display("PASSED: CLKOUT1 ClkReg1 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT1 ClkReg1 PHASE calculation");
fail_count = fail_count + 1;
end
DEN = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
DWE = 1'b1;
DADDR = 7'h0B;
/* RESERVED = 0
* FRAC = 000
* FRAC_EN = 0
* FRAC_WF_R = 0
* MX = 2b'00
* EDGE = 0
* NO COUNT = 1
* DELAY TIME = 3 */
DI = 16'b0_000_0_0_00_1_0_00011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
if (CLKOUT1_DIVIDE == 1) begin
$display("PASSED: CLKOUT1 ClkReg2 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT1 ClkReg2 DIVIDE calculation");
fail_count = fail_count + 1;
end
if ((CLKOUT1_DUTY_CYCLE / 1000.0) == 0.5) begin
$display("PASSED: CLKOUT1 ClkReg2 DUTY_CYCLE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT1 ClkReg2 DUTY_CYCLE calculation");
fail_count = fail_count + 1;
end
if (CLKOUT1_PHASE == (((vco_period_1000 / 1000.0) / 8) * 3) + ((vco_period_1000 / 1000.0) * 3)) begin
$display("PASSED: CLKOUT1 ClkReg2 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT1 ClkReg2 PHASE calculation");
fail_count = fail_count + 1;
end
/* CLKOUT5 */
DADDR = 7'h06;
DEN = 1'b1;
DWE = 1'b1;
/* PHASE MUX = 3
* RESERVED = 0
* HIGH TIME = 6
* LOW TIME = 3 */
DI = 16'b011_0_000110_000011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
#(`CLK_PERIOD * 2);
if (CLKOUT5_DIVIDE == 9) begin
$display("PASSED: CLKOUT5 ClkReg1 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT5 ClkReg1 DIVIDE calculation");
fail_count = fail_count + 1;
end
duty_cycle = (6.0 * 1000) / (6.0 + 3.0);
if (CLKOUT5_DUTY_CYCLE == duty_cycle) begin
$display("PASSED: CLKOUT5 ClkReg1 DUTY_CYCLE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT5 ClkReg1 DUTY_CYCLE calculation");
fail_count = fail_count + 1;
end
if (CLKOUT5_PHASE == (((vco_period_1000 / 1000) / 8) * 3)) begin
$display("PASSED: CLKOUT5 ClkReg1 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT5 ClkReg1 PHASE calculation");
fail_count = fail_count + 1;
end
DEN = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
DWE = 1'b1;
DADDR = 7'h07;
/* RESERVED = 00
* PHASE_MUX_F_CLKOUT0 = 000
* FRAC_WF_F_CLKOUT0 = 0
* MX = 2b'00
* EDGE = 0
* NO COUNT = 1
* DELAY TIME = 3 */
DI = 16'b00_000_0_00_1_0_00011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
if (CLKOUT5_DIVIDE == 1) begin
$display("PASSED: CLKOUT5 ClkReg2 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT5 ClkReg2 DIVIDE calculation");
fail_count = fail_count + 1;
end
if ((CLKOUT5_DUTY_CYCLE / 1000.0) == 0.5) begin
$display("PASSED: CLKOUT5 ClkReg2 DUTY_CYCLE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT5 ClkReg2 DUTY_CYCLE calculation");
fail_count = fail_count + 1;
end
if (CLKOUT5_PHASE == (((vco_period_1000 / 1000.0) / 8) * 3) + ((vco_period_1000 / 1000.0) * 3)) begin
$display("PASSED: CLKOUT5 ClkReg2 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT5 ClkReg2 PHASE calculation");
fail_count = fail_count + 1;
end
/* CLKFBOUT */
DADDR = 7'h14;
DEN = 1'b1;
DWE = 1'b1;
/* PHASE MUX = 3
* RESERVED = 0
* HIGH TIME = 6
* LOW TIME = 3 */
DI = 16'b011_0_000110_000011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
#(`CLK_PERIOD * 2);
if (CLKFBOUT_MULT_F_1000 == 9000) begin
$display("PASSED: CLKFBOUT ClkReg1 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT ClkReg1 DIVIDE calculation");
fail_count = fail_count + 1;
end
if (CLKFBOUT_PHASE == (((vco_period_1000 / 1000) / 8) * 3)) begin
$display("PASSED: CLKFBOUT ClkReg1 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT ClkReg1 PHASE calculation");
fail_count = fail_count + 1;
end
DEN = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
DWE = 1'b1;
DADDR = 7'h15;
/* RESERVED = 0
* FRAC = 000
* FRAC_EN = 0
* FRAC_WF_R = 0
* MX = 2b'00
* EDGE = 0
* NO COUNT = 1
* DELAY TIME = 3 */
DI = 16'b0_000_0_0_00_1_0_00011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
if (CLKFBOUT_MULT_F_1000 == 1000) begin
$display("PASSED: CLKFBOUT ClkReg2 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT ClkReg2 DIVIDE calculation");
fail_count = fail_count + 1;
end
if (CLKFBOUT_PHASE == (((vco_period_1000 / 1000.0) / 8) * 3) + ((vco_period_1000 / 1000.0) * 3)) begin
$display("PASSED: CLKFBOUT ClkReg2 PHASE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT ClkReg2 PHASE calculation");
fail_count = fail_count + 1;
end
/* DIVCLK_DIVIDE */
DADDR = 7'h16;
DEN = 1'b1;
DWE = 1'b1;
/* RESERVED = 0
* EDGE = 0
* NO COUNT = 0
* HIGH TIME = 3
* LOW TIME = 3 */
DI = 16'b00_0_0_000011_000011;
#(`CLK_PERIOD * 2);
DEN = 1'b0;
DWE = 1'b0;
#(`CLK_PERIOD * 2);
DEN = 1'b1;
#(`CLK_PERIOD * 2);
if (DIVCLK_DIVIDE == 6) begin
$display("PASSED: ClkReg1 DIVIDE calculation");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ClkReg1 DIVIDE calculation");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #`CLK_PERIOD DCLK <= ~DCLK;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_1_V
`define SKY130_FD_SC_HD__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_1_V
|
//-----------------------------------------------------
// Design Name : clk_div_45
// File Name : clk_div_45.v
// Function : Divide by 4.5
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module clk_div_45 (
clk_in, // Input Clock
enable, // Enable is sync with falling edge of clk_in
clk_out // Output Clock
);
// --------------Port Declaration-----------------------
input clk_in ;
input enable ;
output clk_out ;
//--------------Port data type declaration-------------
wire clk_in ;
wire enable ;
wire clk_out ;
//--------------Internal Registers----------------------
reg [3:0] counter1 ;
reg [3:0] counter2 ;
reg toggle1 ;
reg toggle2 ;
//--------------Code Starts Here-----------------------
always @ (posedge clk_in)
if (enable == 1'b0) begin
counter1 <= 4'b0;
toggle1 <= 0;
end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
counter1 <= 4'b0;
toggle1 <= ~toggle1;
end else begin
counter1 <= counter1 + 1;
end
always @ (negedge clk_in)
if (enable == 1'b0) begin
counter2 <= 4'b0;
toggle2 <= 0;
end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4)) begin
counter2 <= 4'b0;
toggle2 <= ~toggle2;
end else begin
counter2 <= counter2 + 1;
end
assign clk_out = (counter1 <3 && counter2 < 3) & enable;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** This Verilog HDL file is used for simulation in chaining DMA design example
//*
//* This file is the top level of the testbench
//*/
module pcie_hip_s4gx_gen2_x4_128_chaining_testbench
;
parameter PIPE_MODE_SIM = 1'b1;
parameter TEST_LEVEL = 1;
parameter NUM_CONNECTED_LANES = 8;
parameter FAST_COUNTERS = 1'b1;
wire bfm_log_common_dummy_out;
wire bfm_req_intf_common_dummy_out;
wire bfm_shmem_common_dummy_out;
wire [ 7: 0] connected_bits;
wire [ 3: 0] connected_lanes;
wire dummy_out;
wire ep_clk250_out;
wire ep_clk500_out;
wire ep_clk_out;
wire ep_core_clk_out;
wire [ 4: 0] ep_ltssm;
wire ep_pclk_in;
wire ep_pld_clk;
wire [ 1: 0] gnd_powerdown4_ext;
wire [ 1: 0] gnd_powerdown5_ext;
wire [ 1: 0] gnd_powerdown6_ext;
wire [ 1: 0] gnd_powerdown7_ext;
wire gnd_rp_rx_in4;
wire gnd_rp_rx_in5;
wire gnd_rp_rx_in6;
wire gnd_rp_rx_in7;
wire gnd_rxpolarity4_ext;
wire gnd_rxpolarity5_ext;
wire gnd_rxpolarity6_ext;
wire gnd_rxpolarity7_ext;
wire gnd_txcompl4_ext;
wire gnd_txcompl5_ext;
wire gnd_txcompl6_ext;
wire gnd_txcompl7_ext;
wire [ 7: 0] gnd_txdata4_ext;
wire [ 7: 0] gnd_txdata5_ext;
wire [ 7: 0] gnd_txdata6_ext;
wire [ 7: 0] gnd_txdata7_ext;
wire gnd_txdatak4_ext;
wire gnd_txdatak5_ext;
wire gnd_txdatak6_ext;
wire gnd_txdatak7_ext;
wire gnd_txdetectrx4_ext;
wire gnd_txdetectrx5_ext;
wire gnd_txdetectrx6_ext;
wire gnd_txdetectrx7_ext;
wire gnd_txelecidle4_ext;
wire gnd_txelecidle5_ext;
wire gnd_txelecidle6_ext;
wire gnd_txelecidle7_ext;
wire [ 3: 0] lane_width_code;
wire local_rstn;
wire ltssm_dummy_out;
wire open_phystatus4_ext;
wire open_phystatus5_ext;
wire open_phystatus6_ext;
wire open_phystatus7_ext;
wire open_rp_tx_out4;
wire open_rp_tx_out5;
wire open_rp_tx_out6;
wire open_rp_tx_out7;
wire [ 7: 0] open_rxdata4_ext;
wire [ 7: 0] open_rxdata5_ext;
wire [ 7: 0] open_rxdata6_ext;
wire [ 7: 0] open_rxdata7_ext;
wire open_rxdatak4_ext;
wire open_rxdatak5_ext;
wire open_rxdatak6_ext;
wire open_rxdatak7_ext;
wire open_rxelecidle4_ext;
wire open_rxelecidle5_ext;
wire open_rxelecidle6_ext;
wire open_rxelecidle7_ext;
wire [ 2: 0] open_rxstatus4_ext;
wire [ 2: 0] open_rxstatus5_ext;
wire [ 2: 0] open_rxstatus6_ext;
wire [ 2: 0] open_rxstatus7_ext;
wire open_rxvalid4_ext;
wire open_rxvalid5_ext;
wire open_rxvalid6_ext;
wire open_rxvalid7_ext;
wire pcie_rstn;
wire [ 3: 0] phy_sel_code;
wire phystatus0_ext;
wire phystatus1_ext;
wire phystatus2_ext;
wire phystatus3_ext;
wire pipe_mode;
wire pipe_mode_sig2;
wire [ 1: 0] powerdown0_ext;
wire [ 1: 0] powerdown1_ext;
wire [ 1: 0] powerdown2_ext;
wire [ 1: 0] powerdown3_ext;
wire rate_ext;
wire [ 3: 0] ref_clk_sel_code;
wire refclk;
wire [ 4: 0] rp_ltssm;
wire rp_pclk;
wire rp_phystatus0_ext;
wire rp_phystatus1_ext;
wire rp_phystatus2_ext;
wire rp_phystatus3_ext;
wire rp_phystatus4_ext;
wire rp_phystatus5_ext;
wire rp_phystatus6_ext;
wire rp_phystatus7_ext;
wire [ 1: 0] rp_powerdown0_ext;
wire [ 1: 0] rp_powerdown1_ext;
wire [ 1: 0] rp_powerdown2_ext;
wire [ 1: 0] rp_powerdown3_ext;
wire [ 1: 0] rp_powerdown4_ext;
wire [ 1: 0] rp_powerdown5_ext;
wire [ 1: 0] rp_powerdown6_ext;
wire [ 1: 0] rp_powerdown7_ext;
wire rp_rate;
wire rp_rstn;
wire rp_rx_in0;
wire rp_rx_in1;
wire rp_rx_in2;
wire rp_rx_in3;
wire [ 7: 0] rp_rxdata0_ext;
wire [ 7: 0] rp_rxdata1_ext;
wire [ 7: 0] rp_rxdata2_ext;
wire [ 7: 0] rp_rxdata3_ext;
wire [ 7: 0] rp_rxdata4_ext;
wire [ 7: 0] rp_rxdata5_ext;
wire [ 7: 0] rp_rxdata6_ext;
wire [ 7: 0] rp_rxdata7_ext;
wire rp_rxdatak0_ext;
wire rp_rxdatak1_ext;
wire rp_rxdatak2_ext;
wire rp_rxdatak3_ext;
wire rp_rxdatak4_ext;
wire rp_rxdatak5_ext;
wire rp_rxdatak6_ext;
wire rp_rxdatak7_ext;
wire rp_rxelecidle0_ext;
wire rp_rxelecidle1_ext;
wire rp_rxelecidle2_ext;
wire rp_rxelecidle3_ext;
wire rp_rxelecidle4_ext;
wire rp_rxelecidle5_ext;
wire rp_rxelecidle6_ext;
wire rp_rxelecidle7_ext;
wire rp_rxpolarity0_ext;
wire rp_rxpolarity1_ext;
wire rp_rxpolarity2_ext;
wire rp_rxpolarity3_ext;
wire rp_rxpolarity4_ext;
wire rp_rxpolarity5_ext;
wire rp_rxpolarity6_ext;
wire rp_rxpolarity7_ext;
wire [ 2: 0] rp_rxstatus0_ext;
wire [ 2: 0] rp_rxstatus1_ext;
wire [ 2: 0] rp_rxstatus2_ext;
wire [ 2: 0] rp_rxstatus3_ext;
wire [ 2: 0] rp_rxstatus4_ext;
wire [ 2: 0] rp_rxstatus5_ext;
wire [ 2: 0] rp_rxstatus6_ext;
wire [ 2: 0] rp_rxstatus7_ext;
wire rp_rxvalid0_ext;
wire rp_rxvalid1_ext;
wire rp_rxvalid2_ext;
wire rp_rxvalid3_ext;
wire rp_rxvalid4_ext;
wire rp_rxvalid5_ext;
wire rp_rxvalid6_ext;
wire rp_rxvalid7_ext;
wire [ 31: 0] rp_test_in;
wire [511: 0] rp_test_out;
wire rp_tx_out0;
wire rp_tx_out1;
wire rp_tx_out2;
wire rp_tx_out3;
wire rp_txcompl0_ext;
wire rp_txcompl1_ext;
wire rp_txcompl2_ext;
wire rp_txcompl3_ext;
wire rp_txcompl4_ext;
wire rp_txcompl5_ext;
wire rp_txcompl6_ext;
wire rp_txcompl7_ext;
wire [ 7: 0] rp_txdata0_ext;
wire [ 7: 0] rp_txdata1_ext;
wire [ 7: 0] rp_txdata2_ext;
wire [ 7: 0] rp_txdata3_ext;
wire [ 7: 0] rp_txdata4_ext;
wire [ 7: 0] rp_txdata5_ext;
wire [ 7: 0] rp_txdata6_ext;
wire [ 7: 0] rp_txdata7_ext;
wire rp_txdatak0_ext;
wire rp_txdatak1_ext;
wire rp_txdatak2_ext;
wire rp_txdatak3_ext;
wire rp_txdatak4_ext;
wire rp_txdatak5_ext;
wire rp_txdatak6_ext;
wire rp_txdatak7_ext;
wire rp_txdetectrx0_ext;
wire rp_txdetectrx1_ext;
wire rp_txdetectrx2_ext;
wire rp_txdetectrx3_ext;
wire rp_txdetectrx4_ext;
wire rp_txdetectrx5_ext;
wire rp_txdetectrx6_ext;
wire rp_txdetectrx7_ext;
wire rp_txelecidle0_ext;
wire rp_txelecidle1_ext;
wire rp_txelecidle2_ext;
wire rp_txelecidle3_ext;
wire rp_txelecidle4_ext;
wire rp_txelecidle5_ext;
wire rp_txelecidle6_ext;
wire rp_txelecidle7_ext;
wire rx_in0;
wire rx_in1;
wire rx_in2;
wire rx_in3;
wire [ 7: 0] rxdata0_ext;
wire [ 7: 0] rxdata1_ext;
wire [ 7: 0] rxdata2_ext;
wire [ 7: 0] rxdata3_ext;
wire rxdatak0_ext;
wire rxdatak1_ext;
wire rxdatak2_ext;
wire rxdatak3_ext;
wire rxelecidle0_ext;
wire rxelecidle1_ext;
wire rxelecidle2_ext;
wire rxelecidle3_ext;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire [ 2: 0] rxstatus0_ext;
wire [ 2: 0] rxstatus1_ext;
wire [ 2: 0] rxstatus2_ext;
wire [ 2: 0] rxstatus3_ext;
wire rxvalid0_ext;
wire rxvalid1_ext;
wire rxvalid2_ext;
wire rxvalid3_ext;
wire [ 5: 0] swdn_out;
wire [ 39: 0] test_in;
wire [ 8: 0] test_out;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx0_ext;
wire txdetectrx1_ext;
wire txdetectrx2_ext;
wire txdetectrx3_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
assign gnd_rp_rx_in4 = 1;
assign gnd_rp_rx_in5 = 1;
assign gnd_rp_rx_in6 = 1;
assign gnd_rp_rx_in7 = 1;
assign ep_ltssm = test_out[4 : 0];
assign rp_ltssm = rp_test_out[324 : 320];
assign gnd_txdata4_ext = 0;
assign gnd_txdatak4_ext = 0;
assign gnd_txdetectrx4_ext = 0;
assign gnd_txelecidle4_ext = 0;
assign gnd_rxpolarity4_ext = 0;
assign gnd_txcompl4_ext = 0;
assign gnd_powerdown4_ext = 0;
assign gnd_txdata5_ext = 0;
assign gnd_txdatak5_ext = 0;
assign gnd_txdetectrx5_ext = 0;
assign gnd_txelecidle5_ext = 0;
assign gnd_rxpolarity5_ext = 0;
assign gnd_txcompl5_ext = 0;
assign gnd_powerdown5_ext = 0;
assign gnd_txdata6_ext = 0;
assign gnd_txdatak6_ext = 0;
assign gnd_txdetectrx6_ext = 0;
assign gnd_txelecidle6_ext = 0;
assign gnd_rxpolarity6_ext = 0;
assign gnd_txcompl6_ext = 0;
assign gnd_powerdown6_ext = 0;
assign gnd_txdata7_ext = 0;
assign gnd_txdatak7_ext = 0;
assign gnd_txdetectrx7_ext = 0;
assign gnd_txelecidle7_ext = 0;
assign gnd_rxpolarity7_ext = 0;
assign gnd_txcompl7_ext = 0;
assign gnd_powerdown7_ext = 0;
assign txdetectrx1_ext = txdetectrx0_ext;
assign powerdown1_ext = powerdown0_ext;
assign txdetectrx2_ext = txdetectrx0_ext;
assign powerdown2_ext = powerdown0_ext;
assign txdetectrx3_ext = txdetectrx0_ext;
assign powerdown3_ext = powerdown0_ext;
assign ep_pld_clk = ep_core_clk_out;
assign ep_clk_out = ep_pclk_in;
assign ep_pclk_in = (rate_ext == 1) ? ep_clk500_out : ep_clk250_out;
assign rp_pclk = (rp_rate == 1) ? ep_clk500_out : ep_clk250_out;
assign rx_in0 = (connected_bits[0] == 1'b1) ? rp_tx_out0 : 1;
assign rp_rx_in0 = tx_out0;
assign rx_in1 = (connected_bits[1] == 1'b1) ? rp_tx_out1 : 1;
assign rp_rx_in1 = tx_out1;
assign rx_in2 = (connected_bits[2] == 1'b1) ? rp_tx_out2 : 1;
assign rp_rx_in2 = tx_out2;
assign rx_in3 = (connected_bits[3] == 1'b1) ? rp_tx_out3 : 1;
assign rp_rx_in3 = tx_out3;
assign local_rstn = 1;
assign test_in[2 : 1] = 0;
assign test_in[8 : 4] = 0;
assign test_in[9] = 1;
assign test_in[39 : 10] = 0;
//Bit 3: Work around simulation Reciever Detect issue for Stratix IV GX
assign test_in[3] = ~pipe_mode;
//Bit 0: Speed up the simulation but making counters faster than normal
assign test_in[0] = FAST_COUNTERS;
//Compute number of lanes to hookup
assign connected_lanes = NUM_CONNECTED_LANES;
assign connected_bits = connected_lanes[3] ? 8'hFF : connected_lanes[2] ? 8'h0F : connected_lanes[1] ? 8'h03 : 8'h01;
assign rp_test_in[31 : 8] = 0;
assign rp_test_in[6] = 0;
assign rp_test_in[4] = 0;
assign rp_test_in[2 : 1] = 0;
//Bit 0: Speed up the simulation but making counters faster than normal
assign rp_test_in[0] = 1;
//Bit 3: Forces all lanes to detect the receiver
//For Stratix GX we must force but can use Rx Detect for
//the generic PIPE interface
assign rp_test_in[3] = ~pipe_mode;
//Bit 5: Disable polling.compliance
assign rp_test_in[5] = 1;
//Bit 7: Disable any entrance to low power link states (for Stratix GX)
//For Stratix GX we must disable but can use Low Power for
//the generic PIPE interface
assign rp_test_in[7] = ~pipe_mode;
//When the phy is Stratix GX we can allow the pipe_mode to be disabled
//otherwise we need to force pipe_mode on
assign pipe_mode_sig2 = PIPE_MODE_SIM;
assign pipe_mode = ((phy_sel_code == 4'h0) || (phy_sel_code == 4'h2) || (phy_sel_code == 4'h6) || (phy_sel_code == 4'h7)) ? pipe_mode_sig2 : 1'b1;
altpcietb_bfm_rp_top_x8_pipen1b rp
(
.clk250_in (ep_clk250_out),
.clk500_in (ep_clk500_out),
.local_rstn (local_rstn),
.pcie_rstn (rp_rstn),
.phystatus0_ext (rp_phystatus0_ext),
.phystatus1_ext (rp_phystatus1_ext),
.phystatus2_ext (rp_phystatus2_ext),
.phystatus3_ext (rp_phystatus3_ext),
.phystatus4_ext (rp_phystatus4_ext),
.phystatus5_ext (rp_phystatus5_ext),
.phystatus6_ext (rp_phystatus6_ext),
.phystatus7_ext (rp_phystatus7_ext),
.pipe_mode (pipe_mode),
.powerdown0_ext (rp_powerdown0_ext),
.powerdown1_ext (rp_powerdown1_ext),
.powerdown2_ext (rp_powerdown2_ext),
.powerdown3_ext (rp_powerdown3_ext),
.powerdown4_ext (rp_powerdown4_ext),
.powerdown5_ext (rp_powerdown5_ext),
.powerdown6_ext (rp_powerdown6_ext),
.powerdown7_ext (rp_powerdown7_ext),
.rate_ext (rp_rate),
.rx_in0 (rp_rx_in0),
.rx_in1 (rp_rx_in1),
.rx_in2 (rp_rx_in2),
.rx_in3 (rp_rx_in3),
.rx_in4 (gnd_rp_rx_in4),
.rx_in5 (gnd_rp_rx_in5),
.rx_in6 (gnd_rp_rx_in6),
.rx_in7 (gnd_rp_rx_in7),
.rxdata0_ext (rp_rxdata0_ext),
.rxdata1_ext (rp_rxdata1_ext),
.rxdata2_ext (rp_rxdata2_ext),
.rxdata3_ext (rp_rxdata3_ext),
.rxdata4_ext (rp_rxdata4_ext),
.rxdata5_ext (rp_rxdata5_ext),
.rxdata6_ext (rp_rxdata6_ext),
.rxdata7_ext (rp_rxdata7_ext),
.rxdatak0_ext (rp_rxdatak0_ext),
.rxdatak1_ext (rp_rxdatak1_ext),
.rxdatak2_ext (rp_rxdatak2_ext),
.rxdatak3_ext (rp_rxdatak3_ext),
.rxdatak4_ext (rp_rxdatak4_ext),
.rxdatak5_ext (rp_rxdatak5_ext),
.rxdatak6_ext (rp_rxdatak6_ext),
.rxdatak7_ext (rp_rxdatak7_ext),
.rxelecidle0_ext (rp_rxelecidle0_ext),
.rxelecidle1_ext (rp_rxelecidle1_ext),
.rxelecidle2_ext (rp_rxelecidle2_ext),
.rxelecidle3_ext (rp_rxelecidle3_ext),
.rxelecidle4_ext (rp_rxelecidle4_ext),
.rxelecidle5_ext (rp_rxelecidle5_ext),
.rxelecidle6_ext (rp_rxelecidle6_ext),
.rxelecidle7_ext (rp_rxelecidle7_ext),
.rxpolarity0_ext (rp_rxpolarity0_ext),
.rxpolarity1_ext (rp_rxpolarity1_ext),
.rxpolarity2_ext (rp_rxpolarity2_ext),
.rxpolarity3_ext (rp_rxpolarity3_ext),
.rxpolarity4_ext (rp_rxpolarity4_ext),
.rxpolarity5_ext (rp_rxpolarity5_ext),
.rxpolarity6_ext (rp_rxpolarity6_ext),
.rxpolarity7_ext (rp_rxpolarity7_ext),
.rxstatus0_ext (rp_rxstatus0_ext),
.rxstatus1_ext (rp_rxstatus1_ext),
.rxstatus2_ext (rp_rxstatus2_ext),
.rxstatus3_ext (rp_rxstatus3_ext),
.rxstatus4_ext (rp_rxstatus4_ext),
.rxstatus5_ext (rp_rxstatus5_ext),
.rxstatus6_ext (rp_rxstatus6_ext),
.rxstatus7_ext (rp_rxstatus7_ext),
.rxvalid0_ext (rp_rxvalid0_ext),
.rxvalid1_ext (rp_rxvalid1_ext),
.rxvalid2_ext (rp_rxvalid2_ext),
.rxvalid3_ext (rp_rxvalid3_ext),
.rxvalid4_ext (rp_rxvalid4_ext),
.rxvalid5_ext (rp_rxvalid5_ext),
.rxvalid6_ext (rp_rxvalid6_ext),
.rxvalid7_ext (rp_rxvalid7_ext),
.swdn_out (swdn_out),
.test_in (rp_test_in),
.test_out (rp_test_out),
.tx_out0 (rp_tx_out0),
.tx_out1 (rp_tx_out1),
.tx_out2 (rp_tx_out2),
.tx_out3 (rp_tx_out3),
.tx_out4 (open_rp_tx_out4),
.tx_out5 (open_rp_tx_out5),
.tx_out6 (open_rp_tx_out6),
.tx_out7 (open_rp_tx_out7),
.txcompl0_ext (rp_txcompl0_ext),
.txcompl1_ext (rp_txcompl1_ext),
.txcompl2_ext (rp_txcompl2_ext),
.txcompl3_ext (rp_txcompl3_ext),
.txcompl4_ext (rp_txcompl4_ext),
.txcompl5_ext (rp_txcompl5_ext),
.txcompl6_ext (rp_txcompl6_ext),
.txcompl7_ext (rp_txcompl7_ext),
.txdata0_ext (rp_txdata0_ext),
.txdata1_ext (rp_txdata1_ext),
.txdata2_ext (rp_txdata2_ext),
.txdata3_ext (rp_txdata3_ext),
.txdata4_ext (rp_txdata4_ext),
.txdata5_ext (rp_txdata5_ext),
.txdata6_ext (rp_txdata6_ext),
.txdata7_ext (rp_txdata7_ext),
.txdatak0_ext (rp_txdatak0_ext),
.txdatak1_ext (rp_txdatak1_ext),
.txdatak2_ext (rp_txdatak2_ext),
.txdatak3_ext (rp_txdatak3_ext),
.txdatak4_ext (rp_txdatak4_ext),
.txdatak5_ext (rp_txdatak5_ext),
.txdatak6_ext (rp_txdatak6_ext),
.txdatak7_ext (rp_txdatak7_ext),
.txdetectrx0_ext (rp_txdetectrx0_ext),
.txdetectrx1_ext (rp_txdetectrx1_ext),
.txdetectrx2_ext (rp_txdetectrx2_ext),
.txdetectrx3_ext (rp_txdetectrx3_ext),
.txdetectrx4_ext (rp_txdetectrx4_ext),
.txdetectrx5_ext (rp_txdetectrx5_ext),
.txdetectrx6_ext (rp_txdetectrx6_ext),
.txdetectrx7_ext (rp_txdetectrx7_ext),
.txelecidle0_ext (rp_txelecidle0_ext),
.txelecidle1_ext (rp_txelecidle1_ext),
.txelecidle2_ext (rp_txelecidle2_ext),
.txelecidle3_ext (rp_txelecidle3_ext),
.txelecidle4_ext (rp_txelecidle4_ext),
.txelecidle5_ext (rp_txelecidle5_ext),
.txelecidle6_ext (rp_txelecidle6_ext),
.txelecidle7_ext (rp_txelecidle7_ext)
);
altpcietb_bfm_driver_chaining drvr
(
.INTA (swdn_out[0]),
.INTB (swdn_out[1]),
.INTC (swdn_out[2]),
.INTD (swdn_out[3]),
.clk_in (rp_pclk),
.dummy_out (dummy_out),
.rstn (pcie_rstn)
);
defparam drvr.TEST_LEVEL = 1;
altpcietb_ltssm_mon ltssm_mon
(
.dummy_out (ltssm_dummy_out),
.ep_ltssm (ep_ltssm),
.rp_clk (rp_pclk),
.rp_ltssm (rp_ltssm),
.rstn (pcie_rstn)
);
pcie_hip_s4gx_gen2_x4_128_example_chaining_pipen1b ep
(
.clk250_out (ep_clk250_out),
.clk500_out (ep_clk500_out),
.core_clk_out (ep_core_clk_out),
.free_100MHz (refclk),
.lane_width_code (lane_width_code),
.local_rstn (local_rstn),
.pcie_rstn (pcie_rstn),
.pclk_in (ep_pclk_in),
.phy_sel_code (phy_sel_code),
.phystatus_ext (phystatus0_ext),
.pipe_mode (pipe_mode),
.pld_clk (ep_pld_clk),
.powerdown_ext (powerdown0_ext),
.rate_ext (rate_ext),
.ref_clk_sel_code (ref_clk_sel_code),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.test_in (test_in),
.test_out_icm (test_out),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdetectrx_ext (txdetectrx0_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext)
);
altpcietb_bfm_log_common bfm_log_common
(
.dummy_out (bfm_log_common_dummy_out)
);
altpcietb_bfm_req_intf_common bfm_req_intf_common
(
.dummy_out (bfm_req_intf_common_dummy_out)
);
altpcietb_bfm_shmem_common bfm_shmem_common
(
.dummy_out (bfm_shmem_common_dummy_out)
);
altpcietb_pipe_phy lane0
(
.A_lane_conn (connected_bits[0]),
.A_phystatus (phystatus0_ext),
.A_powerdown (powerdown0_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata0_ext),
.A_rxdatak (rxdatak0_ext),
.A_rxelecidle (rxelecidle0_ext),
.A_rxpolarity (rxpolarity0_ext),
.A_rxstatus (rxstatus0_ext),
.A_rxvalid (rxvalid0_ext),
.A_txcompl (txcompl0_ext),
.A_txdata (txdata0_ext),
.A_txdatak (txdatak0_ext),
.A_txdetectrx (txdetectrx0_ext),
.A_txelecidle (txelecidle0_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus0_ext),
.B_powerdown (rp_powerdown0_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata0_ext),
.B_rxdatak (rp_rxdatak0_ext),
.B_rxelecidle (rp_rxelecidle0_ext),
.B_rxpolarity (rp_rxpolarity0_ext),
.B_rxstatus (rp_rxstatus0_ext),
.B_rxvalid (rp_rxvalid0_ext),
.B_txcompl (rp_txcompl0_ext),
.B_txdata (rp_txdata0_ext),
.B_txdatak (rp_txdatak0_ext),
.B_txdetectrx (rp_txdetectrx0_ext),
.B_txelecidle (rp_txelecidle0_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane0.APIPE_WIDTH = 8,
lane0.BPIPE_WIDTH = 8,
lane0.LANE_NUM = 0;
altpcietb_pipe_phy lane1
(
.A_lane_conn (connected_bits[1]),
.A_phystatus (phystatus1_ext),
.A_powerdown (powerdown1_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata1_ext),
.A_rxdatak (rxdatak1_ext),
.A_rxelecidle (rxelecidle1_ext),
.A_rxpolarity (rxpolarity1_ext),
.A_rxstatus (rxstatus1_ext),
.A_rxvalid (rxvalid1_ext),
.A_txcompl (txcompl1_ext),
.A_txdata (txdata1_ext),
.A_txdatak (txdatak1_ext),
.A_txdetectrx (txdetectrx1_ext),
.A_txelecidle (txelecidle1_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus1_ext),
.B_powerdown (rp_powerdown1_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata1_ext),
.B_rxdatak (rp_rxdatak1_ext),
.B_rxelecidle (rp_rxelecidle1_ext),
.B_rxpolarity (rp_rxpolarity1_ext),
.B_rxstatus (rp_rxstatus1_ext),
.B_rxvalid (rp_rxvalid1_ext),
.B_txcompl (rp_txcompl1_ext),
.B_txdata (rp_txdata1_ext),
.B_txdatak (rp_txdatak1_ext),
.B_txdetectrx (rp_txdetectrx1_ext),
.B_txelecidle (rp_txelecidle1_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane1.APIPE_WIDTH = 8,
lane1.BPIPE_WIDTH = 8,
lane1.LANE_NUM = 1;
altpcietb_pipe_phy lane2
(
.A_lane_conn (connected_bits[2]),
.A_phystatus (phystatus2_ext),
.A_powerdown (powerdown2_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata2_ext),
.A_rxdatak (rxdatak2_ext),
.A_rxelecidle (rxelecidle2_ext),
.A_rxpolarity (rxpolarity2_ext),
.A_rxstatus (rxstatus2_ext),
.A_rxvalid (rxvalid2_ext),
.A_txcompl (txcompl2_ext),
.A_txdata (txdata2_ext),
.A_txdatak (txdatak2_ext),
.A_txdetectrx (txdetectrx2_ext),
.A_txelecidle (txelecidle2_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus2_ext),
.B_powerdown (rp_powerdown2_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata2_ext),
.B_rxdatak (rp_rxdatak2_ext),
.B_rxelecidle (rp_rxelecidle2_ext),
.B_rxpolarity (rp_rxpolarity2_ext),
.B_rxstatus (rp_rxstatus2_ext),
.B_rxvalid (rp_rxvalid2_ext),
.B_txcompl (rp_txcompl2_ext),
.B_txdata (rp_txdata2_ext),
.B_txdatak (rp_txdatak2_ext),
.B_txdetectrx (rp_txdetectrx2_ext),
.B_txelecidle (rp_txelecidle2_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane2.APIPE_WIDTH = 8,
lane2.BPIPE_WIDTH = 8,
lane2.LANE_NUM = 2;
altpcietb_pipe_phy lane3
(
.A_lane_conn (connected_bits[3]),
.A_phystatus (phystatus3_ext),
.A_powerdown (powerdown3_ext),
.A_rate (rate_ext),
.A_rxdata (rxdata3_ext),
.A_rxdatak (rxdatak3_ext),
.A_rxelecidle (rxelecidle3_ext),
.A_rxpolarity (rxpolarity3_ext),
.A_rxstatus (rxstatus3_ext),
.A_rxvalid (rxvalid3_ext),
.A_txcompl (txcompl3_ext),
.A_txdata (txdata3_ext),
.A_txdatak (txdatak3_ext),
.A_txdetectrx (txdetectrx3_ext),
.A_txelecidle (txelecidle3_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus3_ext),
.B_powerdown (rp_powerdown3_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata3_ext),
.B_rxdatak (rp_rxdatak3_ext),
.B_rxelecidle (rp_rxelecidle3_ext),
.B_rxpolarity (rp_rxpolarity3_ext),
.B_rxstatus (rp_rxstatus3_ext),
.B_rxvalid (rp_rxvalid3_ext),
.B_txcompl (rp_txcompl3_ext),
.B_txdata (rp_txdata3_ext),
.B_txdatak (rp_txdatak3_ext),
.B_txdetectrx (rp_txdetectrx3_ext),
.B_txelecidle (rp_txelecidle3_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane3.APIPE_WIDTH = 8,
lane3.BPIPE_WIDTH = 8,
lane3.LANE_NUM = 3;
altpcietb_pipe_phy lane4
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus4_ext),
.A_powerdown (gnd_powerdown4_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata4_ext),
.A_rxdatak (open_rxdatak4_ext),
.A_rxelecidle (open_rxelecidle4_ext),
.A_rxpolarity (gnd_rxpolarity4_ext),
.A_rxstatus (open_rxstatus4_ext),
.A_rxvalid (open_rxvalid4_ext),
.A_txcompl (gnd_txcompl4_ext),
.A_txdata (gnd_txdata4_ext),
.A_txdatak (gnd_txdatak4_ext),
.A_txdetectrx (gnd_txdetectrx4_ext),
.A_txelecidle (gnd_txelecidle4_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus4_ext),
.B_powerdown (rp_powerdown4_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata4_ext),
.B_rxdatak (rp_rxdatak4_ext),
.B_rxelecidle (rp_rxelecidle4_ext),
.B_rxpolarity (rp_rxpolarity4_ext),
.B_rxstatus (rp_rxstatus4_ext),
.B_rxvalid (rp_rxvalid4_ext),
.B_txcompl (rp_txcompl4_ext),
.B_txdata (rp_txdata4_ext),
.B_txdatak (rp_txdatak4_ext),
.B_txdetectrx (rp_txdetectrx4_ext),
.B_txelecidle (rp_txelecidle4_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane4.APIPE_WIDTH = 8,
lane4.BPIPE_WIDTH = 8,
lane4.LANE_NUM = 4;
altpcietb_pipe_phy lane5
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus5_ext),
.A_powerdown (gnd_powerdown5_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata5_ext),
.A_rxdatak (open_rxdatak5_ext),
.A_rxelecidle (open_rxelecidle5_ext),
.A_rxpolarity (gnd_rxpolarity5_ext),
.A_rxstatus (open_rxstatus5_ext),
.A_rxvalid (open_rxvalid5_ext),
.A_txcompl (gnd_txcompl5_ext),
.A_txdata (gnd_txdata5_ext),
.A_txdatak (gnd_txdatak5_ext),
.A_txdetectrx (gnd_txdetectrx5_ext),
.A_txelecidle (gnd_txelecidle5_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus5_ext),
.B_powerdown (rp_powerdown5_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata5_ext),
.B_rxdatak (rp_rxdatak5_ext),
.B_rxelecidle (rp_rxelecidle5_ext),
.B_rxpolarity (rp_rxpolarity5_ext),
.B_rxstatus (rp_rxstatus5_ext),
.B_rxvalid (rp_rxvalid5_ext),
.B_txcompl (rp_txcompl5_ext),
.B_txdata (rp_txdata5_ext),
.B_txdatak (rp_txdatak5_ext),
.B_txdetectrx (rp_txdetectrx5_ext),
.B_txelecidle (rp_txelecidle5_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane5.APIPE_WIDTH = 8,
lane5.BPIPE_WIDTH = 8,
lane5.LANE_NUM = 5;
altpcietb_pipe_phy lane6
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus6_ext),
.A_powerdown (gnd_powerdown6_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata6_ext),
.A_rxdatak (open_rxdatak6_ext),
.A_rxelecidle (open_rxelecidle6_ext),
.A_rxpolarity (gnd_rxpolarity6_ext),
.A_rxstatus (open_rxstatus6_ext),
.A_rxvalid (open_rxvalid6_ext),
.A_txcompl (gnd_txcompl6_ext),
.A_txdata (gnd_txdata6_ext),
.A_txdatak (gnd_txdatak6_ext),
.A_txdetectrx (gnd_txdetectrx6_ext),
.A_txelecidle (gnd_txelecidle6_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus6_ext),
.B_powerdown (rp_powerdown6_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata6_ext),
.B_rxdatak (rp_rxdatak6_ext),
.B_rxelecidle (rp_rxelecidle6_ext),
.B_rxpolarity (rp_rxpolarity6_ext),
.B_rxstatus (rp_rxstatus6_ext),
.B_rxvalid (rp_rxvalid6_ext),
.B_txcompl (rp_txcompl6_ext),
.B_txdata (rp_txdata6_ext),
.B_txdatak (rp_txdatak6_ext),
.B_txdetectrx (rp_txdetectrx6_ext),
.B_txelecidle (rp_txelecidle6_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane6.APIPE_WIDTH = 8,
lane6.BPIPE_WIDTH = 8,
lane6.LANE_NUM = 6;
altpcietb_pipe_phy lane7
(
.A_lane_conn (1'b0),
.A_phystatus (open_phystatus7_ext),
.A_powerdown (gnd_powerdown7_ext),
.A_rate (rate_ext),
.A_rxdata (open_rxdata7_ext),
.A_rxdatak (open_rxdatak7_ext),
.A_rxelecidle (open_rxelecidle7_ext),
.A_rxpolarity (gnd_rxpolarity7_ext),
.A_rxstatus (open_rxstatus7_ext),
.A_rxvalid (open_rxvalid7_ext),
.A_txcompl (gnd_txcompl7_ext),
.A_txdata (gnd_txdata7_ext),
.A_txdatak (gnd_txdatak7_ext),
.A_txdetectrx (gnd_txdetectrx7_ext),
.A_txelecidle (gnd_txelecidle7_ext),
.B_lane_conn (1'b1),
.B_phystatus (rp_phystatus7_ext),
.B_powerdown (rp_powerdown7_ext),
.B_rate (rp_rate),
.B_rxdata (rp_rxdata7_ext),
.B_rxdatak (rp_rxdatak7_ext),
.B_rxelecidle (rp_rxelecidle7_ext),
.B_rxpolarity (rp_rxpolarity7_ext),
.B_rxstatus (rp_rxstatus7_ext),
.B_rxvalid (rp_rxvalid7_ext),
.B_txcompl (rp_txcompl7_ext),
.B_txdata (rp_txdata7_ext),
.B_txdatak (rp_txdatak7_ext),
.B_txdetectrx (rp_txdetectrx7_ext),
.B_txelecidle (rp_txelecidle7_ext),
.pclk_a (ep_clk_out),
.pclk_b (rp_pclk),
.pipe_mode (pipe_mode),
.resetn (pcie_rstn)
);
defparam lane7.APIPE_WIDTH = 8,
lane7.BPIPE_WIDTH = 8,
lane7.LANE_NUM = 7;
altpcietb_rst_clk rst_clk_gen
(
.ep_core_clk_out (ep_core_clk_out),
.pcie_rstn (pcie_rstn),
.ref_clk_out (refclk),
.ref_clk_sel_code (ref_clk_sel_code),
.rp_rstn (rp_rstn)
);
endmodule
|
/****************************************************************************************
*
* File Name: ddr.v
* Version: 6.00
* Model: BUS Functional
*
* Dependencies: ddr_parameters.v
*
* Description: Micron SDRAM DDR (Double Data Rate)
*
* Limitation: - Doesn't check for 8K-cycle refresh.
* - Doesn't check power-down entry/exit
* - Doesn't check self-refresh entry/exit.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
* - Model assume Clk and Clk# crossing at both edge
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --- ------ ---------- ---------------------------------------
* 2.1 SPH 03/19/2002 - Second Release
* - Fix tWR and several incompatability
* between different simulators
* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
* - Added tDQSH and tDQSL timing checks.
* 3.1 CAH 05/28/2003 - update all models to release version 3.1
* (no changes to this model)
* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
* - Fixed tWTR check
* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade
* - Fixed mem_sizes parameter
* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
* - Changed Dq_buf size to [15:0]
* 5.0 JMK 06/16/2004 - Added read to write checking.
* - Added read with precharge truncation to write checking.
* - Added associative memory array to reduce memory consumption.
* - Added checking for required DQS edges during write.
* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
* - Fixed wdqs_valid window.
* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
* - Added tRFC checking during Load Mode and Precharge.
* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
* JMK 02/11/2005 - Changed the display format for numbers to hex.
* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
* - Renamed parameters file with .vh extension.
* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
* - Added x32 functionality
* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model
* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1ns / 1ps
module ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);
`include "ddr_parameters.vh"
// Port Declarations
input Clk;
input Clk_n;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Ba;
input [ADDR_BITS - 1 : 0] Addr;
input [DM_BITS - 1 : 0] Dm;
inout [DQ_BITS - 1 : 0] Dq;
inout [DQS_BITS - 1 : 0] Dqs;
// Internal Wires (fixed width)
wire [31 : 0] Dq_in;
wire [3 : 0] Dqs_in;
wire [3 : 0] Dm_in;
assign Dq_in [DQ_BITS - 1 : 0] = Dq;
assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
assign Dm_in [DM_BITS - 1 : 0] = Dm;
// Data pair
reg [31 : 0] dq_rise;
reg [3 : 0] dm_rise;
reg [31 : 0] dq_fall;
reg [3 : 0] dm_fall;
reg [7 : 0] dm_pair;
reg [31 : 0] Dq_buf;
// Mode Register
reg [ADDR_BITS - 1 : 0] Mode_reg;
// Internal System Clock
reg CkeZ, Sys_clk;
// Internal Dqs initialize
reg Dqs_int;
// Dqs buffer
reg [DQS_BITS - 1 : 0] Dqs_out;
// Dq buffer
reg [DQ_BITS - 1 : 0] Dq_out;
// Read pipeline variables
reg Read_cmnd [0 : 6];
reg [1 : 0] Read_bank [0 : 6];
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
// Write pipeline variables
reg Write_cmnd [0 : 3];
reg [1 : 0] Write_bank [0 : 3];
reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
// Auto precharge variables
reg Read_precharge [0 : 3];
reg Write_precharge [0 : 3];
integer Count_precharge [0 : 3];
// Manual precharge variables
reg A10_precharge [0 : 6];
reg [1 : 0] Bank_precharge [0 : 6];
reg Cmnd_precharge [0 : 6];
// Burst terminate variables
reg Cmnd_bst [0 : 6];
// Memory Banks
`ifdef FULL_MEM
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<full_mem_bits)-1];
`else
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<part_mem_bits)-1];
reg [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
reg [part_mem_bits : 0] mem_used;
initial mem_used = 0;
`endif
// Dqs edge checking
integer i;
reg [3 :0] expect_pos_dqs;
reg [3 :0] expect_neg_dqs;
// Burst counter
reg [COL_BITS - 1 : 0] Burst_counter;
// Precharge variables
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;
// Activate variables
reg Act_b0, Act_b1, Act_b2, Act_b3;
// Data IO variables
reg Data_in_enable;
reg Data_out_enable;
// Internal address mux variables
reg [1 : 0] Prev_bank;
reg [1 : 0] Bank_addr;
reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
reg [ADDR_BITS - 1 : 0] Rows_addr;
reg [ADDR_BITS - 1 : 0] B0_row_addr;
reg [ADDR_BITS - 1 : 0] B1_row_addr;
reg [ADDR_BITS - 1 : 0] B2_row_addr;
reg [ADDR_BITS - 1 : 0] B3_row_addr;
// DLL Reset variable
reg DLL_enable;
reg DLL_reset;
reg DLL_done;
integer DLL_count;
integer aref_count;
integer Prech_count;
reg power_up_done;
// Write DQS for tDSS, tDSH, tDQSH, tDQSL checks
wire wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[0] & ~Ba[1];
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire [3:0] burst_length = 1 << (Mode_reg[2:0]);
reg [3:0] read_precharge_truncation;
// CAS Latency Decode
wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];
// DQS Buffer
assign Dqs = Dqs_out;
// DQ Buffer
assign Dq = Dq_out;
// Timing Check
time MRD_chk;
time RFC_chk;
time RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
time WR_chk0, WR_chk1, WR_chk2, WR_chk3;
initial begin
CkeZ = 1'b0;
Sys_clk = 1'b0;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
Dqs_int = 1'b0;
Dqs_out = {DQS_BITS{1'bz}};
Dq_out = {DQ_BITS{1'bz}};
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
DLL_enable = 1'b0;
DLL_reset = 1'b0;
DLL_done = 1'b0;
DLL_count = 0;
aref_count = 0;
Prech_count = 0;
power_up_done = 0;
MRD_chk = 0;
RFC_chk = 0;
RRD_chk = 0;
Mode_reg = 0; // added by lekernel to suppress warnings during first commands
{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
{RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0;
{RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;
{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
{WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;
$timeformat (-9, 3, " ns", 12);
end
// System Clock
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
// Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
always @(Cke) begin
if (Cke === 1'b1) begin
if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin
$display ("%m: at time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $time);
$display ("%m: when the Clock Enable is brought High.");
end
end
end
// Check the initialization sequence
initial begin
@ (posedge Cke) begin
@ (posedge DLL_enable) begin
aref_count = 0;
@ (posedge DLL_reset) begin
@ (Prech_count) begin
if (aref_count >= 2) begin
if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end else begin
aref_count = 0;
@ (aref_count >= 2) begin
if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end
end
end
end
end
end
end
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
mem_array[addr] = data;
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i === mem_used) begin
if (i === (1<<part_mem_bits)) begin
$display ("%m: At time %t ERROR: Memory overflow.\n Write to Address %h with Data %h will be lost.\n You must increase the part_mem_bits parameter or define FULL_MEM.", $time, addr, data);
end else begin
mem_used = mem_used + 1;
addr_array[i] = addr;
end
end
mem_array[i] = data;
`endif
end
endtask
// Read Memory
task read_mem;
input [full_mem_bits - 1 : 0] addr;
output [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
data = mem_array[addr];
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i <= mem_used) begin
data = mem_array[i];
end
`endif
end
endtask
// Burst Decode
task Burst_Decode;
begin
// Advance Burst Counter
if (Burst_counter < burst_length) begin
Burst_counter = Burst_counter + 1;
end
// Burst Type
if (Mode_reg[3] === 1'b0) begin // Sequential Burst
Cols_temp = Cols_addr + 1;
end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
end
// Burst Length
if (burst_length === 2) begin
Cols_addr [0] = Cols_temp [0];
end else if (burst_length === 4) begin
Cols_addr [1 : 0] = Cols_temp [1 : 0];
end else if (burst_length === 8) begin
Cols_addr [2 : 0] = Cols_temp [2 : 0];
end else begin
Cols_addr = Cols_temp;
end
// Data Counter
if (Burst_counter >= burst_length) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
read_precharge_truncation = 4'h0;
end
end
endtask
// Manual Precharge Pipeline
task Manual_Precharge_Pipeline;
begin
// A10 Precharge Pipeline
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = A10_precharge[4];
A10_precharge[4] = A10_precharge[5];
A10_precharge[5] = A10_precharge[6];
A10_precharge[6] = 1'b0;
// Bank Precharge Pipeline
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = Bank_precharge[4];
Bank_precharge[4] = Bank_precharge[5];
Bank_precharge[5] = Bank_precharge[6];
Bank_precharge[6] = 2'b0;
// Command Precharge Pipeline
Cmnd_precharge[0] = Cmnd_precharge[1];
Cmnd_precharge[1] = Cmnd_precharge[2];
Cmnd_precharge[2] = Cmnd_precharge[3];
Cmnd_precharge[3] = Cmnd_precharge[4];
Cmnd_precharge[4] = Cmnd_precharge[5];
Cmnd_precharge[5] = Cmnd_precharge[6];
Cmnd_precharge[6] = 1'b0;
// Terminate a Read if same bank or all banks
if (Cmnd_precharge[0] === 1'b1) begin
if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
if (Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
read_precharge_truncation = 4'hF;
end
end
end
end
endtask
// Burst Terminate Pipeline
task Burst_Terminate_Pipeline;
begin
// Command Precharge Pipeline
Cmnd_bst[0] = Cmnd_bst[1];
Cmnd_bst[1] = Cmnd_bst[2];
Cmnd_bst[2] = Cmnd_bst[3];
Cmnd_bst[3] = Cmnd_bst[4];
Cmnd_bst[4] = Cmnd_bst[5];
Cmnd_bst[5] = Cmnd_bst[6];
Cmnd_bst[6] = 1'b0;
// Terminate a Read regardless of banks
if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
end
end
endtask
// Dq and Dqs Drivers
task Dq_Dqs_Drivers;
begin
// read command pipeline
Read_cmnd [0] = Read_cmnd [1];
Read_cmnd [1] = Read_cmnd [2];
Read_cmnd [2] = Read_cmnd [3];
Read_cmnd [3] = Read_cmnd [4];
Read_cmnd [4] = Read_cmnd [5];
Read_cmnd [5] = Read_cmnd [6];
Read_cmnd [6] = 1'b0;
// read bank pipeline
Read_bank [0] = Read_bank [1];
Read_bank [1] = Read_bank [2];
Read_bank [2] = Read_bank [3];
Read_bank [3] = Read_bank [4];
Read_bank [4] = Read_bank [5];
Read_bank [5] = Read_bank [6];
Read_bank [6] = 2'b0;
// read column pipeline
Read_cols [0] = Read_cols [1];
Read_cols [1] = Read_cols [2];
Read_cols [2] = Read_cols [3];
Read_cols [3] = Read_cols [4];
Read_cols [4] = Read_cols [5];
Read_cols [5] = Read_cols [6];
Read_cols [6] = 0;
// Initialize Read command
if (Read_cmnd [0] === 1'b1) begin
Data_out_enable = 1'b1;
Bank_addr = Read_bank [0];
Cols_addr = Read_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row Address Mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("%m: At time %t ERROR: Invalid Bank Address", $time);
endcase
end
// Toggle Dqs during Read command
if (Data_out_enable === 1'b1) begin
Dqs_int = 1'b0;
if (Dqs_out === {DQS_BITS{1'b0}}) begin
Dqs_out = {DQS_BITS{1'b1}};
end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
Dqs_out = {DQS_BITS{1'b0}};
end else begin
Dqs_out = {DQS_BITS{1'b0}};
end
end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
Dqs_out = {DQS_BITS{1'bz}};
end
// Initialize dqs for Read command
if (Read_cmnd [2] === 1'b1) begin
if (Data_out_enable === 1'b0) begin
Dqs_int = 1'b1;
Dqs_out = {DQS_BITS{1'b0}};
end
end
// Read latch
if (Data_out_enable === 1'b1) begin
// output data
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
if (DEBUG) begin
$display ("%m: At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
end
end else begin
Dq_out = {DQ_BITS{1'bz}};
end
end
endtask
// Write FIFO and DM Mask Logic
task Write_FIFO_DM_Mask_Logic;
begin
// Write command pipeline
Write_cmnd [0] = Write_cmnd [1];
Write_cmnd [1] = Write_cmnd [2];
Write_cmnd [2] = Write_cmnd [3];
Write_cmnd [3] = 1'b0;
// Write command pipeline
Write_bank [0] = Write_bank [1];
Write_bank [1] = Write_bank [2];
Write_bank [2] = Write_bank [3];
Write_bank [3] = 2'b0;
// Write column pipeline
Write_cols [0] = Write_cols [1];
Write_cols [1] = Write_cols [2];
Write_cols [2] = Write_cols [3];
Write_cols [3] = {COL_BITS{1'b0}};
// Initialize Write command
if (Write_cmnd [0] === 1'b1) begin
Data_in_enable = 1'b1;
Bank_addr = Write_bank [0];
Cols_addr = Write_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row address mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("%m: At time %t ERROR: Invalid Row Address", $time);
endcase
end
// Write data
if (Data_in_enable === 1'b1) begin
// Data Buffer
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// write negedge Dqs on posedge Sys_clk
if (Sys_clk) begin
if (!dm_fall[0]) begin
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
end
if (!dm_fall[1]) begin
Dq_buf [15 : 8] = dq_fall [15 : 8];
end
if (!dm_fall[2]) begin
Dq_buf [23 : 16] = dq_fall [23 : 16];
end
if (!dm_fall[3]) begin
Dq_buf [31 : 24] = dq_fall [31 : 24];
end
if (~&dm_fall) begin
if (DEBUG) begin
$display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
// write posedge Dqs on negedge Sys_clk
end else begin
if (!dm_rise[0]) begin
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
end
if (!dm_rise[1]) begin
Dq_buf [15 : 8] = dq_rise [15 : 8];
end
if (!dm_rise[2]) begin
Dq_buf [23 : 16] = dq_rise [23 : 16];
end
if (!dm_rise[3]) begin
Dq_buf [31 : 24] = dq_rise [31 : 24];
end
if (~&dm_rise) begin
if (DEBUG) begin
$display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
end
// Write Data
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// tWR start and tWTR check
if (Sys_clk && &dm_pair === 1'b0) begin
case (Bank_addr)
2'd0 : WR_chk0 = $time;
2'd1 : WR_chk1 = $time;
2'd2 : WR_chk2 = $time;
2'd3 : WR_chk3 = $time;
default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $time);
endcase
// tWTR check
if (Read_enable === 1'b1) begin
$display ("%m: At time %t ERROR: tWTR violation during Read", $time);
end
end
end
end
endtask
// Auto Precharge Calculation
task Auto_Precharge_Calculation;
begin
// Precharge counter
if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
Count_precharge [0] = Count_precharge [0] + 1;
end
if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
Count_precharge [1] = Count_precharge [1] + 1;
end
if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
Count_precharge [2] = Count_precharge [2] + 1;
end
if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
Count_precharge [3] = Count_precharge [3] + 1;
end
// Read with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. BL/2 cycles after command
if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if (Count_precharge[0] >= burst_length/2) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Read_precharge[0] = 1'b0;
end
end
if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if (Count_precharge[1] >= burst_length/2) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Read_precharge[1] = 1'b0;
end
end
if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if (Count_precharge[2] >= burst_length/2) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Read_precharge[2] = 1'b0;
end
end
if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if (Count_precharge[3] >= burst_length/2) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Read_precharge[3] = 1'b0;
end
end
// Write with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command
if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Write_precharge[0] = 1'b0;
end
end
if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Write_precharge[1] = 1'b0;
end
end
if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Write_precharge[2] = 1'b0;
end
end
if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Write_precharge[3] = 1'b0;
end
end
end
endtask
// DLL Counter
task DLL_Counter;
begin
if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
DLL_count = DLL_count + 1;
if (DLL_count >= 200) begin
DLL_done = 1'b1;
end
end
end
endtask
// Control Logic
task Control_Logic;
begin
// Auto Refresh
if (Aref_enable === 1'b1) begin
// Display DEBUG Message
if (DEBUG) begin
$display ("%m: At time %t AREF : Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $time);
end
// LMR/EMR to Auto Refresh
if ($time - MRD_chk < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
if (!no_halt) $stop (0);
end else begin
aref_count = aref_count + 1;
RFC_chk = $time;
end
end
// Extended Mode Register
if (Ext_mode_enable === 1'b1) begin
if (DEBUG) begin
$display ("%m: At time %t EMR : Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
if (!no_halt) $stop (0);
end else begin
if (Addr[0] === 1'b0) begin
DLL_enable = 1'b1;
if (DEBUG) begin
$display ("%m: At time %t EMR : Enable DLL", $time);
end
end else begin
DLL_enable = 1'b0;
if (DEBUG) begin
$display ("%m: At time %t EMR : Disable DLL", $time);
end
end
MRD_chk = $time;
end
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
if (DEBUG) begin
$display ("%m: At time %t LMR : Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
end else begin
// Register Mode
Mode_reg = Addr;
// DLL Reset
if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
DLL_reset = 1'b1;
DLL_done = 1'b0;
DLL_count = 0;
end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
$display ("%m: At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
$display ("%m: At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
end
// Burst Length
case (Addr [2 : 0])
3'b001 : $display ("%m: At time %t LMR : Burst Length = 2", $time);
3'b010 : $display ("%m: At time %t LMR : Burst Length = 4", $time);
3'b011 : $display ("%m: At time %t LMR : Burst Length = 8", $time);
default : $display ("%m: At time %t ERROR: Burst Length not supported", $time);
endcase
// CAS Latency
case (Addr [6 : 4])
3'b010 : $display ("%m: At time %t LMR : CAS Latency = 2", $time);
3'b110 : $display ("%m: At time %t LMR : CAS Latency = 2.5", $time);
3'b011 : $display ("%m: At time %t LMR : CAS Latency = 3", $time);
default : $display ("%m: At time %t ERROR: CAS Latency not supported", $time);
endcase
// Record current tMRD time
MRD_chk = $time;
end
end
// Activate Block
if (Active_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: %m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
end
// Display DEBUG Message
if (DEBUG) begin
$display ("%m: At time %t ACT : Bank = %h, Row = %h", $time, Ba, Addr);
end
// Activate to Activate (different bank)
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m: At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
end
// LMR/EMR to Activate
if ($time - MRD_chk < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
end
// AutoRefresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
$display ("%m: At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
if (!no_halt) $stop (0);
end else begin
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk0 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk0 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr;
RC_chk0 = $time;
RCD_chk0 = $time;
RAS_chk0 = $time;
RAP_chk0 = $time;
end
// Activate Bank 1
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk1 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk1 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr;
RC_chk1 = $time;
RCD_chk1 = $time;
RAS_chk1 = $time;
RAP_chk1 = $time;
end
// Activate Bank 2
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk2 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk2 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr;
RC_chk2 = $time;
RCD_chk2 = $time;
RAS_chk2 = $time;
RAP_chk2 = $time;
end
// Activate Bank 3
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk3 < tRC) begin
$display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk3 < tRP) begin
$display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr;
RC_chk3 = $time;
RCD_chk3 = $time;
RAS_chk3 = $time;
RAP_chk3 = $time;
end
// Record variable for checking violation
RRD_chk = $time;
Prev_bank = Ba;
read_precharge_truncation[Ba] = 1'b0;
end
end
// Precharge Block - consider NOP if bank already precharged or in process of precharging
if (Prech_enable === 1'b1) begin
// Display DEBUG Message
if (DEBUG) begin
$display ("%m: At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
end
// LMR/EMR to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m: At time %t ERROR: tMRD violation during Precharge", $time);
if (!no_halt) $stop (0);
end
// AutoRefresh to Precharge
if ($time - RFC_chk < tRFC) begin
$display ("%m: At time %t ERROR: tRFC violation during Precharge", $time);
if (!no_halt) $stop (0);
end
// Precharge bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge Bank
if ($time - RAS_chk0 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
if (!no_halt) $stop (0);
end
// tWR violation check for Write
if ($time - WR_chk0 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
if (!no_halt) $stop (0);
end
end
// Precharge bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
if (!no_halt) $stop (0);
end
// tWR violation check for Write
if ($time - WR_chk1 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
if (!no_halt) $stop (0);
end
end
// Precharge bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
if (!no_halt) $stop (0);
end
// tWR violation check for Write
if ($time - WR_chk2 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
if (!no_halt) $stop (0);
end
end
// Precharge bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
if (!no_halt) $stop (0);
end
// tWR violation check for Write
if ($time - WR_chk3 < tWR) begin
$display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
if (!no_halt) $stop (0);
end
end
// Prech_count is to make sure we have met part of the initialization sequence
Prech_count = Prech_count + 1;
// Pipeline for READ
A10_precharge [cas_latency_x2] = Addr[10];
Bank_precharge[cas_latency_x2] = Ba;
Cmnd_precharge[cas_latency_x2] = 1'b1;
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Display DEBUG Message
if (DEBUG) begin
$display ("%m: At time %t BST : Burst Terminate",$time);
end
if (Data_in_enable === 1'b1) begin
// Illegal to burst terminate a Write
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $time);
if (!no_halt) $stop (0);
end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
// Illegal to burst terminate a Read with Auto Precharge
Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
end else begin
// Burst Terminate Command Pipeline for Read
Cmnd_bst[cas_latency_x2] = 1'b1;
end
end
// Read Command
if (Read_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
end
// Check for DLL reset before Read
if (DLL_reset === 1 && DLL_done === 0) begin
$display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
end
// Display DEBUG Message
if (DEBUG) begin
$display ("%m: At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]});
end
// Terminate a Write
if (Data_in_enable === 1'b1) begin
Data_in_enable = 1'b0;
end
// Activate to Read without Auto Precharge
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("%m: At time %t ERROR: tRCD violation during Read", $time);
end
// Activate to Read with Auto Precharge
if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
$display ("%m: At time %t ERROR: tRAP violation during Read", $time);
end
// Interrupt a Read with Auto Precharge (same bank only)
if (Read_precharge [Ba] === 1'b1) begin
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Read_precharge [Ba]= 1'b0;
end
end
// Activate to Read
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("%m: At time %t ERROR: Bank is not Activated for Read", $time);
if (!no_halt) $stop (0);
end else begin
// CAS Latency pipeline
Read_cmnd[cas_latency_x2] = 1'b1;
Read_bank[cas_latency_x2] = Ba;
Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Read_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
// Write Command
if (Write_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
if (!no_halt) $stop (0);
end
// display DEBUG message
if (DEBUG) begin
$display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
end
// Activate to Write
if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("%m: At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba);
end
// Read to Write
if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
if (Data_out_enable || read_precharge_truncation[Ba]) begin
$display("%m: At time %t ERROR: Read to Write violation", $time);
end
end
// Interrupt a Write with Auto Precharge (same bank only)
if (Write_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Write_precharge [Ba]= 1'b0;
end
end
// Activate to Write
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("%m: At time %t ERROR: Bank is not Activated for Write", $time);
if (!no_halt) $stop (0);
end else begin
// Pipeline for Write
Write_cmnd [3] = 1'b1;
Write_bank [3] = Ba;
Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Write_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
end
endtask
task check_neg_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_neg_dqs[i]) begin
$display ("%m: At time %t ERROR: Negative DQS[%d] transition required.", $time, i);
end
expect_neg_dqs[i] = 1'b1;
end
end else begin
expect_pos_dqs = 0;
expect_neg_dqs = 0;
end
end
endtask
task check_pos_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_pos_dqs[i]) begin
$display ("%m: At time %t ERROR: Positive DQS[%d] transition required.", $time, i);
end
expect_pos_dqs[i] = 1'b1;
end
end else begin
expect_pos_dqs = 0;
expect_neg_dqs = 0;
end
end
endtask
// Main Logic
always @ (posedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
check_neg_dqs;
Auto_Precharge_Calculation;
DLL_Counter;
Control_Logic;
end
always @ (negedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
check_pos_dqs;
end
// Dqs Receiver
always @ (posedge Dqs_in[0]) begin
// Latch data at posedge Dqs
dq_rise[7 : 0] = Dq_in[7 : 0];
dm_rise[0] = Dm_in[0];
expect_pos_dqs[0] = 0;
end
always @ (posedge Dqs_in[1]) begin
// Latch data at posedge Dqs
dq_rise[15 : 8] = Dq_in[15 : 8];
dm_rise[1] = Dm_in [1];
expect_pos_dqs[1] = 0;
end
always @ (posedge Dqs_in[2]) begin
// Latch data at posedge Dqs
dq_rise[23 : 16] = Dq_in[23 : 16];
dm_rise[2] = Dm_in [2];
expect_pos_dqs[2] = 0;
end
always @ (posedge Dqs_in[3]) begin
// Latch data at posedge Dqs
dq_rise[31 : 24] = Dq_in[31 : 24];
dm_rise[3] = Dm_in [3];
expect_pos_dqs[3] = 0;
end
always @ (negedge Dqs_in[0]) begin
// Latch data at negedge Dqs
dq_fall[7 : 0] = Dq_in[7 : 0];
dm_fall[0] = Dm_in[0];
dm_pair[1:0] = {dm_rise[0], dm_fall[0]};
expect_neg_dqs[0] = 0;
end
always @ (negedge Dqs_in[1]) begin
// Latch data at negedge Dqs
dq_fall[15: 8] = Dq_in[15 : 8];
dm_fall[1] = Dm_in[1];
dm_pair[3:2] = {dm_rise[1], dm_fall[1]};
expect_neg_dqs[1] = 0;
end
always @ (negedge Dqs_in[2]) begin
// Latch data at negedge Dqs
dq_fall[23: 16] = Dq_in[23 : 16];
dm_fall[2] = Dm_in[2];
dm_pair[5:4] = {dm_rise[2], dm_fall[2]};
expect_neg_dqs[2] = 0;
end
always @ (negedge Dqs_in[3]) begin
// Latch data at negedge Dqs
dq_fall[31: 24] = Dq_in[31 : 24];
dm_fall[3] = Dm_in[3];
dm_pair[7:6] = {dm_rise[3], dm_fall[3]};
expect_neg_dqs[3] = 0;
end
specify
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5B // specparams for -5B (CL = 3)
specparam tDSS = 1.0; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.0; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 1.75; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 1.75; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
`ifdef sg6 // specparams for -6 (CL = 2.5)
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
`ifdef sg6T // specparams for -6 (CL = 2.5)
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
`ifdef sg75 // specparams for -75E (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
`ifdef sg75E // specparams for -75E (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
`ifdef sg75Z // specparams for -75Z (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif
$width (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
$width (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
$width (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
$width (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
$setuphold(posedge Clk, Cke, tIS, tIH);
$setuphold(posedge Clk, Cs_n, tIS, tIH);
$setuphold(posedge Clk, Cas_n, tIS, tIH);
$setuphold(posedge Clk, Ras_n, tIS, tIH);
$setuphold(posedge Clk, We_n, tIS, tIH);
$setuphold(posedge Clk, Addr, tIS, tIH);
$setuphold(posedge Clk, Ba, tIS, tIH);
$setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS, tDSH);
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:32:00 07/21/2013
// Design Name: sha256_chunk
// Module Name: C:/Dropbox/xilinx/processor/test/sha_chunk_test.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sha256_chunk
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sha_chunk_test;
// Inputs
reg [511:0] data;
reg [255:0] V_in;
reg clk = 0;
// Outputs
wire [255:0] hash;
// Instantiate the Unit Under Test (UUT)
sha256_chunk uut (
.clk(clk),
.data(data),
.V_in(V_in),
.hash(hash)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
// Initialize Inputs
data = 0;
data[7:0] = 8'd97;
data[15:8] = 8'd98;
data[23:16] = 8'd99;
data[31:24] = 8'h80;
data[511:504] = 8'd24;
V_in = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
uut.roundnum = 6'h3e;
#(80*P);
$stop();
end
endmodule
|
module fmrv32im_decode
(
input RST_N,
input CLK,
// インストラクションコード
input wire [31:0] INST_CODE,
// レジスタ番号
output wire [4:0] RD_NUM,
output wire [4:0] RS1_NUM,
output wire [4:0] RS2_NUM,
// イミデート
output reg [31:0] IMM,
// 命令
output reg INST_LUI,
output reg INST_AUIPC,
output reg INST_JAL,
output reg INST_JALR,
output reg INST_BEQ,
output reg INST_BNE,
output reg INST_BLT,
output reg INST_BGE,
output reg INST_BLTU,
output reg INST_BGEU,
output reg INST_LB,
output reg INST_LH,
output reg INST_LW,
output reg INST_LBU,
output reg INST_LHU,
output reg INST_SB,
output reg INST_SH,
output reg INST_SW,
output reg INST_ADDI,
output reg INST_SLTI,
output reg INST_SLTIU,
output reg INST_XORI,
output reg INST_ORI,
output reg INST_ANDI,
output reg INST_SLLI,
output reg INST_SRLI,
output reg INST_SRAI,
output reg INST_ADD,
output reg INST_SUB,
output reg INST_SLL,
output reg INST_SLT,
output reg INST_SLTU,
output reg INST_XOR,
output reg INST_SRL,
output reg INST_SRA,
output reg INST_OR,
output reg INST_AND,
output reg INST_FENCE,
output reg INST_FENCEI,
output reg INST_ECALL,
output reg INST_EBREAK,
output reg INST_MRET,
output reg INST_CSRRW,
output reg INST_CSRRS,
output reg INST_CSRRC,
output reg INST_CSRRWI,
output reg INST_CSRRSI,
output reg INST_CSRRCI,
output reg INST_MUL,
output reg INST_MULH,
output reg INST_MULHSU,
output reg INST_MULHU,
output reg INST_DIV,
output reg INST_DIVU,
output reg INST_REM,
output reg INST_REMU,
output reg INST_CUSTOM0,
output wire ILL_INST
);
// タイプ(イミデート)判別
reg r_type, i_type, s_type, b_type, u_type, j_type;
reg c0_type; // custom0
always @(*) begin
r_type <= (INST_CODE[6:5] == 2'b01) && (INST_CODE[4:2] == 3'b100);
i_type <= ((INST_CODE[6:5] == 2'b00) && ((INST_CODE[4:2] == 3'b000) ||
(INST_CODE[4:2] == 3'b011) ||
(INST_CODE[4:2] == 3'b100))) ||
((INST_CODE[6:5] == 2'b11) && ((INST_CODE[4:2] == 3'b001) ||
(INST_CODE[4:2] == 3'b100)));
s_type <= (INST_CODE[6:5] == 2'b01) && (INST_CODE[4:2] == 3'b000);
b_type <= (INST_CODE[6:5] == 2'b11) && (INST_CODE[4:2] == 3'b000);
u_type <= ((INST_CODE[6:5] == 2'b00) || (INST_CODE[6:5] == 2'b01)) &&
(INST_CODE[4:2] == 3'b101);
j_type <= (INST_CODE[6:5] == 2'b11) && (INST_CODE[4:2] == 3'b011);
c0_type <= (INST_CODE[6:5] == 2'b00) && (INST_CODE[4:2] == 3'b010);
end
// イミデート生成
always @(posedge CLK) begin
if(!RST_N) begin
IMM <= 0;
end else begin
IMM <= (i_type)?{{21{INST_CODE[31]}},
INST_CODE[30:20]}:
(s_type)?{{21{INST_CODE[31]}},
INST_CODE[30:25], INST_CODE[11:7]}:
(b_type)?{{20{INST_CODE[31]}},
INST_CODE[7], INST_CODE[30:25], INST_CODE[11:8], 1'b0}:
(u_type)?{INST_CODE[31:12], 12'b0000_0000_0000}:
(j_type)?{{12{INST_CODE[31]}},
INST_CODE[19:12], INST_CODE[20], INST_CODE[30:21], 1'b0}:
32'd0; // Illigal Code
end
end
// レジスタ番号生成
assign RD_NUM = (r_type | i_type | u_type | j_type | c0_type)?INST_CODE[11:7]:5'd0;
assign RS1_NUM = (r_type | i_type | s_type | b_type)?INST_CODE[19:15]:5'd0;
assign RS2_NUM = (r_type | s_type | b_type)?INST_CODE[24:20]:5'd0;
// 各種ファンクション生成
wire [2:0] func3;
wire [6:0] func7;
assign func3 = INST_CODE[14:12];
assign func7 = INST_CODE[31:25];
// 命令判別
always @(posedge CLK) begin
if(!RST_N) begin
INST_LUI <= 1'b0;
INST_AUIPC <= 1'b0;
INST_JAL <= 1'b0;
INST_JALR <= 1'b0;
INST_BEQ <= 1'b0;
INST_BNE <= 1'b0;
INST_BLT <= 1'b0;
INST_BGE <= 1'b0;
INST_BLTU <= 1'b0;
INST_BGEU <= 1'b0;
INST_LB <= 1'b0;
INST_LH <= 1'b0;
INST_LW <= 1'b0;
INST_LBU <= 1'b0;
INST_LHU <= 1'b0;
INST_SB <= 1'b0;
INST_SH <= 1'b0;
INST_SW <= 1'b0;
INST_ADDI <= 1'b0;
INST_SLTI <= 1'b0;
INST_SLTIU <= 1'b0;
INST_XORI <= 1'b0;
INST_ORI <= 1'b0;
INST_ANDI <= 1'b0;
INST_SLLI <= 1'b0;
INST_SRLI <= 1'b0;
INST_SRAI <= 1'b0;
INST_ADD <= 1'b0;
INST_SUB <= 1'b0;
INST_SLL <= 1'b0;
INST_SLT <= 1'b0;
INST_SLTU <= 1'b0;
INST_XOR <= 1'b0;
INST_SRL <= 1'b0;
INST_SRA <= 1'b0;
INST_OR <= 1'b0;
INST_AND <= 1'b0;
INST_FENCE <= 1'b0;
INST_FENCEI <= 1'b0;
INST_ECALL <= 1'b0;
INST_EBREAK <= 1'b0;
INST_MRET <= 1'b0;
INST_CSRRW <= 1'b0;
INST_CSRRS <= 1'b0;
INST_CSRRC <= 1'b0;
INST_CSRRWI <= 1'b0;
INST_CSRRSI <= 1'b0;
INST_CSRRCI <= 1'b0;
INST_MUL <= 1'b0;
INST_MULH <= 1'b0;
INST_MULHSU <= 1'b0;
INST_MULHU <= 1'b0;
INST_DIV <= 1'b0;
INST_DIVU <= 1'b0;
INST_REM <= 1'b0;
INST_REMU <= 1'b0;
INST_CUSTOM0 <= 1'b0;
end else begin
INST_LUI <= (INST_CODE[6:0] == 7'b0110111);
INST_AUIPC <= (INST_CODE[6:0] == 7'b0010111);
INST_JAL <= (INST_CODE[6:0] == 7'b1101111);
INST_JALR <= (INST_CODE[6:0] == 7'b1100111);
INST_BEQ <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b000);
INST_BNE <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b001);
INST_BLT <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b100);
INST_BGE <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b101);
INST_BLTU <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b110);
INST_BGEU <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b111);
INST_LB <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b000);
INST_LH <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b001);
INST_LW <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b010);
INST_LBU <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b100);
INST_LHU <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b101);
INST_SB <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b000);
INST_SH <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b001);
INST_SW <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b010);
INST_ADDI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b000);
INST_SLTI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b010);
INST_SLTIU <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b011);
INST_XORI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b100);
INST_ORI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b110);
INST_ANDI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b111);
INST_SLLI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b001) &&
(func7 == 7'b0000000);
INST_SRLI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b101) &&
(func7 == 7'b0000000);
INST_SRAI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b101) &&
(func7 == 7'b0100000);
INST_ADD <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0000000);
INST_SUB <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0100000);
INST_SLL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b001) &&
(func7 == 7'b0000000);
INST_SLT <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b010) &&
(func7 == 7'b0000000);
INST_SLTU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b011) &&
(func7 == 7'b0000000);
INST_XOR <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b100) &&
(func7 == 7'b0000000);
INST_SRL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0000000);
INST_SRA <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0100000);
INST_OR <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b110) &&
(func7 == 7'b0000000);
INST_AND <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b111) &&
(func7 == 7'b0000000);
INST_FENCE <= (INST_CODE[6:0] == 7'b0001111) && (func3 == 3'b000);
INST_FENCEI <= (INST_CODE[6:0] == 7'b0001111) && (func3 == 3'b001);
INST_ECALL <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0000_0000_0000);
INST_EBREAK <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0000_0000_0001);
INST_MRET <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0011_0000_0010);
INST_CSRRW <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b001);
INST_CSRRS <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b010);
INST_CSRRC <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b011);
INST_CSRRWI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b101);
INST_CSRRSI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b110);
INST_CSRRCI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b111);
INST_MUL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0000001);
INST_MULH <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b001) &&
(func7 == 7'b0000001);
INST_MULHSU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b010) &&
(func7 == 7'b0000001);
INST_MULHU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b011) &&
(func7 == 7'b0000001);
INST_DIV <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b100) &&
(func7 == 7'b0000001);
INST_DIVU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0000001);
INST_REM <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b110) &&
(func7 == 7'b0000001);
INST_REMU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b111) &&
(func7 == 7'b0000001);
INST_CUSTOM0 <= (INST_CODE[6:0] == 7'b0001011);
end
end
assign ILL_INST = ~(
INST_LUI | INST_AUIPC | INST_JAL | INST_JALR |
INST_BEQ | INST_BNE | INST_BLT | INST_BGE |
INST_BLTU | INST_BGEU |
INST_LB | INST_LH | INST_LW | INST_LBU | INST_LHU |
INST_SB | INST_SH | INST_SW |
INST_ADDI | INST_SLTI | INST_SLTIU |
INST_XORI | INST_ORI | INST_ANDI |
INST_SLLI | INST_SRLI | INST_SRAI |
INST_ADD | INST_SUB |
INST_SLL | INST_SLT | INST_SLTU |
INST_XOR | INST_SRL | INST_SRA |
INST_OR | INST_AND |
INST_FENCE | INST_FENCEI |
INST_ECALL | INST_EBREAK |
INST_MRET |
INST_CSRRW | INST_CSRRS | INST_CSRRC |
INST_CSRRWI | INST_CSRRSI | INST_CSRRCI |
INST_MUL | INST_MULH | INST_MULHSU | INST_MULHU |
INST_DIV | INST_DIVU | INST_REM | INST_REMU |
INST_CUSTOM0
);
endmodule // fmrv32im_decoder
|
(* Copyright (c) 2009-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Arith.
Require Import Cpdt.CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(**
(* %\part{The Big Picture}
\chapter{Proving in the Large}% *)
%\part{大局的}
\chapter{大きな証明をする}% *)
(**
(* It is somewhat unfortunate that the term "theorem proving" looks so much like the word "theory." Most researchers and practitioners in software assume that mechanized theorem proving is profoundly impractical. Indeed, until recently, most advances in theorem proving for higher-order logics have been largely theoretical. However, starting around the beginning of the 21st century, there was a surge in the use of proof assistants in serious verification efforts. That line of work is still quite new, but I believe it is not too soon to distill some lessons on how to work effectively with large formal proofs.
*)
「定理証明」という言葉が、「理論」という言葉によく似ていることは、やや残念です。
ソフトウェアの研究者や実務家のほとんどは、
機械化された定理証明が根本的に実用的でないと信じています。
確かに、最近まで、高階論理について証明された定理の大部分の進歩は、
主に理論的なものでした。
しかし、21世紀初頭から、重大な検証作業において証明支援系(proof assistants)の使用が急増しました。
その仕事の列線(line)はまだ新しいものですが、
私は大規模な形式的な証明で効果的に仕事をする方法について
いくつかの教訓を掘り起こすのは時期尚早ではないと思います。
(*
Thus, this chapter gives some tips for structuring and maintaining large Coq developments. *)
したがって、この章では、大規模なCoqの開発を構造化し、保守するためのヒントを示します。
*)
(*
(** * Ltac Anti-Patterns *)
*)
(** * Ltac アンチパターン *)
(**
(* In this book, I have been following an unusual style, where proofs are not considered finished until they are %\index{fully automated proofs}%"fully automated," in a certain sense. Each such theorem is proved by a single tactic. Since Ltac is a Turing-complete programming language, it is not hard to squeeze arbitrary heuristics into single tactics, using operators like the semicolon to combine steps. In contrast, most Ltac proofs "in the wild" consist of many steps, performed by individual tactics followed by periods. Is it really worth drawing a distinction between proof steps terminated by semicolons and steps terminated by periods?
*)
この本では、%\index{fully automated proofs}% 「完全自動化」
になるまで、証明が完了していないというある意味で、珍しいスタイルに従っています。
そのような定理の各々は、単一ののタクティクによって証明されます。
Ltacはチューリング完全なプログラミング言語なので、
セミコロンのような演算子を使ってステップを組み合わせることで、
任意のヒューリスティックスをひとつのタクティクに絞り込むことは難しくありません。
対照的に、「野良(in the wild)」での大部分のLtacによる証明は、
個々のタクティクのピリオドに続いて実行される多くのステップで構成されています。
セミコロンで終了した証明手順とピリオドで終了した手順を区別することは本当に価値があるでしょうか？
(*
I argue that this is, in fact, a very important distinction, with serious consequences for a majority of important verification domains. The more uninteresting drudge work a proof domain involves, the more important it is to work to prove theorems with single tactics. From an automation standpoint, single-tactic proofs can be extremely effective, and automation becomes more and more critical as proofs are populated by more uninteresting detail. In this section, I will give some examples of the consequences of more common proof styles.
*)
私は、これが実際には非常に重要な違いであり、
重要な検証の領域の大多数に深刻な影響を及ぼしている、と主張しています。
実証的な領域が関与する、より面白くない、退屈な(drudge)とした仕事ほど、
単一のタクティクで定理を証明することがより重要になります。
自動化の観点からは、単一のタクティクによる証明は非常に効果的であり、
証明がより興味深い詳細によって埋められているので、
自動化はますます重要になります。
この節では、より一般的な証明のスタイルの結果のいくつかの例を示します。
(*
As a running example, consider a basic language of arithmetic expressions, an interpreter for it, and a transformation that scales up every constant in an expression. *)
実行中の例として、
算術式の基本言語、
そのためのインタプリタ、および、
式のなかのすべての定数を拡大するトランスレータを考えてみましょう。
*)
Inductive exp : Set :=
| Const : nat -> exp
| Plus : exp -> exp -> exp.
Fixpoint eval (e : exp) : nat :=
match e with
| Const n => n
| Plus e1 e2 => eval e1 + eval e2
end.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
end.
(**
(* We can write a very manual proof that [times] really implements multiplication. *)
実際に乗算([times])を実装するという、非常に手作業の証明を書くことができます。
*)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e.
trivial.
simpl.
rewrite IHe1.
rewrite IHe2.
rewrite mult_plus_distr_l.
trivial.
Qed.
(* begin thide *)
(**
(* We use spaces to separate the two inductive cases, but note that these spaces have no real semantic content; Coq does not enforce that our spacing matches the real case structure of a proof. The second case mentions automatically generated hypothesis names explicitly. As a result, innocuous changes to the theorem statement can invalidate the proof. *)
ふたつの帰納的ケースを分離するために空白（空行）を使用しますが、
これらの空行に実際には意味的な内容がないことに注意してください;
Coqは、その空行が証明の実際の場合分けの構造(case structure)と一致するよう強制しません。
2番目のケースでは、自動的に生成された仮説名が明示的に記述されています。
結果として、定理のステートメントに対する無害な変更は、この証明を無効にすることができます。
*)
Reset eval_times.
Theorem eval_times : forall k x,
eval (times k x) = k * eval x.
induction x.
trivial.
simpl.
(** %\vspace{-.15in}%[[
rewrite IHe1.
]]
<<
Error: The reference IHe1 was not found in the current environment.
>>
(*
The inductive hypotheses are named [IHx1] and [IHx2] now, not [IHe1] and [IHe2]. *)
帰納的な仮説は、[IHe1]と[IHe2]ではなく、いまでは [IHx1]と[IHx2]という名前になりました。
*)
Abort.
(**
(* We might decide to use a more explicit invocation of [induction] to give explicit binders for all of the names that we will reference later in the proof. *)
証明の中で後で参照するすべての名前に対して明示的な束縛子(binder)を与えるために、
[induction]のより明示的な呼び出しを使うことにします。
*)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 ].
trivial.
simpl.
rewrite IHe1.
rewrite IHe2.
rewrite mult_plus_distr_l.
trivial.
Qed.
(**
(* We pass %\index{tactics!induction}%[induction] an%\index{intro pattern}% _intro pattern_, using a [|] character to separate instructions for the different inductive cases. Within a case, we write [?] to ask Coq to generate a name automatically, and we write an explicit name to assign that name to the corresponding new variable. It is apparent that, to use intro patterns to avoid proof brittleness, one needs to keep track of the seemingly unimportant facts of the orders in which variables are introduced. Thus, the script keeps working if we replace [e] by [x], but it has become more cluttered. Arguably, neither proof is particularly easy to follow.
*)
%\index{tactics!induction}%[induction] に、
%\index{intro pattern}% ＿intro パターン＿ を渡し、
[|]文字を使用して、帰納法の場合分けを区別します。
ある場合では、[?]を書いてCoqに自動的に名前を生成するように要求し、
その名前を対応する新しい変数に割り当てるための明示的な名前を書きます。
証明のの脆弱さを避けるためにintroパターンを使用するには、
変数が導入された順番についての、一見重要でない事実を把握する必要があることは明らかです。
したがって、[e]を[x]で置き換えるとスクリプトは動作し続けますが、
複雑になっています。 おそらく、どちらの証明も特に追いかけるのは容易ではありません。
(*
That category of complaint has to do with understanding proofs as static artifacts. As with programming in general, with serious projects, it tends to be much more important to be able to support evolution of proofs as specifications change. Unstructured proofs like the above examples can be very hard to update in concert with theorem statements. For instance, consider how the last proof script plays out when we modify [times] to introduce a bug. *)
その不満のカテゴリーは、静的な人工物としての証明を理解することと関係があります。
一般的なプログラミングと同じように、深刻なプロジェクトでは、
仕様変更に伴い証明の進化をサポートすることが重要になる傾向があります。
上の例のような構造化されていない証明は、定理にあわせて更新するのが非常に難しい場合があります。
たとえば、[times]を修正してバグを導入するときに、
最後の証明のスクリプトがどのように機能するかを考えてみましょう。
*)
Reset times.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (1 + k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
end.
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 ].
trivial.
simpl.
(** %\vspace{-.15in}%[[
rewrite IHe1.
]]
<<
Error: The reference IHe1 was not found in the current environment.
>>
*)
Abort.
(**
(* Can you spot what went wrong, without stepping through the script step-by-step? The problem is that [trivial] never fails. Originally, [trivial] had been succeeding in proving an equality that follows by reflexivity. Our change to [times] leads to a case where that equality is no longer true. The invocation [trivial] happily leaves the false equality in place, and we continue on to the span of tactics intended for the second inductive case. Unfortunately, those tactics end up being applied to the _first_ case instead.
*)
スクリプトをステップ・バイ・ステップで進めることなく、何が間違っているのか分かりますか？
問題は[trivial]が決して失敗しないということです。
もともと、[trivial]は、反射性に従う等式を証明することに成功していました。
[times]の変更は、その等式がもはや真実でない場合につながります。
[trivial] の呼び出しは、幸いにも、偽の等式を適所に残し(* suhara: ひとつめが終わらないこと *)、
帰納法のふたつめの条件のためのタクティクの範囲を続けます。
残念ながら、それらのタクティクは代わりに ＿ひとつめ＿ の場合に適用されてしまいます。
(*
The problem with [trivial] could be "solved" by writing, e.g., [solve [ trivial ]] instead, so that an error is signaled early on if something unexpected happens. However, the root problem is that the syntax of a tactic invocation does not imply how many subgoals it produces. Much more confusing instances of this problem are possible. For example, if a lemma [L] is modified to take an extra hypothesis, then uses of [apply L] will generate more subgoals than before. Old unstructured proof scripts will become hopelessly jumbled, with tactics applied to inappropriate subgoals. Because of the lack of structure, there is usually relatively little to be gleaned from knowledge of the precise point in a proof script where an error is raised. *)
[trivial] についての問題は、代わりに [solve [ trivial ]] と書くことで「解決」することができ、
予期しないことが起こった場合に早期にエラーが通知されます。
しかし、根本的な問題は、タクティク呼び出しの構文が、
それが生成するサブゴールの数を意味するものではないということです。
この問題のはるかに混乱する例が考えられます。
例えば、補題[L]が余分な仮説をとるように修正された場合、
[apply L]の使用は以前より多くの副目標を生成するようになります。
古い構造化されていない証明スクリプトは、
不適切なサブゴールに適用されたタクティクにより、
絶望的に混乱します。
構造が不足しているため、
集められた、エラーが発生した証明スクリプト内の正確なポイントの知識は、
比較的少ししかありません。
*)
Reset times.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
end.
(**
(* Many real developments try to make essentially unstructured proofs look structured by applying careful indentation conventions, idempotent case-marker tactics included solely to serve as documentation, and so on. All of these strategies suffer from the same kind of failure of abstraction that was just demonstrated. I like to say that if you find yourself caring about indentation in a proof script, it is a sign that the script is structured poorly.
*)
多くの実際の開発では、本質的に構造化されていない証明を、
慎重な字下げ規則、文書としての役割を果たすための
偶発的(idempotence)なタクティクの大文字小文字の使い分(case-marker)けなどを
適用することによって構造化するようにしています。
これらの戦略のすべては、今見せた抽象化の失敗と同じ種類の障害に苦しんでいます。
あなたが証明スクリプトでインデントを気にしていると感じたら、
スクリプトがうまく構成されていないという兆候です。
(*
We can rewrite the current proof with a single tactic. *)
現在の証明を単一のタクティクで書き直すことができます。
*)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 ]; [
trivial
| simpl; rewrite IHe1; rewrite IHe2; rewrite mult_plus_distr_l; trivial ].
Qed.
(**
(* We use the form of the semicolon operator that allows a different tactic to be specified for each generated subgoal. This change improves the robustness of the script: we no longer need to worry about tactics from one case being applied to a different case. Still, the proof script is not especially readable. Probably most readers would not find it helpful in explaining why the theorem is true. The same could be said for scripts using the%\index{bullets}% _bullets_ or curly braces provided by Coq 8.4, which allow code like the above to be stepped through interactively, with periods in place of the semicolons, while representing proof structure in a way that is enforced by Coq. Interactive replay of scripts becomes easier, but readability is not really helped.
*)
セミコロン演算子の形式を使用して、
生成された各サブゴールに対して異なる戦術を指定することができます。
この変更により、スクリプトの堅牢性が向上します:
もはや、あるケースから別のケースに適用された戦術について心配する必要はありません。
それでも、証明スクリプトは特に読めるものではありません。
たぶん大部分の読者は、なぜ定理が正しいのかを説明するのに役立つとは思わないでしょう。
%\index{bullets}% _bullets_ ＿ブレット＿ や、
Coq 8.4で提供されている中括弧を使用したスクリプトでも言えます。
これは、Coqによって強制される方法で証明構造を表現して、
上記のようなコードをセミコロンの代わりにピリオドをつけて、
対話的に進めることができます。
対話的なスクリプトの再生(replay)が容易になりますが、
読みやすさの助けには本当になりません。
(*
The situation gets worse in considering extensions to the theorem we want to prove. Let us add multiplication nodes to our [exp] type and see how the proof fares. *)
証明したい定理の拡張を考えると、状況は悪化します。
乗算のノードを [exp] 型に追加し、
証明がどのように費用を払うか(fares)を見てみましょう。
*)
Reset exp.
Inductive exp : Set :=
| Const : nat -> exp
| Plus : exp -> exp -> exp
| Mult : exp -> exp -> exp.
Fixpoint eval (e : exp) : nat :=
match e with
| Const n => n
| Plus e1 e2 => eval e1 + eval e2
| Mult e1 e2 => eval e1 * eval e2
end.
Fixpoint times (k : nat) (e : exp) : exp :=
match e with
| Const n => Const (k * n)
| Plus e1 e2 => Plus (times k e1) (times k e2)
| Mult e1 e2 => Mult (times k e1) e2
end.
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
(** %\vspace{-.25in}%[[
induction e as [ | ? IHe1 ? IHe2 ]; [
trivial
| simpl; rewrite IHe1; rewrite IHe2; rewrite mult_plus_distr_l; trivial ].
]]
<<
Error: Expects a disjunctive pattern with 3 branches.
>>
*)
Abort.
(**
(* Unsurprisingly, the old proof fails, because it explicitly says that there are two inductive cases. To update the script, we must, at a minimum, remember the order in which the inductive cases are generated, so that we can insert the new case in the appropriate place. Even then, it will be painful to add the case, because we cannot walk through proof steps interactively when they occur inside an explicit set of cases. *)
驚くことではありませんが、古い証明は失敗します。
なぜなら、それはふたつの帰納の場合分け(case)があることが明示しているからです。
スクリプトを更新するには、帰納の場合分けが生成される順序を少なくとも覚えておく必要があります。
これにより、新しい場合分けを適切な場所に挿入することができます。
それでも、明示的な一連の場合分けの内で発生した場合に、
証明のステップを対話的に進めることができないため、
場合分けを追加するのは苦労します。
*)
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e as [ | ? IHe1 ? IHe2 | ? IHe1 ? IHe2 ]; [
trivial
| simpl; rewrite IHe1; rewrite IHe2; rewrite mult_plus_distr_l; trivial
| simpl; rewrite IHe1; rewrite mult_assoc; trivial ].
Qed.
(**
(* Now we are in a position to see how much nicer is the style of proof that we have followed in most of this book. *)
今、この本のほとんどで、
私たちが従ってきた証拠のスタイルがどれほど素晴らしいかを知る立場にあります。
*)
Reset eval_times.
Hint Rewrite mult_plus_distr_l.
Theorem eval_times : forall k e,
eval (times k e) = k * eval e.
induction e; crush.
Qed.
(* end thide *)
(**
(* This style is motivated by a hard truth: one person's manual proof script is almost always mostly inscrutable to most everyone else. I claim that step-by-step formal proofs are a poor way of conveying information. Thus, we might as well cut out the steps and automate as much as possible.
*)
このスタイルは手強い(hard)真実によって動機づけられます:
ひとりの手作業による証明スクリプトは
ほとんどの場合、ほとんどすべての人に納得できません。
私は、ステップ・バイ・ステップの形式的な証明は情報を伝達するための貧弱な方法だと主張します。
したがって、可能な限り、ステップを切り出し、自動化することもできます。
(*
What about the illustrative value of proofs? Most informal proofs are read to convey the big ideas of proofs. How can reading [induction e; crush] convey any big ideas? My position is that any ideas that standard automation can find are not very big after all, and the _real_ big ideas should be expressed through lemmas that are added as hints.
*)
証明の説明的(illustrative)な価値はどうでしょうか？
ほとんどの非形式的な証明は、証明の大きなアイデアを伝えるために読み込まれます。
どうすれば、[induction e; crush] を読むことが、
なんらかの大きなアイデアを伝えることができるでしょうか？
私の立場は、標準的な自動化が見つけることができるアイデアは結局はあまり大きくなく、
＿本当に＿ 大きなアイデアはヒントとして追加された補題を使って表現されるべきであるということです。
(*
An example should help illustrate what I mean. Consider this function, which rewrites an expression using associativity of addition and multiplication. *)
ひとつの例が私が意味するものを説明するのに役立つはずです。
加算と乗算の結合性(associativity)を使って、
式を書き換える関数を考えてみましょう。
*)
Fixpoint reassoc (e : exp) : exp :=
match e with
| Const _ => e
| Plus e1 e2 =>
let e1' := reassoc e1 in
let e2' := reassoc e2 in
match e2' with
| Plus e21 e22 => Plus (Plus e1' e21) e22
| _ => Plus e1' e2'
end
| Mult e1 e2 =>
let e1' := reassoc e1 in
let e2' := reassoc e2 in
match e2' with
| Mult e21 e22 => Mult (Mult e1' e21) e22
| _ => Mult e1' e2'
end
end.
Theorem reassoc_correct : forall e, eval (reassoc e) = eval e.
(* begin thide *)
induction e; crush;
match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
(** One subgoal remains:
[[
IHe2 : eval e3 * eval e4 = eval e2
============================
eval e1 * eval e3 * eval e4 = eval e1 * eval e2
]]
(*
The [crush] tactic does not know how to finish this goal. We could finish the proof manually. *)
[crush] タクティクはこのゴールをどのように完成(finish)するか知りません。
ゴールを手動で完成しないといけません。
*)
rewrite <- IHe2; crush.
(**
(* However, the proof would be easier to understand and maintain if we separated this insight into a separate lemma. *)
しかし、この洞察を別の補題に分ければ、
証明は理解しやすくなり、
保守することも容易になります。
*)
Abort.
Lemma rewr : forall a b c d, b * c = d -> a * b * c = a * d.
crush.
Qed.
Hint Resolve rewr.
Theorem reassoc_correct : forall e, eval (reassoc e) = eval e.
induction e; crush;
match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
Qed.
(* end thide *)
(**
(* In the limit, a complicated inductive proof might rely on one hint for each inductive case. The lemma for each hint could restate the associated case. Compared to manual proof scripts, we arrive at more readable results. Scripts no longer need to depend on the order in which cases are generated. The lemmas are easier to digest separately than are fragments of tactic code, since lemma statements include complete proof contexts. Such contexts can only be extracted from monolithic manual proofs by stepping through scripts interactively.
*)
その制限があると、複雑な帰納法による証明はそれぞれの帰納法の場合分け(case)に対して、
ひとつのヒントに依存する可能性があります。
各ヒントの補題は関連する場合分けを再現(restate)する可能性があります。
手動の証明スクリプトと比較して、わかりやすい結果が得られます。
スクリプトは、場合分けが生成される順序に依存する必要がなくなりました。
補題は完全な証明の文脈を含んでいるので、
補題はタクティクのコードの断片であるよりも、別々にこなす(digest)方が簡単です。
このような文脈は、
スクリプトを対話的に踏むことによってモノリシックな手作業の証明から抽出することができます。
(*
The more common situation is that a large induction has several easy cases that automation makes short work of. In the remaining cases, automation performs some standard simplification. Among these cases, some may require quite involved proofs; such a case may deserve a hint lemma of its own, where the lemma statement may copy the simplified version of the case. Alternatively, the proof script for the main theorem may be extended with some automation code targeted at the specific case. Even such targeted scripting is more desirable than manual proving, because it may be read and understood without knowledge of a proof's hierarchical structure, case ordering, or name binding structure.
*)
より一般的な状況は、大きな帰納法は、
自動化が短い作業を行う、いくつかの簡単な場合を有することです。
それ以外の場合、自動化は標準的な単純化を実行します。
これらのケースの中には、かなり複雑な証明が必要なものもあります。
そのような場合は、
その補題のステートメントが場合分けの単純化されたバージョンをコピーしたのならば、
それ自身のヒントの補題に相当するかもしれません。
あるいは、主な定理のための証明スクリプトは、
特定の場合を対象とするいくつかの自動化コードで拡張することができるかもしれません。
そのような対象のスクリプトは、
証明の階層構造や、ケースの順序付けや、名前の束縛の構造(name binding structure)の知識がなくても、
読まれ理解される可能性があるため、
手作業による証明よりも望ましいです。
(*
A competing alternative to the common style of Coq tactics is the%\index{declarative proof scripts}% _declarative_ style, most frequently associated today with the %\index{Isar}%Isar%~\cite{Isar}% language. A declarative proof script is very explicit about subgoal structure and introduction of local names, aiming for human readability. The coding of proof automation is taken to be outside the scope of the proof language, an assumption related to the idea that it is not worth building new automation for each serious theorem. I have shown in this book many examples of theorem-specific automation, which I believe is crucial for scaling to significant results. Declarative proof scripts make it easier to read scripts to modify them for theorem statement changes, but the alternate%\index{adaptive proof scripts}% _adaptive_ style from this book allows use of the _same_ scripts for many versions of a theorem.
*)
Coq戦術の一般的なスタイルの代わりに、
%\index{declarative proof scripts}% _declarative_ ＿宣言的＿ スタイルがあります。
これは今日最も頻繁に
%\index{Isar}%Isar%~\cite{Isar}% 言語に関連付けられています。
宣言的な証明スクリプトは、
人間の可読性を目指して、サブゴール構造とローカル名の導入について非常に明示的です。
自動証明のコーディングは、
各々の深刻な定理のための新しい自動化を構築する価値がないという考えに関連した
証明言語の範囲外であるとみなされます。
この本では、定理に特化した自動化の多くの例を示しました。
私は、重要な結果を得るために重要であると信じています。
宣言的な証明スクリプトを使用すると、定理の変更のためにスクリプトを変更しやすくなりますが、
本書の代替 %\index{adaptive proof scripts}% _adaptive_ ＿適応形＿ スタイルでは、
多くのバージョンの定理で _same_ ＿同じ＿ スクリプトを使用できます。
(*
Perhaps I am a pessimist for thinking that fully formal proofs will inevitably consist of details that are uninteresting to people, but it is my preference to focus on conveying proof-specific details through choice of lemmas. Additionally, adaptive Ltac scripts contain bits of automation that can be understood in isolation. For instance, in a big [repeat match] loop, each case can generally be digested separately, which is a big contrast from trying to understand the hierarchical structure of a script in a more common style. Adaptive scripts rely on variable binding, but generally only over very small scopes, whereas understanding a traditional script requires tracking the identities of local variables potentially across pages of code.
*)
おそらく私は、形式的な証明の全体が
必然的に、人々には面白くない詳細で構成されていると考える悲観論者ですが、
補題の選択を通じて証明固有の詳細を伝えることに焦点を当てることが、私の好みです。
さらに、適応形(adaptive)のLtacスクリプトには、
独立して理解できる一連の自動化が含まれています。
たとえば、大きな[repeat match]ループでは、それぞれのケースを別々に消化することができます。
これは、スクリプトの階層構造をより一般的なスタイルで理解しようとするのとは大きく異なっています。
適応形のスクリプトは可変な束縛に依存(rely)しますが、
一般的に非常に小さなスコープでしか使用だけです。
一方、従来のスクリプトを理解するには、
コードのページ全体で、潜在的なローカル変数の同一性(identities)を追跡する必要があります。
(*
One might also wonder why it makes sense to prove all theorems automatically (in the sense of adaptive proof scripts) but not construct all programs automatically. My view there is that _program synthesis_ is a very useful idea that deserves broader application! In practice, there are difficult obstacles in the way of finding a program automatically from its specification. A typical specification is not exhaustive in its description of program properties. For instance, details of performance on particular machine architectures are often omitted. As a result, a synthesized program may be correct in some sense while suffering from deficiencies in other senses. Program synthesis research will continue to come up with ways of dealing with this problem, but the situation for theorem proving is fundamentally different. Following mathematical practice, the only property of a formal proof that we care about is which theorem it proves, and it is trivial to check this property automatically. In other words, with a simple criterion for what makes a proof acceptable, automatic search is straightforward. Of course, in practice we also care about understandability of proofs to facilitate long-term maintenance, which is just what motivates the techniques outlined above, and the next section gives some related advice. *)
すべての定理を自動的に（適応形の証明スクリプトの意味で）証明するのはなぜ理にかなっているでしょうが、
すべてのプログラムを自動的に構築するのはそうではありあせん。
私の見解では、_program synthesis_ ＿プログラム合成＿
は広範なアプリケーションに適した非常に便利なアイデアです！
実際には、仕様から自動的にプログラムを見つけるのに困難な障害があります。
典型的な仕様は、プログラム特性の記述において網羅的ではありません。
例えば、特定の機械アーキテクチャ上の性能の詳細は、しばしば省略されます。
結果として、合成されたプログラムは、ある意味では正しいかもしれませんが、
別の観点から欠陥に苦しみます。
プログラム合成の研究はこの問題に対処する方法を生み出し続けますが、
定理証明のための状況は基本的にに異なります。
数学的な実践に続いて、
私たちが気にする形式証明の唯一の性質は、それが証明する定理であり、
この特性を自動的にチェックすることは自明です。
言い換えれば、
証明を受け入れられるものとする、簡単な基準(criterion)では、自動探索は簡単です。
もちろん、実際には、
長期の保守を容易にするための証明の理解可能性(understandability)にも気を配ります。
これは上に概説した技術を動機付けるものであり、
次の節ではいくつかの関連するアドバイスを提供します。
*)
(*
(** * Debugging and Maintaining Automation *)
*)
(** * 自動化証明のデバックと保守 *)
(**
(* Fully automated proofs are desirable because they open up possibilities for automatic adaptation to changes of specification. A well-engineered script within a narrow domain can survive many changes to the formulation of the problem it solves. Still, as we are working with higher-order logic, most theorems fall within no obvious decidable theories. It is inevitable that most long-lived automated proofs will need updating.
*)
完全に自動化された証明は、仕様の変更に対して自動的に適応することの可能性を広げているので、
望ましいです。
狭い領域内のうまく設計されたスクリプトは、
それが解決する問題の定式化に多くの変更を生き残ることができます。
それでも、高階論理を使って作業しているので、ほとんどの定理は明らかな決定可能な定理にはなりません。
長く使われている自動化された証明のほとんどは更新が必要であることは避けられません。
(*
Before we are ready to update our proofs, we need to write them in the first place. While fully automated scripts are most robust to changes of specification, it is hard to write every new proof directly in that form. Instead, it is useful to begin a theorem with exploratory proving and then gradually refine it into a suitable automated form.
*)
証明を更新する準備が整う前に、それらの証明を最初に書く必要があります。
完全に自動化されたスクリプトは仕様の変更に対して最も堅牢ですが、
新しいすべての証明をその形式で直接書き込むことは困難です。
代わりに、定理を、探索的な証明(exploratory proving)で開始し、
それを徐々に適切な自動化された形式に修正することは有用です。
(*
Consider this theorem from Chapter 8, which we begin by proving in a mostly manual way, invoking [crush] after each step to discharge any low-hanging fruit. Our manual effort involves choosing which expressions to case-analyze on. *)
第8章のこの定理を考えてみましょう。ほとんど手作業で証明することから始まり、
各ステップの後に、さっさと済ますべきこと(low-hanging fruit)を済ますために[crush]を呼びます。
手作業では、場合分け分析の対象となる式を選択する必要があります。
*)
(* suhara: MoreDep がうまく読めないので「Cpdt.」を付けた。 *)
(* begin hide *)
Require Import Cpdt.MoreDep.
(* end hide *)
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
(* begin thide *)
induction e; crush.
dep_destruct (cfold e1); crush.
dep_destruct (cfold e2); crush.
dep_destruct (cfold e1); crush.
dep_destruct (cfold e2); crush.
dep_destruct (cfold e1); crush.
dep_destruct (cfold e2); crush.
dep_destruct (cfold e1); crush.
dep_destruct (expDenote e1); crush.
dep_destruct (cfold e); crush.
dep_destruct (cfold e); crush.
Qed.
(**
(* In this complete proof, it is hard to avoid noticing a pattern. We rework the proof, abstracting over the patterns we find. *)
この完全な証明では、パターンに気づくのを避けるのは難しいです。
見つけたパターンを抽象化して証明を書き直します。
*)
Reset cfold_correct.
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
induction e; crush.
(**
(* The expression we want to destruct here turns out to be the discriminee of a [match], and we can easily enough write a tactic that destructs all such expressions. *)
ここで destruct しようとしている式は、
[match]で場合分け(discriminee)しようとしているものであり、
そのような表現をすべて destruct するタクティクを簡単に書くことができます。
*)
Ltac t :=
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
end; crush).
t.
(**
(* This tactic invocation discharges the whole case. It does the same on the next two cases, but it gets stuck on the fourth case. *)
このタクティクの使用はすべての場合を済まします。
次の2つの場合では同じですが、第4番めの場合では立ち往生します。
*)
t.
t.
t.
(**
(* The subgoal's conclusion is:
*)
第4番めのサブゴールの結論は：
[[
============================
(if expDenote e1 then expDenote (cfold e2) else expDenote (cfold e3)) =
expDenote (if expDenote e1 then cfold e2 else cfold e3)
]]
(*
We need to expand our [t] tactic to handle this case. *)
この場合を扱うためには、[t] タクティクを拡張する必要があります。
*)
Ltac t' :=
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- (if ?E then _ else _) = _ ] => destruct E
end; crush).
t'.
(**
(* Now the goal is discharged, but [t'] has no effect on the next subgoal. *)
今度は、ゴールは済まされていますが、[t ']は次のサブゴールに影響を与えません。
*)
t'.
(**
(* A final revision of [t] finishes the proof. *)
[t]の最終の改訂版は、証明を終了します。
*)
Ltac t'' :=
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- (if ?E then _ else _) = _ ] => destruct E
| [ |- context[match pairOut ?E with Some _ => _
| None => _ end] ] =>
dep_destruct E
end; crush).
t''.
t''.
Qed.
(**
(* We can take the final tactic and move it into the initial part of the proof script, arriving at a nicely automated proof. *)
最終的なタクティクを採用し、それを証明スクリプトの最初の部分に移して、
うまく自動化された証明に到達しました。
*)
Reset cfold_correct.
Theorem cfold_correct : forall t (e : exp t), expDenote e = expDenote (cfold e).
induction e; crush;
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- (if ?E then _ else _) = _ ] => destruct E
| [ |- context[match pairOut ?E with Some _ => _
| None => _ end] ] =>
dep_destruct E
end; crush).
Qed.
(* end thide *)
(**
(* Even after we put together nice automated proofs, we must deal with specification changes that can invalidate them. It is not generally possible to step through single-tactic proofs interactively. There is a command %\index{Vernacular commands!Debug On}%[Debug On] that lets us step through points in tactic execution, but the debugger tends to make counterintuitive choices of which points we would like to stop at, and per-point output is quite verbose, so most Coq users do not find this debugging mode very helpful. How are we to understand what has broken in a script that used to work?
*)
よい自動化された証明を作った後でさえも、
それらを無効にすることができる仕様の変更に対処する必要があります。
タクティックのひとつずつ(single-tactic)によって、
対話的に証明を進めること(step through)は、一般的に不可能です。
コマンド %\index{Vernacular commands!Debug On}%[Debug On] を使用すると、
タクティクの実行(step through)のポイントを進めることができますが、
デバッカは直感に反して停止したいポイントを選択する傾向があり、
ポイントごとの出力は非常に冗長です。
したがって、Coqのほとんどのユーザーはこれを便利だとは気づきません。
以前使用していたスクリプトで何が壊れているのかを理解するにはどうすればよいでしょうか？
(*
An example helps demonstrate a useful approach. Consider what would have happened in our proof of [reassoc_correct] if we had first added an unfortunate rewriting hint. *)
例は、有用なアプローチを示すのに役立ちます。
不適切な書き換え(rewrite)のためのヒントを追加してしまった場合、
[reassoc_correct]の証明で何が起きたかを考えてみましょう。
*)
Reset reassoc_correct.
Theorem confounder : forall e1 e2 e3,
eval e1 * eval e2 * eval e3 = eval e1 * (eval e2 + 1 - 1) * eval e3.
crush.
Qed.
Hint Rewrite confounder.
Theorem reassoc_correct : forall e, eval (reassoc e) = eval e.
(* begin thide *)
induction e; crush;
match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
(**
(* One subgoal remains: *)
ひとつのサブゴールが残ります：
[[
============================
eval e1 * (eval e3 + 1 - 1) * eval e4 = eval e1 * eval e2
]]
(*
The poorly chosen rewrite rule fired, changing the goal to a form where another hint no longer applies. Imagine that we are in the middle of a large development with many hints. How would we diagnose the problem? First, we might not be sure which case of the inductive proof has gone wrong. It is useful to separate out our automation procedure and apply it manually. *)
不適切に選択された書き換え規則選択され(fired)、
ゴールを別のヒントが適用されなくなった式(form)に変更しました。
私たちが多くのヒントを持つ大きな開発の真っ只中にいると想像してください。
問題をどのように診断しますか？
最初に、帰納的な証明のどの場合分けが間違っているのかわからないかもしれません。
自動化した手順を分けて手動で適用すると便利です。
*)
Restart.
Ltac t := crush; match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] =>
destruct E; crush
end.
induction e.
(**
(* Since we see the subgoals before any simplification occurs, it is clear that we are looking at the case for constants. Our [t] makes short work of it. *)
単純化が起こる前にサブゴールを見るので、
（最初のサブゴールは）定数の場合分けを見ていることがわかります。
*)
t.
(**
(* The next subgoal, for addition, is also discharged without trouble. *)
加算(addition)のための、次のサブゴールも問題なく済まされます(discharged)。
*)
t.
(**
(* The final subgoal is for multiplication, and it is here that we get stuck in the proof state summarized above. *)
最後のサブゴールはは乗算(multiplication)のためのものであり、
ここでは、上で説明した状態で、証明は立ち往生します。
*)
t.
(**
(* What is [t] doing to get us to this point? The %\index{tactics!info}%[info] command can help us answer this kind of question. (As of this writing, [info] is no longer functioning in the most recent Coq release, but I hope it returns.) *)
この時点で [t] は何をしていますか？
%\index{tactics!info}%[info] コマンドはこの種の質問に答えるのに役立ちます。
これを書いている時点で、最近のCoqのリリースでは、[info] はもう機能していませんが、
私は復帰することを期待しています。
*)
Undo.
info t.
(* begin hide *)
(* begin thide *)
Definition eir := eq_ind_r.
(* end thide *)
(* end hide *)
(** %\vspace{-.15in}%[[
== simpl in *; intuition; subst; autorewrite with core in *;
simpl in *; intuition; subst; autorewrite with core in *;
simpl in *; intuition; subst; destruct (reassoc e2).
simpl in *; intuition.
simpl in *; intuition.
simpl in *; intuition; subst; autorewrite with core in *;
refine (eq_ind_r
(fun n : nat =>
n * (eval e3 + 1 - 1) * eval e4 = eval e1 * eval e2) _ IHe1);
autorewrite with core in *; simpl in *; intuition;
subst; autorewrite with core in *; simpl in *;
intuition; subst.
]]
(*
A detailed trace of [t]'s execution appears. Since we are using the very general [crush] tactic, many of these steps have no effect and only occur as instances of a more general strategy. We can copy-and-paste the details to see where things go wrong. *)
[t]の実行の詳細なトレースが表示されます。
非常に一般的な[crush]タクティクを使用しているので、
これらのステップの多くは効果がなく、より一般的なタクティクのインスタンスとしてのみ発生します。
詳細をコピー＆ペーストして、どこが間違っているかを確認することができます。
*)
Undo.
(**
(* We arbitrarily split the script into chunks. The first few seem not to do any harm. *)
私たちは任意にスクリプトを複数の塊に分割しています。
最初のいくつかは悪影響(harm)を及ぼさないようです。
*)
simpl in *; intuition; subst; autorewrite with core in *.
simpl in *; intuition; subst; autorewrite with core in *.
simpl in *; intuition; subst; destruct (reassoc e2).
simpl in *; intuition.
simpl in *; intuition.
(**
(* The next step is revealed as the culprit, bringing us to the final unproved subgoal. *)
次のステップは、最終的に証明されないいサブゴールに至らせる原因(culprit)として、明かにされます。
*)
simpl in *; intuition; subst; autorewrite with core in *.
(**
(* We can split the steps further to assign blame. *)
私たちはさらに責任を明確にする(assign blame)ためにステップを分けることができます。
*)
Undo.
simpl in *.
intuition.
subst.
autorewrite with core in *.
(**
(* It was the final of these four tactics that made the rewrite. We can find out exactly what happened. The [info] command presents hierarchical views of proof steps, and we can zoom down to a lower level of detail by applying [info] to one of the steps that appeared in the original trace. *)
これらの4つのタクティクのうち最後のものは、書き換えを行ないました。
何が起こったのかを正確に知ることができます。
[info]コマンドは証明のステップの階層の視点(view)を示し、
元のトレースに表示されたステップのひとつ[info]を適用することで、
より詳細なレベルまでズームダウンすることができます。
*)
Undo.
info autorewrite with core in *.
(** %\vspace{-.15in}%[[
== refine (eq_ind_r (fun n : nat => n = eval e1 * eval e2) _
(confounder (reassoc e1) e3 e4)).
]]
(*
The way a rewrite is displayed is somewhat baroque, but we can see that theorem [confounder] is the final culprit. At this point, we could remove that hint, prove an alternate version of the key lemma [rewr], or come up with some other remedy. Fixing this kind of problem tends to be relatively easy once the problem is revealed. *)
書き換えの方法はやや凝ったもの(baroque)ですが、
定理[confounder]が最終的な原因(culprit)であることがわかります。
この時点で、そのヒントを取り除き、鍵となる補題[rewr]の代替バージョンを証明するか、
あるいは他のいくつかの救済方法を考え出すことができます。
この種の問題を解決するには、問題が明らかになったならば、比較的容易になる傾向があります。
*)
Abort.
(* end thide *)
(**
(* Sometimes a change to a development has undesirable performance consequences, even if it does not prevent any old proof scripts from completing. If the performance consequences are severe enough, the proof scripts can be considered broken for practical purposes.
*)
時に、古い証明スクリプトが完成しないようにしても、
開発への変更は望ましくないパフォーマンスへの影響(consequences)をもたらすことがあります。
パフォーマンスへの影響が十分に厳しい場合は、
実際的な意味で、証明スクリプトが壊れたとみなすことができます。
(*
Here is one example of a performance surprise. *)
パフォーマンスについての驚きの一例を以下に示します。
*)
Section slow.
Hint Resolve trans_eq.
(**
(* The central element of the problem is the addition of transitivity as a hint. With transitivity available, it is easy for proof search to wind up exploring exponential search spaces. We also add a few other arbitrary variables and hypotheses, designed to lead to trouble later. *)
問題の中心的な要素は、推移性(transitivity)をヒントとして追加することです。
推移性を利用すると、証明検索で指数関数的な探索空間を探索することが容易になり、
後でトラブルを起こします。
*)
Variable A : Set.
Variables P Q R S : A -> A -> Prop.
Variable f : A -> A.
Hypothesis H1 : forall x y, P x y -> Q x y -> R x y -> f x = f y.
Hypothesis H2 : forall x y, S x y -> R x y.
(**
(* We prove a simple lemma very quickly, using the %\index{Vernacular commands!Time}%[Time] command to measure exactly how quickly. *)
単純な補題をとても早く証明し、 %\index{Vernacular commands!Time}%[Time] コマンドを使っていかに早く
証明できるか計測できます。
*)
Lemma slow : forall x y, P x y -> Q x y -> S x y -> f x = f y.
Time eauto 6.
(** <<
Finished transaction in 0. secs (0.068004u,0.s)
>>
*)
Qed.
(**
(* Now we add a different hypothesis, which is innocent enough; in fact, it is even provable as a theorem. *)
ここで、別の仮説を追加します。これは無益なもの(innocent)です：
実際には、定理としても証明可能です。
*)
Hypothesis H3 : forall x y, x = y -> f x = f y.
Lemma slow' : forall x y, P x y -> Q x y -> S x y -> f x = f y.
Time eauto 6.
(** <<
Finished transaction in 2. secs (1.264079u,0.s)
>>
(*
%\vspace{-.15in}%Why has the search time gone up so much? The [info] command is not much help, since it only shows the result of search, not all of the paths that turned out to be worthless. *)
%\vspace{-.15in}% 検索時間があまりにも長くなったのはなぜでしょうか？
[info]コマンドはあまり役に立ちません。
検索の結果だけを表示するだけで、有用でないと判明したすべてのパスが表示されるわけではありません。
*)
(* begin thide *)
Restart.
info eauto 6.
(** %\vspace{-.15in}%[[
== intro x; intro y; intro H; intro H0; intro H4;
simple eapply trans_eq.
simple apply eq_refl.
simple eapply trans_eq.
simple apply eq_refl.
simple eapply trans_eq.
simple apply eq_refl.
simple apply H1.
eexact H.
eexact H0.
simple apply H2; eexact H4.
]]
(*
This output does not tell us why proof search takes so long, but it does provide a clue that would be useful if we had forgotten that we added transitivity as a hint. The [eauto] tactic is applying depth-first search, and the proof script where the real action is ends up buried inside a chain of pointless invocations of transitivity, where each invocation uses reflexivity to discharge one subgoal.
Each increment to the depth argument to [eauto] adds another silly use of transitivity. This wasted proof effort only adds linear time overhead, as long as proof search never makes false steps. No false steps were made before we added the new hypothesis, but somehow the addition made possible a new faulty path. To understand which paths we enabled, we can use the %\index{tactics!debug}%[debug] command. *)
この出力は、証明検索に時間がかかりすぎる理由を教えてくれませんが、
推論をヒントとして追加したことを忘れてしまった場合に役立つヒントを提供します。
[eauto]タクティクは深さ優先探索を適用しており、
実際のアクションが終わっている証明スクリプトは、
それぞれの呼び出しがひとつの副目標を済ます(discharege)ために反射性を使用する
無意味な呼び出しの連鎖の中に埋もれてしまいます。
[eauto]の深さを指定する引数への各増分は、推論の別の愚かな使用を追加します。
この浪費された証明の努力は、証明検索が誤ったステップを決してしない限り、
線形時間オーバーヘッドを追加するだけです。
新しい仮説を追加する前に、間違った手順はありませんでしたが、
何らかの形で追加すると、新しい欠陥のあるパスが可能になりました。
有効にしたパスを理解するために、%\index{tactics!debug}%[debug] コマンドを使用できます。
*)
Restart.
debug eauto 6.
(* begin hide *)
(* begin thide *)
Definition deeeebug := (@eq_refl, @sym_eq).
(* end thide *)
(* end hide *)
(**
(* The output is a large proof tree. The beginning of the tree is enough to reveal what is happening:
*)
出力は大きな証明木です。
木の始まりは何が起こっているかを明らかにするには十分です：
[[
1 depth=6
1.1 depth=6 intro
1.1.1 depth=6 intro
1.1.1.1 depth=6 intro
1.1.1.1.1 depth=6 intro
1.1.1.1.1.1 depth=6 intro
1.1.1.1.1.1.1 depth=5 apply H3
1.1.1.1.1.1.1.1 depth=4 eapply trans_eq
1.1.1.1.1.1.1.1.1 depth=4 apply eq_refl
1.1.1.1.1.1.1.1.1.1 depth=3 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1 depth=3 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1 depth=2 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1 depth=2 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1.1.1 depth=1 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1.1.1 depth=1 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1.1.1.1.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1.1.2 depth=1 apply sym_eq ; trivial
1.1.1.1.1.1.1.1.1.1.1.1.1.1.2.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.1.1.3 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2 depth=2 apply sym_eq ; trivial
1.1.1.1.1.1.1.1.1.1.1.1.2.1 depth=1 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2.1.1 depth=1 apply eq_refl
1.1.1.1.1.1.1.1.1.1.1.1.2.1.1.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2.1.2 depth=1 apply sym_eq ; trivial
1.1.1.1.1.1.1.1.1.1.1.1.2.1.2.1 depth=0 eapply trans_eq
1.1.1.1.1.1.1.1.1.1.1.1.2.1.3 depth=0 eapply trans_eq
]]
(*
The first choice [eauto] makes is to apply [H3], since [H3] has the fewest hypotheses of all of the hypotheses and hints that match. However, it turns out that the single hypothesis generated is unprovable. That does not stop [eauto] from trying to prove it with an exponentially sized tree of applications of transitivity, reflexivity, and symmetry of equality. It is the children of the initial [apply H3] that account for all of the noticeable time in proof execution. In a more realistic development, we might use this output of [debug] to realize that adding transitivity as a hint was a bad idea. *)
最初の選択肢[eauto]は[H3]を適用することです。
なぜなら、[H3]は一致するすべての仮説とヒントの仮説が少ないためです。
しかしながら、生成された単一の仮説は証明できないことがわかりました。
それは、推移的、反射性、平等の対称性の指数関数的なツリーでそれを証明しようとすることを止めるものではありません。
証明実行の際の顕著な時間のすべてを占めるのは、最初の[apply H3]の子供たちです。
より現実的な開発では、この出力を[debug]として使用して、
推移性をヒントとして追加することは悪い考えであることに気付くかもしれません。
*)
Qed.
(* end thide *)
End slow.
(**
(* As aggravating as the above situation may be, there is greater aggravation to be had from importing library modules with commands like %\index{Vernacular commands!Require Import}%[Require Import]. Such a command imports not just the Gallina terms from a module, but also all the hints for [auto], [eauto], and [autorewrite]. Some very recent versions of Coq include mechanisms for removing hints from databases, but the proper solution is to be very conservative in exporting hints from modules. Consider putting hints in named databases, so that they may be used only when called upon explicitly, as demonstrated in Chapter 13.
*)
上記の状況が悪化すると、
%\index{Vernacular commands!Require Import}%[Require Import]
のようなコマンドを使ってライブラリモジュールをインポートすると、
非常に最近のバージョンのCoqには、
データベースからヒントを取り除くためのメカニズムが含まれていますが、
適切な解決策は、ヒントをエクスポートする際には非常に慎重でなければなりません。
ヒントを明示的に呼び出されたときにのみ使用できるように、
名前付きデータベースにヒントを入れることを検討してください（第13章を参照）。
(*
It is also easy to end up with a proof script that uses too much memory. As tactics run, they avoid generating proof terms, since serious proof search will consider many possible avenues, and we do not want to build proof terms for subproofs that end up unused. Instead, tactic execution maintains%\index{thunks}% _thunks_ (suspended computations, represented with closures), such that a tactic's proof-producing thunk is only executed when we run %\index{Vernacular commands!Qed}%[Qed]. These thunks can use up large amounts of space, such that a proof script exhausts available memory, even when we know that we could have used much less memory by forcing some thunks earlier.
*)
あまりにも多くのメモリを使用する証明スクリプトで終わるのも簡単です。
タクティクが実行されるにつれて、
重大な証拠検索では多くの可能な手段が考慮されるため、証明項の生成は避けられます。
また、使用されない副証明(subproof)に関する証明項語を作成したくありません。
代わりに、タクティックの実行は、%\index{Vernacular commands!Qed}%[Qed]
を実行したときにのみ実行されるように、%\index{thunks}% _thunks_
（中断された計算、クロージャで表される）を維持します。
これらのサンクは大量のスペースを消費することがあります。thunks を早期に強制することで
メモリを大幅に節約できたとしても、証明スクリプトが使用可能なメモリを使い果たしてしまいます。
(*
The %\index{tactics!abstract}%[abstract] tactical helps us force thunks by proving some subgoals as their own lemmas. For instance, a proof [induction x; crush] can in many cases be made to use significantly less peak memory by changing it to [induction x; abstract crush]. The main limitation of [abstract] is that it can only be applied to subgoals that are proved completely, with no undetermined unification variables in their initial states. Still, many large automated proofs can realize vast memory savings via [abstract]. *)
%\index{tactics!abstract}%[abstract] タクティカルは、
いくつかのサブゴールを独自の補題として証明することによって、
thunks を強制するのに役立ちます。
例えば、証明 [induction x; crush] は、多くの場合で、
[induction x; abstract crush] に変更することによって
大幅に少ないメモリを使用することができます。
[abstract] の主な制限は、初期状態では未定の統一変数がなく、
完全に証明されたサブゴールにしか適用できないということです。
それでも、多くの大規模な自動証明は、
[abstract]を介して膨大なメモリ節約を実現することができます。
*)
(*
(** * Modules *)
*)
(** * モージュール *)
(**
(*
Last chapter's examples of proof by reflection demonstrate opportunities for implementing abstract proof strategies with stronger formal guarantees than can be had with Ltac scripting. Coq's _module system_ provides another tool for more rigorous development of generic theorems. This feature is inspired by the module systems found in Standard ML%~\cite{modules}% and OCaml, and the discussion that follows assumes familiarity with the basics of one of those systems.
*)
前章のリフレクションによる証明の例は、Ltacスクリプトよりもより強力な形式的保証を伴う抽象的な証明戦略を実装する機会を示しています。
Coqの ＿モジュール・システム＿ は、一般的な定理(generic theorems)の
厳格な開発のための別なツールを提供します。
この機能は、Standard ML %~\cite{modules}% と OCaml にあるモジュールz・システムから
インスピレーションを受けています。以下の議論では、
これらのシステムのひとつについて熟知していることを前提とします。
(*
ML modules facilitate the grouping of %\index{abstract type}%abstract types with operations over those types. Moreover, there is support for%\index{functor}% _functors_, which are functions from modules to modules. A canonical example of a functor is one that builds a data structure implementation from a module that describes a domain of keys and its associated comparison operations.
*)
MLのモジュールは、%\index{abstract type}%抽象型 (abstract types) と
それらの型に対する操作のグループ化を容易にします。
また、モジュール間の関数である %\index{functor}% ＿関手＿ (_functors_) もサポートされています。
関手の標準的な例は、キーとなるのドメインと、
関連する比較演算子(* suhara: 結合性を満たす、ではなないと思う*)を記述するモジュールから
データ構造の実装を構築するものです。
(*
When we add modules to a base language with dependent types, it becomes possible to use modules and functors to formalize kinds of reasoning that are common in algebra. For instance, the following module signature captures the essence of the algebraic structure known as a group. A group consists of a carrier set [G], an associative binary operation [f], a left identity element [id] for [f], and an operation [i] that is a left inverse for [f].%\index{Vernacular commands!Module Type}% *)
依存型を持つ基本言語にモジュールを追加すると、
モジュールとファンクタを使用して、代数で一般的な推論の種類を正式化することが可能になります。
例えば、以下のモジュールのシグネチャは、群(group)と呼ばれる代数構造の本質を捉えています。
群は、台集合(carrier set) [G]、
結合性を満たす二項演算[f]、
[f]の左単位元[id]、
[f]の左逆元ある演算[i]で構成されます。
%\index{Vernacular commands!Module Type}%
*)
Module Type GROUP.
Parameter G : Set.
Parameter f : G -> G -> G.
Parameter id : G.
Parameter i : G -> G.
Axiom assoc : forall a b c, f (f a b) c = f a (f b c).
Axiom ident : forall a, f id a = a.
Axiom inverse : forall a, f (i a) a = id.
End GROUP.
(**
(* Many useful theorems hold of arbitrary groups. We capture some such theorem statements in another module signature.%\index{Vernacular commands!Declare Module}% *)
多くの便利な定理は任意の群を保持していますが、
他のモジュールのシグネチャでそのような定理文をいくつか取ります。
%\index{Vernacular commands!Declare Module}%
*)
Module Type GROUP_THEOREMS.
Declare Module M : GROUP.
Axiom ident' : forall a, M.f a M.id = a.
Axiom inverse' : forall a, M.f a (M.i a) = M.id.
Axiom unique_ident : forall id', (forall a, M.f id' a = a) -> id' = M.id.
End GROUP_THEOREMS.
(**
(* We implement generic proofs of these theorems with a functor, whose input is an arbitrary group [M]. %\index{Vernacular commands!Module}% *)
これらの定理の一般的な証明は、入力が任意の群[M]であるファンクタで実装されます。
%\index{Vernacular commands!Module}%
*)
Module GroupProofs (M : GROUP) : GROUP_THEOREMS with Module M := M.
(**
(* As in ML, Coq provides multiple options for ascribing signatures to modules. Here we use just the colon operator, which implements%\index{opaque ascription}% _opaque ascription_, hiding all details of the module not exposed by the signature. Another option is%\index{transparent ascription}% _transparent ascription_ via the [<:] operator, which checks for signature compatibility without hiding implementation details. Here we stick with opaque ascription but employ the [with] operation to add more detail to a signature, exposing just those implementation details that we need to. For instance, here we expose the underlying group representation set and operator definitions. Without such a refinement, we would get an output module proving theorems about some unknown group, which is not very useful. Also note that opaque ascription can in Coq have some undesirable consequences without analogues in ML, since not just the types but also the _definitions_ of identifiers have significance in type checking and theorem proving. *)
MLのように、Coqはシグネチャをモジュールに帰属させるための複数のオプションを提供します。
ここでは、%\index{opaque ascription}% _opaque ascription_
(* suhara: wikipedia.jp の SMLの項でも英語のまま *)
を実装するコロン演算子を使用して、
シグネチャによって公開されていないモジュールのすべての詳細を隠します。
もうひとつのオプションは、実装の詳細を隠すことなく、
シグネチャの互換性をチェックする [<:] 演算子による
%\index{transparent ascription}% _transparent ascription_
です。
ここでは、[op]を使用します。このような洗練がなければ、
あまり有用でないいくつかの未知のグループについての定理を証明する出力モジュールを得ることになります。
Coqの不透明な帰納法は、型のチェックだけでなく、
識別子の_definitions_もタイプチェックと定理証明の意味を持つため、
MLの中で関連性(analogues)がないと望ましくない結果をもたらす可能性があることにも注意してください。
*)
Module M := M.
(**
(* To ensure that the module we are building meets the [GROUP_THEOREMS] signature, we add an extra local name for [M], the functor argument. *)
構築しているモジュールが[GROUP_THEOREMS]署名を満たしていることを確認するために、
関手の引数の[M]に追加のローカル名を追加します。
*)
Import M.
(*
(** It would be inconvenient to repeat the prefix [M.] everywhere in our theorem statements and proofs, so we bring all the identifiers of [M] into the local scope unqualified.
*)
定理宣言と証明ではどこにでも接頭辞[M]を繰り返すのは不便かもしれません。
したがって、[M]のすべての識別子を無限定のローカルスコープに持ち込みます。
(*
Now we are ready to prove the three theorems. The proofs are completely manual, which may seem ironic given the content of the previous sections! This illustrates another lesson, which is that short proof scripts that change infrequently may be worth leaving unautomated. It would take some effort to build suitable generic automation for these theorems about groups, so I stick with manual proof scripts to avoid distracting us from the main message of the section. We take the proofs from the Wikipedia page on elementary group theory. *)
今我々は3つの定理を証明する準備ができています。
証明は完全にマニュアルであり、
これは前のセクションの内容を考えると皮肉に思えるかもしれません！
これは別のレッスンを示しています。
頻繁に変更される短い証明スクリプトは、自動化されないままにする価値があります。
群についてのこれらの定理に適した一般的な自動化を構築するには多少の努力が必要なので、
セクションの主なメッセージから私たちを邪魔しないように手作業による証明スクリプトを貼り付けます。
私たちは、Wikipediaの「群論入門」のページから証明を取っています。 *）
*)
Theorem inverse' : forall a, f a (i a) = id.
intro.
rewrite <- (ident (f a (i a))).
rewrite <- (inverse (f a (i a))) at 1.
rewrite assoc.
rewrite assoc.
rewrite <- (assoc (i a) a (i a)).
rewrite inverse.
rewrite ident.
apply inverse.
Qed.
Theorem ident' : forall a, f a id = a.
intro.
rewrite <- (inverse a).
rewrite <- assoc.
rewrite inverse'.
apply ident.
Qed.
Theorem unique_ident : forall id', (forall a, M.f id' a = a) -> id' = M.id.
intros.
rewrite <- (H id).
symmetry.
apply ident'.
Qed.
End GroupProofs.
(**
(* We can show that the integers with [+] form a group. *)
整数は [+] について群をなすことをしめします。
*)
Require Import ZArith.
Open Scope Z_scope.
Module Int.
Definition G := Z.
Definition f x y := x + y.
Definition id := 0.
Definition i x := -x.
Theorem assoc : forall a b c, f (f a b) c = f a (f b c).
unfold f; crush.
Qed.
Theorem ident : forall a, f id a = a.
unfold f, id; crush.
Qed.
Theorem inverse : forall a, f (i a) a = id.
unfold f, i, id; crush.
Qed.
End Int.
(**
(* Next, we can produce integer-specific versions of the generic group theorems. *)
次に、一般的な群の定理の整数固有のバージョンを生成することができます。
*)
Module IntProofs := GroupProofs(Int).
Check IntProofs.unique_ident.
(** %\vspace{-.15in}% [[
IntProofs.unique_ident
: forall e' : Int.G, (forall a : Int.G, Int.f e' a = a) -> e' = Int.e
]]
(*
Projections like [Int.G] are known to be definitionally equal to the concrete values we have assigned to them, so the above theorem yields as a trivial corollary the following more natural restatement: *)
[Int.G]のような射影(projection)は、
我々がそれらに割り当てた具体的な値と定義的に等しいことが知られているので、
上記の定理は、以下のより自然な再記述を簡単な結果としてもたらします：
*)
Theorem unique_ident : forall id', (forall a, id' + a = a) -> id' = 0.
(* begin thide *)
exact IntProofs.unique_ident.
Qed.
(* end thide *)
(**
(* As in ML, the module system provides an effective way to structure large developments. Unlike in ML, Coq modules add no expressiveness; we can implement any module as an inhabitant of a dependent record type. It is the second-class nature of modules that makes them easier to use than dependent records in many cases. Because modules may only be used in quite restricted ways, it is easier to support convenient module coding through special commands and editing modes, as the above example demonstrates. An isomorphic implementation with records would have suffered from lack of such conveniences as module subtyping and importation of the fields of a module. On the other hand, all module values must be determined statically, so modules may not be computed, e.g., within the definitions of normal functions, based on particular function parameters. *)
MLのように、モジュール・システムは、大規模な開発を構築する効果的な方法を提供します。
MLとは異なり、Coqモジュールは表現力を追加せず、
依存型のレコードのフィールド(inhabitant)として任意のモジュールを実装することができます。
多くの場合、依存レコードよりも使いやすくするセカンド・クラス(second-class nature)のモジュールです。
モジュールは非常に限定された方法でしか使用できないので、上記の例が示すように、
特別なコマンドと編集モードで便利なモジュールコーディングをサポートする方が簡単です。
レコードの同形(isomorphic)の実装は、
モジュールのサブタイプ化やモジュールのフィールドのインポートなどの利便性の欠如に悩まされていました。
一方、すべてのモジュール値は静的に決定されなければならないので、モジュールは、例えば、特定の関数パラメータに基づいて、通常の関数の定義内で計算されないことがあります。
*)
(*
(** * Build Processes *)
*)
(** * ビルド・プロセス *)
(* begin hide *)
(* begin thide *)
Module Lib.
Module A.
End A.
Module B.
End B.
Module C.
End C.
End Lib.
Module Client.
Module D.
End D.
Module E.
End E.
End Client.
(* end thide *)
(* end hide *)
(**
(* As in software development, large Coq projects are much more manageable when split across multiple files and when decomposed into libraries. Coq and Proof General provide very good support for these activities.
*)
ソフトウェア開発のように、大規模なCoqプロジェクトは、
複数のファイルに分割してライブラリに分解すると、はるかに管理しやすくなります。
CoqとProof Generalはこれらの活動を非常にうまくサポートしています。
(*
Consider a library that we will name [Lib], housed in directory <<LIB>> and split between files <<A.v>>, <<B.v>>, and <<C.v>>. A simple %\index{Makefile}%Makefile will compile the library, relying on the standard Coq tool %\index{coq\_makefile}%<<coq_makefile>> to do the hard work.
*)
ディレクトリ <<LIB>> に格納され、ファイル <<A.v>>、<<B.v>>、および <<C.v>> の間で
分割される[Lib]という名前のライブラリを考えてみましょう。
シンプルな %\index{Makefile}%Makefile は、標準的なCoqツール
%\index{coq\_makefile}%<<coq_makefile>> を使ってライブラリをコンパイルします。
<<
MODULES := A B C
VS := $(MODULES:%=%.v)
.PHONY: coq clean
coq: Makefile.coq
$(MAKE) -f Makefile.coq
Makefile.coq: Makefile $(VS)
coq_makefile -R . Lib $(VS) -o Makefile.coq
clean:: Makefile.coq
$(MAKE) -f Makefile.coq clean
rm -f Makefile.coq
>>
(*
The Makefile begins by defining a variable <<VS>> holding the list of filenames to be included in the project. The primary target is <<coq>>, which depends on the construction of an auxiliary Makefile called <<Makefile.coq>>. Another rule explains how to build that file. We call <<coq_makefile>>, using the <<-R>> flag to specify that files in the current directory should be considered to belong to the library [Lib]. This Makefile will build a compiled version of each module, such that <<X.v>> is compiled into <<X.vo>>.
*)
Makefileは、
プロジェクトに含めるファイル名のリストを保持する変数 <<VS>> を定義することから始まります。
主なターゲットは<<coq>>です。
これは<<Makefile.coq>>と呼ばれる補助的なMakefileの構成に依存します。
別のルールは、そのファイルを構築する方法を説明します。
カレント・ディレクトリのファイルをライブラリ[Lib]に属するとみなすために、
<<-R>>フラグを使用して、<<coq_makefile>> を呼び出します。
このMakefileは、（たとえば）<<X.v>>が<<X.vo>>にコンパイルされるように、
各モジュールのコンパイルされたバージョンを構築します。
(*
Now code in <<B.v>> may refer to definitions in <<A.v>> after running
*)
ここで、<<B.v>>のコードは、実行後に<<A.v>>の定義を参照することがあります
[[
Require Import Lib.A.
]]
(*
%\vspace{-.15in}%Library [Lib] is presented as a module, containing a submodule [A], which contains the definitions from <<A.v>>. These are genuine modules in the sense of Coq's module system, and they may be passed to functors and so on.
*)
%\vspace{-.15in}%ライブラリ [Lib] はモジュールとして表示され、
<<A.v>>から定義されるサブモジュール[A]を含みます。
これらはCoqのモジュール・システムの意味での本物のモジュールであり、
ファンクタ(functor)などに渡すことができます。
(*
The command [Require Import] is a convenient combination of two more primitive commands. The %\index{Vernacular commands!Require}%[Require] command finds the <<.vo>> file containing the named module, ensuring that the module is loaded into memory. The %\index{Vernacular commands!Import}%[Import] command loads all top-level definitions of the named module into the current namespace, and it may be used with local modules that do not have corresponding <<.vo>> files. Another command, %\index{Vernacular commands!Load}%[Load], is for inserting the contents of a named file verbatim. It is generally better to use the module-based commands, since they avoid rerunning proof scripts, and they facilitate reorganization of directory structure without the need to change code.
*)
[Require Import]コマンドは、さらにふたつの基本的(primitive)なコマンドの便利な組み合わせです。
%\index{Vernacular commands!Require}%[Require] コマンドは、
名前付きモジュールを含む<<.vo>>ファイルを見つけ、
モジュールがメモリにロードされていることを確認します。
%\index{Vernacular commands!Import}%[Import] コマンドは、
名前付きモジュールのすべてのトップレベルの定義を現在の名前空間にロードし、
対応する<<.vo>>ファイルを持たないローカルなモジュールで使用できます。
別のコマンド、%\index{Vernacular commands!Load}%[Load] は、
名前付きファイルの内容をそのまま挿入するためのものです。
証明スクリプトを再実行するのを避け、
コードを変更することなくディレクトリ構造の再編成を容易にするので、
モジュールベースのコマンド(suhara: Load ではなく、Require と Import)
を使用する方が一般的に適しています。
(*
Now we would like to use our library from a different development, called [Client] and found in directory <<CLIENT>>, which has its own Makefile.
*)
今度は、<<CLIENT>>ディレクトリにある、[Client]と呼ばれる独自のMakefileを持つ、
別の開発用ライブラリを使用したいと考えます。
<<
MODULES := D E
VS := $(MODULES:%=%.v)
.PHONY: coq clean
coq: Makefile.coq
$(MAKE) -f Makefile.coq
Makefile.coq: Makefile $(VS)
coq_makefile -R LIB Lib -R . Client $(VS) -o Makefile.coq
clean:: Makefile.coq
$(MAKE) -f Makefile.coq clean
rm -f Makefile.coq
>>
(*
We change the <<coq_makefile>> call to indicate where the library [Lib] is found. Now <<D.v>> and <<E.v>> can refer to definitions from [Lib] module [A] after running
*)
<<coq_makefile>>の呼び出しを変更して、ライブラリ[Lib]がどこにあるかを示します。
現在、<<D.v>>と<<E.v>>は、実行後の[Lib]モジュール[A]の定義を参照できます。
[[
Require Import Lib.A.
]]
(*
%\vspace{-.15in}\noindent{}%and <<E.v>> can refer to definitions from <<D.v>> by running
*)
%\vspace{-.15in}\noindent{}% そして、<<E.v>>は、実行によって<<D.v>>の定義を参照できます。
[[
Require Import Client.D.
]]
(*
%\vspace{-.15in}%It can be useful to split a library into several files, but it is also inconvenient for client code to import library modules individually. We can get the best of both worlds by, for example, adding an extra source file <<Lib.v>> to [Lib]'s directory and Makefile, where that file contains just this line:%\index{Vernacular commands!Require Export}%
*)
%\vspace{-.15in}% ライブラリを複数のファイルに分割すると便利ですが、
クライアントのコードが個別にライブラリのモジュールをインポートすることも不便です。
たとえば、余分なソースファイル "Lib.v"を[Lib]のディレクトリとMakefileに追加することで、
両方にとっての最良を得ることができます。
このファイルには、次の行だけが含まれています：
%\index{Vernacular commands!Require Export}%
[[
Require Export Lib.A Lib.B Lib.C.
]]
(*
%\vspace{-.15in}%Now client code can import all definitions from all of [Lib]'s modules simply by running
*)
%\vspace{-.15in}%ここで、クライアントのコードはすべての[Lib]のモジュールから、
すべての定義を単純に実行することでインポートできます。
[[
Require Import Lib.
]]
(*
%\vspace{-.15in}%The two Makefiles above share a lot of code, so, in practice, it is useful to define a common Makefile that is included by multiple library-specific Makefiles.
*)
%\vspace{-.15in}%上記のふたつのMakefileは多くのコードを共有しているので、
実際には、複数のライブラリ固有のMakefileに含まれる（定義を）
共通のMakefileに定義すると便利です。
%\medskip%
(*
The remaining ingredient is the proper way of editing library code files in Proof General. Recall this snippet of <<.emacs>> code from Chapter 2, which tells Proof General where to find the library associated with this book.
*)
残りの成分は、Proof Generalでライブラリのコードのファイルを編集する適切な方法です。
第2章の<<.emacs >>コードのこのスニペットを思い出してください。
このスニペットは、Proof Generalにこの本に関連するライブラリを見つける場所を教えてくれます。
<<
(custom-set-variables
...
'(coq-prog-args '("-R" "/path/to/cpdt/src" "Cpdt"))
...
)
>>
(*
To do interactive editing of our current example, we just need to change the flags to point to the right places.
*)
現在の例を対話的に編集するには、適切な場所を指すようにフラグを変更するだけです。
<<
(custom-set-variables
...
; '(coq-prog-args '("-R" "/path/to/cpdt/src" "Cpdt"))
'(coq-prog-args '("-R" "LIB" "Lib" "-R" "CLIENT" "Client"))
...
)
>>
(*
When working on multiple projects, it is useful to leave multiple versions of this setting in your <<.emacs>> file, commenting out all but one of them at any moment in time. To switch between projects, change the commenting structure and restart Emacs.
*)
複数のプロジェクトに取り組んでいるときは、
この設定の複数のバージョンを<<.emacs>>ファイルに残しておいて、
いつでもそのうちのひとつを除いてすべてをコメントアウトすると便利です。
プロジェクトの間で切り替えるには、コメント構造を変更してEmacsを再起動します。
(*
Alternatively, we can revisit the directory-local settings approach and write the following into a file <<.dir-locals.el>> in <<CLIENT>>:
*)
あるいは、ディレクトリにローカルな設定の方法を再訪し、
<<CLIENT>> の <<.dir-locals.el>>ファイルに次のように書き込むことができます：
<<
((coq-mode . ((coq-prog-args .
("-emacs-U" "-R" "LIB" "Lib" "-R" "CLIENT" "Client")))))
>>
(*
A downside of this approach is that users of your code may not want to trust the arbitrary Emacs Lisp programs that you are allowed to place in such files, so that they prefer to add mappings manually.
*)
このアプローチの欠点は、コードのユーザが、
そのようなファイルに置くことが許されている任意のEmacs Lispプログラムを信頼したくないことで、
マッピングを手動で追加することが好きなことです。
(*
Relatively recent versions of Coq support another, more principled approach to all this. A project's list of settings and source files may be saved in a single file named <<_CoqProject>>, which is processed uniformly by recent enough versions of <<coq_makefile>>, Proof General, and CoqIDE. For details, see the Coq manual.
*)
Coqの比較的最近のバージョンでは、
このすべてに対するもう一つのより原理的なアプローチがサポートされています。
プロジェクトの設定とソースファイルのリストは、
最新のバージョンの、<<coq_makefile>>、Proof General、CoqIDEで
一様に処理される <<_CoqProject>> という名前の単一ファイルに保存されます。
詳細については、Coqマニュアルを参照してください。
*)
(* END *)
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %Version
// \ \ Application: MIG
// / / Filename: circ_buffer.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:02 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Circular Buffer for synchronizing signals between clock domains. Assumes
// write and read clocks are the same frequency (but can be varying phase).
// Parameter List;
// DATA_WIDTH: # bits in data bus
// BUF_DEPTH: # of entries in circular buffer.
// Port list:
// rdata: read data
// wdata: write data
// rclk: read clock
// wclk: write clock
// rst: reset - shared between read and write sides
//Reference:
//Revision History:
// Rev 1.1 - Initial Checkin - jlogue 03/06/09
//*****************************************************************************
/******************************************************************************
**$Id: circ_buffer.v,v 1.1 2011/06/02 07:18:02 mishra Exp $
**$Date: 2011/06/02 07:18:02 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/circ_buffer.v,v $
******************************************************************************/
`timescale 1ps/1ps
module circ_buffer #
(
parameter TCQ = 100,
parameter BUF_DEPTH = 5, // valid values are 5, 6, 7, and 8
parameter DATA_WIDTH = 1
)
(
output[DATA_WIDTH-1:0] rdata,
input [DATA_WIDTH-1:0] wdata,
input rclk,
input wclk,
input rst
);
//***************************************************************************
// Local parameters
//***************************************************************************
localparam SHFTR_MSB = (BUF_DEPTH-1)/2;
//***************************************************************************
// Internal signals
//***************************************************************************
reg SyncResetRd;
reg [SHFTR_MSB:0] RdCEshftr;
reg [2:0] RdAdrsCntr;
reg SyncResetWt;
reg WtAdrsCntr_ce;
reg [2:0] WtAdrsCntr;
//***************************************************************************
// read domain registers
//***************************************************************************
always @(posedge rclk or posedge rst)
if (rst) SyncResetRd <= #TCQ 1'b1;
else SyncResetRd <= #TCQ 1'b0;
always @(posedge rclk or posedge SyncResetRd)
begin
if (SyncResetRd)
begin
RdCEshftr <= #TCQ 'b0;
RdAdrsCntr <= #TCQ 'b0;
end
else
begin
RdCEshftr <= #TCQ {RdCEshftr[SHFTR_MSB-1:0], WtAdrsCntr_ce};
if(RdCEshftr[SHFTR_MSB])
begin
if(RdAdrsCntr == (BUF_DEPTH-1)) RdAdrsCntr <= #TCQ 'b0;
else RdAdrsCntr <= #TCQ RdAdrsCntr + 1;
end
end
end
//***************************************************************************
// write domain registers
//***************************************************************************
always @(posedge wclk or posedge SyncResetRd)
if (SyncResetRd) SyncResetWt <= #TCQ 1'b1;
else SyncResetWt <= #TCQ 1'b0;
always @(posedge wclk or posedge SyncResetWt)
begin
if (SyncResetWt)
begin
WtAdrsCntr_ce <= #TCQ 1'b0;
WtAdrsCntr <= #TCQ 'b0;
end
else
begin
WtAdrsCntr_ce <= #TCQ 1'b1;
if(WtAdrsCntr_ce)
begin
if(WtAdrsCntr == (BUF_DEPTH-1)) WtAdrsCntr <= #TCQ 'b0;
else WtAdrsCntr <= #TCQ WtAdrsCntr + 1;
end
end
end
//***************************************************************************
// instantiate one RAM64X1D for each data bit
//***************************************************************************
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i = i+1) begin: gen_ram
RAM64X1D #
(
.INIT (64'h0000000000000000)
)
u_RAM64X1D
(.DPO (rdata[i]),
.SPO (),
.A0 (WtAdrsCntr[0]),
.A1 (WtAdrsCntr[1]),
.A2 (WtAdrsCntr[2]),
.A3 (1'b0),
.A4 (1'b0),
.A5 (1'b0),
.D (wdata[i]),
.DPRA0 (RdAdrsCntr[0]),
.DPRA1 (RdAdrsCntr[1]),
.DPRA2 (RdAdrsCntr[2]),
.DPRA3 (1'b0),
.DPRA4 (1'b0),
.DPRA5 (1'b0),
.WCLK (wclk),
.WE (1'b1)
);
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Simple Asynchronous Serial Comm. Device ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sasc/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: sasc_top.v,v 1.2 2006/03/30 02:47:07 rudi Exp $
//
// $Date: 2006/03/30 02:47:07 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: sasc_top.v,v $
// Revision 1.2 2006/03/30 02:47:07 rudi
// Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug
// with the DPLL and data alignment:
//
// You were right that it was a problem with the dpll. I found
// that it was possible to get two baud clocks (rx_sio_ce) during
// one bit period. I fixed the problem by delaying the input data
// signal with a shift register and using that in the equations
// for the "change" variable that controls the DPLL FSM.
//
// Revision 1.1.1.1 2002/09/16 16:16:42 rudi
// Initial Checkin
//
//
//
//
//
//
//
//
`timescale 1ns / 100ps
/*
Serial IO Interface
===============================
RTS I Request To Send
CTS O Clear to send
TD I Transmit Data
RD O Receive Data
*/
module sasc_top( clk, rst_n,
// SIO
rxd_i, txd_o, cts_i, rts_o,
// External Baud Rate Generator
sio_ce, sio_ce_x4,
// Internal Interface
din_i, dout_o, re_i, we_i, full_o, empty_o);
input clk;
input rst_n;
input rxd_i;
output txd_o;
input cts_i;
output rts_o;
input sio_ce;
input sio_ce_x4;
input [7:0] din_i;
output [7:0] dout_o;
input re_i, we_i;
output full_o, empty_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter START_BIT = 1'b0,
STOP_BIT = 1'b1,
IDLE_BIT = 1'b1;
wire [7:0] txd_p;
reg load;
wire load_e;
reg [9:0] hold_reg;
wire txf_empty;
reg txd_o;
reg shift_en;
reg [3:0] tx_bit_cnt;
reg rxd_s, rxd_r;
wire start;
reg [3:0] rx_bit_cnt;
reg rx_go;
reg [9:0] rxr;
reg rx_valid, rx_valid_r;
wire rx_we;
wire rxf_full;
reg rts_o;
reg txf_empty_r;
reg shift_en_r;
reg rxd_r1;
reg change;
reg rx_sio_ce_d, rx_sio_ce_r1, rx_sio_ce_r2, rx_sio_ce;
reg [1:0] dpll_state, dpll_next_state;
reg [5:0] rxd_dly; //New input delay used to ensure no baud clocks
// occur twice in one baud period
///////////////////////////////////////////////////////////////////
//
// IO Fifo's
//
sasc_fifo4 tx_fifo( .clk( clk ),
.rst_n( rst_n ),
.clr( 1'b0 ),
.din( din_i ),
.we( we_i ),
.dout( txd_p ),
.re( load_e ),
.full( full_o ),
.empty( txf_empty )
);
sasc_fifo4 rx_fifo( .clk( clk ),
.rst_n( rst_n ),
.clr( 1'b0 ),
.din( rxr[9:2] ),
.we( rx_we ),
.dout( dout_o ),
.re( re_i ),
.full( rxf_full ),
.empty( empty_o )
);
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
always @(posedge clk)
if(!rst_n) txf_empty_r <= 1'b1;
else
if(sio_ce) txf_empty_r <= txf_empty;
always @(posedge clk)
load <= !txf_empty_r & !shift_en & !cts_i;
assign load_e = load & sio_ce;
always @(posedge clk)
if(load_e) hold_reg <= {STOP_BIT, txd_p, START_BIT};
else
if(shift_en & sio_ce) hold_reg <= {IDLE_BIT, hold_reg[9:1]};
always @(posedge clk)
if(!rst_n) txd_o <= IDLE_BIT;
else
if(sio_ce)
if(shift_en | shift_en_r) txd_o <= hold_reg[0];
else txd_o <= IDLE_BIT;
always @(posedge clk)
if(!rst_n) tx_bit_cnt <= 4'h9;
else
if(load_e) tx_bit_cnt <= 4'h0;
else
if(shift_en & sio_ce) tx_bit_cnt <= tx_bit_cnt + 4'h1;
always @(posedge clk)
shift_en <= (tx_bit_cnt != 4'h9);
always @(posedge clk)
if(!rst_n) shift_en_r <= 1'b0;
else
if(sio_ce) shift_en_r <= shift_en;
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
always @(posedge clk)
begin
rxd_dly[5:1] <= rxd_dly[4:0];
rxd_dly[0] <= rxd_i;
rxd_s <= rxd_dly[5]; // rxd_s = delay 1
rxd_r <= rxd_s; // rxd_r = delay 2
end
assign start = (rxd_r == IDLE_BIT) & (rxd_s == START_BIT);
always @(posedge clk)
if(!rst_n) rx_bit_cnt <= 4'ha;
else
if(~rx_go & start) rx_bit_cnt <= 4'b0000;
else
if(rx_go & rx_sio_ce) rx_bit_cnt <= rx_bit_cnt + 4'h1;
always @(posedge clk)
rx_go <= (rx_bit_cnt != 4'ha);
always @(posedge clk)
rx_valid <= (rx_bit_cnt == 4'h9);
always @(posedge clk)
rx_valid_r <= rx_valid;
assign rx_we = !rx_valid_r & rx_valid & !rxf_full;
always @(posedge clk)
if(rx_go & rx_sio_ce) rxr <= {rxd_s, rxr[9:1]};
always @(posedge clk)
rts_o <= rxf_full;
///////////////////////////////////////////////////////////////////
//
// Reciever DPLL
//
// Uses 4x baud clock to lock to incoming stream
// Edge detector
always @(posedge clk)
if(sio_ce_x4) rxd_r1 <= rxd_s;
always @(posedge clk)
if(!rst_n)
change <= 1'b0;
else if ((rxd_dly[1] != rxd_r1) || (rxd_dly[1] != rxd_s))
change <= 1'b1;
else if(sio_ce_x4)
change <= 1'b0;
// DPLL FSM
always @(posedge clk or negedge rst_n)
if(!rst_n) dpll_state <= 2'h1;
else
if(sio_ce_x4) dpll_state <= dpll_next_state;
always @(dpll_state or change)
begin
rx_sio_ce_d = 1'b0;
case(dpll_state)
2'h0:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h1;
2'h1:begin
rx_sio_ce_d = 1'b1;
if(change) dpll_next_state = 3'h3;
else dpll_next_state = 3'h2;
end
2'h2:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h3;
2'h3:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h0;
endcase
end
// Compensate for sync registers at the input - allign sio
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
rx_sio_ce_r1 <= rx_sio_ce_d;
always @(posedge clk)
rx_sio_ce_r2 <= rx_sio_ce_r1;
always @(posedge clk)
rx_sio_ce <= rx_sio_ce_r1 & !rx_sio_ce_r2;
endmodule
|
// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_tx
// ============================================================
// File Name: altera_tse_pma_lvds_tx.v
// Megafunction Name(s):
// altlvds_tx
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Internal Build 97 06/25/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_pma_lvds_tx (
tx_in,
tx_inclock,
tx_out);
input [9:0] tx_in;
input tx_inclock;
output [0:0] tx_out;
wire [0:0] sub_wire0;
wire [0:0] tx_out = sub_wire0[0:0];
altlvds_tx altlvds_tx_component (
.tx_in (tx_in),
.tx_inclock (tx_inclock),
.tx_out (sub_wire0),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_enable (1'b1),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
defparam
altlvds_tx_component.common_rx_tx_pll = "ON",
altlvds_tx_component.deserialization_factor = 10,
altlvds_tx_component.implement_in_les = "OFF",
altlvds_tx_component.inclock_data_alignment = "UNUSED",
altlvds_tx_component.inclock_period = 8000,
altlvds_tx_component.inclock_phase_shift = 0,
altlvds_tx_component.intended_device_family = "Stratix III",
altlvds_tx_component.lpm_type = "altlvds_tx",
altlvds_tx_component.number_of_channels = 1,
altlvds_tx_component.outclock_resource = "AUTO",
altlvds_tx_component.output_data_rate = 1250,
altlvds_tx_component.registered_input = "TX_CLKIN",
altlvds_tx_component.use_external_pll = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Clock_Choices STRING "TX_CLKIN"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "1250"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: Int_Device STRING "Stratix III"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
// Retrieval info: PRIVATE: OUTCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: Outclock_Divide_By NUMERIC "10"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "125.00"
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_CoreClock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "1"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "UNUSED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CLKIN"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: USED_PORT: tx_in 0 0 10 0 INPUT NODEFVAL tx_in[9..0]
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT_CLK_EXT GND tx_inclock
// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL tx_out[0..0]
// Retrieval info: CONNECT: @tx_in 0 0 10 0 tx_in 0 0 10 0
// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tse_pma_lvds_tx_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_tx_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_0_poc_top.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser out calibration top.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_0_poc_top #
(parameter LANE_CNT_WIDTH = 2,
parameter MMCM_SAMP_WAIT = 10,
parameter PCT_SAMPS_SOLID = 95,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter TCQ = 100,
parameter CCENABLE = 0,
parameter SCANFROMRIGHT = 0,
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK =112)
(/*AUTOARG*/
// Outputs
psincdec, poc_error, dbg_poc, psen, rise_lead_right,
rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned,
poc_backup,
// Inputs
use_noise_window, rst, psdone, poc_sample_pd, pd_out,
ninety_offsets, mmcm_edge_detect_rdy, lane, ktap_at_right_edge,
ktap_at_left_edge, clk
);
localparam SMWIDTH = 2;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ...
input ktap_at_left_edge; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ...
input ktap_at_right_edge; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ...
input [LANE_CNT_WIDTH-1:0] lane; // To u_poc_cc of mig_7series_v4_0_poc_cc.v
input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v4_0_poc_meta.v, ...
input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v4_0_poc_meta.v
input pd_out; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
input poc_sample_pd; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
input psdone; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
input rst; // To u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v, ...
input use_noise_window; // To u_poc_meta of mig_7series_v4_0_poc_meta.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [1023:0] dbg_poc; // From u_poc_cc of mig_7series_v4_0_poc_cc.v
output poc_error; // From u_poc_cc of mig_7series_v4_0_poc_cc.v
output psincdec; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
// End of automatics
/*AUTOwire*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [TAPCNTRWIDTH+1:0] diff; // From u_poc_meta of mig_7series_v4_0_poc_meta.v
wire [TAPCNTRWIDTH:0] edge_center; // From u_poc_meta of mig_7series_v4_0_poc_meta.v
wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] left; // From u_poc_meta of mig_7series_v4_0_poc_meta.v
wire [TAPCNTRWIDTH-1:0] right; // From u_poc_meta of mig_7series_v4_0_poc_meta.v
wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v4_0_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire run_end; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [1:0] run_ends; // From u_poc_meta of mig_7series_v4_0_poc_meta.v
wire run_polarity; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire run_too_small; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [SAMPCNTRWIDTH-1:0] samp_cntr; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v4_0_poc_cc.v
wire [SAMPCNTRWIDTH:0] samps_hi; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire samps_one; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v4_0_poc_cc.v
wire samps_zero; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [SMWIDTH-1:0] sm; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v4_0_poc_tap_base.v
wire [TAPCNTRWIDTH:0] window_center; // From u_poc_meta of mig_7series_v4_0_poc_meta.v
// End of automatics
output psen;
output [TAPCNTRWIDTH-1:0] rise_lead_right;
output [TAPCNTRWIDTH-1:0] rise_trail_right;
output mmcm_edge_detect_done;
output mmcm_lbclk_edge_aligned;
output poc_backup;
mig_7series_v4_0_poc_tap_base #
(/*AUTOINSTPARAM*/
// Parameters
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SMWIDTH (SMWIDTH),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc_tap_base
(/*AUTOINST*/
// Outputs
.psen (psen),
.psincdec (psincdec),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.run_too_small (run_too_small),
.samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]),
.samps_hi (samps_hi[SAMPCNTRWIDTH:0]),
.samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]),
.samps_one (samps_one),
.samps_zero (samps_zero),
.sm (sm[SMWIDTH-1:0]),
.tap (tap[TAPCNTRWIDTH-1:0]),
// Inputs
.clk (clk),
.pd_out (pd_out),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.rst (rst),
.samples (samples[SAMPCNTRWIDTH:0]),
.samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]));
mig_7series_v4_0_poc_meta #
(/*AUTOINSTPARAM*/
// Parameters
.SCANFROMRIGHT (SCANFROMRIGHT),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc_meta
(/*AUTOINST*/
// Outputs
.diff (diff[TAPCNTRWIDTH+1:0]),
.edge_center (edge_center[TAPCNTRWIDTH:0]),
.left (left[TAPCNTRWIDTH-1:0]),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.poc_backup (poc_backup),
.right (right[TAPCNTRWIDTH-1:0]),
.run_ends (run_ends[1:0]),
.window_center (window_center[TAPCNTRWIDTH:0]),
// Inputs
.clk (clk),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.ninety_offsets (ninety_offsets[1:0]),
.rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]),
.rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]),
.rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
.rst (rst),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.run_too_small (run_too_small),
.use_noise_window (use_noise_window));
/*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" (
.\(.*\)lead (\1lead_@@"vl-bits"),
.\(.*\)trail (\1trail_@@"vl-bits"),
.select0 (ktap_at_@_edge),
.select1 (1'b1),)*/
mig_7series_v4_0_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_right
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (ktap_at_right_edge), // Templated
.select1 (1'b1), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
mig_7series_v4_0_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_left
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (ktap_at_left_edge), // Templated
.select1 (1'b1), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
wire not_ktap_at_right_edge = ~ktap_at_right_edge;
wire not_ktap_at_left_edge = ~ktap_at_left_edge;
/*mig_7series_v4_0_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" (
.\(.*\)lead (\1lead_@@"vl-bits"),
.\(.*\)trail (\1trail_@@"vl-bits"),
.select0 (not_ktap_at_right_edge),
.select1 (not_ktap_at_left_edge),)*/
mig_7series_v4_0_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_center
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (not_ktap_at_right_edge), // Templated
.select1 (not_ktap_at_left_edge), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
mig_7series_v4_0_poc_cc #
(/*AUTOINSTPARAM*/
// Parameters
.CCENABLE (CCENABLE),
.LANE_CNT_WIDTH (LANE_CNT_WIDTH),
.PCT_SAMPS_SOLID (PCT_SAMPS_SOLID),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SAMPLES (SAMPLES),
.SMWIDTH (SMWIDTH),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TCQ (TCQ))
u_poc_cc
(/*AUTOINST*/
// Outputs
.dbg_poc (dbg_poc[1023:0]),
.poc_error (poc_error),
.samples (samples[SAMPCNTRWIDTH:0]),
.samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]),
// Inputs
.clk (clk),
.diff (diff[TAPCNTRWIDTH+1:0]),
.edge_center (edge_center[TAPCNTRWIDTH:0]),
.fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]),
.fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]),
.fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]),
.fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]),
.fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]),
.fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.lane (lane[LANE_CNT_WIDTH-1:0]),
.left (left[TAPCNTRWIDTH-1:0]),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.poc_backup (poc_backup),
.psen (psen),
.right (right[TAPCNTRWIDTH-1:0]),
.rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]),
.rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]),
.rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
.rst (rst),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_ends (run_ends[1:0]),
.run_polarity (run_polarity),
.run_too_small (run_too_small),
.samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]),
.samps_hi (samps_hi[SAMPCNTRWIDTH:0]),
.samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]),
.samps_one (samps_one),
.samps_zero (samps_zero),
.sm (sm[SMWIDTH-1:0]),
.tap (tap[TAPCNTRWIDTH-1:0]),
.window_center (window_center[TAPCNTRWIDTH:0]));
endmodule // mig_7series_v4_0_poc_top
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r,
inhbt_rd_r, inhbt_wr_r, wtr_inhbt_config_r, maint_rank_r, maint_zq_r,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd_r;
output [RANKS-1:0] inhbt_wr_r;
output [RANKS-1:0] wtr_inhbt_config_r;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
rank_cntrl#
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd_r (inhbt_rd_r[ID]),
.inhbt_wr_r (inhbt_wr_r[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
rank_common#
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_zq_req (app_zq_req),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
module top (
input wire i_clk,
input wire i_clkb,
input wire i_rst,
input wire i_ce,
output wire o_q1,
output wire o_q2,
input wire [11:0] io
);
// BUFGs
wire clk;
wire clkb;
BUFG bufg_1 (.I(i_clk), .O(clk));
BUFG bufg_2 (.I(i_clkb), .O(clkb));
// Generate IDDR cases
wire [11:0] q1;
wire [11:0] q2;
assign o_q1 = |q1;
assign o_q2 = |q2;
genvar sa, e, i, sr, inv;
generate begin
// SRTYPE
for (sa = 0; sa < 2; sa = sa + 1) begin
localparam SRTYPE = (sa != 0) ? "SYNC" : "ASYNC";
localparam sa_idx = sa;
IDDR_2CLK # (
.SRTYPE(SRTYPE)
) iddr_sr_type (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[sa_idx]), .Q2(q2[sa_idx]),
.D(io[sa_idx])
);
end
// DDR_CLK_EDGE
for (e = 0; e < 3; e = e + 1) begin
localparam EDGE = (e == 0) ? "SAME_EDGE" :
(e == 1) ? "SAME_EDGE_PIPELINED" :
/*(e == 2) ?*/ "OPPOSITE_EDGE";
localparam e_idx = 2 + e;
IDDR_2CLK # (
.DDR_CLK_EDGE(EDGE)
) iddr_edge (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[e_idx]), .Q2(q2[e_idx]),
.D(io[e_idx])
);
end
// Set, Reset or neither
for (sr = 0; sr < 3; sr = sr + 1) begin
localparam sr_idx = 5 + sr;
wire r;
wire s;
assign r = ((sr & 1) != 0) ? i_rst : 1'b0;
assign s = ((sr & 2) != 0) ? i_rst : 1'b0;
IDDR_2CLK iddr_sr (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[sr_idx]), .Q2(q2[sr_idx]),
.R(r), .S(s),
.D(io[sr_idx])
);
end
// INIT_Q1, INIT_Q2
for (i = 0; i < 2; i = i + 1) begin
localparam i_idx = 8 + i;
IDDR_2CLK # (
.INIT_Q1(i == 1),
.INIT_Q2(i != 1)
) iddr_init (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[i_idx]), .Q2(q2[i_idx]),
.D(io[i_idx])
);
end
// Inverted D
for (inv = 0; inv < 2; inv = inv + 1) begin
localparam inv_idx = 10 + inv;
IDDR_2CLK # (
.IS_D_INVERTED(inv != 0)
) iddr_inverted (
.C(clk), .CB(clkb), .CE(i_ce), .Q1(q1[inv_idx]), .Q2(q2[inv_idx]),
.D(io[inv_idx])
);
end
end endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_RX_ENGINE.v
// Version : 1.11
//--
//-- Description: Local-Link Receive Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_RX_ENGINE #(
parameter TCQ = 1,
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
input clk,
input rst_n,
// AXI-S
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output reg m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Memory Read data handshake with Completion
// transmit unit. Transmit unit reponds to
// req_compl assertion and responds with compl_done
// assertion when a Completion w/ data is transmitted.
output reg req_compl,
output reg req_compl_wd,
input compl_done,
output reg [2:0] req_tc, // Memory Read TC
output reg req_td, // Memory Read TD
output reg req_ep, // Memory Read EP
output reg [1:0] req_attr, // Memory Read Attribute
output reg [9:0] req_len, // Memory Read Length (1DW)
output reg [15:0] req_rid, // Memory Read Requestor ID
output reg [7:0] req_tag, // Memory Read Tag
output reg [7:0] req_be, // Memory Read Byte Enables
output reg [12:0] req_addr, // Memory Read Address
// Memory interface used to save 1 DW data received
// on Memory Write 32 TLP. Data extracted from
// inbound TLP is presented to the Endpoint memory
// unit. Endpoint memory unit reacts to wr_en
// assertion and asserts wr_busy when it is
// processing written information.
output reg [10:0] wr_addr, // Memory Write Address
output reg [7:0] wr_be, // Memory Write Byte Enable
output reg [31:0] wr_data, // Memory Write Data
output reg wr_en, // Memory Write Enable
input wr_busy // Memory Write Busy
);
localparam PIO_RX_MEM_RD32_FMT_TYPE = 7'b00_00000;
localparam PIO_RX_MEM_WR32_FMT_TYPE = 7'b10_00000;
localparam PIO_RX_MEM_RD64_FMT_TYPE = 7'b01_00000;
localparam PIO_RX_MEM_WR64_FMT_TYPE = 7'b11_00000;
localparam PIO_RX_IO_RD32_FMT_TYPE = 7'b00_00010;
localparam PIO_RX_IO_WR32_FMT_TYPE = 7'b10_00010;
localparam PIO_RX_RST_STATE = 8'b00000000;
localparam PIO_RX_MEM_RD32_DW1DW2 = 8'b00000001;
localparam PIO_RX_MEM_WR32_DW1DW2 = 8'b00000010;
localparam PIO_RX_MEM_RD64_DW1DW2 = 8'b00000100;
localparam PIO_RX_MEM_WR64_DW1DW2 = 8'b00001000;
localparam PIO_RX_MEM_WR64_DW3 = 8'b00010000;
localparam PIO_RX_WAIT_STATE = 8'b00100000;
localparam PIO_RX_IO_WR_DW1DW2 = 8'b01000000;
localparam PIO_RX_IO_MEM_WR_WAIT_STATE = 8'b10000000;
// Local Registers
reg [7:0] state;
reg [7:0] tlp_type;
wire io_bar_hit_n;
wire mem32_bar_hit_n;
wire mem64_bar_hit_n;
wire erom_bar_hit_n;
reg [1:0] region_select;
generate
if (C_DATA_WIDTH == 64) begin : pio_rx_sm_64
wire sop; // Start of packet
reg in_packet_q;
// Generate a signal that indicates if we are currently receiving a packet.
// This value is one clock cycle delayed from what is actually on the AXIS
// data bus.
always@(posedge clk)
begin
if(!rst_n)
in_packet_q <= # TCQ 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready && m_axis_rx_tlast)
in_packet_q <= # TCQ 1'b0;
else if (sop && m_axis_rx_tready)
in_packet_q <= # TCQ 1'b1;
end
assign sop = !in_packet_q && m_axis_rx_tvalid;
always @ ( posedge clk ) begin
if (!rst_n )
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
req_compl_wd <= #TCQ 1'b1;
req_tc <= #TCQ 3'b0;
req_td <= #TCQ 1'b0;
req_ep <= #TCQ 1'b0;
req_attr <= #TCQ 2'b0;
req_len <= #TCQ 10'b0;
req_rid <= #TCQ 16'b0;
req_tag <= #TCQ 8'b0;
req_be <= #TCQ 8'b0;
req_addr <= #TCQ 13'b0;
wr_be <= #TCQ 8'b0;
wr_addr <= #TCQ 11'b0;
wr_data <= #TCQ 32'b0;
wr_en <= #TCQ 1'b0;
state <= #TCQ PIO_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end
else
begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
case (state)
PIO_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
if (sop)
begin
case (m_axis_rx_tdata[30:24])
PIO_RX_MEM_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
wr_be <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_RX_IO_WR_DW1DW2;
end //if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end //if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
default : begin // other TLPs
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end // if (sop)
else
state <= #TCQ PIO_RX_RST_STATE;
end // PIO_RX_RST_STATE
PIO_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // PIO_RX_MEM_RD32_DW1DW2
PIO_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // PIO_RX_MEM_WR32_DW1DW2
PIO_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
req_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // PIO_RX_MEM_RD64_DW1DW2
PIO_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34]};
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // PIO_RX_MEM_WR64_DW1DW2
PIO_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[31:0];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // PIO_RX_MEM_WR64_DW3
PIO_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
state <= #TCQ PIO_RX_IO_WR_DW1DW2;
end // PIO_RX_IO_WR_DW1DW2
PIO_RX_WAIT_STATE : begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
else
state <= #TCQ PIO_RX_WAIT_STATE;
end // PIO_RX_WAIT_STATE
default : begin
// default case stmt
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end
end
end
else if (C_DATA_WIDTH == 128) begin : pio_rx_sm_128
// Define where the start of packet happens. Remember that PCIe dwords
// start on the right and get filled in to the left of the 128-bit data
// bus.
// Start of packet can only happen on byte 0 (right most byte) or on
// byte 8 (middle byte).
wire sof_present = m_axis_rx_tuser[14];
wire sof_right = !m_axis_rx_tuser[13] && sof_present;
wire sof_mid = m_axis_rx_tuser[13] && sof_present;
always @ ( posedge clk ) begin
if (!rst_n )
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
req_compl_wd <= #TCQ 1'b1;
req_tc <= #TCQ 3'b0;
req_td <= #TCQ 1'b0;
req_ep <= #TCQ 1'b0;
req_attr <= #TCQ 2'b0;
req_len <= #TCQ 10'b0;
req_rid <= #TCQ 16'b0;
req_tag <= #TCQ 8'b0;
req_be <= #TCQ 8'b0;
req_addr <= #TCQ 13'b0;
wr_be <= #TCQ 8'b0;
wr_addr <= #TCQ 11'b0;
wr_data <= #TCQ 32'b0;
wr_en <= #TCQ 1'b0;
state <= #TCQ PIO_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end // if (!rst_n )
else
begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
case (state)
PIO_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
req_compl_wd <= #TCQ 1'b1;
// Packet starts in the middle of the 128-bit bus.
if ((m_axis_rx_tvalid) && (m_axis_rx_tready))
begin
if (sof_mid)
begin
tlp_type <= #TCQ m_axis_rx_tdata[95:88];
req_len <= #TCQ m_axis_rx_tdata[73:64];
m_axis_rx_tready <= #TCQ 1'b0;
// Evaluate packet type
case (m_axis_rx_tdata[94:88])
PIO_RX_MEM_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
req_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[73:64] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[86:84];
req_td <= #TCQ m_axis_rx_tdata[79];
req_ep <= #TCQ m_axis_rx_tdata[78];
req_attr <= #TCQ m_axis_rx_tdata[77:76];
req_len <= #TCQ m_axis_rx_tdata[73:64];
req_rid <= #TCQ m_axis_rx_tdata[127:112];
req_tag <= #TCQ m_axis_rx_tdata[111:104];
wr_be <= #TCQ m_axis_rx_tdata[103:96];
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if (m_axis_rx_tdata[73:64] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[73:64] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
default : begin // other TLPs
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase // case (m_axis_rx_tdata[94:88])
// Packet starts on the right of the data bus. Remember, packets start
// on the right and are filled to the left. The data-bus is filled 32-bits
// (one Dword) at time.
end
else if (sof_right)
begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
case (m_axis_rx_tdata[30:24])
PIO_RX_MEM_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_addr <= #TCQ {region_select[1:0],
m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD32_FMT_TYPE
PIO_RX_MEM_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
wr_data <= #TCQ m_axis_rx_tdata[127:96];
wr_en <= #TCQ 1'b1;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR32_FMT_TYPE
PIO_RX_MEM_RD64_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
// Upper 32-bits of 64-bit address not used, but would be captured
// in this state if used. Upper 32 address bits are on
//m_axis_rx_tdata[127:96]
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_RD64_FMT_TYPE
PIO_RX_MEM_WR64_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
// lower qw
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_WAIT_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_MEM_WR64_FMT_TYPE
PIO_RX_IO_RD32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
req_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66],2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_RD32_FMT_TYPE
PIO_RX_IO_WR32_FMT_TYPE : begin
if (m_axis_rx_tdata[9:0] == 10'b1)
begin
wr_be <= #TCQ m_axis_rx_tdata[39:32];
//lower qw
req_tc <= #TCQ m_axis_rx_tdata[22:20];
req_td <= #TCQ m_axis_rx_tdata[15];
req_ep <= #TCQ m_axis_rx_tdata[14];
req_attr <= #TCQ m_axis_rx_tdata[13:12];
req_len <= #TCQ m_axis_rx_tdata[9:0];
req_rid <= #TCQ m_axis_rx_tdata[63:48];
req_tag <= #TCQ m_axis_rx_tdata[47:40];
wr_data <= #TCQ m_axis_rx_tdata[127:96];
wr_en <= #TCQ 1'b1;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[74:66]};
wr_en <= #TCQ 1'b1;
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tdata[9:0] == 10'b1)
else
begin
state <= #TCQ PIO_RX_RST_STATE;
end // if !(m_axis_rx_tdata[9:0] == 10'b1)
end // PIO_RX_IO_WR32_FMT_TYPE
endcase // case (m_axis_rx_tdata[30:24])
end // if (sof_right)
end
else // not a start of packet
state <= #TCQ PIO_RX_RST_STATE;
end //PIO_RX_RST_STATE
PIO_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[31:0];
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR64_DW3;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_WR64_DW3
PIO_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_RD32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_RD32_DW1DW2
PIO_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_WR32_DW1DW2
PIO_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
wr_data <= #TCQ m_axis_rx_tdata[63:32];
wr_en <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR32_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_IO_WR_DW1DW2
PIO_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
req_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2], 2'b00};
req_compl <= #TCQ 1'b1;
req_compl_wd <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_RD64_DW1DW2;
end // if !(m_axis_rx_tvalid)
end // PIO_RX_MEM_RD64_DW1DW2
PIO_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid)
begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr <= #TCQ {region_select[1:0], m_axis_rx_tdata[10:2]};
// lower QW
wr_data <= #TCQ m_axis_rx_tdata[95:64];
wr_en <= #TCQ 1'b1;
state <= #TCQ PIO_RX_WAIT_STATE;
end // if (m_axis_rx_tvalid)
else
begin
state <= #TCQ PIO_RX_MEM_WR64_DW1DW2;
end // if (m_axis_rx_tvalid)
end // PIO_RX_MEM_WR64_DW1DW2
PIO_RX_WAIT_STATE : begin
wr_en <= #TCQ 1'b0;
req_compl <= #TCQ 1'b0;
if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) &&(!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR32_FMT_TYPE) &&(!wr_busy))
else if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_WR32_FMT_TYPE) && (!compl_done))
else if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_WR64_FMT_TYPE) && (!wr_busy))
else if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_IO_RD32_FMT_TYPE) && (compl_done))
else if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_RX_RST_STATE;
end // if ((tlp_type == PIO_RX_MEM_RD64_FMT_TYPE) && (compl_done))
else
begin
state <= #TCQ PIO_RX_WAIT_STATE;
end
end // PIO_RX_WAIT_STATE
default : begin
// default case stmt
state <= #TCQ PIO_RX_RST_STATE;
end // default
endcase
end // if rst_n
end // always
end // pio_rx_sm_128
endgenerate
assign mem64_bar_hit_n = 1'b1;
assign io_bar_hit_n = 1'b1;
assign mem32_bar_hit_n = ~(m_axis_rx_tuser[2]);
assign erom_bar_hit_n = ~(m_axis_rx_tuser[8]);
always @*
begin
case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
4'b0111 : begin
region_select <= #TCQ 2'b00; // Select IO region
end // 4'b0111
4'b1011 : begin
region_select <= #TCQ 2'b01; // Select Mem32 region
end // 4'b1011
4'b1101 : begin
region_select <= #TCQ 2'b10; // Select Mem64 region
end // 4'b1101
4'b1110 : begin
region_select <= #TCQ 2'b11; // Select EROM region
end // 4'b1110
default : begin
region_select <= #TCQ 2'b00; // Error selection will select IO region
end // default
endcase // case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(state)
begin
case (state)
PIO_RX_RST_STATE : state_ascii <= #TCQ "RX_RST_STATE";
PIO_RX_MEM_RD32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD32_DW1DW2";
PIO_RX_MEM_WR32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR32_DW1DW2";
PIO_RX_MEM_RD64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD64_DW1DW2";
PIO_RX_MEM_WR64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR64_DW1DW2";
PIO_RX_MEM_WR64_DW3 : state_ascii <= #TCQ "RX_MEM_WR64_DW3";
PIO_RX_WAIT_STATE : state_ascii <= #TCQ "RX_WAIT_STATE";
PIO_RX_IO_WR_DW1DW2 : state_ascii <= #TCQ "RX_IO_WR_DW1DW2";
PIO_RX_IO_MEM_WR_WAIT_STATE : state_ascii <= #TCQ "RX_IO_MEM_WR_WAIT_STATE";
default : state_ascii <= #TCQ "PIO 128 STATE ERR";
endcase
end
// synthesis translate_on
endmodule // PIO_RX_ENGINE
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005-2007 by Wilson Snyder.
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 read requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_req1,
prt_req2,
prt_req3,
prt_req4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input prt_req1, prt_req2,prt_req3, prt_req4, prt_dv;
output reg [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
output reg prt_dv1,prt_dv2,prt_dv3,prt_dv4,prt_req;
input [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 3'b100, wait_dv_low=3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_addr = prt_addr4;
prt_qos = qos4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_req4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
prt_req = 1;
prt_addr = prt_addr1;
prt_qos = qos1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv4 = 1'b0;
if(prt_dv)begin
prt_dv3 = 1'b1;
prt_data3 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_req1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
if(prt_dv)begin
prt_dv4 = 1'b1;
prt_data4 = prt_data;
//state = wait_req;
state = wait_dv_low;
prt_req = 1'b0;
if(prt_req1) begin
state = serv_req1;
prt_qos = qos1;
prt_req = 1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req3) begin
prt_req = 1;
prt_addr = prt_addr3;
prt_qos = qos3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_dv_low:begin
state = wait_dv_low;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_dv3 = 1'b0;
prt_dv4 = 1'b0;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(* ####################################################### *)
(** ** Notation for Assertions *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1, assn_sub_ex2]
and use [hoare_asgn] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality m a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* This rule was proposed by Nick Giannarakis and Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1', assn_sub_ex2'] and
use [hoare_asgn] and [hoare_consequence_pre] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
- (* right part of seq *)
apply hoare_skip.
- (* left part of seq *)
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(* FILL IN HERE *) admit.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
- (* b is true *)
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
- (* b is false *)
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Hoare Logic: So Far *)
(**
Idea: create a _domain specific logic_ for reasoning about properties of Imp programs.
- This hides the low-level details of the semantics of the program
- Leads to a compositional reasoning process
The basic structure is given by _Hoare triples_ of the form:
{{P}} c {{Q}}
]]
- [P] and [Q] are predicates about the state of the Imp program
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
*)
(** ** Hoare Logic Rules (so far) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
- (* Then *)
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
- (* Else *)
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* FILL IN HERE *) Admitted.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally [hoare_if1_good] that your rule is
precise enough to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* FILL IN HERE *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** *** *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
induction He;
try (inversion Heqwcom); subst; clear Heqwcom.
- (* E_WhileEnd *)
split. assumption. apply bexp_eval_false. assumption.
- (* E_WhileLoop *)
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
- (* Loop body preserves invariant *)
apply hoare_post_true. intros st. apply I.
- (* Loop invariant and negated guard imply postcondition *)
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
- (* Precondition implies invariant *)
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* FILL IN HERE *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Complete List of Hoare Logic Rules *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(** $Date$ *)
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2010/04/12 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_multi_mac_pcs
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
input wire ref_clk, // Reference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_0, // 125MHz Recoved Clock
input wire tbi_tx_clk_0, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_0, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_0, // Transmit TBI Interface
output wire sd_loopback_0, // SERDES Loopback Enable
output wire powerdown_0, // Powerdown Enable
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_1, // 125MHz Recoved Clock
input wire tbi_tx_clk_1, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_1, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_1, // Transmit TBI Interface
output wire sd_loopback_1, // SERDES Loopback Enable
output wire powerdown_1, // Powerdown Enable
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_2, // 125MHz Recoved Clock
input wire tbi_tx_clk_2, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_2, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_2, // Transmit TBI Interface
output wire sd_loopback_2, // SERDES Loopback Enable
output wire powerdown_2, // Powerdown Enable
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_3, // 125MHz Recoved Clock
input wire tbi_tx_clk_3, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_3, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_3, // Transmit TBI Interface
output wire sd_loopback_3, // SERDES Loopback Enable
output wire powerdown_3, // Powerdown Enable
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_4, // 125MHz Recoved Clock
input wire tbi_tx_clk_4, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_4, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_4, // Transmit TBI Interface
output wire sd_loopback_4, // SERDES Loopback Enable
output wire powerdown_4, // Powerdown Enable
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_5, // 125MHz Recoved Clock
input wire tbi_tx_clk_5, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_5, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_5, // Transmit TBI Interface
output wire sd_loopback_5, // SERDES Loopback Enable
output wire powerdown_5, // Powerdown Enable
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_6, // 125MHz Recoved Clock
input wire tbi_tx_clk_6, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_6, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_6, // Transmit TBI Interface
output wire sd_loopback_6, // SERDES Loopback Enable
output wire powerdown_6, // Powerdown Enable
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_7, // 125MHz Recoved Clock
input wire tbi_tx_clk_7, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_7, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_7, // Transmit TBI Interface
output wire sd_loopback_7, // SERDES Loopback Enable
output wire powerdown_7, // Powerdown Enable
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_8, // 125MHz Recoved Clock
input wire tbi_tx_clk_8, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_8, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_8, // Transmit TBI Interface
output wire sd_loopback_8, // SERDES Loopback Enable
output wire powerdown_8, // Powerdown Enable
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_9, // 125MHz Recoved Clock
input wire tbi_tx_clk_9, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_9, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_9, // Transmit TBI Interface
output wire sd_loopback_9, // SERDES Loopback Enable
output wire powerdown_9, // Powerdown Enable
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_10, // 125MHz Recoved Clock
input wire tbi_tx_clk_10, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_10, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_10, // Transmit TBI Interface
output wire sd_loopback_10, // SERDES Loopback Enable
output wire powerdown_10, // Powerdown Enable
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_11, // 125MHz Recoved Clock
input wire tbi_tx_clk_11, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_11, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_11, // Transmit TBI Interface
output wire sd_loopback_11, // SERDES Loopback Enable
output wire powerdown_11, // Powerdown Enable
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_12, // 125MHz Recoved Clock
input wire tbi_tx_clk_12, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_12, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_12, // Transmit TBI Interface
output wire sd_loopback_12, // SERDES Loopback Enable
output wire powerdown_12, // Powerdown Enable
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_13, // 125MHz Recoved Clock
input wire tbi_tx_clk_13, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_13, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_13, // Transmit TBI Interface
output wire sd_loopback_13, // SERDES Loopback Enable
output wire powerdown_13, // Powerdown Enable
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_14, // 125MHz Recoved Clock
input wire tbi_tx_clk_14, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_14, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_14, // Transmit TBI Interface
output wire sd_loopback_14, // SERDES Loopback Enable
output wire powerdown_14, // Powerdown Enable
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_15, // 125MHz Recoved Clock
input wire tbi_tx_clk_15, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_15, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_15, // Transmit TBI Interface
output wire sd_loopback_15, // SERDES Loopback Enable
output wire powerdown_15, // Powerdown Enable
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_16, // 125MHz Recoved Clock
input wire tbi_tx_clk_16, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_16, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_16, // Transmit TBI Interface
output wire sd_loopback_16, // SERDES Loopback Enable
output wire powerdown_16, // Powerdown Enable
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_17, // 125MHz Recoved Clock
input wire tbi_tx_clk_17, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_17, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_17, // Transmit TBI Interface
output wire sd_loopback_17, // SERDES Loopback Enable
output wire powerdown_17, // Powerdown Enable
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_18, // 125MHz Recoved Clock
input wire tbi_tx_clk_18, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_18, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_18, // Transmit TBI Interface
output wire sd_loopback_18, // SERDES Loopback Enable
output wire powerdown_18, // Powerdown Enable
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_19, // 125MHz Recoved Clock
input wire tbi_tx_clk_19, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_19, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_19, // Transmit TBI Interface
output wire sd_loopback_19, // SERDES Loopback Enable
output wire powerdown_19, // Powerdown Enable
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_20, // 125MHz Recoved Clock
input wire tbi_tx_clk_20, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_20, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_20, // Transmit TBI Interface
output wire sd_loopback_20, // SERDES Loopback Enable
output wire powerdown_20, // Powerdown Enable
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_21, // 125MHz Recoved Clock
input wire tbi_tx_clk_21, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_21, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_21, // Transmit TBI Interface
output wire sd_loopback_21, // SERDES Loopback Enable
output wire powerdown_21, // Powerdown Enable
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_22, // 125MHz Recoved Clock
input wire tbi_tx_clk_22, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_22, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_22, // Transmit TBI Interface
output wire sd_loopback_22, // SERDES Loopback Enable
output wire powerdown_22, // Powerdown Enable
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire tbi_rx_clk_23, // 125MHz Recoved Clock
input wire tbi_tx_clk_23, // 125MHz Transmit Clock
input wire [9:0] tbi_rx_d_23, // Non Aligned 10-Bit Characters
output wire [9:0] tbi_tx_d_23, // Transmit TBI Interface
output wire sd_loopback_23, // SERDES Loopback Enable
output wire powerdown_23, // Powerdown Enable
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23); // Wake Up Request
// Component instantiation
altera_tse_top_multi_mac_pcs U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.tbi_rx_clk_0(tbi_rx_clk_0), //INPUT : Receive TBI Clock
.tbi_tx_clk_0(tbi_tx_clk_0), //INPUT : Transmit TBI Clock
.tbi_rx_d_0(tbi_rx_d_0), //INPUT : Receive TBI Interface
.tbi_tx_d_0(tbi_tx_d_0), //OUTPUT : Transmit TBI Interface
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(powerdown_0), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_0), //OUTPUT : Character error
.led_disp_err_0(led_disp_err_0), //OUTPUT : Disparity error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(led_link_0), //OUTPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.tbi_rx_clk_1(tbi_rx_clk_1), //INPUT : Receive TBI Clock
.tbi_tx_clk_1(tbi_tx_clk_1), //INPUT : Transmit TBI Clock
.tbi_rx_d_1(tbi_rx_d_1), //INPUT : Receive TBI Interface
.tbi_tx_d_1(tbi_tx_d_1), //OUTPUT : Transmit TBI Interface
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(powerdown_1), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_1), //OUTPUT : Character error
.led_disp_err_1(led_disp_err_1), //OUTPUT : Disparity error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(led_link_1), //OUTPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.tbi_rx_clk_2(tbi_rx_clk_2), //INPUT : Receive TBI Clock
.tbi_tx_clk_2(tbi_tx_clk_2), //INPUT : Transmit TBI Clock
.tbi_rx_d_2(tbi_rx_d_2), //INPUT : Receive TBI Interface
.tbi_tx_d_2(tbi_tx_d_2), //OUTPUT : Transmit TBI Interface
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(powerdown_2), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_2), //OUTPUT : Character error
.led_disp_err_2(led_disp_err_2), //OUTPUT : Disparity error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(led_link_2), //OUTPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.tbi_rx_clk_3(tbi_rx_clk_3), //INPUT : Receive TBI Clock
.tbi_tx_clk_3(tbi_tx_clk_3), //INPUT : Transmit TBI Clock
.tbi_rx_d_3(tbi_rx_d_3), //INPUT : Receive TBI Interface
.tbi_tx_d_3(tbi_tx_d_3), //OUTPUT : Transmit TBI Interface
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(powerdown_3), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_3), //OUTPUT : Character error
.led_disp_err_3(led_disp_err_3), //OUTPUT : Disparity error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(led_link_3), //OUTPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.tbi_rx_clk_4(tbi_rx_clk_4), //INPUT : Receive TBI Clock
.tbi_tx_clk_4(tbi_tx_clk_4), //INPUT : Transmit TBI Clock
.tbi_rx_d_4(tbi_rx_d_4), //INPUT : Receive TBI Interface
.tbi_tx_d_4(tbi_tx_d_4), //OUTPUT : Transmit TBI Interface
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(powerdown_4), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_4), //OUTPUT : Character error
.led_disp_err_4(led_disp_err_4), //OUTPUT : Disparity error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(led_link_4), //OUTPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.tbi_rx_clk_5(tbi_rx_clk_5), //INPUT : Receive TBI Clock
.tbi_tx_clk_5(tbi_tx_clk_5), //INPUT : Transmit TBI Clock
.tbi_rx_d_5(tbi_rx_d_5), //INPUT : Receive TBI Interface
.tbi_tx_d_5(tbi_tx_d_5), //OUTPUT : Transmit TBI Interface
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(powerdown_5), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_5), //OUTPUT : Character error
.led_disp_err_5(led_disp_err_5), //OUTPUT : Disparity error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(led_link_5), //OUTPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.tbi_rx_clk_6(tbi_rx_clk_6), //INPUT : Receive TBI Clock
.tbi_tx_clk_6(tbi_tx_clk_6), //INPUT : Transmit TBI Clock
.tbi_rx_d_6(tbi_rx_d_6), //INPUT : Receive TBI Interface
.tbi_tx_d_6(tbi_tx_d_6), //OUTPUT : Transmit TBI Interface
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(powerdown_6), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_6), //OUTPUT : Character error
.led_disp_err_6(led_disp_err_6), //OUTPUT : Disparity error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(led_link_6), //OUTPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.tbi_rx_clk_7(tbi_rx_clk_7), //INPUT : Receive TBI Clock
.tbi_tx_clk_7(tbi_tx_clk_7), //INPUT : Transmit TBI Clock
.tbi_rx_d_7(tbi_rx_d_7), //INPUT : Receive TBI Interface
.tbi_tx_d_7(tbi_tx_d_7), //OUTPUT : Transmit TBI Interface
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(powerdown_7), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_7), //OUTPUT : Character error
.led_disp_err_7(led_disp_err_7), //OUTPUT : Disparity error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(led_link_7), //OUTPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.tbi_rx_clk_8(tbi_rx_clk_8), //INPUT : Receive TBI Clock
.tbi_tx_clk_8(tbi_tx_clk_8), //INPUT : Transmit TBI Clock
.tbi_rx_d_8(tbi_rx_d_8), //INPUT : Receive TBI Interface
.tbi_tx_d_8(tbi_tx_d_8), //OUTPUT : Transmit TBI Interface
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(powerdown_8), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_8), //OUTPUT : Character error
.led_disp_err_8(led_disp_err_8), //OUTPUT : Disparity error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(led_link_8), //OUTPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.tbi_rx_clk_9(tbi_rx_clk_9), //INPUT : Receive TBI Clock
.tbi_tx_clk_9(tbi_tx_clk_9), //INPUT : Transmit TBI Clock
.tbi_rx_d_9(tbi_rx_d_9), //INPUT : Receive TBI Interface
.tbi_tx_d_9(tbi_tx_d_9), //OUTPUT : Transmit TBI Interface
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(powerdown_9), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_9), //OUTPUT : Character error
.led_disp_err_9(led_disp_err_9), //OUTPUT : Disparity error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(led_link_9), //OUTPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.tbi_rx_clk_10(tbi_rx_clk_10), //INPUT : Receive TBI Clock
.tbi_tx_clk_10(tbi_tx_clk_10), //INPUT : Transmit TBI Clock
.tbi_rx_d_10(tbi_rx_d_10), //INPUT : Receive TBI Interface
.tbi_tx_d_10(tbi_tx_d_10), //OUTPUT : Transmit TBI Interface
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(powerdown_10), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_10), //OUTPUT : Character error
.led_disp_err_10(led_disp_err_10), //OUTPUT : Disparity error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(led_link_10), //OUTPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.tbi_rx_clk_11(tbi_rx_clk_11), //INPUT : Receive TBI Clock
.tbi_tx_clk_11(tbi_tx_clk_11), //INPUT : Transmit TBI Clock
.tbi_rx_d_11(tbi_rx_d_11), //INPUT : Receive TBI Interface
.tbi_tx_d_11(tbi_tx_d_11), //OUTPUT : Transmit TBI Interface
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(powerdown_11), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_11), //OUTPUT : Character error
.led_disp_err_11(led_disp_err_11), //OUTPUT : Disparity error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(led_link_11), //OUTPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.tbi_rx_clk_12(tbi_rx_clk_12), //INPUT : Receive TBI Clock
.tbi_tx_clk_12(tbi_tx_clk_12), //INPUT : Transmit TBI Clock
.tbi_rx_d_12(tbi_rx_d_12), //INPUT : Receive TBI Interface
.tbi_tx_d_12(tbi_tx_d_12), //OUTPUT : Transmit TBI Interface
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(powerdown_12), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_12), //OUTPUT : Character error
.led_disp_err_12(led_disp_err_12), //OUTPUT : Disparity error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(led_link_12), //OUTPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.tbi_rx_clk_13(tbi_rx_clk_13), //INPUT : Receive TBI Clock
.tbi_tx_clk_13(tbi_tx_clk_13), //INPUT : Transmit TBI Clock
.tbi_rx_d_13(tbi_rx_d_13), //INPUT : Receive TBI Interface
.tbi_tx_d_13(tbi_tx_d_13), //OUTPUT : Transmit TBI Interface
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(powerdown_13), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_13), //OUTPUT : Character error
.led_disp_err_13(led_disp_err_13), //OUTPUT : Disparity error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(led_link_13), //OUTPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.tbi_rx_clk_14(tbi_rx_clk_14), //INPUT : Receive TBI Clock
.tbi_tx_clk_14(tbi_tx_clk_14), //INPUT : Transmit TBI Clock
.tbi_rx_d_14(tbi_rx_d_14), //INPUT : Receive TBI Interface
.tbi_tx_d_14(tbi_tx_d_14), //OUTPUT : Transmit TBI Interface
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(powerdown_14), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_14), //OUTPUT : Character error
.led_disp_err_14(led_disp_err_14), //OUTPUT : Disparity error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(led_link_14), //OUTPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.tbi_rx_clk_15(tbi_rx_clk_15), //INPUT : Receive TBI Clock
.tbi_tx_clk_15(tbi_tx_clk_15), //INPUT : Transmit TBI Clock
.tbi_rx_d_15(tbi_rx_d_15), //INPUT : Receive TBI Interface
.tbi_tx_d_15(tbi_tx_d_15), //OUTPUT : Transmit TBI Interface
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(powerdown_15), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_15), //OUTPUT : Character error
.led_disp_err_15(led_disp_err_15), //OUTPUT : Disparity error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(led_link_15), //OUTPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.tbi_rx_clk_16(tbi_rx_clk_16), //INPUT : Receive TBI Clock
.tbi_tx_clk_16(tbi_tx_clk_16), //INPUT : Transmit TBI Clock
.tbi_rx_d_16(tbi_rx_d_16), //INPUT : Receive TBI Interface
.tbi_tx_d_16(tbi_tx_d_16), //OUTPUT : Transmit TBI Interface
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(powerdown_16), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_16), //OUTPUT : Character error
.led_disp_err_16(led_disp_err_16), //OUTPUT : Disparity error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(led_link_16), //OUTPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.tbi_rx_clk_17(tbi_rx_clk_17), //INPUT : Receive TBI Clock
.tbi_tx_clk_17(tbi_tx_clk_17), //INPUT : Transmit TBI Clock
.tbi_rx_d_17(tbi_rx_d_17), //INPUT : Receive TBI Interface
.tbi_tx_d_17(tbi_tx_d_17), //OUTPUT : Transmit TBI Interface
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(powerdown_17), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_17), //OUTPUT : Character error
.led_disp_err_17(led_disp_err_17), //OUTPUT : Disparity error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(led_link_17), //OUTPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.tbi_rx_clk_18(tbi_rx_clk_18), //INPUT : Receive TBI Clock
.tbi_tx_clk_18(tbi_tx_clk_18), //INPUT : Transmit TBI Clock
.tbi_rx_d_18(tbi_rx_d_18), //INPUT : Receive TBI Interface
.tbi_tx_d_18(tbi_tx_d_18), //OUTPUT : Transmit TBI Interface
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(powerdown_18), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_18), //OUTPUT : Character error
.led_disp_err_18(led_disp_err_18), //OUTPUT : Disparity error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(led_link_18), //OUTPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.tbi_rx_clk_19(tbi_rx_clk_19), //INPUT : Receive TBI Clock
.tbi_tx_clk_19(tbi_tx_clk_19), //INPUT : Transmit TBI Clock
.tbi_rx_d_19(tbi_rx_d_19), //INPUT : Receive TBI Interface
.tbi_tx_d_19(tbi_tx_d_19), //OUTPUT : Transmit TBI Interface
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(powerdown_19), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_19), //OUTPUT : Character error
.led_disp_err_19(led_disp_err_19), //OUTPUT : Disparity error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(led_link_19), //OUTPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.tbi_rx_clk_20(tbi_rx_clk_20), //INPUT : Receive TBI Clock
.tbi_tx_clk_20(tbi_tx_clk_20), //INPUT : Transmit TBI Clock
.tbi_rx_d_20(tbi_rx_d_20), //INPUT : Receive TBI Interface
.tbi_tx_d_20(tbi_tx_d_20), //OUTPUT : Transmit TBI Interface
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(powerdown_20), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_20), //OUTPUT : Character error
.led_disp_err_20(led_disp_err_20), //OUTPUT : Disparity error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(led_link_20), //OUTPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.tbi_rx_clk_21(tbi_rx_clk_21), //INPUT : Receive TBI Clock
.tbi_tx_clk_21(tbi_tx_clk_21), //INPUT : Transmit TBI Clock
.tbi_rx_d_21(tbi_rx_d_21), //INPUT : Receive TBI Interface
.tbi_tx_d_21(tbi_tx_d_21), //OUTPUT : Transmit TBI Interface
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(powerdown_21), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_21), //OUTPUT : Character error
.led_disp_err_21(led_disp_err_21), //OUTPUT : Disparity error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(led_link_21), //OUTPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.tbi_rx_clk_22(tbi_rx_clk_22), //INPUT : Receive TBI Clock
.tbi_tx_clk_22(tbi_tx_clk_22), //INPUT : Transmit TBI Clock
.tbi_rx_d_22(tbi_rx_d_22), //INPUT : Receive TBI Interface
.tbi_tx_d_22(tbi_tx_d_22), //OUTPUT : Transmit TBI Interface
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(powerdown_22), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_22), //OUTPUT : Character error
.led_disp_err_22(led_disp_err_22), //OUTPUT : Disparity error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(led_link_22), //OUTPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.tbi_rx_clk_23(tbi_rx_clk_23), //INPUT : Receive TBI Clock
.tbi_tx_clk_23(tbi_tx_clk_23), //INPUT : Transmit TBI Clock
.tbi_rx_d_23(tbi_rx_d_23), //INPUT : Receive TBI Interface
.tbi_tx_d_23(tbi_tx_d_23), //OUTPUT : Transmit TBI Interface
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(powerdown_23), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_23), //OUTPUT : Character error
.led_disp_err_23(led_disp_err_23), //OUTPUT : Disparity error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(led_link_23), //OUTPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
endmodule // module altera_tse_multi_mac_pcs
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "../framework_defines.vh"
module user_tx_rd_if #(parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
input wire reset_interface,
input wire set_if_mem_pipelined,
input wire set_if_direct_pipelined,
input wire [57:0] mem_pipeline_addr,
input wire [3:0] mem_pipeline_addr_code,
input wire [3:0] direct_pipeline_addr_code,
input wire reads_finished,
//--------------------- User RD Request -----------------------------//
// User Module TX RD
input wire [57:0] um_tx_rd_addr,
input wire [USER_TAG-1:0] um_tx_rd_tag,
input wire um_tx_rd_valid,
output wire um_tx_rd_ready,
// User Module RX RD
output wire [USER_TAG-1:0] um_rx_rd_tag,
output wire [511:0] um_rx_data,
output wire um_rx_rd_valid,
input wire um_rx_rd_ready,
//-------------------- to Fthread Controller ------------------------//
output wire usr_arb_tx_rd_valid,
output wire [57:0] usr_arb_tx_rd_addr,
output wire [`IF_TAG-1:0] usr_arb_tx_rd_tag,
input wire usr_arb_tx_rd_ready,
input wire usr_arb_rx_rd_valid,
input wire [`IF_TAG-1:0] usr_arb_rx_rd_tag,
input wire [511:0] usr_arb_rx_data,
output wire [57:0] rif_tx_wr_addr,
output wire [`IF_TAG-1:0] rif_tx_wr_tag,
output wire rif_tx_wr_valid,
output wire [511:0] rif_tx_data,
input wire rif_tx_wr_ready,
input wire [`IF_TAG-1:0] rif_rx_wr_tag,
input wire rif_rx_wr_valid,
//-------------------- To pipeline writer ---------------------------//
output wire usr_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] usr_pipe_tx_rd_tag,
input wire usr_pipe_tx_rd_ready,
input wire usr_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] usr_pipe_rx_rd_tag,
input wire [511:0] usr_pipe_rx_data,
output wire usr_pipe_rx_rd_ready
);
wire [57+USER_TAG:0] tx_rd_fifo_dout;
wire tx_rd_fifo_valid;
wire tx_rd_fifo_full;
wire tx_rd_fifo_re;
wire ord_tx_rd_ready;
// RX RD
reg [`IF_TAG-1:0] rx_rd_tag_reg;
reg [511:0] rx_data_reg;
reg rx_rd_valid_reg;
wire tx_rd_ready;
wire tx_rd_valid;
wire [57:0] tx_rd_addr;
wire [`IF_TAG-1:0] tx_rd_tag;
wire usr_tx_rd_ready;
wire usr_tx_rd_valid;
wire [57:0] usr_tx_rd_addr;
wire [USER_TAG+1:0] usr_tx_rd_tag;
wire [USER_TAG+1:0] usr_rx_rd_tag;
wire usr_rx_rd_valid;
wire [511:0] usr_rx_data;
reg [57:0] fifo_base_addr;
reg [3:0] fifo_addr_code;
reg [3:0] direct_pipeline_code;
reg direct_pipeline_code_valid;
reg in_memory_pipeline;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Pipelining Control Flags ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (~rst_n | reset_interface | reads_finished) begin
in_memory_pipeline <= 0;
fifo_base_addr <= 0;
fifo_addr_code <= 0;
direct_pipeline_code <= 0;
direct_pipeline_code_valid <= 1'b0;
end
else begin
if(set_if_mem_pipelined) begin
in_memory_pipeline <= 1'b1;
fifo_base_addr <= mem_pipeline_addr;
fifo_addr_code <= mem_pipeline_addr_code;
end
if(set_if_direct_pipelined) begin
direct_pipeline_code <= direct_pipeline_addr_code;
direct_pipeline_code_valid <= 1'b1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Reader Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(58 + USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n & ~reset_interface),
.din ({um_tx_rd_tag, um_tx_rd_addr}),
.we (um_tx_rd_valid),
.re (tx_rd_fifo_re),
.dout (tx_rd_fifo_dout),
.empty (),
.valid (tx_rd_fifo_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
assign um_tx_rd_ready = ~tx_rd_fifo_full;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Through SW FIFO Reader /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Arbiter TX RD
//(direct_pipeline_code_valid)?(tx_rd_addr[57:54] != direct_pipeline_code) & tx_rd_valid : tx_rd_valid;
// Pass through in-memory FIFO
sw_fifo_reader #(.USER_TAG(USER_TAG) )
sw_fifo_reader(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
.fifo_base_addr (fifo_base_addr),
.fifo_addr_code (fifo_addr_code),
.setup_fifo (in_memory_pipeline),
.reads_finished (reads_finished),
//--------------------- FIFO to QPI ----------------//
// TX RD
.fifo_tx_wr_addr (rif_tx_wr_addr),
.fifo_tx_wr_tag (rif_tx_wr_tag),
.fifo_tx_wr_valid (rif_tx_wr_valid),
.fifo_tx_data (rif_tx_data),
.fifo_tx_wr_ready (rif_tx_wr_ready),
// TX RD
.fifo_tx_rd_addr (usr_tx_rd_addr),
.fifo_tx_rd_tag (usr_tx_rd_tag),
.fifo_tx_rd_valid (usr_tx_rd_valid),
.fifo_tx_rd_ready (usr_tx_rd_ready),
// RX RD
.fifo_rx_wr_tag (rif_rx_wr_tag),
.fifo_rx_wr_valid (rif_rx_wr_valid),
// RX WR
.fifo_rx_rd_valid (usr_rx_rd_valid),
.fifo_rx_rd_tag (usr_rx_rd_tag),
.fifo_rx_data (usr_rx_data),
.fifo_rx_rd_ready (usr_rx_rd_ready),
///////////////////////// User Logic Interface ////////////////////
.usr_tx_rd_tag (tx_rd_fifo_dout[57+USER_TAG:58]),
.usr_tx_rd_valid (tx_rd_fifo_valid),
.usr_tx_rd_addr (tx_rd_fifo_dout[57:0]),
.usr_tx_rd_ready (tx_rd_fifo_re),
.usr_rx_rd_tag (um_rx_rd_tag),
.usr_rx_rd_valid (um_rx_rd_valid),
.usr_rx_data (um_rx_data),
.usr_rx_rd_ready (um_rx_rd_ready)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Requests Ordering Module ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
order_module_backpressure #(
.TAG_WIDTH(7),
.OUT_TAG_WIDTH(`IF_TAG),
.USER_TAG_WIDTH(USER_TAG+2))
omodule(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
// input requests
.usr_tx_rd_addr (usr_tx_rd_addr),
.usr_tx_rd_tag (usr_tx_rd_tag),
.usr_tx_rd_valid (usr_tx_rd_valid),
.usr_tx_rd_free (usr_tx_rd_ready),
// TX RD
.ord_tx_rd_addr (tx_rd_addr),
.ord_tx_rd_tag (tx_rd_tag),
.ord_tx_rd_valid (tx_rd_valid),
.ord_tx_rd_free (tx_rd_ready),
// RX RD
.ord_rx_rd_tag (rx_rd_tag_reg[6:0]),
.ord_rx_rd_data (rx_data_reg),
.ord_rx_rd_valid (rx_rd_valid_reg),
//
.usr_rx_rd_tag (usr_rx_rd_tag),
.usr_rx_rd_data (usr_rx_data),
.usr_rx_rd_valid (usr_rx_rd_valid),
.usr_rx_rd_ready (usr_rx_rd_ready)
);
//--------------------------------------------//
assign tx_rd_ready = ((tx_rd_addr[57:54] == direct_pipeline_code) & direct_pipeline_code_valid)? usr_pipe_tx_rd_ready : usr_arb_tx_rd_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Accesses To Main Memory /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Arbiter TX RD
assign usr_arb_tx_rd_addr = tx_rd_addr;
assign usr_arb_tx_rd_tag = tx_rd_tag;
assign usr_arb_tx_rd_valid = (direct_pipeline_code_valid)?(tx_rd_addr[57:54] != direct_pipeline_code) & tx_rd_valid : tx_rd_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Direct AFU-AFU Pipeline /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------//
// Pipe TX RD
assign usr_pipe_tx_rd_tag = tx_rd_tag;
assign usr_pipe_tx_rd_valid = (tx_rd_addr[57:54] == direct_pipeline_code) & direct_pipeline_code_valid & tx_rd_valid;
assign usr_pipe_rx_rd_ready = ~usr_arb_rx_rd_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Read Request Responses /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------//
// order module rd rx
// data
always @(posedge clk) begin
if(usr_arb_rx_rd_valid) begin
rx_data_reg <= usr_arb_rx_data;
end
else begin
rx_data_reg <= usr_pipe_rx_data;
end
end
// valid
always @(posedge clk) begin
if (~rst_n | reset_interface) begin
rx_rd_tag_reg <= 0;
rx_rd_valid_reg <= 0;
end
else begin
if(usr_arb_rx_rd_valid) begin
rx_rd_tag_reg <= usr_arb_rx_rd_tag;
rx_rd_valid_reg <= 1'b1;
end
else begin
rx_rd_tag_reg <= usr_pipe_rx_rd_tag;
rx_rd_valid_reg <= usr_pipe_rx_rd_valid;
end
end
end
endmodule
|
//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//-- **************************************
//-- ** Copyright (C) 2005, Xilinx, Inc. **
//-- ** All Rights Reserved. **
//-- **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: BMD_CFG_CTRL.v
//--
//-- Description: Configuration Controller.
//--
//--------------------------------------------------------------------------------
`define BMD_CFG_STATE_RESET 5'b00001
`define BMD_CFG_STATE_MSI 5'b00010
`define BMD_CFG_STATE_DCAP 5'b00100
`define BMD_CFG_STATE_LCAP 5'b01000
`define BMD_CFG_STATE_END 5'b10000
`define BMD_CFG_MSI_CAP0_ADDR 10'h012
`ifdef PCIEBLK
`define BMD_CFG_DEV_CAP_ADDR 10'h019
`define BMD_CFG_LNK_CAP_ADDR 10'h01B
`else // PCIEBLK
`define BMD_CFG_DEV_CAP_ADDR 10'h017
`define BMD_CFG_LNK_CAP_ADDR 10'h019
`endif // PCIEBLK
`timescale 1ns/1ns
module BMD_CFG_CTRL (
clk,
rst_n,
cfg_bus_mstr_enable,
cfg_dwaddr,
cfg_rd_en_n,
cfg_do,
cfg_rd_wr_done_n,
cfg_cap_max_lnk_width,
cfg_cap_max_lnk_speed,
cfg_cap_max_payload_size
// cfg_msi_enable
);
input clk;
input rst_n;
input cfg_bus_mstr_enable;
output [9:0] cfg_dwaddr;
output cfg_rd_en_n;
input [31:0] cfg_do;
input cfg_rd_wr_done_n;
output [5:0] cfg_cap_max_lnk_width;
output [3:0] cfg_cap_max_lnk_speed;
output [2:0] cfg_cap_max_payload_size;
//output cfg_msi_enable;
reg [4:0] cfg_intf_state;
reg cfg_bme_state;
reg [9:0] cfg_dwaddr;
reg cfg_rd_en_n;
reg [15:0] cfg_msi_control;
reg [5:0] cfg_cap_max_lnk_width;
reg [3:0] cfg_cap_max_lnk_speed;
reg [2:0] cfg_cap_max_payload_size;
always @(posedge clk ) begin
if ( !rst_n ) begin
cfg_dwaddr <= 0;
cfg_rd_en_n <= 1'b1;
cfg_msi_control <= 16'b0;
cfg_cap_max_lnk_width <= 6'b0;
cfg_cap_max_lnk_speed <= 4'b0;
cfg_cap_max_payload_size <= 3'b0;
cfg_intf_state <= `BMD_CFG_STATE_RESET;
cfg_bme_state <= cfg_bus_mstr_enable;
end else begin
case ( cfg_intf_state )
`BMD_CFG_STATE_RESET : begin
cfg_bme_state <= cfg_bus_mstr_enable;
if (cfg_rd_wr_done_n == 1'b1 && cfg_bus_mstr_enable) begin
cfg_dwaddr <= `BMD_CFG_MSI_CAP0_ADDR;
cfg_rd_en_n <= 1'b0;
cfg_intf_state <= `BMD_CFG_STATE_MSI;
end else begin
cfg_intf_state <= `BMD_CFG_STATE_RESET;
cfg_rd_en_n <= 1'b1;
end
end
`BMD_CFG_STATE_MSI : begin
if (cfg_rd_wr_done_n == 1'b0) begin
cfg_msi_control <= cfg_do[31:16];
cfg_dwaddr <= `BMD_CFG_DEV_CAP_ADDR;
cfg_rd_en_n <= 1'b0;
cfg_intf_state <= `BMD_CFG_STATE_DCAP;
end else begin
cfg_intf_state <= `BMD_CFG_STATE_MSI;
end
end
`BMD_CFG_STATE_DCAP : begin
if (cfg_rd_wr_done_n == 1'b0) begin
cfg_cap_max_payload_size <= cfg_do[2:0];
cfg_dwaddr <= `BMD_CFG_LNK_CAP_ADDR;
cfg_rd_en_n <= 1'b0;
cfg_intf_state <= `BMD_CFG_STATE_LCAP;
end else begin
cfg_intf_state <= `BMD_CFG_STATE_DCAP;
end
end
`BMD_CFG_STATE_LCAP : begin
if (cfg_rd_wr_done_n == 1'b0) begin
cfg_cap_max_lnk_width <= cfg_do[9:4];
cfg_cap_max_lnk_speed <= cfg_do[3:0];
cfg_intf_state <= `BMD_CFG_STATE_END;
end else begin
cfg_intf_state <= `BMD_CFG_STATE_LCAP;
end
end
`BMD_CFG_STATE_END : begin
cfg_dwaddr <= 0;
cfg_rd_en_n <= 1'b1;
if (cfg_bme_state != cfg_bus_mstr_enable)
cfg_intf_state <= `BMD_CFG_STATE_RESET;
else
cfg_intf_state <= `BMD_CFG_STATE_END;
end
endcase
end
end
//assign cfg_msi_enable = cfg_msi_control[0];
/*
assign cfg_dwaddr = 0;
assign cfg_rd_en_n = 1;
`ifdef _3GIO_1_LANE_PRODUCT
assign cfg_cap_max_lnk_width = 6'b000001;
assign cfg_cap_max_payload_size = 3'b010;
`endif // _3GIO_1_LANE_PRODUCT
`ifdef _3GIO_4_LANE_PRODUCT
assign cfg_cap_max_lnk_width = 6'b000100;
assign cfg_cap_max_payload_size = 3'b010;
`endif // _3GIO_4_LANE_PRODUCT
`ifdef _3GIO_4_LANE_PRODUCT
assign cfg_cap_max_lnk_width = 6'b001000;
assign cfg_cap_max_payload_size = 3'b001;
`endif // _3GIO_4_LANE_PRODUCT
*/
endmodule // BMD_CFG_CTRL
|
/*
* Text mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* Pipeline description
* h_count[3:0]
* 000
* 001 col_addr, row_addr
* 010 ver_addr, hor_addr
* 011 csr_adr_o
* 100 csr_adr_i
* 101 sram_addr_
* 110 csr_dat_o
* 111 char_data_out, attr_data_out
* 000 vga_shift
* 001 vga_blue_o <= vga_shift[7]
*/
module vga_text_mode_fml (
input clk,
input rst,
input enable,
// CSR slave interface for reading
output reg [16:1] fml_adr_o,
input [15:0] fml_dat_i,
output fml_stb_o,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
// CRTC
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
output reg [3:0] attr,
output horiz_sync_o
);
// Registers and nets
reg [ 6:0] col_addr;
reg [ 4:0] row_addr;
reg [ 6:0] hor_addr;
reg [ 6:0] ver_addr;
wire [10:0] vga_addr;
reg [ 15:0] fml1_dat;
wire [11:0] char_addr;
wire [ 7:0] char_data_out;
reg [ 7:0] attr_data_out;
reg [ 7:0] char_addr_in;
reg [15:0] pipe;
wire load_shift;
reg [7:0] video_on_h;
reg [7:0] horiz_sync;
wire fg_or_bg;
wire brown_bg;
wire brown_fg;
reg [ 7:0] vga_shift;
reg [ 3:0] fg_colour;
reg [ 2:0] bg_colour;
reg [22:0] blink_count;
// Cursor
reg cursor_on_v;
reg cursor_on_h;
reg cursor_on;
wire cursor_on1;
// Module instances
vga_char_rom char_rom (
.clk (clk),
.addr (char_addr),
.q (char_data_out)
);
// Continuous assignments
assign vga_addr = { 4'b0, hor_addr } + { ver_addr, 4'b0 };
assign char_addr = { char_addr_in, v_count[3:0] };
assign load_shift = pipe[7] | pipe[15];
assign video_on_h_o = video_on_h[7];
assign horiz_sync_o = horiz_sync[7];
assign fml_stb_o = pipe[2];
assign fg_or_bg = vga_shift[7] ^ cursor_on;
assign cursor_on1 = cursor_on_h && cursor_on_v;
// Behaviour
// Address generation
always @(posedge clk)
if (rst)
begin
col_addr <= 7'h0;
row_addr <= 5'h0;
ver_addr <= 7'h0;
hor_addr <= 7'h0;
fml_adr_o <= 16'h0;
end
else
if (enable)
begin
// h_count[2:0] == 001
col_addr <= h_count[9:3];
row_addr <= v_count[8:4];
// h_count[2:0] == 010
ver_addr <= { 2'b00, row_addr } + { row_addr, 2'b00 };
// ver_addr = row_addr x 5
hor_addr <= col_addr;
// h_count[2:0] == 011
// vga_addr = row_addr * 80 + hor_addr
fml_adr_o <= { 3'h0, vga_addr, 2'b00 };
end
// cursor
always @(posedge clk)
if (rst)
begin
cursor_on_v <= 1'b0;
cursor_on_h <= 1'b0;
end
else
if (enable)
begin
cursor_on_h <= (h_count[9:3] == hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == vcursor[4:0])
&& ({2'b00, v_count[3:0]} >= cur_start)
&& ({2'b00, v_count[3:0]} <= cur_end);
end
// FML 8x16 pipeline count
always @(posedge clk)
if (rst)
begin
pipe <= 15'b0;
end
else
if (enable)
begin
pipe <= { pipe[14:0], (h_count[3:0]==3'b0) };
end
// Load FML 8x16 burst
always @(posedge clk)
if (enable)
begin
fml1_dat <= pipe[9] ? fml_dat_i[15:0] : fml1_dat;
end
// attr_data_out
always @(posedge clk)
if (enable)
begin
if (pipe[5])
attr_data_out <= fml_dat_i[15:8];
else
if (pipe[13])
attr_data_out <= fml1_dat[15:8];
end
// char_addr_in
always @(posedge clk)
if (enable)
begin
if (pipe[5])
char_addr_in <= fml_dat_i[7:0];
else
if (pipe[13])
char_addr_in <= fml1_dat[7:0];
end
// video_on_h
always @(posedge clk)
if (rst)
begin
video_on_h <= 8'b0;
end
else
if (enable)
begin
video_on_h <= { video_on_h[6:0], video_on_h_i };
end
// horiz_sync
always @(posedge clk)
if (rst)
begin
horiz_sync <= 8'b0;
end
else
if (enable)
begin
horiz_sync <= { horiz_sync[6:0], horiz_sync_i };
end
// blink_count
always @(posedge clk)
if (rst)
begin
blink_count <= 23'h0;
end
else
if (enable)
begin
blink_count <= (blink_count + 23'h1);
end
// Video shift register
always @(posedge clk)
if (rst)
begin
fg_colour <= 4'b0;
bg_colour <= 3'b0;
vga_shift <= 8'h0;
end
else
if (enable)
begin
if (load_shift)
begin
fg_colour <= attr_data_out[3:0];
bg_colour <= attr_data_out[6:4];
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];
vga_shift <= char_data_out;
end
else vga_shift <= { vga_shift[6:0], 1'b0 };
end
// pixel attribute
always @(posedge clk)
if (rst)
begin
attr <= 4'h0;
end
else
if (enable)
begin
attr <= fg_or_bg ? fg_colour : { 1'b0, bg_colour };
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iobuf32(
input [31:0] T,
input [31:0] I,
output [31:0] O,
inout [31:0] IO
);
IOBUF iobuf0(
.T(T[0]),
.I(I[0]),
.O(O[0]),
.IO(IO[0])
);
IOBUF iobuf1(
.T(T[1]),
.I(I[1]),
.O(O[1]),
.IO(IO[1])
);
IOBUF iobuf2(
.T(T[2]),
.I(I[2]),
.O(O[2]),
.IO(IO[2])
);
IOBUF iobuf3(
.T(T[3]),
.I(I[3]),
.O(O[3]),
.IO(IO[3])
);
IOBUF iobuf4(
.T(T[4]),
.I(I[4]),
.O(O[4]),
.IO(IO[4])
);
IOBUF iobuf5(
.T(T[5]),
.I(I[5]),
.O(O[5]),
.IO(IO[5])
);
IOBUF iobuf6(
.T(T[6]),
.I(I[6]),
.O(O[6]),
.IO(IO[6])
);
IOBUF iobuf7(
.T(T[7]),
.I(I[7]),
.O(O[7]),
.IO(IO[7])
);
IOBUF iobuf8(
.T(T[8]),
.I(I[8]),
.O(O[8]),
.IO(IO[8])
);
IOBUF iobuf9(
.T(T[9]),
.I(I[9]),
.O(O[9]),
.IO(IO[9])
);
IOBUF iobuf10(
.T(T[10]),
.I(I[10]),
.O(O[10]),
.IO(IO[10])
);
IOBUF iobuf11(
.T(T[11]),
.I(I[11]),
.O(O[11]),
.IO(IO[11])
);
IOBUF iobuf12(
.T(T[12]),
.I(I[12]),
.O(O[12]),
.IO(IO[12])
);
IOBUF iobuf13(
.T(T[13]),
.I(I[13]),
.O(O[13]),
.IO(IO[13])
);
IOBUF iobuf14(
.T(T[14]),
.I(I[14]),
.O(O[14]),
.IO(IO[14])
);
IOBUF iobuf15(
.T(T[15]),
.I(I[15]),
.O(O[15]),
.IO(IO[15])
);
IOBUF iobuf16(
.T(T[16]),
.I(I[16]),
.O(O[16]),
.IO(IO[16])
);
IOBUF iobuf17(
.T(T[17]),
.I(I[17]),
.O(O[17]),
.IO(IO[17])
);
IOBUF iobuf18(
.T(T[18]),
.I(I[18]),
.O(O[18]),
.IO(IO[18])
);
IOBUF iobuf19(
.T(T[19]),
.I(I[19]),
.O(O[19]),
.IO(IO[19])
);
IOBUF iobuf20(
.T(T[20]),
.I(I[20]),
.O(O[20]),
.IO(IO[20])
);
IOBUF iobuf21(
.T(T[21]),
.I(I[21]),
.O(O[21]),
.IO(IO[21])
);
IOBUF iobuf22(
.T(T[22]),
.I(I[22]),
.O(O[22]),
.IO(IO[22])
);
IOBUF iobuf23(
.T(T[23]),
.I(I[23]),
.O(O[23]),
.IO(IO[23])
);
IOBUF iobuf24(
.T(T[24]),
.I(I[24]),
.O(O[24]),
.IO(IO[24])
);
IOBUF iobuf25(
.T(T[25]),
.I(I[25]),
.O(O[25]),
.IO(IO[25])
);
IOBUF iobuf26(
.T(T[26]),
.I(I[26]),
.O(O[26]),
.IO(IO[26])
);
IOBUF iobuf27(
.T(T[27]),
.I(I[27]),
.O(O[27]),
.IO(IO[27])
);
IOBUF iobuf28(
.T(T[28]),
.I(I[28]),
.O(O[28]),
.IO(IO[28])
);
IOBUF iobuf29(
.T(T[29]),
.I(I[29]),
.O(O[29]),
.IO(IO[29])
);
IOBUF iobuf30(
.T(T[30]),
.I(I[30]),
.O(O[30]),
.IO(IO[30])
);
IOBUF iobuf31(
.T(T[31]),
.I(I[31]),
.O(O[31]),
.IO(IO[31])
);
endmodule
|
module test;
reg pass;
reg [8*40:1] str;
integer s;
reg [31:0] su;
integer res;
initial begin
pass = 1'b1;
s = 2000;
su = 2000;
res = s + (1 << 3) - 1;
if (res !== 2007) begin
$display("FAILED first term << (s), expected 2007, got %d", res);
pass = 1'b0;
end
res = su + (1 << 3) - 1;
if (res !== 2007) begin
$display("FAILED first term << (su), expected 2007, got %d", res);
pass = 1'b0;
end
res = s + (16 >> 1) - 1;
if (res !== 2007) begin
$display("FAILED first term >> (s), expected 2007, got %d", res);
pass = 1'b0;
end
res = su + (16 >> 1) - 1;
if (res !== 2007) begin
$display("FAILED first term >> (su), expected 2007, got %d", res);
pass = 1'b0;
end
res = (s + (1 << 3) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term << (s), expected 32112000, got %d", res);
pass = 1'b0;
end
res = (su + (1 << 3) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term << (su), expected 32112000, got %d", res);
pass = 1'b0;
end
res = (s + (16 >> 1) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term >> (s), expected 32112000, got %d", res);
pass = 1'b0;
end
res = (su + (16 >> 1) - 1) * 16000;
if (res !== 32112000) begin
$display("FAILED second term >> (su), expected 32112000, got %d", res);
pass = 1'b0;
end
$sformat(str, "%0d", s + (1 << 3) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string << (s), expected \"2007\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", su + (1 << 3) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string << (su), expected \"2007\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", s + (16 >> 1) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string >> (s), expected \"2007\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", su + (16 >> 1) - 1);
if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin
$display("FAILED first string >> (su), expected \"2007\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", (s + (1 << 3) - 1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string << (s), expected \"32112000\", got %s",
str);
pass = 1'b0;
end
$sformat(str, "%0d", (su + (1 << 3) - 1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string << (su), expected \"32112000\", got %s",
str);
pass = 1'b0;
end
$sformat(str, "%0d", (s + (16 >> 1) - 1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string >> (s), expected \"32112000\", got %s",
str);
pass = 1'b0;
end
$sformat(str, "%0d", (su + (16 >> 1) -1) * 16000);
if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin
$display("FAILED second string >> (su), expected \"32112000\", got %s",
str);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:04:46 03/14/2015
// Design Name: deserializer
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/sys-rek/lab3/deserializer/tb_deserializer.v
// Project Name: deserializer
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: deserializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_deserializer;
wire rxd;
wire rst;
wire clk;
wire [7:0] data;
wire received;
deserializer_gen_test generator (
.rxd(rxd),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
deserializer uut (
.rxd(rxd),
.rst(rst),
.clk(clk),
.data(data),
.received(received)
);
deserializer_check_test writer (
.received(received),
.data(data)
);
endmodule
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: addsub16.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 17
module addsub16_add_sub_gp9
(
aclr,
add_sub,
clken,
clock,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr;
input add_sub;
input clken;
input clock;
input [15:0] dataa;
input [15:0] datab;
output [15:0] result;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [0:0] wire_add_sub_cella_7cout;
wire [0:0] wire_add_sub_cella_8cout;
wire [0:0] wire_add_sub_cella_9cout;
wire [0:0] wire_add_sub_cella_10cout;
wire [0:0] wire_add_sub_cella_11cout;
wire [0:0] wire_add_sub_cella_12cout;
wire [0:0] wire_add_sub_cella_13cout;
wire [0:0] wire_add_sub_cella_14cout;
wire [15:0] wire_add_sub_cella_dataa;
wire [15:0] wire_add_sub_cella_datab;
wire [15:0] wire_add_sub_cella_regout;
wire wire_strx_lcell1_cout;
stratix_lcell add_sub_cella_0
(
.aclr(aclr),
.cin(wire_strx_lcell1_cout),
.clk(clock),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.aclr(aclr),
.cin(wire_add_sub_cella_0cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.aclr(aclr),
.cin(wire_add_sub_cella_1cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.aclr(aclr),
.cin(wire_add_sub_cella_2cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.aclr(aclr),
.cin(wire_add_sub_cella_3cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.aclr(aclr),
.cin(wire_add_sub_cella_4cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.aclr(aclr),
.cin(wire_add_sub_cella_5cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.aclr(aclr),
.cin(wire_add_sub_cella_6cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_7cout[0:0]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "96e8",
add_sub_cella_7.operation_mode = "arithmetic",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_8
(
.aclr(aclr),
.cin(wire_add_sub_cella_7cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_8cout[0:0]),
.dataa(wire_add_sub_cella_dataa[8:8]),
.datab(wire_add_sub_cella_datab[8:8]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[8:8]));
defparam
add_sub_cella_8.cin_used = "true",
add_sub_cella_8.lut_mask = "96e8",
add_sub_cella_8.operation_mode = "arithmetic",
add_sub_cella_8.sum_lutc_input = "cin",
add_sub_cella_8.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_9
(
.aclr(aclr),
.cin(wire_add_sub_cella_8cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_9cout[0:0]),
.dataa(wire_add_sub_cella_dataa[9:9]),
.datab(wire_add_sub_cella_datab[9:9]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[9:9]));
defparam
add_sub_cella_9.cin_used = "true",
add_sub_cella_9.lut_mask = "96e8",
add_sub_cella_9.operation_mode = "arithmetic",
add_sub_cella_9.sum_lutc_input = "cin",
add_sub_cella_9.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_10
(
.aclr(aclr),
.cin(wire_add_sub_cella_9cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_10cout[0:0]),
.dataa(wire_add_sub_cella_dataa[10:10]),
.datab(wire_add_sub_cella_datab[10:10]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[10:10]));
defparam
add_sub_cella_10.cin_used = "true",
add_sub_cella_10.lut_mask = "96e8",
add_sub_cella_10.operation_mode = "arithmetic",
add_sub_cella_10.sum_lutc_input = "cin",
add_sub_cella_10.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_11
(
.aclr(aclr),
.cin(wire_add_sub_cella_10cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_11cout[0:0]),
.dataa(wire_add_sub_cella_dataa[11:11]),
.datab(wire_add_sub_cella_datab[11:11]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[11:11]));
defparam
add_sub_cella_11.cin_used = "true",
add_sub_cella_11.lut_mask = "96e8",
add_sub_cella_11.operation_mode = "arithmetic",
add_sub_cella_11.sum_lutc_input = "cin",
add_sub_cella_11.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_12
(
.aclr(aclr),
.cin(wire_add_sub_cella_11cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_12cout[0:0]),
.dataa(wire_add_sub_cella_dataa[12:12]),
.datab(wire_add_sub_cella_datab[12:12]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[12:12]));
defparam
add_sub_cella_12.cin_used = "true",
add_sub_cella_12.lut_mask = "96e8",
add_sub_cella_12.operation_mode = "arithmetic",
add_sub_cella_12.sum_lutc_input = "cin",
add_sub_cella_12.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_13
(
.aclr(aclr),
.cin(wire_add_sub_cella_12cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_13cout[0:0]),
.dataa(wire_add_sub_cella_dataa[13:13]),
.datab(wire_add_sub_cella_datab[13:13]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[13:13]));
defparam
add_sub_cella_13.cin_used = "true",
add_sub_cella_13.lut_mask = "96e8",
add_sub_cella_13.operation_mode = "arithmetic",
add_sub_cella_13.sum_lutc_input = "cin",
add_sub_cella_13.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_14
(
.aclr(aclr),
.cin(wire_add_sub_cella_13cout[0:0]),
.clk(clock),
.cout(wire_add_sub_cella_14cout[0:0]),
.dataa(wire_add_sub_cella_dataa[14:14]),
.datab(wire_add_sub_cella_datab[14:14]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[14:14]));
defparam
add_sub_cella_14.cin_used = "true",
add_sub_cella_14.lut_mask = "96e8",
add_sub_cella_14.operation_mode = "arithmetic",
add_sub_cella_14.sum_lutc_input = "cin",
add_sub_cella_14.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_15
(
.aclr(aclr),
.cin(wire_add_sub_cella_14cout[0:0]),
.clk(clock),
.dataa(wire_add_sub_cella_dataa[15:15]),
.datab(wire_add_sub_cella_datab[15:15]),
.ena(clken),
.inverta((~ add_sub)),
.regout(wire_add_sub_cella_regout[15:15]));
defparam
add_sub_cella_15.cin_used = "true",
add_sub_cella_15.lut_mask = "9696",
add_sub_cella_15.operation_mode = "normal",
add_sub_cella_15.sum_lutc_input = "cin",
add_sub_cella_15.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = datab,
wire_add_sub_cella_datab = dataa;
stratix_lcell strx_lcell1
(
.cout(wire_strx_lcell1_cout),
.dataa(1'b0),
.datab((~ add_sub)),
.inverta((~ add_sub)));
defparam
strx_lcell1.cin_used = "false",
strx_lcell1.lut_mask = "00cc",
strx_lcell1.operation_mode = "arithmetic",
strx_lcell1.lpm_type = "stratix_lcell";
assign
result = wire_add_sub_cella_regout;
endmodule //addsub16_add_sub_gp9
//VALID FILE
module addsub16 (
add_sub,
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
input aclr;
input clken;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
addsub16_add_sub_gp9 addsub16_add_sub_gp9_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clken (clken),
.aclr (aclr),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "1"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:43 02/02/2015
// Design Name:
// Module Name: sha256_W
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sha256_W (
input clk,
input load_i,
input busy_i,
input [511:0] data_i,
output [31:0] W_o
);
`define DATA_IDX(x) data_i[512 - (x * 32) - 1:512 - (x * 32) - 32]
reg [31:0] W[15:0];
reg [31:0] W_new00, W_new01, W_new02, W_new03, W_new04, W_new05, W_new06, W_new07;
reg [31:0] W_new08, W_new09, W_new10, W_new11, W_new12, W_new13, W_new14, W_new15;
reg [31:0] W_new;
reg [31:0] h0, h1, h0_new, h1_new;
always @(posedge clk)
begin
W[ 0] <= W_new00;
W[ 1] <= W_new01;
W[ 2] <= W_new02;
W[ 3] <= W_new03;
W[ 4] <= W_new04;
W[ 5] <= W_new05;
W[ 6] <= W_new06;
W[ 7] <= W_new07;
W[ 8] <= W_new08;
W[ 9] <= W_new09;
W[10] <= W_new10;
W[11] <= W_new11;
W[12] <= W_new12;
W[13] <= W_new13;
W[14] <= W_new14;
W[15] <= W_new15;
h0 <= h0_new;
h1 <= h1_new;
end
assign W_o = W[0];
always @*
begin : W_update
reg [31:0] w_0, w_1, w_9, w_14, d0, d1;
W_new00 = 0;
W_new01 = 0;
W_new02 = 0;
W_new03 = 0;
W_new04 = 0;
W_new05 = 0;
W_new06 = 0;
W_new07 = 0;
W_new08 = 0;
W_new09 = 0;
W_new10 = 0;
W_new11 = 0;
W_new12 = 0;
W_new13 = 0;
W_new14 = 0;
W_new15 = 0;
w_0 = W[1];
w_1 = W[2];
w_9 = W[10];
w_14 = W[15];
W_new = h0 + h1;
if(load_i)
begin
W_new00 = `DATA_IDX( 0);
W_new01 = `DATA_IDX( 1);
W_new02 = `DATA_IDX( 2);
W_new03 = `DATA_IDX( 3);
W_new04 = `DATA_IDX( 4);
W_new05 = `DATA_IDX( 5);
W_new06 = `DATA_IDX( 6);
W_new07 = `DATA_IDX( 7);
W_new08 = `DATA_IDX( 8);
W_new09 = `DATA_IDX( 9);
W_new10 = `DATA_IDX(10);
W_new11 = `DATA_IDX(11);
W_new12 = `DATA_IDX(12);
W_new13 = `DATA_IDX(13);
W_new14 = `DATA_IDX(14);
W_new15 = `DATA_IDX(15);
w_0 = `DATA_IDX(0);
w_1 = `DATA_IDX(1);
w_9 = `DATA_IDX(9);
w_14 = `DATA_IDX(14);
end
else if(busy_i)
begin
W_new00 = W[ 1];
W_new01 = W[ 2];
W_new02 = W[ 3];
W_new03 = W[ 4];
W_new04 = W[ 5];
W_new05 = W[ 6];
W_new06 = W[ 7];
W_new07 = W[ 8];
W_new08 = W[ 9];
W_new09 = W[10];
W_new10 = W[11];
W_new11 = W[12];
W_new12 = W[13];
W_new13 = W[14];
W_new14 = W[15];
W_new15 = W_new;
end
d0 = {w_1[ 6: 0], w_1[31: 7]} ^ {w_1[17: 0], w_1[31:18]} ^ {3'h0, w_1[31: 3]};
d1 = {w_14[16: 0], w_14[31:17]} ^ {w_14[18: 0], w_14[31:19]} ^ {10'h0, w_14[31:10]};
h0_new = d0 + w_0;
h1_new = d1 + w_9;
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`define ENABLE_VCD
`define TEST_SOMETRANSFERS
//`define TEST_RANDOMTRANSFERS
//`define TEST_PEAK
module tb_hpdmc();
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire [3:0] sdram_dm;
wire [12:0] sdram_adr;
wire [1:0] sdram_ba;
wire [31:0] sdram_dq;
wire [3:0] sdram_dqs;
ddr sdram1(
.Addr(sdram_adr),
.Ba(sdram_ba),
.Clk(clk),
.Clk_n(~clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dm(sdram_dm[3:2]),
.Dqs(sdram_dqs[3:2]),
.Dq(sdram_dq[31:16])
);
ddr sdram0(
.Addr(sdram_adr),
.Ba(sdram_ba),
.Clk(clk),
.Clk_n(~clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dm(sdram_dm[1:0]),
.Dqs(sdram_dqs[1:0]),
.Dq(sdram_dq[15:0])
);
reg rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [25:0] fml_adr;
reg fml_stb;
reg fml_we;
wire fml_eack;
reg [7:0] fml_sel;
reg [63:0] fml_di;
wire [63:0] fml_do;
hpdmc dut(
.sys_clk(clk),
.sys_clk_n(~clk),
.sys_rst(rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_eack(fml_eack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dm(sdram_dm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs)
);
pulldown(sdram_dqs[0]);
pulldown(sdram_dqs[1]);
pulldown(sdram_dqs[2]);
pulldown(sdram_dqs[3]);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
for(i=0;i<n;i=i+1)
waitclock;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
real reads;
real read_clocks;
task readburst;
input [31:0] address;
integer i;
integer b;
begin
$display("READ [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b0;
i = 0;
#1;
while(~fml_eack) begin
i = i+1;
waitclock;
end
if(i == 0) begin
b = 1;
waitclock;
end else
b = 0;
$display("%t: Memory Read : %x early acked in %d clocks", $time, address, i);
fml_stb = 1'b0;
reads = reads + 1;
read_clocks = read_clocks + i + 5;
i = 0;
while(i < (4-b)) begin
i = i+1;
waitclock;
end
for(i=0;i<4;i=i+1) begin
waitclock;
$display("%t: (R burst) %x", $time, fml_do);
end
waitclock;
end
endtask
real writes;
real write_clocks;
task writeburst;
input [31:0] address;
integer i;
integer b;
begin
$display("WRITE [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b1;
fml_sel = 8'hff;
fml_di = {$random, $random};
i = 0;
#1;
while(~fml_eack) begin
i = i+1;
waitclock;
end
if(i == 0) begin
waitclock;
b = 1;
end else
b = 0;
$display("%t: Memory Write : %x=%x early acked in %d clocks", $time, address, fml_di, i);
fml_stb = 1'b0;
writes = writes + 1;
write_clocks = write_clocks + i + 2;
i = 0;
while(i < (2-b)) begin
i = i+1;
waitclock;
end
for(i=0;i<3;i=i+1) begin
waitclock;
fml_di = {$random, $random};
$display("%t: (W burst) %x", $time, fml_di);
end
waitclock;
end
endtask
integer n, addr;
always begin
`ifdef ENABLE_VCD
$dumpfile("hpdmc.vcd");
`endif
/* Reset / Initialize our logic */
rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_adr = 26'd0;
fml_di = 64'd0;
fml_sel = 8'd0;
fml_stb = 1'b0;
fml_we = 1'b0;
waitclock;
rst = 1'b0;
waitclock;
/* SDRAM initialization sequence. */
/* The controller already comes up in Bypass mode with CKE disabled. */
/* Wait 200us */
//#200000;
#200;
/* Bring CKE high */
csrwrite(32'h00, 32'h07);
/* Precharge All:
* CS=1
* WE=1
* CAS=0
* RAS=1
* A=A10
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Load Extended Mode Register:
* CS=1
* WE=1
* CAS=1
* RAS=1
* A=Value
* BA=01
*
* Extended mode register encoding :
* A12-A2 reserved, must be 0
* A1 weak drive strength
* A0 DLL disable
*/
csrwrite(32'h04, 32'b01_0000000000000_1111);
waitnclock(2);
/* Load Mode Register, DLL in Reset:
* CS=1
* WE=1
* CAS=1
* RAS=1
* A=Value
* BA=00
*
* Mode register encoding :
* A12-A7 = 000000 Normal operation w/o DLL reset
* 000010 Normal operation in DLL reset
* A6-A4 = 010 CL2
* A3 = 0 Sequential burst
* A2-A0 = 011 Burst length = 8
*/
csrwrite(32'h04, 32'b00__000010_010_0_011__1111);
waitnclock(200);
/* Precharge All */
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Auto Refresh
* CS=1
* WE=0
* CAS=1
* RAS=1
* A=Don't Care
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Auto Refresh */
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Load Mode Register, DLL enabled */
csrwrite(32'h04, 32'b00__000000_010_0_011__1111);
waitnclock(200);
/* SDRAM initialization completed */
`ifdef ENABLE_VCD
/* Now, we want to know what the controller will send to the SDRAM chips */
$dumpvars(0, dut);
`endif
/* Bring up the controller ! */
csrwrite(32'h00, 32'h04);
`ifdef TEST_SOMETRANSFERS
/*
* Try some transfers.
*/
writeburst(32'h00);
writeburst(32'h200000);
//writeburst(32'h20);
//writeburst(32'h40);
readburst(32'h200000);
readburst(32'h00);
//readburst(32'h20);
/*readburst(32'h40);
writeburst(32'h40);
readburst(32'h40);*/
`endif
`ifdef TEST_RANDOMTRANSFERS
writes = 0;
write_clocks = 0;
reads = 0;
read_clocks = 0;
for(n=0;n<500;n=n+1) begin
addr = $random;
if($random > 32'h80000000) begin
writeburst(addr);
//writeburst(addr+32'h20);
//writeburst(addr+32'h40);
end else begin
readburst(addr);
//readburst(addr+32'h20);
//readburst(addr+32'h40);
end
end
$display("");
$display("=======================================================");
$display(" Tested: %.0f reads, %.0f writes ", reads, writes);
$display("=======================================================");
$display(" Average read latency: %f cycles", read_clocks/reads);
$display(" Average write latency: %f cycles", write_clocks/writes);
$display("=======================================================");
$display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100);
$display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100);
$display("=======================================================");
`endif
`ifdef TEST_PEAK
fml_adr = 32'h000000;
fml_stb = 1'b1;
fml_we = 1'b0;
n = 0;
while(n < 10) begin
while(~fml_eack) begin
waitclock;
end
waitclock;
n = n+1;
end
/* generate page miss */
fml_adr = 32'h200000;
n = 0;
while(n < 10) begin
while(~fml_eack) begin
waitclock;
end
waitclock;
n = n+1;
end
`endif
$finish;
end
endmodule
|
module FswArbiter (/*AUTOARG*/
// Outputs
xb_ecc_error_dbit, xb_ecc_error_1bit, insert_idle_ack, bp_performance_count, obx_xb0_GntPst_s3a,
obx_xb0_GntByp_s3a, obx_xb1_GntPst_s3a, obx_xb1_GntByp_s3a, obx_xb2_GntPst_s3a,
obx_xb2_GntByp_s3a, obx_xb3_GntPst_s3a, obx_xb3_GntByp_s3a, xbx_grant_cycle, bp1_grant_cycle,
set_arbitration_enable_d1, reset_ackbuf, wait_for_ack, ice9_databus,
// Inputs
sclk, lreset_l, csr_insert_idle, csr_arb_enable, csr_bypass3_enable, csr_bypass2_enable,
csr_bypass1_enable, csr_xb_ecc_enable, xb0_obx_ReqPst_s2a, xb0_obx_NextVc_s2a,
xb0_obx_NextPort_s2a, xb0_obx_NextXbe_s2a, xb0_obx_NextXbe_s3a, xb0_obx_OutDat_s4a,
xb0_obx_ReqBypS3_s2a, xb0_obx_ReqBypS2_s2a, xb1_obx_ReqPst_s2a, xb1_obx_NextVc_s2a,
xb1_obx_NextPort_s2a, xb1_obx_NextXbe_s2a, xb1_obx_NextXbe_s3a, xb1_obx_OutDat_s4a,
xb1_obx_ReqBypS3_s2a, xb1_obx_ReqBypS2_s2a, xb2_obx_ReqPst_s2a, xb2_obx_NextVc_s2a,
xb2_obx_NextPort_s2a, xb2_obx_NextXbe_s2a, xb2_obx_NextXbe_s3a, xb2_obx_OutDat_s4a,
xb2_obx_ReqBypS3_s2a, xb2_obx_ReqBypS2_s2a, xb3_obx_ReqPst_s2a, xb3_obx_NextVc_s2a,
xb3_obx_NextPort_s2a, xb3_obx_NextXbe_s2a, xb3_obx_NextXbe_s3a, xb3_obx_OutDat_s4a,
xb3_obx_ReqBypS3_s2a, xb3_obx_ReqBypS2_s2a, ib0_obx_PortSel_s1a, ib0_obx_InDat_s1a,
ib0_obx_NextPort_s1a, ib0_obx_NextVc_s1a, ib1_obx_PortSel_s1a, ib1_obx_InDat_s1a,
ib1_obx_NextPort_s1a, ib1_obx_NextVc_s1a, ib2_obx_PortSel_s1a, ib2_obx_InDat_s1a,
ib2_obx_NextPort_s1a, ib2_obx_NextVc_s1a, ib3_obx_PortSel_s1a, ib3_obx_InDat_s1a,
ib3_obx_NextPort_s1a, ib3_obx_NextVc_s1a, rp_is_full, rp_in_progress, rp_arb_poolmask,
rp_arb_bufbusy_mask
) ;
// ========================
// Include parameter File
// ========================
parameter DMAO = 0;
`include "chip_fsw_spec_param.v"
// ===============
// Physical Pins
// ===============
input sclk; // Fabric switch clock
input lreset_l;
input csr_insert_idle;
input csr_arb_enable;
input [3:0] csr_bypass3_enable;
input [3:0] csr_bypass2_enable;
input [3:0] csr_bypass1_enable;
input csr_xb_ecc_enable;
output [3:0] xb_ecc_error_dbit;
output [3:0] xb_ecc_error_1bit;
output insert_idle_ack;
output [2:0] bp_performance_count;
input xb0_obx_ReqPst_s2a;
input [3:0] xb0_obx_NextVc_s2a;
input [1:0] xb0_obx_NextPort_s2a;
input [3:0] xb0_obx_NextXbe_s2a;
input [3:0] xb0_obx_NextXbe_s3a;
input [71:0] xb0_obx_OutDat_s4a;
output obx_xb0_GntPst_s3a;
output obx_xb0_GntByp_s3a;
input xb0_obx_ReqBypS3_s2a;
input xb0_obx_ReqBypS2_s2a;
input xb1_obx_ReqPst_s2a;
input [3:0] xb1_obx_NextVc_s2a;
input [1:0] xb1_obx_NextPort_s2a;
input [3:0] xb1_obx_NextXbe_s2a;
input [3:0] xb1_obx_NextXbe_s3a;
input [71:0] xb1_obx_OutDat_s4a;
output obx_xb1_GntPst_s3a;
output obx_xb1_GntByp_s3a;
input xb1_obx_ReqBypS3_s2a;
input xb1_obx_ReqBypS2_s2a;
input xb2_obx_ReqPst_s2a;
input [3:0] xb2_obx_NextVc_s2a;
input [1:0] xb2_obx_NextPort_s2a;
input [3:0] xb2_obx_NextXbe_s2a;
input [3:0] xb2_obx_NextXbe_s3a;
input [71:0] xb2_obx_OutDat_s4a;
output obx_xb2_GntPst_s3a;
output obx_xb2_GntByp_s3a;
input xb2_obx_ReqBypS3_s2a;
input xb2_obx_ReqBypS2_s2a;
input xb3_obx_ReqPst_s2a;
input [3:0] xb3_obx_NextVc_s2a;
input [1:0] xb3_obx_NextPort_s2a;
input [3:0] xb3_obx_NextXbe_s2a;
input [3:0] xb3_obx_NextXbe_s3a;
input [71:0] xb3_obx_OutDat_s4a;
output obx_xb3_GntPst_s3a;
output obx_xb3_GntByp_s3a;
input xb3_obx_ReqBypS3_s2a;
input xb3_obx_ReqBypS2_s2a;
input ib0_obx_PortSel_s1a;
input [63:0] ib0_obx_InDat_s1a;
input [1:0] ib0_obx_NextPort_s1a;
input [3:0] ib0_obx_NextVc_s1a;
input ib1_obx_PortSel_s1a;
input [63:0] ib1_obx_InDat_s1a;
input [1:0] ib1_obx_NextPort_s1a;
input [3:0] ib1_obx_NextVc_s1a;
input ib2_obx_PortSel_s1a;
input [63:0] ib2_obx_InDat_s1a;
input [1:0] ib2_obx_NextPort_s1a;
input [3:0] ib2_obx_NextVc_s1a;
input ib3_obx_PortSel_s1a;
input [63:0] ib3_obx_InDat_s1a;
input [1:0] ib3_obx_NextPort_s1a;
input [3:0] ib3_obx_NextVc_s1a;
input rp_is_full;
input rp_in_progress;
input [15:0] rp_arb_poolmask;
input [63:0] rp_arb_bufbusy_mask;
output xbx_grant_cycle;
output bp1_grant_cycle;
output set_arbitration_enable_d1;
output [63:0] reset_ackbuf;
output [63:0] wait_for_ack;
output [63:0] ice9_databus;
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bp1_grant0; // From bp1 of FswBypassArbiter.v
wire bp1_grant1; // From bp1 of FswBypassArbiter.v
wire bp1_grant2; // From bp1 of FswBypassArbiter.v
wire bp1_grant3; // From bp1 of FswBypassArbiter.v
wire bp1_grant_cycle_d1; // From bp1 of FswBypassArbiter.v
wire bp1_grant_cycle_d2; // From bp1 of FswBypassArbiter.v
wire bp1_header; // From bp1 of FswBypassArbiter.v
wire bp1_header_d1; // From bp1 of FswBypassArbiter.v
wire bp1_header_d2; // From bp1 of FswBypassArbiter.v
wire [5:0] bp1_hold_wait_vector; // From bp1 of FswBypassArbiter.v
wire [5:0] bp1_hold_wait_vector_d1;// From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner; // From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner_d1; // From bp1 of FswBypassArbiter.v
wire [1:0] bp1_next_winner_d2; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe_d1; // From bp1 of FswBypassArbiter.v
wire [3:0] bp1_nextxbe_d2; // From bp1 of FswBypassArbiter.v
wire bp1_select; // From bp1 of FswBypassArbiter.v
wire bp1_select_d1; // From bp1 of FswBypassArbiter.v
wire bp1_select_d2; // From bp1 of FswBypassArbiter.v
wire bp2_grant0; // From bp2 of FswBypassArbiter.v
wire bp2_grant1; // From bp2 of FswBypassArbiter.v
wire bp2_grant2; // From bp2 of FswBypassArbiter.v
wire bp2_grant3; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle_d1; // From bp2 of FswBypassArbiter.v
wire bp2_grant_cycle_d2; // From bp2 of FswBypassArbiter.v
wire bp2_header; // From bp2 of FswBypassArbiter.v
wire bp2_header_d1; // From bp2 of FswBypassArbiter.v
wire bp2_header_d2; // From bp2 of FswBypassArbiter.v
wire [5:0] bp2_hold_wait_vector; // From bp2 of FswBypassArbiter.v
wire [5:0] bp2_hold_wait_vector_d1;// From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner; // From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner_d1; // From bp2 of FswBypassArbiter.v
wire [1:0] bp2_next_winner_d2; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe_d1; // From bp2 of FswBypassArbiter.v
wire [3:0] bp2_nextxbe_d2; // From bp2 of FswBypassArbiter.v
wire bp2_select; // From bp2 of FswBypassArbiter.v
wire bp2_select_d1; // From bp2 of FswBypassArbiter.v
wire bp2_select_d2; // From bp2 of FswBypassArbiter.v
wire bp3_grant0; // From bp3 of FswBypassArbiter.v
wire bp3_grant1; // From bp3 of FswBypassArbiter.v
wire bp3_grant2; // From bp3 of FswBypassArbiter.v
wire bp3_grant3; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle_d1; // From bp3 of FswBypassArbiter.v
wire bp3_grant_cycle_d2; // From bp3 of FswBypassArbiter.v
wire bp3_header; // From bp3 of FswBypassArbiter.v
wire bp3_header_d1; // From bp3 of FswBypassArbiter.v
wire bp3_header_d2; // From bp3 of FswBypassArbiter.v
wire [5:0] bp3_hold_wait_vector; // From bp3 of FswBypassArbiter.v
wire [5:0] bp3_hold_wait_vector_d1;// From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner; // From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner_d1; // From bp3 of FswBypassArbiter.v
wire [1:0] bp3_next_winner_d2; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe_d1; // From bp3 of FswBypassArbiter.v
wire [3:0] bp3_nextxbe_d2; // From bp3 of FswBypassArbiter.v
wire bp3_select; // From bp3 of FswBypassArbiter.v
wire bp3_select_d1; // From bp3 of FswBypassArbiter.v
wire bp3_select_d2; // From bp3 of FswBypassArbiter.v
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] bp_performance_count;
reg [63:0] ice9_databus;
reg insert_idle_ack;
reg obx_xb0_GntByp_s3a;
reg obx_xb0_GntPst_s3a;
reg obx_xb1_GntByp_s3a;
reg obx_xb1_GntPst_s3a;
reg obx_xb2_GntByp_s3a;
reg obx_xb2_GntPst_s3a;
reg obx_xb3_GntByp_s3a;
reg obx_xb3_GntPst_s3a;
reg [63:0] reset_ackbuf;
reg set_arbitration_enable_d1;
reg [63:0] wait_for_ack;
reg [3:0] xb_ecc_error_1bit;
reg [3:0] xb_ecc_error_dbit;
reg xbx_grant_cycle;
// End of automatics
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp3_enable_3),
.sop2 (sop2 & xbx_bp3_enable_2),
.sop1 (sop1 & xbx_bp3_enable_1),
.sop0 (sop0 & xbx_bp3_enable_0),
); */
FswBypassArbiter bp3 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp3_grant3), // Templated
.bp_grant2 (bp3_grant2), // Templated
.bp_grant1 (bp3_grant1), // Templated
.bp_grant0 (bp3_grant0), // Templated
.bp_grant_cycle (bp3_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp3_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp3_grant_cycle_d2), // Templated
.bp_next_winner (bp3_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp3_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp3_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp3_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp3_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp3_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp3_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp3_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp3_header), // Templated
.bp_header_d1 (bp3_header_d1), // Templated
.bp_header_d2 (bp3_header_d2), // Templated
.bp_select (bp3_select), // Templated
.bp_select_d1 (bp3_select_d1), // Templated
.bp_select_d2 (bp3_select_d2), // Templated
// Inputs
.lreset_l (bp3_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp3_arb_enable), // Templated
.sop3 (sop3 & xbx_bp3_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & xbx_bp3_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & xbx_bp3_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & xbx_bp3_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp2_enable_3),
.sop2 (sop2 & xbx_bp2_enable_2),
.sop1 (sop1 & xbx_bp2_enable_1),
.sop0 (sop0 & xbx_bp2_enable_0),
); */
FswBypassArbiter bp2 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp2_grant3), // Templated
.bp_grant2 (bp2_grant2), // Templated
.bp_grant1 (bp2_grant1), // Templated
.bp_grant0 (bp2_grant0), // Templated
.bp_grant_cycle (bp2_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp2_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp2_grant_cycle_d2), // Templated
.bp_next_winner (bp2_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp2_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp2_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp2_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp2_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp2_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp2_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp2_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp2_header), // Templated
.bp_header_d1 (bp2_header_d1), // Templated
.bp_header_d2 (bp2_header_d2), // Templated
.bp_select (bp2_select), // Templated
.bp_select_d1 (bp2_select_d1), // Templated
.bp_select_d2 (bp2_select_d2), // Templated
// Inputs
.lreset_l (bp2_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp2_arb_enable), // Templated
.sop3 (sop3 & xbx_bp2_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & xbx_bp2_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & xbx_bp2_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & xbx_bp2_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & csr_bp1_enable_3),
.sop2 (sop2 & csr_bp1_enable_2),
.sop1 (sop1 & csr_bp1_enable_1),
.sop0 (sop0 & csr_bp1_enable_0),
); */
FswBypassArbiter bp1 (/*AUTOINST*/
// Outputs
.bp_grant3 (bp1_grant3), // Templated
.bp_grant2 (bp1_grant2), // Templated
.bp_grant1 (bp1_grant1), // Templated
.bp_grant0 (bp1_grant0), // Templated
.bp_grant_cycle (bp1_grant_cycle), // Templated
.bp_grant_cycle_d1 (bp1_grant_cycle_d1), // Templated
.bp_grant_cycle_d2 (bp1_grant_cycle_d2), // Templated
.bp_next_winner (bp1_next_winner[1:0]), // Templated
.bp_next_winner_d1 (bp1_next_winner_d1[1:0]), // Templated
.bp_next_winner_d2 (bp1_next_winner_d2[1:0]), // Templated
.bp_nextxbe (bp1_nextxbe[3:0]), // Templated
.bp_nextxbe_d1 (bp1_nextxbe_d1[3:0]), // Templated
.bp_nextxbe_d2 (bp1_nextxbe_d2[3:0]), // Templated
.bp_hold_wait_vector (bp1_hold_wait_vector[5:0]), // Templated
.bp_hold_wait_vector_d1(bp1_hold_wait_vector_d1[5:0]), // Templated
.bp_header (bp1_header), // Templated
.bp_header_d1 (bp1_header_d1), // Templated
.bp_header_d2 (bp1_header_d2), // Templated
.bp_select (bp1_select), // Templated
.bp_select_d1 (bp1_select_d1), // Templated
.bp_select_d2 (bp1_select_d2), // Templated
// Inputs
.lreset_l (bp1_lreset_l), // Templated
.sclk (sclk),
.bp_arb_enable (bp1_arb_enable), // Templated
.sop3 (sop3 & csr_bp1_enable_3), // Templated
.sop3_data (sop3_data[63:0]),
.sop3_bpcontext (sop3_bpcontext[5:0]),
.sop2 (sop2 & csr_bp1_enable_2), // Templated
.sop2_data (sop2_data[63:0]),
.sop2_bpcontext (sop2_bpcontext[5:0]),
.sop1 (sop1 & csr_bp1_enable_1), // Templated
.sop1_data (sop1_data[63:0]),
.sop1_bpcontext (sop1_bpcontext[5:0]),
.sop0 (sop0 & csr_bp1_enable_0), // Templated
.sop0_data (sop0_data[63:0]),
.sop0_bpcontext (sop0_bpcontext[5:0]),
.poolmask (poolmask[15:0]),
.bufbusy_mask (bufbusy_mask[63:0]));
// =======================================
// Coverage
// =======================================
// psl default clock = negedge sclk;
generate if (DMAO == 0)
begin
// psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
// psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
// psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
end
endgenerate
// ================
// Unused signals
// ================
// lint_checking SCX_UNUSED off
wire _unused_ok = &{1'b0,
bp_select,
bp3_hold_wait_vector,
bp2_hold_wait_vector_d1,
bp1_hold_wait_vector_d1,
bp3_header,
bp3_header_d1,
bp3_select,
bp3_select_d1,
bp3_next_winner[1:0],
bp3_next_winner_d1[1:0],
bp3_nextxbe[3:0],
bp3_nextxbe_d1[3:0],
bp2_grant_cycle_d2,
bp2_header,
bp2_header_d2,
bp2_select,
bp2_select_d2,
bp2_next_winner[1:0],
bp2_next_winner_d2[1:0],
bp2_nextxbe[3:0],
bp2_nextxbe_d2[3:0],
bp1_header_d1,
bp1_header_d2,
bp1_select_d1,
bp1_select_d2,
bp1_next_winner_d1[1:0],
bp1_next_winner_d2[1:0],
bp1_nextxbe_d1[3:0],
bp1_nextxbe_d2[3:0],
xb0_obx_NextXbe_s3a, // This is unused signal now.
xb1_obx_NextXbe_s3a,
xb2_obx_NextXbe_s3a,
xb3_obx_NextXbe_s3a,
syn64,
dataout64,
1'b0
};
// lint_checking SCX_UNUSED on
endmodule
module FswBypassArbiter (/*AUTOARG*/
// Outputs
bp_grant3, bp_grant2, bp_grant1, bp_grant0, bp_grant_cycle, bp_grant_cycle_d1, bp_grant_cycle_d2,
bp_next_winner, bp_next_winner_d1, bp_next_winner_d2, bp_nextxbe, bp_nextxbe_d1, bp_nextxbe_d2,
bp_hold_wait_vector, bp_hold_wait_vector_d1, bp_header, bp_header_d1, bp_header_d2, bp_select,
bp_select_d1, bp_select_d2,
// Inputs
lreset_l, sclk, bp_arb_enable, sop3, sop3_data, sop3_bpcontext, sop2, sop2_data, sop2_bpcontext,
sop1, sop1_data, sop1_bpcontext, sop0, sop0_data, sop0_bpcontext, poolmask, bufbusy_mask
) ;
input lreset_l;
input sclk;
input bp_arb_enable;
output bp_grant3;
output bp_grant2;
output bp_grant1;
output bp_grant0;
output bp_grant_cycle;
output bp_grant_cycle_d1;
output bp_grant_cycle_d2;
output [1:0] bp_next_winner;
output [1:0] bp_next_winner_d1;
output [1:0] bp_next_winner_d2;
output [3:0] bp_nextxbe;
output [3:0] bp_nextxbe_d1;
output [3:0] bp_nextxbe_d2;
output [5:0] bp_hold_wait_vector;
output [5:0] bp_hold_wait_vector_d1;
output bp_header;
output bp_header_d1;
output bp_header_d2;
output bp_select;
output bp_select_d1;
output bp_select_d2;
input sop3;
input [63:0] sop3_data;
input [5:0] sop3_bpcontext;
input sop2;
input [63:0] sop2_data;
input [5:0] sop2_bpcontext;
input sop1;
input [63:0] sop1_data;
input [5:0] sop1_bpcontext;
input sop0;
input [63:0] sop0_data;
input [5:0] sop0_bpcontext;
input [15:0] poolmask;
input [63:0] bufbusy_mask;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
else
begin
assign encoder_output = {CFG_DATA_WIDTH{1'b0}};
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
module top;
reg pass;
reg in;
reg pout;
wire out;
function invert;
input in;
// When this is a named block the compiler creates a fork/join to
// create the new scope. The problem with this is that of_EXEC_UFUNC
// opcode does not work correctly since the vthread_run(child) call
// returns when the join is executed which then copies the return value
// before the function body code has actually run. This causes the
// results to be delayed by one call. Does this need to be split into
// two functions. One that acts like fork and copies the input values
// and one that acts like join and returns the function result?
// It appears that procedural user function calls work correctly since
// they use fork/join to call the user function.
// Both V0.9 and development have this problem.
begin: block_name
invert = ~in;
$display("Function should return %b when given %b.", invert, in);
end
endfunction
assign out = invert(in);
initial begin
pass = 1'b1;
in = 1'b0;
#1;
if (out !== 1'b1) begin
$display("CA result was %b when given %b, expect 1'b1.", out, in);
pass = 1'b0;
end
pout = invert(in);
if (pout !== 1'b1) begin
$display("Result was %b when given %b, expect 1'b1.", pout, in);
pass = 1'b0;
end
in = 1'b1;
#1;
if (out !== 1'b0) begin
$display("CA result was %b when given %b, expect 1'b0.", out, in);
pass = 1'b0;
end
pout = invert(in);
if (pout !== 1'b0) begin
$display("Result was %b when given %b, expect 1'b0.", pout, in);
pass = 1'b0;
end
in = 1'bz;
#1;
if (out !== 1'bx) begin
$display("CA result was %b when given %b, expect 1'bx.", out, in);
pass = 1'b0;
end
pout = invert(in);
if (pout !== 1'bx) begin
$display("Result was %b when given %b, expect 1'bx.", pout, in);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
|
/*
* Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
module aq_div32x32(
input RST_N,
input CLK,
input [31:0] DINA,
input [31:0] DINB,
output [31:0] DOUT
);
reg [64:0] r00r;
reg [64:0] r01r;
reg [64:0] r02r;
reg [64:0] r03r;
reg [64:0] r04r;
reg [64:0] r05r;
reg [64:0] r06r;
reg [64:0] r07r;
reg [64:0] r08r;
reg [64:0] r09r;
reg [64:0] r10r;
reg [64:0] r11r;
reg [64:0] r12r;
reg [64:0] r13r;
reg [64:0] r14r;
reg [64:0] r15r;
reg [64:0] r16r;
reg [64:0] r17r;
reg [64:0] r18r;
reg [64:0] r19r;
reg [64:0] r20r;
reg [64:0] r21r;
reg [64:0] r22r;
reg [64:0] r23r;
reg [64:0] r24r;
reg [64:0] r25r;
reg [64:0] r26r;
reg [64:0] r27r;
reg [64:0] r28r;
reg [64:0] r29r;
reg [64:0] r30r;
reg [64:0] r31r;
reg [64:0] r32r;
reg [31:0] s00r;
reg [31:0] s01r;
reg [31:0] s02r;
reg [31:0] s03r;
reg [31:0] s04r;
reg [31:0] s05r;
reg [31:0] s06r;
reg [31:0] s07r;
reg [31:0] s08r;
reg [31:0] s09r;
reg [31:0] s10r;
reg [31:0] s11r;
reg [31:0] s12r;
reg [31:0] s13r;
reg [31:0] s14r;
reg [31:0] s15r;
reg [31:0] s16r;
reg [31:0] s17r;
reg [31:0] s18r;
reg [31:0] s19r;
reg [31:0] s20r;
reg [31:0] s21r;
reg [31:0] s22r;
reg [31:0] s23r;
reg [31:0] s24r;
reg [31:0] s25r;
reg [31:0] s26r;
reg [31:0] s27r;
reg [31:0] s28r;
reg [31:0] s29r;
reg [31:0] s30r;
reg [31:0] s31r;
always @(negedge RST_N or posedge CLK) begin
if(!RST_N) begin
r00r <= 65'd0;
r01r <= 65'd0;
r02r <= 65'd0;
r03r <= 65'd0;
r04r <= 65'd0;
r05r <= 65'd0;
r06r <= 65'd0;
r07r <= 65'd0;
r08r <= 65'd0;
r09r <= 65'd0;
r10r <= 65'd0;
r11r <= 65'd0;
r12r <= 65'd0;
r13r <= 65'd0;
r14r <= 65'd0;
r15r <= 65'd0;
r16r <= 65'd0;
r17r <= 65'd0;
r18r <= 65'd0;
r19r <= 65'd0;
r20r <= 65'd0;
r21r <= 65'd0;
r22r <= 65'd0;
r23r <= 65'd0;
r24r <= 65'd0;
r25r <= 65'd0;
r26r <= 65'd0;
r27r <= 65'd0;
r28r <= 65'd0;
r29r <= 65'd0;
r30r <= 65'd0;
r31r <= 65'd0;
r32r <= 65'd0;
s00r <= 32'd0;
s01r <= 32'd0;
s02r <= 32'd0;
s03r <= 32'd0;
s04r <= 32'd0;
s05r <= 32'd0;
s06r <= 32'd0;
s07r <= 32'd0;
s08r <= 32'd0;
s09r <= 32'd0;
s10r <= 32'd0;
s11r <= 32'd0;
s12r <= 32'd0;
s13r <= 32'd0;
s14r <= 32'd0;
s15r <= 32'd0;
s16r <= 32'd0;
s17r <= 32'd0;
s18r <= 32'd0;
s19r <= 32'd0;
s20r <= 32'd0;
s21r <= 32'd0;
s22r <= 32'd0;
s23r <= 32'd0;
s24r <= 32'd0;
s25r <= 32'd0;
s26r <= 32'd0;
s27r <= 32'd0;
s28r <= 32'd0;
s29r <= 32'd0;
s30r <= 32'd0;
s31r <= 32'd0;
end else begin
// Stage: buffer
r00r[64:0] <= {1'b1, 32'd0, DINA};
s00r <= DINB;
// State: 01
r01r[64:31] <= ({1'b1,r00r[63:31]}) + (~{2'b00,s00r}) + 1;
r01r[30:0] <= r00r[30:0] ;
s01r <= s00r;
// State: 02
r02r[63:30] <= ({r01r[64],r01r[62:30]}) + (({34{r01r[64]}}^{2'b00,s01r}) + r01r[64]);
r02r[64:64] <= r01r[64:64] ;
r02r[29:0] <= r01r[29:0] ;
s02r <= s01r;
// State: 03
r03r[62:29] <= ({r02r[63],r02r[61:29]}) + (({34{r02r[63]}}^{2'b00,s02r}) + r02r[63]);
r03r[64:63] <= r02r[64:63] ;
r03r[28:0] <= r02r[28:0] ;
s03r <= s02r;
// State: 04
r04r[61:28] <= ({r03r[62],r03r[60:28]}) + (({34{r03r[62]}}^{2'b00,s03r}) + r03r[62]);
r04r[64:62] <= r03r[64:62] ;
r04r[27:0] <= r03r[27:0] ;
s04r <= s03r;
// State: 05
r05r[60:27] <= ({r04r[61],r04r[59:27]}) + (({34{r04r[61]}}^{2'b00,s04r}) + r04r[61]);
r05r[64:61] <= r04r[64:61] ;
r05r[26:0] <= r04r[26:0] ;
s05r <= s04r;
// State: 06
r06r[59:26] <= ({r05r[60],r05r[58:26]}) + (({34{r05r[60]}}^{2'b00,s05r}) + r05r[60]);
r06r[64:60] <= r05r[64:60] ;
r06r[25:0] <= r05r[25:0] ;
s06r <= s05r;
// State: 07
r07r[58:25] <= ({r06r[59],r06r[57:25]}) + (({34{r06r[59]}}^{2'b00,s06r}) + r06r[59]);
r07r[64:59] <= r06r[64:59] ;
r07r[24:0] <= r06r[24:0] ;
s07r <= s06r;
// State: 08
r08r[57:24] <= ({r07r[58],r07r[56:24]}) + (({34{r07r[58]}}^{2'b00,s07r}) + r07r[58]);
r08r[64:58] <= r07r[64:58] ;
r08r[23:0] <= r07r[23:0] ;
s08r <= s07r;
// State: 09
r09r[56:23] <= ({r08r[57],r08r[55:23]}) + (({34{r08r[57]}}^{2'b00,s08r}) + r08r[57]);
r09r[64:57] <= r08r[64:57] ;
r09r[22:0] <= r08r[22:0] ;
s09r <= s08r;
// State: 10
r10r[55:22] <= ({r09r[56],r09r[54:22]}) + (({34{r09r[56]}}^{2'b00,s09r}) + r09r[56]);
r10r[64:56] <= r09r[64:56] ;
r10r[21:0] <= r09r[21:0] ;
s10r <= s09r;
// State: 11
r11r[54:21] <= ({r10r[55],r10r[53:21]}) + (({34{r10r[55]}}^{2'b00,s10r}) + r10r[55]);
r11r[64:55] <= r10r[64:55] ;
r11r[20:0] <= r10r[20:0] ;
s11r <= s10r;
// State: 12
r12r[53:20] <= ({r11r[54],r11r[52:20]}) + (({34{r11r[54]}}^{2'b00,s11r}) + r11r[54]);
r12r[64:54] <= r11r[64:54] ;
r12r[19:0] <= r11r[19:0] ;
s12r <= s11r;
// State: 13
r13r[52:19] <= ({r12r[53],r12r[51:19]}) + (({34{r12r[53]}}^{2'b00,s12r}) + r12r[53]);
r13r[64:53] <= r12r[64:53] ;
r13r[18:0] <= r12r[18:0] ;
s13r <= s12r;
// State: 14
r14r[51:18] <= ({r13r[52],r13r[50:18]}) + (({34{r13r[52]}}^{2'b00,s13r}) + r13r[52]);
r14r[64:52] <= r13r[64:52] ;
r14r[17:0] <= r13r[17:0] ;
s14r <= s13r;
// State: 15
r15r[50:17] <= ({r14r[51],r14r[49:17]}) + (({34{r14r[51]}}^{2'b00,s14r}) + r14r[51]);
r15r[64:51] <= r14r[64:51] ;
r15r[16:0] <= r14r[16:0] ;
s15r <= s14r;
// State: 16
r16r[49:16] <= ({r15r[50],r15r[48:16]}) + (({34{r15r[50]}}^{2'b00,s15r}) + r15r[50]);
r16r[64:50] <= r15r[64:50] ;
r16r[15:0] <= r15r[15:0] ;
s16r <= s15r;
// State: 17
r17r[48:15] <= ({r16r[49],r16r[47:15]}) + (({34{r16r[49]}}^{2'b00,s16r}) + r16r[49]);
r17r[64:49] <= r16r[64:49] ;
r17r[14:0] <= r16r[14:0] ;
s17r <= s16r;
// State: 18
r18r[47:14] <= ({r17r[48],r17r[46:14]}) + (({34{r17r[48]}}^{2'b00,s17r}) + r17r[48]);
r18r[64:48] <= r17r[64:48] ;
r18r[13:0] <= r17r[13:0] ;
s18r <= s17r;
// State: 19
r19r[46:13] <= ({r18r[47],r18r[45:13]}) + (({34{r18r[47]}}^{2'b00,s18r}) + r18r[47]);
r19r[64:47] <= r18r[64:47] ;
r19r[12:0] <= r18r[12:0] ;
s19r <= s18r;
// State: 20
r20r[45:12] <= ({r19r[46],r19r[44:12]}) + (({34{r19r[46]}}^{2'b00,s19r}) + r19r[46]);
r20r[64:46] <= r19r[64:46] ;
r20r[11:0] <= r19r[11:0] ;
s20r <= s19r;
// State: 21
r21r[44:11] <= ({r20r[45],r20r[43:11]}) + (({34{r20r[45]}}^{2'b00,s20r}) + r20r[45]);
r21r[64:45] <= r20r[64:45] ;
r21r[10:0] <= r20r[10:0] ;
s21r <= s20r;
// State: 22
r22r[43:10] <= ({r21r[44],r21r[42:10]}) + (({34{r21r[44]}}^{2'b00,s21r}) + r21r[44]);
r22r[64:44] <= r21r[64:44] ;
r22r[9:0] <= r21r[9:0] ;
s22r <= s21r;
// State: 23
r23r[42:9] <= ({r22r[43],r22r[41:9]}) + (({34{r22r[43]}}^{2'b00,s22r}) + r22r[43]);
r23r[64:43] <= r22r[64:43] ;
r23r[8:0] <= r22r[8:0] ;
s23r <= s22r;
// State: 24
r24r[41:8] <= ({r23r[42],r23r[40:8]}) + (({34{r23r[42]}}^{2'b00,s23r}) + r23r[42]);
r24r[64:42] <= r23r[64:42] ;
r24r[7:0] <= r23r[7:0] ;
s24r <= s23r;
// State: 25
r25r[40:7] <= ({r24r[41],r24r[39:7]}) + (({34{r24r[41]}}^{2'b00,s24r}) + r24r[41]);
r25r[64:41] <= r24r[64:41] ;
r25r[6:0] <= r24r[6:0] ;
s25r <= s24r;
// State: 26
r26r[39:6] <= ({r25r[40],r25r[38:6]}) + (({34{r25r[40]}}^{2'b00,s25r}) + r25r[40]);
r26r[64:40] <= r25r[64:40] ;
r26r[5:0] <= r25r[5:0] ;
s26r <= s25r;
// State: 27
r27r[38:5] <= ({r26r[39],r26r[37:5]}) + (({34{r26r[39]}}^{2'b00,s26r}) + r26r[39]);
r27r[64:39] <= r26r[64:39] ;
r27r[4:0] <= r26r[4:0] ;
s27r <= s26r;
// State: 28
r28r[37:4] <= ({r27r[38],r27r[36:4]}) + (({34{r27r[38]}}^{2'b00,s27r}) + r27r[38]);
r28r[64:38] <= r27r[64:38] ;
r28r[3:0] <= r27r[3:0] ;
s28r <= s27r;
// State: 29
r29r[36:3] <= ({r28r[37],r28r[35:3]}) + (({34{r28r[37]}}^{2'b00,s28r}) + r28r[37]);
r29r[64:37] <= r28r[64:37] ;
r29r[2:0] <= r28r[2:0] ;
s29r <= s28r;
// State: 30
r30r[35:2] <= ({r29r[36],r29r[34:2]}) + (({34{r29r[36]}}^{2'b00,s29r}) + r29r[36]);
r30r[64:36] <= r29r[64:36] ;
r30r[1:0] <= r29r[1:0] ;
s30r <= s29r;
// State: 31
r31r[34:1] <= ({r30r[35],r30r[33:1]}) + (({34{r30r[35]}}^{2'b00,s30r}) + r30r[35]);
r31r[64:35] <= r30r[64:35] ;
r31r[0:0] <= r30r[0:0] ;
s31r <= s30r;
// State: 32
r32r[33:0] <= ({r31r[34],r31r[32:0]}) + (({34{r31r[34]}}^{2'b00,s31r}) + r31r[34]);
r32r[64:34] <= r31r[64:34] ;
end
end
assign DOUT = r32r[64:33];
endmodule
|
module UpCounter(clock,reset,count,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
data_o <= data_o + 1;
end
end
end
endmodule // UpCounter
module UDCounter(clock,reset,count,direction,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
input wire [('b1) - ('b1):0] direction;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
case (direction)
'b0: data_o <= data_o + 1;
'b1: data_o <= data_o - 1;
endcase
end
end
end
endmodule // UDCounter
module Mux2(select,data_i00,data_i01,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
output reg [(Size) - ('b1):0] data_o;
always @ (select or data_i00 or data_i01) begin
case (select)
'b0:data_o = data_i00;
'b1:data_o = data_i01;
endcase // case (select)
end
endmodule // Mux2
module Mux4(select,data_i00,data_i01,data_i02,data_i03,data_o);
parameter Size = 8;
input wire [('d2) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03) begin
case (select)
'b00: data_o = data_i00;
'b01: data_o = data_i01;
'b10: data_o = data_i02;
'b11: data_o = data_i03;
endcase
end
endmodule // Mux4
module Mux8(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_o);
parameter Size = 8;
input wire [('d3) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07) begin
case (select)
'b000: data_o = data_i00;
'b001: data_o = data_i01;
'b010: data_o = data_i02;
'b011: data_o = data_i03;
'b100: data_o = data_i04;
'b101: data_o = data_i05;
'b110: data_o = data_i06;
'b111: data_o = data_i07;
endcase
end
endmodule // Mux8
module Mux16(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_o);
parameter Size = 8;
input wire [('d4) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15) begin
case (select)
'b0000: data_o = data_i00;
'b0001: data_o = data_i01;
'b0010: data_o = data_i02;
'b0011: data_o = data_i03;
'b0100: data_o = data_i04;
'b0101: data_o = data_i05;
'b0110: data_o = data_i06;
'b0111: data_o = data_i07;
'b1000: data_o = data_i08;
'b1001: data_o = data_i09;
'b1010: data_o = data_i10;
'b1011: data_o = data_i11;
'b1100: data_o = data_i12;
'b1101: data_o = data_i13;
'b1110: data_o = data_i14;
'b1111: data_o = data_i15;
endcase
end
endmodule // Mux16
module Mux32(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_i16,data_i17,data_i18,data_i19,data_i20,data_i21,data_i22,data_i23,data_i24,data_i25,data_i26,data_i27,data_i28,data_i29,data_i30,data_i31,data_o);
parameter Size = 8;
input wire [('d5) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
input wire [(Size) - ('b1):0] data_i16;
input wire [(Size) - ('b1):0] data_i17;
input wire [(Size) - ('b1):0] data_i18;
input wire [(Size) - ('b1):0] data_i19;
input wire [(Size) - ('b1):0] data_i20;
input wire [(Size) - ('b1):0] data_i21;
input wire [(Size) - ('b1):0] data_i22;
input wire [(Size) - ('b1):0] data_i23;
input wire [(Size) - ('b1):0] data_i24;
input wire [(Size) - ('b1):0] data_i25;
input wire [(Size) - ('b1):0] data_i26;
input wire [(Size) - ('b1):0] data_i27;
input wire [(Size) - ('b1):0] data_i28;
input wire [(Size) - ('b1):0] data_i29;
input wire [(Size) - ('b1):0] data_i30;
input wire [(Size) - ('b1):0] data_i31;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15 or
data_i16 or data_i17 or data_i18 or data_i19 or data_i20 or data_i21 or data_i22 or data_i23 or
data_i24 or data_i25 or data_i26 or data_i27 or data_i28 or data_i29 or data_i30 or data_i31) begin
case (select)
'b00000: data_o = data_i00;
'b00001: data_o = data_i01;
'b00010: data_o = data_i02;
'b00011: data_o = data_i03;
'b00100: data_o = data_i04;
'b00101: data_o = data_i05;
'b00110: data_o = data_i06;
'b00111: data_o = data_i07;
'b01000: data_o = data_i08;
'b01001: data_o = data_i09;
'b01010: data_o = data_i10;
'b01011: data_o = data_i11;
'b01100: data_o = data_i12;
'b01101: data_o = data_i13;
'b01110: data_o = data_i14;
'b01111: data_o = data_i15;
'b10000: data_o = data_i16;
'b10001: data_o = data_i17;
'b10010: data_o = data_i18;
'b10011: data_o = data_i19;
'b10100: data_o = data_i20;
'b10101: data_o = data_i21;
'b10110: data_o = data_i22;
'b10111: data_o = data_i23;
'b11000: data_o = data_i24;
'b11001: data_o = data_i25;
'b11010: data_o = data_i26;
'b11011: data_o = data_i27;
'b11100: data_o = data_i28;
'b11101: data_o = data_i29;
'b11110: data_o = data_i30;
'b11111: data_o = data_i31;
endcase
end
endmodule // Mux32
module Reg(clock,reset,data_i,writeEn,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] clock;
input wire [('d1) - ('b1):0] reset;
input wire [(Size) - ('b1):0] data_i;
input wire [('d1) - ('b1):0] writeEn;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (writeEn) begin
data_o <= data_i;
end
end
end
endmodule // Reg
module FPGADCM(clock,reset,locked,clock_o0,clock_o90,clock_o180,clock_o270,clock_o2x,clock_o2x180);
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
output wire [('b1) - ('b1):0] locked;
output wire [('b1) - ('b1):0] clock_o0;
output wire [('b1) - ('b1):0] clock_o90;
output wire [('b1) - ('b1):0] clock_o180;
output wire [('b1) - ('b1):0] clock_o270;
output wire [('b1) - ('b1):0] clock_o2x;
output wire [('b1) - ('b1):0] clock_o2x180;
wire FPGABUFG_o;
wire FPGASPDCM_CLK0;
assign clock_o0 = FPGASPDCM_CLK0;
DCM_SP #(.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(0.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE"))
FPGASPDCM (.CLKIN(clock),
.CLKFB(FPGABUFG_o),
.RST(reset),
.DSSEN(0),
.PSINCDEC(0),
.PSEN(0),
.PSCLK(0),
.LOCKED(locked),
.CLK0(FPGASPDCM_CLK0),
.CLK90(clock_o90),
.CLK180(clock_o180),
.CLK270(clock_o270),
.CLK2X(clock_o2x),
.CLK2X180(clock_o2x180));
BUFG
FPGABUFG (.I(FPGASPDCM_CLK0),
.O(FPGABUFG_o));
endmodule // DCM
module VGAVideo(
input wire [('b1) - ('b1):0] clock,
input wire [('b1) - ('b1):0] reset,
output wire [('b1) - ('b1):0] vga_r,
output wire [('b1) - ('b1):0] vga_g,
output wire [('b1) - ('b1):0] vga_b,
output wire [('b1) - ('b1):0] vga_hsync,
output wire [('b1) - ('b1):0] vga_vsync);
parameter hack_hcounter_Size = 'b1011;
parameter hack_vcounter_Size = 'b1010;
wire [(hack_hcounter_Size) - ('b1):0] hcounter_data_o;
wire [(hack_vcounter_Size) - ('b1):0] vcounter_data_o;
assign vga_r = 'b1;
assign vga_g = 'b0;
assign vga_b = 'b0;
assign vga_hsync = (hcounter_data_o['b1010:'b101] == 'b0);
assign vga_vsync = (vcounter_data_o == 'b0);
UpCounter #(
.Size('b1011))
hcounter(
.clock(clock),
.reset((hcounter_data_o == 'b1011111111)),
.count('b1),
.data_o(hcounter_data_o));
UpCounter #(
.Size('b1010))
vcounter(
.clock(clock),
.reset('b0),
.count('b1),
.data_o(vcounter_data_o));
endmodule // VGAVideo
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_BEHAVIORAL_V
`define SKY130_FD_SC_LP__XOR3_BEHAVIORAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_BEHAVIORAL_V |
`default_nettype none
module romtest2 (
input wire sysclk,
input wire clk,
input wire rst,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
wire [7:0] dout;
reg [3:0] addr;
//-- Instanciar la memoria rom
rom16x8
ROM (
.clk(sysclk),
.addr(addr),
.data(dout)
);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(clk),
.D_IN_0(clk2)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(rst),
.D_IN_0(rst2)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign rst_in = ~rst2;
assign sw = ~clk2;
debounce deb1 (
.clk(sysclk),
.sw_in(sw),
.sw_out(clk_in)
);
//-- Counter for incrementing the address
always @(posedge clk_in or posedge rst_in) begin
if (rst_in==1'b1)
addr <= 4'b0;
else
addr <= addr + 1;
end
assign {d7,d6,d5,d4,d3,d2,d1,d0} = dout;
endmodule
module rom16x8 (input clk,
input wire [3:0] addr,
output reg [7:0] data);
//-- Name of the file with the rom contents
parameter ROMFILE = "rom2.list";
//-- Memoria
reg [7:0] rom [0:15];
always @(negedge clk) begin
data <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
//////////////////////////////////////////////////////////////////////////////////
// SCFIFO_64x64_withCount for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Single clock FIFO (64 width, 64 depth) wrapper
// Module Name: SCFIFO_64x64_withCount
// File Name: SCFIFO_64x64_withCount.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module SCFIFO_64x64_withCount
(
input iClock ,
input iReset ,
input [63:0] iPushData ,
input iPushEnable ,
output oIsFull ,
output [63:0] oPopData ,
input iPopEnable ,
output oIsEmpty ,
output [5:0] oDataCount
);
DPBSCFIFO64x64WC
Inst_DPBSCFIFO64x64WC
(
.clk (iClock ),
.srst (iReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty ),
.data_count (oDataCount )
);
endmodule
|
`define ADDER_WIDTH 128
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [32 - 1 : 0] a;
input [32 - 1 : 0] b;
output [32 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [32 - 1 : 0] a_reg;
wire [32 - 1 : 0] b_reg;
// wires for each small adder
wire [4 - 1 : 0] a0_cb;
wire [4 - 1 : 0] b0_cb;
wire [8 - 1 : 4] a1_cb;
wire [8 - 1 : 4] b1_cb;
wire [12 - 1 : 8] a2_cb;
wire [12 - 1 : 8] b2_cb;
wire [16 - 1 : 12] a3_cb;
wire [16 - 1 : 12] b3_cb;
wire [20 - 1 : 16] a4_cb;
wire [20 - 1 : 16] b4_cb;
wire [24 - 1 : 20] a5_cb;
wire [24 - 1 : 20] b5_cb;
wire [28 - 1 : 24] a6_cb;
wire [28 - 1 : 24] b6_cb;
wire [32 - 1 : 28] a7_cb;
wire [32 - 1 : 28] b7_cb;
// registers for input register array
reg [4 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [4 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
reg [4 - 1 : 0] a4_cb_regi4[4 - 1 : 0];
reg [4 - 1 : 0] b4_cb_regi4[4 - 1 : 0];
reg [4 - 1 : 0] a5_cb_regi5[5 - 1 : 0];
reg [4 - 1 : 0] b5_cb_regi5[5 - 1 : 0];
reg [4 - 1 : 0] a6_cb_regi6[6 - 1 : 0];
reg [4 - 1 : 0] b6_cb_regi6[6 - 1 : 0];
reg [4 - 1 : 0] a7_cb_regi7[7 - 1 : 0];
reg [4 - 1 : 0] b7_cb_regi7[7 - 1 : 0];
// wires for each full adder sum
wire [32 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
wire faccout4_co4;
wire faccout5_co5;
wire faccout6_co6;
wire faccout7_co7;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
reg faccout3_co3_reg;
reg faccout4_co4_reg;
reg faccout5_co5_reg;
reg faccout6_co6_reg;
// registers for output register array
reg [4 - 1 : 0] s0_ca_rego0[6 - 0 : 0];
reg [4 - 1 : 0] s1_ca_rego1[6 - 1 : 0];
reg [4 - 1 : 0] s2_ca_rego2[6 - 2 : 0];
reg [4 - 1 : 0] s3_ca_rego3[6 - 3 : 0];
reg [4 - 1 : 0] s4_ca_rego4[6 - 4 : 0];
reg [4 - 1 : 0] s5_ca_rego5[6 - 5 : 0];
reg [4 - 1 : 0] s6_ca_rego6[6 - 6 : 0];
// wire for the temporary output
wire [32 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[4 - 1 : 0];
assign b0_cb = b_reg[4 - 1 : 0];
assign a1_cb = a_reg[8 - 1 : 4];
assign b1_cb = b_reg[8 - 1 : 4];
assign a2_cb = a_reg[12 - 1 : 8];
assign b2_cb = b_reg[12 - 1 : 8];
assign a3_cb = a_reg[16 - 1 : 12];
assign b3_cb = b_reg[16 - 1 : 12];
assign a4_cb = a_reg[20 - 1 : 16];
assign b4_cb = b_reg[20 - 1 : 16];
assign a5_cb = a_reg[24 - 1 : 20];
assign b5_cb = b_reg[24 - 1 : 20];
assign a6_cb = a_reg[28 - 1 : 24];
assign b6_cb = b_reg[28 - 1 : 24];
assign a7_cb = a_reg[32 - 1 : 28];
assign b7_cb = b_reg[32 - 1 : 28];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a4_cb_regi4 [0] <= a4_cb;
b4_cb_regi4 [0] <= b4_cb;
a5_cb_regi5 [0] <= a5_cb;
b5_cb_regi5 [0] <= b5_cb;
a6_cb_regi6 [0] <= a6_cb;
b6_cb_regi6 [0] <= b6_cb;
a7_cb_regi7 [0] <= a7_cb;
b7_cb_regi7 [0] <= b7_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a4_cb_regi4 [1] <= a4_cb_regi4 [0];
b4_cb_regi4 [1] <= b4_cb_regi4 [0];
a5_cb_regi5 [1] <= a5_cb_regi5 [0];
b5_cb_regi5 [1] <= b5_cb_regi5 [0];
a6_cb_regi6 [1] <= a6_cb_regi6 [0];
b6_cb_regi6 [1] <= b6_cb_regi6 [0];
a7_cb_regi7 [1] <= a7_cb_regi7 [0];
b7_cb_regi7 [1] <= b7_cb_regi7 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
a4_cb_regi4 [2] <= a4_cb_regi4 [1];
b4_cb_regi4 [2] <= b4_cb_regi4 [1];
a5_cb_regi5 [2] <= a5_cb_regi5 [1];
b5_cb_regi5 [2] <= b5_cb_regi5 [1];
a6_cb_regi6 [2] <= a6_cb_regi6 [1];
b6_cb_regi6 [2] <= b6_cb_regi6 [1];
a7_cb_regi7 [2] <= a7_cb_regi7 [1];
b7_cb_regi7 [2] <= b7_cb_regi7 [1];
a4_cb_regi4 [3] <= a4_cb_regi4 [2];
b4_cb_regi4 [3] <= b4_cb_regi4 [2];
a5_cb_regi5 [3] <= a5_cb_regi5 [2];
b5_cb_regi5 [3] <= b5_cb_regi5 [2];
a6_cb_regi6 [3] <= a6_cb_regi6 [2];
b6_cb_regi6 [3] <= b6_cb_regi6 [2];
a7_cb_regi7 [3] <= a7_cb_regi7 [2];
b7_cb_regi7 [3] <= b7_cb_regi7 [2];
a5_cb_regi5 [4] <= a5_cb_regi5 [3];
b5_cb_regi5 [4] <= b5_cb_regi5 [3];
a6_cb_regi6 [4] <= a6_cb_regi6 [3];
b6_cb_regi6 [4] <= b6_cb_regi6 [3];
a7_cb_regi7 [4] <= a7_cb_regi7 [3];
b7_cb_regi7 [4] <= b7_cb_regi7 [3];
a6_cb_regi6 [5] <= a6_cb_regi6 [4];
b6_cb_regi6 [5] <= b6_cb_regi6 [4];
a7_cb_regi7 [5] <= a7_cb_regi7 [4];
b7_cb_regi7 [5] <= b7_cb_regi7 [4];
a7_cb_regi7 [6] <= a7_cb_regi7 [5];
b7_cb_regi7 [6] <= b7_cb_regi7 [5];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
faccout3_co3_reg <= faccout3_co3;
faccout4_co4_reg <= faccout4_co4;
faccout5_co5_reg <= faccout5_co5;
faccout6_co6_reg <= faccout6_co6;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[3:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[7:4] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[11:8] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg),
.fas ( fas[15:12] ),
.facout ( faccout3_co3 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u4 (
.faa ( a4_cb_regi4[3] ),
.fab ( b4_cb_regi4[3] ),
.facin ( faccout3_co3_reg),
.fas ( fas[19:16] ),
.facout ( faccout4_co4 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u5 (
.faa ( a5_cb_regi5[4] ),
.fab ( b5_cb_regi5[4] ),
.facin ( faccout4_co4_reg),
.fas ( fas[23:20] ),
.facout ( faccout5_co5 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder u6 (
.faa ( a6_cb_regi6[5] ),
.fab ( b6_cb_regi6[5] ),
.facin ( faccout5_co5_reg),
.fas ( fas[27:24] ),
.facout ( faccout6_co6 )
);
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f u7 (
.faa ( a7_cb_regi7[6] ),
.fab ( b7_cb_regi7[6] ),
.facin ( faccout6_co6_reg ),
.fas ( fas[31 :28] ),
.facout ( faccout7_co7 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[4-1 : 0];
s1_ca_rego1 [0] <= fas[8-1 : 4];
s2_ca_rego2 [0] <= fas[12-1 : 8];
s3_ca_rego3 [0] <= fas[16-1 : 12];
s4_ca_rego4 [0] <= fas[20-1 : 16];
s5_ca_rego5 [0] <= fas[24-1 : 20];
s6_ca_rego6 [0] <= fas[28-1 : 24];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s0_ca_rego0 [3] <= s0_ca_rego0 [2];
s0_ca_rego0 [4] <= s0_ca_rego0 [3];
s0_ca_rego0 [5] <= s0_ca_rego0 [4];
s0_ca_rego0 [6] <= s0_ca_rego0 [5];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
s1_ca_rego1 [2] <= s1_ca_rego1 [1];
s1_ca_rego1 [3] <= s1_ca_rego1 [2];
s1_ca_rego1 [4] <= s1_ca_rego1 [3];
s1_ca_rego1 [5] <= s1_ca_rego1 [4];
s2_ca_rego2 [1] <= s2_ca_rego2 [0];
s2_ca_rego2 [2] <= s2_ca_rego2 [1];
s2_ca_rego2 [3] <= s2_ca_rego2 [2];
s2_ca_rego2 [4] <= s2_ca_rego2 [3];
s3_ca_rego3 [1] <= s3_ca_rego3 [0];
s3_ca_rego3 [2] <= s3_ca_rego3 [1];
s3_ca_rego3 [3] <= s3_ca_rego3 [2];
s4_ca_rego4 [1] <= s4_ca_rego4 [0];
s4_ca_rego4 [2] <= s4_ca_rego4 [1];
s5_ca_rego5 [1] <= s5_ca_rego5 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[4-1 : 0] = s0_ca_rego0[6];
assign s_tmp[8-1 : 4] = s1_ca_rego1[5];
assign s_tmp[12-1 : 8] = s2_ca_rego2[4];
assign s_tmp[16-1 : 12] = s3_ca_rego3[3];
assign s_tmp[20-1 : 16] = s4_ca_rego4[2];
assign s_tmp[24-1 : 20] = s5_ca_rego5[1];
assign s_tmp[28-1 : 24] = s6_ca_rego6[0];
assign s_tmp[32 - 1 : 28] = fas[31 :28];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_fadder_f
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_32ns_32s_32_8(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1 nfa_accept_samples_generic_hw_add_32ns_32s_32_8_AddSubnS_1_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's instruction fetch ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PC, instruction fetch, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_if(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
// Internal i/f
if_freeze, if_insn, if_pc, flushpipe,
if_stall, no_more_dslot, genpc_refetch, rfe,
except_itlbmiss, except_immufault, except_ibuserr
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Internal i/f
//
input if_freeze;
output [31:0] if_insn;
output [31:0] if_pc;
input flushpipe;
output if_stall;
input no_more_dslot;
output genpc_refetch;
input rfe;
output except_itlbmiss;
output except_immufault;
output except_ibuserr;
//
// Internal wires and regs
//
reg [31:0] insn_saved;
reg [31:0] addr_saved;
reg saved;
//
// IF stage insn
//
assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
if (rst)
saved <= #1 1'b0;
else if (flushpipe)
saved <= #1 1'b0;
else if (icpu_ack_i & if_freeze & !saved)
saved <= #1 1'b1;
else if (!if_freeze)
saved <= #1 1'b0;
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
if (rst)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (icpu_ack_i & if_freeze & !saved)
insn_saved <= #1 icpu_dat_i;
else if (!if_freeze)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
if (rst)
addr_saved <= #1 32'h00000000;
else if (flushpipe)
addr_saved <= #1 32'h00000000;
else if (icpu_ack_i & if_freeze & !saved)
addr_saved <= #1 icpu_adr_i;
else if (!if_freeze)
addr_saved <= #1 icpu_adr_i;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_alu(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input ifb,
input [3:0] opcode,
output [31:0] r,
output r_valid,
output reg dma_en,
output err_collision
);
/* Compensate for the latency cycle of the register file SRAM. */
reg [3:0] opcode_r;
always @(posedge sys_clk) begin
if(alu_rst)
opcode_r <= 4'd0;
else
opcode_r <= opcode;
end
/* Detect VECTOUT opcodes and trigger DMA */
always @(posedge sys_clk) begin
if(alu_rst)
dma_en <= 1'b0;
else
dma_en <= opcode == 4'h7;
end
/* Computation units */
wire faddsub_valid;
wire [31:0] r_faddsub;
pfpu_faddsub u_faddsub(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.sub(~opcode_r[0]),
.valid_i((opcode_r == 4'h1) | (opcode_r == 4'h2)),
.r(r_faddsub),
.valid_o(faddsub_valid)
);
wire fmul_valid;
wire [31:0] r_fmul;
pfpu_fmul u_fmul(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.valid_i(opcode_r == 4'h3),
.r(r_fmul),
.valid_o(fmul_valid)
);
wire tsign_valid;
wire [31:0] r_tsign;
pfpu_tsign u_tsign(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.tsign(opcode_r[3]),
.valid_i((opcode_r == 4'h4) | (opcode_r == 4'he)),
.r(r_tsign),
.valid_o(tsign_valid)
);
wire f2i_valid;
wire [31:0] r_f2i;
pfpu_f2i u_f2i(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'h5),
.r(r_f2i),
.valid_o(f2i_valid)
);
wire i2f_valid;
wire [31:0] r_i2f;
pfpu_i2f u_i2f(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'h6),
.r(r_i2f),
.valid_o(i2f_valid)
);
wire sincos_valid;
wire [31:0] r_sincos;
pfpu_sincos u_sincos(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.cos(opcode_r[0]),
.valid_i((opcode_r == 4'h8) | (opcode_r == 4'h9)),
.r(r_sincos),
.valid_o(sincos_valid)
);
wire above_valid;
wire [31:0] r_above;
pfpu_above u_above(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.valid_i(opcode_r == 4'ha),
.r(r_above),
.valid_o(above_valid)
);
wire equal_valid;
wire [31:0] r_equal;
pfpu_equal u_equal(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.valid_i(opcode_r == 4'hb),
.r(r_equal),
.valid_o(equal_valid)
);
wire copy_valid;
wire [31:0] r_copy;
pfpu_copy u_copy(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'hc),
.r(r_copy),
.valid_o(copy_valid)
);
wire if_valid;
wire [31:0] r_if;
pfpu_if u_if(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.ifb(ifb),
.valid_i(opcode_r == 4'hd),
.r(r_if),
.valid_o(if_valid)
);
wire quake_valid;
wire [31:0] r_quake;
pfpu_quake u_quake(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'hf),
.r(r_quake),
.valid_o(quake_valid)
);
/* Generate output */
assign r =
({32{faddsub_valid}} & r_faddsub)
|({32{fmul_valid}} & r_fmul)
|({32{tsign_valid}} & r_tsign)
|({32{f2i_valid}} & r_f2i)
|({32{i2f_valid}} & r_i2f)
|({32{sincos_valid}} & r_sincos)
|({32{above_valid}} & r_above)
|({32{equal_valid}} & r_equal)
|({32{copy_valid}} & r_copy)
|({32{if_valid}} & r_if)
|({32{quake_valid}} & r_quake);
assign r_valid =
faddsub_valid
|fmul_valid
|tsign_valid
|f2i_valid
|i2f_valid
|sincos_valid
|above_valid
|equal_valid
|copy_valid
|if_valid
|quake_valid;
assign err_collision =
(faddsub_valid & (fmul_valid|tsign_valid|f2i_valid|i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(fmul_valid & (tsign_valid|f2i_valid|i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(tsign_valid & (f2i_valid|i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(f2i_valid & (i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(i2f_valid & (sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(sincos_valid & (above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(above_valid & (equal_valid|copy_valid|if_valid|quake_valid))
|(equal_valid & (copy_valid|if_valid|quake_valid))
|(copy_valid & (if_valid|quake_valid))
|(if_valid & (quake_valid));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_SYMBOL_V
`define SKY130_FD_SC_LP__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async reset, enable
module \$_DFFE_PP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
// Async set, enable
module \$_DFFE_PP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
// Async set & reset
module \$_DFFSR_PPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
// Async set, reset & enable
module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
// Latch with async set and reset
module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(R), .S(S));
endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
module \$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
module \$_DFFE_NP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
module \$_DFFSR_NPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \$_DFFSRE_PPPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
|
// Modulo sencillo que permite determinar la dirección en la que se mueven los motores
// En 0 los motores van hacia adelante, en 1 van hacia atras. Están determinados de manera independiente
// para permitir el giro
module peripheral_uart (
// Propias del periferico
input clk,
input rst,
input [15:0] d_in, // Dato de entrada
input cs, //
input [3:0] addr, // 4 LSB from j1_io_addr
input rd, // Leer
input wr, // Escribir
output reg [15:0] d_out, // Dato de salida
// Otras entradas y salidas
output [1:0] adelante ,
output [1:0] atras
);
//------------------------------------ regs and wires-------------------------------
reg [1:0] s; // Selector
reg [1:0] reversa;
//------------------------------------ regs and wires-------------------------------
always @(*) begin // Selector
case(addr)
4'h0: s = (cs && wr) ? 2'b01 : 2'b00 ; // Dirección motor 1;
4'h2: s = (cs && wr) ? 2'b10 : 2'b00 ; // Dirección motor 2;
default: s = 2'b00 ;
endcase
end
always @(negedge clk) begin // Multiplexa entradas al periferico
case (s)
2'b01: reversa[0] = d_in[0] ;
2'b10: reversa[1] = d_in[0] ;
default: begin
reversa[0] = 0 ;
reversa[1] = 0 ;
end
endcase
end
direccion direccion1 ( .reversa(reversa[0]) , .adelante(adelante[0]) , .atras(atras[0]) ) ;
direccion direccion2 ( .reversa(reversa[1]) , .adelante(adelante[1]) , .atras(atras[1]) ) ;
endmodule
|
module image_processor (
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
input iHSync,
input iVSync,
input iLineValid,
input iFrameValid,
input iClk,
input iRst,
input [23:0] iDebug,
output [7:0] oR,
output [7:0] oG,
output [7:0] oB,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid,
output [23:0] oDebug
);
/************************************************
* Debug SW[4:3]
***********************************************/
reg [23:0] rDebugFPS = 0;
reg [23:0] rFPS = 0;
reg [32:0] rTime = 0;
reg [23:0] rDebugRes = 0;
reg [23:0] rWidth = 0;
reg [23:0] rHeight = 0;
reg rLineValidL = 0;
reg rFrameValidL = 0;
always@(posedge iClk)
begin
rTime <= rTime + 1;
if({rFrameValidL,iFrameValid} == 2'b10) rFPS <= rFPS + 1;
case({rLineValidL,iLineValid})
2'b10: rDebugRes[23:12] <= rWidth[11:0];
2'b00: rWidth <= 0;
2'b01: rWidth <= 0;
2'b11: rWidth <= rWidth + 1;
endcase
rLineValidL <= iLineValid;
case({rFrameValidL,iFrameValid})
2'b10: rDebugRes[11:0] <= rHeight[11:0];
2'b00: rHeight <= 0;
2'b01: rHeight <= 0;
2'b11: if({rLineValidL,iLineValid} == 2'b10) rHeight <= rHeight + 1;
endcase
rFrameValidL <= iFrameValid;
if(rTime == 25000000)
begin
rTime <= 0;
rDebugFPS <= rFPS;
rFPS <= 0;
end
end
/************************************************
* Option mux SW[2:0]
***********************************************/
wire [7:0] wRMux [7:0];
wire [7:0] wGMux [7:0];
wire [7:0] wBMux [7:0];
wire [23:0] wDebugMux [7:0];
wire wHSync [7:0];
wire wVSync [7:0];
wire wLineValid [7:0];
wire wFrameValid [7:0];
/************************************************
* Debug mux
***********************************************/
wire [23:0] wDebugMuxSw [2:0];
//Option 0
assign wDebugMuxSw[0] = rDebugRes;
//Option 1
assign wDebugMuxSw[1] = rDebugFPS;
//Option 2
assign wDebugMuxSw[2] = wDebugMux[iDebug[2:0]];
//Option 0
assign wRMux[0] = iR;
assign wGMux[0] = iG;
assign wBMux[0] = iB;
assign wHSync[0] = iHSync;
assign wVSync[0] = iVSync;
assign wLineValid[0] = iLineValid;
assign wFrameValid[0] = iFrameValid;
assign wDebugMux[0] = 1;
//Option 1
assign wRMux[1] = iR;
assign wGMux[1] = iG;
assign wBMux[1] = iB;
assign wHSync[1] = iHSync;
assign wVSync[1] = iVSync;
assign wLineValid[1] = iLineValid;
assign wFrameValid[1] = iFrameValid;
assign wDebugMux[1] = 1;
//Option 2
assign wRMux[2] = iR;
assign wGMux[2] = iG;
assign wBMux[2] = iB;
assign wHSync[2] = iHSync;
assign wVSync[2] = iVSync;
assign wLineValid[2] = iLineValid;
assign wFrameValid[2] = iFrameValid;
assign wDebugMux[2] = 2;
//Option 3
assign wRMux[3] = iR;
assign wGMux[3] = iG;
assign wBMux[3] = iB;
assign wHSync[3] = iHSync;
assign wVSync[3] = iVSync;
assign wLineValid[3] = iLineValid;
assign wFrameValid[3] = iFrameValid;
assign wDebugMux[3] = 3;
//Option 4
assign wRMux[4] = iR;
assign wGMux[4] = iG;
assign wBMux[4] = iB;
assign wHSync[4] = iHSync;
assign wVSync[4] = iVSync;
assign wLineValid[4] = iLineValid;
assign wFrameValid[4] = iFrameValid;
assign wDebugMux[4] = 4;
//Option 5
assign wRMux[5] = iR;
assign wGMux[5] = iG;
assign wBMux[5] = iB;
assign wHSync[5] = iHSync;
assign wVSync[5] = iVSync;
assign wLineValid[5] = iLineValid;
assign wFrameValid[5] = iFrameValid;
assign wDebugMux[5] = 5;
//Option 6
assign wRMux[6] = iR;
assign wGMux[6] = iG;
assign wBMux[6] = iB;
assign wHSync[6] = iHSync;
assign wVSync[6] = iVSync;
assign wLineValid[6] = iLineValid;
assign wFrameValid[6] = iFrameValid;
assign wDebugMux[6] = 6;
//Option 7
assign wRMux[7] = 0;
assign wGMux[7] = 0;
assign wBMux[7] = 0;
assign wHSync[7] = iHSync;
assign wVSync[7] = iVSync;
assign wLineValid[7] = iLineValid;
assign wFrameValid[7] = iFrameValid;
assign wDebugMux[7] = 7;
//Mux connect
assign oR = wRMux[iDebug[2:0]];
assign oG = wGMux[iDebug[2:0]];
assign oB = wBMux[iDebug[2:0]];
assign oDebug = wDebugMuxSw[iDebug[4:3]];
assign oHSync = wHSync[iDebug[2:0]];
assign oVSync = wVSync[iDebug[2:0]];
assign oLineValid = wLineValid[iDebug[2:0]];
assign oFrameValid = wFrameValid[iDebug[2:0]];
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N16_M4_P4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N16_M4_P4(
input [15:0] in1,
input [15:0] in2,
output [16:0] res
);
wire [4:0] temp1, temp2, temp3, temp4;
//C4
wire g0,g1,g2,g3,p0,p1,p2,p3;
wire p3g2,p3p2,p3p2g1,p3p2p1,p3p2p1g0;
wire res_or_1, res_or_2;
wire c4;
and and_3(g3,in1[3],in2[3]);
and and_2(g2,in1[2],in2[2]);
and and_1(g1,in1[1],in2[1]);
and and_0(g0,in1[0],in2[0]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_0(p0,in1[0],in2[0]);
and and_4(p3g2,p3,g2);
and and_5(p3p2,p3,p2);
and and_6(p3p2g1,p3p2,g1);
and and_7(p3p2p1,p3p2,p1);
and and_8(p3p2p1g0,p3p2p1,g0);
or or_3(res_or_1,g3,p3g2);
or or_2(res_or_2,p3p2g1,p3p2p1g0);
or or_1(c4,res_or_1,res_or_2);
//C8
wire g4,g5,g6,g7,p4,p5,p6,p7;
wire p7g6,p7p6,p7p6g5,p7p6p5,p7p6p5g4;
wire res_or_3, res_or_4;
wire c8;
and and_9 (g7,in1[7],in2[7]);
and and_10(g6,in1[6],in2[6]);
and and_11(g5,in1[5],in2[5]);
and and_12(g4,in1[4],in2[4]);
xor xor_7(p7,in1[7],in2[7]);
xor xor_6(p6,in1[6],in2[6]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_4(p4,in1[4],in2[4]);
and and_13(p7g6,p7,g6);
and and_14(p7p6,p7,p6);
and and_15(p7p6g5,p7p6,g5);
and and_16(p7p6p5,p7p6,p5);
and and_17(p7p6p5g4,p7p6p5,g4);
or or_6(res_or_3,g7,p7g6);
or or_5(res_or_4,p7p6g5,p7p6p5g4);
or or_4(c8,res_or_3,res_or_4);
//C12
wire g8,g9,g10,g11,p8,p9,p10,p11;
wire p11g10,p11p10,p11p10g9,p11p10p9;
wire res_or_5, res_or_6;
wire c12;
and and_18(g11,in1[11],in2[11]);
and and_19(g10,in1[10],in2[10]);
and and_20(g9,in1[9],in2[9]);
and and_21(g8,in1[8],in2[8]);
xor xor_11(p11,in1[11],in2[11]);
xor xor_10(p10,in1[10],in2[10]);
xor xor_9(p9,in1[9],in2[9]);
xor xor_8(p8,in1[8],in2[8]);
and and_22(p11g10,p11,g10);
and and_23(p11p10,p11,p10);
and and_24(p11p10g9,p11p10,g9);
and and_25(p11p10p9,p11p10,p9);
and and_26(p11p10p9g8,p11p10p9,g8);
or or_9(res_or_5,g11,p11g10);
or or_8(res_or_6,p11p10g9,p11p10p9g8);
or or_7(c12,res_or_5,res_or_6);
// Results
assign temp1[4:0] = in1[ 3: 0] + in2[ 3: 0];
assign temp2[4:0] = in1[ 7: 4] + in2[ 7: 4] + c4;
assign temp3[4:0] = in1[11: 8] + in2[11: 8] + c8;
assign temp4[4:0] = in1[15:12] + in2[15:12] + c12;
assign res[16:0] = {temp4[4:0],temp3[3:0],temp2[3:0],temp1[3:0]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg [40:0] quad; initial quad = 41'ha_bbbb_cccc;
reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678;
reg [31:0] str; initial str = "\000\277\021\n";
reg [47:0] str2; initial str2 = "\000what!";
reg [79:0] str3; initial str3 = "\000hmmm!1234";
reg [8:0] nine;
sub sub ();
sub2 sub2 ();
initial begin
$write("[%0t] In %m: Hi\n", $time);
sub.write_m;
sub2.write_m;
// Escapes
$display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line.
// Display formatting
nine = {3'd0,quad[5:0]};
$display("[%0t] %%X=%X %%0X=%0X %%0O=%0O %%B=%B", $time,
nine, nine, nine, nine);
$display("[%0t] %%x=%x %%0x=%0x %%0o=%0o %%b=%b", $time,
nine, nine, nine, nine);
$display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time,
nine, nine, nine, nine, nine);
$display("[%0t] %%x=%x %%0x=%0x %%o=%o %%b=%b", $time,
quad, quad, quad, quad);
$display("[%0t] %%x=%x %%0x=%0x %%o=%o %%b=%b", $time,
wide, wide, wide, wide);
$display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time,
$time, $time, $time);
$display;
// Not testing %0s, it does different things in different simulators
$display("[%0t] %%s=%s %%s=%s %%s=%s", $time,
str2[7:0], str2, str3);
$display("[%0t] %s%s%s", $time,
"hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
$write("[%0t] Embedded \r return\n", $time);
$display("[%0t] Embedded\
multiline", $time);
// Str check
`ifndef NC // NC-Verilog 5.3 chokes on this test
if (str !== 32'h00_bf_11_0a) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub;
task write_m;
begin
$write("[%0t] In %m\n", $time);
begin : subblock
$write("[%0t] In %M\n", $time); // Uppercase %M test
end
end
endtask
endmodule
module sub2;
// verilator no_inline_module
task write_m;
begin
$write("[%0t] In %m\n", $time);
begin : subblock2
$write("[%0t] In %m\n", $time);
end
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] l;
reg [49:0] q;
reg [79:0] w;
reg [4:0] lc;
reg lo;
reg l0;
reg [5:0] qc;
reg qo;
reg q0;
reg [6:0] wc;
reg wo;
reg w0;
always @* begin
lc = $countones(l);
lo = $onehot(l);
l0 = $onehot0(l);
wc = $countones(w);
wo = $onehot(w);
w0 = $onehot0(w);
qc = $countones(q);
qo = $onehot(q);
q0 = $onehot0(q);
end
integer cyc; initial cyc=1;
integer cyc_com;
always_comb begin
cyc_com = cyc;
end
integer cyc_d1;
always_ff @ (posedge clk) begin
cyc_d1 <= cyc_com;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n",
// cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0);
if (cyc_com != cyc_com) $stop;
if (cyc_d1 != cyc-1) $stop;
if (cyc==0) begin
// Constification check
if ($countones(32'b11001011101) != 7) $stop;
if ($countones(32'b0) != 0) $stop;
if ($isunknown(32'b11101x11111) != 1) $stop;
if ($isunknown(32'b11101011111) != 0) $stop;
if ($isunknown(32'b10zzzzzzzzz) != 0) $stop;
if ($bits(0) != 32'd32) $stop;
if ($bits(lc) != 5) $stop;
if ($onehot(32'b00000001000000) != 1'b1) $stop;
if ($onehot(32'b00001001000000) != 1'b0) $stop;
if ($onehot(32'b0) != 1'b0) $stop;
if ($onehot0(32'b00000001000000) != 1'b1) $stop;
if ($onehot0(32'b00001001000000) != 1'b0) $stop;
if ($onehot0(32'b0) != 1'b1) $stop;
end
if (cyc==1) begin
l <= 16'b0;
q <= 50'h0;
w <= 80'h0;
end
if (cyc==2) begin
l <= ~16'b0;
q <= ~50'h0;
w <= ~80'h0;
//
if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
end
if (cyc==3) begin
l <= 16'b0010110010110111;
q <= 50'h01_1111_0001;
w <= 80'h0100_0000_0f00_00f0_0000;
//
if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
end
if (cyc==4) begin
l <= 16'b0000010000000000;
q <= 50'h1_0000_0000;
w <= 80'h010_00000000_00000000;
//
if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
end
if (cyc==5) begin
l <= 16'b0000000100000000;
q <= 50'h8000_0000_0000;
w <= 80'h10_00000000_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==6) begin
l <= 16'b0000100100000000;
q <= 50'h01_00000100;
w <= 80'h01_00000100_00000000;
//
if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
end
if (cyc==7) begin
//
if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
end
if (cyc==8) begin
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
final begin
$write("Goodbye world, at cycle %0d\n", cyc);
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:33:05 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_16_stub.v
// Design : mul8_16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[7:0],B[15:0],P[15:0]" */;
input CLK;
input [7:0]A;
input [15:0]B;
output [15:0]P;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_BLACKBOX_V
`define SKY130_FD_SC_LP__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_BLACKBOX_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_optimized_clz_27(dataa, result);
// count the number of leading zeros in the 27-bit mantissa
input [31:0] dataa;
output [31:0] result;
wire all_zero;
acl_fp_custom_clz myclz( .mantissa(dataa[26:0]),
.result(result[4:0]),
.all_zero(all_zero));
assign result[5] = all_zero;
assign result[31:6] = 26'd0;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module altera_mem_if_hhp_qseq_synth_top
# ( parameter
APB_DATA_WIDTH = 32,
APB_ADDR_WIDTH = 32,
AVL_DATA_WIDTH = 32,
AVL_ADDR_WIDTH = 16, // for PHY
AVL_MMR_DATA_WIDTH = 32,
AVL_MMR_ADDR_WIDTH = 8,
MEM_IF_DQS_WIDTH = 1,
MEM_IF_DQ_WIDTH = 8,
MEM_IF_DM_WIDTH = 1,
MEM_IF_CS_WIDTH = 1
) (
);
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: acl_int_mult64s.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 174 10/17/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult64s_s5 (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 64;
parameter INPUT2_WIDTH = 64;
input enable;
input clock;
input [INPUT1_WIDTH - 1 : 0] dataa;
input [INPUT2_WIDTH - 1 : 0] datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [63:0] result;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab2;
localparam TMP1_WIDTH = (INPUT1_WIDTH > 32)? INPUT1_WIDTH : 33;
localparam TMP2_WIDTH = (INPUT2_WIDTH > 32)? INPUT2_WIDTH : 33;
generate
if(INPUT1_WIDTH>=19 && INPUT1_WIDTH<=27 && INPUT2_WIDTH>=19 && INPUT2_WIDTH<=27)
begin
// Use a special WYSIWYG for the 27x27 multiplier mode
always@(posedge clock)
begin
if (enable)
begin
reg_dataa <= dataa;
reg_datab <= datab;
end
end
wire [53:0] mul_result;
wire [26:0] inp_a;
wire [26:0] inp_b;
assign inp_a = reg_dataa;
assign inp_b = reg_datab;
sv_mult27 the_multiplier(clock,enable,inp_a,inp_b,mul_result);
always@(*)
begin
result <= mul_result;
end
end
else if(INPUT1_WIDTH == 64 && INPUT2_WIDTH >= 32 || INPUT2_WIDTH == 64 && INPUT1_WIDTH >= 32) begin : GEN_LONG_MUL //Karatsuba algorithm
reg [63:0] temp0;
reg [TMP1_WIDTH-1:0] R_a;
reg [TMP2_WIDTH-1:0] R_b;
reg [31:0] temp1, temp2;
always@(posedge clock) begin
if(enable) begin
R_a <= dataa;
R_b <= datab;
temp0 <= R_a[31:0] * R_b[31:0];
temp1 <= R_a[31:0] * R_b[TMP2_WIDTH-1:32];
temp2 <= R_a[TMP1_WIDTH-1:32] * R_b[31:0];
result[63:32] <= temp0[63:32] + temp1 + temp2;
result[31:0] <= temp0[31:0];
end
end
end
else
begin
// Default LPM_MULT inference
always@(posedge clock)
begin
if (enable)
begin
result <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
end
endgenerate
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "3"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "64"
// Retrieval info: PRIVATE: WidthB NUMERIC "64"
// Retrieval info: PRIVATE: WidthP NUMERIC "128"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "128"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
module peripheral_bt(clk , rst , d_in , cs , addr , rd , wr, d_out, uart_tx, uart_rx );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output uart_rx;
output uart_tx;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and demux_4
reg uart_enable;
reg [7:0] din_uart; // data in uart
wire [7:0] dout_uart;
wire uart_busy; // out_uart
wire uart_done;
wire uart_avail;
//------------------------------------ regs and wires-------------------------------
bluetooth bt(.rx(uart_rx), .avail(uart_avail), .clk_in(clk), .reset(rst), .dout(dout_uart), .din(din_uart), .enable(uart_enable), .busy(uart_busy), .done(uart_done), .tx(uart_tx));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end //din_uart
4'h2:begin s = (cs && rd) ? 5'b00010 : 5'b00000 ;end //done
4'h4:begin s = (cs && rd) ? 5'b00100 : 5'b00000 ;end //avail
4'h6:begin s = (cs && rd) ? 5'b01000 : 5'b00000 ;end //busy
4'h8:begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end //dout_uart <asdfghjkl
default:begin s=5'b00000 ; end
endcase
end//-----------------address_decoder--------------------
wire busymachete= (uart_busy | uart_enable);
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1) begin
din_uart<=d_in[7:0];
uart_enable=1;
end
else begin
if (uart_busy)
uart_enable=0;
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
5'b01000: d_out[0]= busymachete;
5'b00010: d_out[0]= uart_done;
5'b00100: d_out[0]= uart_avail;
5'b10000: d_out[7:0] = dout_uart;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Create tags for the non-posted packet generators.
// Uses a simple 5-bit counter which rolls over
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tag_generator(
input clk,
input rst,
output reg np_tag_gnt,
input np_tag_inc,
output [7:0] tag_value,
input [31:0] completion_pending);
reg rst_reg;
reg [4:0] tag_value_i;
always@(posedge clk) rst_reg <= rst;
//check to see if the tag is already in use
//assert the grant signal if it is not
always@(posedge clk)begin
if(completion_pending[tag_value_i[4:0]])
np_tag_gnt <= 1'b0;
else
np_tag_gnt <= 1'b1;
end
assign tag_value[7:0] = {3'b000,tag_value_i[4:0]};
//tag generator is simply a counter with enable
always@(posedge clk)begin
if(rst_reg)begin
tag_value_i[4:0] <= 5'b00000;
end else if(np_tag_inc)begin
tag_value_i <= tag_value_i + 1;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.49d
// \ \ Application: netgen
// / / Filename: floating_point_v5_0.v
// /___/ /\ Timestamp: Wed Mar 26 14:46:57 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ecelrc/students/smirkhani/maysam/virtex-5/adder/tmp/_cg/floating_point_v5_0.ngc /home/ecelrc/students/smirkhani/maysam/virtex-5/adder/tmp/_cg/floating_point_v5_0.v
// Device : 6vhx250tff1154-2
// Input file : /home/ecelrc/students/smirkhani/maysam/virtex-5/adder/tmp/_cg/floating_point_v5_0.ngc
// Output file : /home/ecelrc/students/smirkhani/maysam/virtex-5/adder/tmp/_cg/floating_point_v5_0.v
// # of Modules : 1
// Design Name : floating_point_v5_0
// Xilinx : /misc/linuxws/packages/Xilinx/14.4/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module floating_point_v5_0 (
clk, a, b, operation, result
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input [63 : 0] a;
input [63 : 0] b;
input [5 : 0] operation;
output [63 : 0] result;
// synthesis translate_off
wire \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
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wire sig000005b8;
wire sig000005b9;
wire sig000005ba;
wire sig000005bb;
wire sig000005bc;
wire sig000005bd;
wire sig000005be;
wire sig000005bf;
wire sig000005c0;
wire sig000005c1;
wire sig000005c2;
wire sig000005c3;
wire sig000005c4;
wire sig000005c5;
wire sig000005c6;
wire sig000005c7;
wire sig000005c8;
wire sig000005c9;
wire sig000005ca;
wire sig000005cb;
wire sig000005cc;
wire sig000005cd;
wire sig000005ce;
wire sig000005cf;
wire sig000005d0;
wire sig000005d1;
wire sig000005d2;
wire sig000005d3;
wire sig000005d4;
wire sig000005d5;
wire sig000005d6;
wire sig000005d7;
wire sig000005d8;
wire sig000005d9;
wire sig000005da;
wire sig000005db;
wire sig000005dc;
wire sig000005dd;
wire sig000005de;
wire sig000005df;
wire sig000005e0;
wire sig000005e1;
wire sig000005e2;
wire sig000005e3;
wire sig000005e4;
wire sig000005e5;
wire sig000005e6;
wire sig000005e7;
wire sig000005e8;
wire sig000005e9;
wire sig000005ea;
wire sig000005eb;
wire sig000005ec;
wire sig000005ed;
wire sig000005ee;
wire sig000005ef;
wire sig000005f0;
wire sig000005f1;
wire sig000005f2;
wire sig000005f3;
wire sig000005f4;
wire sig000005f5;
wire sig000005f6;
wire sig000005f7;
wire sig000005f8;
wire sig000005f9;
wire sig000005fa;
wire sig000005fb;
wire sig000005fc;
wire sig000005fd;
wire sig000005fe;
wire sig000005ff;
wire sig00000600;
wire sig00000601;
wire sig00000602;
wire sig00000603;
wire sig00000604;
wire sig00000605;
wire sig00000606;
wire sig00000607;
wire sig00000608;
wire sig00000609;
wire sig0000060a;
wire sig0000060b;
wire sig0000060c;
wire sig0000060d;
wire sig0000060e;
wire sig0000060f;
wire sig00000610;
wire sig00000611;
wire sig00000612;
wire sig00000613;
wire sig00000614;
wire sig00000615;
wire sig00000616;
wire sig00000617;
wire sig00000618;
wire sig00000619;
wire sig0000061a;
wire sig0000061b;
wire sig0000061c;
wire sig0000061d;
wire sig0000061e;
wire sig0000061f;
wire sig00000620;
wire sig00000621;
wire sig00000622;
wire sig00000623;
wire sig00000624;
wire sig00000625;
wire sig00000626;
wire sig00000627;
wire sig00000628;
wire sig00000629;
wire sig0000062a;
wire sig0000062b;
wire sig0000062c;
wire sig0000062d;
wire sig0000062e;
wire sig0000062f;
wire sig00000630;
wire sig00000631;
wire sig00000632;
wire sig00000633;
wire sig00000634;
wire sig00000635;
wire sig00000636;
wire sig00000637;
wire sig00000638;
wire sig00000639;
wire sig0000063a;
wire sig0000063b;
wire sig0000063c;
wire sig0000063d;
wire sig0000063e;
wire sig0000063f;
wire sig00000640;
wire sig00000641;
wire sig00000642;
wire sig00000643;
wire sig00000644;
wire sig00000645;
wire sig00000646;
wire sig00000647;
wire sig00000648;
wire sig00000649;
wire sig0000064a;
wire sig0000064b;
wire sig0000064c;
wire sig0000064d;
wire sig0000064e;
wire sig0000064f;
wire sig00000650;
wire sig00000651;
wire sig00000652;
wire sig00000653;
wire sig00000654;
wire sig00000655;
wire sig00000656;
wire sig00000657;
wire sig00000658;
wire sig00000659;
wire sig0000065a;
wire sig0000065b;
wire sig0000065c;
wire sig0000065d;
wire sig0000065e;
wire sig0000065f;
wire sig00000660;
wire sig00000661;
wire sig00000662;
wire sig00000663;
wire sig00000664;
wire sig00000665;
wire sig00000666;
wire sig00000667;
wire sig00000668;
wire sig00000669;
wire sig0000066a;
wire sig0000066b;
wire sig0000066c;
wire sig0000066d;
wire sig0000066e;
wire sig0000066f;
wire sig00000670;
wire sig00000671;
wire sig00000672;
wire sig00000673;
wire sig00000674;
wire sig00000675;
wire sig00000676;
wire sig00000677;
wire sig00000678;
wire sig00000679;
wire sig0000067a;
wire sig0000067b;
wire sig0000067c;
wire sig0000067d;
wire sig0000067e;
wire sig0000067f;
wire sig00000680;
wire sig00000681;
wire sig00000682;
wire sig00000683;
wire sig00000684;
wire sig00000685;
wire sig00000686;
wire sig00000687;
wire sig00000688;
wire sig00000689;
wire sig0000068a;
wire sig0000068b;
wire sig0000068c;
wire sig0000068d;
wire sig0000068e;
wire sig0000068f;
wire sig00000690;
wire sig00000691;
wire sig00000692;
wire sig00000693;
wire sig00000694;
wire sig00000695;
wire sig00000696;
wire sig00000697;
wire sig00000698;
wire sig00000699;
wire sig0000069a;
wire sig0000069b;
wire sig0000069c;
wire sig0000069d;
wire sig0000069e;
wire sig0000069f;
wire sig000006a0;
wire sig000006a1;
wire sig000006a2;
wire sig000006a3;
wire sig000006a4;
wire sig000006a5;
wire sig000006a6;
wire sig000006a7;
wire sig000006a8;
wire sig000006a9;
wire sig000006aa;
wire sig000006ab;
wire sig000006ac;
wire sig000006ad;
wire sig000006ae;
wire sig000006af;
wire sig000006b0;
wire sig000006b1;
wire sig000006b2;
wire sig000006b3;
wire sig000006b4;
wire sig000006b5;
wire sig000006b6;
wire sig000006b7;
wire sig000006b8;
wire sig000006b9;
wire sig000006ba;
wire sig000006bb;
wire sig000006bc;
wire sig000006bd;
wire sig000006be;
wire sig000006bf;
wire sig000006c0;
wire sig000006c1;
wire sig000006c2;
wire sig000006c3;
wire sig000006c4;
wire sig000006c5;
wire sig000006c6;
wire sig000006c7;
wire sig000006c8;
wire sig000006c9;
wire sig000006ca;
wire sig000006cb;
wire sig000006cc;
wire sig000006cd;
wire sig000006ce;
wire sig000006cf;
wire sig000006d0;
wire sig000006d1;
wire sig000006d2;
wire sig000006d3;
wire sig000006d4;
wire sig000006d5;
wire sig000006d6;
wire sig000006d7;
wire sig000006d8;
wire sig000006d9;
wire sig000006da;
wire sig000006db;
wire sig000006dc;
wire sig000006dd;
wire sig000006de;
wire sig000006df;
wire sig000006e0;
wire sig000006e1;
wire sig000006e2;
wire sig000006e3;
wire sig000006e4;
wire sig000006e5;
wire sig000006e6;
wire sig000006e7;
wire sig000006e8;
wire sig000006e9;
wire sig000006ea;
wire sig000006eb;
wire sig000006ec;
wire sig000006ed;
wire sig000006ee;
wire sig000006ef;
wire sig000006f0;
wire sig000006f1;
wire sig000006f2;
wire sig000006f3;
wire sig000006f4;
wire sig000006f5;
wire sig000006f6;
wire sig000006f7;
wire sig000006f8;
wire sig000006f9;
wire sig000006fa;
wire sig000006fb;
wire sig000006fc;
wire sig000006fd;
wire sig000006fe;
wire sig000006ff;
wire sig00000700;
wire sig00000701;
wire sig00000702;
wire sig00000703;
wire sig00000704;
wire sig00000705;
wire sig00000706;
wire sig00000707;
wire sig00000708;
wire sig00000709;
wire sig0000070a;
wire sig0000070b;
wire sig0000070c;
wire sig0000070d;
wire sig0000070e;
wire sig0000070f;
wire sig00000710;
wire sig00000711;
wire sig00000712;
wire sig00000713;
wire sig00000714;
wire sig00000715;
wire sig00000716;
wire sig00000717;
wire sig00000718;
wire sig00000719;
wire sig0000071a;
wire sig0000071b;
wire sig0000071c;
wire sig0000071d;
wire sig0000071e;
wire sig0000071f;
wire sig00000720;
wire sig00000721;
wire sig00000722;
wire sig00000723;
wire sig00000724;
wire sig00000725;
wire sig00000726;
wire sig00000727;
wire sig00000728;
wire sig00000729;
wire sig0000072a;
wire sig0000072b;
wire sig0000072c;
wire sig0000072d;
wire sig0000072e;
wire sig0000072f;
wire sig00000730;
wire sig00000731;
wire sig00000732;
wire sig00000733;
wire sig00000734;
wire sig00000735;
wire sig00000736;
wire sig00000737;
wire sig00000738;
wire sig00000739;
wire sig0000073a;
wire sig0000073b;
wire sig0000073c;
wire sig0000073d;
wire sig0000073e;
wire sig0000073f;
wire sig00000740;
wire sig00000741;
wire sig00000742;
wire sig00000743;
wire sig00000744;
wire sig00000745;
wire sig00000746;
wire sig00000747;
wire sig00000748;
wire sig00000749;
wire sig0000074a;
wire sig0000074b;
wire sig0000074c;
wire sig0000074d;
wire sig0000074e;
wire sig0000074f;
wire sig00000750;
wire sig00000751;
wire sig00000752;
wire sig00000753;
wire sig00000754;
wire sig00000755;
wire sig00000756;
wire sig00000757;
wire sig00000758;
wire sig00000759;
wire sig0000075a;
wire sig0000075b;
wire sig0000075c;
wire sig0000075d;
wire sig0000075e;
wire sig0000075f;
wire sig00000760;
wire sig00000761;
wire sig00000762;
wire sig00000763;
wire sig00000764;
wire sig00000765;
wire sig00000766;
wire sig00000767;
wire sig00000768;
wire sig00000769;
wire sig0000076a;
wire sig0000076b;
wire sig0000076c;
wire sig0000076d;
wire sig0000076e;
wire sig0000076f;
wire sig00000770;
wire sig00000771;
wire sig00000772;
wire sig00000773;
wire sig00000774;
wire sig00000775;
wire sig00000776;
wire sig00000777;
wire sig00000778;
wire sig00000779;
wire sig0000077a;
wire sig0000077b;
wire sig0000077c;
wire sig0000077d;
wire sig0000077e;
wire sig0000077f;
wire sig00000780;
wire sig00000781;
wire sig00000782;
wire sig00000783;
wire sig00000784;
wire sig00000785;
wire sig00000786;
wire sig00000787;
wire sig00000788;
wire sig00000789;
wire sig0000078a;
wire sig0000078b;
wire sig0000078c;
wire sig0000078d;
wire sig0000078e;
wire sig0000078f;
wire sig00000790;
wire sig00000791;
wire sig00000792;
wire sig00000793;
wire sig00000794;
wire sig00000795;
wire sig00000796;
wire sig00000797;
wire sig00000798;
wire sig00000799;
wire sig0000079a;
wire sig0000079b;
wire sig0000079c;
wire sig0000079d;
wire sig0000079e;
wire sig0000079f;
wire sig000007a0;
wire sig000007a1;
wire sig000007a2;
wire sig000007a3;
wire sig000007a4;
wire sig000007a5;
wire sig000007a6;
wire sig000007a7;
wire sig000007a8;
wire sig000007a9;
wire sig000007aa;
wire sig000007ab;
wire sig000007ac;
wire sig000007ad;
wire sig000007ae;
wire sig000007af;
wire sig000007b0;
wire sig000007b1;
wire sig000007b2;
wire sig000007b3;
wire sig000007b4;
wire sig000007b5;
wire sig000007b6;
wire sig000007b7;
wire sig000007b8;
wire sig000007b9;
wire sig000007ba;
wire sig000007bb;
wire sig000007bc;
wire sig000007bd;
wire sig000007be;
wire sig000007bf;
wire sig000007c0;
wire sig000007c1;
wire sig000007c2;
wire sig000007c3;
wire sig000007c4;
wire sig000007c5;
wire sig000007c6;
wire sig000007c7;
wire sig000007c8;
wire sig000007c9;
wire sig000007ca;
wire sig000007cb;
wire sig000007cc;
wire sig000007cd;
wire sig000007ce;
wire sig000007cf;
wire sig000007d0;
wire sig000007d1;
wire sig000007d2;
wire sig000007d3;
wire sig000007d4;
wire sig000007d5;
wire sig000007d6;
wire sig000007d7;
wire sig000007d8;
wire sig000007d9;
wire sig000007da;
wire sig000007db;
wire sig000007dc;
wire sig000007dd;
wire sig000007de;
wire sig000007df;
wire sig000007e0;
wire sig000007e1;
wire sig000007e2;
wire sig000007e3;
wire sig000007e4;
wire sig000007e5;
wire sig000007e6;
wire sig000007e7;
wire sig000007e8;
wire sig000007e9;
wire sig000007ea;
wire sig000007eb;
wire sig000007ec;
wire sig000007ed;
wire sig000007ee;
wire sig000007ef;
wire sig000007f0;
wire sig000007f1;
wire sig000007f2;
wire sig000007f3;
wire sig000007f4;
wire sig000007f5;
wire sig000007f6;
wire sig000007f7;
wire sig000007f8;
wire sig000007f9;
wire sig000007fa;
wire sig000007fb;
wire sig000007fc;
wire sig000007fd;
wire sig000007fe;
wire sig000007ff;
wire sig00000800;
wire sig00000801;
wire sig00000802;
wire sig00000803;
wire sig00000804;
wire sig00000805;
wire sig00000806;
wire sig00000807;
wire sig00000808;
wire sig00000809;
wire sig0000080a;
wire sig0000080b;
wire sig0000080c;
wire sig0000080d;
wire sig0000080e;
wire sig0000080f;
wire sig00000810;
wire sig00000811;
wire sig00000812;
wire sig00000813;
wire sig00000814;
wire sig00000815;
wire sig00000816;
wire sig00000817;
wire sig00000818;
wire sig00000819;
wire sig0000081a;
wire sig0000081b;
wire sig0000081c;
wire sig0000081d;
wire sig0000081e;
wire sig0000081f;
wire sig00000820;
wire sig00000821;
wire sig00000822;
wire sig00000823;
wire sig00000824;
wire sig00000825;
wire sig00000826;
wire sig00000827;
wire sig00000828;
wire sig00000829;
wire sig0000082a;
wire sig0000082b;
wire sig0000082c;
wire sig0000082d;
wire sig0000082e;
wire sig0000082f;
wire sig00000830;
wire sig00000831;
wire sig00000832;
wire sig00000833;
wire sig00000834;
wire sig00000835;
wire sig00000836;
wire sig00000837;
wire sig00000838;
wire sig00000839;
wire sig0000083a;
wire sig0000083b;
wire sig0000083c;
wire sig0000083d;
wire sig0000083e;
wire sig0000083f;
wire sig00000840;
wire sig00000841;
wire sig00000842;
wire sig00000843;
wire sig00000844;
wire sig00000845;
wire NLW_blk000003c6_O_UNCONNECTED;
wire NLW_blk000003cc_O_UNCONNECTED;
wire NLW_blk00000416_O_UNCONNECTED;
wire NLW_blk00000418_O_UNCONNECTED;
wire NLW_blk0000041a_O_UNCONNECTED;
wire NLW_blk0000041c_O_UNCONNECTED;
wire NLW_blk0000041e_O_UNCONNECTED;
wire NLW_blk00000420_O_UNCONNECTED;
wire NLW_blk00000422_O_UNCONNECTED;
wire NLW_blk00000424_O_UNCONNECTED;
wire NLW_blk00000426_O_UNCONNECTED;
wire NLW_blk00000428_O_UNCONNECTED;
wire NLW_blk0000042a_O_UNCONNECTED;
wire NLW_blk0000042c_O_UNCONNECTED;
wire NLW_blk0000042d_O_UNCONNECTED;
wire NLW_blk0000043b_O_UNCONNECTED;
wire NLW_blk0000043f_O_UNCONNECTED;
wire NLW_blk00000441_O_UNCONNECTED;
wire NLW_blk00000443_O_UNCONNECTED;
wire NLW_blk00000445_O_UNCONNECTED;
wire NLW_blk00000447_O_UNCONNECTED;
wire NLW_blk00000449_O_UNCONNECTED;
wire NLW_blk0000044b_O_UNCONNECTED;
wire NLW_blk0000044d_O_UNCONNECTED;
wire NLW_blk0000044f_O_UNCONNECTED;
wire NLW_blk00000451_O_UNCONNECTED;
wire NLW_blk00000452_O_UNCONNECTED;
wire NLW_blk000007d8_Q15_UNCONNECTED;
wire NLW_blk000007da_Q15_UNCONNECTED;
wire NLW_blk000007dc_Q15_UNCONNECTED;
wire NLW_blk000007de_Q15_UNCONNECTED;
wire NLW_blk000007e0_Q15_UNCONNECTED;
wire NLW_blk000007e2_Q15_UNCONNECTED;
wire NLW_blk000007e4_Q15_UNCONNECTED;
wire NLW_blk000007e6_Q15_UNCONNECTED;
wire NLW_blk000007e8_Q15_UNCONNECTED;
wire NLW_blk000007ea_Q15_UNCONNECTED;
wire NLW_blk000007ec_Q15_UNCONNECTED;
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wire NLW_blk000007f0_Q15_UNCONNECTED;
wire NLW_blk000007f2_Q15_UNCONNECTED;
wire NLW_blk000007f4_Q15_UNCONNECTED;
wire NLW_blk000007f6_Q15_UNCONNECTED;
wire NLW_blk000007f8_Q15_UNCONNECTED;
wire NLW_blk000007fa_Q15_UNCONNECTED;
wire NLW_blk000007fc_Q15_UNCONNECTED;
wire NLW_blk000007fe_Q15_UNCONNECTED;
wire NLW_blk00000800_Q15_UNCONNECTED;
wire NLW_blk00000802_Q15_UNCONNECTED;
wire NLW_blk00000804_Q15_UNCONNECTED;
wire NLW_blk00000806_Q15_UNCONNECTED;
wire NLW_blk00000808_Q15_UNCONNECTED;
wire NLW_blk0000080a_Q15_UNCONNECTED;
wire NLW_blk0000080c_Q15_UNCONNECTED;
wire NLW_blk0000080e_Q15_UNCONNECTED;
wire NLW_blk00000810_Q15_UNCONNECTED;
wire NLW_blk00000812_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000812_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000812_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000812_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000812_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000812_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000812_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000812_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000812_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000812_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000812_P<47>_UNCONNECTED ;
wire \NLW_blk00000812_P<46>_UNCONNECTED ;
wire \NLW_blk00000812_P<45>_UNCONNECTED ;
wire \NLW_blk00000812_P<44>_UNCONNECTED ;
wire \NLW_blk00000812_P<43>_UNCONNECTED ;
wire \NLW_blk00000812_P<42>_UNCONNECTED ;
wire \NLW_blk00000812_P<41>_UNCONNECTED ;
wire \NLW_blk00000812_P<40>_UNCONNECTED ;
wire \NLW_blk00000812_P<39>_UNCONNECTED ;
wire \NLW_blk00000812_P<38>_UNCONNECTED ;
wire \NLW_blk00000812_P<37>_UNCONNECTED ;
wire \NLW_blk00000812_P<36>_UNCONNECTED ;
wire \NLW_blk00000812_P<35>_UNCONNECTED ;
wire \NLW_blk00000812_P<34>_UNCONNECTED ;
wire \NLW_blk00000812_P<33>_UNCONNECTED ;
wire \NLW_blk00000812_P<32>_UNCONNECTED ;
wire \NLW_blk00000812_P<31>_UNCONNECTED ;
wire \NLW_blk00000812_P<30>_UNCONNECTED ;
wire \NLW_blk00000812_P<29>_UNCONNECTED ;
wire \NLW_blk00000812_P<28>_UNCONNECTED ;
wire \NLW_blk00000812_P<27>_UNCONNECTED ;
wire \NLW_blk00000812_P<26>_UNCONNECTED ;
wire \NLW_blk00000812_P<25>_UNCONNECTED ;
wire \NLW_blk00000812_P<24>_UNCONNECTED ;
wire \NLW_blk00000812_P<23>_UNCONNECTED ;
wire \NLW_blk00000812_P<22>_UNCONNECTED ;
wire \NLW_blk00000812_P<21>_UNCONNECTED ;
wire \NLW_blk00000812_P<20>_UNCONNECTED ;
wire \NLW_blk00000812_P<19>_UNCONNECTED ;
wire \NLW_blk00000812_P<18>_UNCONNECTED ;
wire \NLW_blk00000812_P<17>_UNCONNECTED ;
wire \NLW_blk00000812_P<16>_UNCONNECTED ;
wire \NLW_blk00000812_P<15>_UNCONNECTED ;
wire \NLW_blk00000812_P<14>_UNCONNECTED ;
wire \NLW_blk00000812_P<13>_UNCONNECTED ;
wire \NLW_blk00000812_P<12>_UNCONNECTED ;
wire \NLW_blk00000812_P<11>_UNCONNECTED ;
wire \NLW_blk00000812_P<10>_UNCONNECTED ;
wire \NLW_blk00000812_P<9>_UNCONNECTED ;
wire \NLW_blk00000812_P<8>_UNCONNECTED ;
wire \NLW_blk00000812_P<7>_UNCONNECTED ;
wire \NLW_blk00000812_P<6>_UNCONNECTED ;
wire \NLW_blk00000812_P<5>_UNCONNECTED ;
wire \NLW_blk00000812_P<4>_UNCONNECTED ;
wire \NLW_blk00000812_P<3>_UNCONNECTED ;
wire \NLW_blk00000812_P<2>_UNCONNECTED ;
wire \NLW_blk00000812_P<1>_UNCONNECTED ;
wire \NLW_blk00000812_P<0>_UNCONNECTED ;
wire NLW_blk00000813_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000813_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000813_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000813_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000813_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000813_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000813_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000813_PCOUT<0>_UNCONNECTED ;
wire NLW_blk00000814_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000814_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000814_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000814_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000814_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000814_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000814_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000814_P<0>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000814_PCOUT<0>_UNCONNECTED ;
wire [10 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op ;
wire [51 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op ;
assign
result[63] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op ,
result[62] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [10],
result[61] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [9],
result[60] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [8],
result[59] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [7],
result[58] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [6],
result[57] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [5],
result[56] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [4],
result[55] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [3],
result[54] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [2],
result[53] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [1],
result[52] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [0],
result[51] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [51],
result[50] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [50],
result[49] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [49],
result[48] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [48],
result[47] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [47],
result[46] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [46],
result[45] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [45],
result[44] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [44],
result[43] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [43],
result[42] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [42],
result[41] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [41],
result[40] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [40],
result[39] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [39],
result[38] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [38],
result[37] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [37],
result[36] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [36],
result[35] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [35],
result[34] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [34],
result[33] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [33],
result[32] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [32],
result[31] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [31],
result[30] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [30],
result[29] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [29],
result[28] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [28],
result[27] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [27],
result[26] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [26],
result[25] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [25],
result[24] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [24],
result[23] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [23],
result[22] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [22],
result[21] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [21],
result[20] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [20],
result[19] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [19],
result[18] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [18],
result[17] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [17],
result[16] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [16],
result[15] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [15],
result[14] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [14],
result[13] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [13],
result[12] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [12],
result[11] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [11],
result[10] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [10],
result[9] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [9],
result[8] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [8],
result[7] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [7],
result[6] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [6],
result[5] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [5],
result[4] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [4],
result[3] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [3],
result[2] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [2],
result[1] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [1],
result[0] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig000006c3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(sig00000001),
.D(sig00000156),
.Q(sig0000023f)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000279),
.Q(sig0000023b)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(sig00000278),
.Q(sig0000023c)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(sig00000277),
.Q(sig0000023e)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(sig000002b6),
.Q(sig0000023a)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(sig000002b7),
.Q(sig0000023d)
);
XORCY blk00000009 (
.CI(sig0000024b),
.LI(sig00000001),
.O(sig000002aa)
);
XORCY blk0000000a (
.CI(sig0000024d),
.LI(sig0000024c),
.O(sig000002b5)
);
MUXCY blk0000000b (
.CI(sig0000024d),
.DI(sig000002d1),
.S(sig0000024c),
.O(sig0000024b)
);
XORCY blk0000000c (
.CI(sig0000024f),
.LI(sig0000024e),
.O(sig000002b4)
);
MUXCY blk0000000d (
.CI(sig0000024f),
.DI(sig000002d0),
.S(sig0000024e),
.O(sig0000024d)
);
XORCY blk0000000e (
.CI(sig00000251),
.LI(sig00000250),
.O(sig000002b3)
);
MUXCY blk0000000f (
.CI(sig00000251),
.DI(sig000002cf),
.S(sig00000250),
.O(sig0000024f)
);
XORCY blk00000010 (
.CI(sig00000253),
.LI(sig00000252),
.O(sig000002b2)
);
MUXCY blk00000011 (
.CI(sig00000253),
.DI(sig000002ce),
.S(sig00000252),
.O(sig00000251)
);
XORCY blk00000012 (
.CI(sig00000255),
.LI(sig00000254),
.O(sig000002b1)
);
MUXCY blk00000013 (
.CI(sig00000255),
.DI(sig000002cd),
.S(sig00000254),
.O(sig00000253)
);
XORCY blk00000014 (
.CI(sig00000257),
.LI(sig00000256),
.O(sig000002b0)
);
MUXCY blk00000015 (
.CI(sig00000257),
.DI(sig000002cc),
.S(sig00000256),
.O(sig00000255)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000016 (
.I0(sig000002cc),
.I1(sig00000189),
.O(sig00000256)
);
XORCY blk00000017 (
.CI(sig00000259),
.LI(sig00000258),
.O(sig000002af)
);
MUXCY blk00000018 (
.CI(sig00000259),
.DI(sig000002cb),
.S(sig00000258),
.O(sig00000257)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000019 (
.I0(sig000002cb),
.I1(sig00000188),
.O(sig00000258)
);
XORCY blk0000001a (
.CI(sig0000025b),
.LI(sig0000025a),
.O(sig000002ae)
);
MUXCY blk0000001b (
.CI(sig0000025b),
.DI(sig000002ca),
.S(sig0000025a),
.O(sig00000259)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001c (
.I0(sig000002ca),
.I1(sig00000187),
.O(sig0000025a)
);
XORCY blk0000001d (
.CI(sig0000025d),
.LI(sig0000025c),
.O(sig000002ad)
);
MUXCY blk0000001e (
.CI(sig0000025d),
.DI(sig000002c9),
.S(sig0000025c),
.O(sig0000025b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001f (
.I0(sig000002c9),
.I1(sig00000186),
.O(sig0000025c)
);
XORCY blk00000020 (
.CI(sig0000025f),
.LI(sig0000025e),
.O(sig000002ac)
);
MUXCY blk00000021 (
.CI(sig0000025f),
.DI(sig000002c8),
.S(sig0000025e),
.O(sig0000025d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000022 (
.I0(sig000002c8),
.I1(sig0000011c),
.O(sig0000025e)
);
XORCY blk00000023 (
.CI(sig00000001),
.LI(sig00000260),
.O(sig000002ab)
);
MUXCY blk00000024 (
.CI(sig00000001),
.DI(sig000002c7),
.S(sig00000260),
.O(sig0000025f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000025 (
.I0(sig000002c7),
.I1(sig0000011d),
.O(sig00000260)
);
XORCY blk00000026 (
.CI(sig00000261),
.LI(sig00000001),
.O(sig0000029e)
);
XORCY blk00000027 (
.CI(sig00000263),
.LI(sig00000262),
.O(sig0000029d)
);
MUXCY blk00000028 (
.CI(sig00000263),
.DI(b[62]),
.S(sig00000262),
.O(sig00000261)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000029 (
.I0(b[62]),
.I1(a[62]),
.O(sig00000262)
);
XORCY blk0000002a (
.CI(sig00000265),
.LI(sig00000264),
.O(sig0000029c)
);
MUXCY blk0000002b (
.CI(sig00000265),
.DI(b[61]),
.S(sig00000264),
.O(sig00000263)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002c (
.I0(b[61]),
.I1(a[61]),
.O(sig00000264)
);
XORCY blk0000002d (
.CI(sig00000267),
.LI(sig00000266),
.O(sig0000029b)
);
MUXCY blk0000002e (
.CI(sig00000267),
.DI(b[60]),
.S(sig00000266),
.O(sig00000265)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002f (
.I0(b[60]),
.I1(a[60]),
.O(sig00000266)
);
XORCY blk00000030 (
.CI(sig00000269),
.LI(sig00000268),
.O(sig0000029a)
);
MUXCY blk00000031 (
.CI(sig00000269),
.DI(b[59]),
.S(sig00000268),
.O(sig00000267)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000032 (
.I0(b[59]),
.I1(a[59]),
.O(sig00000268)
);
XORCY blk00000033 (
.CI(sig0000026b),
.LI(sig0000026a),
.O(sig00000299)
);
MUXCY blk00000034 (
.CI(sig0000026b),
.DI(b[58]),
.S(sig0000026a),
.O(sig00000269)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000035 (
.I0(b[58]),
.I1(a[58]),
.O(sig0000026a)
);
XORCY blk00000036 (
.CI(sig0000026d),
.LI(sig0000026c),
.O(sig00000298)
);
MUXCY blk00000037 (
.CI(sig0000026d),
.DI(b[57]),
.S(sig0000026c),
.O(sig0000026b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000038 (
.I0(b[57]),
.I1(a[57]),
.O(sig0000026c)
);
XORCY blk00000039 (
.CI(sig0000026f),
.LI(sig0000026e),
.O(sig00000297)
);
MUXCY blk0000003a (
.CI(sig0000026f),
.DI(b[56]),
.S(sig0000026e),
.O(sig0000026d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000003b (
.I0(b[56]),
.I1(a[56]),
.O(sig0000026e)
);
XORCY blk0000003c (
.CI(sig00000271),
.LI(sig00000270),
.O(sig00000296)
);
MUXCY blk0000003d (
.CI(sig00000271),
.DI(b[55]),
.S(sig00000270),
.O(sig0000026f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000003e (
.I0(b[55]),
.I1(a[55]),
.O(sig00000270)
);
XORCY blk0000003f (
.CI(sig00000273),
.LI(sig00000272),
.O(sig00000295)
);
MUXCY blk00000040 (
.CI(sig00000273),
.DI(b[54]),
.S(sig00000272),
.O(sig00000271)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000041 (
.I0(b[54]),
.I1(a[54]),
.O(sig00000272)
);
XORCY blk00000042 (
.CI(sig00000275),
.LI(sig00000274),
.O(sig00000294)
);
MUXCY blk00000043 (
.CI(sig00000275),
.DI(b[53]),
.S(sig00000274),
.O(sig00000273)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000044 (
.I0(b[53]),
.I1(a[53]),
.O(sig00000274)
);
MUXCY blk00000045 (
.CI(sig00000001),
.DI(b[52]),
.S(sig00000276),
.O(sig00000275)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000046 (
.I0(b[52]),
.I1(a[52]),
.O(sig00000276)
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(clk),
.CE(sig00000001),
.D(sig000002a1),
.Q(sig000002b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(clk),
.CE(sig00000001),
.D(sig000002a2),
.Q(sig000002b7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(clk),
.CE(sig00000001),
.D(a[63]),
.Q(sig000002f5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(clk),
.CE(sig00000001),
.D(sig000002a9),
.Q(sig000002f4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(clk),
.CE(sig00000001),
.D(sig000002aa),
.Q(sig000002b8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004c (
.C(clk),
.CE(sig00000001),
.D(sig00000157),
.Q(sig0000027d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004d (
.C(clk),
.CE(sig00000001),
.D(sig0000027d),
.Q(sig0000030c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004e (
.C(clk),
.CE(sig00000001),
.D(sig000002a0),
.Q(sig0000027e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004f (
.C(clk),
.CE(sig00000001),
.D(sig0000027e),
.Q(sig0000022b)
);
FD #(
.INIT ( 1'b0 ))
blk00000050 (
.C(clk),
.D(sig000001c2),
.Q(sig0000027f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000051 (
.C(clk),
.CE(sig00000001),
.D(sig0000022d),
.Q(sig000002f3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000052 (
.C(clk),
.CE(sig00000001),
.D(sig00000291),
.Q(sig000002f2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000053 (
.C(clk),
.CE(sig00000001),
.D(sig00000293),
.Q(sig000002f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000054 (
.C(clk),
.CE(sig00000001),
.D(sig00000292),
.Q(sig000002ef)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(clk),
.CE(sig00000001),
.D(sig00000290),
.Q(sig000004b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000056 (
.C(clk),
.CE(sig00000001),
.D(sig000002a6),
.Q(sig000002ee)
);
FDE #(
.INIT ( 1'b0 ))
blk00000057 (
.C(clk),
.CE(sig00000001),
.D(sig000002a7),
.Q(sig000002f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000058 (
.C(clk),
.CE(sig00000001),
.D(sig000002a8),
.Q(sig000002ed)
);
FDE #(
.INIT ( 1'b0 ))
blk00000059 (
.C(clk),
.CE(sig00000001),
.D(sig0000029f),
.Q(sig000002c5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005a (
.C(clk),
.CE(sig00000001),
.D(sig0000030e),
.Q(sig000002c4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005b (
.C(clk),
.CE(sig00000001),
.D(sig00000283),
.Q(sig0000030f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005c (
.C(clk),
.CE(sig00000001),
.D(sig00000282),
.Q(sig00000310)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005d (
.C(clk),
.CE(sig00000001),
.D(sig00000281),
.Q(sig00000312)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005e (
.C(clk),
.CE(sig00000001),
.D(sig00000280),
.Q(sig00000313)
);
MUXCY blk0000005f (
.CI(sig00000328),
.DI(sig000006c3),
.S(sig00000326),
.O(sig00000327)
);
MUXCY blk00000060 (
.CI(sig00000329),
.DI(sig000006c3),
.S(sig0000031e),
.O(sig00000328)
);
MUXCY blk00000061 (
.CI(sig0000032a),
.DI(sig000006c3),
.S(sig0000031f),
.O(sig00000329)
);
MUXCY blk00000062 (
.CI(sig0000032b),
.DI(sig000006c3),
.S(sig00000320),
.O(sig0000032a)
);
MUXCY blk00000063 (
.CI(sig0000032c),
.DI(sig000006c3),
.S(sig00000321),
.O(sig0000032b)
);
MUXCY blk00000064 (
.CI(sig0000032d),
.DI(sig000006c3),
.S(sig00000322),
.O(sig0000032c)
);
MUXCY blk00000065 (
.CI(sig0000032e),
.DI(sig000006c3),
.S(sig00000323),
.O(sig0000032d)
);
MUXCY blk00000066 (
.CI(sig0000032f),
.DI(sig000006c3),
.S(sig00000324),
.O(sig0000032e)
);
MUXCY blk00000067 (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig00000325),
.O(sig0000032f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(clk),
.CE(sig00000001),
.D(sig00000327),
.Q(sig00000311)
);
MUXCY blk00000069 (
.CI(sig00000331),
.DI(sig000006c3),
.S(sig0000031d),
.O(sig00000330)
);
MUXCY blk0000006a (
.CI(sig00000332),
.DI(sig000006c3),
.S(sig00000315),
.O(sig00000331)
);
MUXCY blk0000006b (
.CI(sig00000333),
.DI(sig000006c3),
.S(sig00000316),
.O(sig00000332)
);
MUXCY blk0000006c (
.CI(sig00000334),
.DI(sig000006c3),
.S(sig00000317),
.O(sig00000333)
);
MUXCY blk0000006d (
.CI(sig00000335),
.DI(sig000006c3),
.S(sig00000318),
.O(sig00000334)
);
MUXCY blk0000006e (
.CI(sig00000336),
.DI(sig000006c3),
.S(sig00000319),
.O(sig00000335)
);
MUXCY blk0000006f (
.CI(sig00000337),
.DI(sig000006c3),
.S(sig0000031a),
.O(sig00000336)
);
MUXCY blk00000070 (
.CI(sig00000338),
.DI(sig000006c3),
.S(sig0000031b),
.O(sig00000337)
);
MUXCY blk00000071 (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig0000031c),
.O(sig00000338)
);
FDE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(sig00000001),
.D(sig00000330),
.Q(sig00000314)
);
MUXCY blk00000073 (
.CI(sig0000037a),
.DI(sig00000359),
.S(sig0000035a),
.O(sig00000379)
);
MUXCY blk00000074 (
.CI(sig0000037b),
.DI(sig0000035b),
.S(sig0000035c),
.O(sig0000037a)
);
MUXCY blk00000075 (
.CI(sig0000037c),
.DI(sig0000035d),
.S(sig0000035e),
.O(sig0000037b)
);
MUXCY blk00000076 (
.CI(sig0000037d),
.DI(sig0000035f),
.S(sig00000360),
.O(sig0000037c)
);
MUXCY blk00000077 (
.CI(sig0000037e),
.DI(sig00000361),
.S(sig00000362),
.O(sig0000037d)
);
MUXCY blk00000078 (
.CI(sig0000037f),
.DI(sig00000363),
.S(sig00000364),
.O(sig0000037e)
);
MUXCY blk00000079 (
.CI(sig00000380),
.DI(sig00000365),
.S(sig00000366),
.O(sig0000037f)
);
MUXCY blk0000007a (
.CI(sig00000381),
.DI(sig00000367),
.S(sig00000368),
.O(sig00000380)
);
MUXCY blk0000007b (
.CI(sig00000382),
.DI(sig00000369),
.S(sig0000036a),
.O(sig00000381)
);
MUXCY blk0000007c (
.CI(sig00000383),
.DI(sig0000036b),
.S(sig0000036c),
.O(sig00000382)
);
MUXCY blk0000007d (
.CI(sig00000384),
.DI(sig0000036d),
.S(sig0000036e),
.O(sig00000383)
);
MUXCY blk0000007e (
.CI(sig00000385),
.DI(sig0000036f),
.S(sig00000370),
.O(sig00000384)
);
MUXCY blk0000007f (
.CI(sig00000386),
.DI(sig00000371),
.S(sig00000372),
.O(sig00000385)
);
MUXCY blk00000080 (
.CI(sig00000387),
.DI(sig00000373),
.S(sig00000374),
.O(sig00000386)
);
MUXCY blk00000081 (
.CI(sig00000388),
.DI(sig00000375),
.S(sig00000376),
.O(sig00000387)
);
MUXCY blk00000082 (
.CI(sig000006c3),
.DI(sig00000377),
.S(sig00000378),
.O(sig00000388)
);
FDE #(
.INIT ( 1'b0 ))
blk00000083 (
.C(clk),
.CE(sig00000001),
.D(sig00000379),
.Q(sig0000027b)
);
MUXCY blk00000084 (
.CI(sig0000038a),
.DI(sig00000339),
.S(sig0000033a),
.O(sig00000389)
);
MUXCY blk00000085 (
.CI(sig0000038b),
.DI(sig0000033b),
.S(sig0000033c),
.O(sig0000038a)
);
MUXCY blk00000086 (
.CI(sig0000038c),
.DI(sig0000033d),
.S(sig0000033e),
.O(sig0000038b)
);
MUXCY blk00000087 (
.CI(sig0000038d),
.DI(sig0000033f),
.S(sig00000340),
.O(sig0000038c)
);
MUXCY blk00000088 (
.CI(sig0000038e),
.DI(sig00000341),
.S(sig00000342),
.O(sig0000038d)
);
MUXCY blk00000089 (
.CI(sig0000038f),
.DI(sig00000343),
.S(sig00000344),
.O(sig0000038e)
);
MUXCY blk0000008a (
.CI(sig00000390),
.DI(sig00000345),
.S(sig00000346),
.O(sig0000038f)
);
MUXCY blk0000008b (
.CI(sig00000391),
.DI(sig00000347),
.S(sig00000348),
.O(sig00000390)
);
MUXCY blk0000008c (
.CI(sig00000392),
.DI(sig00000349),
.S(sig0000034a),
.O(sig00000391)
);
MUXCY blk0000008d (
.CI(sig00000393),
.DI(sig0000034b),
.S(sig0000034c),
.O(sig00000392)
);
MUXCY blk0000008e (
.CI(sig00000394),
.DI(sig0000034d),
.S(sig0000034e),
.O(sig00000393)
);
MUXCY blk0000008f (
.CI(sig00000395),
.DI(sig0000034f),
.S(sig00000350),
.O(sig00000394)
);
MUXCY blk00000090 (
.CI(sig00000396),
.DI(sig00000351),
.S(sig00000352),
.O(sig00000395)
);
MUXCY blk00000091 (
.CI(sig00000397),
.DI(sig00000353),
.S(sig00000354),
.O(sig00000396)
);
MUXCY blk00000092 (
.CI(sig00000398),
.DI(sig00000355),
.S(sig00000356),
.O(sig00000397)
);
MUXCY blk00000093 (
.CI(sig000006c3),
.DI(sig00000357),
.S(sig00000358),
.O(sig00000398)
);
FDE #(
.INIT ( 1'b0 ))
blk00000094 (
.C(clk),
.CE(sig00000001),
.D(sig00000389),
.Q(sig0000027a)
);
MUXCY blk00000095 (
.CI(sig000003a5),
.DI(sig000006c3),
.S(sig00000399),
.O(sig000003a4)
);
MUXCY blk00000096 (
.CI(sig000003a6),
.DI(sig000006c3),
.S(sig0000039a),
.O(sig000003a5)
);
MUXCY blk00000097 (
.CI(sig000003a7),
.DI(sig000006c3),
.S(sig0000039b),
.O(sig000003a6)
);
MUXCY blk00000098 (
.CI(sig000003a8),
.DI(sig000006c3),
.S(sig0000039c),
.O(sig000003a7)
);
MUXCY blk00000099 (
.CI(sig000003a9),
.DI(sig000006c3),
.S(sig0000039d),
.O(sig000003a8)
);
MUXCY blk0000009a (
.CI(sig000003aa),
.DI(sig000006c3),
.S(sig0000039e),
.O(sig000003a9)
);
MUXCY blk0000009b (
.CI(sig000003ab),
.DI(sig000006c3),
.S(sig0000039f),
.O(sig000003aa)
);
MUXCY blk0000009c (
.CI(sig000003ac),
.DI(sig000006c3),
.S(sig000003a0),
.O(sig000003ab)
);
MUXCY blk0000009d (
.CI(sig000003ad),
.DI(sig000006c3),
.S(sig000003a1),
.O(sig000003ac)
);
MUXCY blk0000009e (
.CI(sig000003ae),
.DI(sig000006c3),
.S(sig000003a2),
.O(sig000003ad)
);
MUXCY blk0000009f (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000003a3),
.O(sig000003ae)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(clk),
.CE(sig00000001),
.D(sig000003a4),
.Q(sig0000027c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a1 (
.C(clk),
.CE(sig00000001),
.D(sig000002b5),
.Q(sig000002c3)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a2 (
.C(clk),
.CE(sig00000001),
.D(sig000002b4),
.Q(sig000002c2)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a3 (
.C(clk),
.CE(sig00000001),
.D(sig000002b3),
.Q(sig000002c1)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a4 (
.C(clk),
.CE(sig00000001),
.D(sig000002b2),
.Q(sig000002c0)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a5 (
.C(clk),
.CE(sig00000001),
.D(sig000002b1),
.Q(sig000002bf)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a6 (
.C(clk),
.CE(sig00000001),
.D(sig000002b0),
.Q(sig000002be)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a7 (
.C(clk),
.CE(sig00000001),
.D(sig000002af),
.Q(sig000002bd)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a8 (
.C(clk),
.CE(sig00000001),
.D(sig000002ae),
.Q(sig000002bc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a9 (
.C(clk),
.CE(sig00000001),
.D(sig000002ad),
.Q(sig000002bb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000aa (
.C(clk),
.CE(sig00000001),
.D(sig000002ac),
.Q(sig000002ba)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ab (
.C(clk),
.CE(sig00000001),
.D(sig000002ab),
.Q(sig000002b9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ac (
.C(clk),
.CE(sig00000001),
.D(b[62]),
.Q(sig00000300)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ad (
.C(clk),
.CE(sig00000001),
.D(b[61]),
.Q(sig000002ff)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ae (
.C(clk),
.CE(sig00000001),
.D(b[60]),
.Q(sig000002fe)
);
FDE #(
.INIT ( 1'b0 ))
blk000000af (
.C(clk),
.CE(sig00000001),
.D(b[59]),
.Q(sig000002fd)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b0 (
.C(clk),
.CE(sig00000001),
.D(b[58]),
.Q(sig000002fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b1 (
.C(clk),
.CE(sig00000001),
.D(b[57]),
.Q(sig000002fb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b2 (
.C(clk),
.CE(sig00000001),
.D(b[56]),
.Q(sig000002fa)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b3 (
.C(clk),
.CE(sig00000001),
.D(b[55]),
.Q(sig000002f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b4 (
.C(clk),
.CE(sig00000001),
.D(b[54]),
.Q(sig000002f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b5 (
.C(clk),
.CE(sig00000001),
.D(b[53]),
.Q(sig000002f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b6 (
.C(clk),
.CE(sig00000001),
.D(b[52]),
.Q(sig000002f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b7 (
.C(clk),
.CE(sig00000001),
.D(a[62]),
.Q(sig0000030b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b8 (
.C(clk),
.CE(sig00000001),
.D(a[61]),
.Q(sig0000030a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b9 (
.C(clk),
.CE(sig00000001),
.D(a[60]),
.Q(sig00000309)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ba (
.C(clk),
.CE(sig00000001),
.D(a[59]),
.Q(sig00000308)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bb (
.C(clk),
.CE(sig00000001),
.D(a[58]),
.Q(sig00000307)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bc (
.C(clk),
.CE(sig00000001),
.D(a[57]),
.Q(sig00000306)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.CE(sig00000001),
.D(a[56]),
.Q(sig00000305)
);
FDE #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.CE(sig00000001),
.D(a[55]),
.Q(sig00000304)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.CE(sig00000001),
.D(a[54]),
.Q(sig00000303)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.CE(sig00000001),
.D(a[53]),
.Q(sig00000302)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.CE(sig00000001),
.D(a[52]),
.Q(sig00000301)
);
FD #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.D(sig0000029e),
.Q(sig0000024a)
);
FD #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.D(sig0000029d),
.Q(sig00000249)
);
FD #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.D(sig0000029c),
.Q(sig00000248)
);
FD #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.D(sig0000029b),
.Q(sig00000247)
);
FD #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.D(sig0000029a),
.Q(sig00000246)
);
FD #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.D(sig00000299),
.Q(sig00000245)
);
FD #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.D(sig00000298),
.Q(sig00000244)
);
FD #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.D(sig00000297),
.Q(sig00000243)
);
FD #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.D(sig00000296),
.Q(sig00000242)
);
FD #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.D(sig00000295),
.Q(sig00000241)
);
FD #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.D(sig00000294),
.Q(sig00000240)
);
FD #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.D(sig000002a5),
.Q(sig000003b0)
);
FD #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.D(sig000002a4),
.Q(sig000003af)
);
FD #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.D(sig000002a3),
.Q(sig000003b1)
);
XORCY blk000000d0 (
.CI(sig000003b2),
.LI(sig000006c3),
.O(sig000002e9)
);
XORCY blk000000d1 (
.CI(sig000003b3),
.LI(sig0000028e),
.O(sig000002e8)
);
MUXCY blk000000d2 (
.CI(sig000003b3),
.DI(sig000006c3),
.S(sig0000028e),
.O(sig000003b2)
);
XORCY blk000000d3 (
.CI(sig000003b4),
.LI(sig0000028d),
.O(sig000002e7)
);
MUXCY blk000000d4 (
.CI(sig000003b4),
.DI(sig000006c3),
.S(sig0000028d),
.O(sig000003b3)
);
XORCY blk000000d5 (
.CI(sig000003b5),
.LI(sig0000028c),
.O(sig000002e6)
);
MUXCY blk000000d6 (
.CI(sig000003b5),
.DI(sig000006c3),
.S(sig0000028c),
.O(sig000003b4)
);
XORCY blk000000d7 (
.CI(sig000003b6),
.LI(sig0000028b),
.O(sig000002e5)
);
MUXCY blk000000d8 (
.CI(sig000003b6),
.DI(sig000006c3),
.S(sig0000028b),
.O(sig000003b5)
);
XORCY blk000000d9 (
.CI(sig000003b7),
.LI(sig0000028a),
.O(sig000002e4)
);
MUXCY blk000000da (
.CI(sig000003b7),
.DI(sig000006c3),
.S(sig0000028a),
.O(sig000003b6)
);
XORCY blk000000db (
.CI(sig000003b8),
.LI(sig00000289),
.O(sig000002e3)
);
MUXCY blk000000dc (
.CI(sig000003b8),
.DI(sig000006c3),
.S(sig00000289),
.O(sig000003b7)
);
XORCY blk000000dd (
.CI(sig000003b9),
.LI(sig00000288),
.O(sig000002e2)
);
MUXCY blk000000de (
.CI(sig000003b9),
.DI(sig000006c3),
.S(sig00000288),
.O(sig000003b8)
);
XORCY blk000000df (
.CI(sig000003ba),
.LI(sig00000287),
.O(sig000002e1)
);
MUXCY blk000000e0 (
.CI(sig000003ba),
.DI(sig000006c3),
.S(sig00000287),
.O(sig000003b9)
);
XORCY blk000000e1 (
.CI(sig000003bb),
.LI(sig00000286),
.O(sig000002e0)
);
MUXCY blk000000e2 (
.CI(sig000003bb),
.DI(sig000006c3),
.S(sig00000286),
.O(sig000003ba)
);
XORCY blk000000e3 (
.CI(sig000003bc),
.LI(sig00000285),
.O(sig000002df)
);
MUXCY blk000000e4 (
.CI(sig000003bc),
.DI(sig000006c3),
.S(sig00000285),
.O(sig000003bb)
);
XORCY blk000000e5 (
.CI(sig000006c3),
.LI(sig00000284),
.O(sig000002de)
);
MUXCY blk000000e6 (
.CI(sig000006c3),
.DI(sig00000001),
.S(sig00000284),
.O(sig000003bc)
);
FD #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.D(sig000002e9),
.Q(sig000002dd)
);
FD #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.D(sig000002e8),
.Q(sig000002dc)
);
FD #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.D(sig000002e7),
.Q(sig000002db)
);
FD #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.D(sig000002e6),
.Q(sig000002da)
);
FD #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.D(sig000002e5),
.Q(sig000002d9)
);
FD #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.D(sig000002e4),
.Q(sig000002d8)
);
FD #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.D(sig000002e3),
.Q(sig000002d7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.D(sig000002e2),
.Q(sig000002d6)
);
FD #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.D(sig000002e1),
.Q(sig000002d5)
);
FD #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.D(sig000002e0),
.Q(sig000002d4)
);
FD #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.D(sig000002df),
.Q(sig000002d3)
);
FD #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.D(sig000002de),
.Q(sig000002d2)
);
FD #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.D(sig0000028f),
.Q(sig000003bd)
);
FD #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.D(sig000003c8),
.Q(sig00000239)
);
FD #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.D(sig000003c7),
.Q(sig00000238)
);
FD #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.D(sig000003c6),
.Q(sig00000237)
);
FD #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.D(sig000003c5),
.Q(sig00000236)
);
FD #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.D(sig000003c4),
.Q(sig00000235)
);
FD #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.D(sig000003c3),
.Q(sig00000234)
);
FD #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.D(sig000003c2),
.Q(sig00000233)
);
FD #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.D(sig000003c1),
.Q(sig00000232)
);
FD #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.D(sig000003c0),
.Q(sig00000231)
);
FD #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.D(sig000003bf),
.Q(sig00000230)
);
FD #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.D(sig000003be),
.Q(sig0000022f)
);
FD #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.D(sig000002c3),
.Q(sig000003c8)
);
FD #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.D(sig000002c2),
.Q(sig000003c7)
);
FD #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.D(sig000002c1),
.Q(sig000003c6)
);
FD #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.D(sig000002c0),
.Q(sig000003c5)
);
FD #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.D(sig000002bf),
.Q(sig000003c4)
);
FD #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.D(sig000002be),
.Q(sig000003c3)
);
FD #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.D(sig000002bd),
.Q(sig000003c2)
);
FD #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.D(sig000002bc),
.Q(sig000003c1)
);
FD #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.D(sig000002bb),
.Q(sig000003c0)
);
FD #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.D(sig000002ba),
.Q(sig000003bf)
);
FD #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.D(sig000002b9),
.Q(sig000003be)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.CE(sig00000001),
.D(b[51]),
.Q(sig000001f6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.CE(sig00000001),
.D(b[50]),
.Q(sig000001f5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.CE(sig00000001),
.D(b[49]),
.Q(sig000001f4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.CE(sig00000001),
.D(b[48]),
.Q(sig000001f3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010e (
.C(clk),
.CE(sig00000001),
.D(b[47]),
.Q(sig000001f2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010f (
.C(clk),
.CE(sig00000001),
.D(b[46]),
.Q(sig000001f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000110 (
.C(clk),
.CE(sig00000001),
.D(b[45]),
.Q(sig000001f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000111 (
.C(clk),
.CE(sig00000001),
.D(b[44]),
.Q(sig000001ef)
);
FDE #(
.INIT ( 1'b0 ))
blk00000112 (
.C(clk),
.CE(sig00000001),
.D(b[43]),
.Q(sig000001ee)
);
FDE #(
.INIT ( 1'b0 ))
blk00000113 (
.C(clk),
.CE(sig00000001),
.D(b[42]),
.Q(sig000001ed)
);
FDE #(
.INIT ( 1'b0 ))
blk00000114 (
.C(clk),
.CE(sig00000001),
.D(b[41]),
.Q(sig000001ec)
);
FDE #(
.INIT ( 1'b0 ))
blk00000115 (
.C(clk),
.CE(sig00000001),
.D(b[40]),
.Q(sig000001eb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000116 (
.C(clk),
.CE(sig00000001),
.D(b[39]),
.Q(sig000001ea)
);
FDE #(
.INIT ( 1'b0 ))
blk00000117 (
.C(clk),
.CE(sig00000001),
.D(b[38]),
.Q(sig000001e9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000118 (
.C(clk),
.CE(sig00000001),
.D(b[37]),
.Q(sig000001e8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000119 (
.C(clk),
.CE(sig00000001),
.D(b[36]),
.Q(sig000001e7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011a (
.C(clk),
.CE(sig00000001),
.D(b[35]),
.Q(sig000001e6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011b (
.C(clk),
.CE(sig00000001),
.D(b[34]),
.Q(sig000001e5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011c (
.C(clk),
.CE(sig00000001),
.D(b[33]),
.Q(sig000001e4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011d (
.C(clk),
.CE(sig00000001),
.D(b[32]),
.Q(sig000001e3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011e (
.C(clk),
.CE(sig00000001),
.D(b[31]),
.Q(sig000001e2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011f (
.C(clk),
.CE(sig00000001),
.D(b[30]),
.Q(sig000001e1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000120 (
.C(clk),
.CE(sig00000001),
.D(b[29]),
.Q(sig000001e0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000121 (
.C(clk),
.CE(sig00000001),
.D(b[28]),
.Q(sig000001df)
);
FDE #(
.INIT ( 1'b0 ))
blk00000122 (
.C(clk),
.CE(sig00000001),
.D(b[27]),
.Q(sig000001de)
);
FDE #(
.INIT ( 1'b0 ))
blk00000123 (
.C(clk),
.CE(sig00000001),
.D(b[26]),
.Q(sig000001dd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000124 (
.C(clk),
.CE(sig00000001),
.D(b[25]),
.Q(sig000001dc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000125 (
.C(clk),
.CE(sig00000001),
.D(b[24]),
.Q(sig000001db)
);
FDE #(
.INIT ( 1'b0 ))
blk00000126 (
.C(clk),
.CE(sig00000001),
.D(b[23]),
.Q(sig000001da)
);
FDE #(
.INIT ( 1'b0 ))
blk00000127 (
.C(clk),
.CE(sig00000001),
.D(b[22]),
.Q(sig000001d9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000128 (
.C(clk),
.CE(sig00000001),
.D(b[21]),
.Q(sig000001d8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000129 (
.C(clk),
.CE(sig00000001),
.D(b[20]),
.Q(sig000001d7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012a (
.C(clk),
.CE(sig00000001),
.D(b[19]),
.Q(sig000001d6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012b (
.C(clk),
.CE(sig00000001),
.D(b[18]),
.Q(sig000001d5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012c (
.C(clk),
.CE(sig00000001),
.D(b[17]),
.Q(sig000001d4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012d (
.C(clk),
.CE(sig00000001),
.D(b[16]),
.Q(sig000001d3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012e (
.C(clk),
.CE(sig00000001),
.D(b[15]),
.Q(sig000001d2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012f (
.C(clk),
.CE(sig00000001),
.D(b[14]),
.Q(sig000001d1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000130 (
.C(clk),
.CE(sig00000001),
.D(b[13]),
.Q(sig000001d0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000131 (
.C(clk),
.CE(sig00000001),
.D(b[12]),
.Q(sig000001cf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000132 (
.C(clk),
.CE(sig00000001),
.D(b[11]),
.Q(sig000001ce)
);
FDE #(
.INIT ( 1'b0 ))
blk00000133 (
.C(clk),
.CE(sig00000001),
.D(b[10]),
.Q(sig000001cd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000134 (
.C(clk),
.CE(sig00000001),
.D(b[9]),
.Q(sig000001cc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000135 (
.C(clk),
.CE(sig00000001),
.D(b[8]),
.Q(sig000001cb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000136 (
.C(clk),
.CE(sig00000001),
.D(b[7]),
.Q(sig000001ca)
);
FDE #(
.INIT ( 1'b0 ))
blk00000137 (
.C(clk),
.CE(sig00000001),
.D(b[6]),
.Q(sig000001c9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000138 (
.C(clk),
.CE(sig00000001),
.D(b[5]),
.Q(sig000001c8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000139 (
.C(clk),
.CE(sig00000001),
.D(b[4]),
.Q(sig000001c7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013a (
.C(clk),
.CE(sig00000001),
.D(b[3]),
.Q(sig000001c6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013b (
.C(clk),
.CE(sig00000001),
.D(b[2]),
.Q(sig000001c5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013c (
.C(clk),
.CE(sig00000001),
.D(b[1]),
.Q(sig000001c4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013d (
.C(clk),
.CE(sig00000001),
.D(b[0]),
.Q(sig000001c3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013e (
.C(clk),
.CE(sig00000001),
.D(a[51]),
.Q(sig0000022a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013f (
.C(clk),
.CE(sig00000001),
.D(a[50]),
.Q(sig00000229)
);
FDE #(
.INIT ( 1'b0 ))
blk00000140 (
.C(clk),
.CE(sig00000001),
.D(a[49]),
.Q(sig00000228)
);
FDE #(
.INIT ( 1'b0 ))
blk00000141 (
.C(clk),
.CE(sig00000001),
.D(a[48]),
.Q(sig00000227)
);
FDE #(
.INIT ( 1'b0 ))
blk00000142 (
.C(clk),
.CE(sig00000001),
.D(a[47]),
.Q(sig00000226)
);
FDE #(
.INIT ( 1'b0 ))
blk00000143 (
.C(clk),
.CE(sig00000001),
.D(a[46]),
.Q(sig00000225)
);
FDE #(
.INIT ( 1'b0 ))
blk00000144 (
.C(clk),
.CE(sig00000001),
.D(a[45]),
.Q(sig00000224)
);
FDE #(
.INIT ( 1'b0 ))
blk00000145 (
.C(clk),
.CE(sig00000001),
.D(a[44]),
.Q(sig00000223)
);
FDE #(
.INIT ( 1'b0 ))
blk00000146 (
.C(clk),
.CE(sig00000001),
.D(a[43]),
.Q(sig00000222)
);
FDE #(
.INIT ( 1'b0 ))
blk00000147 (
.C(clk),
.CE(sig00000001),
.D(a[42]),
.Q(sig00000221)
);
FDE #(
.INIT ( 1'b0 ))
blk00000148 (
.C(clk),
.CE(sig00000001),
.D(a[41]),
.Q(sig00000220)
);
FDE #(
.INIT ( 1'b0 ))
blk00000149 (
.C(clk),
.CE(sig00000001),
.D(a[40]),
.Q(sig0000021f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014a (
.C(clk),
.CE(sig00000001),
.D(a[39]),
.Q(sig0000021e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014b (
.C(clk),
.CE(sig00000001),
.D(a[38]),
.Q(sig0000021d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.CE(sig00000001),
.D(a[37]),
.Q(sig0000021c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014d (
.C(clk),
.CE(sig00000001),
.D(a[36]),
.Q(sig0000021b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014e (
.C(clk),
.CE(sig00000001),
.D(a[35]),
.Q(sig0000021a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014f (
.C(clk),
.CE(sig00000001),
.D(a[34]),
.Q(sig00000219)
);
FDE #(
.INIT ( 1'b0 ))
blk00000150 (
.C(clk),
.CE(sig00000001),
.D(a[33]),
.Q(sig00000218)
);
FDE #(
.INIT ( 1'b0 ))
blk00000151 (
.C(clk),
.CE(sig00000001),
.D(a[32]),
.Q(sig00000217)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(sig00000001),
.D(a[31]),
.Q(sig00000216)
);
FDE #(
.INIT ( 1'b0 ))
blk00000153 (
.C(clk),
.CE(sig00000001),
.D(a[30]),
.Q(sig00000215)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(sig00000001),
.D(a[29]),
.Q(sig00000214)
);
FDE #(
.INIT ( 1'b0 ))
blk00000155 (
.C(clk),
.CE(sig00000001),
.D(a[28]),
.Q(sig00000213)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(sig00000001),
.D(a[27]),
.Q(sig00000212)
);
FDE #(
.INIT ( 1'b0 ))
blk00000157 (
.C(clk),
.CE(sig00000001),
.D(a[26]),
.Q(sig00000211)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(sig00000001),
.D(a[25]),
.Q(sig00000210)
);
FDE #(
.INIT ( 1'b0 ))
blk00000159 (
.C(clk),
.CE(sig00000001),
.D(a[24]),
.Q(sig0000020f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(sig00000001),
.D(a[23]),
.Q(sig0000020e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015b (
.C(clk),
.CE(sig00000001),
.D(a[22]),
.Q(sig0000020d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(sig00000001),
.D(a[21]),
.Q(sig0000020c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015d (
.C(clk),
.CE(sig00000001),
.D(a[20]),
.Q(sig0000020b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(sig00000001),
.D(a[19]),
.Q(sig0000020a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015f (
.C(clk),
.CE(sig00000001),
.D(a[18]),
.Q(sig00000209)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(sig00000001),
.D(a[17]),
.Q(sig00000208)
);
FDE #(
.INIT ( 1'b0 ))
blk00000161 (
.C(clk),
.CE(sig00000001),
.D(a[16]),
.Q(sig00000207)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(sig00000001),
.D(a[15]),
.Q(sig00000206)
);
FDE #(
.INIT ( 1'b0 ))
blk00000163 (
.C(clk),
.CE(sig00000001),
.D(a[14]),
.Q(sig00000205)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(sig00000001),
.D(a[13]),
.Q(sig00000204)
);
FDE #(
.INIT ( 1'b0 ))
blk00000165 (
.C(clk),
.CE(sig00000001),
.D(a[12]),
.Q(sig00000203)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(sig00000001),
.D(a[11]),
.Q(sig00000202)
);
FDE #(
.INIT ( 1'b0 ))
blk00000167 (
.C(clk),
.CE(sig00000001),
.D(a[10]),
.Q(sig00000201)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(sig00000001),
.D(a[9]),
.Q(sig00000200)
);
FDE #(
.INIT ( 1'b0 ))
blk00000169 (
.C(clk),
.CE(sig00000001),
.D(a[8]),
.Q(sig000001ff)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(sig00000001),
.D(a[7]),
.Q(sig000001fe)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016b (
.C(clk),
.CE(sig00000001),
.D(a[6]),
.Q(sig000001fd)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(sig00000001),
.D(a[5]),
.Q(sig000001fc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016d (
.C(clk),
.CE(sig00000001),
.D(a[4]),
.Q(sig000001fb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(sig00000001),
.D(a[3]),
.Q(sig000001fa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016f (
.C(clk),
.CE(sig00000001),
.D(a[2]),
.Q(sig000001f9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(sig00000001),
.D(a[1]),
.Q(sig000001f8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000171 (
.C(clk),
.CE(sig00000001),
.D(a[0]),
.Q(sig000001f7)
);
XORCY blk00000172 (
.CI(sig000003c9),
.LI(sig00000583),
.O(sig000004c6)
);
XORCY blk00000173 (
.CI(sig000003ca),
.LI(sig00000582),
.O(sig000004c5)
);
MUXCY blk00000174 (
.CI(sig000003ca),
.DI(sig000006c3),
.S(sig00000582),
.O(sig000003c9)
);
XORCY blk00000175 (
.CI(sig000003cb),
.LI(sig00000581),
.O(sig000004c4)
);
MUXCY blk00000176 (
.CI(sig000003cb),
.DI(sig000006c3),
.S(sig00000581),
.O(sig000003ca)
);
XORCY blk00000177 (
.CI(sig000003cc),
.LI(sig00000580),
.O(sig000004c3)
);
MUXCY blk00000178 (
.CI(sig000003cc),
.DI(sig000006c3),
.S(sig00000580),
.O(sig000003cb)
);
XORCY blk00000179 (
.CI(sig000003cd),
.LI(sig0000057f),
.O(sig000004c2)
);
MUXCY blk0000017a (
.CI(sig000003cd),
.DI(sig000006c3),
.S(sig0000057f),
.O(sig000003cc)
);
XORCY blk0000017b (
.CI(sig000003ce),
.LI(sig0000057e),
.O(sig000004c1)
);
MUXCY blk0000017c (
.CI(sig000003ce),
.DI(sig000006c3),
.S(sig0000057e),
.O(sig000003cd)
);
XORCY blk0000017d (
.CI(sig000003cf),
.LI(sig0000057d),
.O(sig000004c0)
);
MUXCY blk0000017e (
.CI(sig000003cf),
.DI(sig000006c3),
.S(sig0000057d),
.O(sig000003ce)
);
XORCY blk0000017f (
.CI(sig000003d0),
.LI(sig0000057c),
.O(sig000004bf)
);
MUXCY blk00000180 (
.CI(sig000003d0),
.DI(sig000006c3),
.S(sig0000057c),
.O(sig000003cf)
);
XORCY blk00000181 (
.CI(sig000003d1),
.LI(sig0000057b),
.O(sig000004be)
);
MUXCY blk00000182 (
.CI(sig000003d1),
.DI(sig000006c3),
.S(sig0000057b),
.O(sig000003d0)
);
XORCY blk00000183 (
.CI(sig000003d2),
.LI(sig0000057a),
.O(sig000004bd)
);
MUXCY blk00000184 (
.CI(sig000003d2),
.DI(sig000006c3),
.S(sig0000057a),
.O(sig000003d1)
);
XORCY blk00000185 (
.CI(sig000006c3),
.LI(sig00000828),
.O(sig000004bc)
);
MUXCY blk00000186 (
.CI(sig000006c3),
.DI(sig0000024a),
.S(sig00000828),
.O(sig000003d2)
);
FD #(
.INIT ( 1'b0 ))
blk00000187 (
.C(clk),
.D(sig000004b8),
.Q(sig000004c7)
);
FD #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.D(sig000004b7),
.Q(sig000004c8)
);
FD #(
.INIT ( 1'b0 ))
blk00000189 (
.C(clk),
.D(sig000004ba),
.Q(sig000004c9)
);
FD #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.D(sig000004cc),
.Q(sig000003d3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018b (
.C(clk),
.CE(sig00000001),
.D(sig000004d0),
.Q(sig0000040e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.CE(sig00000001),
.D(sig000004d1),
.Q(sig0000040d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018d (
.C(clk),
.CE(sig00000001),
.D(sig000004b4),
.Q(sig0000050d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.CE(sig00000001),
.D(sig0000022c),
.Q(sig000004b5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018f (
.C(clk),
.CE(sig00000001),
.D(sig000004b5),
.Q(sig00000544)
);
FDE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.CE(sig00000001),
.D(sig000004b6),
.Q(sig000004b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000191 (
.C(clk),
.CE(sig00000001),
.D(sig000004cf),
.Q(sig000004cb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000192 (
.C(clk),
.CE(sig00000001),
.D(sig000004b9),
.Q(sig000004cd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000193 (
.C(clk),
.CE(sig00000001),
.D(sig000004bb),
.Q(sig000004ca)
);
FD #(
.INIT ( 1'b0 ))
blk00000194 (
.C(clk),
.D(sig00000543),
.Q(sig0000050c)
);
FD #(
.INIT ( 1'b0 ))
blk00000195 (
.C(clk),
.D(sig00000542),
.Q(sig0000050b)
);
FD #(
.INIT ( 1'b0 ))
blk00000196 (
.C(clk),
.D(sig00000541),
.Q(sig0000050a)
);
FD #(
.INIT ( 1'b0 ))
blk00000197 (
.C(clk),
.D(sig00000540),
.Q(sig00000509)
);
FD #(
.INIT ( 1'b0 ))
blk00000198 (
.C(clk),
.D(sig0000053f),
.Q(sig00000508)
);
FD #(
.INIT ( 1'b0 ))
blk00000199 (
.C(clk),
.D(sig0000053e),
.Q(sig00000507)
);
FD #(
.INIT ( 1'b0 ))
blk0000019a (
.C(clk),
.D(sig0000053d),
.Q(sig00000506)
);
FD #(
.INIT ( 1'b0 ))
blk0000019b (
.C(clk),
.D(sig0000053c),
.Q(sig00000505)
);
FD #(
.INIT ( 1'b0 ))
blk0000019c (
.C(clk),
.D(sig0000053b),
.Q(sig00000504)
);
FD #(
.INIT ( 1'b0 ))
blk0000019d (
.C(clk),
.D(sig0000053a),
.Q(sig00000503)
);
FD #(
.INIT ( 1'b0 ))
blk0000019e (
.C(clk),
.D(sig00000539),
.Q(sig00000502)
);
FD #(
.INIT ( 1'b0 ))
blk0000019f (
.C(clk),
.D(sig00000538),
.Q(sig00000501)
);
FD #(
.INIT ( 1'b0 ))
blk000001a0 (
.C(clk),
.D(sig00000537),
.Q(sig00000500)
);
FD #(
.INIT ( 1'b0 ))
blk000001a1 (
.C(clk),
.D(sig00000536),
.Q(sig000004ff)
);
FD #(
.INIT ( 1'b0 ))
blk000001a2 (
.C(clk),
.D(sig00000535),
.Q(sig000004fe)
);
FD #(
.INIT ( 1'b0 ))
blk000001a3 (
.C(clk),
.D(sig00000534),
.Q(sig000004fd)
);
FD #(
.INIT ( 1'b0 ))
blk000001a4 (
.C(clk),
.D(sig00000533),
.Q(sig000004fc)
);
FD #(
.INIT ( 1'b0 ))
blk000001a5 (
.C(clk),
.D(sig00000532),
.Q(sig000004fb)
);
FD #(
.INIT ( 1'b0 ))
blk000001a6 (
.C(clk),
.D(sig00000531),
.Q(sig000004fa)
);
FD #(
.INIT ( 1'b0 ))
blk000001a7 (
.C(clk),
.D(sig00000530),
.Q(sig000004f9)
);
FD #(
.INIT ( 1'b0 ))
blk000001a8 (
.C(clk),
.D(sig0000052f),
.Q(sig000004f8)
);
FD #(
.INIT ( 1'b0 ))
blk000001a9 (
.C(clk),
.D(sig0000052e),
.Q(sig000004f7)
);
FD #(
.INIT ( 1'b0 ))
blk000001aa (
.C(clk),
.D(sig0000052d),
.Q(sig000004f6)
);
FD #(
.INIT ( 1'b0 ))
blk000001ab (
.C(clk),
.D(sig0000052c),
.Q(sig000004f5)
);
FD #(
.INIT ( 1'b0 ))
blk000001ac (
.C(clk),
.D(sig0000052b),
.Q(sig000004f4)
);
FD #(
.INIT ( 1'b0 ))
blk000001ad (
.C(clk),
.D(sig0000052a),
.Q(sig000004f3)
);
FD #(
.INIT ( 1'b0 ))
blk000001ae (
.C(clk),
.D(sig00000529),
.Q(sig000004f2)
);
FD #(
.INIT ( 1'b0 ))
blk000001af (
.C(clk),
.D(sig00000528),
.Q(sig000004f1)
);
FD #(
.INIT ( 1'b0 ))
blk000001b0 (
.C(clk),
.D(sig00000527),
.Q(sig000004f0)
);
FD #(
.INIT ( 1'b0 ))
blk000001b1 (
.C(clk),
.D(sig00000526),
.Q(sig000004ef)
);
FD #(
.INIT ( 1'b0 ))
blk000001b2 (
.C(clk),
.D(sig00000525),
.Q(sig000004ee)
);
FD #(
.INIT ( 1'b0 ))
blk000001b3 (
.C(clk),
.D(sig00000524),
.Q(sig000004ed)
);
FD #(
.INIT ( 1'b0 ))
blk000001b4 (
.C(clk),
.D(sig00000523),
.Q(sig000004ec)
);
FD #(
.INIT ( 1'b0 ))
blk000001b5 (
.C(clk),
.D(sig00000522),
.Q(sig000004eb)
);
FD #(
.INIT ( 1'b0 ))
blk000001b6 (
.C(clk),
.D(sig00000521),
.Q(sig000004ea)
);
FD #(
.INIT ( 1'b0 ))
blk000001b7 (
.C(clk),
.D(sig00000520),
.Q(sig000004e9)
);
FD #(
.INIT ( 1'b0 ))
blk000001b8 (
.C(clk),
.D(sig0000051f),
.Q(sig000004e8)
);
FD #(
.INIT ( 1'b0 ))
blk000001b9 (
.C(clk),
.D(sig0000051e),
.Q(sig000004e7)
);
FD #(
.INIT ( 1'b0 ))
blk000001ba (
.C(clk),
.D(sig0000051d),
.Q(sig000004e6)
);
FD #(
.INIT ( 1'b0 ))
blk000001bb (
.C(clk),
.D(sig0000051c),
.Q(sig000004e5)
);
FD #(
.INIT ( 1'b0 ))
blk000001bc (
.C(clk),
.D(sig0000051b),
.Q(sig000004e4)
);
FD #(
.INIT ( 1'b0 ))
blk000001bd (
.C(clk),
.D(sig0000051a),
.Q(sig000004e3)
);
FD #(
.INIT ( 1'b0 ))
blk000001be (
.C(clk),
.D(sig00000519),
.Q(sig000004e2)
);
FD #(
.INIT ( 1'b0 ))
blk000001bf (
.C(clk),
.D(sig00000518),
.Q(sig000004e1)
);
FD #(
.INIT ( 1'b0 ))
blk000001c0 (
.C(clk),
.D(sig00000517),
.Q(sig000004e0)
);
FD #(
.INIT ( 1'b0 ))
blk000001c1 (
.C(clk),
.D(sig00000516),
.Q(sig000004df)
);
FD #(
.INIT ( 1'b0 ))
blk000001c2 (
.C(clk),
.D(sig00000515),
.Q(sig000004de)
);
FD #(
.INIT ( 1'b0 ))
blk000001c3 (
.C(clk),
.D(sig00000514),
.Q(sig000004dd)
);
FD #(
.INIT ( 1'b0 ))
blk000001c4 (
.C(clk),
.D(sig00000513),
.Q(sig000004dc)
);
FD #(
.INIT ( 1'b0 ))
blk000001c5 (
.C(clk),
.D(sig00000512),
.Q(sig000004db)
);
FD #(
.INIT ( 1'b0 ))
blk000001c6 (
.C(clk),
.D(sig00000511),
.Q(sig000004da)
);
FD #(
.INIT ( 1'b0 ))
blk000001c7 (
.C(clk),
.D(sig00000510),
.Q(sig000004d9)
);
FD #(
.INIT ( 1'b0 ))
blk000001c8 (
.C(clk),
.D(sig0000050f),
.Q(sig000004d8)
);
FD #(
.INIT ( 1'b0 ))
blk000001c9 (
.C(clk),
.D(sig0000050e),
.Q(sig000004d7)
);
FD #(
.INIT ( 1'b0 ))
blk000001ca (
.C(clk),
.D(sig000004c6),
.Q(sig000004d6)
);
FD #(
.INIT ( 1'b0 ))
blk000001cb (
.C(clk),
.D(sig000004c5),
.Q(sig000004d5)
);
FD #(
.INIT ( 1'b0 ))
blk000001cc (
.C(clk),
.D(sig000004c4),
.Q(sig000004d4)
);
FD #(
.INIT ( 1'b0 ))
blk000001cd (
.C(clk),
.D(sig000004c3),
.Q(sig000004d3)
);
FD #(
.INIT ( 1'b0 ))
blk000001ce (
.C(clk),
.D(sig000004c2),
.Q(sig000004d2)
);
FD #(
.INIT ( 1'b0 ))
blk000001cf (
.C(clk),
.D(sig000004c1),
.Q(sig000003d4)
);
FD #(
.INIT ( 1'b0 ))
blk000001d0 (
.C(clk),
.D(sig000004c0),
.Q(sig000003d5)
);
FD #(
.INIT ( 1'b0 ))
blk000001d1 (
.C(clk),
.D(sig000004bf),
.Q(sig000004d1)
);
FD #(
.INIT ( 1'b0 ))
blk000001d2 (
.C(clk),
.D(sig000004be),
.Q(sig000004d0)
);
FD #(
.INIT ( 1'b0 ))
blk000001d3 (
.C(clk),
.D(sig000004bd),
.Q(sig000004cf)
);
FD #(
.INIT ( 1'b0 ))
blk000001d4 (
.C(clk),
.D(sig000004bc),
.Q(sig000004ce)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d5 (
.C(clk),
.CE(sig00000001),
.D(sig0000040f),
.Q(sig000003d6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d6 (
.C(clk),
.CE(sig00000001),
.D(sig00000410),
.Q(sig000003d7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d7 (
.C(clk),
.CE(sig00000001),
.D(sig00000411),
.Q(sig000003d8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d8 (
.C(clk),
.CE(sig00000001),
.D(sig00000412),
.Q(sig000003d9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001d9 (
.C(clk),
.CE(sig00000001),
.D(sig00000413),
.Q(sig000003da)
);
FDE #(
.INIT ( 1'b0 ))
blk000001da (
.C(clk),
.CE(sig00000001),
.D(sig00000414),
.Q(sig000003db)
);
FDE #(
.INIT ( 1'b0 ))
blk000001db (
.C(clk),
.CE(sig00000001),
.D(sig00000415),
.Q(sig000003dc)
);
FDE #(
.INIT ( 1'b0 ))
blk000001dc (
.C(clk),
.CE(sig00000001),
.D(sig00000416),
.Q(sig000003dd)
);
FDE #(
.INIT ( 1'b0 ))
blk000001dd (
.C(clk),
.CE(sig00000001),
.D(sig00000417),
.Q(sig000003de)
);
FDE #(
.INIT ( 1'b0 ))
blk000001de (
.C(clk),
.CE(sig00000001),
.D(sig00000418),
.Q(sig000003df)
);
FDE #(
.INIT ( 1'b0 ))
blk000001df (
.C(clk),
.CE(sig00000001),
.D(sig00000419),
.Q(sig000003e0)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e0 (
.C(clk),
.CE(sig00000001),
.D(sig0000041a),
.Q(sig000003e1)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e1 (
.C(clk),
.CE(sig00000001),
.D(sig0000041b),
.Q(sig000003e2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e2 (
.C(clk),
.CE(sig00000001),
.D(sig0000041c),
.Q(sig000003e3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e3 (
.C(clk),
.CE(sig00000001),
.D(sig0000041d),
.Q(sig000003e4)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e4 (
.C(clk),
.CE(sig00000001),
.D(sig0000041e),
.Q(sig000003e5)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e5 (
.C(clk),
.CE(sig00000001),
.D(sig0000041f),
.Q(sig000003e6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e6 (
.C(clk),
.CE(sig00000001),
.D(sig00000420),
.Q(sig000003e7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e7 (
.C(clk),
.CE(sig00000001),
.D(sig00000421),
.Q(sig000003e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e8 (
.C(clk),
.CE(sig00000001),
.D(sig00000422),
.Q(sig000003e9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e9 (
.C(clk),
.CE(sig00000001),
.D(sig00000423),
.Q(sig000003ea)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ea (
.C(clk),
.CE(sig00000001),
.D(sig00000424),
.Q(sig000003eb)
);
FDE #(
.INIT ( 1'b0 ))
blk000001eb (
.C(clk),
.CE(sig00000001),
.D(sig00000425),
.Q(sig000003ec)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ec (
.C(clk),
.CE(sig00000001),
.D(sig00000426),
.Q(sig000003ed)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ed (
.C(clk),
.CE(sig00000001),
.D(sig00000427),
.Q(sig000003ee)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ee (
.C(clk),
.CE(sig00000001),
.D(sig00000428),
.Q(sig000003ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ef (
.C(clk),
.CE(sig00000001),
.D(sig00000429),
.Q(sig000003f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f0 (
.C(clk),
.CE(sig00000001),
.D(sig0000042a),
.Q(sig000003f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f1 (
.C(clk),
.CE(sig00000001),
.D(sig0000042b),
.Q(sig000003f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f2 (
.C(clk),
.CE(sig00000001),
.D(sig0000042c),
.Q(sig000003f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f3 (
.C(clk),
.CE(sig00000001),
.D(sig0000042d),
.Q(sig000003f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f4 (
.C(clk),
.CE(sig00000001),
.D(sig0000042e),
.Q(sig000003f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f5 (
.C(clk),
.CE(sig00000001),
.D(sig0000042f),
.Q(sig000003f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f6 (
.C(clk),
.CE(sig00000001),
.D(sig00000430),
.Q(sig000003f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f7 (
.C(clk),
.CE(sig00000001),
.D(sig00000431),
.Q(sig000003f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f8 (
.C(clk),
.CE(sig00000001),
.D(sig00000432),
.Q(sig000003f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f9 (
.C(clk),
.CE(sig00000001),
.D(sig00000433),
.Q(sig000003fa)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fa (
.C(clk),
.CE(sig00000001),
.D(sig00000434),
.Q(sig000003fb)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fb (
.C(clk),
.CE(sig00000001),
.D(sig00000435),
.Q(sig000003fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fc (
.C(clk),
.CE(sig00000001),
.D(sig00000436),
.Q(sig000003fd)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fd (
.C(clk),
.CE(sig00000001),
.D(sig00000437),
.Q(sig000003fe)
);
FDE #(
.INIT ( 1'b0 ))
blk000001fe (
.C(clk),
.CE(sig00000001),
.D(sig00000438),
.Q(sig000003ff)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ff (
.C(clk),
.CE(sig00000001),
.D(sig00000439),
.Q(sig00000400)
);
FDE #(
.INIT ( 1'b0 ))
blk00000200 (
.C(clk),
.CE(sig00000001),
.D(sig0000043a),
.Q(sig00000401)
);
FDE #(
.INIT ( 1'b0 ))
blk00000201 (
.C(clk),
.CE(sig00000001),
.D(sig0000043b),
.Q(sig00000402)
);
FDE #(
.INIT ( 1'b0 ))
blk00000202 (
.C(clk),
.CE(sig00000001),
.D(sig0000043c),
.Q(sig00000403)
);
FDE #(
.INIT ( 1'b0 ))
blk00000203 (
.C(clk),
.CE(sig00000001),
.D(sig0000043d),
.Q(sig00000404)
);
FDE #(
.INIT ( 1'b0 ))
blk00000204 (
.C(clk),
.CE(sig00000001),
.D(sig0000043e),
.Q(sig00000405)
);
FDE #(
.INIT ( 1'b0 ))
blk00000205 (
.C(clk),
.CE(sig00000001),
.D(sig0000043f),
.Q(sig00000406)
);
FDE #(
.INIT ( 1'b0 ))
blk00000206 (
.C(clk),
.CE(sig00000001),
.D(sig00000440),
.Q(sig00000407)
);
FDE #(
.INIT ( 1'b0 ))
blk00000207 (
.C(clk),
.CE(sig00000001),
.D(sig00000441),
.Q(sig00000408)
);
FDE #(
.INIT ( 1'b0 ))
blk00000208 (
.C(clk),
.CE(sig00000001),
.D(sig00000442),
.Q(sig00000409)
);
FDE #(
.INIT ( 1'b0 ))
blk00000209 (
.C(clk),
.CE(sig00000001),
.D(sig00000443),
.Q(sig0000040a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020a (
.C(clk),
.CE(sig00000001),
.D(sig00000444),
.Q(sig0000040b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020b (
.C(clk),
.CE(sig00000001),
.D(sig00000445),
.Q(sig0000040c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020c (
.C(clk),
.CE(sig00000001),
.D(sig00000446),
.Q(sig0000047d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020d (
.C(clk),
.CE(sig00000001),
.D(sig00000447),
.Q(sig0000047e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020e (
.C(clk),
.CE(sig00000001),
.D(sig00000448),
.Q(sig0000047f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000020f (
.C(clk),
.CE(sig00000001),
.D(sig00000449),
.Q(sig00000480)
);
FDE #(
.INIT ( 1'b0 ))
blk00000210 (
.C(clk),
.CE(sig00000001),
.D(sig0000044a),
.Q(sig00000481)
);
FDE #(
.INIT ( 1'b0 ))
blk00000211 (
.C(clk),
.CE(sig00000001),
.D(sig0000044b),
.Q(sig00000482)
);
FDE #(
.INIT ( 1'b0 ))
blk00000212 (
.C(clk),
.CE(sig00000001),
.D(sig0000044c),
.Q(sig00000483)
);
FDE #(
.INIT ( 1'b0 ))
blk00000213 (
.C(clk),
.CE(sig00000001),
.D(sig0000044d),
.Q(sig00000484)
);
FDE #(
.INIT ( 1'b0 ))
blk00000214 (
.C(clk),
.CE(sig00000001),
.D(sig0000044e),
.Q(sig00000485)
);
FDE #(
.INIT ( 1'b0 ))
blk00000215 (
.C(clk),
.CE(sig00000001),
.D(sig0000044f),
.Q(sig00000486)
);
FDE #(
.INIT ( 1'b0 ))
blk00000216 (
.C(clk),
.CE(sig00000001),
.D(sig00000450),
.Q(sig00000487)
);
FDE #(
.INIT ( 1'b0 ))
blk00000217 (
.C(clk),
.CE(sig00000001),
.D(sig00000451),
.Q(sig00000488)
);
FDE #(
.INIT ( 1'b0 ))
blk00000218 (
.C(clk),
.CE(sig00000001),
.D(sig00000452),
.Q(sig00000489)
);
FDE #(
.INIT ( 1'b0 ))
blk00000219 (
.C(clk),
.CE(sig00000001),
.D(sig00000453),
.Q(sig0000048a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021a (
.C(clk),
.CE(sig00000001),
.D(sig00000454),
.Q(sig0000048b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021b (
.C(clk),
.CE(sig00000001),
.D(sig00000455),
.Q(sig0000048c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021c (
.C(clk),
.CE(sig00000001),
.D(sig00000456),
.Q(sig0000048d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021d (
.C(clk),
.CE(sig00000001),
.D(sig00000457),
.Q(sig0000048e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021e (
.C(clk),
.CE(sig00000001),
.D(sig00000458),
.Q(sig0000048f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000021f (
.C(clk),
.CE(sig00000001),
.D(sig00000459),
.Q(sig00000490)
);
FDE #(
.INIT ( 1'b0 ))
blk00000220 (
.C(clk),
.CE(sig00000001),
.D(sig0000045a),
.Q(sig00000491)
);
FDE #(
.INIT ( 1'b0 ))
blk00000221 (
.C(clk),
.CE(sig00000001),
.D(sig0000045b),
.Q(sig00000492)
);
FDE #(
.INIT ( 1'b0 ))
blk00000222 (
.C(clk),
.CE(sig00000001),
.D(sig0000045c),
.Q(sig00000493)
);
FDE #(
.INIT ( 1'b0 ))
blk00000223 (
.C(clk),
.CE(sig00000001),
.D(sig0000045d),
.Q(sig00000494)
);
FDE #(
.INIT ( 1'b0 ))
blk00000224 (
.C(clk),
.CE(sig00000001),
.D(sig0000045e),
.Q(sig00000495)
);
FDE #(
.INIT ( 1'b0 ))
blk00000225 (
.C(clk),
.CE(sig00000001),
.D(sig0000045f),
.Q(sig00000496)
);
FDE #(
.INIT ( 1'b0 ))
blk00000226 (
.C(clk),
.CE(sig00000001),
.D(sig00000460),
.Q(sig00000497)
);
FDE #(
.INIT ( 1'b0 ))
blk00000227 (
.C(clk),
.CE(sig00000001),
.D(sig00000461),
.Q(sig00000498)
);
FDE #(
.INIT ( 1'b0 ))
blk00000228 (
.C(clk),
.CE(sig00000001),
.D(sig00000462),
.Q(sig00000499)
);
FDE #(
.INIT ( 1'b0 ))
blk00000229 (
.C(clk),
.CE(sig00000001),
.D(sig00000463),
.Q(sig0000049a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022a (
.C(clk),
.CE(sig00000001),
.D(sig00000464),
.Q(sig0000049b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022b (
.C(clk),
.CE(sig00000001),
.D(sig00000465),
.Q(sig0000049c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022c (
.C(clk),
.CE(sig00000001),
.D(sig00000466),
.Q(sig0000049d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022d (
.C(clk),
.CE(sig00000001),
.D(sig00000467),
.Q(sig0000049e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022e (
.C(clk),
.CE(sig00000001),
.D(sig00000468),
.Q(sig0000049f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000022f (
.C(clk),
.CE(sig00000001),
.D(sig00000469),
.Q(sig000004a0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000230 (
.C(clk),
.CE(sig00000001),
.D(sig0000046a),
.Q(sig000004a1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000231 (
.C(clk),
.CE(sig00000001),
.D(sig0000046b),
.Q(sig000004a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000232 (
.C(clk),
.CE(sig00000001),
.D(sig0000046c),
.Q(sig000004a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000233 (
.C(clk),
.CE(sig00000001),
.D(sig0000046d),
.Q(sig000004a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000234 (
.C(clk),
.CE(sig00000001),
.D(sig0000046e),
.Q(sig000004a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000235 (
.C(clk),
.CE(sig00000001),
.D(sig0000046f),
.Q(sig000004a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000236 (
.C(clk),
.CE(sig00000001),
.D(sig00000470),
.Q(sig000004a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000237 (
.C(clk),
.CE(sig00000001),
.D(sig00000471),
.Q(sig000004a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000238 (
.C(clk),
.CE(sig00000001),
.D(sig00000472),
.Q(sig000004a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000239 (
.C(clk),
.CE(sig00000001),
.D(sig00000473),
.Q(sig000004aa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023a (
.C(clk),
.CE(sig00000001),
.D(sig00000474),
.Q(sig000004ab)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023b (
.C(clk),
.CE(sig00000001),
.D(sig00000475),
.Q(sig000004ac)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023c (
.C(clk),
.CE(sig00000001),
.D(sig00000476),
.Q(sig000004ad)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023d (
.C(clk),
.CE(sig00000001),
.D(sig00000477),
.Q(sig000004ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023e (
.C(clk),
.CE(sig00000001),
.D(sig00000478),
.Q(sig000004af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023f (
.C(clk),
.CE(sig00000001),
.D(sig00000479),
.Q(sig000004b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000240 (
.C(clk),
.CE(sig00000001),
.D(sig0000047a),
.Q(sig000004b1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000241 (
.C(clk),
.CE(sig00000001),
.D(sig0000047b),
.Q(sig000004b2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000242 (
.C(clk),
.CE(sig00000001),
.D(sig0000047c),
.Q(sig000004b3)
);
MUXF8 blk00000243 (
.I0(sig00000586),
.I1(sig00000585),
.S(sig00000595),
.O(sig00000584)
);
MUXF7 blk00000244 (
.I0(sig00000598),
.I1(sig00000597),
.S(sig00000596),
.O(sig00000585)
);
MUXF7 blk00000245 (
.I0(sig0000059a),
.I1(sig00000599),
.S(sig00000596),
.O(sig00000586)
);
FDE #(
.INIT ( 1'b0 ))
blk00000246 (
.C(clk),
.CE(sig00000001),
.D(sig000003d5),
.Q(sig00000596)
);
FDE #(
.INIT ( 1'b0 ))
blk00000247 (
.C(clk),
.CE(sig00000001),
.D(sig000003d4),
.Q(sig00000595)
);
MUXCY blk00000248 (
.CI(sig000005c7),
.DI(sig000006c3),
.S(sig000005b7),
.O(sig000005c6)
);
MUXCY blk00000249 (
.CI(sig000005c8),
.DI(sig000006c3),
.S(sig000005b8),
.O(sig000005c7)
);
MUXCY blk0000024a (
.CI(sig000005c9),
.DI(sig000006c3),
.S(sig000005b9),
.O(sig000005c8)
);
MUXCY blk0000024b (
.CI(sig000005ca),
.DI(sig000006c3),
.S(sig000005ba),
.O(sig000005c9)
);
MUXCY blk0000024c (
.CI(sig000005cb),
.DI(sig000006c3),
.S(sig000005bb),
.O(sig000005ca)
);
MUXCY blk0000024d (
.CI(sig000005cc),
.DI(sig000006c3),
.S(sig000005bc),
.O(sig000005cb)
);
MUXCY blk0000024e (
.CI(sig000005cd),
.DI(sig000006c3),
.S(sig000005bd),
.O(sig000005cc)
);
MUXCY blk0000024f (
.CI(sig000005ce),
.DI(sig000006c3),
.S(sig000005be),
.O(sig000005cd)
);
MUXCY blk00000250 (
.CI(sig000005cf),
.DI(sig000006c3),
.S(sig000005bf),
.O(sig000005ce)
);
MUXCY blk00000251 (
.CI(sig000005d0),
.DI(sig000006c3),
.S(sig000005c0),
.O(sig000005cf)
);
MUXCY blk00000252 (
.CI(sig000005d1),
.DI(sig000006c3),
.S(sig000005c1),
.O(sig000005d0)
);
MUXCY blk00000253 (
.CI(sig000005d2),
.DI(sig000006c3),
.S(sig000005c2),
.O(sig000005d1)
);
MUXCY blk00000254 (
.CI(sig000005d3),
.DI(sig000006c3),
.S(sig000005c3),
.O(sig000005d2)
);
MUXCY blk00000255 (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000005c4),
.O(sig000005d3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000256 (
.C(clk),
.CE(sig00000001),
.D(sig000005c6),
.Q(sig000005c5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000257 (
.C(clk),
.CE(sig00000001),
.D(sig000005c7),
.Q(sig000005ab)
);
FDE #(
.INIT ( 1'b0 ))
blk00000258 (
.C(clk),
.CE(sig00000001),
.D(sig000005c8),
.Q(sig000005aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000259 (
.C(clk),
.CE(sig00000001),
.D(sig000005c9),
.Q(sig000005ad)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025a (
.C(clk),
.CE(sig00000001),
.D(sig000005ca),
.Q(sig000005ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025b (
.C(clk),
.CE(sig00000001),
.D(sig000005cb),
.Q(sig000005af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025c (
.C(clk),
.CE(sig00000001),
.D(sig000005cc),
.Q(sig000005ac)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025d (
.C(clk),
.CE(sig00000001),
.D(sig000005cd),
.Q(sig000005b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025e (
.C(clk),
.CE(sig00000001),
.D(sig000005ce),
.Q(sig000005b2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025f (
.C(clk),
.CE(sig00000001),
.D(sig000005cf),
.Q(sig000005b3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000260 (
.C(clk),
.CE(sig00000001),
.D(sig000005d0),
.Q(sig000005b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000261 (
.C(clk),
.CE(sig00000001),
.D(sig000005d1),
.Q(sig000005b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000262 (
.C(clk),
.CE(sig00000001),
.D(sig000005d2),
.Q(sig000005b5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000263 (
.C(clk),
.CE(sig00000001),
.D(sig000005d3),
.Q(sig000005b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000264 (
.C(clk),
.CE(sig00000001),
.D(sig00000584),
.Q(sig000004cc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000265 (
.C(clk),
.CE(sig00000001),
.D(sig00000001),
.Q(sig0000059c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000266 (
.C(clk),
.CE(sig00000001),
.D(sig00000587),
.Q(sig0000059d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000267 (
.C(clk),
.CE(sig00000001),
.D(sig00000588),
.Q(sig0000059b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000268 (
.C(clk),
.CE(sig00000001),
.D(sig00000589),
.Q(sig0000059f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000269 (
.C(clk),
.CE(sig00000001),
.D(sig0000058a),
.Q(sig000005a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026a (
.C(clk),
.CE(sig00000001),
.D(sig0000058b),
.Q(sig000005a1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026b (
.C(clk),
.CE(sig00000001),
.D(sig0000058c),
.Q(sig0000059e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026c (
.C(clk),
.CE(sig00000001),
.D(sig0000058d),
.Q(sig000005a3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026d (
.C(clk),
.CE(sig00000001),
.D(sig0000058e),
.Q(sig000005a4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026e (
.C(clk),
.CE(sig00000001),
.D(sig0000058f),
.Q(sig000005a5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000026f (
.C(clk),
.CE(sig00000001),
.D(sig00000590),
.Q(sig000005a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000270 (
.C(clk),
.CE(sig00000001),
.D(sig00000591),
.Q(sig000005a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000271 (
.C(clk),
.CE(sig00000001),
.D(sig00000592),
.Q(sig000005a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000272 (
.C(clk),
.CE(sig00000001),
.D(sig00000593),
.Q(sig000005a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000273 (
.C(clk),
.CE(sig00000001),
.D(sig00000594),
.Q(sig000005a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000274 (
.C(clk),
.CE(sig00000001),
.D(sig000004ca),
.Q(sig00000697)
);
FDE #(
.INIT ( 1'b0 ))
blk00000275 (
.C(clk),
.CE(sig00000001),
.D(sig0000050d),
.Q(sig00000696)
);
FD #(
.INIT ( 1'b0 ))
blk00000276 (
.C(clk),
.D(sig00000571),
.Q(sig00000665)
);
FD #(
.INIT ( 1'b0 ))
blk00000277 (
.C(clk),
.D(sig00000570),
.Q(sig00000664)
);
FD #(
.INIT ( 1'b0 ))
blk00000278 (
.C(clk),
.D(sig0000056f),
.Q(sig00000663)
);
FD #(
.INIT ( 1'b0 ))
blk00000279 (
.C(clk),
.D(sig0000056e),
.Q(sig00000662)
);
FD #(
.INIT ( 1'b0 ))
blk0000027a (
.C(clk),
.D(sig0000056d),
.Q(sig00000661)
);
FD #(
.INIT ( 1'b0 ))
blk0000027b (
.C(clk),
.D(sig0000056c),
.Q(sig00000660)
);
FD #(
.INIT ( 1'b0 ))
blk0000027c (
.C(clk),
.D(sig0000056b),
.Q(sig0000065f)
);
FD #(
.INIT ( 1'b0 ))
blk0000027d (
.C(clk),
.D(sig0000056a),
.Q(sig0000065e)
);
FD #(
.INIT ( 1'b0 ))
blk0000027e (
.C(clk),
.D(sig00000569),
.Q(sig0000065d)
);
FD #(
.INIT ( 1'b0 ))
blk0000027f (
.C(clk),
.D(sig00000568),
.Q(sig0000065c)
);
FD #(
.INIT ( 1'b0 ))
blk00000280 (
.C(clk),
.D(sig00000567),
.Q(sig0000065b)
);
FD #(
.INIT ( 1'b0 ))
blk00000281 (
.C(clk),
.D(sig00000566),
.Q(sig0000065a)
);
FD #(
.INIT ( 1'b0 ))
blk00000282 (
.C(clk),
.D(sig00000565),
.Q(sig00000659)
);
FD #(
.INIT ( 1'b0 ))
blk00000283 (
.C(clk),
.D(sig00000564),
.Q(sig00000658)
);
FD #(
.INIT ( 1'b0 ))
blk00000284 (
.C(clk),
.D(sig00000563),
.Q(sig00000657)
);
FD #(
.INIT ( 1'b0 ))
blk00000285 (
.C(clk),
.D(sig00000562),
.Q(sig00000656)
);
FD #(
.INIT ( 1'b0 ))
blk00000286 (
.C(clk),
.D(sig00000561),
.Q(sig00000655)
);
FD #(
.INIT ( 1'b0 ))
blk00000287 (
.C(clk),
.D(sig00000560),
.Q(sig00000654)
);
FD #(
.INIT ( 1'b0 ))
blk00000288 (
.C(clk),
.D(sig0000055f),
.Q(sig00000653)
);
FD #(
.INIT ( 1'b0 ))
blk00000289 (
.C(clk),
.D(sig0000055e),
.Q(sig00000652)
);
FD #(
.INIT ( 1'b0 ))
blk0000028a (
.C(clk),
.D(sig0000055d),
.Q(sig00000651)
);
FD #(
.INIT ( 1'b0 ))
blk0000028b (
.C(clk),
.D(sig0000055c),
.Q(sig00000650)
);
FD #(
.INIT ( 1'b0 ))
blk0000028c (
.C(clk),
.D(sig0000055b),
.Q(sig0000064f)
);
FD #(
.INIT ( 1'b0 ))
blk0000028d (
.C(clk),
.D(sig0000055a),
.Q(sig0000064e)
);
FD #(
.INIT ( 1'b0 ))
blk0000028e (
.C(clk),
.D(sig00000559),
.Q(sig0000064d)
);
FD #(
.INIT ( 1'b0 ))
blk0000028f (
.C(clk),
.D(sig00000558),
.Q(sig0000064c)
);
FD #(
.INIT ( 1'b0 ))
blk00000290 (
.C(clk),
.D(sig00000557),
.Q(sig0000064b)
);
FD #(
.INIT ( 1'b0 ))
blk00000291 (
.C(clk),
.D(sig00000556),
.Q(sig0000064a)
);
FD #(
.INIT ( 1'b0 ))
blk00000292 (
.C(clk),
.D(sig00000555),
.Q(sig00000649)
);
FD #(
.INIT ( 1'b0 ))
blk00000293 (
.C(clk),
.D(sig00000554),
.Q(sig00000648)
);
FD #(
.INIT ( 1'b0 ))
blk00000294 (
.C(clk),
.D(sig00000553),
.Q(sig00000647)
);
FD #(
.INIT ( 1'b0 ))
blk00000295 (
.C(clk),
.D(sig00000552),
.Q(sig00000646)
);
FD #(
.INIT ( 1'b0 ))
blk00000296 (
.C(clk),
.D(sig00000551),
.Q(sig00000645)
);
FD #(
.INIT ( 1'b0 ))
blk00000297 (
.C(clk),
.D(sig00000550),
.Q(sig00000644)
);
FD #(
.INIT ( 1'b0 ))
blk00000298 (
.C(clk),
.D(sig0000054f),
.Q(sig00000643)
);
FD #(
.INIT ( 1'b0 ))
blk00000299 (
.C(clk),
.D(sig0000054e),
.Q(sig00000642)
);
FD #(
.INIT ( 1'b0 ))
blk0000029a (
.C(clk),
.D(sig0000054d),
.Q(sig00000641)
);
FD #(
.INIT ( 1'b0 ))
blk0000029b (
.C(clk),
.D(sig0000054c),
.Q(sig00000640)
);
FD #(
.INIT ( 1'b0 ))
blk0000029c (
.C(clk),
.D(sig0000054b),
.Q(sig0000063f)
);
FD #(
.INIT ( 1'b0 ))
blk0000029d (
.C(clk),
.D(sig0000054a),
.Q(sig0000063e)
);
FD #(
.INIT ( 1'b0 ))
blk0000029e (
.C(clk),
.D(sig00000549),
.Q(sig0000063d)
);
FD #(
.INIT ( 1'b0 ))
blk0000029f (
.C(clk),
.D(sig00000548),
.Q(sig0000063c)
);
FD #(
.INIT ( 1'b0 ))
blk000002a0 (
.C(clk),
.D(sig00000547),
.Q(sig0000063b)
);
FD #(
.INIT ( 1'b0 ))
blk000002a1 (
.C(clk),
.D(sig00000546),
.Q(sig0000063a)
);
FD #(
.INIT ( 1'b0 ))
blk000002a2 (
.C(clk),
.D(sig00000545),
.Q(sig00000639)
);
FD #(
.INIT ( 1'b0 ))
blk000002a3 (
.C(clk),
.D(sig00000579),
.Q(sig0000069f)
);
FD #(
.INIT ( 1'b0 ))
blk000002a4 (
.C(clk),
.D(sig00000578),
.Q(sig0000069e)
);
FD #(
.INIT ( 1'b0 ))
blk000002a5 (
.C(clk),
.D(sig00000577),
.Q(sig0000069d)
);
FD #(
.INIT ( 1'b0 ))
blk000002a6 (
.C(clk),
.D(sig00000576),
.Q(sig0000069c)
);
FD #(
.INIT ( 1'b0 ))
blk000002a7 (
.C(clk),
.D(sig00000575),
.Q(sig0000069b)
);
FD #(
.INIT ( 1'b0 ))
blk000002a8 (
.C(clk),
.D(sig00000574),
.Q(sig0000069a)
);
FD #(
.INIT ( 1'b0 ))
blk000002a9 (
.C(clk),
.D(sig00000573),
.Q(sig00000699)
);
FD #(
.INIT ( 1'b0 ))
blk000002aa (
.C(clk),
.D(sig00000572),
.Q(sig00000698)
);
FD #(
.INIT ( 1'b0 ))
blk000002ab (
.C(clk),
.D(sig0000047d),
.Q(sig00000600)
);
FD #(
.INIT ( 1'b0 ))
blk000002ac (
.C(clk),
.D(sig0000047e),
.Q(sig000005ff)
);
FD #(
.INIT ( 1'b0 ))
blk000002ad (
.C(clk),
.D(sig0000047f),
.Q(sig000005fe)
);
FD #(
.INIT ( 1'b0 ))
blk000002ae (
.C(clk),
.D(sig00000480),
.Q(sig000005fd)
);
FD #(
.INIT ( 1'b0 ))
blk000002af (
.C(clk),
.D(sig00000481),
.Q(sig000005fc)
);
FD #(
.INIT ( 1'b0 ))
blk000002b0 (
.C(clk),
.D(sig00000482),
.Q(sig000005fb)
);
FD #(
.INIT ( 1'b0 ))
blk000002b1 (
.C(clk),
.D(sig00000483),
.Q(sig000005fa)
);
FD #(
.INIT ( 1'b0 ))
blk000002b2 (
.C(clk),
.D(sig00000484),
.Q(sig000005f9)
);
XORCY blk000002b3 (
.CI(sig000006a2),
.LI(sig00000827),
.O(sig000006a0)
);
XORCY blk000002b4 (
.CI(sig000006a4),
.LI(sig00000811),
.O(sig000006a1)
);
MUXCY blk000002b5 (
.CI(sig000006a4),
.DI(sig00000608),
.S(sig00000811),
.O(sig000006a2)
);
XORCY blk000002b6 (
.CI(sig000006a6),
.LI(sig00000812),
.O(sig000006a3)
);
MUXCY blk000002b7 (
.CI(sig000006a6),
.DI(sig00000607),
.S(sig00000812),
.O(sig000006a4)
);
XORCY blk000002b8 (
.CI(sig000006a8),
.LI(sig00000813),
.O(sig000006a5)
);
MUXCY blk000002b9 (
.CI(sig000006a8),
.DI(sig00000606),
.S(sig00000813),
.O(sig000006a6)
);
XORCY blk000002ba (
.CI(sig000006aa),
.LI(sig00000814),
.O(sig000006a7)
);
MUXCY blk000002bb (
.CI(sig000006aa),
.DI(sig00000605),
.S(sig00000814),
.O(sig000006a8)
);
XORCY blk000002bc (
.CI(sig000006ac),
.LI(sig00000815),
.O(sig000006a9)
);
MUXCY blk000002bd (
.CI(sig000006ac),
.DI(sig00000604),
.S(sig00000815),
.O(sig000006aa)
);
XORCY blk000002be (
.CI(sig000006ae),
.LI(sig00000816),
.O(sig000006ab)
);
MUXCY blk000002bf (
.CI(sig000006ae),
.DI(sig00000603),
.S(sig00000816),
.O(sig000006ac)
);
XORCY blk000002c0 (
.CI(sig000006b0),
.LI(sig00000817),
.O(sig000006ad)
);
MUXCY blk000002c1 (
.CI(sig000006b0),
.DI(sig00000602),
.S(sig00000817),
.O(sig000006ae)
);
XORCY blk000002c2 (
.CI(sig00000001),
.LI(sig00000818),
.O(sig000006af)
);
MUXCY blk000002c3 (
.CI(sig00000001),
.DI(sig00000601),
.S(sig00000818),
.O(sig000006b0)
);
XORCY blk000002c4 (
.CI(sig000006b3),
.LI(sig000005dc),
.O(sig000006b1)
);
XORCY blk000002c5 (
.CI(sig000006b5),
.LI(sig000005db),
.O(sig000006b2)
);
MUXCY blk000002c6 (
.CI(sig000006b5),
.DI(sig00000608),
.S(sig000005db),
.O(sig000006b3)
);
XORCY blk000002c7 (
.CI(sig000006b7),
.LI(sig000005da),
.O(sig000006b4)
);
MUXCY blk000002c8 (
.CI(sig000006b7),
.DI(sig00000607),
.S(sig000005da),
.O(sig000006b5)
);
XORCY blk000002c9 (
.CI(sig000006b9),
.LI(sig000005d9),
.O(sig000006b6)
);
MUXCY blk000002ca (
.CI(sig000006b9),
.DI(sig00000606),
.S(sig000005d9),
.O(sig000006b7)
);
XORCY blk000002cb (
.CI(sig000006bb),
.LI(sig000005d8),
.O(sig000006b8)
);
MUXCY blk000002cc (
.CI(sig000006bb),
.DI(sig00000605),
.S(sig000005d8),
.O(sig000006b9)
);
XORCY blk000002cd (
.CI(sig000006bd),
.LI(sig000005d7),
.O(sig000006ba)
);
MUXCY blk000002ce (
.CI(sig000006bd),
.DI(sig00000604),
.S(sig000005d7),
.O(sig000006bb)
);
XORCY blk000002cf (
.CI(sig000006bf),
.LI(sig000005d6),
.O(sig000006bc)
);
MUXCY blk000002d0 (
.CI(sig000006bf),
.DI(sig00000603),
.S(sig000005d6),
.O(sig000006bd)
);
XORCY blk000002d1 (
.CI(sig000006c1),
.LI(sig000005d5),
.O(sig000006be)
);
MUXCY blk000002d2 (
.CI(sig000006c1),
.DI(sig00000602),
.S(sig000005d5),
.O(sig000006bf)
);
XORCY blk000002d3 (
.CI(sig000006c3),
.LI(sig000005d4),
.O(sig000006c0)
);
MUXCY blk000002d4 (
.CI(sig000006c3),
.DI(sig00000601),
.S(sig000005d4),
.O(sig000006c1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d5 (
.C(clk),
.CE(sig00000001),
.D(sig000006b1),
.Q(sig000005f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d6 (
.C(clk),
.CE(sig00000001),
.D(sig000006b2),
.Q(sig000005f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d7 (
.C(clk),
.CE(sig00000001),
.D(sig000006b4),
.Q(sig000005f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d8 (
.C(clk),
.CE(sig00000001),
.D(sig000006b6),
.Q(sig000005f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d9 (
.C(clk),
.CE(sig00000001),
.D(sig000006b8),
.Q(sig000005f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000002da (
.C(clk),
.CE(sig00000001),
.D(sig000006ba),
.Q(sig000005f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000002db (
.C(clk),
.CE(sig00000001),
.D(sig000006bc),
.Q(sig000005f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002dc (
.C(clk),
.CE(sig00000001),
.D(sig000006be),
.Q(sig000005f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000002dd (
.C(clk),
.CE(sig00000001),
.D(sig000006c0),
.Q(sig000005ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000002de (
.C(clk),
.CE(sig00000001),
.D(sig000006a0),
.Q(sig000005ee)
);
FDE #(
.INIT ( 1'b0 ))
blk000002df (
.C(clk),
.CE(sig00000001),
.D(sig000006a1),
.Q(sig000005ed)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e0 (
.C(clk),
.CE(sig00000001),
.D(sig000006a3),
.Q(sig000005ec)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e1 (
.C(clk),
.CE(sig00000001),
.D(sig000006a5),
.Q(sig000005eb)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e2 (
.C(clk),
.CE(sig00000001),
.D(sig000006a7),
.Q(sig000005ea)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e3 (
.C(clk),
.CE(sig00000001),
.D(sig000006a9),
.Q(sig000005e9)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e4 (
.C(clk),
.CE(sig00000001),
.D(sig000006ab),
.Q(sig000005e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e5 (
.C(clk),
.CE(sig00000001),
.D(sig000006ad),
.Q(sig000005e7)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e6 (
.C(clk),
.CE(sig00000001),
.D(sig000006af),
.Q(sig000005e6)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e7 (
.C(clk),
.CE(sig00000001),
.D(sig000005e5),
.Q(sig000001c2)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e8 (
.C(clk),
.CE(sig00000001),
.D(sig000005e4),
.Q(sig000001c1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e9 (
.C(clk),
.CE(sig00000001),
.D(sig000005e3),
.Q(sig000001c0)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ea (
.C(clk),
.CE(sig00000001),
.D(sig000005e2),
.Q(sig000001bf)
);
FDE #(
.INIT ( 1'b0 ))
blk000002eb (
.C(clk),
.CE(sig00000001),
.D(sig000005e1),
.Q(sig000001be)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ec (
.C(clk),
.CE(sig00000001),
.D(sig000005e0),
.Q(sig000001bd)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ed (
.C(clk),
.CE(sig00000001),
.D(sig000005df),
.Q(sig000001bc)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ee (
.C(clk),
.CE(sig00000001),
.D(sig000005de),
.Q(sig000001bb)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ef (
.C(clk),
.CE(sig00000001),
.D(sig000005dd),
.Q(sig000001ba)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f0 (
.C(clk),
.CE(sig00000001),
.D(sig00000695),
.Q(sig000001b9)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f1 (
.C(clk),
.CE(sig00000001),
.D(sig00000694),
.Q(sig000001b8)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f2 (
.C(clk),
.CE(sig00000001),
.D(sig00000693),
.Q(sig000001b7)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f3 (
.C(clk),
.CE(sig00000001),
.D(sig00000692),
.Q(sig000001b6)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f4 (
.C(clk),
.CE(sig00000001),
.D(sig00000691),
.Q(sig000001b5)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f5 (
.C(clk),
.CE(sig00000001),
.D(sig00000690),
.Q(sig000001b4)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f6 (
.C(clk),
.CE(sig00000001),
.D(sig0000068f),
.Q(sig000001b3)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f7 (
.C(clk),
.CE(sig00000001),
.D(sig0000068e),
.Q(sig000001b2)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f8 (
.C(clk),
.CE(sig00000001),
.D(sig0000068d),
.Q(sig000001b1)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f9 (
.C(clk),
.CE(sig00000001),
.D(sig0000068c),
.Q(sig000001b0)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fa (
.C(clk),
.CE(sig00000001),
.D(sig0000068b),
.Q(sig000001af)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fb (
.C(clk),
.CE(sig00000001),
.D(sig0000068a),
.Q(sig000001ae)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fc (
.C(clk),
.CE(sig00000001),
.D(sig00000689),
.Q(sig000001ad)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fd (
.C(clk),
.CE(sig00000001),
.D(sig00000688),
.Q(sig000001ac)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fe (
.C(clk),
.CE(sig00000001),
.D(sig00000687),
.Q(sig000001ab)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ff (
.C(clk),
.CE(sig00000001),
.D(sig00000686),
.Q(sig000001aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000300 (
.C(clk),
.CE(sig00000001),
.D(sig00000685),
.Q(sig000001a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000301 (
.C(clk),
.CE(sig00000001),
.D(sig00000684),
.Q(sig000001a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000302 (
.C(clk),
.CE(sig00000001),
.D(sig00000683),
.Q(sig000001a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000303 (
.C(clk),
.CE(sig00000001),
.D(sig00000682),
.Q(sig000001a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000304 (
.C(clk),
.CE(sig00000001),
.D(sig00000681),
.Q(sig000001a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000305 (
.C(clk),
.CE(sig00000001),
.D(sig00000680),
.Q(sig000001a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000306 (
.C(clk),
.CE(sig00000001),
.D(sig0000067f),
.Q(sig000001a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000307 (
.C(clk),
.CE(sig00000001),
.D(sig0000067e),
.Q(sig000001a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000308 (
.C(clk),
.CE(sig00000001),
.D(sig0000067d),
.Q(sig000001a1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000309 (
.C(clk),
.CE(sig00000001),
.D(sig0000067c),
.Q(sig000001a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030a (
.C(clk),
.CE(sig00000001),
.D(sig0000067b),
.Q(sig0000019f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030b (
.C(clk),
.CE(sig00000001),
.D(sig0000067a),
.Q(sig0000019e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030c (
.C(clk),
.CE(sig00000001),
.D(sig00000679),
.Q(sig0000019d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030d (
.C(clk),
.CE(sig00000001),
.D(sig00000678),
.Q(sig0000019c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030e (
.C(clk),
.CE(sig00000001),
.D(sig00000677),
.Q(sig0000019b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030f (
.C(clk),
.CE(sig00000001),
.D(sig00000676),
.Q(sig0000019a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000310 (
.C(clk),
.CE(sig00000001),
.D(sig00000675),
.Q(sig00000199)
);
FDE #(
.INIT ( 1'b0 ))
blk00000311 (
.C(clk),
.CE(sig00000001),
.D(sig00000674),
.Q(sig00000198)
);
FDE #(
.INIT ( 1'b0 ))
blk00000312 (
.C(clk),
.CE(sig00000001),
.D(sig00000673),
.Q(sig00000197)
);
FDE #(
.INIT ( 1'b0 ))
blk00000313 (
.C(clk),
.CE(sig00000001),
.D(sig00000672),
.Q(sig00000196)
);
FDE #(
.INIT ( 1'b0 ))
blk00000314 (
.C(clk),
.CE(sig00000001),
.D(sig00000671),
.Q(sig00000195)
);
FDE #(
.INIT ( 1'b0 ))
blk00000315 (
.C(clk),
.CE(sig00000001),
.D(sig00000670),
.Q(sig00000194)
);
FDE #(
.INIT ( 1'b0 ))
blk00000316 (
.C(clk),
.CE(sig00000001),
.D(sig0000066f),
.Q(sig00000193)
);
FDE #(
.INIT ( 1'b0 ))
blk00000317 (
.C(clk),
.CE(sig00000001),
.D(sig0000066e),
.Q(sig00000192)
);
FDE #(
.INIT ( 1'b0 ))
blk00000318 (
.C(clk),
.CE(sig00000001),
.D(sig0000066d),
.Q(sig00000191)
);
FDE #(
.INIT ( 1'b0 ))
blk00000319 (
.C(clk),
.CE(sig00000001),
.D(sig0000066c),
.Q(sig00000190)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031a (
.C(clk),
.CE(sig00000001),
.D(sig0000066b),
.Q(sig0000018f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031b (
.C(clk),
.CE(sig00000001),
.D(sig0000066a),
.Q(sig0000018e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031c (
.C(clk),
.CE(sig00000001),
.D(sig00000669),
.Q(sig0000018d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031d (
.C(clk),
.CE(sig00000001),
.D(sig00000668),
.Q(sig0000018c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031e (
.C(clk),
.CE(sig00000001),
.D(sig00000667),
.Q(sig0000018b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031f (
.C(clk),
.CE(sig00000001),
.D(sig00000072),
.Q(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000320 (
.C(clk),
.CE(sig00000001),
.D(sig00000073),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000321 (
.C(clk),
.CE(sig00000001),
.D(sig00000074),
.Q(sig00000004)
);
FDE #(
.INIT ( 1'b0 ))
blk00000322 (
.C(clk),
.CE(sig00000001),
.D(sig00000075),
.Q(sig00000005)
);
FDE #(
.INIT ( 1'b0 ))
blk00000323 (
.C(clk),
.CE(sig00000001),
.D(sig00000076),
.Q(sig00000006)
);
FDE #(
.INIT ( 1'b0 ))
blk00000324 (
.C(clk),
.CE(sig00000001),
.D(sig00000077),
.Q(sig00000007)
);
FDE #(
.INIT ( 1'b0 ))
blk00000325 (
.C(clk),
.CE(sig00000001),
.D(sig00000078),
.Q(sig00000008)
);
FDE #(
.INIT ( 1'b0 ))
blk00000326 (
.C(clk),
.CE(sig00000001),
.D(sig00000079),
.Q(sig00000009)
);
FDE #(
.INIT ( 1'b0 ))
blk00000327 (
.C(clk),
.CE(sig00000001),
.D(sig0000007a),
.Q(sig0000000a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000328 (
.C(clk),
.CE(sig00000001),
.D(sig0000007b),
.Q(sig0000000b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000329 (
.C(clk),
.CE(sig00000001),
.D(sig0000007c),
.Q(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032a (
.C(clk),
.CE(sig00000001),
.D(sig0000007d),
.Q(sig0000000d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032b (
.C(clk),
.CE(sig00000001),
.D(sig0000007e),
.Q(sig0000000e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032c (
.C(clk),
.CE(sig00000001),
.D(sig0000007f),
.Q(sig0000000f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032d (
.C(clk),
.CE(sig00000001),
.D(sig00000080),
.Q(sig00000010)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032e (
.C(clk),
.CE(sig00000001),
.D(sig00000081),
.Q(sig00000011)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032f (
.C(clk),
.CE(sig00000001),
.D(sig00000082),
.Q(sig00000012)
);
FDE #(
.INIT ( 1'b0 ))
blk00000330 (
.C(clk),
.CE(sig00000001),
.D(sig00000083),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk00000331 (
.C(clk),
.CE(sig00000001),
.D(sig00000084),
.Q(sig00000014)
);
FDE #(
.INIT ( 1'b0 ))
blk00000332 (
.C(clk),
.CE(sig00000001),
.D(sig00000085),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk00000333 (
.C(clk),
.CE(sig00000001),
.D(sig00000086),
.Q(sig00000016)
);
FDE #(
.INIT ( 1'b0 ))
blk00000334 (
.C(clk),
.CE(sig00000001),
.D(sig00000087),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk00000335 (
.C(clk),
.CE(sig00000001),
.D(sig00000088),
.Q(sig00000018)
);
FDE #(
.INIT ( 1'b0 ))
blk00000336 (
.C(clk),
.CE(sig00000001),
.D(sig00000089),
.Q(sig00000019)
);
FDE #(
.INIT ( 1'b0 ))
blk00000337 (
.C(clk),
.CE(sig00000001),
.D(sig0000008a),
.Q(sig0000001a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000338 (
.C(clk),
.CE(sig00000001),
.D(sig0000008b),
.Q(sig0000001b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000339 (
.C(clk),
.CE(sig00000001),
.D(sig0000008c),
.Q(sig0000001c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033a (
.C(clk),
.CE(sig00000001),
.D(sig0000008d),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033b (
.C(clk),
.CE(sig00000001),
.D(sig0000008e),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033c (
.C(clk),
.CE(sig00000001),
.D(sig0000008f),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033d (
.C(clk),
.CE(sig00000001),
.D(sig00000090),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033e (
.C(clk),
.CE(sig00000001),
.D(sig00000091),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033f (
.C(clk),
.CE(sig00000001),
.D(sig00000092),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk00000340 (
.C(clk),
.CE(sig00000001),
.D(sig00000093),
.Q(sig00000023)
);
FDE #(
.INIT ( 1'b0 ))
blk00000341 (
.C(clk),
.CE(sig00000001),
.D(sig00000094),
.Q(sig00000024)
);
FDE #(
.INIT ( 1'b0 ))
blk00000342 (
.C(clk),
.CE(sig00000001),
.D(sig00000095),
.Q(sig00000025)
);
FDE #(
.INIT ( 1'b0 ))
blk00000343 (
.C(clk),
.CE(sig00000001),
.D(sig00000096),
.Q(sig00000026)
);
FDE #(
.INIT ( 1'b0 ))
blk00000344 (
.C(clk),
.CE(sig00000001),
.D(sig00000097),
.Q(sig00000027)
);
FDE #(
.INIT ( 1'b0 ))
blk00000345 (
.C(clk),
.CE(sig00000001),
.D(sig00000098),
.Q(sig00000028)
);
FDE #(
.INIT ( 1'b0 ))
blk00000346 (
.C(clk),
.CE(sig00000001),
.D(sig00000099),
.Q(sig00000029)
);
FDE #(
.INIT ( 1'b0 ))
blk00000347 (
.C(clk),
.CE(sig00000001),
.D(sig0000009a),
.Q(sig0000002a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000348 (
.C(clk),
.CE(sig00000001),
.D(sig0000009b),
.Q(sig0000002b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000349 (
.C(clk),
.CE(sig00000001),
.D(sig0000009c),
.Q(sig0000002c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034a (
.C(clk),
.CE(sig00000001),
.D(sig0000009d),
.Q(sig0000002d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034b (
.C(clk),
.CE(sig00000001),
.D(sig0000009e),
.Q(sig0000002e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034c (
.C(clk),
.CE(sig00000001),
.D(sig0000009f),
.Q(sig0000002f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034d (
.C(clk),
.CE(sig00000001),
.D(sig000000a0),
.Q(sig00000030)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034e (
.C(clk),
.CE(sig00000001),
.D(sig000000a1),
.Q(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034f (
.C(clk),
.CE(sig00000001),
.D(sig000000a2),
.Q(sig00000032)
);
FDE #(
.INIT ( 1'b0 ))
blk00000350 (
.C(clk),
.CE(sig00000001),
.D(sig000000a3),
.Q(sig00000033)
);
FDE #(
.INIT ( 1'b0 ))
blk00000351 (
.C(clk),
.CE(sig00000001),
.D(sig000000a4),
.Q(sig00000034)
);
FDE #(
.INIT ( 1'b0 ))
blk00000352 (
.C(clk),
.CE(sig00000001),
.D(sig000000a5),
.Q(sig00000035)
);
FDE #(
.INIT ( 1'b0 ))
blk00000353 (
.C(clk),
.CE(sig00000001),
.D(sig000000a6),
.Q(sig00000036)
);
FDE #(
.INIT ( 1'b0 ))
blk00000354 (
.C(clk),
.CE(sig00000001),
.D(sig000000a7),
.Q(sig00000037)
);
FDE #(
.INIT ( 1'b0 ))
blk00000355 (
.C(clk),
.CE(sig00000001),
.D(sig000000a8),
.Q(sig00000038)
);
FDE #(
.INIT ( 1'b0 ))
blk00000356 (
.C(clk),
.CE(sig00000001),
.D(sig000000a9),
.Q(sig00000039)
);
FDE #(
.INIT ( 1'b0 ))
blk00000357 (
.C(clk),
.CE(sig00000001),
.D(sig000000aa),
.Q(sig0000003a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000358 (
.C(clk),
.CE(sig00000001),
.D(sig000000ab),
.Q(sig0000003b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000359 (
.C(clk),
.CE(sig00000001),
.D(sig000000ac),
.Q(sig0000003c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035a (
.C(clk),
.CE(sig00000001),
.D(sig000000ad),
.Q(sig0000003d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035b (
.C(clk),
.CE(sig00000001),
.D(sig000000ae),
.Q(sig0000003e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035c (
.C(clk),
.CE(sig00000001),
.D(sig000000af),
.Q(sig0000003f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035d (
.C(clk),
.CE(sig00000001),
.D(sig000000b0),
.Q(sig00000040)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035e (
.C(clk),
.CE(sig00000001),
.D(sig000000b1),
.Q(sig00000041)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035f (
.C(clk),
.CE(sig00000001),
.D(sig000000b2),
.Q(sig00000042)
);
FDE #(
.INIT ( 1'b0 ))
blk00000360 (
.C(clk),
.CE(sig00000001),
.D(sig000000b3),
.Q(sig00000043)
);
FDE #(
.INIT ( 1'b0 ))
blk00000361 (
.C(clk),
.CE(sig00000001),
.D(sig000000b4),
.Q(sig00000044)
);
FDE #(
.INIT ( 1'b0 ))
blk00000362 (
.C(clk),
.CE(sig00000001),
.D(sig000000b5),
.Q(sig00000045)
);
FDE #(
.INIT ( 1'b0 ))
blk00000363 (
.C(clk),
.CE(sig00000001),
.D(sig000000b6),
.Q(sig00000046)
);
FDE #(
.INIT ( 1'b0 ))
blk00000364 (
.C(clk),
.CE(sig00000001),
.D(sig000000b7),
.Q(sig00000047)
);
FDE #(
.INIT ( 1'b0 ))
blk00000365 (
.C(clk),
.CE(sig00000001),
.D(sig000000b8),
.Q(sig00000048)
);
FDE #(
.INIT ( 1'b0 ))
blk00000366 (
.C(clk),
.CE(sig00000001),
.D(sig000000b9),
.Q(sig00000049)
);
FDE #(
.INIT ( 1'b0 ))
blk00000367 (
.C(clk),
.CE(sig00000001),
.D(sig000000ba),
.Q(sig0000004a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000368 (
.C(clk),
.CE(sig00000001),
.D(sig000000bb),
.Q(sig0000004b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000369 (
.C(clk),
.CE(sig00000001),
.D(sig000000bc),
.Q(sig0000004c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036a (
.C(clk),
.CE(sig00000001),
.D(sig000000bd),
.Q(sig0000004d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036b (
.C(clk),
.CE(sig00000001),
.D(sig000000be),
.Q(sig0000004e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036c (
.C(clk),
.CE(sig00000001),
.D(sig000000bf),
.Q(sig0000004f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036d (
.C(clk),
.CE(sig00000001),
.D(sig000000c0),
.Q(sig00000050)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036e (
.C(clk),
.CE(sig00000001),
.D(sig000000c1),
.Q(sig00000051)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036f (
.C(clk),
.CE(sig00000001),
.D(sig000000c2),
.Q(sig00000052)
);
FDE #(
.INIT ( 1'b0 ))
blk00000370 (
.C(clk),
.CE(sig00000001),
.D(sig000000c3),
.Q(sig00000053)
);
FDE #(
.INIT ( 1'b0 ))
blk00000371 (
.C(clk),
.CE(sig00000001),
.D(sig000000c4),
.Q(sig00000054)
);
FDE #(
.INIT ( 1'b0 ))
blk00000372 (
.C(clk),
.CE(sig00000001),
.D(sig000000c5),
.Q(sig00000055)
);
FDE #(
.INIT ( 1'b0 ))
blk00000373 (
.C(clk),
.CE(sig00000001),
.D(sig000000c6),
.Q(sig00000056)
);
FDE #(
.INIT ( 1'b0 ))
blk00000374 (
.C(clk),
.CE(sig00000001),
.D(sig000000c7),
.Q(sig00000057)
);
FDE #(
.INIT ( 1'b0 ))
blk00000375 (
.C(clk),
.CE(sig00000001),
.D(sig000000c8),
.Q(sig00000058)
);
FDE #(
.INIT ( 1'b0 ))
blk00000376 (
.C(clk),
.CE(sig00000001),
.D(sig000000c9),
.Q(sig00000059)
);
FDE #(
.INIT ( 1'b0 ))
blk00000377 (
.C(clk),
.CE(sig00000001),
.D(sig000000ca),
.Q(sig0000005a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000378 (
.C(clk),
.CE(sig00000001),
.D(sig000000cb),
.Q(sig0000005b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000379 (
.C(clk),
.CE(sig00000001),
.D(sig000000cc),
.Q(sig0000005c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037a (
.C(clk),
.CE(sig00000001),
.D(sig000000cd),
.Q(sig0000005d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037b (
.C(clk),
.CE(sig00000001),
.D(sig000000ce),
.Q(sig0000005e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037c (
.C(clk),
.CE(sig00000001),
.D(sig000000cf),
.Q(sig0000005f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037d (
.C(clk),
.CE(sig00000001),
.D(sig000000d0),
.Q(sig00000060)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037e (
.C(clk),
.CE(sig00000001),
.D(sig000000d1),
.Q(sig00000061)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037f (
.C(clk),
.CE(sig00000001),
.D(sig000000d2),
.Q(sig00000062)
);
FDE #(
.INIT ( 1'b0 ))
blk00000380 (
.C(clk),
.CE(sig00000001),
.D(sig000000d3),
.Q(sig00000063)
);
FDE #(
.INIT ( 1'b0 ))
blk00000381 (
.C(clk),
.CE(sig00000001),
.D(sig000000d4),
.Q(sig00000064)
);
FDE #(
.INIT ( 1'b0 ))
blk00000382 (
.C(clk),
.CE(sig00000001),
.D(sig000000d5),
.Q(sig00000065)
);
FDE #(
.INIT ( 1'b0 ))
blk00000383 (
.C(clk),
.CE(sig00000001),
.D(sig000000d6),
.Q(sig00000066)
);
FDE #(
.INIT ( 1'b0 ))
blk00000384 (
.C(clk),
.CE(sig00000001),
.D(sig000000d7),
.Q(sig00000067)
);
FDE #(
.INIT ( 1'b0 ))
blk00000385 (
.C(clk),
.CE(sig00000001),
.D(sig000000d8),
.Q(sig00000068)
);
FDE #(
.INIT ( 1'b0 ))
blk00000386 (
.C(clk),
.CE(sig00000001),
.D(sig000000d9),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk00000387 (
.C(clk),
.CE(sig00000001),
.D(sig000000da),
.Q(sig0000006a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000388 (
.C(clk),
.CE(sig00000001),
.D(sig000000db),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000389 (
.C(clk),
.CE(sig00000001),
.D(sig000000dc),
.Q(sig0000006c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038a (
.C(clk),
.CE(sig00000001),
.D(sig000000dd),
.Q(sig0000006d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038b (
.C(clk),
.CE(sig00000001),
.D(sig000000de),
.Q(sig0000006e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038c (
.C(clk),
.CE(sig00000001),
.D(sig000000df),
.Q(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038d (
.C(clk),
.CE(sig00000001),
.D(sig000000e0),
.Q(sig00000070)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038e (
.C(clk),
.CE(sig00000001),
.D(sig000000e1),
.Q(sig00000071)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038f (
.C(clk),
.CE(sig00000001),
.D(sig000001c1),
.Q(sig0000011e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000390 (
.C(clk),
.CE(sig00000001),
.D(sig000001c0),
.Q(sig0000011f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000391 (
.C(clk),
.CE(sig00000001),
.D(sig000001bf),
.Q(sig00000120)
);
FDE #(
.INIT ( 1'b0 ))
blk00000392 (
.C(clk),
.CE(sig00000001),
.D(sig000001be),
.Q(sig00000121)
);
FDE #(
.INIT ( 1'b0 ))
blk00000393 (
.C(clk),
.CE(sig00000001),
.D(sig000001bd),
.Q(sig00000122)
);
FDE #(
.INIT ( 1'b0 ))
blk00000394 (
.C(clk),
.CE(sig00000001),
.D(sig000001bc),
.Q(sig00000123)
);
FDE #(
.INIT ( 1'b0 ))
blk00000395 (
.C(clk),
.CE(sig00000001),
.D(sig000001bb),
.Q(sig00000124)
);
FDE #(
.INIT ( 1'b0 ))
blk00000396 (
.C(clk),
.CE(sig00000001),
.D(sig000001ba),
.Q(sig00000125)
);
FDE #(
.INIT ( 1'b0 ))
blk00000397 (
.C(clk),
.CE(sig00000001),
.D(sig000001b9),
.Q(sig00000126)
);
FDE #(
.INIT ( 1'b0 ))
blk00000398 (
.C(clk),
.CE(sig00000001),
.D(sig000001b8),
.Q(sig00000127)
);
FDE #(
.INIT ( 1'b0 ))
blk00000399 (
.C(clk),
.CE(sig00000001),
.D(sig000001b7),
.Q(sig00000128)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039a (
.C(clk),
.CE(sig00000001),
.D(sig000001b6),
.Q(sig00000129)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039b (
.C(clk),
.CE(sig00000001),
.D(sig000001b5),
.Q(sig0000012a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039c (
.C(clk),
.CE(sig00000001),
.D(sig000001b4),
.Q(sig0000012b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039d (
.C(clk),
.CE(sig00000001),
.D(sig000001b3),
.Q(sig0000012c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039e (
.C(clk),
.CE(sig00000001),
.D(sig000001b2),
.Q(sig0000012d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039f (
.C(clk),
.CE(sig00000001),
.D(sig000001b1),
.Q(sig0000012e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a0 (
.C(clk),
.CE(sig00000001),
.D(sig000001b0),
.Q(sig0000012f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a1 (
.C(clk),
.CE(sig00000001),
.D(sig000001af),
.Q(sig00000130)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a2 (
.C(clk),
.CE(sig00000001),
.D(sig000001ae),
.Q(sig00000131)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a3 (
.C(clk),
.CE(sig00000001),
.D(sig000001ad),
.Q(sig00000132)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a4 (
.C(clk),
.CE(sig00000001),
.D(sig000001ac),
.Q(sig00000133)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a5 (
.C(clk),
.CE(sig00000001),
.D(sig000001ab),
.Q(sig00000134)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a6 (
.C(clk),
.CE(sig00000001),
.D(sig000001aa),
.Q(sig00000135)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a7 (
.C(clk),
.CE(sig00000001),
.D(sig000001a9),
.Q(sig00000136)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a8 (
.C(clk),
.CE(sig00000001),
.D(sig000001a8),
.Q(sig00000137)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a9 (
.C(clk),
.CE(sig00000001),
.D(sig000001a7),
.Q(sig00000138)
);
FDE #(
.INIT ( 1'b0 ))
blk000003aa (
.C(clk),
.CE(sig00000001),
.D(sig000001a6),
.Q(sig00000139)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ab (
.C(clk),
.CE(sig00000001),
.D(sig000001a5),
.Q(sig0000013a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ac (
.C(clk),
.CE(sig00000001),
.D(sig000001a4),
.Q(sig0000013b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ad (
.C(clk),
.CE(sig00000001),
.D(sig000001a3),
.Q(sig0000013c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ae (
.C(clk),
.CE(sig00000001),
.D(sig000001a2),
.Q(sig0000013d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003af (
.C(clk),
.CE(sig00000001),
.D(sig000001a1),
.Q(sig0000013e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b0 (
.C(clk),
.CE(sig00000001),
.D(sig000001a0),
.Q(sig0000013f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b1 (
.C(clk),
.CE(sig00000001),
.D(sig0000019f),
.Q(sig00000140)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b2 (
.C(clk),
.CE(sig00000001),
.D(sig0000019e),
.Q(sig00000141)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b3 (
.C(clk),
.CE(sig00000001),
.D(sig0000019d),
.Q(sig00000142)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b4 (
.C(clk),
.CE(sig00000001),
.D(sig0000019c),
.Q(sig00000143)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b5 (
.C(clk),
.CE(sig00000001),
.D(sig0000019b),
.Q(sig00000144)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b6 (
.C(clk),
.CE(sig00000001),
.D(sig0000019a),
.Q(sig00000145)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b7 (
.C(clk),
.CE(sig00000001),
.D(sig00000199),
.Q(sig00000146)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b8 (
.C(clk),
.CE(sig00000001),
.D(sig00000198),
.Q(sig00000147)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b9 (
.C(clk),
.CE(sig00000001),
.D(sig00000197),
.Q(sig00000148)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ba (
.C(clk),
.CE(sig00000001),
.D(sig00000196),
.Q(sig00000149)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bb (
.C(clk),
.CE(sig00000001),
.D(sig00000195),
.Q(sig0000014a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bc (
.C(clk),
.CE(sig00000001),
.D(sig00000194),
.Q(sig0000014b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bd (
.C(clk),
.CE(sig00000001),
.D(sig00000193),
.Q(sig0000014c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003be (
.C(clk),
.CE(sig00000001),
.D(sig00000192),
.Q(sig0000014d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bf (
.C(clk),
.CE(sig00000001),
.D(sig00000191),
.Q(sig0000014e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c0 (
.C(clk),
.CE(sig00000001),
.D(sig00000190),
.Q(sig0000014f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c1 (
.C(clk),
.CE(sig00000001),
.D(sig0000018f),
.Q(sig00000150)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c2 (
.C(clk),
.CE(sig00000001),
.D(sig0000018e),
.Q(sig00000151)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c3 (
.C(clk),
.CE(sig00000001),
.D(sig0000018d),
.Q(sig00000152)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c4 (
.C(clk),
.CE(sig00000001),
.D(sig0000018c),
.Q(sig00000153)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c5 (
.C(clk),
.CE(sig00000001),
.D(sig0000018b),
.Q(sig00000154)
);
MUXF7 blk000003c6 (
.I0(sig000006c2),
.I1(sig000006c3),
.S(sig0000011a),
.O(NLW_blk000003c6_O_UNCONNECTED)
);
MUXF7 blk000003c7 (
.I0(sig000006c4),
.I1(sig000006c6),
.S(sig0000011a),
.O(sig000006c8)
);
MUXF7 blk000003c8 (
.I0(sig000006c5),
.I1(sig000006c7),
.S(sig0000011a),
.O(sig000006c9)
);
MUXF7 blk000003c9 (
.I0(sig000006ca),
.I1(sig000006ce),
.S(sig00000118),
.O(sig000006d1)
);
MUXF7 blk000003ca (
.I0(sig000006cb),
.I1(sig000006cf),
.S(sig00000118),
.O(sig000006d2)
);
MUXF7 blk000003cb (
.I0(sig000006cc),
.I1(sig000006d0),
.S(sig00000118),
.O(sig000006d3)
);
MUXF7 blk000003cc (
.I0(sig000006cd),
.I1(sig000006c3),
.S(sig00000118),
.O(NLW_blk000003cc_O_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cd (
.C(clk),
.CE(sig00000001),
.D(sig000006c9),
.Q(sig0000011c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ce (
.C(clk),
.CE(sig00000001),
.D(sig000006c8),
.Q(sig0000011d)
);
FD #(
.INIT ( 1'b0 ))
blk000003cf (
.C(clk),
.D(sig000006d1),
.Q(sig000006e4)
);
FD #(
.INIT ( 1'b0 ))
blk000003d0 (
.C(clk),
.D(sig000006d2),
.Q(sig0000011a)
);
FD #(
.INIT ( 1'b0 ))
blk000003d1 (
.C(clk),
.D(sig000006d3),
.Q(sig000006e3)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d2 (
.C(clk),
.CE(sig00000001),
.D(sig0000011a),
.Q(sig00000187)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d3 (
.C(clk),
.CE(sig00000001),
.D(sig0000011b),
.Q(sig00000186)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d4 (
.C(clk),
.CE(sig00000001),
.D(sig000006d4),
.Q(sig00000157)
);
MUXCY blk000003d5 (
.CI(sig000006fb),
.DI(sig000006c3),
.S(sig000006dc),
.O(sig000006fa)
);
MUXCY blk000003d6 (
.CI(sig000006fc),
.DI(sig000006c3),
.S(sig000006db),
.O(sig000006fb)
);
MUXCY blk000003d7 (
.CI(sig000006fd),
.DI(sig000006c3),
.S(sig000006da),
.O(sig000006fc)
);
MUXCY blk000003d8 (
.CI(sig000006fe),
.DI(sig000006c3),
.S(sig000006d9),
.O(sig000006fd)
);
MUXCY blk000003d9 (
.CI(sig000006ff),
.DI(sig000006c3),
.S(sig000006d8),
.O(sig000006fe)
);
MUXCY blk000003da (
.CI(sig00000700),
.DI(sig000006c3),
.S(sig000006d7),
.O(sig000006ff)
);
MUXCY blk000003db (
.CI(sig00000701),
.DI(sig000006c3),
.S(sig000006d6),
.O(sig00000700)
);
MUXCY blk000003dc (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000006d5),
.O(sig00000701)
);
FDE #(
.INIT ( 1'b0 ))
blk000003dd (
.C(clk),
.CE(sig00000001),
.D(sig000006fa),
.Q(sig00000118)
);
FDE #(
.INIT ( 1'b0 ))
blk000003de (
.C(clk),
.CE(sig00000001),
.D(sig000006fb),
.Q(sig000006f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000003df (
.C(clk),
.CE(sig00000001),
.D(sig000006fc),
.Q(sig000006f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e0 (
.C(clk),
.CE(sig00000001),
.D(sig000006fd),
.Q(sig000006f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e1 (
.C(clk),
.CE(sig00000001),
.D(sig000006fe),
.Q(sig000006f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e2 (
.C(clk),
.CE(sig00000001),
.D(sig000006ff),
.Q(sig000006f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e3 (
.C(clk),
.CE(sig00000001),
.D(sig00000700),
.Q(sig000006f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e4 (
.C(clk),
.CE(sig00000001),
.D(sig00000701),
.Q(sig000006f6)
);
MUXCY blk000003e5 (
.CI(sig00000703),
.DI(sig000006c3),
.S(sig000006e2),
.O(sig00000702)
);
MUXCY blk000003e6 (
.CI(sig00000704),
.DI(sig000006c3),
.S(sig000006e1),
.O(sig00000703)
);
MUXCY blk000003e7 (
.CI(sig00000705),
.DI(sig000006c3),
.S(sig000006e0),
.O(sig00000704)
);
MUXCY blk000003e8 (
.CI(sig00000706),
.DI(sig000006c3),
.S(sig000006df),
.O(sig00000705)
);
MUXCY blk000003e9 (
.CI(sig00000707),
.DI(sig000006c3),
.S(sig000006de),
.O(sig00000706)
);
MUXCY blk000003ea (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig000006dd),
.O(sig00000707)
);
FDE #(
.INIT ( 1'b0 ))
blk000003eb (
.C(clk),
.CE(sig00000001),
.D(sig00000702),
.Q(sig000006f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ec (
.C(clk),
.CE(sig00000001),
.D(sig00000703),
.Q(sig000006ed)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ed (
.C(clk),
.CE(sig00000001),
.D(sig00000704),
.Q(sig000006f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ee (
.C(clk),
.CE(sig00000001),
.D(sig00000705),
.Q(sig000006f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ef (
.C(clk),
.CE(sig00000001),
.D(sig00000706),
.Q(sig000006ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f0 (
.C(clk),
.CE(sig00000001),
.D(sig00000707),
.Q(sig000006ee)
);
MUXF7 blk000003f1 (
.I0(sig00000718),
.I1(sig00000710),
.S(sig00000118),
.O(sig00000708)
);
MUXF7 blk000003f2 (
.I0(sig00000719),
.I1(sig00000711),
.S(sig00000118),
.O(sig00000709)
);
MUXF7 blk000003f3 (
.I0(sig0000071a),
.I1(sig00000712),
.S(sig00000118),
.O(sig0000070a)
);
MUXF7 blk000003f4 (
.I0(sig0000071b),
.I1(sig00000713),
.S(sig00000118),
.O(sig0000070b)
);
MUXF7 blk000003f5 (
.I0(sig0000071c),
.I1(sig00000714),
.S(sig00000118),
.O(sig0000070c)
);
MUXF7 blk000003f6 (
.I0(sig0000071d),
.I1(sig00000715),
.S(sig00000118),
.O(sig0000070d)
);
MUXF7 blk000003f7 (
.I0(sig0000071e),
.I1(sig00000716),
.S(sig00000118),
.O(sig0000070e)
);
MUXF7 blk000003f8 (
.I0(sig0000071f),
.I1(sig00000717),
.S(sig00000118),
.O(sig0000070f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f9 (
.C(clk),
.CE(sig00000001),
.D(sig00000708),
.Q(sig000006e6)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fa (
.C(clk),
.CE(sig00000001),
.D(sig00000709),
.Q(sig000006e5)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fb (
.C(clk),
.CE(sig00000001),
.D(sig0000070a),
.Q(sig000006e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fc (
.C(clk),
.CE(sig00000001),
.D(sig0000070b),
.Q(sig000006e7)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fd (
.C(clk),
.CE(sig00000001),
.D(sig0000070c),
.Q(sig000006ea)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fe (
.C(clk),
.CE(sig00000001),
.D(sig0000070d),
.Q(sig000006e9)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ff (
.C(clk),
.CE(sig00000001),
.D(sig0000070e),
.Q(sig000006ec)
);
FDE #(
.INIT ( 1'b0 ))
blk00000400 (
.C(clk),
.CE(sig00000001),
.D(sig0000070f),
.Q(sig000006eb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000401 (
.C(clk),
.CE(sig00000001),
.D(sig00000769),
.Q(sig00000761)
);
FDE #(
.INIT ( 1'b0 ))
blk00000402 (
.C(clk),
.CE(sig00000001),
.D(sig0000076a),
.Q(sig00000762)
);
FDE #(
.INIT ( 1'b0 ))
blk00000403 (
.C(clk),
.CE(sig00000001),
.D(sig0000076b),
.Q(sig00000763)
);
FDE #(
.INIT ( 1'b0 ))
blk00000404 (
.C(clk),
.CE(sig00000001),
.D(sig0000076c),
.Q(sig00000764)
);
FDE #(
.INIT ( 1'b0 ))
blk00000405 (
.C(clk),
.CE(sig00000001),
.D(sig0000076d),
.Q(sig00000765)
);
FDE #(
.INIT ( 1'b0 ))
blk00000406 (
.C(clk),
.CE(sig00000001),
.D(sig0000076e),
.Q(sig00000766)
);
FDE #(
.INIT ( 1'b0 ))
blk00000407 (
.C(clk),
.CE(sig00000001),
.D(sig0000076f),
.Q(sig00000760)
);
FDE #(
.INIT ( 1'b0 ))
blk00000408 (
.C(clk),
.CE(sig00000001),
.D(sig00000720),
.Q(sig00000768)
);
MUXCY blk00000409 (
.CI(sig000006c3),
.DI(sig000006c3),
.S(sig00000819),
.O(sig00000721)
);
XORCY blk0000040a (
.CI(sig000006c3),
.LI(sig00000819),
.O(sig00000722)
);
MUXCY blk0000040b (
.CI(sig00000721),
.DI(sig000006c3),
.S(sig0000081a),
.O(sig00000723)
);
XORCY blk0000040c (
.CI(sig00000721),
.LI(sig0000081a),
.O(sig00000724)
);
MUXCY blk0000040d (
.CI(sig00000723),
.DI(sig000006c3),
.S(sig0000081b),
.O(sig00000725)
);
XORCY blk0000040e (
.CI(sig00000723),
.LI(sig0000081b),
.O(sig00000726)
);
MUXCY blk0000040f (
.CI(sig00000725),
.DI(sig000006c3),
.S(sig0000081c),
.O(sig00000727)
);
XORCY blk00000410 (
.CI(sig00000725),
.LI(sig0000081c),
.O(sig00000728)
);
MUXCY blk00000411 (
.CI(sig00000727),
.DI(sig000006c3),
.S(sig0000081d),
.O(sig00000729)
);
XORCY blk00000412 (
.CI(sig00000727),
.LI(sig0000081d),
.O(sig0000072a)
);
MUXCY blk00000413 (
.CI(sig00000729),
.DI(sig000006c3),
.S(sig0000081e),
.O(sig0000072b)
);
XORCY blk00000414 (
.CI(sig00000729),
.LI(sig0000081e),
.O(sig0000072c)
);
MUXCY blk00000415 (
.CI(sig0000072b),
.DI(sig000006c3),
.S(sig0000081f),
.O(sig0000072d)
);
XORCY blk00000416 (
.CI(sig0000072b),
.LI(sig0000081f),
.O(NLW_blk00000416_O_UNCONNECTED)
);
MUXCY blk00000417 (
.CI(sig0000072d),
.DI(sig00000001),
.S(sig00000001),
.O(sig0000072e)
);
XORCY blk00000418 (
.CI(sig0000072d),
.LI(sig00000001),
.O(NLW_blk00000418_O_UNCONNECTED)
);
MUXCY blk00000419 (
.CI(sig0000072e),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000072f)
);
XORCY blk0000041a (
.CI(sig0000072e),
.LI(sig000006c3),
.O(NLW_blk0000041a_O_UNCONNECTED)
);
MUXCY blk0000041b (
.CI(sig0000072f),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000730)
);
XORCY blk0000041c (
.CI(sig0000072f),
.LI(sig000006c3),
.O(NLW_blk0000041c_O_UNCONNECTED)
);
MUXCY blk0000041d (
.CI(sig00000730),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000731)
);
XORCY blk0000041e (
.CI(sig00000730),
.LI(sig000006c3),
.O(NLW_blk0000041e_O_UNCONNECTED)
);
MUXCY blk0000041f (
.CI(sig00000731),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000732)
);
XORCY blk00000420 (
.CI(sig00000731),
.LI(sig000006c3),
.O(NLW_blk00000420_O_UNCONNECTED)
);
MUXCY blk00000421 (
.CI(sig00000732),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000733)
);
XORCY blk00000422 (
.CI(sig00000732),
.LI(sig000006c3),
.O(NLW_blk00000422_O_UNCONNECTED)
);
MUXCY blk00000423 (
.CI(sig00000733),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000734)
);
XORCY blk00000424 (
.CI(sig00000733),
.LI(sig000006c3),
.O(NLW_blk00000424_O_UNCONNECTED)
);
MUXCY blk00000425 (
.CI(sig00000734),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000735)
);
XORCY blk00000426 (
.CI(sig00000734),
.LI(sig000006c3),
.O(NLW_blk00000426_O_UNCONNECTED)
);
MUXCY blk00000427 (
.CI(sig00000735),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000736)
);
XORCY blk00000428 (
.CI(sig00000735),
.LI(sig000006c3),
.O(NLW_blk00000428_O_UNCONNECTED)
);
MUXCY blk00000429 (
.CI(sig00000736),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000737)
);
XORCY blk0000042a (
.CI(sig00000736),
.LI(sig000006c3),
.O(NLW_blk0000042a_O_UNCONNECTED)
);
MUXCY blk0000042b (
.CI(sig00000737),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000738)
);
XORCY blk0000042c (
.CI(sig00000737),
.LI(sig000006c3),
.O(NLW_blk0000042c_O_UNCONNECTED)
);
XORCY blk0000042d (
.CI(sig00000738),
.LI(sig000006c3),
.O(NLW_blk0000042d_O_UNCONNECTED)
);
MUXCY blk0000042e (
.CI(sig00000001),
.DI(sig000006c3),
.S(sig00000820),
.O(sig00000739)
);
XORCY blk0000042f (
.CI(sig00000001),
.LI(sig00000820),
.O(sig0000073a)
);
MUXCY blk00000430 (
.CI(sig00000739),
.DI(sig000006c3),
.S(sig00000821),
.O(sig0000073b)
);
XORCY blk00000431 (
.CI(sig00000739),
.LI(sig00000821),
.O(sig0000073c)
);
MUXCY blk00000432 (
.CI(sig0000073b),
.DI(sig000006c3),
.S(sig00000822),
.O(sig0000073d)
);
XORCY blk00000433 (
.CI(sig0000073b),
.LI(sig00000822),
.O(sig0000073e)
);
MUXCY blk00000434 (
.CI(sig0000073d),
.DI(sig000006c3),
.S(sig00000823),
.O(sig0000073f)
);
XORCY blk00000435 (
.CI(sig0000073d),
.LI(sig00000823),
.O(sig00000740)
);
MUXCY blk00000436 (
.CI(sig0000073f),
.DI(sig000006c3),
.S(sig00000824),
.O(sig00000741)
);
XORCY blk00000437 (
.CI(sig0000073f),
.LI(sig00000824),
.O(sig00000742)
);
MUXCY blk00000438 (
.CI(sig00000741),
.DI(sig000006c3),
.S(sig00000825),
.O(sig00000743)
);
XORCY blk00000439 (
.CI(sig00000741),
.LI(sig00000825),
.O(sig00000744)
);
MUXCY blk0000043a (
.CI(sig00000743),
.DI(sig000006c3),
.S(sig00000826),
.O(sig00000745)
);
XORCY blk0000043b (
.CI(sig00000743),
.LI(sig00000826),
.O(NLW_blk0000043b_O_UNCONNECTED)
);
MUXCY blk0000043c (
.CI(sig00000745),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000746)
);
XORCY blk0000043d (
.CI(sig00000745),
.LI(sig00000001),
.O(sig00000747)
);
MUXCY blk0000043e (
.CI(sig00000746),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000748)
);
XORCY blk0000043f (
.CI(sig00000746),
.LI(sig000006c3),
.O(NLW_blk0000043f_O_UNCONNECTED)
);
MUXCY blk00000440 (
.CI(sig00000748),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000749)
);
XORCY blk00000441 (
.CI(sig00000748),
.LI(sig000006c3),
.O(NLW_blk00000441_O_UNCONNECTED)
);
MUXCY blk00000442 (
.CI(sig00000749),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074a)
);
XORCY blk00000443 (
.CI(sig00000749),
.LI(sig000006c3),
.O(NLW_blk00000443_O_UNCONNECTED)
);
MUXCY blk00000444 (
.CI(sig0000074a),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074b)
);
XORCY blk00000445 (
.CI(sig0000074a),
.LI(sig000006c3),
.O(NLW_blk00000445_O_UNCONNECTED)
);
MUXCY blk00000446 (
.CI(sig0000074b),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074c)
);
XORCY blk00000447 (
.CI(sig0000074b),
.LI(sig000006c3),
.O(NLW_blk00000447_O_UNCONNECTED)
);
MUXCY blk00000448 (
.CI(sig0000074c),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074d)
);
XORCY blk00000449 (
.CI(sig0000074c),
.LI(sig000006c3),
.O(NLW_blk00000449_O_UNCONNECTED)
);
MUXCY blk0000044a (
.CI(sig0000074d),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074e)
);
XORCY blk0000044b (
.CI(sig0000074d),
.LI(sig000006c3),
.O(NLW_blk0000044b_O_UNCONNECTED)
);
MUXCY blk0000044c (
.CI(sig0000074e),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig0000074f)
);
XORCY blk0000044d (
.CI(sig0000074e),
.LI(sig000006c3),
.O(NLW_blk0000044d_O_UNCONNECTED)
);
MUXCY blk0000044e (
.CI(sig0000074f),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000750)
);
XORCY blk0000044f (
.CI(sig0000074f),
.LI(sig000006c3),
.O(NLW_blk0000044f_O_UNCONNECTED)
);
MUXCY blk00000450 (
.CI(sig00000750),
.DI(sig000006c3),
.S(sig000006c3),
.O(sig00000751)
);
XORCY blk00000451 (
.CI(sig00000750),
.LI(sig000006c3),
.O(NLW_blk00000451_O_UNCONNECTED)
);
XORCY blk00000452 (
.CI(sig00000751),
.LI(sig000006c3),
.O(NLW_blk00000452_O_UNCONNECTED)
);
FD #(
.INIT ( 1'b0 ))
blk00000453 (
.C(clk),
.D(sig00000117),
.Q(sig0000076f)
);
FD #(
.INIT ( 1'b0 ))
blk00000454 (
.C(clk),
.D(sig00000116),
.Q(sig0000076e)
);
FD #(
.INIT ( 1'b0 ))
blk00000455 (
.C(clk),
.D(sig00000115),
.Q(sig0000076d)
);
FD #(
.INIT ( 1'b0 ))
blk00000456 (
.C(clk),
.D(sig00000114),
.Q(sig0000076c)
);
FD #(
.INIT ( 1'b0 ))
blk00000457 (
.C(clk),
.D(sig00000113),
.Q(sig0000076b)
);
FD #(
.INIT ( 1'b0 ))
blk00000458 (
.C(clk),
.D(sig00000112),
.Q(sig0000076a)
);
FD #(
.INIT ( 1'b0 ))
blk00000459 (
.C(clk),
.D(sig00000111),
.Q(sig00000769)
);
FD #(
.INIT ( 1'b0 ))
blk0000045a (
.C(clk),
.D(sig00000110),
.Q(sig00000752)
);
FD #(
.INIT ( 1'b0 ))
blk0000045b (
.C(clk),
.D(sig0000010f),
.Q(sig0000079d)
);
FD #(
.INIT ( 1'b0 ))
blk0000045c (
.C(clk),
.D(sig0000010e),
.Q(sig0000079c)
);
FD #(
.INIT ( 1'b0 ))
blk0000045d (
.C(clk),
.D(sig0000010d),
.Q(sig0000079b)
);
FD #(
.INIT ( 1'b0 ))
blk0000045e (
.C(clk),
.D(sig0000010c),
.Q(sig0000079a)
);
FD #(
.INIT ( 1'b0 ))
blk0000045f (
.C(clk),
.D(sig0000010b),
.Q(sig00000799)
);
FD #(
.INIT ( 1'b0 ))
blk00000460 (
.C(clk),
.D(sig0000010a),
.Q(sig00000798)
);
FD #(
.INIT ( 1'b0 ))
blk00000461 (
.C(clk),
.D(sig00000109),
.Q(sig00000797)
);
FD #(
.INIT ( 1'b0 ))
blk00000462 (
.C(clk),
.D(sig00000108),
.Q(sig00000796)
);
FD #(
.INIT ( 1'b0 ))
blk00000463 (
.C(clk),
.D(sig00000107),
.Q(sig00000795)
);
FD #(
.INIT ( 1'b0 ))
blk00000464 (
.C(clk),
.D(sig00000106),
.Q(sig00000794)
);
FD #(
.INIT ( 1'b0 ))
blk00000465 (
.C(clk),
.D(sig00000105),
.Q(sig00000793)
);
FD #(
.INIT ( 1'b0 ))
blk00000466 (
.C(clk),
.D(sig00000104),
.Q(sig00000792)
);
FD #(
.INIT ( 1'b0 ))
blk00000467 (
.C(clk),
.D(sig00000103),
.Q(sig00000791)
);
FD #(
.INIT ( 1'b0 ))
blk00000468 (
.C(clk),
.D(sig00000102),
.Q(sig00000790)
);
FD #(
.INIT ( 1'b0 ))
blk00000469 (
.C(clk),
.D(sig00000101),
.Q(sig0000078f)
);
FD #(
.INIT ( 1'b0 ))
blk0000046a (
.C(clk),
.D(sig00000100),
.Q(sig0000078e)
);
FD #(
.INIT ( 1'b0 ))
blk0000046b (
.C(clk),
.D(sig000000ff),
.Q(sig0000078d)
);
FD #(
.INIT ( 1'b0 ))
blk0000046c (
.C(clk),
.D(sig000000fe),
.Q(sig0000078c)
);
FD #(
.INIT ( 1'b0 ))
blk0000046d (
.C(clk),
.D(sig000000fd),
.Q(sig0000078b)
);
FD #(
.INIT ( 1'b0 ))
blk0000046e (
.C(clk),
.D(sig000000fc),
.Q(sig0000078a)
);
FD #(
.INIT ( 1'b0 ))
blk0000046f (
.C(clk),
.D(sig000000fb),
.Q(sig00000789)
);
FD #(
.INIT ( 1'b0 ))
blk00000470 (
.C(clk),
.D(sig000000fa),
.Q(sig00000788)
);
FD #(
.INIT ( 1'b0 ))
blk00000471 (
.C(clk),
.D(sig000000f9),
.Q(sig00000787)
);
FD #(
.INIT ( 1'b0 ))
blk00000472 (
.C(clk),
.D(sig000000f8),
.Q(sig00000786)
);
FD #(
.INIT ( 1'b0 ))
blk00000473 (
.C(clk),
.D(sig000000f7),
.Q(sig00000785)
);
FD #(
.INIT ( 1'b0 ))
blk00000474 (
.C(clk),
.D(sig000000f6),
.Q(sig00000784)
);
FD #(
.INIT ( 1'b0 ))
blk00000475 (
.C(clk),
.D(sig000000f5),
.Q(sig00000783)
);
FD #(
.INIT ( 1'b0 ))
blk00000476 (
.C(clk),
.D(sig000000f4),
.Q(sig00000782)
);
FD #(
.INIT ( 1'b0 ))
blk00000477 (
.C(clk),
.D(sig000000f3),
.Q(sig00000781)
);
FD #(
.INIT ( 1'b0 ))
blk00000478 (
.C(clk),
.D(sig000000f2),
.Q(sig00000780)
);
FD #(
.INIT ( 1'b0 ))
blk00000479 (
.C(clk),
.D(sig000000f1),
.Q(sig0000077f)
);
FD #(
.INIT ( 1'b0 ))
blk0000047a (
.C(clk),
.D(sig000000f0),
.Q(sig0000077e)
);
FD #(
.INIT ( 1'b0 ))
blk0000047b (
.C(clk),
.D(sig000000ef),
.Q(sig0000077d)
);
FD #(
.INIT ( 1'b0 ))
blk0000047c (
.C(clk),
.D(sig000000ee),
.Q(sig0000077c)
);
FD #(
.INIT ( 1'b0 ))
blk0000047d (
.C(clk),
.D(sig000000ed),
.Q(sig0000077b)
);
FD #(
.INIT ( 1'b0 ))
blk0000047e (
.C(clk),
.D(sig000000ec),
.Q(sig0000077a)
);
FD #(
.INIT ( 1'b0 ))
blk0000047f (
.C(clk),
.D(sig000000eb),
.Q(sig00000779)
);
FD #(
.INIT ( 1'b0 ))
blk00000480 (
.C(clk),
.D(sig000000ea),
.Q(sig00000778)
);
FD #(
.INIT ( 1'b0 ))
blk00000481 (
.C(clk),
.D(sig000000e9),
.Q(sig00000777)
);
FD #(
.INIT ( 1'b0 ))
blk00000482 (
.C(clk),
.D(sig000000e8),
.Q(sig00000776)
);
FD #(
.INIT ( 1'b0 ))
blk00000483 (
.C(clk),
.D(sig000000e7),
.Q(sig00000775)
);
FD #(
.INIT ( 1'b0 ))
blk00000484 (
.C(clk),
.D(sig000000e6),
.Q(sig00000774)
);
FD #(
.INIT ( 1'b0 ))
blk00000485 (
.C(clk),
.D(sig000000e5),
.Q(sig00000773)
);
FD #(
.INIT ( 1'b0 ))
blk00000486 (
.C(clk),
.D(sig000000e4),
.Q(sig00000772)
);
FD #(
.INIT ( 1'b0 ))
blk00000487 (
.C(clk),
.D(sig000000e3),
.Q(sig00000771)
);
FD #(
.INIT ( 1'b0 ))
blk00000488 (
.C(clk),
.D(sig000000e2),
.Q(sig00000770)
);
FDE #(
.INIT ( 1'b0 ))
blk00000489 (
.C(clk),
.CE(sig00000001),
.D(sig0000072c),
.Q(sig0000075f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048a (
.C(clk),
.CE(sig00000001),
.D(sig0000072a),
.Q(sig0000075e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048b (
.C(clk),
.CE(sig00000001),
.D(sig00000728),
.Q(sig0000075d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048c (
.C(clk),
.CE(sig00000001),
.D(sig00000726),
.Q(sig0000075c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048d (
.C(clk),
.CE(sig00000001),
.D(sig00000724),
.Q(sig0000075b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048e (
.C(clk),
.CE(sig00000001),
.D(sig00000722),
.Q(sig0000075a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000048f (
.C(clk),
.CE(sig00000001),
.D(sig00000747),
.Q(sig00000759)
);
FDE #(
.INIT ( 1'b0 ))
blk00000490 (
.C(clk),
.CE(sig00000001),
.D(sig00000744),
.Q(sig00000758)
);
FDE #(
.INIT ( 1'b0 ))
blk00000491 (
.C(clk),
.CE(sig00000001),
.D(sig00000742),
.Q(sig00000757)
);
FDE #(
.INIT ( 1'b0 ))
blk00000492 (
.C(clk),
.CE(sig00000001),
.D(sig00000740),
.Q(sig00000756)
);
FDE #(
.INIT ( 1'b0 ))
blk00000493 (
.C(clk),
.CE(sig00000001),
.D(sig0000073e),
.Q(sig00000755)
);
FDE #(
.INIT ( 1'b0 ))
blk00000494 (
.C(clk),
.CE(sig00000001),
.D(sig0000073c),
.Q(sig00000754)
);
FDE #(
.INIT ( 1'b0 ))
blk00000495 (
.C(clk),
.CE(sig00000001),
.D(sig0000073a),
.Q(sig00000753)
);
XORCY blk00000496 (
.CI(sig0000079e),
.LI(sig000007f2),
.O(sig000007b3)
);
XORCY blk00000497 (
.CI(sig0000079f),
.LI(sig000007f1),
.O(sig000007b2)
);
MUXCY blk00000498 (
.CI(sig0000079f),
.DI(sig000006c3),
.S(sig000007f1),
.O(sig0000079e)
);
XORCY blk00000499 (
.CI(sig000007a0),
.LI(sig000007f0),
.O(sig000007b1)
);
MUXCY blk0000049a (
.CI(sig000007a0),
.DI(sig000006c3),
.S(sig000007f0),
.O(sig0000079f)
);
XORCY blk0000049b (
.CI(sig000007a1),
.LI(sig000007ef),
.O(sig000007b0)
);
MUXCY blk0000049c (
.CI(sig000007a1),
.DI(sig000006c3),
.S(sig000007ef),
.O(sig000007a0)
);
XORCY blk0000049d (
.CI(sig000007a2),
.LI(sig000007ee),
.O(sig000007af)
);
MUXCY blk0000049e (
.CI(sig000007a2),
.DI(sig000006c3),
.S(sig000007ee),
.O(sig000007a1)
);
XORCY blk0000049f (
.CI(sig000007a3),
.LI(sig000007ed),
.O(sig000007ae)
);
MUXCY blk000004a0 (
.CI(sig000007a3),
.DI(sig000006c3),
.S(sig000007ed),
.O(sig000007a2)
);
XORCY blk000004a1 (
.CI(sig000007a4),
.LI(sig000007ec),
.O(sig000007ad)
);
MUXCY blk000004a2 (
.CI(sig000007a4),
.DI(sig000006c3),
.S(sig000007ec),
.O(sig000007a3)
);
XORCY blk000004a3 (
.CI(sig000007a5),
.LI(sig000007eb),
.O(sig000007ac)
);
MUXCY blk000004a4 (
.CI(sig000007a5),
.DI(sig000006c3),
.S(sig000007eb),
.O(sig000007a4)
);
XORCY blk000004a5 (
.CI(sig000007a6),
.LI(sig000007ea),
.O(sig000007ab)
);
MUXCY blk000004a6 (
.CI(sig000007a6),
.DI(sig000006c3),
.S(sig000007ea),
.O(sig000007a5)
);
XORCY blk000004a7 (
.CI(sig000007a7),
.LI(sig000007e9),
.O(sig000007aa)
);
MUXCY blk000004a8 (
.CI(sig000007a7),
.DI(sig000006c3),
.S(sig000007e9),
.O(sig000007a6)
);
XORCY blk000004a9 (
.CI(sig000006c3),
.LI(sig000007a8),
.O(sig000007a9)
);
MUXCY blk000004aa (
.CI(sig000006c3),
.DI(sig000007e8),
.S(sig000007a8),
.O(sig000007a7)
);
FD blk000004ab (
.C(clk),
.D(sig000007b3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [10])
);
FD blk000004ac (
.C(clk),
.D(sig000007b2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [9])
);
FD blk000004ad (
.C(clk),
.D(sig000007b1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [8])
);
FD blk000004ae (
.C(clk),
.D(sig000007b0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [7])
);
FD blk000004af (
.C(clk),
.D(sig000007af),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [6])
);
FD blk000004b0 (
.C(clk),
.D(sig000007ae),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [5])
);
FD blk000004b1 (
.C(clk),
.D(sig000007ad),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [4])
);
FD blk000004b2 (
.C(clk),
.D(sig000007ac),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [3])
);
FD blk000004b3 (
.C(clk),
.D(sig000007ab),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [2])
);
FD blk000004b4 (
.C(clk),
.D(sig000007aa),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [1])
);
FD blk000004b5 (
.C(clk),
.D(sig000007a9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [0])
);
FD blk000004b6 (
.C(clk),
.D(sig000007e7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [51])
);
FD blk000004b7 (
.C(clk),
.D(sig000007e6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [50])
);
FD blk000004b8 (
.C(clk),
.D(sig000007e5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [49])
);
FD blk000004b9 (
.C(clk),
.D(sig000007e4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [48])
);
FD blk000004ba (
.C(clk),
.D(sig000007e3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [47])
);
FD blk000004bb (
.C(clk),
.D(sig000007e2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [46])
);
FD blk000004bc (
.C(clk),
.D(sig000007e1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [45])
);
FD blk000004bd (
.C(clk),
.D(sig000007e0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [44])
);
FD blk000004be (
.C(clk),
.D(sig000007df),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [43])
);
FD blk000004bf (
.C(clk),
.D(sig000007de),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [42])
);
FD blk000004c0 (
.C(clk),
.D(sig000007dd),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [41])
);
FD blk000004c1 (
.C(clk),
.D(sig000007dc),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [40])
);
FD blk000004c2 (
.C(clk),
.D(sig000007db),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [39])
);
FD blk000004c3 (
.C(clk),
.D(sig000007da),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [38])
);
FD blk000004c4 (
.C(clk),
.D(sig000007d9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [37])
);
FD blk000004c5 (
.C(clk),
.D(sig000007d8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [36])
);
FD blk000004c6 (
.C(clk),
.D(sig000007d7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [35])
);
FD blk000004c7 (
.C(clk),
.D(sig000007d6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [34])
);
FD blk000004c8 (
.C(clk),
.D(sig000007d5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [33])
);
FD blk000004c9 (
.C(clk),
.D(sig000007d4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [32])
);
FD blk000004ca (
.C(clk),
.D(sig000007d3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [31])
);
FD blk000004cb (
.C(clk),
.D(sig000007d2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [30])
);
FD blk000004cc (
.C(clk),
.D(sig000007d1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [29])
);
FD blk000004cd (
.C(clk),
.D(sig000007d0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [28])
);
FD blk000004ce (
.C(clk),
.D(sig000007cf),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [27])
);
FD blk000004cf (
.C(clk),
.D(sig000007ce),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [26])
);
FD blk000004d0 (
.C(clk),
.D(sig000007cd),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [25])
);
FD blk000004d1 (
.C(clk),
.D(sig000007cc),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [24])
);
FD blk000004d2 (
.C(clk),
.D(sig000007cb),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [23])
);
FD blk000004d3 (
.C(clk),
.D(sig000007ca),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [22])
);
FD blk000004d4 (
.C(clk),
.D(sig000007c9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [21])
);
FD blk000004d5 (
.C(clk),
.D(sig000007c8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [20])
);
FD blk000004d6 (
.C(clk),
.D(sig000007c7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [19])
);
FD blk000004d7 (
.C(clk),
.D(sig000007c6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [18])
);
FD blk000004d8 (
.C(clk),
.D(sig000007c5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [17])
);
FD blk000004d9 (
.C(clk),
.D(sig000007c4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [16])
);
FD blk000004da (
.C(clk),
.D(sig000007c3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [15])
);
FD blk000004db (
.C(clk),
.D(sig000007c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [14])
);
FD blk000004dc (
.C(clk),
.D(sig000007c1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [13])
);
FD blk000004dd (
.C(clk),
.D(sig000007c0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [12])
);
FD blk000004de (
.C(clk),
.D(sig000007bf),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [11])
);
FD blk000004df (
.C(clk),
.D(sig000007be),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [10])
);
FD blk000004e0 (
.C(clk),
.D(sig000007bd),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [9])
);
FD blk000004e1 (
.C(clk),
.D(sig000007bc),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [8])
);
FD blk000004e2 (
.C(clk),
.D(sig000007bb),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [7])
);
FD blk000004e3 (
.C(clk),
.D(sig000007ba),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [6])
);
FD blk000004e4 (
.C(clk),
.D(sig000007b9),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [5])
);
FD blk000004e5 (
.C(clk),
.D(sig000007b8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [4])
);
FD blk000004e6 (
.C(clk),
.D(sig000007b7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [3])
);
FD blk000004e7 (
.C(clk),
.D(sig000007b6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [2])
);
FD blk000004e8 (
.C(clk),
.D(sig000007b5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [1])
);
FD blk000004e9 (
.C(clk),
.D(sig000007b4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [0])
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ea (
.I0(sig00000124),
.I1(sig00000134),
.I2(sig00000144),
.I3(sig00000154),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a2)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004eb (
.I0(sig00000123),
.I1(sig00000133),
.I2(sig00000143),
.I3(sig00000153),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a3)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ec (
.I0(sig0000027f),
.I1(sig0000012d),
.I2(sig0000013d),
.I3(sig0000014d),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a9)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ed (
.I0(sig00000122),
.I1(sig00000132),
.I2(sig00000142),
.I3(sig00000152),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a4)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ee (
.I0(sig00000121),
.I1(sig00000131),
.I2(sig00000141),
.I3(sig00000151),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a5)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004ef (
.I0(sig00000120),
.I1(sig00000130),
.I2(sig00000140),
.I3(sig00000150),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004f0 (
.I0(sig0000011f),
.I1(sig0000012f),
.I2(sig0000013f),
.I3(sig0000014f),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a7)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000004f1 (
.I0(sig0000011e),
.I1(sig0000012e),
.I2(sig0000013e),
.I3(sig0000014e),
.I4(sig00000118),
.I5(sig00000119),
.O(sig000000a8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f2 (
.I0(sig0000000e),
.I1(sig00000006),
.I2(sig00000002),
.I3(sig0000000a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b6)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f3 (
.I0(sig0000000f),
.I1(sig00000007),
.I2(sig00000003),
.I3(sig0000000b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f4 (
.I0(sig00000010),
.I1(sig00000008),
.I2(sig00000004),
.I3(sig0000000c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f5 (
.I0(sig00000011),
.I1(sig00000009),
.I2(sig00000005),
.I3(sig0000000d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000b9)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f6 (
.I0(sig00000012),
.I1(sig0000000a),
.I2(sig00000006),
.I3(sig0000000e),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000ba)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f7 (
.I0(sig00000016),
.I1(sig0000000e),
.I2(sig0000000a),
.I3(sig00000012),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000be)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f8 (
.I0(sig00000017),
.I1(sig0000000f),
.I2(sig0000000b),
.I3(sig00000013),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bf)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004f9 (
.I0(sig00000018),
.I1(sig00000010),
.I2(sig0000000c),
.I3(sig00000014),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c0)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fa (
.I0(sig00000019),
.I1(sig00000011),
.I2(sig0000000d),
.I3(sig00000015),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c1)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fb (
.I0(sig0000001a),
.I1(sig00000012),
.I2(sig0000000e),
.I3(sig00000016),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c2)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fc (
.I0(sig0000001f),
.I1(sig00000017),
.I2(sig00000013),
.I3(sig0000001b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fd (
.I0(sig00000020),
.I1(sig00000018),
.I2(sig00000014),
.I3(sig0000001c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004fe (
.I0(sig00000021),
.I1(sig00000019),
.I2(sig00000015),
.I3(sig0000001d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c9)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000004ff (
.I0(sig00000013),
.I1(sig0000000b),
.I2(sig00000007),
.I3(sig0000000f),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bb)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000500 (
.I0(sig00000022),
.I1(sig0000001a),
.I2(sig00000016),
.I3(sig0000001e),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000ca)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000501 (
.I0(sig0000001b),
.I1(sig00000013),
.I2(sig0000000f),
.I3(sig00000017),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c3)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000502 (
.I0(sig00000023),
.I1(sig0000001b),
.I2(sig00000017),
.I3(sig0000001f),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cb)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000503 (
.I0(sig00000024),
.I1(sig0000001c),
.I2(sig00000018),
.I3(sig00000020),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cc)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000504 (
.I0(sig0000001c),
.I1(sig00000014),
.I2(sig00000010),
.I3(sig00000018),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c4)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000505 (
.I0(sig00000025),
.I1(sig0000001d),
.I2(sig00000019),
.I3(sig00000021),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cd)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000506 (
.I0(sig0000001d),
.I1(sig00000015),
.I2(sig00000011),
.I3(sig00000019),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c5)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000507 (
.I0(sig00000026),
.I1(sig0000001e),
.I2(sig0000001a),
.I3(sig00000022),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000ce)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000508 (
.I0(sig0000001e),
.I1(sig00000016),
.I2(sig00000012),
.I3(sig0000001a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000c6)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000509 (
.I0(sig00000027),
.I1(sig0000001f),
.I2(sig0000001b),
.I3(sig00000023),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000cf)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050a (
.I0(sig00000028),
.I1(sig00000020),
.I2(sig0000001c),
.I3(sig00000024),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d0)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050b (
.I0(sig00000029),
.I1(sig00000021),
.I2(sig0000001d),
.I3(sig00000025),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d1)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050c (
.I0(sig0000002a),
.I1(sig00000022),
.I2(sig0000001e),
.I3(sig00000026),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d2)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050d (
.I0(sig00000014),
.I1(sig0000000c),
.I2(sig00000008),
.I3(sig00000010),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bc)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050e (
.I0(sig0000002b),
.I1(sig00000023),
.I2(sig0000001f),
.I3(sig00000027),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d3)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000050f (
.I0(sig0000002c),
.I1(sig00000024),
.I2(sig00000020),
.I3(sig00000028),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d4)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000510 (
.I0(sig0000002d),
.I1(sig00000025),
.I2(sig00000021),
.I3(sig00000029),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d5)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000511 (
.I0(sig0000002e),
.I1(sig00000026),
.I2(sig00000022),
.I3(sig0000002a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d6)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000512 (
.I0(sig0000002f),
.I1(sig00000027),
.I2(sig00000023),
.I3(sig0000002b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d7)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000513 (
.I0(sig00000030),
.I1(sig00000028),
.I2(sig00000024),
.I3(sig0000002c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d8)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000514 (
.I0(sig00000038),
.I1(sig00000034),
.I2(sig00000030),
.I3(sig0000002c),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000e0)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000515 (
.I0(sig00000031),
.I1(sig00000029),
.I2(sig00000025),
.I3(sig0000002d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000d9)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000516 (
.I0(sig00000032),
.I1(sig0000002e),
.I2(sig0000002a),
.I3(sig00000026),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000da)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000517 (
.I0(sig00000039),
.I1(sig00000035),
.I2(sig00000031),
.I3(sig0000002d),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000e1)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000518 (
.I0(sig00000015),
.I1(sig0000000d),
.I2(sig00000009),
.I3(sig00000011),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000bd)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000519 (
.I0(sig00000033),
.I1(sig0000002f),
.I2(sig0000002b),
.I3(sig00000027),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000db)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051a (
.I0(sig00000034),
.I1(sig00000030),
.I2(sig0000002c),
.I3(sig00000028),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000dc)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051b (
.I0(sig00000035),
.I1(sig00000031),
.I2(sig0000002d),
.I3(sig00000029),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000dd)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051c (
.I0(sig00000036),
.I1(sig00000032),
.I2(sig0000002e),
.I3(sig0000002a),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000de)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000051d (
.I0(sig00000037),
.I1(sig00000033),
.I2(sig0000002f),
.I3(sig0000002b),
.I4(sig0000011a),
.I5(sig0000011b),
.O(sig000000df)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000051e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006d),
.I3(sig0000006b),
.I4(sig0000006c),
.I5(sig0000006e),
.O(sig00000114)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000051f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006b),
.I3(sig00000069),
.I4(sig0000006a),
.I5(sig0000006c),
.O(sig00000112)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000520 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000041),
.I3(sig0000003f),
.I4(sig00000040),
.I5(sig00000042),
.O(sig000000e8)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000521 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003f),
.I3(sig0000003d),
.I4(sig0000003e),
.I5(sig00000040),
.O(sig000000e6)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000522 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000042),
.I3(sig00000040),
.I4(sig00000041),
.I5(sig00000043),
.O(sig000000e9)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000523 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000040),
.I3(sig0000003e),
.I4(sig0000003f),
.I5(sig00000041),
.O(sig000000e7)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000524 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000043),
.I3(sig00000041),
.I4(sig00000042),
.I5(sig00000044),
.O(sig000000ea)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000525 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000048),
.I3(sig00000046),
.I4(sig00000047),
.I5(sig00000049),
.O(sig000000ef)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000526 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000046),
.I3(sig00000044),
.I4(sig00000045),
.I5(sig00000047),
.O(sig000000ed)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000527 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000049),
.I3(sig00000047),
.I4(sig00000048),
.I5(sig0000004a),
.O(sig000000f0)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000528 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000047),
.I3(sig00000045),
.I4(sig00000046),
.I5(sig00000048),
.O(sig000000ee)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000529 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004a),
.I3(sig00000048),
.I4(sig00000049),
.I5(sig0000004b),
.O(sig000000f1)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052a (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006e),
.I3(sig0000006c),
.I4(sig0000006d),
.I5(sig0000006f),
.O(sig00000115)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052b (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006c),
.I3(sig0000006a),
.I4(sig0000006b),
.I5(sig0000006d),
.O(sig00000113)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052c (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000044),
.I3(sig00000042),
.I4(sig00000043),
.I5(sig00000045),
.O(sig000000eb)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052d (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000051),
.I3(sig0000004f),
.I4(sig00000050),
.I5(sig00000052),
.O(sig000000f8)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004f),
.I3(sig0000004d),
.I4(sig0000004e),
.I5(sig00000050),
.O(sig000000f6)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000052f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000052),
.I3(sig00000050),
.I4(sig00000051),
.I5(sig00000053),
.O(sig000000f9)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000530 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000050),
.I3(sig0000004e),
.I4(sig0000004f),
.I5(sig00000051),
.O(sig000000f7)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000531 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000053),
.I3(sig00000051),
.I4(sig00000052),
.I5(sig00000054),
.O(sig000000fa)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000532 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000054),
.I3(sig00000052),
.I4(sig00000053),
.I5(sig00000055),
.O(sig000000fb)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000533 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004b),
.I3(sig00000049),
.I4(sig0000004a),
.I5(sig0000004c),
.O(sig000000f2)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000534 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006f),
.I3(sig0000006d),
.I4(sig0000006e),
.I5(sig00000070),
.O(sig00000116)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000535 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000055),
.I3(sig00000053),
.I4(sig00000054),
.I5(sig00000056),
.O(sig000000fc)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000536 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000056),
.I3(sig00000054),
.I4(sig00000055),
.I5(sig00000057),
.O(sig000000fd)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000537 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000057),
.I3(sig00000055),
.I4(sig00000056),
.I5(sig00000058),
.O(sig000000fe)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000538 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000058),
.I3(sig00000056),
.I4(sig00000057),
.I5(sig00000059),
.O(sig000000ff)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000539 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000045),
.I3(sig00000043),
.I4(sig00000044),
.I5(sig00000046),
.O(sig000000ec)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053a (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000059),
.I3(sig00000057),
.I4(sig00000058),
.I5(sig0000005a),
.O(sig00000100)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053b (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005a),
.I3(sig00000058),
.I4(sig00000059),
.I5(sig0000005b),
.O(sig00000101)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053c (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005b),
.I3(sig00000059),
.I4(sig0000005a),
.I5(sig0000005c),
.O(sig00000102)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053d (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005c),
.I3(sig0000005a),
.I4(sig0000005b),
.I5(sig0000005d),
.O(sig00000103)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005d),
.I3(sig0000005b),
.I4(sig0000005c),
.I5(sig0000005e),
.O(sig00000104)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000053f (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004c),
.I3(sig0000004a),
.I4(sig0000004b),
.I5(sig0000004d),
.O(sig000000f3)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000540 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005e),
.I3(sig0000005c),
.I4(sig0000005d),
.I5(sig0000005f),
.O(sig00000105)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000541 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000005f),
.I3(sig0000005d),
.I4(sig0000005e),
.I5(sig00000060),
.O(sig00000106)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000542 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000060),
.I3(sig0000005e),
.I4(sig0000005f),
.I5(sig00000061),
.O(sig00000107)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000543 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000061),
.I3(sig0000005f),
.I4(sig00000060),
.I5(sig00000062),
.O(sig00000108)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000544 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000062),
.I3(sig00000060),
.I4(sig00000061),
.I5(sig00000063),
.O(sig00000109)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000545 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000063),
.I3(sig00000061),
.I4(sig00000062),
.I5(sig00000064),
.O(sig0000010a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000546 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000064),
.I3(sig00000062),
.I4(sig00000063),
.I5(sig00000065),
.O(sig0000010b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000547 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000070),
.I3(sig0000006e),
.I4(sig0000006f),
.I5(sig00000071),
.O(sig00000117)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000548 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000065),
.I3(sig00000063),
.I4(sig00000064),
.I5(sig00000066),
.O(sig0000010c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000549 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000066),
.I3(sig00000064),
.I4(sig00000065),
.I5(sig00000067),
.O(sig0000010d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054a (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004d),
.I3(sig0000004b),
.I4(sig0000004c),
.I5(sig0000004e),
.O(sig000000f4)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054b (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000067),
.I3(sig00000065),
.I4(sig00000066),
.I5(sig00000068),
.O(sig0000010e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054c (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000068),
.I3(sig00000066),
.I4(sig00000067),
.I5(sig00000069),
.O(sig0000010f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054d (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig00000069),
.I3(sig00000067),
.I4(sig00000068),
.I5(sig0000006a),
.O(sig00000110)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000054e (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000006a),
.I3(sig00000068),
.I4(sig00000069),
.I5(sig0000006b),
.O(sig00000111)
);
LUT6 #(
.INIT ( 64'hAAAAFF00F0F0CCCC ))
blk0000054f (
.I0(sig0000003a),
.I1(sig0000003d),
.I2(sig0000003b),
.I3(sig0000003c),
.I4(sig0000011c),
.I5(sig0000011d),
.O(sig000000e3)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000550 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003d),
.I3(sig0000003b),
.I4(sig0000003c),
.I5(sig0000003e),
.O(sig000000e4)
);
LUT5 #(
.INIT ( 32'h00AAF0CC ))
blk00000551 (
.I0(sig0000003a),
.I1(sig0000003c),
.I2(sig0000003b),
.I3(sig0000011d),
.I4(sig0000011c),
.O(sig000000e2)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000552 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000003e),
.I3(sig0000003c),
.I4(sig0000003d),
.I5(sig0000003f),
.O(sig000000e5)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000553 (
.I0(sig0000011d),
.I1(sig0000011c),
.I2(sig0000004e),
.I3(sig0000004c),
.I4(sig0000004d),
.I5(sig0000004f),
.O(sig000000f5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000554 (
.I0(a[52]),
.I1(b[52]),
.O(sig00000156)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000555 (
.I0(b[63]),
.I1(operation[0]),
.O(sig000002a9)
);
LUT3 #(
.INIT ( 8'hF8 ))
blk00000556 (
.I0(sig0000027c),
.I1(sig0000027a),
.I2(sig0000027b),
.O(sig0000022e)
);
LUT5 #(
.INIT ( 32'hFEEE0222 ))
blk00000557 (
.I0(sig000002f5),
.I1(sig0000027b),
.I2(sig0000027c),
.I3(sig0000027a),
.I4(sig000002f4),
.O(sig000002a8)
);
LUT4 #(
.INIT ( 16'hAA8A ))
blk00000558 (
.I0(sig000002ea),
.I1(sig000002eb),
.I2(sig0000030c),
.I3(sig000002ec),
.O(sig000002a0)
);
LUT4 #(
.INIT ( 16'hEA2A ))
blk00000559 (
.I0(sig000002f4),
.I1(sig00000313),
.I2(sig00000314),
.I3(sig000002f5),
.O(sig000002a6)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk0000055a (
.I0(sig00000313),
.I1(sig00000314),
.I2(sig00000310),
.I3(sig00000311),
.O(sig00000293)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk0000055b (
.I0(sig00000313),
.I1(sig00000314),
.I2(sig00000310),
.I3(sig00000311),
.O(sig00000292)
);
LUT5 #(
.INIT ( 32'hFFFF1504 ))
blk0000055c (
.I0(sig000002f2),
.I1(sig000002f1),
.I2(sig000004b6),
.I3(sig000002ef),
.I4(sig000002f3),
.O(sig000002a5)
);
LUT4 #(
.INIT ( 16'h5554 ))
blk0000055d (
.I0(sig000002f3),
.I1(sig000002f1),
.I2(sig000002ef),
.I3(sig000002f2),
.O(sig000002a4)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF55555554 ))
blk0000055e (
.I0(sig000002eb),
.I1(sig0000030c),
.I2(sig000002b8),
.I3(sig000002c5),
.I4(sig000002c4),
.I5(sig000002ec),
.O(sig000002a2)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAABAA ))
blk0000055f (
.I0(sig000002eb),
.I1(sig0000030c),
.I2(sig000002ec),
.I3(sig000002c5),
.I4(sig000002b8),
.I5(sig000002c4),
.O(sig000002a1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000560 (
.I0(sig0000024a),
.I1(sig0000030b),
.I2(sig00000300),
.O(sig0000028e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000561 (
.I0(sig000002f7),
.I1(sig00000302),
.I2(sig0000024a),
.O(sig00000285)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000562 (
.I0(sig0000024a),
.I1(sig00000303),
.I2(sig000002f8),
.O(sig00000286)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000563 (
.I0(sig0000024a),
.I1(sig00000304),
.I2(sig000002f9),
.O(sig00000287)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000564 (
.I0(sig0000024a),
.I1(sig00000305),
.I2(sig000002fa),
.O(sig00000288)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000565 (
.I0(sig0000024a),
.I1(sig00000306),
.I2(sig000002fb),
.O(sig00000289)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000566 (
.I0(sig0000024a),
.I1(sig00000307),
.I2(sig000002fc),
.O(sig0000028a)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000567 (
.I0(sig0000024a),
.I1(sig00000308),
.I2(sig000002fd),
.O(sig0000028b)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000568 (
.I0(sig0000024a),
.I1(sig00000309),
.I2(sig000002fe),
.O(sig0000028c)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000569 (
.I0(sig0000024a),
.I1(sig0000030a),
.I2(sig000002ff),
.O(sig0000028d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000056a (
.I0(sig000002f5),
.I1(sig000002f4),
.O(sig00000290)
);
LUT3 #(
.INIT ( 8'h53 ))
blk0000056b (
.I0(sig00000301),
.I1(sig000002f6),
.I2(sig0000024a),
.O(sig00000284)
);
LUT2 #(
.INIT ( 4'hE ))
blk0000056c (
.I0(sig000002b7),
.I1(sig000002b6),
.O(sig00000277)
);
LUT2 #(
.INIT ( 4'h2 ))
blk0000056d (
.I0(sig000002b6),
.I1(sig000002b7),
.O(sig00000278)
);
LUT2 #(
.INIT ( 4'h2 ))
blk0000056e (
.I0(sig000002b7),
.I1(sig000002b6),
.O(sig00000279)
);
LUT4 #(
.INIT ( 16'h22F2 ))
blk0000056f (
.I0(sig00000313),
.I1(sig00000314),
.I2(sig00000310),
.I3(sig00000311),
.O(sig00000291)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000570 (
.I0(sig000002c6),
.I1(sig0000030d),
.O(sig0000029f)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000571 (
.I0(sig000002f5),
.I1(sig000002f4),
.O(sig000002a7)
);
LUT2 #(
.INIT ( 4'hE ))
blk00000572 (
.I0(sig0000030f),
.I1(sig00000312),
.O(sig0000022c)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000573 (
.I0(sig0000030f),
.I1(sig00000312),
.O(sig0000022d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000574 (
.I0(a[42]),
.I1(a[43]),
.I2(a[44]),
.I3(a[45]),
.I4(a[46]),
.I5(a[47]),
.O(sig00000315)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000575 (
.I0(a[36]),
.I1(a[37]),
.I2(a[38]),
.I3(a[39]),
.I4(a[40]),
.I5(a[41]),
.O(sig00000316)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000576 (
.I0(a[30]),
.I1(a[31]),
.I2(a[32]),
.I3(a[33]),
.I4(a[34]),
.I5(a[35]),
.O(sig00000317)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000577 (
.I0(a[24]),
.I1(a[25]),
.I2(a[26]),
.I3(a[27]),
.I4(a[28]),
.I5(a[29]),
.O(sig00000318)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000578 (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.I5(a[23]),
.O(sig00000319)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000579 (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000031a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057a (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000031b)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057b (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000031c)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000057c (
.I0(a[48]),
.I1(a[49]),
.I2(a[50]),
.I3(a[51]),
.O(sig0000031d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057d (
.I0(b[42]),
.I1(b[43]),
.I2(b[44]),
.I3(b[45]),
.I4(b[46]),
.I5(b[47]),
.O(sig0000031e)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057e (
.I0(b[36]),
.I1(b[37]),
.I2(b[38]),
.I3(b[39]),
.I4(b[40]),
.I5(b[41]),
.O(sig0000031f)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000057f (
.I0(b[30]),
.I1(b[31]),
.I2(b[32]),
.I3(b[33]),
.I4(b[34]),
.I5(b[35]),
.O(sig00000320)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000580 (
.I0(b[24]),
.I1(b[25]),
.I2(b[26]),
.I3(b[27]),
.I4(b[28]),
.I5(b[29]),
.O(sig00000321)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000581 (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.I5(b[23]),
.O(sig00000322)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000582 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000323)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000583 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000324)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000584 (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000325)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000585 (
.I0(b[48]),
.I1(b[49]),
.I2(b[50]),
.I3(b[51]),
.O(sig00000326)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000586 (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000346)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000587 (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000348)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000588 (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig0000034a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000589 (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig0000034c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058a (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000034e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058b (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig00000350)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058c (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig00000352)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058d (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000354)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058e (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000356)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058f (
.I0(b[31]),
.I1(a[31]),
.I2(b[30]),
.I3(a[30]),
.O(sig0000033a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000590 (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig0000033c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000591 (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000033e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000592 (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig00000340)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000593 (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig00000342)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000594 (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000344)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000595 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000358)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000596 (
.I0(b[31]),
.I1(a[31]),
.I2(b[30]),
.I3(a[30]),
.O(sig00000339)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000597 (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig0000033b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000598 (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000033d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk00000599 (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig0000033f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059a (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig00000341)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059b (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000343)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059c (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000345)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059d (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000347)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059e (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig00000349)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk0000059f (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig0000034b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a0 (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000034d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a1 (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig0000034f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a2 (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig00000351)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a3 (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000353)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a4 (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000355)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005a5 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000357)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a6 (
.I0(b[51]),
.I1(a[51]),
.I2(b[50]),
.I3(a[50]),
.O(sig00000366)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a7 (
.I0(b[49]),
.I1(a[49]),
.I2(b[48]),
.I3(a[48]),
.O(sig00000368)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a8 (
.I0(b[47]),
.I1(a[47]),
.I2(b[46]),
.I3(a[46]),
.O(sig0000036a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005a9 (
.I0(b[45]),
.I1(a[45]),
.I2(b[44]),
.I3(a[44]),
.O(sig0000036c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005aa (
.I0(b[43]),
.I1(a[43]),
.I2(b[42]),
.I3(a[42]),
.O(sig0000036e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ab (
.I0(b[41]),
.I1(a[41]),
.I2(b[40]),
.I3(a[40]),
.O(sig00000370)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ac (
.I0(b[39]),
.I1(a[39]),
.I2(b[38]),
.I3(a[38]),
.O(sig00000372)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ad (
.I0(b[37]),
.I1(a[37]),
.I2(b[36]),
.I3(a[36]),
.O(sig00000374)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005ae (
.I0(b[35]),
.I1(a[35]),
.I2(b[34]),
.I3(a[34]),
.O(sig00000376)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000005af (
.I0(b[62]),
.I1(a[62]),
.O(sig0000035a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b0 (
.I0(b[61]),
.I1(a[61]),
.I2(b[60]),
.I3(a[60]),
.O(sig0000035c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b1 (
.I0(b[59]),
.I1(a[59]),
.I2(b[58]),
.I3(a[58]),
.O(sig0000035e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b2 (
.I0(b[57]),
.I1(a[57]),
.I2(b[56]),
.I3(a[56]),
.O(sig00000360)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b3 (
.I0(b[55]),
.I1(a[55]),
.I2(b[54]),
.I3(a[54]),
.O(sig00000362)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b4 (
.I0(b[53]),
.I1(a[53]),
.I2(b[52]),
.I3(a[52]),
.O(sig00000364)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000005b5 (
.I0(b[33]),
.I1(a[33]),
.I2(b[32]),
.I3(a[32]),
.O(sig00000378)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000005b6 (
.I0(b[62]),
.I1(a[62]),
.O(sig00000359)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005b7 (
.I0(b[61]),
.I1(a[61]),
.I2(b[60]),
.I3(a[60]),
.O(sig0000035b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005b8 (
.I0(b[59]),
.I1(a[59]),
.I2(b[58]),
.I3(a[58]),
.O(sig0000035d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005b9 (
.I0(b[57]),
.I1(a[57]),
.I2(b[56]),
.I3(a[56]),
.O(sig0000035f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005ba (
.I0(b[55]),
.I1(a[55]),
.I2(b[54]),
.I3(a[54]),
.O(sig00000361)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bb (
.I0(b[53]),
.I1(a[53]),
.I2(b[52]),
.I3(a[52]),
.O(sig00000363)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bc (
.I0(b[51]),
.I1(a[51]),
.I2(b[50]),
.I3(a[50]),
.O(sig00000365)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bd (
.I0(b[49]),
.I1(a[49]),
.I2(b[48]),
.I3(a[48]),
.O(sig00000367)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005be (
.I0(b[47]),
.I1(a[47]),
.I2(b[46]),
.I3(a[46]),
.O(sig00000369)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005bf (
.I0(b[45]),
.I1(a[45]),
.I2(b[44]),
.I3(a[44]),
.O(sig0000036b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c0 (
.I0(b[43]),
.I1(a[43]),
.I2(b[42]),
.I3(a[42]),
.O(sig0000036d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c1 (
.I0(b[41]),
.I1(a[41]),
.I2(b[40]),
.I3(a[40]),
.O(sig0000036f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c2 (
.I0(b[39]),
.I1(a[39]),
.I2(b[38]),
.I3(a[38]),
.O(sig00000371)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c3 (
.I0(b[37]),
.I1(a[37]),
.I2(b[36]),
.I3(a[36]),
.O(sig00000373)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c4 (
.I0(b[35]),
.I1(a[35]),
.I2(b[34]),
.I3(a[34]),
.O(sig00000375)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000005c5 (
.I0(b[33]),
.I1(a[33]),
.I2(b[32]),
.I3(a[32]),
.O(sig00000377)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c6 (
.I0(b[59]),
.I1(a[59]),
.I2(b[61]),
.I3(a[61]),
.I4(b[60]),
.I5(a[60]),
.O(sig0000039a)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c7 (
.I0(b[56]),
.I1(a[56]),
.I2(b[58]),
.I3(a[58]),
.I4(b[57]),
.I5(a[57]),
.O(sig0000039b)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c8 (
.I0(b[53]),
.I1(a[53]),
.I2(b[55]),
.I3(a[55]),
.I4(b[54]),
.I5(a[54]),
.O(sig0000039c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005c9 (
.I0(b[50]),
.I1(a[50]),
.I2(b[52]),
.I3(a[52]),
.I4(b[51]),
.I5(a[51]),
.O(sig0000039d)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005ca (
.I0(b[47]),
.I1(a[47]),
.I2(b[49]),
.I3(a[49]),
.I4(b[48]),
.I5(a[48]),
.O(sig0000039e)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cb (
.I0(b[44]),
.I1(a[44]),
.I2(b[46]),
.I3(a[46]),
.I4(b[45]),
.I5(a[45]),
.O(sig0000039f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cc (
.I0(b[42]),
.I1(a[42]),
.I2(b[41]),
.I3(a[41]),
.I4(b[43]),
.I5(a[43]),
.O(sig000003a0)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cd (
.I0(b[38]),
.I1(a[38]),
.I2(b[40]),
.I3(a[40]),
.I4(b[39]),
.I5(a[39]),
.O(sig000003a1)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005ce (
.I0(b[35]),
.I1(a[35]),
.I2(b[37]),
.I3(a[37]),
.I4(b[36]),
.I5(a[36]),
.O(sig000003a2)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000005cf (
.I0(b[32]),
.I1(a[32]),
.I2(b[34]),
.I3(a[34]),
.I4(b[33]),
.I5(a[33]),
.O(sig000003a3)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000005d0 (
.I0(a[62]),
.I1(b[62]),
.O(sig00000399)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d1 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004ec),
.I3(sig0000050c),
.I4(sig000004fc),
.I5(sig000004dc),
.O(sig0000043f)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d2 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fc),
.I3(sig0000050c),
.O(sig0000041f)
);
LUT5 #(
.INIT ( 32'hE6C4A280 ))
blk000005d3 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000506),
.I3(sig000004f6),
.I4(sig000004e6),
.O(sig00000445)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d4 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f6),
.I3(sig00000506),
.O(sig00000425)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d5 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004eb),
.I3(sig0000050b),
.I4(sig000004fb),
.I5(sig000004db),
.O(sig00000440)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d6 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fb),
.I3(sig0000050b),
.O(sig00000420)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d7 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004ea),
.I3(sig0000050a),
.I4(sig000004fa),
.I5(sig000004da),
.O(sig00000441)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005d8 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fa),
.I3(sig0000050a),
.O(sig00000421)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005d9 (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004e8),
.I3(sig00000508),
.I4(sig000004f8),
.I5(sig000004d8),
.O(sig00000443)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005da (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f8),
.I3(sig00000508),
.O(sig00000423)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005db (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004e9),
.I3(sig00000509),
.I4(sig000004f9),
.I5(sig000004d9),
.O(sig00000442)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005dc (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f9),
.I3(sig00000509),
.O(sig00000422)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000005dd (
.I0(sig000003d5),
.I1(sig000003d4),
.I2(sig000004e7),
.I3(sig00000507),
.I4(sig000004f7),
.I5(sig000004d7),
.O(sig00000444)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000005de (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f7),
.I3(sig00000507),
.O(sig00000424)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005df (
.I0(sig000001ea),
.I1(sig000001eb),
.I2(sig0000021f),
.I3(sig0000021e),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000536)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e0 (
.I0(sig000001eb),
.I1(sig000001ec),
.I2(sig00000220),
.I3(sig0000021f),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000537)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e1 (
.I0(sig000001e9),
.I1(sig000001ea),
.I2(sig0000021e),
.I3(sig0000021d),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000535)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e2 (
.I0(sig000001e8),
.I1(sig000001e9),
.I2(sig0000021d),
.I3(sig0000021c),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000534)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e3 (
.I0(sig000001e7),
.I1(sig000001e8),
.I2(sig0000021c),
.I3(sig0000021b),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000533)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e4 (
.I0(sig000001e3),
.I1(sig000001e4),
.I2(sig00000218),
.I3(sig00000217),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e5 (
.I0(sig000001e4),
.I1(sig000001e5),
.I2(sig00000219),
.I3(sig00000218),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000530)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e6 (
.I0(sig000001e2),
.I1(sig000001e3),
.I2(sig00000217),
.I3(sig00000216),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052e)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e7 (
.I0(sig000001e6),
.I1(sig000001e7),
.I2(sig0000021b),
.I3(sig0000021a),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000532)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e8 (
.I0(sig000001e1),
.I1(sig000001e2),
.I2(sig00000216),
.I3(sig00000215),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052d)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005e9 (
.I0(sig000001e0),
.I1(sig000001e1),
.I2(sig00000215),
.I3(sig00000214),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052c)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ea (
.I0(sig000001da),
.I1(sig000001db),
.I2(sig0000020f),
.I3(sig0000020e),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000526)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005eb (
.I0(sig000001db),
.I1(sig000001dc),
.I2(sig00000210),
.I3(sig0000020f),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000527)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ec (
.I0(sig000001d9),
.I1(sig000001da),
.I2(sig0000020e),
.I3(sig0000020d),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000525)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ed (
.I0(sig000001df),
.I1(sig000001e0),
.I2(sig00000214),
.I3(sig00000213),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052b)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ee (
.I0(sig000001d8),
.I1(sig000001d9),
.I2(sig0000020d),
.I3(sig0000020c),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000524)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ef (
.I0(sig000001d7),
.I1(sig000001d8),
.I2(sig0000020c),
.I3(sig0000020b),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000523)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f0 (
.I0(sig000001d6),
.I1(sig000001d7),
.I2(sig0000020b),
.I3(sig0000020a),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000522)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f1 (
.I0(sig000001d5),
.I1(sig000001d6),
.I2(sig0000020a),
.I3(sig00000209),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000521)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f2 (
.I0(sig000001d4),
.I1(sig000001d5),
.I2(sig00000209),
.I3(sig00000208),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000520)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f3 (
.I0(sig000001e5),
.I1(sig000001e6),
.I2(sig0000021a),
.I3(sig00000219),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000531)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f4 (
.I0(sig000001d3),
.I1(sig000001d4),
.I2(sig00000208),
.I3(sig00000207),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f5 (
.I0(sig000001d2),
.I1(sig000001d3),
.I2(sig00000207),
.I3(sig00000206),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051e)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f6 (
.I0(sig000001d1),
.I1(sig000001d2),
.I2(sig00000206),
.I3(sig00000205),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051d)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f7 (
.I0(sig000001c3),
.I1(sig000001c4),
.I2(sig000001f8),
.I3(sig000001f7),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000050f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f8 (
.I0(sig000001c4),
.I1(sig000001c5),
.I2(sig000001f9),
.I3(sig000001f8),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000510)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005f9 (
.I0(sig000001d0),
.I1(sig000001d1),
.I2(sig00000205),
.I3(sig00000204),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051c)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fa (
.I0(sig000001de),
.I1(sig000001df),
.I2(sig00000213),
.I3(sig00000212),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000052a)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fb (
.I0(sig000001cf),
.I1(sig000001d0),
.I2(sig00000204),
.I3(sig00000203),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051b)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fc (
.I0(sig000001ce),
.I1(sig000001cf),
.I2(sig00000203),
.I3(sig00000202),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000051a)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fd (
.I0(sig000001cd),
.I1(sig000001ce),
.I2(sig00000202),
.I3(sig00000201),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000519)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005fe (
.I0(sig000001cc),
.I1(sig000001cd),
.I2(sig00000201),
.I3(sig00000200),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000518)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk000005ff (
.I0(sig000001c6),
.I1(sig000001c7),
.I2(sig000001fb),
.I3(sig000001fa),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000512)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000600 (
.I0(sig000001c5),
.I1(sig000001c6),
.I2(sig000001fa),
.I3(sig000001f9),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000511)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000601 (
.I0(sig000001cb),
.I1(sig000001cc),
.I2(sig00000200),
.I3(sig000001ff),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000517)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000602 (
.I0(sig000001ca),
.I1(sig000001cb),
.I2(sig000001ff),
.I3(sig000001fe),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000516)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000603 (
.I0(sig000001c9),
.I1(sig000001ca),
.I2(sig000001fe),
.I3(sig000001fd),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000515)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000604 (
.I0(sig000001c8),
.I1(sig000001c9),
.I2(sig000001fd),
.I3(sig000001fc),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000514)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000605 (
.I0(sig000001c7),
.I1(sig000001c8),
.I2(sig000001fc),
.I3(sig000001fb),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000513)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000606 (
.I0(sig000001f5),
.I1(sig000001f6),
.I2(sig0000022a),
.I3(sig00000229),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000541)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000607 (
.I0(sig000001dd),
.I1(sig000001de),
.I2(sig00000212),
.I3(sig00000211),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000529)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000608 (
.I0(sig000001f4),
.I1(sig000001f5),
.I2(sig00000229),
.I3(sig00000228),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000540)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000609 (
.I0(sig000001f3),
.I1(sig000001f4),
.I2(sig00000228),
.I3(sig00000227),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053f)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060a (
.I0(sig000001f2),
.I1(sig000001f3),
.I2(sig00000227),
.I3(sig00000226),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053e)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060b (
.I0(sig000001f1),
.I1(sig000001f2),
.I2(sig00000226),
.I3(sig00000225),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053d)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060c (
.I0(sig000001f0),
.I1(sig000001f1),
.I2(sig00000225),
.I3(sig00000224),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053c)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060d (
.I0(sig000001ef),
.I1(sig000001f0),
.I2(sig00000224),
.I3(sig00000223),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053b)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060e (
.I0(sig000001ee),
.I1(sig000001ef),
.I2(sig00000223),
.I3(sig00000222),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig0000053a)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000060f (
.I0(sig000001ed),
.I1(sig000001ee),
.I2(sig00000222),
.I3(sig00000221),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000539)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000610 (
.I0(sig000001dc),
.I1(sig000001dd),
.I2(sig00000211),
.I3(sig00000210),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000528)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000611 (
.I0(sig000001ec),
.I1(sig000001ed),
.I2(sig00000221),
.I3(sig00000220),
.I4(sig0000023f),
.I5(sig0000022e),
.O(sig00000538)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000612 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003de),
.I3(sig000003d6),
.I4(sig000003da),
.I5(sig000003e2),
.O(sig00000452)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000613 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003da),
.I3(sig000003d6),
.O(sig0000044a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000614 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003df),
.I3(sig000003d7),
.I4(sig000003db),
.I5(sig000003e3),
.O(sig00000453)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000615 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003db),
.I3(sig000003d7),
.O(sig0000044b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000616 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e0),
.I3(sig000003d8),
.I4(sig000003dc),
.I5(sig000003e4),
.O(sig00000454)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000617 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dc),
.I3(sig000003d8),
.O(sig0000044c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000618 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e1),
.I3(sig000003d9),
.I4(sig000003dd),
.I5(sig000003e5),
.O(sig00000455)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000619 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dd),
.I3(sig000003d9),
.O(sig0000044d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061a (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e5),
.I3(sig000003dd),
.I4(sig000003e1),
.I5(sig000003e9),
.O(sig00000459)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000061b (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dd),
.I3(sig000003e1),
.I4(sig000003d9),
.O(sig00000451)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061c (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e6),
.I3(sig000003de),
.I4(sig000003e2),
.I5(sig000003ea),
.O(sig0000045a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061d (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e7),
.I3(sig000003df),
.I4(sig000003e3),
.I5(sig000003eb),
.O(sig0000045b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061e (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e8),
.I3(sig000003e0),
.I4(sig000003e4),
.I5(sig000003ec),
.O(sig0000045c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000061f (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e9),
.I3(sig000003e1),
.I4(sig000003e5),
.I5(sig000003ed),
.O(sig0000045d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000620 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ee),
.I3(sig000003e6),
.I4(sig000003ea),
.I5(sig000003f2),
.O(sig00000462)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000621 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ef),
.I3(sig000003e7),
.I4(sig000003eb),
.I5(sig000003f3),
.O(sig00000463)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000622 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e2),
.I3(sig000003da),
.I4(sig000003de),
.I5(sig000003e6),
.O(sig00000456)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000623 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003da),
.I3(sig000003de),
.I4(sig000003d6),
.O(sig0000044e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000624 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f0),
.I3(sig000003e8),
.I4(sig000003ec),
.I5(sig000003f4),
.O(sig00000464)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000625 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f1),
.I3(sig000003e9),
.I4(sig000003ed),
.I5(sig000003f5),
.O(sig00000465)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000626 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ea),
.I3(sig000003e2),
.I4(sig000003e6),
.I5(sig000003ee),
.O(sig0000045e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000627 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f2),
.I3(sig000003ea),
.I4(sig000003ee),
.I5(sig000003f6),
.O(sig00000466)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000628 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f3),
.I3(sig000003eb),
.I4(sig000003ef),
.I5(sig000003f7),
.O(sig00000467)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000629 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003eb),
.I3(sig000003e3),
.I4(sig000003e7),
.I5(sig000003ef),
.O(sig0000045f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062a (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f4),
.I3(sig000003ec),
.I4(sig000003f0),
.I5(sig000003f8),
.O(sig00000468)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062b (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ec),
.I3(sig000003e4),
.I4(sig000003e8),
.I5(sig000003f0),
.O(sig00000460)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062c (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f5),
.I3(sig000003ed),
.I4(sig000003f1),
.I5(sig000003f9),
.O(sig00000469)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062d (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ed),
.I3(sig000003e5),
.I4(sig000003e9),
.I5(sig000003f1),
.O(sig00000461)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062e (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f6),
.I3(sig000003ee),
.I4(sig000003f2),
.I5(sig000003fa),
.O(sig0000046a)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000062f (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f7),
.I3(sig000003ef),
.I4(sig000003f3),
.I5(sig000003fb),
.O(sig0000046b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000630 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f8),
.I3(sig000003f0),
.I4(sig000003f4),
.I5(sig000003fc),
.O(sig0000046c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000631 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e3),
.I3(sig000003db),
.I4(sig000003df),
.I5(sig000003e7),
.O(sig00000457)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000632 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003db),
.I3(sig000003df),
.I4(sig000003d7),
.O(sig0000044f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000633 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003f9),
.I3(sig000003f1),
.I4(sig000003f5),
.I5(sig000003fd),
.O(sig0000046d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000634 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fa),
.I3(sig000003f2),
.I4(sig000003f6),
.I5(sig000003fe),
.O(sig0000046e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000635 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fb),
.I3(sig000003f3),
.I4(sig000003f7),
.I5(sig000003ff),
.O(sig0000046f)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000636 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fc),
.I3(sig000003f4),
.I4(sig000003f8),
.I5(sig00000400),
.O(sig00000470)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000637 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fd),
.I3(sig000003f5),
.I4(sig000003f9),
.I5(sig00000401),
.O(sig00000471)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000638 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003fe),
.I3(sig000003f6),
.I4(sig000003fa),
.I5(sig00000402),
.O(sig00000472)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000639 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003ff),
.I3(sig000003f7),
.I4(sig000003fb),
.I5(sig00000403),
.O(sig00000473)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063a (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000407),
.I3(sig000003ff),
.I4(sig00000403),
.I5(sig0000040b),
.O(sig0000047b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063b (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000400),
.I3(sig000003f8),
.I4(sig000003fc),
.I5(sig00000404),
.O(sig00000474)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063c (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000401),
.I3(sig000003f9),
.I4(sig000003fd),
.I5(sig00000405),
.O(sig00000475)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063d (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000003e4),
.I3(sig000003dc),
.I4(sig000003e0),
.I5(sig000003e8),
.O(sig00000458)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000063e (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003dc),
.I3(sig000003e0),
.I4(sig000003d8),
.O(sig00000450)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000063f (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000408),
.I3(sig00000400),
.I4(sig00000404),
.I5(sig0000040c),
.O(sig0000047c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000640 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000402),
.I3(sig000003fa),
.I4(sig000003fe),
.I5(sig00000406),
.O(sig00000476)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000641 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000403),
.I3(sig000003fb),
.I4(sig000003ff),
.I5(sig00000407),
.O(sig00000477)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000642 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000404),
.I3(sig000003fc),
.I4(sig00000400),
.I5(sig00000408),
.O(sig00000478)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000643 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000405),
.I3(sig000003fd),
.I4(sig00000401),
.I5(sig00000409),
.O(sig00000479)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000644 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig00000406),
.I3(sig000003fe),
.I4(sig00000402),
.I5(sig0000040a),
.O(sig0000047a)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000645 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f0),
.I3(sig000004e0),
.I4(sig00000500),
.O(sig0000043b)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000646 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f1),
.I3(sig000004e1),
.I4(sig00000501),
.O(sig0000043a)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000647 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f2),
.I3(sig000004e2),
.I4(sig00000502),
.O(sig00000439)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000648 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f3),
.I3(sig000004e3),
.I4(sig00000503),
.O(sig00000438)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000649 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f4),
.I3(sig000004e4),
.I4(sig00000504),
.O(sig00000437)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064a (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f5),
.I3(sig000004e5),
.I4(sig00000505),
.O(sig00000436)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064b (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f6),
.I3(sig000004e6),
.I4(sig00000506),
.O(sig00000435)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064c (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f7),
.I3(sig000004e7),
.I4(sig00000507),
.O(sig00000434)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064d (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f8),
.I3(sig000004e8),
.I4(sig00000508),
.O(sig00000433)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064e (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f9),
.I3(sig000004e9),
.I4(sig00000509),
.O(sig00000432)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000064f (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fa),
.I3(sig000004ea),
.I4(sig0000050a),
.O(sig00000431)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000650 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fb),
.I3(sig000004eb),
.I4(sig0000050b),
.O(sig00000430)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk00000651 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fc),
.I3(sig000004ec),
.I4(sig0000050c),
.O(sig0000042f)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000652 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ed),
.I3(sig000004fd),
.O(sig0000042e)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000653 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ee),
.I3(sig000004fe),
.O(sig0000042d)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000654 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ef),
.I3(sig000004ff),
.O(sig0000042c)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000655 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f0),
.I3(sig00000500),
.O(sig0000042b)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000656 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f1),
.I3(sig00000501),
.O(sig0000042a)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000657 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f2),
.I3(sig00000502),
.O(sig00000429)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000658 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f3),
.I3(sig00000503),
.O(sig00000428)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000659 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f4),
.I3(sig00000504),
.O(sig00000427)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000065a (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004f5),
.I3(sig00000505),
.O(sig00000426)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000065b (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ed),
.I3(sig000004dd),
.I4(sig000004fd),
.O(sig0000043e)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000065c (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ee),
.I3(sig000004de),
.I4(sig000004fe),
.O(sig0000043d)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk0000065d (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ef),
.I3(sig000004df),
.I4(sig000004ff),
.O(sig0000043c)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000065e (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d9),
.O(sig00000449)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000065f (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d8),
.O(sig00000448)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000660 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d7),
.O(sig00000447)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000661 (
.I0(sig0000040d),
.I1(sig0000040e),
.I2(sig000003d6),
.O(sig00000446)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000662 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fd),
.O(sig0000041e)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000663 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004fe),
.O(sig0000041d)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000664 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig000004ff),
.O(sig0000041c)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000665 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000500),
.O(sig0000041b)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000666 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000501),
.O(sig0000041a)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000667 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000502),
.O(sig00000419)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000668 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000503),
.O(sig00000418)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000669 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000504),
.O(sig00000417)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066a (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000505),
.O(sig00000416)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066b (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000506),
.O(sig00000415)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066c (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000507),
.O(sig00000414)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066d (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000508),
.O(sig00000413)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066e (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig00000509),
.O(sig00000412)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000066f (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig0000050a),
.O(sig00000411)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000670 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig0000050b),
.O(sig00000410)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000671 (
.I0(sig000003d4),
.I1(sig000003d5),
.I2(sig0000050c),
.O(sig0000040f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000672 (
.I0(sig00000249),
.I1(sig0000024a),
.O(sig00000583)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000673 (
.I0(sig00000240),
.I1(sig0000024a),
.O(sig0000057a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000674 (
.I0(sig00000241),
.I1(sig0000024a),
.O(sig0000057b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000675 (
.I0(sig00000242),
.I1(sig0000024a),
.O(sig0000057c)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000676 (
.I0(sig00000243),
.I1(sig0000024a),
.O(sig0000057d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000677 (
.I0(sig00000244),
.I1(sig0000024a),
.O(sig0000057e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000678 (
.I0(sig00000245),
.I1(sig0000024a),
.O(sig0000057f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000679 (
.I0(sig00000246),
.I1(sig0000024a),
.O(sig00000580)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000067a (
.I0(sig00000247),
.I1(sig0000024a),
.O(sig00000581)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000067b (
.I0(sig00000248),
.I1(sig0000024a),
.O(sig00000582)
);
LUT2 #(
.INIT ( 4'hE ))
blk0000067c (
.I0(sig000004cd),
.I1(sig00000544),
.O(sig000004bb)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000067d (
.I0(sig0000050b),
.I1(sig0000050a),
.I2(sig000004cf),
.O(sig00000587)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000067e (
.I0(sig00000507),
.I1(sig00000506),
.I2(sig000004cf),
.O(sig00000588)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000067f (
.I0(sig000004ff),
.I1(sig000004fe),
.I2(sig000004cf),
.O(sig0000058a)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000680 (
.I0(sig000004fb),
.I1(sig000004fa),
.I2(sig000004cf),
.O(sig0000058b)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000681 (
.I0(sig00000503),
.I1(sig00000502),
.I2(sig000004cf),
.O(sig00000589)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000682 (
.I0(sig000004f3),
.I1(sig000004f2),
.I2(sig000004cf),
.O(sig0000058d)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000683 (
.I0(sig000004ef),
.I1(sig000004ee),
.I2(sig000004cf),
.O(sig0000058e)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000684 (
.I0(sig000004f7),
.I1(sig000004f6),
.I2(sig000004cf),
.O(sig0000058c)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000685 (
.I0(sig000004e7),
.I1(sig000004e6),
.I2(sig000004cf),
.O(sig00000590)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000686 (
.I0(sig000004e3),
.I1(sig000004e2),
.I2(sig000004cf),
.O(sig00000591)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000687 (
.I0(sig000004eb),
.I1(sig000004ea),
.I2(sig000004cf),
.O(sig0000058f)
);
LUT3 #(
.INIT ( 8'h1F ))
blk00000688 (
.I0(sig000004db),
.I1(sig000004da),
.I2(sig000004cf),
.O(sig00000593)
);
LUT2 #(
.INIT ( 4'h7 ))
blk00000689 (
.I0(sig000004cf),
.I1(sig000004d7),
.O(sig00000594)
);
LUT3 #(
.INIT ( 8'h1F ))
blk0000068a (
.I0(sig000004df),
.I1(sig000004de),
.I2(sig000004cf),
.O(sig00000592)
);
LUT3 #(
.INIT ( 8'h01 ))
blk0000068b (
.I0(sig0000050a),
.I1(sig0000050b),
.I2(sig0000050c),
.O(sig000005b7)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068c (
.I0(sig00000506),
.I1(sig00000507),
.I2(sig00000508),
.I3(sig00000509),
.O(sig000005b8)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068d (
.I0(sig00000502),
.I1(sig00000503),
.I2(sig00000504),
.I3(sig00000505),
.O(sig000005b9)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068e (
.I0(sig000004fe),
.I1(sig000004ff),
.I2(sig00000500),
.I3(sig00000501),
.O(sig000005ba)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000068f (
.I0(sig000004fa),
.I1(sig000004fb),
.I2(sig000004fc),
.I3(sig000004fd),
.O(sig000005bb)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000690 (
.I0(sig000004f6),
.I1(sig000004f7),
.I2(sig000004f8),
.I3(sig000004f9),
.O(sig000005bc)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000691 (
.I0(sig000004f2),
.I1(sig000004f3),
.I2(sig000004f4),
.I3(sig000004f5),
.O(sig000005bd)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000692 (
.I0(sig000004ee),
.I1(sig000004ef),
.I2(sig000004f0),
.I3(sig000004f1),
.O(sig000005be)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000693 (
.I0(sig000004ea),
.I1(sig000004eb),
.I2(sig000004ec),
.I3(sig000004ed),
.O(sig000005bf)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000694 (
.I0(sig000004e6),
.I1(sig000004e7),
.I2(sig000004e8),
.I3(sig000004e9),
.O(sig000005c0)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000695 (
.I0(sig000004e2),
.I1(sig000004e3),
.I2(sig000004e4),
.I3(sig000004e5),
.O(sig000005c1)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000696 (
.I0(sig000004de),
.I1(sig000004df),
.I2(sig000004e0),
.I3(sig000004e1),
.O(sig000005c2)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000697 (
.I0(sig000004da),
.I1(sig000004db),
.I2(sig000004dc),
.I3(sig000004dd),
.O(sig000005c3)
);
LUT3 #(
.INIT ( 8'h01 ))
blk00000698 (
.I0(sig000004d7),
.I1(sig000004d8),
.I2(sig000004d9),
.O(sig000005c4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000699 (
.I0(sig00000696),
.I1(sig00000697),
.O(sig000005dc)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk0000069a (
.I0(sig000005f9),
.I1(sig00000601),
.I2(sig000005fb),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d4)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk0000069b (
.I0(sig000005fa),
.I1(sig00000602),
.I2(sig000005fc),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d5)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069c (
.I0(sig00000603),
.I1(sig000005fb),
.I2(sig000005fd),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d6)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069d (
.I0(sig00000604),
.I1(sig000005fc),
.I2(sig000005fe),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d7)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069e (
.I0(sig00000605),
.I1(sig000005fd),
.I2(sig000005ff),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d8)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk0000069f (
.I0(sig00000606),
.I1(sig000005fe),
.I2(sig00000600),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig000005d9)
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk000006a0 (
.I0(sig00000607),
.I1(sig000005ff),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig000005da)
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk000006a1 (
.I0(sig00000608),
.I1(sig00000600),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig000005db)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a2 (
.I0(sig00000666),
.I1(sig000005e6),
.I2(sig000005ef),
.O(sig000005dd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a3 (
.I0(sig00000666),
.I1(sig000005e7),
.I2(sig000005f0),
.O(sig000005de)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a4 (
.I0(sig00000666),
.I1(sig000005e8),
.I2(sig000005f1),
.O(sig000005df)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a5 (
.I0(sig00000666),
.I1(sig000005e9),
.I2(sig000005f2),
.O(sig000005e0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a6 (
.I0(sig00000666),
.I1(sig000005ea),
.I2(sig000005f3),
.O(sig000005e1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a7 (
.I0(sig00000666),
.I1(sig000005eb),
.I2(sig000005f4),
.O(sig000005e2)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a8 (
.I0(sig00000666),
.I1(sig000005ec),
.I2(sig000005f5),
.O(sig000005e3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006a9 (
.I0(sig00000666),
.I1(sig000005ed),
.I2(sig000005f6),
.O(sig000005e4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006aa (
.I0(sig00000666),
.I1(sig000005ee),
.I2(sig000005f7),
.O(sig000005e5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ab (
.I0(sig000006e4),
.I1(sig000006e9),
.I2(sig000006eb),
.O(sig000006c4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ac (
.I0(sig000006e4),
.I1(sig000006ea),
.I2(sig000006ec),
.O(sig000006c5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ad (
.I0(sig000006e3),
.I1(sig000006e5),
.I2(sig000006e7),
.O(sig000006c6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006ae (
.I0(sig000006e3),
.I1(sig000006e6),
.I2(sig000006e8),
.O(sig000006c7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006af (
.I0(sig000006f9),
.I1(sig000006f3),
.I2(sig000006f6),
.O(sig000006ca)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b0 (
.I0(sig000006f9),
.I1(sig000006f4),
.I2(sig000006f7),
.O(sig000006cb)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b1 (
.I0(sig000006f9),
.I1(sig000006f5),
.I2(sig000006f8),
.O(sig000006cc)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006b2 (
.I0(sig000006f9),
.I1(sig00000118),
.O(sig000006cd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b3 (
.I0(sig000006f1),
.I1(sig000006ed),
.I2(sig000006ee),
.O(sig000006ce)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b4 (
.I0(sig000006f1),
.I1(sig000006f2),
.I2(sig000006ef),
.O(sig000006cf)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006b5 (
.I0(sig000006f0),
.I1(sig000006f1),
.O(sig000006d0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000006b6 (
.I0(sig00000118),
.I1(sig000006f1),
.I2(sig000006f9),
.O(sig00000119)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000006b7 (
.I0(sig000006e3),
.I1(sig000006e4),
.I2(sig0000011a),
.O(sig0000011b)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006b8 (
.I0(sig0000011a),
.I1(sig000006e4),
.O(sig000006c2)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006b9 (
.I0(sig00000118),
.I1(sig000006f2),
.O(sig000006d4)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006ba (
.I0(sig000001c2),
.I1(sig000001c1),
.I2(sig000001c0),
.I3(sig000001bf),
.O(sig000006d5)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bb (
.I0(sig000001be),
.I1(sig000001bd),
.I2(sig000001bc),
.I3(sig000001bb),
.O(sig000006d6)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bc (
.I0(sig000001b8),
.I1(sig000001b7),
.I2(sig000001ba),
.I3(sig000001b9),
.O(sig000006d7)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bd (
.I0(sig000001b6),
.I1(sig000001b5),
.I2(sig000001b4),
.I3(sig000001b3),
.O(sig000006d8)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006be (
.I0(sig000001b2),
.I1(sig000001b1),
.I2(sig000001b0),
.I3(sig000001af),
.O(sig000006d9)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006bf (
.I0(sig000001ae),
.I1(sig000001ad),
.I2(sig000001ac),
.I3(sig000001ab),
.O(sig000006da)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c0 (
.I0(sig000001aa),
.I1(sig000001a9),
.I2(sig000001a8),
.I3(sig000001a7),
.O(sig000006db)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c1 (
.I0(sig000001a6),
.I1(sig000001a5),
.I2(sig000001a4),
.I3(sig000001a3),
.O(sig000006dc)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c2 (
.I0(sig000001a2),
.I1(sig000001a1),
.I2(sig000001a0),
.I3(sig0000019f),
.O(sig000006dd)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c3 (
.I0(sig0000019e),
.I1(sig0000019d),
.I2(sig0000019c),
.I3(sig0000019b),
.O(sig000006de)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c4 (
.I0(sig0000019a),
.I1(sig00000199),
.I2(sig00000198),
.I3(sig00000197),
.O(sig000006df)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c5 (
.I0(sig00000196),
.I1(sig00000195),
.I2(sig00000194),
.I3(sig00000193),
.O(sig000006e0)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c6 (
.I0(sig00000192),
.I1(sig00000191),
.I2(sig00000190),
.I3(sig0000018f),
.O(sig000006e1)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000006c7 (
.I0(sig0000018e),
.I1(sig0000018d),
.I2(sig0000018c),
.I3(sig0000018b),
.O(sig000006e2)
);
LUT5 #(
.INIT ( 32'h11110010 ))
blk000006c8 (
.I0(sig000006f1),
.I1(sig00000145),
.I2(sig00000148),
.I3(sig00000147),
.I4(sig00000146),
.O(sig00000713)
);
LUT5 #(
.INIT ( 32'h01010100 ))
blk000006c9 (
.I0(sig000006f1),
.I1(sig00000146),
.I2(sig00000145),
.I3(sig00000148),
.I4(sig00000147),
.O(sig00000712)
);
LUT5 #(
.INIT ( 32'h11110010 ))
blk000006ca (
.I0(sig000006f1),
.I1(sig00000149),
.I2(sig0000014c),
.I3(sig0000014b),
.I4(sig0000014a),
.O(sig00000711)
);
LUT5 #(
.INIT ( 32'h01010100 ))
blk000006cb (
.I0(sig000006f1),
.I1(sig0000014a),
.I2(sig00000149),
.I3(sig0000014c),
.I4(sig0000014b),
.O(sig00000710)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006cc (
.I0(sig00000158),
.I1(sig0000023e),
.O(sig000007b4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006cd (
.I0(sig00000159),
.I1(sig0000023e),
.O(sig000007b5)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ce (
.I0(sig0000015b),
.I1(sig0000023e),
.O(sig000007b7)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006cf (
.I0(sig0000015c),
.I1(sig0000023e),
.O(sig000007b8)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d0 (
.I0(sig0000015a),
.I1(sig0000023e),
.O(sig000007b6)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d1 (
.I0(sig0000015e),
.I1(sig0000023e),
.O(sig000007ba)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d2 (
.I0(sig0000015f),
.I1(sig0000023e),
.O(sig000007bb)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d3 (
.I0(sig0000015d),
.I1(sig0000023e),
.O(sig000007b9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d4 (
.I0(sig00000160),
.I1(sig0000023e),
.O(sig000007bc)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d5 (
.I0(sig00000161),
.I1(sig0000023e),
.O(sig000007bd)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d6 (
.I0(sig00000162),
.I1(sig0000023e),
.O(sig000007be)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d7 (
.I0(sig00000163),
.I1(sig0000023e),
.O(sig000007bf)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d8 (
.I0(sig00000165),
.I1(sig0000023e),
.O(sig000007c1)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006d9 (
.I0(sig00000166),
.I1(sig0000023e),
.O(sig000007c2)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006da (
.I0(sig00000164),
.I1(sig0000023e),
.O(sig000007c0)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006db (
.I0(sig00000167),
.I1(sig0000023e),
.O(sig000007c3)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006dc (
.I0(sig00000168),
.I1(sig0000023e),
.O(sig000007c4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006dd (
.I0(sig00000169),
.I1(sig0000023e),
.O(sig000007c5)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006de (
.I0(sig0000016a),
.I1(sig0000023e),
.O(sig000007c6)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006df (
.I0(sig0000016c),
.I1(sig0000023e),
.O(sig000007c8)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e0 (
.I0(sig0000016d),
.I1(sig0000023e),
.O(sig000007c9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e1 (
.I0(sig0000016b),
.I1(sig0000023e),
.O(sig000007c7)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e2 (
.I0(sig0000016e),
.I1(sig0000023e),
.O(sig000007ca)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e3 (
.I0(sig0000016f),
.I1(sig0000023e),
.O(sig000007cb)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e4 (
.I0(sig00000170),
.I1(sig0000023e),
.O(sig000007cc)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e5 (
.I0(sig00000171),
.I1(sig0000023e),
.O(sig000007cd)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e6 (
.I0(sig00000173),
.I1(sig0000023e),
.O(sig000007cf)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e7 (
.I0(sig00000174),
.I1(sig0000023e),
.O(sig000007d0)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e8 (
.I0(sig00000172),
.I1(sig0000023e),
.O(sig000007ce)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006e9 (
.I0(sig00000176),
.I1(sig0000023e),
.O(sig000007d2)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ea (
.I0(sig00000177),
.I1(sig0000023e),
.O(sig000007d3)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006eb (
.I0(sig00000175),
.I1(sig0000023e),
.O(sig000007d1)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ec (
.I0(sig00000179),
.I1(sig0000023e),
.O(sig000007d5)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ed (
.I0(sig0000017a),
.I1(sig0000023e),
.O(sig000007d6)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ee (
.I0(sig00000178),
.I1(sig0000023e),
.O(sig000007d4)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006ef (
.I0(sig0000017b),
.I1(sig0000023e),
.O(sig000007d7)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f0 (
.I0(sig0000017c),
.I1(sig0000023e),
.O(sig000007d8)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f1 (
.I0(sig0000017d),
.I1(sig0000023e),
.O(sig000007d9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f2 (
.I0(sig0000017e),
.I1(sig0000023e),
.O(sig000007da)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f3 (
.I0(sig00000180),
.I1(sig0000023e),
.O(sig000007dc)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f4 (
.I0(sig00000181),
.I1(sig0000023e),
.O(sig000007dd)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f5 (
.I0(sig0000017f),
.I1(sig0000023e),
.O(sig000007db)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f6 (
.I0(sig00000182),
.I1(sig0000023e),
.O(sig000007de)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f7 (
.I0(sig00000183),
.I1(sig0000023e),
.O(sig000007df)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f8 (
.I0(sig00000184),
.I1(sig0000023e),
.O(sig000007e0)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000006f9 (
.I0(sig00000185),
.I1(sig0000023e),
.O(sig000007e1)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fa (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075b),
.I3(sig00000754),
.O(sig000007e3)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fb (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075c),
.I3(sig00000755),
.O(sig000007e4)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fc (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075a),
.I3(sig00000753),
.O(sig000007e2)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fd (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075d),
.I3(sig00000756),
.O(sig000007e5)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk000006fe (
.I0(sig0000023e),
.I1(sig00000767),
.I2(sig0000075e),
.I3(sig00000757),
.O(sig000007e6)
);
LUT5 #(
.INIT ( 32'h55555410 ))
blk000006ff (
.I0(sig0000023d),
.I1(sig00000767),
.I2(sig0000075f),
.I3(sig00000758),
.I4(sig0000023c),
.O(sig000007e7)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000700 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig0000022f),
.O(sig000007e8)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000701 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000239),
.O(sig000007f2)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000702 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000230),
.O(sig000007e9)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000703 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000231),
.O(sig000007ea)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000704 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000232),
.O(sig000007eb)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000705 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000233),
.O(sig000007ec)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000706 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000234),
.O(sig000007ed)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000707 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000235),
.O(sig000007ee)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000708 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000236),
.O(sig000007ef)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000709 (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000237),
.O(sig000007f0)
);
LUT3 #(
.INIT ( 8'h54 ))
blk0000070a (
.I0(sig0000023b),
.I1(sig0000023a),
.I2(sig00000238),
.O(sig000007f1)
);
LUT6 #(
.INIT ( 64'h0001000000000001 ))
blk0000070b (
.I0(sig000002d0),
.I1(sig000002cf),
.I2(sig000002ce),
.I3(sig000002d1),
.I4(sig000002cc),
.I5(sig00000189),
.O(sig000007f3)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000070c (
.I0(sig00000188),
.I1(sig000002cb),
.I2(sig000002c7),
.I3(sig0000011d),
.O(sig000007f4)
);
LUT5 #(
.INIT ( 32'h00009009 ))
blk0000070d (
.I0(sig000002c9),
.I1(sig00000186),
.I2(sig000002c8),
.I3(sig0000011c),
.I4(sig000002cd),
.O(sig000007f5)
);
LUT5 #(
.INIT ( 32'h90000000 ))
blk0000070e (
.I0(sig00000187),
.I1(sig000002ca),
.I2(sig000007f4),
.I3(sig000007f5),
.I4(sig000007f3),
.O(sig0000030e)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000070f (
.I0(sig000002ef),
.I1(sig000002ee),
.I2(sig000002ed),
.O(sig000007f6)
);
LUT5 #(
.INIT ( 32'hAA0BAA08 ))
blk00000710 (
.I0(sig000002f0),
.I1(sig000002f1),
.I2(sig000002f2),
.I3(sig000002f3),
.I4(sig000007f6),
.O(sig000002a3)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000711 (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig000007f7)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000712 (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig000007f7),
.O(sig00000280)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000713 (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig000007f8)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000714 (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig000007f8),
.O(sig00000281)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000715 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig000007f9)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000716 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig000007f9),
.O(sig00000282)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000717 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig000007fa)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000718 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig000007fa),
.O(sig00000283)
);
LUT5 #(
.INIT ( 32'h40000000 ))
blk00000719 (
.I0(sig000002dd),
.I1(sig000002d2),
.I2(sig000002d5),
.I3(sig000002d4),
.I4(sig000002d3),
.O(sig000007fb)
);
LUT5 #(
.INIT ( 32'h80000000 ))
blk0000071a (
.I0(sig000002d9),
.I1(sig000002d8),
.I2(sig000002dc),
.I3(sig000002db),
.I4(sig000002da),
.O(sig000007fc)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk0000071b (
.I0(sig000002d7),
.I1(sig000002d6),
.I2(sig000007fc),
.I3(sig000007fb),
.O(sig0000028f)
);
LUT6 #(
.INIT ( 64'hECCC000000000000 ))
blk0000071c (
.I0(sig000004ce),
.I1(sig000004d1),
.I2(sig000004d0),
.I3(sig000004cf),
.I4(sig000003d4),
.I5(sig000003d5),
.O(sig000007fd)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk0000071d (
.I0(sig000004d4),
.I1(sig000004d5),
.I2(sig000004d6),
.I3(sig000004d2),
.I4(sig000004d3),
.I5(sig000007fd),
.O(sig000004b9)
);
LUT5 #(
.INIT ( 32'h0FFF7777 ))
blk0000071e (
.I0(sig0000059b),
.I1(sig000005aa),
.I2(sig000005ab),
.I3(sig0000059d),
.I4(sig0000040e),
.O(sig000007fe)
);
LUT5 #(
.INIT ( 32'h8880BBB3 ))
blk0000071f (
.I0(sig0000059c),
.I1(sig0000040d),
.I2(sig0000040e),
.I3(sig000005c5),
.I4(sig000007fe),
.O(sig00000597)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000720 (
.I0(sig000005b4),
.I1(sig000005a7),
.I2(sig000005b6),
.I3(sig000005a9),
.I4(sig0000040d),
.O(sig000007ff)
);
LUT6 #(
.INIT ( 64'hFBBBEAAA51114000 ))
blk00000721 (
.I0(sig0000040e),
.I1(sig0000040d),
.I2(sig000005a8),
.I3(sig000005b5),
.I4(sig000005a6),
.I5(sig000007ff),
.O(sig0000059a)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000722 (
.I0(sig000005ad),
.I1(sig0000059f),
.I2(sig000005af),
.I3(sig000005a1),
.I4(sig0000040d),
.O(sig00000800)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000723 (
.I0(sig000005ae),
.I1(sig000005a0),
.I2(sig000005ac),
.I3(sig0000059e),
.I4(sig0000040d),
.O(sig00000801)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000724 (
.I0(sig0000040e),
.I1(sig00000800),
.I2(sig00000801),
.O(sig00000598)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000725 (
.I0(sig000005b1),
.I1(sig000005a3),
.I2(sig000005b3),
.I3(sig000005a5),
.I4(sig0000040d),
.O(sig00000802)
);
LUT5 #(
.INIT ( 32'h8888F000 ))
blk00000726 (
.I0(sig000005b2),
.I1(sig000005a4),
.I2(sig000005b0),
.I3(sig000005a2),
.I4(sig0000040d),
.O(sig00000803)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000727 (
.I0(sig0000040e),
.I1(sig00000802),
.I2(sig00000803),
.O(sig00000599)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000728 (
.I0(sig0000013e),
.I1(sig0000013f),
.I2(sig00000140),
.I3(sig0000013d),
.O(sig00000804)
);
LUT6 #(
.INIT ( 64'h2222020077775755 ))
blk00000729 (
.I0(sig000006f1),
.I1(sig0000014d),
.I2(sig0000014f),
.I3(sig00000150),
.I4(sig0000014e),
.I5(sig00000804),
.O(sig00000717)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000072a (
.I0(sig0000013e),
.I1(sig0000013f),
.I2(sig00000140),
.I3(sig0000013d),
.O(sig00000805)
);
LUT6 #(
.INIT ( 64'h0404040037373733 ))
blk0000072b (
.I0(sig0000014d),
.I1(sig000006f1),
.I2(sig0000014e),
.I3(sig00000150),
.I4(sig0000014f),
.I5(sig00000805),
.O(sig00000716)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk0000072c (
.I0(sig00000142),
.I1(sig00000143),
.I2(sig00000144),
.I3(sig00000141),
.O(sig00000806)
);
LUT6 #(
.INIT ( 64'h2222020077775755 ))
blk0000072d (
.I0(sig000006f1),
.I1(sig00000151),
.I2(sig00000153),
.I3(sig00000154),
.I4(sig00000152),
.I5(sig00000806),
.O(sig00000715)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000072e (
.I0(sig00000142),
.I1(sig00000143),
.I2(sig00000144),
.I3(sig00000141),
.O(sig00000807)
);
LUT6 #(
.INIT ( 64'h0404040037373733 ))
blk0000072f (
.I0(sig00000151),
.I1(sig000006f1),
.I2(sig00000152),
.I3(sig00000154),
.I4(sig00000153),
.I5(sig00000807),
.O(sig00000714)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000730 (
.I0(sig0000012e),
.I1(sig0000012f),
.I2(sig00000130),
.I3(sig0000012d),
.O(sig00000808)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk00000731 (
.I0(sig000006f9),
.I1(sig0000027f),
.I2(sig0000011e),
.I3(sig0000011f),
.I4(sig00000120),
.I5(sig00000808),
.O(sig0000071f)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk00000732 (
.I0(sig0000012d),
.I1(sig0000012f),
.I2(sig00000130),
.I3(sig0000012e),
.O(sig00000809)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk00000733 (
.I0(sig0000027f),
.I1(sig000006f9),
.I2(sig0000011e),
.I3(sig00000120),
.I4(sig0000011f),
.I5(sig00000809),
.O(sig0000071e)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000734 (
.I0(sig00000132),
.I1(sig00000133),
.I2(sig00000134),
.I3(sig00000131),
.O(sig0000080a)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk00000735 (
.I0(sig000006f9),
.I1(sig00000121),
.I2(sig00000122),
.I3(sig00000123),
.I4(sig00000124),
.I5(sig0000080a),
.O(sig0000071d)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk00000736 (
.I0(sig00000131),
.I1(sig00000133),
.I2(sig00000134),
.I3(sig00000132),
.O(sig0000080b)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk00000737 (
.I0(sig00000122),
.I1(sig000006f9),
.I2(sig00000121),
.I3(sig00000124),
.I4(sig00000123),
.I5(sig0000080b),
.O(sig0000071c)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk00000738 (
.I0(sig00000136),
.I1(sig00000137),
.I2(sig00000138),
.I3(sig00000135),
.O(sig0000080c)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk00000739 (
.I0(sig000006f9),
.I1(sig00000125),
.I2(sig00000126),
.I3(sig00000127),
.I4(sig00000128),
.I5(sig0000080c),
.O(sig0000071b)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000073a (
.I0(sig00000135),
.I1(sig00000137),
.I2(sig00000138),
.I3(sig00000136),
.O(sig0000080d)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk0000073b (
.I0(sig00000126),
.I1(sig000006f9),
.I2(sig00000125),
.I3(sig00000128),
.I4(sig00000127),
.I5(sig0000080d),
.O(sig0000071a)
);
LUT4 #(
.INIT ( 16'hFF45 ))
blk0000073c (
.I0(sig0000013a),
.I1(sig0000013b),
.I2(sig0000013c),
.I3(sig00000139),
.O(sig0000080e)
);
LUT6 #(
.INIT ( 64'h10111010BABBBABA ))
blk0000073d (
.I0(sig000006f9),
.I1(sig00000129),
.I2(sig0000012a),
.I3(sig0000012b),
.I4(sig0000012c),
.I5(sig0000080e),
.O(sig00000719)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000073e (
.I0(sig00000139),
.I1(sig0000013b),
.I2(sig0000013c),
.I3(sig0000013a),
.O(sig0000080f)
);
LUT6 #(
.INIT ( 64'h01010100CDCDCDCC ))
blk0000073f (
.I0(sig0000012a),
.I1(sig000006f9),
.I2(sig00000129),
.I3(sig0000012c),
.I4(sig0000012b),
.I5(sig0000080f),
.O(sig00000718)
);
LUT2 #(
.INIT ( 4'hD ))
blk00000740 (
.I0(sig0000003b),
.I1(sig0000011d),
.O(sig00000810)
);
LUT6 #(
.INIT ( 64'hFFFF00005D5F0000 ))
blk00000741 (
.I0(sig00000155),
.I1(sig0000003a),
.I2(sig0000011c),
.I3(sig00000810),
.I4(sig000000e2),
.I5(sig000000e3),
.O(sig00000720)
);
FD blk00000742 (
.C(clk),
.D(sig0000022b),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op )
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk00000743 (
.I0(sig00000608),
.I1(sig00000600),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig00000811)
);
LUT5 #(
.INIT ( 32'hAAAA59A6 ))
blk00000744 (
.I0(sig00000607),
.I1(sig000005ff),
.I2(sig000005f8),
.I3(sig00000696),
.I4(sig00000697),
.O(sig00000812)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000745 (
.I0(sig00000606),
.I1(sig000005fe),
.I2(sig00000600),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000813)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000746 (
.I0(sig00000605),
.I1(sig000005fd),
.I2(sig000005ff),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000814)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000747 (
.I0(sig00000604),
.I1(sig000005fc),
.I2(sig000005fe),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000815)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAA5995A66 ))
blk00000748 (
.I0(sig00000603),
.I1(sig000005fb),
.I2(sig000005fd),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000816)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk00000749 (
.I0(sig000005fa),
.I1(sig00000602),
.I2(sig000005fc),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000817)
);
LUT6 #(
.INIT ( 64'hCCCCCCCCC3993C66 ))
blk0000074a (
.I0(sig000005f9),
.I1(sig00000601),
.I2(sig000005fb),
.I3(sig000005f8),
.I4(sig00000696),
.I5(sig00000697),
.O(sig00000818)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074b (
.I0(sig00000761),
.O(sig00000819)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074c (
.I0(sig00000762),
.O(sig0000081a)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074d (
.I0(sig00000763),
.O(sig0000081b)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074e (
.I0(sig00000764),
.O(sig0000081c)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000074f (
.I0(sig00000765),
.O(sig0000081d)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000750 (
.I0(sig00000766),
.O(sig0000081e)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000751 (
.I0(sig00000760),
.O(sig0000081f)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000752 (
.I0(sig00000761),
.O(sig00000820)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000753 (
.I0(sig00000762),
.O(sig00000821)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000754 (
.I0(sig00000763),
.O(sig00000822)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000755 (
.I0(sig00000764),
.O(sig00000823)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000756 (
.I0(sig00000765),
.O(sig00000824)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000757 (
.I0(sig00000766),
.O(sig00000825)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000758 (
.I0(sig00000760),
.O(sig00000826)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000759 (
.I0(sig00000696),
.I1(sig00000697),
.O(sig00000827)
);
LUT6 #(
.INIT ( 64'h0000FFA50000FFC3 ))
blk0000075a (
.I0(sig00000759),
.I1(sig0000059c),
.I2(sig0000022f),
.I3(sig0000023a),
.I4(sig0000023b),
.I5(sig00000767),
.O(sig000007a8)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000144),
.I3(sig00000154),
.O(sig00000082)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000143),
.I3(sig00000153),
.O(sig00000083)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013d),
.I3(sig0000014d),
.O(sig00000089)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000142),
.I3(sig00000152),
.O(sig00000084)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000075f (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000141),
.I3(sig00000151),
.O(sig00000085)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000760 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000140),
.I3(sig00000150),
.O(sig00000086)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000761 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013f),
.I3(sig0000014f),
.O(sig00000087)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000762 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013e),
.I3(sig0000014e),
.O(sig00000088)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000763 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000006),
.I3(sig00000002),
.O(sig000000ae)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000764 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000007),
.I3(sig00000003),
.O(sig000000af)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000765 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000008),
.I3(sig00000004),
.O(sig000000b0)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000766 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000009),
.I3(sig00000005),
.O(sig000000b1)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000767 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000135),
.I3(sig00000145),
.O(sig00000091)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000768 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000136),
.I3(sig00000146),
.O(sig00000090)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk00000769 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000137),
.I3(sig00000147),
.O(sig0000008f)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076a (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000138),
.I3(sig00000148),
.O(sig0000008e)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000139),
.I3(sig00000149),
.O(sig0000008d)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013a),
.I3(sig0000014a),
.O(sig0000008c)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013b),
.I3(sig0000014b),
.O(sig0000008b)
);
LUT4 #(
.INIT ( 16'h5410 ))
blk0000076e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000013c),
.I3(sig0000014c),
.O(sig0000008a)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000076f (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000005),
.O(sig000000ad)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000770 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000004),
.O(sig000000ac)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000771 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000003),
.O(sig000000ab)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000772 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig00000002),
.O(sig000000aa)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000773 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000145),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000774 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000146),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000775 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000147),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000776 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000148),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000777 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000149),
.O(sig0000007d)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000778 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014a),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000779 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014b),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077a (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014c),
.O(sig0000007a)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014d),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014e),
.O(sig00000078)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000014f),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000150),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000077f (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000151),
.O(sig00000075)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000780 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000152),
.O(sig00000074)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000781 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000153),
.O(sig00000073)
);
LUT3 #(
.INIT ( 8'h10 ))
blk00000782 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000154),
.O(sig00000072)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000783 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig000006e3),
.I5(sig00000002),
.O(sig000000b2)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000784 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000b),
.I3(sig00000007),
.I4(sig000006e3),
.I5(sig00000003),
.O(sig000000b3)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000785 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000c),
.I3(sig00000008),
.I4(sig000006e3),
.I5(sig00000004),
.O(sig000000b4)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000786 (
.I0(sig0000011a),
.I1(sig000006e4),
.I2(sig0000000d),
.I3(sig00000009),
.I4(sig000006e3),
.I5(sig00000005),
.O(sig000000b5)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000787 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000127),
.I3(sig00000137),
.I4(sig000006f1),
.I5(sig00000147),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000788 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000128),
.I3(sig00000138),
.I4(sig000006f1),
.I5(sig00000148),
.O(sig0000009e)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000789 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000129),
.I3(sig00000139),
.I4(sig000006f1),
.I5(sig00000149),
.O(sig0000009d)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078a (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012a),
.I3(sig0000013a),
.I4(sig000006f1),
.I5(sig0000014a),
.O(sig0000009c)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078b (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012b),
.I3(sig0000013b),
.I4(sig000006f1),
.I5(sig0000014b),
.O(sig0000009b)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078c (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012c),
.I3(sig0000013c),
.I4(sig000006f1),
.I5(sig0000014c),
.O(sig0000009a)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078d (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012d),
.I3(sig0000013d),
.I4(sig000006f1),
.I5(sig0000014d),
.O(sig00000099)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078e (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012e),
.I3(sig0000013e),
.I4(sig000006f1),
.I5(sig0000014e),
.O(sig00000098)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000078f (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig0000012f),
.I3(sig0000013f),
.I4(sig000006f1),
.I5(sig0000014f),
.O(sig00000097)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000790 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000130),
.I3(sig00000140),
.I4(sig000006f1),
.I5(sig00000150),
.O(sig00000096)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000791 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000131),
.I3(sig00000141),
.I4(sig000006f1),
.I5(sig00000151),
.O(sig00000095)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000792 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000132),
.I3(sig00000142),
.I4(sig000006f1),
.I5(sig00000152),
.O(sig00000094)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000793 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000133),
.I3(sig00000143),
.I4(sig000006f1),
.I5(sig00000153),
.O(sig00000093)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000794 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000134),
.I3(sig00000144),
.I4(sig000006f1),
.I5(sig00000154),
.O(sig00000092)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000795 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000125),
.I3(sig00000135),
.I4(sig000006f1),
.I5(sig00000145),
.O(sig000000a1)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000796 (
.I0(sig00000118),
.I1(sig000006f9),
.I2(sig00000126),
.I3(sig00000136),
.I4(sig000006f1),
.I5(sig00000146),
.O(sig000000a0)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFEEE0444 ))
blk00000797 (
.I0(sig0000027b),
.I1(sig000001f6),
.I2(sig0000027a),
.I3(sig0000027c),
.I4(sig0000022a),
.I5(sig0000023f),
.O(sig00000542)
);
LUT6 #(
.INIT ( 64'hAAA8A8A800202020 ))
blk00000798 (
.I0(sig0000023f),
.I1(sig0000027b),
.I2(sig000001c3),
.I3(sig0000027a),
.I4(sig0000027c),
.I5(sig000001f7),
.O(sig0000050e)
);
LUT2 #(
.INIT ( 4'h7 ))
blk00000799 (
.I0(sig0000030f),
.I1(sig00000312),
.O(sig00000579)
);
LUT3 #(
.INIT ( 8'h01 ))
blk0000079a (
.I0(sig000004cb),
.I1(sig000004cd),
.I2(sig00000544),
.O(sig000004b7)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000079b (
.I0(sig000004cd),
.I1(sig00000544),
.I2(sig000004cb),
.O(sig000004b8)
);
LUT3 #(
.INIT ( 8'h10 ))
blk0000079c (
.I0(sig000004cd),
.I1(sig00000544),
.I2(sig000004b4),
.O(sig000004ba)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk0000079d (
.I0(sig000001c3),
.I1(sig000001f7),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000545)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk0000079e (
.I0(sig000001cd),
.I1(sig00000201),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054f)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk0000079f (
.I0(sig000001ce),
.I1(sig00000202),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000550)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a0 (
.I0(sig000001cf),
.I1(sig00000203),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000551)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a1 (
.I0(sig000001d0),
.I1(sig00000204),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000552)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a2 (
.I0(sig000001d1),
.I1(sig00000205),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000553)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a3 (
.I0(sig000001d2),
.I1(sig00000206),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000554)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a4 (
.I0(sig000001d3),
.I1(sig00000207),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000555)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a5 (
.I0(sig000001d4),
.I1(sig00000208),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000556)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a6 (
.I0(sig000001d5),
.I1(sig00000209),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000557)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a7 (
.I0(sig000001d6),
.I1(sig0000020a),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000558)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a8 (
.I0(sig000001c4),
.I1(sig000001f8),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000546)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007a9 (
.I0(sig000001d7),
.I1(sig0000020b),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000559)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007aa (
.I0(sig000001d8),
.I1(sig0000020c),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055a)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ab (
.I0(sig000001d9),
.I1(sig0000020d),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055b)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ac (
.I0(sig000001da),
.I1(sig0000020e),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055c)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ad (
.I0(sig000001db),
.I1(sig0000020f),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055d)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ae (
.I0(sig000001dc),
.I1(sig00000210),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055e)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007af (
.I0(sig000001dd),
.I1(sig00000211),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000055f)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b0 (
.I0(sig000001de),
.I1(sig00000212),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000560)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b1 (
.I0(sig000001df),
.I1(sig00000213),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000561)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b2 (
.I0(sig000001e0),
.I1(sig00000214),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000562)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b3 (
.I0(sig000001c5),
.I1(sig000001f9),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000547)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b4 (
.I0(sig000001e1),
.I1(sig00000215),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000563)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b5 (
.I0(sig000001e2),
.I1(sig00000216),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000564)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b6 (
.I0(sig000001e3),
.I1(sig00000217),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000565)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b7 (
.I0(sig000001e4),
.I1(sig00000218),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000566)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b8 (
.I0(sig000001e5),
.I1(sig00000219),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000567)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007b9 (
.I0(sig000001e6),
.I1(sig0000021a),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000568)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ba (
.I0(sig000001e7),
.I1(sig0000021b),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000569)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bb (
.I0(sig000001e8),
.I1(sig0000021c),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056a)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bc (
.I0(sig000001e9),
.I1(sig0000021d),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056b)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bd (
.I0(sig000001ea),
.I1(sig0000021e),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056c)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007be (
.I0(sig000001c6),
.I1(sig000001fa),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000548)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007bf (
.I0(sig000001eb),
.I1(sig0000021f),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056d)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c0 (
.I0(sig000001ec),
.I1(sig00000220),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056e)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c1 (
.I0(sig000001ed),
.I1(sig00000221),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000056f)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c2 (
.I0(sig000001ee),
.I1(sig00000222),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000570)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c3 (
.I0(sig000001ef),
.I1(sig00000223),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000571)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c4 (
.I0(sig000001f0),
.I1(sig00000224),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000572)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c5 (
.I0(sig000001f1),
.I1(sig00000225),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000573)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c6 (
.I0(sig000001f2),
.I1(sig00000226),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000574)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c7 (
.I0(sig000001f3),
.I1(sig00000227),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000575)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c8 (
.I0(sig000001f4),
.I1(sig00000228),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000576)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007c9 (
.I0(sig000001c7),
.I1(sig000001fb),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000549)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ca (
.I0(sig000001f5),
.I1(sig00000229),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000577)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cb (
.I0(sig000001f6),
.I1(sig0000022a),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig00000578)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cc (
.I0(sig000001c8),
.I1(sig000001fc),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054a)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cd (
.I0(sig000001c9),
.I1(sig000001fd),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054b)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007ce (
.I0(sig000001ca),
.I1(sig000001fe),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054c)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007cf (
.I0(sig000001cb),
.I1(sig000001ff),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054d)
);
LUT5 #(
.INIT ( 32'h0AAA0CCC ))
blk000007d0 (
.I0(sig000001cc),
.I1(sig00000200),
.I2(sig00000312),
.I3(sig0000030f),
.I4(sig0000022e),
.O(sig0000054e)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007d1 (
.I0(sig0000023f),
.O(sig00000828)
);
INV blk000007d2 (
.I(sig0000023f),
.O(sig00000543)
);
INV blk000007d3 (
.I(sig000002d1),
.O(sig0000024c)
);
INV blk000007d4 (
.I(sig000002cd),
.O(sig00000254)
);
INV blk000007d5 (
.I(sig000002ce),
.O(sig00000252)
);
INV blk000007d6 (
.I(sig000002cf),
.O(sig00000250)
);
INV blk000007d7 (
.I(sig000002d0),
.O(sig0000024e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007d8 (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000027f),
.Q(sig00000829),
.Q15(NLW_blk000007d8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d9 (
.C(clk),
.CE(sig00000001),
.D(sig00000829),
.Q(sig0000030d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007da (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003b0),
.Q(sig0000082a),
.Q15(NLW_blk000007da_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007db (
.C(clk),
.CE(sig00000001),
.D(sig0000082a),
.Q(sig000002ec)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007dc (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003af),
.Q(sig0000082b),
.Q15(NLW_blk000007dc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007dd (
.C(clk),
.CE(sig00000001),
.D(sig0000082b),
.Q(sig000002eb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007de (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003b1),
.Q(sig0000082c),
.Q15(NLW_blk000007de_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007df (
.C(clk),
.CE(sig00000001),
.D(sig0000082c),
.Q(sig000002ea)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e0 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002dc),
.Q(sig0000082d),
.Q15(NLW_blk000007e0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e1 (
.C(clk),
.CE(sig00000001),
.D(sig0000082d),
.Q(sig000002d1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e2 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002db),
.Q(sig0000082e),
.Q15(NLW_blk000007e2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e3 (
.C(clk),
.CE(sig00000001),
.D(sig0000082e),
.Q(sig000002d0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e4 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002da),
.Q(sig0000082f),
.Q15(NLW_blk000007e4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e5 (
.C(clk),
.CE(sig00000001),
.D(sig0000082f),
.Q(sig000002cf)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e6 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d9),
.Q(sig00000830),
.Q15(NLW_blk000007e6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e7 (
.C(clk),
.CE(sig00000001),
.D(sig00000830),
.Q(sig000002ce)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007e8 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d8),
.Q(sig00000831),
.Q15(NLW_blk000007e8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e9 (
.C(clk),
.CE(sig00000001),
.D(sig00000831),
.Q(sig000002cd)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007ea (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d7),
.Q(sig00000832),
.Q15(NLW_blk000007ea_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007eb (
.C(clk),
.CE(sig00000001),
.D(sig00000832),
.Q(sig000002cc)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007ec (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d6),
.Q(sig00000833),
.Q15(NLW_blk000007ec_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ed (
.C(clk),
.CE(sig00000001),
.D(sig00000833),
.Q(sig000002cb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007ee (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d3),
.Q(sig00000834),
.Q15(NLW_blk000007ee_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ef (
.C(clk),
.CE(sig00000001),
.D(sig00000834),
.Q(sig000002c8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f0 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d5),
.Q(sig00000835),
.Q15(NLW_blk000007f0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f1 (
.C(clk),
.CE(sig00000001),
.D(sig00000835),
.Q(sig000002ca)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f2 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d4),
.Q(sig00000836),
.Q15(NLW_blk000007f2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f3 (
.C(clk),
.CE(sig00000001),
.D(sig00000836),
.Q(sig000002c9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f4 (
.A0(sig000006c3),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000002d2),
.Q(sig00000837),
.Q15(NLW_blk000007f4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f5 (
.C(clk),
.CE(sig00000001),
.D(sig00000837),
.Q(sig000002c7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f6 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig00000001),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003bd),
.Q(sig00000838),
.Q15(NLW_blk000007f6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f7 (
.C(clk),
.CE(sig00000001),
.D(sig00000838),
.Q(sig000002c6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007f8 (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000003d3),
.Q(sig00000839),
.Q15(NLW_blk000007f8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f9 (
.C(clk),
.CE(sig00000001),
.D(sig00000839),
.Q(sig0000018a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007fa (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig000004cb),
.Q(sig0000083a),
.Q15(NLW_blk000007fa_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007fb (
.C(clk),
.CE(sig00000001),
.D(sig0000083a),
.Q(sig000005f8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007fc (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069d),
.Q(sig0000083b),
.Q15(NLW_blk000007fc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007fd (
.C(clk),
.CE(sig00000001),
.D(sig0000083b),
.Q(sig00000606)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000007fe (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069f),
.Q(sig0000083c),
.Q15(NLW_blk000007fe_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ff (
.C(clk),
.CE(sig00000001),
.D(sig0000083c),
.Q(sig00000608)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000800 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069e),
.Q(sig0000083d),
.Q15(NLW_blk00000800_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000801 (
.C(clk),
.CE(sig00000001),
.D(sig0000083d),
.Q(sig00000607)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000802 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069c),
.Q(sig0000083e),
.Q15(NLW_blk00000802_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000803 (
.C(clk),
.CE(sig00000001),
.D(sig0000083e),
.Q(sig00000605)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000804 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069b),
.Q(sig0000083f),
.Q15(NLW_blk00000804_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000805 (
.C(clk),
.CE(sig00000001),
.D(sig0000083f),
.Q(sig00000604)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000806 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000069a),
.Q(sig00000840),
.Q15(NLW_blk00000806_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000807 (
.C(clk),
.CE(sig00000001),
.D(sig00000840),
.Q(sig00000603)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000808 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000699),
.Q(sig00000841),
.Q15(NLW_blk00000808_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000809 (
.C(clk),
.CE(sig00000001),
.D(sig00000841),
.Q(sig00000602)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000080a (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000119),
.Q(sig00000842),
.Q15(NLW_blk0000080a_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000080b (
.C(clk),
.CE(sig00000001),
.D(sig00000842),
.Q(sig00000188)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000080c (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000698),
.Q(sig00000843),
.Q15(NLW_blk0000080c_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000080d (
.C(clk),
.CE(sig00000001),
.D(sig00000843),
.Q(sig00000601)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000080e (
.A0(sig000006c3),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig00000118),
.Q(sig00000844),
.Q15(NLW_blk0000080e_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000080f (
.C(clk),
.CE(sig00000001),
.D(sig00000844),
.Q(sig00000189)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000810 (
.A0(sig00000001),
.A1(sig000006c3),
.A2(sig000006c3),
.A3(sig000006c3),
.CE(sig00000001),
.CLK(clk),
.D(sig0000018a),
.Q(sig00000845),
.Q15(NLW_blk00000810_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000811 (
.C(clk),
.CE(sig00000001),
.D(sig00000845),
.Q(sig00000155)
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 0 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "NONE" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000812 (
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000812_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig000006c3),
.CEB1(sig00000001),
.MULTSIGNOUT(NLW_blk00000812_MULTSIGNOUT_UNCONNECTED),
.CEC(sig000006c3),
.RSTM(sig000006c3),
.MULTSIGNIN(sig000006c3),
.CEB2(sig00000001),
.RSTCTRL(sig000006c3),
.CEP(sig00000001),
.CARRYCASCOUT(NLW_blk00000812_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig000006c3),
.CECARRYIN(sig000006c3),
.UNDERFLOW(NLW_blk00000812_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000812_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig000006c3),
.RSTALLCARRYIN(sig000006c3),
.CEALUMODE(sig000006c3),
.CEA2(sig00000001),
.CEA1(sig00000001),
.RSTB(sig000006c3),
.CEMULTCARRYIN(sig000006c3),
.OVERFLOW(NLW_blk00000812_OVERFLOW_UNCONNECTED),
.CECTRL(sig000006c3),
.CEM(sig000006c3),
.CARRYIN(sig000006c3),
.CARRYCASCIN(sig000006c3),
.RSTP(sig000006c3),
.CARRYINSEL({sig000006c3, sig000006c3, sig000006c3}),
.OPMODE({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig00000001, sig00000001}),
.B({sig00000648, sig00000647, sig00000646, sig00000645, sig00000644, sig00000643, sig00000642, sig00000641, sig00000640, sig0000063f, sig0000063e
, sig0000063d, sig0000063c, sig0000063b, sig0000063a, sig00000639, sig000006c3, sig000006c3}),
.A({sig000006c3, sig00000665, sig00000664, sig00000663, sig00000662, sig00000661, sig00000660, sig0000065f, sig0000065e, sig0000065d, sig0000065c
, sig0000065b, sig0000065a, sig00000659, sig00000658, sig00000657, sig00000656, sig00000655, sig00000654, sig00000653, sig00000652, sig00000651,
sig00000650, sig0000064f, sig0000064e, sig0000064d, sig0000064c, sig0000064b, sig0000064a, sig00000649}),
.PCOUT({sig00000638, sig00000637, sig00000636, sig00000635, sig00000634, sig00000633, sig00000632, sig00000631, sig00000630, sig0000062f,
sig0000062e, sig0000062d, sig0000062c, sig0000062b, sig0000062a, sig00000629, sig00000628, sig00000627, sig00000626, sig00000625, sig00000624,
sig00000623, sig00000622, sig00000621, sig00000620, sig0000061f, sig0000061e, sig0000061d, sig0000061c, sig0000061b, sig0000061a, sig00000619,
sig00000618, sig00000617, sig00000616, sig00000615, sig00000614, sig00000613, sig00000612, sig00000611, sig00000610, sig0000060f, sig0000060e,
sig0000060d, sig0000060c, sig0000060b, sig0000060a, sig00000609}),
.ACOUT({\NLW_blk00000812_ACOUT<29>_UNCONNECTED , \NLW_blk00000812_ACOUT<28>_UNCONNECTED , \NLW_blk00000812_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<26>_UNCONNECTED , \NLW_blk00000812_ACOUT<25>_UNCONNECTED , \NLW_blk00000812_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<23>_UNCONNECTED , \NLW_blk00000812_ACOUT<22>_UNCONNECTED , \NLW_blk00000812_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<20>_UNCONNECTED , \NLW_blk00000812_ACOUT<19>_UNCONNECTED , \NLW_blk00000812_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<17>_UNCONNECTED , \NLW_blk00000812_ACOUT<16>_UNCONNECTED , \NLW_blk00000812_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<14>_UNCONNECTED , \NLW_blk00000812_ACOUT<13>_UNCONNECTED , \NLW_blk00000812_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<11>_UNCONNECTED , \NLW_blk00000812_ACOUT<10>_UNCONNECTED , \NLW_blk00000812_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<8>_UNCONNECTED , \NLW_blk00000812_ACOUT<7>_UNCONNECTED , \NLW_blk00000812_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<5>_UNCONNECTED , \NLW_blk00000812_ACOUT<4>_UNCONNECTED , \NLW_blk00000812_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000812_ACOUT<2>_UNCONNECTED , \NLW_blk00000812_ACOUT<1>_UNCONNECTED , \NLW_blk00000812_ACOUT<0>_UNCONNECTED }),
.PCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.ALUMODE({sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.C({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3
, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.CARRYOUT({\NLW_blk00000812_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000812_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000812_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000812_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.BCOUT({\NLW_blk00000812_BCOUT<17>_UNCONNECTED , \NLW_blk00000812_BCOUT<16>_UNCONNECTED , \NLW_blk00000812_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<14>_UNCONNECTED , \NLW_blk00000812_BCOUT<13>_UNCONNECTED , \NLW_blk00000812_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<11>_UNCONNECTED , \NLW_blk00000812_BCOUT<10>_UNCONNECTED , \NLW_blk00000812_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<8>_UNCONNECTED , \NLW_blk00000812_BCOUT<7>_UNCONNECTED , \NLW_blk00000812_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<5>_UNCONNECTED , \NLW_blk00000812_BCOUT<4>_UNCONNECTED , \NLW_blk00000812_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000812_BCOUT<2>_UNCONNECTED , \NLW_blk00000812_BCOUT<1>_UNCONNECTED , \NLW_blk00000812_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000812_P<47>_UNCONNECTED , \NLW_blk00000812_P<46>_UNCONNECTED , \NLW_blk00000812_P<45>_UNCONNECTED ,
\NLW_blk00000812_P<44>_UNCONNECTED , \NLW_blk00000812_P<43>_UNCONNECTED , \NLW_blk00000812_P<42>_UNCONNECTED , \NLW_blk00000812_P<41>_UNCONNECTED ,
\NLW_blk00000812_P<40>_UNCONNECTED , \NLW_blk00000812_P<39>_UNCONNECTED , \NLW_blk00000812_P<38>_UNCONNECTED , \NLW_blk00000812_P<37>_UNCONNECTED ,
\NLW_blk00000812_P<36>_UNCONNECTED , \NLW_blk00000812_P<35>_UNCONNECTED , \NLW_blk00000812_P<34>_UNCONNECTED , \NLW_blk00000812_P<33>_UNCONNECTED ,
\NLW_blk00000812_P<32>_UNCONNECTED , \NLW_blk00000812_P<31>_UNCONNECTED , \NLW_blk00000812_P<30>_UNCONNECTED , \NLW_blk00000812_P<29>_UNCONNECTED ,
\NLW_blk00000812_P<28>_UNCONNECTED , \NLW_blk00000812_P<27>_UNCONNECTED , \NLW_blk00000812_P<26>_UNCONNECTED , \NLW_blk00000812_P<25>_UNCONNECTED ,
\NLW_blk00000812_P<24>_UNCONNECTED , \NLW_blk00000812_P<23>_UNCONNECTED , \NLW_blk00000812_P<22>_UNCONNECTED , \NLW_blk00000812_P<21>_UNCONNECTED ,
\NLW_blk00000812_P<20>_UNCONNECTED , \NLW_blk00000812_P<19>_UNCONNECTED , \NLW_blk00000812_P<18>_UNCONNECTED , \NLW_blk00000812_P<17>_UNCONNECTED ,
\NLW_blk00000812_P<16>_UNCONNECTED , \NLW_blk00000812_P<15>_UNCONNECTED , \NLW_blk00000812_P<14>_UNCONNECTED , \NLW_blk00000812_P<13>_UNCONNECTED ,
\NLW_blk00000812_P<12>_UNCONNECTED , \NLW_blk00000812_P<11>_UNCONNECTED , \NLW_blk00000812_P<10>_UNCONNECTED , \NLW_blk00000812_P<9>_UNCONNECTED ,
\NLW_blk00000812_P<8>_UNCONNECTED , \NLW_blk00000812_P<7>_UNCONNECTED , \NLW_blk00000812_P<6>_UNCONNECTED , \NLW_blk00000812_P<5>_UNCONNECTED ,
\NLW_blk00000812_P<4>_UNCONNECTED , \NLW_blk00000812_P<3>_UNCONNECTED , \NLW_blk00000812_P<2>_UNCONNECTED , \NLW_blk00000812_P<1>_UNCONNECTED ,
\NLW_blk00000812_P<0>_UNCONNECTED }),
.ACIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3})
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 1 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 0 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "NONE" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000813 (
.RSTALLCARRYIN(sig000004cc),
.CLK(clk),
.CARRYIN(sig0000050d),
.PATTERNBDETECT(NLW_blk00000813_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig000006c3),
.CEB1(sig000006c3),
.MULTSIGNOUT(NLW_blk00000813_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000001),
.RSTM(sig000006c3),
.MULTSIGNIN(sig000006c3),
.CEB2(sig00000001),
.RSTCTRL(sig000006c3),
.CEP(sig00000001),
.CARRYCASCOUT(NLW_blk00000813_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig000006c3),
.CECARRYIN(sig00000001),
.UNDERFLOW(NLW_blk00000813_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000813_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig000006c3),
.CEALUMODE(sig00000001),
.CEA2(sig00000001),
.CEA1(sig000006c3),
.RSTB(sig000006c3),
.CEMULTCARRYIN(sig000006c3),
.OVERFLOW(NLW_blk00000813_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000001),
.CEM(sig000006c3),
.CARRYCASCIN(sig000006c3),
.RSTP(sig000006c3),
.CARRYINSEL({sig000006c3, sig000006c3, sig000006c3}),
.OPMODE({sig000006c3, sig000006c3, sig00000001, sig000004c7, sig000004c7, sig000004c8, sig000004c8}),
.PCIN({sig00000638, sig00000637, sig00000636, sig00000635, sig00000634, sig00000633, sig00000632, sig00000631, sig00000630, sig0000062f,
sig0000062e, sig0000062d, sig0000062c, sig0000062b, sig0000062a, sig00000629, sig00000628, sig00000627, sig00000626, sig00000625, sig00000624,
sig00000623, sig00000622, sig00000621, sig00000620, sig0000061f, sig0000061e, sig0000061d, sig0000061c, sig0000061b, sig0000061a, sig00000619,
sig00000618, sig00000617, sig00000616, sig00000615, sig00000614, sig00000613, sig00000612, sig00000611, sig00000610, sig0000060f, sig0000060e,
sig0000060d, sig0000060c, sig0000060b, sig0000060a, sig00000609}),
.A({sig000004c9, sig00000485, sig00000486, sig00000487, sig00000488, sig00000489, sig0000048a, sig0000048b, sig0000048c, sig0000048d, sig0000048e
, sig0000048f, sig00000490, sig00000491, sig00000492, sig00000493, sig00000494, sig00000495, sig00000496, sig00000497, sig00000498, sig00000499,
sig0000049a, sig0000049b, sig0000049c, sig0000049d, sig0000049e, sig0000049f, sig000004a0, sig000004a1}),
.C({sig000004c9, sig00000483, sig00000484, sig00000485, sig00000486, sig00000487, sig00000488, sig00000489, sig0000048a, sig0000048b, sig0000048c
, sig0000048d, sig0000048e, sig0000048f, sig00000490, sig00000491, sig00000492, sig00000493, sig00000494, sig00000495, sig00000496, sig00000497,
sig00000498, sig00000499, sig0000049a, sig0000049b, sig0000049c, sig0000049d, sig0000049e, sig0000049f, sig000004a0, sig000004a1, sig000004a2,
sig000004a3, sig000004a4, sig000004a5, sig000004a6, sig000004a7, sig000004a8, sig000004a9, sig000004aa, sig000004ab, sig000004ac, sig000004ad,
sig000004ae, sig000004af, sig000004b0, sig000004b1}),
.B({sig000004a2, sig000004a3, sig000004a4, sig000004a5, sig000004a6, sig000004a7, sig000004a8, sig000004a9, sig000004aa, sig000004ab, sig000004ac
, sig000004ad, sig000004ae, sig000004af, sig000004b0, sig000004b1, sig000004b2, sig000004b3}),
.P({sig00000666, sig00000695, sig00000694, sig00000693, sig00000692, sig00000691, sig00000690, sig0000068f, sig0000068e, sig0000068d, sig0000068c
, sig0000068b, sig0000068a, sig00000689, sig00000688, sig00000687, sig00000686, sig00000685, sig00000684, sig00000683, sig00000682, sig00000681,
sig00000680, sig0000067f, sig0000067e, sig0000067d, sig0000067c, sig0000067b, sig0000067a, sig00000679, sig00000678, sig00000677, sig00000676,
sig00000675, sig00000674, sig00000673, sig00000672, sig00000671, sig00000670, sig0000066f, sig0000066e, sig0000066d, sig0000066c, sig0000066b,
sig0000066a, sig00000669, sig00000668, sig00000667}),
.ACOUT({\NLW_blk00000813_ACOUT<29>_UNCONNECTED , \NLW_blk00000813_ACOUT<28>_UNCONNECTED , \NLW_blk00000813_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<26>_UNCONNECTED , \NLW_blk00000813_ACOUT<25>_UNCONNECTED , \NLW_blk00000813_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<23>_UNCONNECTED , \NLW_blk00000813_ACOUT<22>_UNCONNECTED , \NLW_blk00000813_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<20>_UNCONNECTED , \NLW_blk00000813_ACOUT<19>_UNCONNECTED , \NLW_blk00000813_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<17>_UNCONNECTED , \NLW_blk00000813_ACOUT<16>_UNCONNECTED , \NLW_blk00000813_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<14>_UNCONNECTED , \NLW_blk00000813_ACOUT<13>_UNCONNECTED , \NLW_blk00000813_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<11>_UNCONNECTED , \NLW_blk00000813_ACOUT<10>_UNCONNECTED , \NLW_blk00000813_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<8>_UNCONNECTED , \NLW_blk00000813_ACOUT<7>_UNCONNECTED , \NLW_blk00000813_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<5>_UNCONNECTED , \NLW_blk00000813_ACOUT<4>_UNCONNECTED , \NLW_blk00000813_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000813_ACOUT<2>_UNCONNECTED , \NLW_blk00000813_ACOUT<1>_UNCONNECTED , \NLW_blk00000813_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig000006c3, sig000006c3, sig000004c9, sig000004c9}),
.CARRYOUT({\NLW_blk00000813_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000813_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000813_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000813_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.BCOUT({\NLW_blk00000813_BCOUT<17>_UNCONNECTED , \NLW_blk00000813_BCOUT<16>_UNCONNECTED , \NLW_blk00000813_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<14>_UNCONNECTED , \NLW_blk00000813_BCOUT<13>_UNCONNECTED , \NLW_blk00000813_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<11>_UNCONNECTED , \NLW_blk00000813_BCOUT<10>_UNCONNECTED , \NLW_blk00000813_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<8>_UNCONNECTED , \NLW_blk00000813_BCOUT<7>_UNCONNECTED , \NLW_blk00000813_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<5>_UNCONNECTED , \NLW_blk00000813_BCOUT<4>_UNCONNECTED , \NLW_blk00000813_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000813_BCOUT<2>_UNCONNECTED , \NLW_blk00000813_BCOUT<1>_UNCONNECTED , \NLW_blk00000813_BCOUT<0>_UNCONNECTED }),
.PCOUT({\NLW_blk00000813_PCOUT<47>_UNCONNECTED , \NLW_blk00000813_PCOUT<46>_UNCONNECTED , \NLW_blk00000813_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<44>_UNCONNECTED , \NLW_blk00000813_PCOUT<43>_UNCONNECTED , \NLW_blk00000813_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<41>_UNCONNECTED , \NLW_blk00000813_PCOUT<40>_UNCONNECTED , \NLW_blk00000813_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<38>_UNCONNECTED , \NLW_blk00000813_PCOUT<37>_UNCONNECTED , \NLW_blk00000813_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<35>_UNCONNECTED , \NLW_blk00000813_PCOUT<34>_UNCONNECTED , \NLW_blk00000813_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<32>_UNCONNECTED , \NLW_blk00000813_PCOUT<31>_UNCONNECTED , \NLW_blk00000813_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<29>_UNCONNECTED , \NLW_blk00000813_PCOUT<28>_UNCONNECTED , \NLW_blk00000813_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<26>_UNCONNECTED , \NLW_blk00000813_PCOUT<25>_UNCONNECTED , \NLW_blk00000813_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<23>_UNCONNECTED , \NLW_blk00000813_PCOUT<22>_UNCONNECTED , \NLW_blk00000813_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<20>_UNCONNECTED , \NLW_blk00000813_PCOUT<19>_UNCONNECTED , \NLW_blk00000813_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<17>_UNCONNECTED , \NLW_blk00000813_PCOUT<16>_UNCONNECTED , \NLW_blk00000813_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<14>_UNCONNECTED , \NLW_blk00000813_PCOUT<13>_UNCONNECTED , \NLW_blk00000813_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<11>_UNCONNECTED , \NLW_blk00000813_PCOUT<10>_UNCONNECTED , \NLW_blk00000813_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<8>_UNCONNECTED , \NLW_blk00000813_PCOUT<7>_UNCONNECTED , \NLW_blk00000813_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<5>_UNCONNECTED , \NLW_blk00000813_PCOUT<4>_UNCONNECTED , \NLW_blk00000813_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000813_PCOUT<2>_UNCONNECTED , \NLW_blk00000813_PCOUT<1>_UNCONNECTED , \NLW_blk00000813_PCOUT<0>_UNCONNECTED }),
.ACIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3})
);
DSP48E #(
.ACASCREG ( 0 ),
.ALUMODEREG ( 1 ),
.AREG ( 0 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 0 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "NONE" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000814 (
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000814_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig000006c3),
.CEB1(sig000006c3),
.MULTSIGNOUT(NLW_blk00000814_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000001),
.RSTM(sig000006c3),
.MULTSIGNIN(sig000006c3),
.CEB2(sig00000001),
.RSTCTRL(sig000006c3),
.CEP(sig00000001),
.CARRYCASCOUT(NLW_blk00000814_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig000006c3),
.CECARRYIN(sig00000001),
.UNDERFLOW(NLW_blk00000814_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000814_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig000006c3),
.RSTALLCARRYIN(sig000006c3),
.CEALUMODE(sig00000001),
.CEA2(sig000006c3),
.CEA1(sig000006c3),
.RSTB(sig000006c3),
.CEMULTCARRYIN(sig000006c3),
.OVERFLOW(NLW_blk00000814_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000001),
.CEM(sig000006c3),
.CARRYIN(sig000006c3),
.CARRYCASCIN(sig000006c3),
.RSTP(sig000006c3),
.CARRYINSEL({sig000006c3, sig000006c3, sig000006c3}),
.OPMODE({sig000006c3, sig00000001, sig00000001, sig000006c3, sig000006c3, sig00000001, sig00000001}),
.C({sig000006c3, sig00000752, sig0000079d, sig0000079c, sig0000079b, sig0000079a, sig00000799, sig00000798, sig00000797, sig00000796, sig00000795
, sig00000794, sig00000793, sig00000792, sig00000791, sig00000790, sig0000078f, sig0000078e, sig0000078d, sig0000078c, sig0000078b, sig0000078a,
sig00000789, sig00000788, sig00000787, sig00000786, sig00000785, sig00000784, sig00000783, sig00000782, sig00000781, sig00000780, sig0000077f,
sig0000077e, sig0000077d, sig0000077c, sig0000077b, sig0000077a, sig00000779, sig00000778, sig00000777, sig00000776, sig00000775, sig00000774,
sig00000773, sig00000772, sig00000771, sig00000770}),
.B({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3
, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig00000768, sig000006c3}),
.P({sig00000767, sig00000185, sig00000184, sig00000183, sig00000182, sig00000181, sig00000180, sig0000017f, sig0000017e, sig0000017d, sig0000017c
, sig0000017b, sig0000017a, sig00000179, sig00000178, sig00000177, sig00000176, sig00000175, sig00000174, sig00000173, sig00000172, sig00000171,
sig00000170, sig0000016f, sig0000016e, sig0000016d, sig0000016c, sig0000016b, sig0000016a, sig00000169, sig00000168, sig00000167, sig00000166,
sig00000165, sig00000164, sig00000163, sig00000162, sig00000161, sig00000160, sig0000015f, sig0000015e, sig0000015d, sig0000015c, sig0000015b,
sig0000015a, sig00000159, sig00000158, \NLW_blk00000814_P<0>_UNCONNECTED }),
.ACOUT({\NLW_blk00000814_ACOUT<29>_UNCONNECTED , \NLW_blk00000814_ACOUT<28>_UNCONNECTED , \NLW_blk00000814_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<26>_UNCONNECTED , \NLW_blk00000814_ACOUT<25>_UNCONNECTED , \NLW_blk00000814_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<23>_UNCONNECTED , \NLW_blk00000814_ACOUT<22>_UNCONNECTED , \NLW_blk00000814_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<20>_UNCONNECTED , \NLW_blk00000814_ACOUT<19>_UNCONNECTED , \NLW_blk00000814_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<17>_UNCONNECTED , \NLW_blk00000814_ACOUT<16>_UNCONNECTED , \NLW_blk00000814_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<14>_UNCONNECTED , \NLW_blk00000814_ACOUT<13>_UNCONNECTED , \NLW_blk00000814_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<11>_UNCONNECTED , \NLW_blk00000814_ACOUT<10>_UNCONNECTED , \NLW_blk00000814_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<8>_UNCONNECTED , \NLW_blk00000814_ACOUT<7>_UNCONNECTED , \NLW_blk00000814_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<5>_UNCONNECTED , \NLW_blk00000814_ACOUT<4>_UNCONNECTED , \NLW_blk00000814_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000814_ACOUT<2>_UNCONNECTED , \NLW_blk00000814_ACOUT<1>_UNCONNECTED , \NLW_blk00000814_ACOUT<0>_UNCONNECTED }),
.PCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.ALUMODE({sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.CARRYOUT({\NLW_blk00000814_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000814_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000814_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000814_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.BCOUT({\NLW_blk00000814_BCOUT<17>_UNCONNECTED , \NLW_blk00000814_BCOUT<16>_UNCONNECTED , \NLW_blk00000814_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<14>_UNCONNECTED , \NLW_blk00000814_BCOUT<13>_UNCONNECTED , \NLW_blk00000814_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<11>_UNCONNECTED , \NLW_blk00000814_BCOUT<10>_UNCONNECTED , \NLW_blk00000814_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<8>_UNCONNECTED , \NLW_blk00000814_BCOUT<7>_UNCONNECTED , \NLW_blk00000814_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<5>_UNCONNECTED , \NLW_blk00000814_BCOUT<4>_UNCONNECTED , \NLW_blk00000814_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000814_BCOUT<2>_UNCONNECTED , \NLW_blk00000814_BCOUT<1>_UNCONNECTED , \NLW_blk00000814_BCOUT<0>_UNCONNECTED }),
.A({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3
, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3}),
.PCOUT({\NLW_blk00000814_PCOUT<47>_UNCONNECTED , \NLW_blk00000814_PCOUT<46>_UNCONNECTED , \NLW_blk00000814_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<44>_UNCONNECTED , \NLW_blk00000814_PCOUT<43>_UNCONNECTED , \NLW_blk00000814_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<41>_UNCONNECTED , \NLW_blk00000814_PCOUT<40>_UNCONNECTED , \NLW_blk00000814_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<38>_UNCONNECTED , \NLW_blk00000814_PCOUT<37>_UNCONNECTED , \NLW_blk00000814_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<35>_UNCONNECTED , \NLW_blk00000814_PCOUT<34>_UNCONNECTED , \NLW_blk00000814_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<32>_UNCONNECTED , \NLW_blk00000814_PCOUT<31>_UNCONNECTED , \NLW_blk00000814_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<29>_UNCONNECTED , \NLW_blk00000814_PCOUT<28>_UNCONNECTED , \NLW_blk00000814_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<26>_UNCONNECTED , \NLW_blk00000814_PCOUT<25>_UNCONNECTED , \NLW_blk00000814_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<23>_UNCONNECTED , \NLW_blk00000814_PCOUT<22>_UNCONNECTED , \NLW_blk00000814_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<20>_UNCONNECTED , \NLW_blk00000814_PCOUT<19>_UNCONNECTED , \NLW_blk00000814_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<17>_UNCONNECTED , \NLW_blk00000814_PCOUT<16>_UNCONNECTED , \NLW_blk00000814_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<14>_UNCONNECTED , \NLW_blk00000814_PCOUT<13>_UNCONNECTED , \NLW_blk00000814_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<11>_UNCONNECTED , \NLW_blk00000814_PCOUT<10>_UNCONNECTED , \NLW_blk00000814_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<8>_UNCONNECTED , \NLW_blk00000814_PCOUT<7>_UNCONNECTED , \NLW_blk00000814_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<5>_UNCONNECTED , \NLW_blk00000814_PCOUT<4>_UNCONNECTED , \NLW_blk00000814_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000814_PCOUT<2>_UNCONNECTED , \NLW_blk00000814_PCOUT<1>_UNCONNECTED , \NLW_blk00000814_PCOUT<0>_UNCONNECTED }),
.ACIN({sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3,
sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3, sig000006c3})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200 Top Level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// OR1200 Top Level ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_top.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_top(
// System
clk_i, rst_i, pic_ints_i, clmode_i,
// Instruction WISHBONE INTERFACE
iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
`ifdef OR1200_WB_CAB
iwb_cab_o,
`endif
`ifdef OR1200_WB_B3
iwb_cti_o, iwb_bte_o,
`endif
// Data WISHBONE INTERFACE
dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
`ifdef OR1200_WB_CAB
dwb_cab_o,
`endif
`ifdef OR1200_WB_B3
dwb_cti_o, dwb_bte_o,
`endif
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Power Management
pm_cpustall_i,
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
,sig_tick
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;
parameter boot_adr = `OR1200_BOOT_ADR;
//
// I/O
//
//
// System
//
input clk_i;
input rst_i;
input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
input [ppic_ints-1:0] pic_ints_i;
//
// Instruction WISHBONE interface
//
input iwb_clk_i; // clock input
input iwb_rst_i; // reset input
input iwb_ack_i; // normal termination
input iwb_err_i; // termination w/ error
input iwb_rty_i; // termination w/ retry
input [dw-1:0] iwb_dat_i; // input data bus
output iwb_cyc_o; // cycle valid output
output [aw-1:0] iwb_adr_o; // address bus outputs
output iwb_stb_o; // strobe output
output iwb_we_o; // indicates write transfer
output [3:0] iwb_sel_o; // byte select outputs
output [dw-1:0] iwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output iwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] iwb_cti_o; // cycle type identifier
output [1:0] iwb_bte_o; // burst type extension
`endif
//
// Data WISHBONE interface
//
input dwb_clk_i; // clock input
input dwb_rst_i; // reset input
input dwb_ack_i; // normal termination
input dwb_err_i; // termination w/ error
input dwb_rty_i; // termination w/ retry
input [dw-1:0] dwb_dat_i; // input data bus
output dwb_cyc_o; // cycle valid output
output [aw-1:0] dwb_adr_o; // address bus outputs
output dwb_stb_o; // strobe output
output dwb_we_o; // indicates write transfer
output [3:0] dwb_sel_o; // byte select outputs
output [dw-1:0] dwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output dwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] dwb_cti_o; // cycle type identifier
output [1:0] dwb_bte_o; // burst type extension
`endif
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Power Management
//
input pm_cpustall_i;
output [3:0] pm_clksd_o;
output pm_dc_gate_o;
output pm_ic_gate_o;
output pm_dmmu_gate_o;
output pm_immu_gate_o;
output pm_tt_gate_o;
output pm_cpu_gate_o;
output pm_wakeup_o;
output pm_lvolt_o;
//
// Internal wires and regs
//
//
// DC to SB
//
wire [dw-1:0] dcsb_dat_dc;
wire [aw-1:0] dcsb_adr_dc;
wire dcsb_cyc_dc;
wire dcsb_stb_dc;
wire dcsb_we_dc;
wire [3:0] dcsb_sel_dc;
wire dcsb_cab_dc;
wire [dw-1:0] dcsb_dat_sb;
wire dcsb_ack_sb;
wire dcsb_err_sb;
//
// SB to BIU
//
wire [dw-1:0] sbbiu_dat_sb;
wire [aw-1:0] sbbiu_adr_sb;
wire sbbiu_cyc_sb;
wire sbbiu_stb_sb;
wire sbbiu_we_sb;
wire [3:0] sbbiu_sel_sb;
wire sbbiu_cab_sb;
wire [dw-1:0] sbbiu_dat_biu;
wire sbbiu_ack_biu;
wire sbbiu_err_biu;
//
// IC to BIU
//
wire [dw-1:0] icbiu_dat_ic;
wire [aw-1:0] icbiu_adr_ic;
wire [aw-1:0] icbiu_adr_ic_word;
wire icbiu_cyc_ic;
wire icbiu_stb_ic;
wire icbiu_we_ic;
wire [3:0] icbiu_sel_ic;
wire [3:0] icbiu_tag_ic;
wire icbiu_cab_ic;
wire [dw-1:0] icbiu_dat_biu;
wire icbiu_ack_biu;
wire icbiu_err_biu;
wire [3:0] icbiu_tag_biu;
//
// SR Interface (this signal can be connected to the input pin)
//
wire boot_adr_sel = `OR1200_SR_EPH_DEF;
//
// CPU's SPR access to various RISC units (shared wires)
//
wire supv;
wire [aw-1:0] spr_addr;
wire [dw-1:0] spr_dat_cpu;
wire [31:0] spr_cs;
wire spr_we;
wire mtspr_dc_done;
//
// SB
//
wire sb_en;
//
// DMMU and CPU
//
wire dmmu_en;
wire [31:0] spr_dat_dmmu;
//
// DMMU and QMEM
//
wire qmemdmmu_err_qmem;
wire [3:0] qmemdmmu_tag_qmem;
wire [aw-1:0] qmemdmmu_adr_dmmu;
wire qmemdmmu_cycstb_dmmu;
wire qmemdmmu_ci_dmmu;
//
// CPU and data memory subsystem
//
wire dc_en;
wire [31:0] dcpu_adr_cpu;
wire dcpu_cycstb_cpu;
wire dcpu_we_cpu;
wire [3:0] dcpu_sel_cpu;
wire [3:0] dcpu_tag_cpu;
wire [31:0] dcpu_dat_cpu;
wire [31:0] dcpu_dat_qmem;
wire dcpu_ack_qmem;
wire dcpu_rty_qmem;
wire dcpu_err_dmmu;
wire [3:0] dcpu_tag_dmmu;
wire dc_no_writethrough;
//
// IMMU and CPU
//
wire immu_en;
wire [31:0] spr_dat_immu;
//
// CPU and insn memory subsystem
//
wire ic_en;
wire [31:0] icpu_adr_cpu;
wire icpu_cycstb_cpu;
wire [3:0] icpu_sel_cpu;
wire [3:0] icpu_tag_cpu;
wire [31:0] icpu_dat_qmem;
wire icpu_ack_qmem;
wire [31:0] icpu_adr_immu;
wire icpu_err_immu;
wire [3:0] icpu_tag_immu;
wire icpu_rty_immu;
//
// IMMU and QMEM
//
wire [aw-1:0] qmemimmu_adr_immu;
wire qmemimmu_rty_qmem;
wire qmemimmu_err_qmem;
wire [3:0] qmemimmu_tag_qmem;
wire qmemimmu_cycstb_immu;
wire qmemimmu_ci_immu;
//
// QMEM and IC
//
wire [aw-1:0] icqmem_adr_qmem;
wire icqmem_rty_ic;
wire icqmem_err_ic;
wire [3:0] icqmem_tag_ic;
wire icqmem_cycstb_qmem;
wire icqmem_ci_qmem;
wire [31:0] icqmem_dat_ic;
wire icqmem_ack_ic;
//
// QMEM and DC
//
wire [aw-1:0] dcqmem_adr_qmem;
wire dcqmem_rty_dc;
wire dcqmem_err_dc;
wire [3:0] dcqmem_tag_dc;
wire dcqmem_cycstb_qmem;
wire dcqmem_ci_qmem;
wire [31:0] dcqmem_dat_dc;
wire [31:0] dcqmem_dat_qmem;
wire dcqmem_we_qmem;
wire [3:0] dcqmem_sel_qmem;
wire dcqmem_ack_dc;
//
// Connection between CPU and PIC
//
wire [dw-1:0] spr_dat_pic;
wire pic_wakeup;
wire sig_int;
//
// Connection between CPU and PM
//
wire [dw-1:0] spr_dat_pm;
//
// CPU and TT
//
wire [dw-1:0] spr_dat_tt;
output wire sig_tick; // jb
//
// Debug port and caches/MMUs
//
wire [dw-1:0] spr_dat_du;
wire du_stall;
wire [dw-1:0] du_addr;
wire [dw-1:0] du_dat_du;
wire du_read;
wire du_write;
wire [13:0] du_except_trig;
wire [13:0] du_except_stop;
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
wire [24:0] du_dmr1;
wire [dw-1:0] du_dat_cpu;
wire [dw-1:0] du_lsu_store_dat;
wire [dw-1:0] du_lsu_load_dat;
wire du_hwbkpt;
wire du_hwbkpt_ls_r = 1'b0;
wire flushpipe;
wire ex_freeze;
wire wb_freeze;
wire id_void;
wire ex_void;
wire [31:0] id_insn;
wire [31:0] ex_insn;
wire [31:0] wb_insn;
wire [31:0] id_pc;
wire [31:0] ex_pc;
wire [31:0] wb_pc;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [31:0] spr_dat_npc;
wire [31:0] rf_dataw;
wire abort_ex;
wire abort_mvspr;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_immu_so;
wire mbist_ic_so;
wire mbist_dmmu_so;
wire mbist_dc_so;
wire mbist_qmem_so;
wire mbist_immu_si = mbist_si_i;
wire mbist_ic_si = mbist_immu_so;
wire mbist_qmem_si = mbist_ic_so;
wire mbist_dmmu_si = mbist_qmem_so;
wire mbist_dc_si = mbist_dmmu_so;
assign mbist_so_o = mbist_dc_so;
`endif
wire [3:0] icqmem_sel_qmem;
wire [3:0] icqmem_tag_qmem;
wire [3:0] dcqmem_tag_qmem;
//
// Instantiation of Instruction WISHBONE BIU
//
or1200_wb_biu
#(.bl((1 << (`OR1200_ICLS-2))))
iwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
.clmode(clmode_i),
// WISHBONE interface
.wb_clk_i(iwb_clk_i),
.wb_rst_i(iwb_rst_i),
.wb_ack_i(iwb_ack_i),
.wb_err_i(iwb_err_i),
.wb_rty_i(iwb_rty_i),
.wb_dat_i(iwb_dat_i),
.wb_cyc_o(iwb_cyc_o),
.wb_adr_o(iwb_adr_o),
.wb_stb_o(iwb_stb_o),
.wb_we_o(iwb_we_o),
.wb_sel_o(iwb_sel_o),
.wb_dat_o(iwb_dat_o),
`ifdef OR1200_WB_CAB
.wb_cab_o(iwb_cab_o),
`endif
`ifdef OR1200_WB_B3
.wb_cti_o(iwb_cti_o),
.wb_bte_o(iwb_bte_o),
`endif
// Internal RISC bus
.biu_dat_i(icbiu_dat_ic),
.biu_adr_i(icbiu_adr_ic_word),
.biu_cyc_i(icbiu_cyc_ic),
.biu_stb_i(icbiu_stb_ic),
.biu_we_i(icbiu_we_ic),
.biu_sel_i(icbiu_sel_ic),
.biu_cab_i(icbiu_cab_ic),
.biu_dat_o(icbiu_dat_biu),
.biu_ack_o(icbiu_ack_biu),
.biu_err_o(icbiu_err_biu)
);
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
//
// Instantiation of Data WISHBONE BIU
//
or1200_wb_biu
#(.bl((1 << (`OR1200_DCLS-2))))
dwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
.clmode(clmode_i),
// WISHBONE interface
.wb_clk_i(dwb_clk_i),
.wb_rst_i(dwb_rst_i),
.wb_ack_i(dwb_ack_i),
.wb_err_i(dwb_err_i),
.wb_rty_i(dwb_rty_i),
.wb_dat_i(dwb_dat_i),
.wb_cyc_o(dwb_cyc_o),
.wb_adr_o(dwb_adr_o),
.wb_stb_o(dwb_stb_o),
.wb_we_o(dwb_we_o),
.wb_sel_o(dwb_sel_o),
.wb_dat_o(dwb_dat_o),
`ifdef OR1200_WB_CAB
.wb_cab_o(dwb_cab_o),
`endif
`ifdef OR1200_WB_B3
.wb_cti_o(dwb_cti_o),
.wb_bte_o(dwb_bte_o),
`endif
// Internal RISC bus
.biu_dat_i(sbbiu_dat_sb),
.biu_adr_i(sbbiu_adr_sb),
.biu_cyc_i(sbbiu_cyc_sb),
.biu_stb_i(sbbiu_stb_sb),
.biu_we_i(sbbiu_we_sb),
.biu_sel_i(sbbiu_sel_sb),
.biu_cab_i(sbbiu_cab_sb),
.biu_dat_o(sbbiu_dat_biu),
.biu_ack_o(sbbiu_ack_biu),
.biu_err_o(sbbiu_err_biu)
);
//
// Instantiation of IMMU
//
wire immu_sxe, immu_uxe;
or1200_immu_top
#(.boot_adr(boot_adr))
or1200_immu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_immu_si),
.mbist_so_o(mbist_immu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// CPU and IMMU
.ic_en(ic_en),
.immu_en(immu_en),
.supv(supv),
.icpu_adr_i(icpu_adr_cpu),
.icpu_cycstb_i(icpu_cycstb_cpu),
.icpu_adr_o(icpu_adr_immu),
.icpu_tag_o(icpu_tag_immu),
.icpu_rty_o(icpu_rty_immu),
.icpu_err_o(icpu_err_immu),
.itlb_uxe(immu_uxe),
.itlb_sxe(immu_sxe),
// SR Interface
.boot_adr_sel_i(boot_adr_sel),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_immu),
// QMEM and IMMU
.qmemimmu_rty_i(qmemimmu_rty_qmem),
.qmemimmu_err_i(qmemimmu_err_qmem),
.qmemimmu_tag_i(qmemimmu_tag_qmem),
.qmemimmu_adr_o(qmemimmu_adr_immu),
.qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
.qmemimmu_ci_o(qmemimmu_ci_immu)
);
//
// Instantiation of Instruction Cache
//
or1200_ic_top or1200_ic_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ic_si),
.mbist_so_o(mbist_ic_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// IC and QMEM
.ic_en(ic_en),
.icqmem_adr_i(icqmem_adr_qmem),
.icqmem_cycstb_i(icqmem_cycstb_qmem),
.icqmem_ci_i(icqmem_ci_qmem),
.icqmem_sel_i(icqmem_sel_qmem),
.icqmem_tag_i(icqmem_tag_qmem),
.icqmem_dat_o(icqmem_dat_ic),
.icqmem_ack_o(icqmem_ack_ic),
.icqmem_rty_o(icqmem_rty_ic),
.icqmem_err_o(icqmem_err_ic),
.icqmem_tag_o(icqmem_tag_ic),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
.spr_write(spr_we),
.spr_dat_i(spr_dat_cpu),
// IC and BIU
.icbiu_dat_o(icbiu_dat_ic),
.icbiu_adr_o(icbiu_adr_ic),
.icbiu_cyc_o(icbiu_cyc_ic),
.icbiu_stb_o(icbiu_stb_ic),
.icbiu_we_o(icbiu_we_ic),
.icbiu_sel_o(icbiu_sel_ic),
.icbiu_cab_o(icbiu_cab_ic),
.icbiu_dat_i(icbiu_dat_biu),
.icbiu_ack_i(icbiu_ack_biu),
.icbiu_err_i(icbiu_err_biu)
);
//
// Instantiation of Instruction Cache
//
or1200_cpu
#(.boot_adr(boot_adr))
or1200_cpu(
.clk(clk_i),
.rst(rst_i),
// Connection QMEM and IFETCHER inside CPU
.ic_en(ic_en),
.icpu_adr_o(icpu_adr_cpu),
.icpu_cycstb_o(icpu_cycstb_cpu),
.icpu_sel_o(icpu_sel_cpu),
.icpu_tag_o(icpu_tag_cpu),
.icpu_dat_i(icpu_dat_qmem),
.icpu_ack_i(icpu_ack_qmem),
.icpu_rty_i(icpu_rty_immu),
.icpu_adr_i(icpu_adr_immu),
.icpu_err_i(icpu_err_immu),
.icpu_tag_i(icpu_tag_immu),
.immu_uxe(immu_uxe),
.immu_sxe(immu_sxe),
// Connection CPU to external Debug port
.id_void(id_void),
.id_insn(id_insn),
.ex_void(ex_void),
.ex_insn(ex_insn),
.ex_freeze(ex_freeze),
.wb_insn(wb_insn),
.wb_freeze(wb_freeze),
.id_pc(id_pc),
.ex_pc(ex_pc),
.wb_pc(wb_pc),
.branch_op(branch_op),
.rf_dataw(rf_dataw),
.ex_flushpipe(flushpipe),
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_except_trig(du_except_trig),
.du_except_stop(du_except_stop),
.du_dsr(du_dsr),
.du_dmr1(du_dmr1),
.du_hwbkpt(du_hwbkpt),
.du_hwbkpt_ls_r(du_hwbkpt_ls_r),
.du_dat_cpu(du_dat_cpu),
.du_lsu_store_dat(du_lsu_store_dat),
.du_lsu_load_dat(du_lsu_load_dat),
.abort_mvspr(abort_mvspr),
.abort_ex(abort_ex),
// Connection IMMU and CPU internally
.immu_en(immu_en),
// Connection QMEM and CPU
.dc_en(dc_en),
.dcpu_adr_o(dcpu_adr_cpu),
.dcpu_cycstb_o(dcpu_cycstb_cpu),
.dcpu_we_o(dcpu_we_cpu),
.dcpu_sel_o(dcpu_sel_cpu),
.dcpu_tag_o(dcpu_tag_cpu),
.dcpu_dat_o(dcpu_dat_cpu),
.dcpu_dat_i(dcpu_dat_qmem),
.dcpu_ack_i(dcpu_ack_qmem),
.dcpu_rty_i(dcpu_rty_qmem),
.dcpu_err_i(dcpu_err_dmmu),
.dcpu_tag_i(dcpu_tag_dmmu),
.dc_no_writethrough(dc_no_writethrough),
// Connection DMMU and CPU internally
.dmmu_en(dmmu_en),
// SR Interface
.boot_adr_sel_i(boot_adr_sel),
// SB Enable
.sb_en(sb_en),
// Connection PIC and CPU's EXCEPT
.sig_int(sig_int),
.sig_tick(sig_tick),
// SPRs
.supv(supv),
.spr_addr(spr_addr),
.spr_dat_cpu(spr_dat_cpu),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_npc(spr_dat_npc),
.spr_cs(spr_cs),
.spr_we(spr_we),
.mtspr_dc_done(mtspr_dc_done)
);
//
// Instantiation of DMMU
//
or1200_dmmu_top or1200_dmmu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_dmmu_si),
.mbist_so_o(mbist_dmmu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// CPU i/f
.dc_en(dc_en),
.dmmu_en(dmmu_en),
.supv(supv),
.dcpu_adr_i(dcpu_adr_cpu),
.dcpu_cycstb_i(dcpu_cycstb_cpu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_tag_o(dcpu_tag_dmmu),
.dcpu_err_o(dcpu_err_dmmu),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_dmmu),
// QMEM and DMMU
.qmemdmmu_err_i(qmemdmmu_err_qmem),
.qmemdmmu_tag_i(qmemdmmu_tag_qmem),
.qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
);
//
// Instantiation of Data Cache
//
or1200_dc_top or1200_dc_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_dc_si),
.mbist_so_o(mbist_dc_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// DC and QMEM
.dc_en(dc_en),
.dcqmem_adr_i(dcqmem_adr_qmem),
.dcqmem_cycstb_i(dcqmem_cycstb_qmem),
.dcqmem_ci_i(dcqmem_ci_qmem),
.dcqmem_we_i(dcqmem_we_qmem),
.dcqmem_sel_i(dcqmem_sel_qmem),
.dcqmem_tag_i(dcqmem_tag_qmem),
.dcqmem_dat_i(dcqmem_dat_qmem),
.dcqmem_dat_o(dcqmem_dat_dc),
.dcqmem_ack_o(dcqmem_ack_dc),
.dcqmem_rty_o(dcqmem_rty_dc),
.dcqmem_err_o(dcqmem_err_dc),
.dcqmem_tag_o(dcqmem_tag_dc),
.dc_no_writethrough(dc_no_writethrough),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
.spr_addr(spr_addr),
.spr_write(spr_we),
.spr_dat_i(spr_dat_cpu),
.mtspr_dc_done(mtspr_dc_done),
// DC and BIU
.dcsb_dat_o(dcsb_dat_dc),
.dcsb_adr_o(dcsb_adr_dc),
.dcsb_cyc_o(dcsb_cyc_dc),
.dcsb_stb_o(dcsb_stb_dc),
.dcsb_we_o(dcsb_we_dc),
.dcsb_sel_o(dcsb_sel_dc),
.dcsb_cab_o(dcsb_cab_dc),
.dcsb_dat_i(dcsb_dat_sb),
.dcsb_ack_i(dcsb_ack_sb),
.dcsb_err_i(dcsb_err_sb)
);
//
// Instantiation of embedded memory - qmem
//
or1200_qmem_top or1200_qmem_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_qmem_si),
.mbist_so_o(mbist_qmem_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// QMEM and CPU/IMMU
.qmemimmu_adr_i(qmemimmu_adr_immu),
.qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
.qmemimmu_ci_i(qmemimmu_ci_immu),
.qmemicpu_sel_i(icpu_sel_cpu),
.qmemicpu_tag_i(icpu_tag_cpu),
.qmemicpu_dat_o(icpu_dat_qmem),
.qmemicpu_ack_o(icpu_ack_qmem),
.qmemimmu_rty_o(qmemimmu_rty_qmem),
.qmemimmu_err_o(qmemimmu_err_qmem),
.qmemimmu_tag_o(qmemimmu_tag_qmem),
// QMEM and IC
.icqmem_adr_o(icqmem_adr_qmem),
.icqmem_cycstb_o(icqmem_cycstb_qmem),
.icqmem_ci_o(icqmem_ci_qmem),
.icqmem_sel_o(icqmem_sel_qmem),
.icqmem_tag_o(icqmem_tag_qmem),
.icqmem_dat_i(icqmem_dat_ic),
.icqmem_ack_i(icqmem_ack_ic),
.icqmem_rty_i(icqmem_rty_ic),
.icqmem_err_i(icqmem_err_ic),
.icqmem_tag_i(icqmem_tag_ic),
// QMEM and CPU/DMMU
.qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
.qmemdcpu_we_i(dcpu_we_cpu),
.qmemdcpu_sel_i(dcpu_sel_cpu),
.qmemdcpu_tag_i(dcpu_tag_cpu),
.qmemdcpu_dat_i(dcpu_dat_cpu),
.qmemdcpu_dat_o(dcpu_dat_qmem),
.qmemdcpu_ack_o(dcpu_ack_qmem),
.qmemdcpu_rty_o(dcpu_rty_qmem),
.qmemdmmu_err_o(qmemdmmu_err_qmem),
.qmemdmmu_tag_o(qmemdmmu_tag_qmem),
// QMEM and DC
.dcqmem_adr_o(dcqmem_adr_qmem),
.dcqmem_cycstb_o(dcqmem_cycstb_qmem),
.dcqmem_ci_o(dcqmem_ci_qmem),
.dcqmem_we_o(dcqmem_we_qmem),
.dcqmem_sel_o(dcqmem_sel_qmem),
.dcqmem_tag_o(dcqmem_tag_qmem),
.dcqmem_dat_o(dcqmem_dat_qmem),
.dcqmem_dat_i(dcqmem_dat_dc),
.dcqmem_ack_i(dcqmem_ack_dc),
.dcqmem_rty_i(dcqmem_rty_dc),
.dcqmem_err_i(dcqmem_err_dc),
.dcqmem_tag_i(dcqmem_tag_dc)
);
//
// Instantiation of Store Buffer
//
or1200_sb or1200_sb(
// RISC clock, reset
.clk(clk_i),
.rst(rst_i),
// Internal RISC bus (SB)
.sb_en(sb_en),
// Internal RISC bus (DC<->SB)
.dcsb_dat_i(dcsb_dat_dc),
.dcsb_adr_i(dcsb_adr_dc),
.dcsb_cyc_i(dcsb_cyc_dc),
.dcsb_stb_i(dcsb_stb_dc),
.dcsb_we_i(dcsb_we_dc),
.dcsb_sel_i(dcsb_sel_dc),
.dcsb_cab_i(dcsb_cab_dc),
.dcsb_dat_o(dcsb_dat_sb),
.dcsb_ack_o(dcsb_ack_sb),
.dcsb_err_o(dcsb_err_sb),
// SB and BIU
.sbbiu_dat_o(sbbiu_dat_sb),
.sbbiu_adr_o(sbbiu_adr_sb),
.sbbiu_cyc_o(sbbiu_cyc_sb),
.sbbiu_stb_o(sbbiu_stb_sb),
.sbbiu_we_o(sbbiu_we_sb),
.sbbiu_sel_o(sbbiu_sel_sb),
.sbbiu_cab_o(sbbiu_cab_sb),
.sbbiu_dat_i(sbbiu_dat_biu),
.sbbiu_ack_i(sbbiu_ack_biu),
.sbbiu_err_i(sbbiu_err_biu)
);
//
// Instantiation of Debug Unit
//
or1200_du or1200_du(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.dcpu_cycstb_i(dcpu_cycstb_cpu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_adr_i(dcpu_adr_cpu),
.dcpu_dat_lsu(dcpu_dat_cpu),
.dcpu_dat_dc(dcpu_dat_qmem),
.icpu_cycstb_i(icpu_cycstb_cpu),
.ex_freeze(ex_freeze),
.branch_op(branch_op),
.ex_insn(ex_insn),
.id_pc(id_pc),
.du_dsr(du_dsr),
.du_dmr1(du_dmr1),
// For Trace buffer
.spr_dat_npc(spr_dat_npc),
.rf_dataw(rf_dataw),
// DU's access to SPR unit
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_i(du_dat_cpu),
.du_dat_o(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_except_stop(du_except_stop),
.du_hwbkpt(du_hwbkpt),
// Access to DU's SPRs
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_du),
// External Debug Interface
.dbg_stall_i(dbg_stall_i),
.dbg_ewt_i(dbg_ewt_i),
.dbg_lss_o(dbg_lss_o),
.dbg_is_o(dbg_is_o),
.dbg_wp_o(dbg_wp_o),
.dbg_bp_o(dbg_bp_o),
.dbg_stb_i(dbg_stb_i),
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.dbg_dat_o(dbg_dat_o),
.dbg_ack_o(dbg_ack_o)
);
//
// Programmable interrupt controller
//
or1200_pic or1200_pic(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pic),
.pic_wakeup(pic_wakeup),
.intr(sig_int),
// PIC Interface
.pic_int(pic_ints_i)
);
//
// Instantiation of Tick timer
//
or1200_tt or1200_tt(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.du_stall(du_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_tt),
.intr(sig_tick)
);
//
// Instantiation of Power Management
//
or1200_pm or1200_pm(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.pic_wakeup(pic_wakeup),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pm),
// Power Management Interface
.pm_cpustall(pm_cpustall_i),
.pm_clksd(pm_clksd_o),
.pm_dc_gate(pm_dc_gate_o),
.pm_ic_gate(pm_ic_gate_o),
.pm_dmmu_gate(pm_dmmu_gate_o),
.pm_immu_gate(pm_immu_gate_o),
.pm_tt_gate(pm_tt_gate_o),
.pm_cpu_gate(pm_cpu_gate_o),
.pm_wakeup(pm_wakeup_o),
.pm_lvolt(pm_lvolt_o)
);
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(**************************************************************)
(* MSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable DecidableTypeEx MSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecideOn (E : DecidableType)(Import M : WSetsOn E).
Module F := MSetFacts.WFactsOn E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the MSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module MSetLogicalFacts.
Require Export Decidable.
Require Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End MSetLogicalFacts.
Import MSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module MSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
(** [if t then t1 else t2] executes [t] and, if it does not
fail, then [t1] will be applied to all subgoals
produced. If [t] fails, then [t2] is executed. *)
Tactic Notation
"if" tactic(t)
"then" tactic(t1)
"else" tactic(t2) :=
first [ t; first [ t1 | fail 2 ] | t2 ].
Ltac abstract_term t :=
if (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-MSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive MSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
MSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
MSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
MSet_elt_Prop (In x s)
| True_elt_prop :
MSet_elt_Prop True
| False_elt_prop :
MSet_elt_Prop False
| conj_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
MSet_elt_Prop P ->
MSet_elt_Prop (~ P).
Inductive MSet_Prop : Prop -> Prop :=
| elt_MSet_Prop : forall P,
MSet_elt_Prop P ->
MSet_Prop P
| Empty_MSet_Prop : forall s,
MSet_Prop (Empty s)
| Subset_MSet_Prop : forall s1 s2,
MSet_Prop (Subset s1 s2)
| Equal_MSet_Prop : forall s1 s2,
MSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors MSet_elt_Prop MSet_Prop : MSet_Prop.
Ltac discard_nonMSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
if (change T with E.t in H) then fail
else if (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
if prop (MSet_Prop P) holds by
(auto 100 with MSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [MSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of MSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [MSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : MSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substMSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_MSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substMSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_MSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using MSet_decidability;
substMSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End MSetDecideAuxiliary.
Import MSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonMSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonMSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [MSet_elt_Prop], noting
that any [MSet_elt_Prop] is decidable. *)
pull not using MSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
if prop (MSet_elt_Prop P) holds by
(auto 100 with MSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module MSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End MSetDecideTestCases.
End WDecideOn.
Require Import MSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WSets) := !WDecideOn M.E M.
Module Decide := WDecide.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_PP_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_PP_V |
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_phinc_rom(
// input clk,
input [9:0] keycode,
output reg [11:0] phinc
);
always @(*) begin : read_lut
case( keycode )
10'd0: phinc = { 12'd1299 }; // nota = 0, KF = 0
10'd1: phinc = { 12'd1300 }; // nota = 0, KF = 1
10'd2: phinc = { 12'd1301 }; // nota = 0, KF = 2
10'd3: phinc = { 12'd1302 }; // nota = 0, KF = 3
10'd4: phinc = { 12'd1303 }; // nota = 0, KF = 4
10'd5: phinc = { 12'd1304 }; // nota = 0, KF = 5
10'd6: phinc = { 12'd1305 }; // nota = 0, KF = 6
10'd7: phinc = { 12'd1306 }; // nota = 0, KF = 7
10'd8: phinc = { 12'd1308 }; // nota = 0, KF = 8
10'd9: phinc = { 12'd1309 }; // nota = 0, KF = 9
10'd10: phinc = { 12'd1310 }; // nota = 0, KF = 10
10'd11: phinc = { 12'd1311 }; // nota = 0, KF = 11
10'd12: phinc = { 12'd1313 }; // nota = 0, KF = 12
10'd13: phinc = { 12'd1314 }; // nota = 0, KF = 13
10'd14: phinc = { 12'd1315 }; // nota = 0, KF = 14
10'd15: phinc = { 12'd1316 }; // nota = 0, KF = 15
10'd16: phinc = { 12'd1318 }; // nota = 0, KF = 16
10'd17: phinc = { 12'd1319 }; // nota = 0, KF = 17
10'd18: phinc = { 12'd1320 }; // nota = 0, KF = 18
10'd19: phinc = { 12'd1321 }; // nota = 0, KF = 19
10'd20: phinc = { 12'd1322 }; // nota = 0, KF = 20
10'd21: phinc = { 12'd1323 }; // nota = 0, KF = 21
10'd22: phinc = { 12'd1324 }; // nota = 0, KF = 22
10'd23: phinc = { 12'd1325 }; // nota = 0, KF = 23
10'd24: phinc = { 12'd1327 }; // nota = 0, KF = 24
10'd25: phinc = { 12'd1328 }; // nota = 0, KF = 25
10'd26: phinc = { 12'd1329 }; // nota = 0, KF = 26
10'd27: phinc = { 12'd1330 }; // nota = 0, KF = 27
10'd28: phinc = { 12'd1332 }; // nota = 0, KF = 28
10'd29: phinc = { 12'd1333 }; // nota = 0, KF = 29
10'd30: phinc = { 12'd1334 }; // nota = 0, KF = 30
10'd31: phinc = { 12'd1335 }; // nota = 0, KF = 31
10'd32: phinc = { 12'd1337 }; // nota = 0, KF = 32
10'd33: phinc = { 12'd1338 }; // nota = 0, KF = 33
10'd34: phinc = { 12'd1339 }; // nota = 0, KF = 34
10'd35: phinc = { 12'd1340 }; // nota = 0, KF = 35
10'd36: phinc = { 12'd1341 }; // nota = 0, KF = 36
10'd37: phinc = { 12'd1342 }; // nota = 0, KF = 37
10'd38: phinc = { 12'd1343 }; // nota = 0, KF = 38
10'd39: phinc = { 12'd1344 }; // nota = 0, KF = 39
10'd40: phinc = { 12'd1346 }; // nota = 0, KF = 40
10'd41: phinc = { 12'd1347 }; // nota = 0, KF = 41
10'd42: phinc = { 12'd1348 }; // nota = 0, KF = 42
10'd43: phinc = { 12'd1349 }; // nota = 0, KF = 43
10'd44: phinc = { 12'd1351 }; // nota = 0, KF = 44
10'd45: phinc = { 12'd1352 }; // nota = 0, KF = 45
10'd46: phinc = { 12'd1353 }; // nota = 0, KF = 46
10'd47: phinc = { 12'd1354 }; // nota = 0, KF = 47
10'd48: phinc = { 12'd1356 }; // nota = 0, KF = 48
10'd49: phinc = { 12'd1357 }; // nota = 0, KF = 49
10'd50: phinc = { 12'd1358 }; // nota = 0, KF = 50
10'd51: phinc = { 12'd1359 }; // nota = 0, KF = 51
10'd52: phinc = { 12'd1361 }; // nota = 0, KF = 52
10'd53: phinc = { 12'd1362 }; // nota = 0, KF = 53
10'd54: phinc = { 12'd1363 }; // nota = 0, KF = 54
10'd55: phinc = { 12'd1364 }; // nota = 0, KF = 55
10'd56: phinc = { 12'd1366 }; // nota = 0, KF = 56
10'd57: phinc = { 12'd1367 }; // nota = 0, KF = 57
10'd58: phinc = { 12'd1368 }; // nota = 0, KF = 58
10'd59: phinc = { 12'd1369 }; // nota = 0, KF = 59
10'd60: phinc = { 12'd1371 }; // nota = 0, KF = 60
10'd61: phinc = { 12'd1372 }; // nota = 0, KF = 61
10'd62: phinc = { 12'd1373 }; // nota = 0, KF = 62
10'd63: phinc = { 12'd1374 }; // nota = 0, KF = 63
10'd64: phinc = { 12'd1376 }; // nota = 1, KF = 0
10'd65: phinc = { 12'd1377 }; // nota = 1, KF = 1
10'd66: phinc = { 12'd1378 }; // nota = 1, KF = 2
10'd67: phinc = { 12'd1379 }; // nota = 1, KF = 3
10'd68: phinc = { 12'd1381 }; // nota = 1, KF = 4
10'd69: phinc = { 12'd1382 }; // nota = 1, KF = 5
10'd70: phinc = { 12'd1383 }; // nota = 1, KF = 6
10'd71: phinc = { 12'd1384 }; // nota = 1, KF = 7
10'd72: phinc = { 12'd1386 }; // nota = 1, KF = 8
10'd73: phinc = { 12'd1387 }; // nota = 1, KF = 9
10'd74: phinc = { 12'd1388 }; // nota = 1, KF = 10
10'd75: phinc = { 12'd1389 }; // nota = 1, KF = 11
10'd76: phinc = { 12'd1391 }; // nota = 1, KF = 12
10'd77: phinc = { 12'd1392 }; // nota = 1, KF = 13
10'd78: phinc = { 12'd1393 }; // nota = 1, KF = 14
10'd79: phinc = { 12'd1394 }; // nota = 1, KF = 15
10'd80: phinc = { 12'd1396 }; // nota = 1, KF = 16
10'd81: phinc = { 12'd1397 }; // nota = 1, KF = 17
10'd82: phinc = { 12'd1398 }; // nota = 1, KF = 18
10'd83: phinc = { 12'd1399 }; // nota = 1, KF = 19
10'd84: phinc = { 12'd1401 }; // nota = 1, KF = 20
10'd85: phinc = { 12'd1402 }; // nota = 1, KF = 21
10'd86: phinc = { 12'd1403 }; // nota = 1, KF = 22
10'd87: phinc = { 12'd1404 }; // nota = 1, KF = 23
10'd88: phinc = { 12'd1406 }; // nota = 1, KF = 24
10'd89: phinc = { 12'd1407 }; // nota = 1, KF = 25
10'd90: phinc = { 12'd1408 }; // nota = 1, KF = 26
10'd91: phinc = { 12'd1409 }; // nota = 1, KF = 27
10'd92: phinc = { 12'd1411 }; // nota = 1, KF = 28
10'd93: phinc = { 12'd1412 }; // nota = 1, KF = 29
10'd94: phinc = { 12'd1413 }; // nota = 1, KF = 30
10'd95: phinc = { 12'd1414 }; // nota = 1, KF = 31
10'd96: phinc = { 12'd1416 }; // nota = 1, KF = 32
10'd97: phinc = { 12'd1417 }; // nota = 1, KF = 33
10'd98: phinc = { 12'd1418 }; // nota = 1, KF = 34
10'd99: phinc = { 12'd1419 }; // nota = 1, KF = 35
10'd100: phinc = { 12'd1421 }; // nota = 1, KF = 36
10'd101: phinc = { 12'd1422 }; // nota = 1, KF = 37
10'd102: phinc = { 12'd1423 }; // nota = 1, KF = 38
10'd103: phinc = { 12'd1424 }; // nota = 1, KF = 39
10'd104: phinc = { 12'd1426 }; // nota = 1, KF = 40
10'd105: phinc = { 12'd1427 }; // nota = 1, KF = 41
10'd106: phinc = { 12'd1429 }; // nota = 1, KF = 42
10'd107: phinc = { 12'd1430 }; // nota = 1, KF = 43
10'd108: phinc = { 12'd1431 }; // nota = 1, KF = 44
10'd109: phinc = { 12'd1432 }; // nota = 1, KF = 45
10'd110: phinc = { 12'd1434 }; // nota = 1, KF = 46
10'd111: phinc = { 12'd1435 }; // nota = 1, KF = 47
10'd112: phinc = { 12'd1437 }; // nota = 1, KF = 48
10'd113: phinc = { 12'd1438 }; // nota = 1, KF = 49
10'd114: phinc = { 12'd1439 }; // nota = 1, KF = 50
10'd115: phinc = { 12'd1440 }; // nota = 1, KF = 51
10'd116: phinc = { 12'd1442 }; // nota = 1, KF = 52
10'd117: phinc = { 12'd1443 }; // nota = 1, KF = 53
10'd118: phinc = { 12'd1444 }; // nota = 1, KF = 54
10'd119: phinc = { 12'd1445 }; // nota = 1, KF = 55
10'd120: phinc = { 12'd1447 }; // nota = 1, KF = 56
10'd121: phinc = { 12'd1448 }; // nota = 1, KF = 57
10'd122: phinc = { 12'd1449 }; // nota = 1, KF = 58
10'd123: phinc = { 12'd1450 }; // nota = 1, KF = 59
10'd124: phinc = { 12'd1452 }; // nota = 1, KF = 60
10'd125: phinc = { 12'd1453 }; // nota = 1, KF = 61
10'd126: phinc = { 12'd1454 }; // nota = 1, KF = 62
10'd127: phinc = { 12'd1455 }; // nota = 1, KF = 63
10'd128: phinc = { 12'd1458 }; // nota = 2, KF = 0
10'd129: phinc = { 12'd1459 }; // nota = 2, KF = 1
10'd130: phinc = { 12'd1460 }; // nota = 2, KF = 2
10'd131: phinc = { 12'd1461 }; // nota = 2, KF = 3
10'd132: phinc = { 12'd1463 }; // nota = 2, KF = 4
10'd133: phinc = { 12'd1464 }; // nota = 2, KF = 5
10'd134: phinc = { 12'd1465 }; // nota = 2, KF = 6
10'd135: phinc = { 12'd1466 }; // nota = 2, KF = 7
10'd136: phinc = { 12'd1468 }; // nota = 2, KF = 8
10'd137: phinc = { 12'd1469 }; // nota = 2, KF = 9
10'd138: phinc = { 12'd1471 }; // nota = 2, KF = 10
10'd139: phinc = { 12'd1472 }; // nota = 2, KF = 11
10'd140: phinc = { 12'd1473 }; // nota = 2, KF = 12
10'd141: phinc = { 12'd1474 }; // nota = 2, KF = 13
10'd142: phinc = { 12'd1476 }; // nota = 2, KF = 14
10'd143: phinc = { 12'd1477 }; // nota = 2, KF = 15
10'd144: phinc = { 12'd1479 }; // nota = 2, KF = 16
10'd145: phinc = { 12'd1480 }; // nota = 2, KF = 17
10'd146: phinc = { 12'd1481 }; // nota = 2, KF = 18
10'd147: phinc = { 12'd1482 }; // nota = 2, KF = 19
10'd148: phinc = { 12'd1484 }; // nota = 2, KF = 20
10'd149: phinc = { 12'd1485 }; // nota = 2, KF = 21
10'd150: phinc = { 12'd1486 }; // nota = 2, KF = 22
10'd151: phinc = { 12'd1487 }; // nota = 2, KF = 23
10'd152: phinc = { 12'd1489 }; // nota = 2, KF = 24
10'd153: phinc = { 12'd1490 }; // nota = 2, KF = 25
10'd154: phinc = { 12'd1492 }; // nota = 2, KF = 26
10'd155: phinc = { 12'd1493 }; // nota = 2, KF = 27
10'd156: phinc = { 12'd1494 }; // nota = 2, KF = 28
10'd157: phinc = { 12'd1495 }; // nota = 2, KF = 29
10'd158: phinc = { 12'd1497 }; // nota = 2, KF = 30
10'd159: phinc = { 12'd1498 }; // nota = 2, KF = 31
10'd160: phinc = { 12'd1501 }; // nota = 2, KF = 32
10'd161: phinc = { 12'd1502 }; // nota = 2, KF = 33
10'd162: phinc = { 12'd1503 }; // nota = 2, KF = 34
10'd163: phinc = { 12'd1504 }; // nota = 2, KF = 35
10'd164: phinc = { 12'd1506 }; // nota = 2, KF = 36
10'd165: phinc = { 12'd1507 }; // nota = 2, KF = 37
10'd166: phinc = { 12'd1509 }; // nota = 2, KF = 38
10'd167: phinc = { 12'd1510 }; // nota = 2, KF = 39
10'd168: phinc = { 12'd1512 }; // nota = 2, KF = 40
10'd169: phinc = { 12'd1513 }; // nota = 2, KF = 41
10'd170: phinc = { 12'd1514 }; // nota = 2, KF = 42
10'd171: phinc = { 12'd1515 }; // nota = 2, KF = 43
10'd172: phinc = { 12'd1517 }; // nota = 2, KF = 44
10'd173: phinc = { 12'd1518 }; // nota = 2, KF = 45
10'd174: phinc = { 12'd1520 }; // nota = 2, KF = 46
10'd175: phinc = { 12'd1521 }; // nota = 2, KF = 47
10'd176: phinc = { 12'd1523 }; // nota = 2, KF = 48
10'd177: phinc = { 12'd1524 }; // nota = 2, KF = 49
10'd178: phinc = { 12'd1525 }; // nota = 2, KF = 50
10'd179: phinc = { 12'd1526 }; // nota = 2, KF = 51
10'd180: phinc = { 12'd1528 }; // nota = 2, KF = 52
10'd181: phinc = { 12'd1529 }; // nota = 2, KF = 53
10'd182: phinc = { 12'd1531 }; // nota = 2, KF = 54
10'd183: phinc = { 12'd1532 }; // nota = 2, KF = 55
10'd184: phinc = { 12'd1534 }; // nota = 2, KF = 56
10'd185: phinc = { 12'd1535 }; // nota = 2, KF = 57
10'd186: phinc = { 12'd1536 }; // nota = 2, KF = 58
10'd187: phinc = { 12'd1537 }; // nota = 2, KF = 59
10'd188: phinc = { 12'd1539 }; // nota = 2, KF = 60
10'd189: phinc = { 12'd1540 }; // nota = 2, KF = 61
10'd190: phinc = { 12'd1542 }; // nota = 2, KF = 62
10'd191: phinc = { 12'd1543 }; // nota = 2, KF = 63
10'd192: phinc = { 12'd1458 }; // nota = 3, KF = 0
10'd193: phinc = { 12'd1459 }; // nota = 3, KF = 1
10'd194: phinc = { 12'd1460 }; // nota = 3, KF = 2
10'd195: phinc = { 12'd1461 }; // nota = 3, KF = 3
10'd196: phinc = { 12'd1463 }; // nota = 3, KF = 4
10'd197: phinc = { 12'd1464 }; // nota = 3, KF = 5
10'd198: phinc = { 12'd1465 }; // nota = 3, KF = 6
10'd199: phinc = { 12'd1466 }; // nota = 3, KF = 7
10'd200: phinc = { 12'd1468 }; // nota = 3, KF = 8
10'd201: phinc = { 12'd1469 }; // nota = 3, KF = 9
10'd202: phinc = { 12'd1471 }; // nota = 3, KF = 10
10'd203: phinc = { 12'd1472 }; // nota = 3, KF = 11
10'd204: phinc = { 12'd1473 }; // nota = 3, KF = 12
10'd205: phinc = { 12'd1474 }; // nota = 3, KF = 13
10'd206: phinc = { 12'd1476 }; // nota = 3, KF = 14
10'd207: phinc = { 12'd1477 }; // nota = 3, KF = 15
10'd208: phinc = { 12'd1479 }; // nota = 3, KF = 16
10'd209: phinc = { 12'd1480 }; // nota = 3, KF = 17
10'd210: phinc = { 12'd1481 }; // nota = 3, KF = 18
10'd211: phinc = { 12'd1482 }; // nota = 3, KF = 19
10'd212: phinc = { 12'd1484 }; // nota = 3, KF = 20
10'd213: phinc = { 12'd1485 }; // nota = 3, KF = 21
10'd214: phinc = { 12'd1486 }; // nota = 3, KF = 22
10'd215: phinc = { 12'd1487 }; // nota = 3, KF = 23
10'd216: phinc = { 12'd1489 }; // nota = 3, KF = 24
10'd217: phinc = { 12'd1490 }; // nota = 3, KF = 25
10'd218: phinc = { 12'd1492 }; // nota = 3, KF = 26
10'd219: phinc = { 12'd1493 }; // nota = 3, KF = 27
10'd220: phinc = { 12'd1494 }; // nota = 3, KF = 28
10'd221: phinc = { 12'd1495 }; // nota = 3, KF = 29
10'd222: phinc = { 12'd1497 }; // nota = 3, KF = 30
10'd223: phinc = { 12'd1498 }; // nota = 3, KF = 31
10'd224: phinc = { 12'd1501 }; // nota = 3, KF = 32
10'd225: phinc = { 12'd1502 }; // nota = 3, KF = 33
10'd226: phinc = { 12'd1503 }; // nota = 3, KF = 34
10'd227: phinc = { 12'd1504 }; // nota = 3, KF = 35
10'd228: phinc = { 12'd1506 }; // nota = 3, KF = 36
10'd229: phinc = { 12'd1507 }; // nota = 3, KF = 37
10'd230: phinc = { 12'd1509 }; // nota = 3, KF = 38
10'd231: phinc = { 12'd1510 }; // nota = 3, KF = 39
10'd232: phinc = { 12'd1512 }; // nota = 3, KF = 40
10'd233: phinc = { 12'd1513 }; // nota = 3, KF = 41
10'd234: phinc = { 12'd1514 }; // nota = 3, KF = 42
10'd235: phinc = { 12'd1515 }; // nota = 3, KF = 43
10'd236: phinc = { 12'd1517 }; // nota = 3, KF = 44
10'd237: phinc = { 12'd1518 }; // nota = 3, KF = 45
10'd238: phinc = { 12'd1520 }; // nota = 3, KF = 46
10'd239: phinc = { 12'd1521 }; // nota = 3, KF = 47
10'd240: phinc = { 12'd1523 }; // nota = 3, KF = 48
10'd241: phinc = { 12'd1524 }; // nota = 3, KF = 49
10'd242: phinc = { 12'd1525 }; // nota = 3, KF = 50
10'd243: phinc = { 12'd1526 }; // nota = 3, KF = 51
10'd244: phinc = { 12'd1528 }; // nota = 3, KF = 52
10'd245: phinc = { 12'd1529 }; // nota = 3, KF = 53
10'd246: phinc = { 12'd1531 }; // nota = 3, KF = 54
10'd247: phinc = { 12'd1532 }; // nota = 3, KF = 55
10'd248: phinc = { 12'd1534 }; // nota = 3, KF = 56
10'd249: phinc = { 12'd1535 }; // nota = 3, KF = 57
10'd250: phinc = { 12'd1536 }; // nota = 3, KF = 58
10'd251: phinc = { 12'd1537 }; // nota = 3, KF = 59
10'd252: phinc = { 12'd1539 }; // nota = 3, KF = 60
10'd253: phinc = { 12'd1540 }; // nota = 3, KF = 61
10'd254: phinc = { 12'd1542 }; // nota = 3, KF = 62
10'd255: phinc = { 12'd1543 }; // nota = 3, KF = 63
10'd256: phinc = { 12'd1545 }; // nota = 4, KF = 0
10'd257: phinc = { 12'd1546 }; // nota = 4, KF = 1
10'd258: phinc = { 12'd1547 }; // nota = 4, KF = 2
10'd259: phinc = { 12'd1548 }; // nota = 4, KF = 3
10'd260: phinc = { 12'd1550 }; // nota = 4, KF = 4
10'd261: phinc = { 12'd1551 }; // nota = 4, KF = 5
10'd262: phinc = { 12'd1553 }; // nota = 4, KF = 6
10'd263: phinc = { 12'd1554 }; // nota = 4, KF = 7
10'd264: phinc = { 12'd1556 }; // nota = 4, KF = 8
10'd265: phinc = { 12'd1557 }; // nota = 4, KF = 9
10'd266: phinc = { 12'd1558 }; // nota = 4, KF = 10
10'd267: phinc = { 12'd1559 }; // nota = 4, KF = 11
10'd268: phinc = { 12'd1561 }; // nota = 4, KF = 12
10'd269: phinc = { 12'd1562 }; // nota = 4, KF = 13
10'd270: phinc = { 12'd1564 }; // nota = 4, KF = 14
10'd271: phinc = { 12'd1565 }; // nota = 4, KF = 15
10'd272: phinc = { 12'd1567 }; // nota = 4, KF = 16
10'd273: phinc = { 12'd1568 }; // nota = 4, KF = 17
10'd274: phinc = { 12'd1569 }; // nota = 4, KF = 18
10'd275: phinc = { 12'd1570 }; // nota = 4, KF = 19
10'd276: phinc = { 12'd1572 }; // nota = 4, KF = 20
10'd277: phinc = { 12'd1573 }; // nota = 4, KF = 21
10'd278: phinc = { 12'd1575 }; // nota = 4, KF = 22
10'd279: phinc = { 12'd1576 }; // nota = 4, KF = 23
10'd280: phinc = { 12'd1578 }; // nota = 4, KF = 24
10'd281: phinc = { 12'd1579 }; // nota = 4, KF = 25
10'd282: phinc = { 12'd1580 }; // nota = 4, KF = 26
10'd283: phinc = { 12'd1581 }; // nota = 4, KF = 27
10'd284: phinc = { 12'd1583 }; // nota = 4, KF = 28
10'd285: phinc = { 12'd1584 }; // nota = 4, KF = 29
10'd286: phinc = { 12'd1586 }; // nota = 4, KF = 30
10'd287: phinc = { 12'd1587 }; // nota = 4, KF = 31
10'd288: phinc = { 12'd1590 }; // nota = 4, KF = 32
10'd289: phinc = { 12'd1591 }; // nota = 4, KF = 33
10'd290: phinc = { 12'd1592 }; // nota = 4, KF = 34
10'd291: phinc = { 12'd1593 }; // nota = 4, KF = 35
10'd292: phinc = { 12'd1595 }; // nota = 4, KF = 36
10'd293: phinc = { 12'd1596 }; // nota = 4, KF = 37
10'd294: phinc = { 12'd1598 }; // nota = 4, KF = 38
10'd295: phinc = { 12'd1599 }; // nota = 4, KF = 39
10'd296: phinc = { 12'd1601 }; // nota = 4, KF = 40
10'd297: phinc = { 12'd1602 }; // nota = 4, KF = 41
10'd298: phinc = { 12'd1604 }; // nota = 4, KF = 42
10'd299: phinc = { 12'd1605 }; // nota = 4, KF = 43
10'd300: phinc = { 12'd1607 }; // nota = 4, KF = 44
10'd301: phinc = { 12'd1608 }; // nota = 4, KF = 45
10'd302: phinc = { 12'd1609 }; // nota = 4, KF = 46
10'd303: phinc = { 12'd1610 }; // nota = 4, KF = 47
10'd304: phinc = { 12'd1613 }; // nota = 4, KF = 48
10'd305: phinc = { 12'd1614 }; // nota = 4, KF = 49
10'd306: phinc = { 12'd1615 }; // nota = 4, KF = 50
10'd307: phinc = { 12'd1616 }; // nota = 4, KF = 51
10'd308: phinc = { 12'd1618 }; // nota = 4, KF = 52
10'd309: phinc = { 12'd1619 }; // nota = 4, KF = 53
10'd310: phinc = { 12'd1621 }; // nota = 4, KF = 54
10'd311: phinc = { 12'd1622 }; // nota = 4, KF = 55
10'd312: phinc = { 12'd1624 }; // nota = 4, KF = 56
10'd313: phinc = { 12'd1625 }; // nota = 4, KF = 57
10'd314: phinc = { 12'd1627 }; // nota = 4, KF = 58
10'd315: phinc = { 12'd1628 }; // nota = 4, KF = 59
10'd316: phinc = { 12'd1630 }; // nota = 4, KF = 60
10'd317: phinc = { 12'd1631 }; // nota = 4, KF = 61
10'd318: phinc = { 12'd1632 }; // nota = 4, KF = 62
10'd319: phinc = { 12'd1633 }; // nota = 4, KF = 63
10'd320: phinc = { 12'd1637 }; // nota = 5, KF = 0
10'd321: phinc = { 12'd1638 }; // nota = 5, KF = 1
10'd322: phinc = { 12'd1639 }; // nota = 5, KF = 2
10'd323: phinc = { 12'd1640 }; // nota = 5, KF = 3
10'd324: phinc = { 12'd1642 }; // nota = 5, KF = 4
10'd325: phinc = { 12'd1643 }; // nota = 5, KF = 5
10'd326: phinc = { 12'd1645 }; // nota = 5, KF = 6
10'd327: phinc = { 12'd1646 }; // nota = 5, KF = 7
10'd328: phinc = { 12'd1648 }; // nota = 5, KF = 8
10'd329: phinc = { 12'd1649 }; // nota = 5, KF = 9
10'd330: phinc = { 12'd1651 }; // nota = 5, KF = 10
10'd331: phinc = { 12'd1652 }; // nota = 5, KF = 11
10'd332: phinc = { 12'd1654 }; // nota = 5, KF = 12
10'd333: phinc = { 12'd1655 }; // nota = 5, KF = 13
10'd334: phinc = { 12'd1656 }; // nota = 5, KF = 14
10'd335: phinc = { 12'd1657 }; // nota = 5, KF = 15
10'd336: phinc = { 12'd1660 }; // nota = 5, KF = 16
10'd337: phinc = { 12'd1661 }; // nota = 5, KF = 17
10'd338: phinc = { 12'd1663 }; // nota = 5, KF = 18
10'd339: phinc = { 12'd1664 }; // nota = 5, KF = 19
10'd340: phinc = { 12'd1666 }; // nota = 5, KF = 20
10'd341: phinc = { 12'd1667 }; // nota = 5, KF = 21
10'd342: phinc = { 12'd1669 }; // nota = 5, KF = 22
10'd343: phinc = { 12'd1670 }; // nota = 5, KF = 23
10'd344: phinc = { 12'd1672 }; // nota = 5, KF = 24
10'd345: phinc = { 12'd1673 }; // nota = 5, KF = 25
10'd346: phinc = { 12'd1675 }; // nota = 5, KF = 26
10'd347: phinc = { 12'd1676 }; // nota = 5, KF = 27
10'd348: phinc = { 12'd1678 }; // nota = 5, KF = 28
10'd349: phinc = { 12'd1679 }; // nota = 5, KF = 29
10'd350: phinc = { 12'd1681 }; // nota = 5, KF = 30
10'd351: phinc = { 12'd1682 }; // nota = 5, KF = 31
10'd352: phinc = { 12'd1685 }; // nota = 5, KF = 32
10'd353: phinc = { 12'd1686 }; // nota = 5, KF = 33
10'd354: phinc = { 12'd1688 }; // nota = 5, KF = 34
10'd355: phinc = { 12'd1689 }; // nota = 5, KF = 35
10'd356: phinc = { 12'd1691 }; // nota = 5, KF = 36
10'd357: phinc = { 12'd1692 }; // nota = 5, KF = 37
10'd358: phinc = { 12'd1694 }; // nota = 5, KF = 38
10'd359: phinc = { 12'd1695 }; // nota = 5, KF = 39
10'd360: phinc = { 12'd1697 }; // nota = 5, KF = 40
10'd361: phinc = { 12'd1698 }; // nota = 5, KF = 41
10'd362: phinc = { 12'd1700 }; // nota = 5, KF = 42
10'd363: phinc = { 12'd1701 }; // nota = 5, KF = 43
10'd364: phinc = { 12'd1703 }; // nota = 5, KF = 44
10'd365: phinc = { 12'd1704 }; // nota = 5, KF = 45
10'd366: phinc = { 12'd1706 }; // nota = 5, KF = 46
10'd367: phinc = { 12'd1707 }; // nota = 5, KF = 47
10'd368: phinc = { 12'd1709 }; // nota = 5, KF = 48
10'd369: phinc = { 12'd1710 }; // nota = 5, KF = 49
10'd370: phinc = { 12'd1712 }; // nota = 5, KF = 50
10'd371: phinc = { 12'd1713 }; // nota = 5, KF = 51
10'd372: phinc = { 12'd1715 }; // nota = 5, KF = 52
10'd373: phinc = { 12'd1716 }; // nota = 5, KF = 53
10'd374: phinc = { 12'd1718 }; // nota = 5, KF = 54
10'd375: phinc = { 12'd1719 }; // nota = 5, KF = 55
10'd376: phinc = { 12'd1721 }; // nota = 5, KF = 56
10'd377: phinc = { 12'd1722 }; // nota = 5, KF = 57
10'd378: phinc = { 12'd1724 }; // nota = 5, KF = 58
10'd379: phinc = { 12'd1725 }; // nota = 5, KF = 59
10'd380: phinc = { 12'd1727 }; // nota = 5, KF = 60
10'd381: phinc = { 12'd1728 }; // nota = 5, KF = 61
10'd382: phinc = { 12'd1730 }; // nota = 5, KF = 62
10'd383: phinc = { 12'd1731 }; // nota = 5, KF = 63
10'd384: phinc = { 12'd1734 }; // nota = 6, KF = 0
10'd385: phinc = { 12'd1735 }; // nota = 6, KF = 1
10'd386: phinc = { 12'd1737 }; // nota = 6, KF = 2
10'd387: phinc = { 12'd1738 }; // nota = 6, KF = 3
10'd388: phinc = { 12'd1740 }; // nota = 6, KF = 4
10'd389: phinc = { 12'd1741 }; // nota = 6, KF = 5
10'd390: phinc = { 12'd1743 }; // nota = 6, KF = 6
10'd391: phinc = { 12'd1744 }; // nota = 6, KF = 7
10'd392: phinc = { 12'd1746 }; // nota = 6, KF = 8
10'd393: phinc = { 12'd1748 }; // nota = 6, KF = 9
10'd394: phinc = { 12'd1749 }; // nota = 6, KF = 10
10'd395: phinc = { 12'd1751 }; // nota = 6, KF = 11
10'd396: phinc = { 12'd1752 }; // nota = 6, KF = 12
10'd397: phinc = { 12'd1754 }; // nota = 6, KF = 13
10'd398: phinc = { 12'd1755 }; // nota = 6, KF = 14
10'd399: phinc = { 12'd1757 }; // nota = 6, KF = 15
10'd400: phinc = { 12'd1759 }; // nota = 6, KF = 16
10'd401: phinc = { 12'd1760 }; // nota = 6, KF = 17
10'd402: phinc = { 12'd1762 }; // nota = 6, KF = 18
10'd403: phinc = { 12'd1763 }; // nota = 6, KF = 19
10'd404: phinc = { 12'd1765 }; // nota = 6, KF = 20
10'd405: phinc = { 12'd1766 }; // nota = 6, KF = 21
10'd406: phinc = { 12'd1768 }; // nota = 6, KF = 22
10'd407: phinc = { 12'd1769 }; // nota = 6, KF = 23
10'd408: phinc = { 12'd1771 }; // nota = 6, KF = 24
10'd409: phinc = { 12'd1773 }; // nota = 6, KF = 25
10'd410: phinc = { 12'd1774 }; // nota = 6, KF = 26
10'd411: phinc = { 12'd1776 }; // nota = 6, KF = 27
10'd412: phinc = { 12'd1777 }; // nota = 6, KF = 28
10'd413: phinc = { 12'd1779 }; // nota = 6, KF = 29
10'd414: phinc = { 12'd1780 }; // nota = 6, KF = 30
10'd415: phinc = { 12'd1782 }; // nota = 6, KF = 31
10'd416: phinc = { 12'd1785 }; // nota = 6, KF = 32
10'd417: phinc = { 12'd1786 }; // nota = 6, KF = 33
10'd418: phinc = { 12'd1788 }; // nota = 6, KF = 34
10'd419: phinc = { 12'd1789 }; // nota = 6, KF = 35
10'd420: phinc = { 12'd1791 }; // nota = 6, KF = 36
10'd421: phinc = { 12'd1793 }; // nota = 6, KF = 37
10'd422: phinc = { 12'd1794 }; // nota = 6, KF = 38
10'd423: phinc = { 12'd1796 }; // nota = 6, KF = 39
10'd424: phinc = { 12'd1798 }; // nota = 6, KF = 40
10'd425: phinc = { 12'd1799 }; // nota = 6, KF = 41
10'd426: phinc = { 12'd1801 }; // nota = 6, KF = 42
10'd427: phinc = { 12'd1802 }; // nota = 6, KF = 43
10'd428: phinc = { 12'd1804 }; // nota = 6, KF = 44
10'd429: phinc = { 12'd1806 }; // nota = 6, KF = 45
10'd430: phinc = { 12'd1807 }; // nota = 6, KF = 46
10'd431: phinc = { 12'd1809 }; // nota = 6, KF = 47
10'd432: phinc = { 12'd1811 }; // nota = 6, KF = 48
10'd433: phinc = { 12'd1812 }; // nota = 6, KF = 49
10'd434: phinc = { 12'd1814 }; // nota = 6, KF = 50
10'd435: phinc = { 12'd1815 }; // nota = 6, KF = 51
10'd436: phinc = { 12'd1817 }; // nota = 6, KF = 52
10'd437: phinc = { 12'd1819 }; // nota = 6, KF = 53
10'd438: phinc = { 12'd1820 }; // nota = 6, KF = 54
10'd439: phinc = { 12'd1822 }; // nota = 6, KF = 55
10'd440: phinc = { 12'd1824 }; // nota = 6, KF = 56
10'd441: phinc = { 12'd1825 }; // nota = 6, KF = 57
10'd442: phinc = { 12'd1827 }; // nota = 6, KF = 58
10'd443: phinc = { 12'd1828 }; // nota = 6, KF = 59
10'd444: phinc = { 12'd1830 }; // nota = 6, KF = 60
10'd445: phinc = { 12'd1832 }; // nota = 6, KF = 61
10'd446: phinc = { 12'd1833 }; // nota = 6, KF = 62
10'd447: phinc = { 12'd1835 }; // nota = 6, KF = 63
10'd448: phinc = { 12'd1734 }; // nota = 7, KF = 0
10'd449: phinc = { 12'd1735 }; // nota = 7, KF = 1
10'd450: phinc = { 12'd1737 }; // nota = 7, KF = 2
10'd451: phinc = { 12'd1738 }; // nota = 7, KF = 3
10'd452: phinc = { 12'd1740 }; // nota = 7, KF = 4
10'd453: phinc = { 12'd1741 }; // nota = 7, KF = 5
10'd454: phinc = { 12'd1743 }; // nota = 7, KF = 6
10'd455: phinc = { 12'd1744 }; // nota = 7, KF = 7
10'd456: phinc = { 12'd1746 }; // nota = 7, KF = 8
10'd457: phinc = { 12'd1748 }; // nota = 7, KF = 9
10'd458: phinc = { 12'd1749 }; // nota = 7, KF = 10
10'd459: phinc = { 12'd1751 }; // nota = 7, KF = 11
10'd460: phinc = { 12'd1752 }; // nota = 7, KF = 12
10'd461: phinc = { 12'd1754 }; // nota = 7, KF = 13
10'd462: phinc = { 12'd1755 }; // nota = 7, KF = 14
10'd463: phinc = { 12'd1757 }; // nota = 7, KF = 15
10'd464: phinc = { 12'd1759 }; // nota = 7, KF = 16
10'd465: phinc = { 12'd1760 }; // nota = 7, KF = 17
10'd466: phinc = { 12'd1762 }; // nota = 7, KF = 18
10'd467: phinc = { 12'd1763 }; // nota = 7, KF = 19
10'd468: phinc = { 12'd1765 }; // nota = 7, KF = 20
10'd469: phinc = { 12'd1766 }; // nota = 7, KF = 21
10'd470: phinc = { 12'd1768 }; // nota = 7, KF = 22
10'd471: phinc = { 12'd1769 }; // nota = 7, KF = 23
10'd472: phinc = { 12'd1771 }; // nota = 7, KF = 24
10'd473: phinc = { 12'd1773 }; // nota = 7, KF = 25
10'd474: phinc = { 12'd1774 }; // nota = 7, KF = 26
10'd475: phinc = { 12'd1776 }; // nota = 7, KF = 27
10'd476: phinc = { 12'd1777 }; // nota = 7, KF = 28
10'd477: phinc = { 12'd1779 }; // nota = 7, KF = 29
10'd478: phinc = { 12'd1780 }; // nota = 7, KF = 30
10'd479: phinc = { 12'd1782 }; // nota = 7, KF = 31
10'd480: phinc = { 12'd1785 }; // nota = 7, KF = 32
10'd481: phinc = { 12'd1786 }; // nota = 7, KF = 33
10'd482: phinc = { 12'd1788 }; // nota = 7, KF = 34
10'd483: phinc = { 12'd1789 }; // nota = 7, KF = 35
10'd484: phinc = { 12'd1791 }; // nota = 7, KF = 36
10'd485: phinc = { 12'd1793 }; // nota = 7, KF = 37
10'd486: phinc = { 12'd1794 }; // nota = 7, KF = 38
10'd487: phinc = { 12'd1796 }; // nota = 7, KF = 39
10'd488: phinc = { 12'd1798 }; // nota = 7, KF = 40
10'd489: phinc = { 12'd1799 }; // nota = 7, KF = 41
10'd490: phinc = { 12'd1801 }; // nota = 7, KF = 42
10'd491: phinc = { 12'd1802 }; // nota = 7, KF = 43
10'd492: phinc = { 12'd1804 }; // nota = 7, KF = 44
10'd493: phinc = { 12'd1806 }; // nota = 7, KF = 45
10'd494: phinc = { 12'd1807 }; // nota = 7, KF = 46
10'd495: phinc = { 12'd1809 }; // nota = 7, KF = 47
10'd496: phinc = { 12'd1811 }; // nota = 7, KF = 48
10'd497: phinc = { 12'd1812 }; // nota = 7, KF = 49
10'd498: phinc = { 12'd1814 }; // nota = 7, KF = 50
10'd499: phinc = { 12'd1815 }; // nota = 7, KF = 51
10'd500: phinc = { 12'd1817 }; // nota = 7, KF = 52
10'd501: phinc = { 12'd1819 }; // nota = 7, KF = 53
10'd502: phinc = { 12'd1820 }; // nota = 7, KF = 54
10'd503: phinc = { 12'd1822 }; // nota = 7, KF = 55
10'd504: phinc = { 12'd1824 }; // nota = 7, KF = 56
10'd505: phinc = { 12'd1825 }; // nota = 7, KF = 57
10'd506: phinc = { 12'd1827 }; // nota = 7, KF = 58
10'd507: phinc = { 12'd1828 }; // nota = 7, KF = 59
10'd508: phinc = { 12'd1830 }; // nota = 7, KF = 60
10'd509: phinc = { 12'd1832 }; // nota = 7, KF = 61
10'd510: phinc = { 12'd1833 }; // nota = 7, KF = 62
10'd511: phinc = { 12'd1835 }; // nota = 7, KF = 63
10'd512: phinc = { 12'd1837 }; // nota = 8, KF = 0
10'd513: phinc = { 12'd1838 }; // nota = 8, KF = 1
10'd514: phinc = { 12'd1840 }; // nota = 8, KF = 2
10'd515: phinc = { 12'd1841 }; // nota = 8, KF = 3
10'd516: phinc = { 12'd1843 }; // nota = 8, KF = 4
10'd517: phinc = { 12'd1845 }; // nota = 8, KF = 5
10'd518: phinc = { 12'd1846 }; // nota = 8, KF = 6
10'd519: phinc = { 12'd1848 }; // nota = 8, KF = 7
10'd520: phinc = { 12'd1850 }; // nota = 8, KF = 8
10'd521: phinc = { 12'd1851 }; // nota = 8, KF = 9
10'd522: phinc = { 12'd1853 }; // nota = 8, KF = 10
10'd523: phinc = { 12'd1854 }; // nota = 8, KF = 11
10'd524: phinc = { 12'd1856 }; // nota = 8, KF = 12
10'd525: phinc = { 12'd1858 }; // nota = 8, KF = 13
10'd526: phinc = { 12'd1859 }; // nota = 8, KF = 14
10'd527: phinc = { 12'd1861 }; // nota = 8, KF = 15
10'd528: phinc = { 12'd1864 }; // nota = 8, KF = 16
10'd529: phinc = { 12'd1865 }; // nota = 8, KF = 17
10'd530: phinc = { 12'd1867 }; // nota = 8, KF = 18
10'd531: phinc = { 12'd1868 }; // nota = 8, KF = 19
10'd532: phinc = { 12'd1870 }; // nota = 8, KF = 20
10'd533: phinc = { 12'd1872 }; // nota = 8, KF = 21
10'd534: phinc = { 12'd1873 }; // nota = 8, KF = 22
10'd535: phinc = { 12'd1875 }; // nota = 8, KF = 23
10'd536: phinc = { 12'd1877 }; // nota = 8, KF = 24
10'd537: phinc = { 12'd1879 }; // nota = 8, KF = 25
10'd538: phinc = { 12'd1880 }; // nota = 8, KF = 26
10'd539: phinc = { 12'd1882 }; // nota = 8, KF = 27
10'd540: phinc = { 12'd1884 }; // nota = 8, KF = 28
10'd541: phinc = { 12'd1885 }; // nota = 8, KF = 29
10'd542: phinc = { 12'd1887 }; // nota = 8, KF = 30
10'd543: phinc = { 12'd1888 }; // nota = 8, KF = 31
10'd544: phinc = { 12'd1891 }; // nota = 8, KF = 32
10'd545: phinc = { 12'd1892 }; // nota = 8, KF = 33
10'd546: phinc = { 12'd1894 }; // nota = 8, KF = 34
10'd547: phinc = { 12'd1895 }; // nota = 8, KF = 35
10'd548: phinc = { 12'd1897 }; // nota = 8, KF = 36
10'd549: phinc = { 12'd1899 }; // nota = 8, KF = 37
10'd550: phinc = { 12'd1900 }; // nota = 8, KF = 38
10'd551: phinc = { 12'd1902 }; // nota = 8, KF = 39
10'd552: phinc = { 12'd1904 }; // nota = 8, KF = 40
10'd553: phinc = { 12'd1906 }; // nota = 8, KF = 41
10'd554: phinc = { 12'd1907 }; // nota = 8, KF = 42
10'd555: phinc = { 12'd1909 }; // nota = 8, KF = 43
10'd556: phinc = { 12'd1911 }; // nota = 8, KF = 44
10'd557: phinc = { 12'd1912 }; // nota = 8, KF = 45
10'd558: phinc = { 12'd1914 }; // nota = 8, KF = 46
10'd559: phinc = { 12'd1915 }; // nota = 8, KF = 47
10'd560: phinc = { 12'd1918 }; // nota = 8, KF = 48
10'd561: phinc = { 12'd1919 }; // nota = 8, KF = 49
10'd562: phinc = { 12'd1921 }; // nota = 8, KF = 50
10'd563: phinc = { 12'd1923 }; // nota = 8, KF = 51
10'd564: phinc = { 12'd1925 }; // nota = 8, KF = 52
10'd565: phinc = { 12'd1926 }; // nota = 8, KF = 53
10'd566: phinc = { 12'd1928 }; // nota = 8, KF = 54
10'd567: phinc = { 12'd1930 }; // nota = 8, KF = 55
10'd568: phinc = { 12'd1932 }; // nota = 8, KF = 56
10'd569: phinc = { 12'd1933 }; // nota = 8, KF = 57
10'd570: phinc = { 12'd1935 }; // nota = 8, KF = 58
10'd571: phinc = { 12'd1937 }; // nota = 8, KF = 59
10'd572: phinc = { 12'd1939 }; // nota = 8, KF = 60
10'd573: phinc = { 12'd1940 }; // nota = 8, KF = 61
10'd574: phinc = { 12'd1942 }; // nota = 8, KF = 62
10'd575: phinc = { 12'd1944 }; // nota = 8, KF = 63
10'd576: phinc = { 12'd1946 }; // nota = 9, KF = 0
10'd577: phinc = { 12'd1947 }; // nota = 9, KF = 1
10'd578: phinc = { 12'd1949 }; // nota = 9, KF = 2
10'd579: phinc = { 12'd1951 }; // nota = 9, KF = 3
10'd580: phinc = { 12'd1953 }; // nota = 9, KF = 4
10'd581: phinc = { 12'd1954 }; // nota = 9, KF = 5
10'd582: phinc = { 12'd1956 }; // nota = 9, KF = 6
10'd583: phinc = { 12'd1958 }; // nota = 9, KF = 7
10'd584: phinc = { 12'd1960 }; // nota = 9, KF = 8
10'd585: phinc = { 12'd1961 }; // nota = 9, KF = 9
10'd586: phinc = { 12'd1963 }; // nota = 9, KF = 10
10'd587: phinc = { 12'd1965 }; // nota = 9, KF = 11
10'd588: phinc = { 12'd1967 }; // nota = 9, KF = 12
10'd589: phinc = { 12'd1968 }; // nota = 9, KF = 13
10'd590: phinc = { 12'd1970 }; // nota = 9, KF = 14
10'd591: phinc = { 12'd1972 }; // nota = 9, KF = 15
10'd592: phinc = { 12'd1975 }; // nota = 9, KF = 16
10'd593: phinc = { 12'd1976 }; // nota = 9, KF = 17
10'd594: phinc = { 12'd1978 }; // nota = 9, KF = 18
10'd595: phinc = { 12'd1980 }; // nota = 9, KF = 19
10'd596: phinc = { 12'd1982 }; // nota = 9, KF = 20
10'd597: phinc = { 12'd1983 }; // nota = 9, KF = 21
10'd598: phinc = { 12'd1985 }; // nota = 9, KF = 22
10'd599: phinc = { 12'd1987 }; // nota = 9, KF = 23
10'd600: phinc = { 12'd1989 }; // nota = 9, KF = 24
10'd601: phinc = { 12'd1990 }; // nota = 9, KF = 25
10'd602: phinc = { 12'd1992 }; // nota = 9, KF = 26
10'd603: phinc = { 12'd1994 }; // nota = 9, KF = 27
10'd604: phinc = { 12'd1996 }; // nota = 9, KF = 28
10'd605: phinc = { 12'd1997 }; // nota = 9, KF = 29
10'd606: phinc = { 12'd1999 }; // nota = 9, KF = 30
10'd607: phinc = { 12'd2001 }; // nota = 9, KF = 31
10'd608: phinc = { 12'd2003 }; // nota = 9, KF = 32
10'd609: phinc = { 12'd2004 }; // nota = 9, KF = 33
10'd610: phinc = { 12'd2006 }; // nota = 9, KF = 34
10'd611: phinc = { 12'd2008 }; // nota = 9, KF = 35
10'd612: phinc = { 12'd2010 }; // nota = 9, KF = 36
10'd613: phinc = { 12'd2011 }; // nota = 9, KF = 37
10'd614: phinc = { 12'd2013 }; // nota = 9, KF = 38
10'd615: phinc = { 12'd2015 }; // nota = 9, KF = 39
10'd616: phinc = { 12'd2017 }; // nota = 9, KF = 40
10'd617: phinc = { 12'd2019 }; // nota = 9, KF = 41
10'd618: phinc = { 12'd2021 }; // nota = 9, KF = 42
10'd619: phinc = { 12'd2022 }; // nota = 9, KF = 43
10'd620: phinc = { 12'd2024 }; // nota = 9, KF = 44
10'd621: phinc = { 12'd2026 }; // nota = 9, KF = 45
10'd622: phinc = { 12'd2028 }; // nota = 9, KF = 46
10'd623: phinc = { 12'd2029 }; // nota = 9, KF = 47
10'd624: phinc = { 12'd2032 }; // nota = 9, KF = 48
10'd625: phinc = { 12'd2033 }; // nota = 9, KF = 49
10'd626: phinc = { 12'd2035 }; // nota = 9, KF = 50
10'd627: phinc = { 12'd2037 }; // nota = 9, KF = 51
10'd628: phinc = { 12'd2039 }; // nota = 9, KF = 52
10'd629: phinc = { 12'd2041 }; // nota = 9, KF = 53
10'd630: phinc = { 12'd2043 }; // nota = 9, KF = 54
10'd631: phinc = { 12'd2044 }; // nota = 9, KF = 55
10'd632: phinc = { 12'd2047 }; // nota = 9, KF = 56
10'd633: phinc = { 12'd2048 }; // nota = 9, KF = 57
10'd634: phinc = { 12'd2050 }; // nota = 9, KF = 58
10'd635: phinc = { 12'd2052 }; // nota = 9, KF = 59
10'd636: phinc = { 12'd2054 }; // nota = 9, KF = 60
10'd637: phinc = { 12'd2056 }; // nota = 9, KF = 61
10'd638: phinc = { 12'd2058 }; // nota = 9, KF = 62
10'd639: phinc = { 12'd2059 }; // nota = 9, KF = 63
10'd640: phinc = { 12'd2062 }; // nota = 10, KF = 0
10'd641: phinc = { 12'd2063 }; // nota = 10, KF = 1
10'd642: phinc = { 12'd2065 }; // nota = 10, KF = 2
10'd643: phinc = { 12'd2067 }; // nota = 10, KF = 3
10'd644: phinc = { 12'd2069 }; // nota = 10, KF = 4
10'd645: phinc = { 12'd2071 }; // nota = 10, KF = 5
10'd646: phinc = { 12'd2073 }; // nota = 10, KF = 6
10'd647: phinc = { 12'd2074 }; // nota = 10, KF = 7
10'd648: phinc = { 12'd2077 }; // nota = 10, KF = 8
10'd649: phinc = { 12'd2078 }; // nota = 10, KF = 9
10'd650: phinc = { 12'd2080 }; // nota = 10, KF = 10
10'd651: phinc = { 12'd2082 }; // nota = 10, KF = 11
10'd652: phinc = { 12'd2084 }; // nota = 10, KF = 12
10'd653: phinc = { 12'd2086 }; // nota = 10, KF = 13
10'd654: phinc = { 12'd2088 }; // nota = 10, KF = 14
10'd655: phinc = { 12'd2089 }; // nota = 10, KF = 15
10'd656: phinc = { 12'd2092 }; // nota = 10, KF = 16
10'd657: phinc = { 12'd2093 }; // nota = 10, KF = 17
10'd658: phinc = { 12'd2095 }; // nota = 10, KF = 18
10'd659: phinc = { 12'd2097 }; // nota = 10, KF = 19
10'd660: phinc = { 12'd2099 }; // nota = 10, KF = 20
10'd661: phinc = { 12'd2101 }; // nota = 10, KF = 21
10'd662: phinc = { 12'd2103 }; // nota = 10, KF = 22
10'd663: phinc = { 12'd2104 }; // nota = 10, KF = 23
10'd664: phinc = { 12'd2107 }; // nota = 10, KF = 24
10'd665: phinc = { 12'd2108 }; // nota = 10, KF = 25
10'd666: phinc = { 12'd2110 }; // nota = 10, KF = 26
10'd667: phinc = { 12'd2112 }; // nota = 10, KF = 27
10'd668: phinc = { 12'd2114 }; // nota = 10, KF = 28
10'd669: phinc = { 12'd2116 }; // nota = 10, KF = 29
10'd670: phinc = { 12'd2118 }; // nota = 10, KF = 30
10'd671: phinc = { 12'd2119 }; // nota = 10, KF = 31
10'd672: phinc = { 12'd2122 }; // nota = 10, KF = 32
10'd673: phinc = { 12'd2123 }; // nota = 10, KF = 33
10'd674: phinc = { 12'd2125 }; // nota = 10, KF = 34
10'd675: phinc = { 12'd2127 }; // nota = 10, KF = 35
10'd676: phinc = { 12'd2129 }; // nota = 10, KF = 36
10'd677: phinc = { 12'd2131 }; // nota = 10, KF = 37
10'd678: phinc = { 12'd2133 }; // nota = 10, KF = 38
10'd679: phinc = { 12'd2134 }; // nota = 10, KF = 39
10'd680: phinc = { 12'd2137 }; // nota = 10, KF = 40
10'd681: phinc = { 12'd2139 }; // nota = 10, KF = 41
10'd682: phinc = { 12'd2141 }; // nota = 10, KF = 42
10'd683: phinc = { 12'd2142 }; // nota = 10, KF = 43
10'd684: phinc = { 12'd2145 }; // nota = 10, KF = 44
10'd685: phinc = { 12'd2146 }; // nota = 10, KF = 45
10'd686: phinc = { 12'd2148 }; // nota = 10, KF = 46
10'd687: phinc = { 12'd2150 }; // nota = 10, KF = 47
10'd688: phinc = { 12'd2153 }; // nota = 10, KF = 48
10'd689: phinc = { 12'd2154 }; // nota = 10, KF = 49
10'd690: phinc = { 12'd2156 }; // nota = 10, KF = 50
10'd691: phinc = { 12'd2158 }; // nota = 10, KF = 51
10'd692: phinc = { 12'd2160 }; // nota = 10, KF = 52
10'd693: phinc = { 12'd2162 }; // nota = 10, KF = 53
10'd694: phinc = { 12'd2164 }; // nota = 10, KF = 54
10'd695: phinc = { 12'd2165 }; // nota = 10, KF = 55
10'd696: phinc = { 12'd2168 }; // nota = 10, KF = 56
10'd697: phinc = { 12'd2170 }; // nota = 10, KF = 57
10'd698: phinc = { 12'd2172 }; // nota = 10, KF = 58
10'd699: phinc = { 12'd2173 }; // nota = 10, KF = 59
10'd700: phinc = { 12'd2176 }; // nota = 10, KF = 60
10'd701: phinc = { 12'd2177 }; // nota = 10, KF = 61
10'd702: phinc = { 12'd2179 }; // nota = 10, KF = 62
10'd703: phinc = { 12'd2181 }; // nota = 10, KF = 63
10'd704: phinc = { 12'd2062 }; // nota = 11, KF = 0
10'd705: phinc = { 12'd2063 }; // nota = 11, KF = 1
10'd706: phinc = { 12'd2065 }; // nota = 11, KF = 2
10'd707: phinc = { 12'd2067 }; // nota = 11, KF = 3
10'd708: phinc = { 12'd2069 }; // nota = 11, KF = 4
10'd709: phinc = { 12'd2071 }; // nota = 11, KF = 5
10'd710: phinc = { 12'd2073 }; // nota = 11, KF = 6
10'd711: phinc = { 12'd2074 }; // nota = 11, KF = 7
10'd712: phinc = { 12'd2077 }; // nota = 11, KF = 8
10'd713: phinc = { 12'd2078 }; // nota = 11, KF = 9
10'd714: phinc = { 12'd2080 }; // nota = 11, KF = 10
10'd715: phinc = { 12'd2082 }; // nota = 11, KF = 11
10'd716: phinc = { 12'd2084 }; // nota = 11, KF = 12
10'd717: phinc = { 12'd2086 }; // nota = 11, KF = 13
10'd718: phinc = { 12'd2088 }; // nota = 11, KF = 14
10'd719: phinc = { 12'd2089 }; // nota = 11, KF = 15
10'd720: phinc = { 12'd2092 }; // nota = 11, KF = 16
10'd721: phinc = { 12'd2093 }; // nota = 11, KF = 17
10'd722: phinc = { 12'd2095 }; // nota = 11, KF = 18
10'd723: phinc = { 12'd2097 }; // nota = 11, KF = 19
10'd724: phinc = { 12'd2099 }; // nota = 11, KF = 20
10'd725: phinc = { 12'd2101 }; // nota = 11, KF = 21
10'd726: phinc = { 12'd2103 }; // nota = 11, KF = 22
10'd727: phinc = { 12'd2104 }; // nota = 11, KF = 23
10'd728: phinc = { 12'd2107 }; // nota = 11, KF = 24
10'd729: phinc = { 12'd2108 }; // nota = 11, KF = 25
10'd730: phinc = { 12'd2110 }; // nota = 11, KF = 26
10'd731: phinc = { 12'd2112 }; // nota = 11, KF = 27
10'd732: phinc = { 12'd2114 }; // nota = 11, KF = 28
10'd733: phinc = { 12'd2116 }; // nota = 11, KF = 29
10'd734: phinc = { 12'd2118 }; // nota = 11, KF = 30
10'd735: phinc = { 12'd2119 }; // nota = 11, KF = 31
10'd736: phinc = { 12'd2122 }; // nota = 11, KF = 32
10'd737: phinc = { 12'd2123 }; // nota = 11, KF = 33
10'd738: phinc = { 12'd2125 }; // nota = 11, KF = 34
10'd739: phinc = { 12'd2127 }; // nota = 11, KF = 35
10'd740: phinc = { 12'd2129 }; // nota = 11, KF = 36
10'd741: phinc = { 12'd2131 }; // nota = 11, KF = 37
10'd742: phinc = { 12'd2133 }; // nota = 11, KF = 38
10'd743: phinc = { 12'd2134 }; // nota = 11, KF = 39
10'd744: phinc = { 12'd2137 }; // nota = 11, KF = 40
10'd745: phinc = { 12'd2139 }; // nota = 11, KF = 41
10'd746: phinc = { 12'd2141 }; // nota = 11, KF = 42
10'd747: phinc = { 12'd2142 }; // nota = 11, KF = 43
10'd748: phinc = { 12'd2145 }; // nota = 11, KF = 44
10'd749: phinc = { 12'd2146 }; // nota = 11, KF = 45
10'd750: phinc = { 12'd2148 }; // nota = 11, KF = 46
10'd751: phinc = { 12'd2150 }; // nota = 11, KF = 47
10'd752: phinc = { 12'd2153 }; // nota = 11, KF = 48
10'd753: phinc = { 12'd2154 }; // nota = 11, KF = 49
10'd754: phinc = { 12'd2156 }; // nota = 11, KF = 50
10'd755: phinc = { 12'd2158 }; // nota = 11, KF = 51
10'd756: phinc = { 12'd2160 }; // nota = 11, KF = 52
10'd757: phinc = { 12'd2162 }; // nota = 11, KF = 53
10'd758: phinc = { 12'd2164 }; // nota = 11, KF = 54
10'd759: phinc = { 12'd2165 }; // nota = 11, KF = 55
10'd760: phinc = { 12'd2168 }; // nota = 11, KF = 56
10'd761: phinc = { 12'd2170 }; // nota = 11, KF = 57
10'd762: phinc = { 12'd2172 }; // nota = 11, KF = 58
10'd763: phinc = { 12'd2173 }; // nota = 11, KF = 59
10'd764: phinc = { 12'd2176 }; // nota = 11, KF = 60
10'd765: phinc = { 12'd2177 }; // nota = 11, KF = 61
10'd766: phinc = { 12'd2179 }; // nota = 11, KF = 62
10'd767: phinc = { 12'd2181 }; // nota = 11, KF = 63
10'd768: phinc = { 12'd2185 }; // nota = 12, KF = 0
10'd769: phinc = { 12'd2186 }; // nota = 12, KF = 1
10'd770: phinc = { 12'd2188 }; // nota = 12, KF = 2
10'd771: phinc = { 12'd2190 }; // nota = 12, KF = 3
10'd772: phinc = { 12'd2192 }; // nota = 12, KF = 4
10'd773: phinc = { 12'd2194 }; // nota = 12, KF = 5
10'd774: phinc = { 12'd2196 }; // nota = 12, KF = 6
10'd775: phinc = { 12'd2197 }; // nota = 12, KF = 7
10'd776: phinc = { 12'd2200 }; // nota = 12, KF = 8
10'd777: phinc = { 12'd2202 }; // nota = 12, KF = 9
10'd778: phinc = { 12'd2204 }; // nota = 12, KF = 10
10'd779: phinc = { 12'd2205 }; // nota = 12, KF = 11
10'd780: phinc = { 12'd2208 }; // nota = 12, KF = 12
10'd781: phinc = { 12'd2209 }; // nota = 12, KF = 13
10'd782: phinc = { 12'd2211 }; // nota = 12, KF = 14
10'd783: phinc = { 12'd2213 }; // nota = 12, KF = 15
10'd784: phinc = { 12'd2216 }; // nota = 12, KF = 16
10'd785: phinc = { 12'd2218 }; // nota = 12, KF = 17
10'd786: phinc = { 12'd2220 }; // nota = 12, KF = 18
10'd787: phinc = { 12'd2222 }; // nota = 12, KF = 19
10'd788: phinc = { 12'd2223 }; // nota = 12, KF = 20
10'd789: phinc = { 12'd2226 }; // nota = 12, KF = 21
10'd790: phinc = { 12'd2227 }; // nota = 12, KF = 22
10'd791: phinc = { 12'd2230 }; // nota = 12, KF = 23
10'd792: phinc = { 12'd2232 }; // nota = 12, KF = 24
10'd793: phinc = { 12'd2234 }; // nota = 12, KF = 25
10'd794: phinc = { 12'd2236 }; // nota = 12, KF = 26
10'd795: phinc = { 12'd2238 }; // nota = 12, KF = 27
10'd796: phinc = { 12'd2239 }; // nota = 12, KF = 28
10'd797: phinc = { 12'd2242 }; // nota = 12, KF = 29
10'd798: phinc = { 12'd2243 }; // nota = 12, KF = 30
10'd799: phinc = { 12'd2246 }; // nota = 12, KF = 31
10'd800: phinc = { 12'd2249 }; // nota = 12, KF = 32
10'd801: phinc = { 12'd2251 }; // nota = 12, KF = 33
10'd802: phinc = { 12'd2253 }; // nota = 12, KF = 34
10'd803: phinc = { 12'd2255 }; // nota = 12, KF = 35
10'd804: phinc = { 12'd2256 }; // nota = 12, KF = 36
10'd805: phinc = { 12'd2259 }; // nota = 12, KF = 37
10'd806: phinc = { 12'd2260 }; // nota = 12, KF = 38
10'd807: phinc = { 12'd2263 }; // nota = 12, KF = 39
10'd808: phinc = { 12'd2265 }; // nota = 12, KF = 40
10'd809: phinc = { 12'd2267 }; // nota = 12, KF = 41
10'd810: phinc = { 12'd2269 }; // nota = 12, KF = 42
10'd811: phinc = { 12'd2271 }; // nota = 12, KF = 43
10'd812: phinc = { 12'd2272 }; // nota = 12, KF = 44
10'd813: phinc = { 12'd2275 }; // nota = 12, KF = 45
10'd814: phinc = { 12'd2276 }; // nota = 12, KF = 46
10'd815: phinc = { 12'd2279 }; // nota = 12, KF = 47
10'd816: phinc = { 12'd2281 }; // nota = 12, KF = 48
10'd817: phinc = { 12'd2283 }; // nota = 12, KF = 49
10'd818: phinc = { 12'd2285 }; // nota = 12, KF = 50
10'd819: phinc = { 12'd2287 }; // nota = 12, KF = 51
10'd820: phinc = { 12'd2288 }; // nota = 12, KF = 52
10'd821: phinc = { 12'd2291 }; // nota = 12, KF = 53
10'd822: phinc = { 12'd2292 }; // nota = 12, KF = 54
10'd823: phinc = { 12'd2295 }; // nota = 12, KF = 55
10'd824: phinc = { 12'd2297 }; // nota = 12, KF = 56
10'd825: phinc = { 12'd2299 }; // nota = 12, KF = 57
10'd826: phinc = { 12'd2301 }; // nota = 12, KF = 58
10'd827: phinc = { 12'd2303 }; // nota = 12, KF = 59
10'd828: phinc = { 12'd2304 }; // nota = 12, KF = 60
10'd829: phinc = { 12'd2307 }; // nota = 12, KF = 61
10'd830: phinc = { 12'd2308 }; // nota = 12, KF = 62
10'd831: phinc = { 12'd2311 }; // nota = 12, KF = 63
10'd832: phinc = { 12'd2315 }; // nota = 13, KF = 0
10'd833: phinc = { 12'd2317 }; // nota = 13, KF = 1
10'd834: phinc = { 12'd2319 }; // nota = 13, KF = 2
10'd835: phinc = { 12'd2321 }; // nota = 13, KF = 3
10'd836: phinc = { 12'd2322 }; // nota = 13, KF = 4
10'd837: phinc = { 12'd2325 }; // nota = 13, KF = 5
10'd838: phinc = { 12'd2326 }; // nota = 13, KF = 6
10'd839: phinc = { 12'd2329 }; // nota = 13, KF = 7
10'd840: phinc = { 12'd2331 }; // nota = 13, KF = 8
10'd841: phinc = { 12'd2333 }; // nota = 13, KF = 9
10'd842: phinc = { 12'd2335 }; // nota = 13, KF = 10
10'd843: phinc = { 12'd2337 }; // nota = 13, KF = 11
10'd844: phinc = { 12'd2338 }; // nota = 13, KF = 12
10'd845: phinc = { 12'd2341 }; // nota = 13, KF = 13
10'd846: phinc = { 12'd2342 }; // nota = 13, KF = 14
10'd847: phinc = { 12'd2345 }; // nota = 13, KF = 15
10'd848: phinc = { 12'd2348 }; // nota = 13, KF = 16
10'd849: phinc = { 12'd2350 }; // nota = 13, KF = 17
10'd850: phinc = { 12'd2352 }; // nota = 13, KF = 18
10'd851: phinc = { 12'd2354 }; // nota = 13, KF = 19
10'd852: phinc = { 12'd2355 }; // nota = 13, KF = 20
10'd853: phinc = { 12'd2358 }; // nota = 13, KF = 21
10'd854: phinc = { 12'd2359 }; // nota = 13, KF = 22
10'd855: phinc = { 12'd2362 }; // nota = 13, KF = 23
10'd856: phinc = { 12'd2364 }; // nota = 13, KF = 24
10'd857: phinc = { 12'd2366 }; // nota = 13, KF = 25
10'd858: phinc = { 12'd2368 }; // nota = 13, KF = 26
10'd859: phinc = { 12'd2370 }; // nota = 13, KF = 27
10'd860: phinc = { 12'd2371 }; // nota = 13, KF = 28
10'd861: phinc = { 12'd2374 }; // nota = 13, KF = 29
10'd862: phinc = { 12'd2375 }; // nota = 13, KF = 30
10'd863: phinc = { 12'd2378 }; // nota = 13, KF = 31
10'd864: phinc = { 12'd2382 }; // nota = 13, KF = 32
10'd865: phinc = { 12'd2384 }; // nota = 13, KF = 33
10'd866: phinc = { 12'd2386 }; // nota = 13, KF = 34
10'd867: phinc = { 12'd2388 }; // nota = 13, KF = 35
10'd868: phinc = { 12'd2389 }; // nota = 13, KF = 36
10'd869: phinc = { 12'd2392 }; // nota = 13, KF = 37
10'd870: phinc = { 12'd2393 }; // nota = 13, KF = 38
10'd871: phinc = { 12'd2396 }; // nota = 13, KF = 39
10'd872: phinc = { 12'd2398 }; // nota = 13, KF = 40
10'd873: phinc = { 12'd2400 }; // nota = 13, KF = 41
10'd874: phinc = { 12'd2402 }; // nota = 13, KF = 42
10'd875: phinc = { 12'd2404 }; // nota = 13, KF = 43
10'd876: phinc = { 12'd2407 }; // nota = 13, KF = 44
10'd877: phinc = { 12'd2410 }; // nota = 13, KF = 45
10'd878: phinc = { 12'd2411 }; // nota = 13, KF = 46
10'd879: phinc = { 12'd2414 }; // nota = 13, KF = 47
10'd880: phinc = { 12'd2417 }; // nota = 13, KF = 48
10'd881: phinc = { 12'd2419 }; // nota = 13, KF = 49
10'd882: phinc = { 12'd2421 }; // nota = 13, KF = 50
10'd883: phinc = { 12'd2423 }; // nota = 13, KF = 51
10'd884: phinc = { 12'd2424 }; // nota = 13, KF = 52
10'd885: phinc = { 12'd2427 }; // nota = 13, KF = 53
10'd886: phinc = { 12'd2428 }; // nota = 13, KF = 54
10'd887: phinc = { 12'd2431 }; // nota = 13, KF = 55
10'd888: phinc = { 12'd2433 }; // nota = 13, KF = 56
10'd889: phinc = { 12'd2435 }; // nota = 13, KF = 57
10'd890: phinc = { 12'd2437 }; // nota = 13, KF = 58
10'd891: phinc = { 12'd2439 }; // nota = 13, KF = 59
10'd892: phinc = { 12'd2442 }; // nota = 13, KF = 60
10'd893: phinc = { 12'd2445 }; // nota = 13, KF = 61
10'd894: phinc = { 12'd2446 }; // nota = 13, KF = 62
10'd895: phinc = { 12'd2449 }; // nota = 13, KF = 63
10'd896: phinc = { 12'd2452 }; // nota = 14, KF = 0
10'd897: phinc = { 12'd2454 }; // nota = 14, KF = 1
10'd898: phinc = { 12'd2456 }; // nota = 14, KF = 2
10'd899: phinc = { 12'd2458 }; // nota = 14, KF = 3
10'd900: phinc = { 12'd2459 }; // nota = 14, KF = 4
10'd901: phinc = { 12'd2462 }; // nota = 14, KF = 5
10'd902: phinc = { 12'd2463 }; // nota = 14, KF = 6
10'd903: phinc = { 12'd2466 }; // nota = 14, KF = 7
10'd904: phinc = { 12'd2468 }; // nota = 14, KF = 8
10'd905: phinc = { 12'd2470 }; // nota = 14, KF = 9
10'd906: phinc = { 12'd2472 }; // nota = 14, KF = 10
10'd907: phinc = { 12'd2474 }; // nota = 14, KF = 11
10'd908: phinc = { 12'd2477 }; // nota = 14, KF = 12
10'd909: phinc = { 12'd2480 }; // nota = 14, KF = 13
10'd910: phinc = { 12'd2481 }; // nota = 14, KF = 14
10'd911: phinc = { 12'd2484 }; // nota = 14, KF = 15
10'd912: phinc = { 12'd2488 }; // nota = 14, KF = 16
10'd913: phinc = { 12'd2490 }; // nota = 14, KF = 17
10'd914: phinc = { 12'd2492 }; // nota = 14, KF = 18
10'd915: phinc = { 12'd2494 }; // nota = 14, KF = 19
10'd916: phinc = { 12'd2495 }; // nota = 14, KF = 20
10'd917: phinc = { 12'd2498 }; // nota = 14, KF = 21
10'd918: phinc = { 12'd2499 }; // nota = 14, KF = 22
10'd919: phinc = { 12'd2502 }; // nota = 14, KF = 23
10'd920: phinc = { 12'd2504 }; // nota = 14, KF = 24
10'd921: phinc = { 12'd2506 }; // nota = 14, KF = 25
10'd922: phinc = { 12'd2508 }; // nota = 14, KF = 26
10'd923: phinc = { 12'd2510 }; // nota = 14, KF = 27
10'd924: phinc = { 12'd2513 }; // nota = 14, KF = 28
10'd925: phinc = { 12'd2516 }; // nota = 14, KF = 29
10'd926: phinc = { 12'd2517 }; // nota = 14, KF = 30
10'd927: phinc = { 12'd2520 }; // nota = 14, KF = 31
10'd928: phinc = { 12'd2524 }; // nota = 14, KF = 32
10'd929: phinc = { 12'd2526 }; // nota = 14, KF = 33
10'd930: phinc = { 12'd2528 }; // nota = 14, KF = 34
10'd931: phinc = { 12'd2530 }; // nota = 14, KF = 35
10'd932: phinc = { 12'd2531 }; // nota = 14, KF = 36
10'd933: phinc = { 12'd2534 }; // nota = 14, KF = 37
10'd934: phinc = { 12'd2535 }; // nota = 14, KF = 38
10'd935: phinc = { 12'd2538 }; // nota = 14, KF = 39
10'd936: phinc = { 12'd2540 }; // nota = 14, KF = 40
10'd937: phinc = { 12'd2542 }; // nota = 14, KF = 41
10'd938: phinc = { 12'd2544 }; // nota = 14, KF = 42
10'd939: phinc = { 12'd2546 }; // nota = 14, KF = 43
10'd940: phinc = { 12'd2549 }; // nota = 14, KF = 44
10'd941: phinc = { 12'd2552 }; // nota = 14, KF = 45
10'd942: phinc = { 12'd2553 }; // nota = 14, KF = 46
10'd943: phinc = { 12'd2556 }; // nota = 14, KF = 47
10'd944: phinc = { 12'd2561 }; // nota = 14, KF = 48
10'd945: phinc = { 12'd2563 }; // nota = 14, KF = 49
10'd946: phinc = { 12'd2565 }; // nota = 14, KF = 50
10'd947: phinc = { 12'd2567 }; // nota = 14, KF = 51
10'd948: phinc = { 12'd2568 }; // nota = 14, KF = 52
10'd949: phinc = { 12'd2571 }; // nota = 14, KF = 53
10'd950: phinc = { 12'd2572 }; // nota = 14, KF = 54
10'd951: phinc = { 12'd2575 }; // nota = 14, KF = 55
10'd952: phinc = { 12'd2577 }; // nota = 14, KF = 56
10'd953: phinc = { 12'd2579 }; // nota = 14, KF = 57
10'd954: phinc = { 12'd2581 }; // nota = 14, KF = 58
10'd955: phinc = { 12'd2583 }; // nota = 14, KF = 59
10'd956: phinc = { 12'd2586 }; // nota = 14, KF = 60
10'd957: phinc = { 12'd2589 }; // nota = 14, KF = 61
10'd958: phinc = { 12'd2590 }; // nota = 14, KF = 62
10'd959: phinc = { 12'd2593 }; // nota = 14, KF = 63
10'd960: phinc = { 12'd2452 }; // nota = 15, KF = 0
10'd961: phinc = { 12'd2454 }; // nota = 15, KF = 1
10'd962: phinc = { 12'd2456 }; // nota = 15, KF = 2
10'd963: phinc = { 12'd2458 }; // nota = 15, KF = 3
10'd964: phinc = { 12'd2459 }; // nota = 15, KF = 4
10'd965: phinc = { 12'd2462 }; // nota = 15, KF = 5
10'd966: phinc = { 12'd2463 }; // nota = 15, KF = 6
10'd967: phinc = { 12'd2466 }; // nota = 15, KF = 7
10'd968: phinc = { 12'd2468 }; // nota = 15, KF = 8
10'd969: phinc = { 12'd2470 }; // nota = 15, KF = 9
10'd970: phinc = { 12'd2472 }; // nota = 15, KF = 10
10'd971: phinc = { 12'd2474 }; // nota = 15, KF = 11
10'd972: phinc = { 12'd2477 }; // nota = 15, KF = 12
10'd973: phinc = { 12'd2480 }; // nota = 15, KF = 13
10'd974: phinc = { 12'd2481 }; // nota = 15, KF = 14
10'd975: phinc = { 12'd2484 }; // nota = 15, KF = 15
10'd976: phinc = { 12'd2488 }; // nota = 15, KF = 16
10'd977: phinc = { 12'd2490 }; // nota = 15, KF = 17
10'd978: phinc = { 12'd2492 }; // nota = 15, KF = 18
10'd979: phinc = { 12'd2494 }; // nota = 15, KF = 19
10'd980: phinc = { 12'd2495 }; // nota = 15, KF = 20
10'd981: phinc = { 12'd2498 }; // nota = 15, KF = 21
10'd982: phinc = { 12'd2499 }; // nota = 15, KF = 22
10'd983: phinc = { 12'd2502 }; // nota = 15, KF = 23
10'd984: phinc = { 12'd2504 }; // nota = 15, KF = 24
10'd985: phinc = { 12'd2506 }; // nota = 15, KF = 25
10'd986: phinc = { 12'd2508 }; // nota = 15, KF = 26
10'd987: phinc = { 12'd2510 }; // nota = 15, KF = 27
10'd988: phinc = { 12'd2513 }; // nota = 15, KF = 28
10'd989: phinc = { 12'd2516 }; // nota = 15, KF = 29
10'd990: phinc = { 12'd2517 }; // nota = 15, KF = 30
10'd991: phinc = { 12'd2520 }; // nota = 15, KF = 31
10'd992: phinc = { 12'd2524 }; // nota = 15, KF = 32
10'd993: phinc = { 12'd2526 }; // nota = 15, KF = 33
10'd994: phinc = { 12'd2528 }; // nota = 15, KF = 34
10'd995: phinc = { 12'd2530 }; // nota = 15, KF = 35
10'd996: phinc = { 12'd2531 }; // nota = 15, KF = 36
10'd997: phinc = { 12'd2534 }; // nota = 15, KF = 37
10'd998: phinc = { 12'd2535 }; // nota = 15, KF = 38
10'd999: phinc = { 12'd2538 }; // nota = 15, KF = 39
10'd1000: phinc = { 12'd2540 }; // nota = 15, KF = 40
10'd1001: phinc = { 12'd2542 }; // nota = 15, KF = 41
10'd1002: phinc = { 12'd2544 }; // nota = 15, KF = 42
10'd1003: phinc = { 12'd2546 }; // nota = 15, KF = 43
10'd1004: phinc = { 12'd2549 }; // nota = 15, KF = 44
10'd1005: phinc = { 12'd2552 }; // nota = 15, KF = 45
10'd1006: phinc = { 12'd2553 }; // nota = 15, KF = 46
10'd1007: phinc = { 12'd2556 }; // nota = 15, KF = 47
10'd1008: phinc = { 12'd2561 }; // nota = 15, KF = 48
10'd1009: phinc = { 12'd2563 }; // nota = 15, KF = 49
10'd1010: phinc = { 12'd2565 }; // nota = 15, KF = 50
10'd1011: phinc = { 12'd2567 }; // nota = 15, KF = 51
10'd1012: phinc = { 12'd2568 }; // nota = 15, KF = 52
10'd1013: phinc = { 12'd2571 }; // nota = 15, KF = 53
10'd1014: phinc = { 12'd2572 }; // nota = 15, KF = 54
10'd1015: phinc = { 12'd2575 }; // nota = 15, KF = 55
10'd1016: phinc = { 12'd2577 }; // nota = 15, KF = 56
10'd1017: phinc = { 12'd2579 }; // nota = 15, KF = 57
10'd1018: phinc = { 12'd2581 }; // nota = 15, KF = 58
10'd1019: phinc = { 12'd2583 }; // nota = 15, KF = 59
10'd1020: phinc = { 12'd2586 }; // nota = 15, KF = 60
10'd1021: phinc = { 12'd2589 }; // nota = 15, KF = 61
10'd1022: phinc = { 12'd2590 }; // nota = 15, KF = 62
10'd1023: phinc = { 12'd2593 }; // nota = 15, KF = 63
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/27/2016 08:14:07 AM
// Design Name:
// Module Name: FPU_UART
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_UART
#(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)//-- Single Precision*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
input wire clk,
input wire rst,
output wire TX
);
//local parameters
localparam shift_region = 2'b00;
localparam N = 2; //2 para 32 bits, 3 para 64 bits
localparam op = 1'b0;
localparam d = 0;
localparam r_mode=2'b00;
//signal declaration
wire ready_op;
wire max_tick_address;
wire max_tick_ch;
wire TX_DONE;
wire beg_op;
wire ack_op;
wire load_address;
wire enab_address;
wire enab_ch;
wire load_ch;
wire TX_START;
wire [W-1:0] Data_X;
wire [W-1:0] Data_Y;
wire [W-1:0] final_result_ieee;
wire [7:0] TX_DATA;
wire [9:0] cont_address_sig;
wire [N-1:0] cont_ch;
FSM_test fsm_test_uart
(
.clk(clk),
.rst(rst),
.ready_op(ready_op),
.max_tick_address(max_tick_address),
.max_tick_ch(max_tick_ch),
.TX_DONE(TX_DONE),
.beg_op(beg_op),
.ack_op(ack_op),
.load_address(load_address),
.enab_address(enab_address),
.enab_ch(enab_ch),
.load_ch(load_ch),
.TX_START(TX_START)
);
//Adder-Subtract//////////////////////////////////////////////////////////////////////////////
FPU_Add_Subtract_Function #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) Add_Subt_uart(
.clk(clk), //System clock
.rst(rst), //System reset
.beg_FSM(beg_op), //Start operation control signal
.ack_FSM(ack_op), //Acknoledge control signal
.Data_X(Data_X), //Data_X
.Data_Y(Data_Y), //Data_Y
.add_subt(op), //1'b0 =Adder, 1'b1=Substract
.r_mode(r_mode), //Rounding control signal. 2'b00=no round, 2'b01= -infinite round , 2'b10 +infinite round
//.overflow_flag,
//.underflow_flag,
.ready(ready_op), //Ready flag
.final_result_ieee(final_result_ieee) //Result of the operation
);//*/
//Multiplication
/*FPU_Multiplication_Function #(.W(W),.EW(EW),.SW(SW)) Multiplication_uart(
.clk(clk),
.rst(rst),
.beg_FSM(beg_op),
.ack_FSM(ack_op),
.Data_MX(Data_X),
.Data_MY(Data_Y),
.round_mode(r_mode),
//.overflow_flag,
//.underflow_flag,
.ready(ready_op),
.final_result_ieee(final_result_ieee)
);
//*/
Uart uart_mod
(
.RST(rst),
.CLK(clk),
.TX_START(TX_START),
.TX_DATA(TX_DATA),
.TX(TX),
.TX_DONE(TX_DONE)
);
///Data file ROM
ROM_test #(.W(W),.N(0)) rom_test_uart_X
(
.address(cont_address_sig),
.data(Data_X)
);
ROM_test #(.W(W),.N(1)) rom_test_uart_Y
(
.address(cont_address_sig),
.data(Data_Y)
);
cont_test #(.W(10)) cont_address
(
.clk(clk),
.rst(rst),
.load(load_address),
.enable(enab_address),
.d(d),
.max_tick(max_tick_address),
.q(cont_address_sig)
);
cont_test #(.W(N)) con_mux_data
(
.clk(clk),
.rst(rst),
.load(load_ch),
.enable(enab_ch),
.d(d),
.max_tick(max_tick_ch),
.q(cont_ch)
);
generate
case(W)
32:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.data_out(TX_DATA)
);
end
64:
begin
Mux_8x1 mux_64_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.ch_4(final_result_ieee[39:32]),
.ch_5(final_result_ieee[47:40]),
.ch_6(final_result_ieee[55:48]),
.ch_7(final_result_ieee[63:56]),
.data_out(TX_DATA)
);
end
default:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.data_out(TX_DATA)
);
end
endcase
endgenerate
endmodule |
module ram_dual_memsplit_2banks
#(
parameter init_type="hex", init_data="data.hex", dat_width=32, adr_width=32, mem_size=1024, P0_FRAC="NO", P1_FRAC="NO"
)
(
input clk_i,
input rst_i,
input [0:0] bus0_bank0_req_i,
input [0:0] bus0_bank0_we_i,
input [31:0] bus0_bank0_addr_bi,
input [3:0] bus0_bank0_be_bi,
input [31:0] bus0_bank0_wdata_bi,
output reg [0:0] bus0_bank0_ack_o,
output reg [0:0] bus0_bank0_resp_o,
output reg [31:0] bus0_bank0_rdata_bo,
input [0:0] bus0_bank1_req_i,
input [0:0] bus0_bank1_we_i,
input [31:0] bus0_bank1_addr_bi,
input [3:0] bus0_bank1_be_bi,
input [31:0] bus0_bank1_wdata_bi,
output reg [0:0] bus0_bank1_ack_o,
output reg [0:0] bus0_bank1_resp_o,
output reg [31:0] bus0_bank1_rdata_bo,
input [0:0] bus1_bank0_req_i,
input [0:0] bus1_bank0_we_i,
input [31:0] bus1_bank0_addr_bi,
input [3:0] bus1_bank0_be_bi,
input [31:0] bus1_bank0_wdata_bi,
output reg [0:0] bus1_bank0_ack_o,
output reg [0:0] bus1_bank0_resp_o,
output reg [31:0] bus1_bank0_rdata_bo,
input [0:0] bus1_bank1_req_i,
input [0:0] bus1_bank1_we_i,
input [31:0] bus1_bank1_addr_bi,
input [3:0] bus1_bank1_be_bi,
input [31:0] bus1_bank1_wdata_bi,
output reg [0:0] bus1_bank1_ack_o,
output reg [0:0] bus1_bank1_resp_o,
output reg [31:0] bus1_bank1_rdata_bo
);
reg bus0_bank0_wb, bus0_bank0_wb_next;
reg bus0_bank1_wb, bus0_bank1_wb_next;
reg bus1_bank0_wb, bus1_bank0_wb_next;
reg bus1_bank1_wb, bus1_bank1_wb_next;
always @(posedge clk_i) bus0_bank0_wb <= rst_i ? 1'b0 : bus0_bank0_wb_next;
always @(posedge clk_i) bus0_bank1_wb <= rst_i ? 1'b0 : bus0_bank1_wb_next;
always @(posedge clk_i) bus1_bank0_wb <= rst_i ? 1'b0 : bus1_bank0_wb_next;
always @(posedge clk_i) bus1_bank1_wb <= rst_i ? 1'b0 : bus1_bank1_wb_next;
reg [31:0] bus0_bank0_addr, bus0_bank0_addr_buf;
reg [3:0] bus0_bank0_be, bus0_bank0_be_buf;
reg bus0_bank0_we;
reg [31:0] bus0_bank0_wdata, bus0_bank0_wdata_buf;
reg bus0_bank0_resp, bus0_bank0_resp_next;
wire [31:0] bus0_bank0_rdata;
reg [31:0] bus0_bank1_addr, bus0_bank1_addr_buf;
reg [3:0] bus0_bank1_be, bus0_bank1_be_buf;
reg bus0_bank1_we;
reg [31:0] bus0_bank1_wdata, bus0_bank1_wdata_buf;
reg bus0_bank1_resp, bus0_bank1_resp_next;
wire [31:0] bus0_bank1_rdata;
reg [31:0] bus1_bank0_addr, bus1_bank0_addr_buf;
reg [3:0] bus1_bank0_be, bus1_bank0_be_buf;
reg bus1_bank0_we;
reg [31:0] bus1_bank0_wdata, bus1_bank0_wdata_buf;
reg bus1_bank0_resp, bus1_bank0_resp_next;
wire [31:0] bus1_bank0_rdata;
reg [31:0] bus1_bank1_addr, bus1_bank1_addr_buf;
reg [3:0] bus1_bank1_be, bus1_bank1_be_buf;
reg bus1_bank1_we;
reg [31:0] bus1_bank1_wdata, bus1_bank1_wdata_buf;
reg bus1_bank1_resp, bus1_bank1_resp_next;
wire [31:0] bus1_bank1_rdata;
reg bus0_rdata_xchg, bus0_rdata_xchg_next;
reg bus1_rdata_xchg, bus1_rdata_xchg_next;
always @(posedge clk_i) bus0_bank0_resp <= rst_i ? 0 : bus0_bank0_resp_next;
always @(posedge clk_i) bus0_bank1_resp <= rst_i ? 0 : bus0_bank1_resp_next;
always @(posedge clk_i) bus1_bank0_resp <= rst_i ? 0 : bus1_bank0_resp_next;
always @(posedge clk_i) bus1_bank1_resp <= rst_i ? 0 : bus1_bank1_resp_next;
always @(posedge clk_i) bus0_rdata_xchg <= rst_i ? 0 : bus0_rdata_xchg_next;
always @(posedge clk_i) bus1_rdata_xchg <= rst_i ? 0 : bus1_rdata_xchg_next;
wire bus0_bank0_we_mask;
wire bus0_bank1_we_mask;
wire bus1_bank0_we_mask;
wire bus1_bank1_we_mask;
assign bus0_bank0_we_mask = bus0_bank0_req_i & bus0_bank0_we_i;
assign bus0_bank1_we_mask = bus0_bank1_req_i & bus0_bank1_we_i;
assign bus1_bank0_we_mask = bus1_bank0_req_i & bus1_bank0_we_i;
assign bus1_bank1_we_mask = bus1_bank1_req_i & bus1_bank1_we_i;
wire bus0_bank0_we_fullword;
wire bus0_bank1_we_fullword;
wire bus1_bank0_we_fullword;
wire bus1_bank1_we_fullword;
assign bus0_bank0_we_fullword = bus0_bank0_we_mask & (bus0_bank0_be_bi == 4'hf);
assign bus0_bank1_we_fullword = bus0_bank1_we_mask & (bus0_bank1_be_bi == 4'hf);
assign bus1_bank0_we_fullword = bus1_bank0_we_mask & (bus1_bank0_be_bi == 4'hf);
assign bus1_bank1_we_fullword = bus1_bank1_we_mask & (bus1_bank1_be_bi == 4'hf);
wire bus0_bank0_we_nfullword;
wire bus0_bank1_we_nfullword;
wire bus1_bank0_we_nfullword;
wire bus1_bank1_we_nfullword;
assign bus0_bank0_we_nfullword = bus0_bank0_we_mask & (bus0_bank0_be_bi != 4'hf);
assign bus0_bank1_we_nfullword = bus0_bank1_we_mask & (bus0_bank1_be_bi != 4'hf);
assign bus1_bank0_we_nfullword = bus1_bank0_we_mask & (bus1_bank0_be_bi != 4'hf);
assign bus1_bank1_we_nfullword = bus1_bank1_we_mask & (bus1_bank1_be_bi != 4'hf);
always @*
begin
bus0_bank0_wb_next = 1'b0;
bus0_bank1_wb_next = 1'b0;
bus0_bank0_addr = bus0_bank0_addr_bi;
bus0_bank0_we = bus0_bank0_we_fullword;
bus0_bank0_be = bus0_bank0_be_bi;
bus0_bank0_wdata = bus0_bank0_wdata_bi;
bus0_bank0_ack_o = bus0_bank0_req_i & !bus0_bank0_wb;
if (P0_FRAC=="YES") bus0_bank0_wb_next = bus0_bank0_we_nfullword & !bus0_bank0_wb;
bus0_bank0_resp_next = bus0_bank0_req_i & !bus0_bank0_we;
bus0_bank1_addr = bus0_bank1_addr_bi;
bus0_bank1_we = bus0_bank1_we_fullword;
bus0_bank1_be = bus0_bank1_be_bi;
bus0_bank1_wdata = bus0_bank1_wdata_bi;
bus0_bank1_ack_o = bus0_bank1_req_i & !bus0_bank1_wb;
if (P0_FRAC=="YES") bus0_bank1_wb_next = bus0_bank1_we_nfullword & !bus0_bank1_wb;
bus0_bank1_resp_next = bus0_bank1_req_i & !bus0_bank1_we;
bus0_rdata_xchg_next = 1'b0;
if (bus0_bank0_req_i)
begin
if (bus0_bank0_addr_bi[2])
begin
bus0_bank1_addr = bus0_bank0_addr_bi;
bus0_bank1_we = bus0_bank0_we_fullword;
bus0_bank1_be = bus0_bank0_be_bi;
bus0_bank1_wdata = bus0_bank0_wdata_bi;
bus0_bank0_we = 1'b0;
bus0_bank0_ack_o = bus0_bank0_req_i & !bus0_bank1_wb;
if (P0_FRAC=="YES") bus0_bank0_wb_next = 1'b0;
if (P0_FRAC=="YES") bus0_bank1_wb_next = bus0_bank0_we_nfullword & !bus0_bank1_wb;
bus0_bank0_resp_next = 1'b0;
bus0_bank1_resp_next = bus0_bank0_req_i & !bus0_bank0_we;
bus0_rdata_xchg_next = 1'b1;
end
end
if (bus0_bank1_req_i)
begin
if (bus0_bank0_req_i && (bus0_bank0_addr_bi[2] == bus0_bank1_addr_bi[2]))
begin
bus0_bank1_ack_o = 1'b0;
if (!bus0_bank1_addr_bi[2]) bus0_bank1_resp_next = 1'b0;
end
else if (!bus0_bank1_addr_bi[2])
begin
bus0_bank0_addr = bus0_bank1_addr_bi;
bus0_bank0_we = bus0_bank1_we_fullword;
bus0_bank0_be = bus0_bank1_be_bi;
bus0_bank0_wdata = bus0_bank1_wdata_bi;
bus0_bank1_ack_o = bus0_bank1_req_i & !bus0_bank0_wb;
if (P0_FRAC=="YES") bus0_bank0_wb_next = bus0_bank1_we_nfullword & !bus0_bank0_wb;
bus0_bank0_resp_next = bus0_bank1_req_i & !bus0_bank1_we;
if (!bus0_bank0_req_i) bus0_bank1_resp_next = 1'b0;
bus0_rdata_xchg_next = 1'b1;
end
end
if (P0_FRAC=="YES")
begin
if (bus0_bank0_wb)
begin
bus0_bank0_addr = bus0_bank0_addr_buf;
bus0_bank0_we = 1'b1;
bus0_bank0_wdata = bus0_bank0_rdata;
case (bus0_bank0_addr_buf[1:0])
2'd0 :
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[7:0] = bus0_bank0_wdata_buf[7:0];
if (bus0_bank0_be_buf[1]) bus0_bank0_wdata[15:8] = bus0_bank0_wdata_buf[15:8];
if (bus0_bank0_be_buf[2]) bus0_bank0_wdata[23:16] = bus0_bank0_wdata_buf[23:16];
if (bus0_bank0_be_buf[3]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[31:24];
end
2'd1:
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[15:8] = bus0_bank0_wdata_buf[7:0];
if (bus0_bank0_be_buf[1]) bus0_bank0_wdata[23:16] = bus0_bank0_wdata_buf[15:8];
if (bus0_bank0_be_buf[2]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[23:16];
end
2'd2:
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[23:16] = bus0_bank0_wdata_buf[7:0];
if (bus0_bank0_be_buf[1]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[15:8];
end
2'd3:
begin
if (bus0_bank0_be_buf[0]) bus0_bank0_wdata[31:24] = bus0_bank0_wdata_buf[7:0];
end
endcase
end
if (bus0_bank1_wb)
begin
bus0_bank1_addr = bus0_bank1_addr_buf;
bus0_bank1_we = 1'b1;
bus0_bank1_wdata = bus0_bank1_rdata;
case (bus0_bank1_addr_buf[1:0])
2'd0 :
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[7:0] = bus0_bank1_wdata_buf[7:0];
if (bus0_bank1_be_buf[1]) bus0_bank1_wdata[15:8] = bus0_bank1_wdata_buf[15:8];
if (bus0_bank1_be_buf[2]) bus0_bank1_wdata[23:16] = bus0_bank1_wdata_buf[23:16];
if (bus0_bank1_be_buf[3]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[31:24];
end
2'd1:
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[15:8] = bus0_bank1_wdata_buf[7:0];
if (bus0_bank1_be_buf[1]) bus0_bank1_wdata[23:16] = bus0_bank1_wdata_buf[15:8];
if (bus0_bank1_be_buf[2]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[23:16];
end
2'd2:
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[23:16] = bus0_bank1_wdata_buf[7:0];
if (bus0_bank1_be_buf[1]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[15:8];
end
2'd3:
begin
if (bus0_bank1_be_buf[0]) bus0_bank1_wdata[31:24] = bus0_bank1_wdata_buf[7:0];
end
endcase
end
end
end
always @*
begin
bus1_bank0_wb_next = 1'b0;
bus1_bank1_wb_next = 1'b0;
bus1_bank0_addr = bus1_bank0_addr_bi;
bus1_bank0_we = bus1_bank0_we_fullword;
bus1_bank0_be = bus1_bank0_be_bi;
bus1_bank0_wdata = bus1_bank0_wdata_bi;
bus1_bank0_ack_o = bus1_bank0_req_i & !bus1_bank0_wb;
if (P1_FRAC=="YES") bus1_bank0_wb_next = bus1_bank0_we_nfullword & !bus1_bank0_wb;
bus1_bank0_resp_next = bus1_bank0_req_i & !bus1_bank0_we;
bus1_bank1_addr = bus1_bank1_addr_bi;
bus1_bank1_we = bus1_bank1_we_fullword;
bus1_bank1_be = bus1_bank1_be_bi;
bus1_bank1_wdata = bus1_bank1_wdata_bi;
bus1_bank1_ack_o = bus1_bank1_req_i & !bus1_bank1_wb;
if (P1_FRAC=="YES") bus1_bank1_wb_next = bus1_bank1_we_nfullword & !bus1_bank1_wb;
bus1_bank1_resp_next = bus1_bank1_req_i & !bus1_bank1_we;
bus1_rdata_xchg_next = 1'b0;
if (bus1_bank0_req_i)
begin
if (bus1_bank0_addr_bi[2])
begin
bus1_bank1_addr = bus1_bank0_addr_bi;
bus1_bank1_we = bus1_bank0_we_fullword;
bus1_bank1_be = bus1_bank0_be_bi;
bus1_bank1_wdata = bus1_bank0_wdata_bi;
bus1_bank0_we = 1'b0;
bus1_bank0_ack_o = bus1_bank0_req_i & !bus1_bank1_wb;
if (P1_FRAC=="YES") bus1_bank0_wb_next = 1'b0;
if (P1_FRAC=="YES") bus1_bank1_wb_next = bus1_bank0_we_nfullword & !bus1_bank1_wb;
bus1_bank0_resp_next = 1'b0;
bus1_bank1_resp_next = bus1_bank0_req_i & !bus1_bank0_we;
bus1_rdata_xchg_next = 1'b1;
end
end
if (bus1_bank1_req_i)
begin
if (bus1_bank0_req_i && (bus1_bank0_addr_bi[2] == bus1_bank1_addr_bi[2]))
begin
bus1_bank1_ack_o = 1'b0;
if (!bus1_bank1_addr_bi[2]) bus1_bank1_resp_next = 1'b0;
end
else if (!bus1_bank1_addr_bi[2])
begin
bus1_bank0_addr = bus1_bank1_addr_bi;
bus1_bank0_we = bus1_bank1_we_fullword;
bus1_bank0_be = bus1_bank1_be_bi;
bus1_bank0_wdata = bus1_bank1_wdata_bi;
bus1_bank1_ack_o = bus1_bank1_req_i & !bus1_bank0_wb;
if (P1_FRAC=="YES") bus1_bank0_wb_next = bus1_bank1_we_nfullword & !bus1_bank0_wb;
bus1_bank0_resp_next = bus1_bank1_req_i & !bus1_bank1_we;
if (!bus1_bank0_req_i) bus1_bank1_resp_next = 1'b0;
bus1_rdata_xchg_next = 1'b1;
end
end
if (P1_FRAC=="YES")
begin
if (bus1_bank0_wb)
begin
bus1_bank0_addr = bus1_bank0_addr_buf;
bus1_bank0_we = 1'b1;
bus1_bank0_wdata = bus1_bank0_rdata;
case (bus1_bank0_addr_buf[1:0])
2'd0 :
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[7:0] = bus1_bank0_wdata_buf[7:0];
if (bus1_bank0_be_buf[1]) bus1_bank0_wdata[15:8] = bus1_bank0_wdata_buf[15:8];
if (bus1_bank0_be_buf[2]) bus1_bank0_wdata[23:16] = bus1_bank0_wdata_buf[23:16];
if (bus1_bank0_be_buf[3]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[31:24];
end
2'd1:
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[15:8] = bus1_bank0_wdata_buf[7:0];
if (bus1_bank0_be_buf[1]) bus1_bank0_wdata[23:16] = bus1_bank0_wdata_buf[15:8];
if (bus1_bank0_be_buf[2]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[23:16];
end
2'd2:
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[23:16] = bus1_bank0_wdata_buf[7:0];
if (bus1_bank0_be_buf[1]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[15:8];
end
2'd3:
begin
if (bus1_bank0_be_buf[0]) bus1_bank0_wdata[31:24] = bus1_bank0_wdata_buf[7:0];
end
endcase
end
if (bus1_bank1_wb)
begin
bus1_bank1_addr = bus1_bank1_addr_buf;
bus1_bank1_we = 1'b1;
bus1_bank1_wdata = bus1_bank1_rdata;
case (bus1_bank1_addr_buf[1:0])
2'd0 :
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[7:0] = bus1_bank1_wdata_buf[7:0];
if (bus1_bank1_be_buf[1]) bus1_bank1_wdata[15:8] = bus1_bank1_wdata_buf[15:8];
if (bus1_bank1_be_buf[2]) bus1_bank1_wdata[23:16] = bus1_bank1_wdata_buf[23:16];
if (bus1_bank1_be_buf[3]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[31:24];
end
2'd1:
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[15:8] = bus1_bank1_wdata_buf[7:0];
if (bus1_bank1_be_buf[1]) bus1_bank1_wdata[23:16] = bus1_bank1_wdata_buf[15:8];
if (bus1_bank1_be_buf[2]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[23:16];
end
2'd2:
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[23:16] = bus1_bank1_wdata_buf[7:0];
if (bus1_bank1_be_buf[1]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[15:8];
end
2'd3:
begin
if (bus1_bank1_be_buf[0]) bus1_bank1_wdata[31:24] = bus1_bank1_wdata_buf[7:0];
end
endcase
end
end
end
always @*
begin
bus0_bank0_resp_o = bus0_bank0_resp;
bus0_bank1_resp_o = bus0_bank1_resp;
bus0_bank0_rdata_bo = bus0_bank0_rdata;
bus0_bank1_rdata_bo = bus0_bank1_rdata;
if (P0_FRAC == "YES")
begin
if (bus0_bank0_addr_buf[1:0] == 2'd1) bus0_bank0_rdata_bo = bus0_bank0_rdata >> 8;
if (bus0_bank0_addr_buf[1:0] == 2'd2) bus0_bank0_rdata_bo = bus0_bank0_rdata >> 16;
if (bus0_bank0_addr_buf[1:0] == 2'd3) bus0_bank0_rdata_bo = bus0_bank0_rdata >> 24;
if (bus0_bank1_addr_buf[1:0] == 2'd1) bus0_bank1_rdata_bo = bus0_bank1_rdata >> 8;
if (bus0_bank1_addr_buf[1:0] == 2'd2) bus0_bank1_rdata_bo = bus0_bank1_rdata >> 16;
if (bus0_bank1_addr_buf[1:0] == 2'd3) bus0_bank1_rdata_bo = bus0_bank1_rdata >> 24;
end
if (bus0_rdata_xchg)
begin
{bus0_bank0_resp_o, bus0_bank1_resp_o} = {bus0_bank1_resp_o, bus0_bank0_resp_o};
{bus0_bank0_rdata_bo, bus0_bank1_rdata_bo} = {bus0_bank1_rdata_bo, bus0_bank0_rdata_bo};
end
end
always @*
begin
bus1_bank0_resp_o = bus1_bank0_resp;
bus1_bank1_resp_o = bus1_bank1_resp;
bus1_bank0_rdata_bo = bus1_bank0_rdata;
bus1_bank1_rdata_bo = bus1_bank1_rdata;
if (P1_FRAC == "YES")
begin
if (bus1_bank0_addr_buf[1:0] == 2'd1) bus1_bank0_rdata_bo = bus1_bank0_rdata >> 8;
if (bus1_bank0_addr_buf[1:0] == 2'd2) bus1_bank0_rdata_bo = bus1_bank0_rdata >> 16;
if (bus1_bank0_addr_buf[1:0] == 2'd3) bus1_bank0_rdata_bo = bus1_bank0_rdata >> 24;
if (bus1_bank1_addr_buf[1:0] == 2'd1) bus1_bank1_rdata_bo = bus1_bank1_rdata >> 8;
if (bus1_bank1_addr_buf[1:0] == 2'd2) bus1_bank1_rdata_bo = bus1_bank1_rdata >> 16;
if (bus1_bank1_addr_buf[1:0] == 2'd3) bus1_bank1_rdata_bo = bus1_bank1_rdata >> 24;
end
if (bus1_rdata_xchg)
begin
{bus1_bank0_resp_o, bus1_bank1_resp_o} = {bus1_bank1_resp_o, bus1_bank0_resp_o};
{bus1_bank0_rdata_bo, bus1_bank1_rdata_bo} = {bus1_bank1_rdata_bo, bus1_bank0_rdata_bo};
end
end
always @(posedge clk_i)
begin
bus0_bank0_addr_buf <= bus0_bank0_addr;
bus0_bank0_be_buf <= bus0_bank0_be;
bus0_bank0_wdata_buf <= bus0_bank0_wdata;
bus0_bank1_addr_buf <= bus0_bank1_addr;
bus0_bank1_be_buf <= bus0_bank1_be;
bus0_bank1_wdata_buf <= bus0_bank1_wdata;
end
always @(posedge clk_i)
begin
bus1_bank0_addr_buf <= bus1_bank0_addr;
bus1_bank0_be_buf <= bus1_bank0_be;
bus1_bank0_wdata_buf <= bus1_bank0_wdata;
bus1_bank1_addr_buf <= bus1_bank1_addr;
bus1_bank1_be_buf <= bus1_bank1_be;
bus1_bank1_wdata_buf <= bus1_bank1_wdata;
end
ram_dual
#(
.init_type("none")
, .init_data("nodata.hex")
, .dat_width(dat_width)
, .adr_width(adr_width-1)
, .mem_size(mem_size >> 1)
) ram_dual_bank0 (
.clk(clk_i)
, .dat0_i(bus0_bank0_wdata)
, .adr0_i(bus0_bank0_addr[31:3])
, .we0_i(bus0_bank0_we)
, .dat0_o(bus0_bank0_rdata)
, .dat1_i(bus1_bank0_wdata)
, .adr1_i(bus1_bank0_addr[31:3])
, .we1_i(bus1_bank0_we)
, .dat1_o(bus1_bank0_rdata)
);
ram_dual
#(
.init_type("none")
, .init_data("nodata.hex")
, .dat_width(dat_width)
, .adr_width(adr_width-1)
, .mem_size(mem_size >> 1)
) ram_dual_bank1 (
.clk(clk_i)
, .dat0_i(bus0_bank1_wdata)
, .adr0_i(bus0_bank1_addr[31:3])
, .we0_i(bus0_bank1_we)
, .dat0_o(bus0_bank1_rdata)
, .dat1_i(bus1_bank1_wdata)
, .adr1_i(bus1_bank1_addr[31:3])
, .we1_i(bus1_bank1_we)
, .dat1_o(bus1_bank1_rdata)
);
// elf processing
integer File_ID, Rd_Status;
reg [7:0] File_Rdata [0 : (mem_size * (dat_width / 8)) - 1] ;
integer File_ptr, header_idx;
integer e_machine, e_phnum, p_offset, p_vaddr, p_filesz, elf_param;
integer bytes_in_word, load_byte_counter;
integer ram_ptr, wrword_byte_counter;
reg [dat_width-1:0] wrword;
reg [8*8:0] e_machine_str;
initial
begin
if (init_type != "none")
begin
if (init_type == "elf")
begin
File_ID = $fopen(init_data, "rb");
Rd_Status = $fread(File_Rdata, File_ID);
if (Rd_Status == 0) $fatal("File %s not found!", init_data);
$display("\n##################################");
$display("#### Loading elf file: %s", init_data);
// parsing ELF header
if ((File_Rdata[0] != 8'h7f) || (File_Rdata[1] != 8'h45) || (File_Rdata[2] != 8'h4c) || (File_Rdata[3] != 8'h46)) $fatal("%s: elf format incorrect!", init_data);
e_machine = File_Rdata[18] + (File_Rdata[19] << 8);
e_machine_str = "UNKNOWN";
if (e_machine == 32'hF3) e_machine_str = "RISC-V";
$display("e_machine: 0x%x (%s)", e_machine, e_machine_str);
e_phnum = File_Rdata[44] + (File_Rdata[45] << 8);
$display("e_phnum: 0x%x", e_phnum);
File_ptr = 52;
for (header_idx = 0; header_idx < e_phnum; header_idx = header_idx + 1)
begin
// parsing program header
$display("---- HEADER: %0d ----", header_idx);
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_type: 0x%x", elf_param);
File_ptr = File_ptr + 4;
p_offset = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_offset: 0x%x", p_offset);
File_ptr = File_ptr + 4;
p_vaddr = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_vaddr: 0x%x", p_vaddr);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_paddr: 0x%x", elf_param);
File_ptr = File_ptr + 4;
p_filesz = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_filesz: 0x%x", p_filesz);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_memsz: 0x%x", elf_param);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_flags: 0x%x", elf_param);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_align: 0x%x", elf_param);
File_ptr = File_ptr + 4;
// loading segment to memory
bytes_in_word = dat_width / 8;
for (load_byte_counter = 0; load_byte_counter < p_filesz; load_byte_counter = load_byte_counter + bytes_in_word)
begin
wrword = 0;
for (wrword_byte_counter = 0; wrword_byte_counter < bytes_in_word; wrword_byte_counter = wrword_byte_counter + 1)
begin
wrword = {File_Rdata[p_offset + load_byte_counter + wrword_byte_counter], wrword[dat_width-1:8]};
end
ram_ptr = (p_vaddr + load_byte_counter) / bytes_in_word;
if (ram_ptr[0] == 1'b0) ram_dual_bank0.ram[ram_ptr >> 1] = wrword;
else ram_dual_bank1.ram[ram_ptr >> 1] = wrword;
end
end
$display("##################################\n");
$fclose(File_ID);
end
else $fatal("init_type parameter incorrect!");
end
end
endmodule
|
module tb_gmii2fifo72();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg phy_rx_dv;
reg [7:0] phy_rxd;
wire [71:0] din;
wire full;
wire wr_en;
wire wr_clk;
gmii2fifo72 # (
.Gap(4'h2)
) gmii2fifo72_tb (
.sys_rst(sys_rst),
.gmii_rx_clk(phy_rx_clk),
.gmii_rx_dv(phy_rx_dv),
.gmii_rxd(phy_rxd),
.din(din),
.full(full),
.wr_en(wr_en),
.wr_clk(wr_clk)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge wr_clk) begin
if (wr_en == 1'b1)
$display("din: %x", din);
end
reg [11:0] rom [0:199];
reg [11:0] counter;
always @(posedge phy_rx_clk) begin
{phy_rx_dv,phy_rxd} <= rom[ counter ];
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_gmii2fifo72);
$readmemh("./phy_rx.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file wr_fifo32to256.v when simulating
// the core, wr_fifo32to256. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module wr_fifo32to256(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output empty;
output [9 : 0] rd_data_count;
output [12 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(13),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("8kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(8191),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(8190),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(13),
.C_WR_DEPTH(8192),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(13),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram
(
data,
rdaddress,
wraddress,
wren, clock,
q
);
parameter DATA_WIDTH=36;
parameter ADDR_WIDTH=8;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
input wren, clock;
output reg [(DATA_WIDTH-1):0] q;
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clock)
begin
if (wren)
ram[wraddress] <= data[DATA_WIDTH-1:0];
q <= ram[rdaddress];
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_shift_reg_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 11;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./fir_shift_reg_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_shift_reg(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd11;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_shift_reg_ram fir_shift_reg_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
q0, q1, q2, q3, q4, q5, q6a, q6b,
// Inputs
clk, d, rst0_n
);
input clk;
input d;
// OK -- from primary
input rst0_n;
output wire q0;
Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
// OK -- from flop
reg rst1_n;
always @ (posedge clk) rst1_n <= rst0_n;
output wire q1;
Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
// Bad - logic
wire rst2_bad_n = rst0_n | rst1_n;
output wire q2;
Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d));
// Bad - logic in submodule
wire rst3_bad_n;
Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n));
output wire q3;
Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d));
// OK - bit selection
reg [3:0] rst4_n;
always @ (posedge clk) rst4_n <= {4{rst0_n}};
output wire q4;
Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d));
// Bad - logic, but waived
// verilator lint_off CDCRSTLOGIC
wire rst5_waive_n = rst0_n & rst1_n;
// verilator lint_on CDCRSTLOGIC
output wire q5;
Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d));
// Bad - for graph test - logic feeds two signals, three destinations
wire rst6_bad_n = rst0_n ^ rst1_n;
wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization
wire rst6b_bad_n = rst6_bad_n ^ $c1("1");
output wire q6a;
output wire q6b;
Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d));
Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d));
initial begin
$display("%%Error: Not a runnable test");
$stop;
end
endmodule
module Flop (
input clk,
input d,
input rst_n,
output logic q);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) q <= 1'b0;
else q <= d;
end
endmodule
module Sub (input a, b,
output z);
assign z = a|b;
endmodule
|
/*
* CRTC controller for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_crtc_fml (
input clk, // 100 Mhz clock
input rst,
input enable_crtc,
// CRTC configuration signals
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
input [6:0] horiz_total,
input [6:0] end_horiz,
input [6:0] st_hor_retr,
input [4:0] end_hor_retr,
input [9:0] vert_total,
input [9:0] end_vert,
input [9:0] st_ver_retr,
input [3:0] end_ver_retr,
// CRTC output signals
output reg [9:0] h_count, // Horizontal pipeline delay is 2 cycles
output reg horiz_sync_i,
output reg [9:0] v_count, // 0 to VER_SCAN_END
output reg vert_sync,
output reg video_on_h_i,
output reg video_on_v
);
// Registers and nets
wire [9:0] hor_disp_end;
wire [9:0] hor_scan_end;
wire [9:0] ver_disp_end;
wire [9:0] ver_sync_beg;
wire [3:0] ver_sync_end;
wire [9:0] ver_scan_end;
// Continuous assignments
assign hor_scan_end = { horiz_total[6:2] + 1'b1, horiz_total[1:0], 3'h7 };
assign hor_disp_end = { end_horiz, 3'h7 };
assign ver_scan_end = vert_total + 10'd1;
assign ver_disp_end = end_vert + 10'd1;
assign ver_sync_beg = st_ver_retr;
assign ver_sync_end = end_ver_retr + 4'd1;
// Sync generation & timing process
// Generate horizontal and vertical timing signals for video signal
always @(posedge clk)
if (rst)
begin
h_count <= 10'b0;
horiz_sync_i <= 1'b1;
v_count <= 10'b0;
vert_sync <= 1'b1;
video_on_h_i <= 1'b1;
video_on_v <= 1'b1;
end
else
if (enable_crtc)
begin
h_count <= (h_count==hor_scan_end) ? 10'b0 : h_count + 10'b1;
horiz_sync_i <= horiz_sync_i ? (h_count[9:3]!=st_hor_retr)
: (h_count[7:3]==end_hor_retr);
v_count <= (v_count==ver_scan_end && h_count==hor_scan_end) ? 10'b0
: ((h_count==hor_scan_end) ? v_count + 10'b1 : v_count);
vert_sync <= vert_sync ? (v_count!=ver_sync_beg)
: (v_count[3:0]==ver_sync_end);
video_on_h_i <= (h_count==hor_scan_end) ? 1'b1
: ((h_count==hor_disp_end) ? 1'b0 : video_on_h_i);
video_on_v <= (v_count==10'h0) ? 1'b1
: ((v_count==ver_disp_end) ? 1'b0 : video_on_v);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_Add_Subt();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
`ifdef SINGLE
FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 uut(
.clk(clk),
.rst(rst),
.beg_FSM(beg_FSM),
.ack_FSM(ack_FSM),
.Data_X(Data_X),
.Data_Y(Data_Y),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready),
.final_result_ieee(final_result_ieee)
);
`endif
`ifdef DOUBLE
FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 uut(
.clk(clk),
.rst(rst),
.beg_FSM(beg_FSM),
.ack_FSM(ack_FSM),
.Data_X(Data_X),
.Data_Y(Data_Y),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready),
.final_result_ieee(final_result_ieee)
);
`endif
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
add_subt = 0;
// // Wait 100 ns for global reset to finish
// #100 rst = 0;
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
// Wait 100 ns for global reset to finish
#100 rst = 0;
//Add stimulus here
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_FSM = 0;
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Cont_CLK = Cont_CLK + 1;
ack_FSM = 0;
end
else if(Cont_CLK ==2) begin
ack_FSM = 0;
beg_FSM = 1;
Cont_CLK = Cont_CLK +1 ;
end
else begin
ack_FSM = 0;
Cont_CLK = Cont_CLK + 1;
beg_FSM = 0;
end
if(ready==1) begin
ack_FSM = 1;
Cont_CLK = 0;
end
if(ready==1 && ack_FSM) begin
Cont_CLK = 0;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
//initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A2BB2O_PP_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_PP_SYMBOL_V
|
//`timescale 1 ns / 100 ps
module dv_emmu
(input clk,
input reset,
input go);
parameter DW = 32; //data width of
parameter AW = 32; //data width of
parameter IW = 12; //index size of table
parameter PAW = 64; //physical address width of output
parameter MW = PAW-AW+IW; //table data width
parameter MD = 1<<IW; //memory depth
//Stimulus to drive
reg mmu_en;
//Reg interface
reg mi_en;
reg [12:0] mi_addr;
reg [31:0] mi_din;
reg [3:0] mi_we;
//emesh interface
reg emesh_access_in;
reg emesh_write_in;
reg [1:0] emesh_datamode_in;
reg [3:0] emesh_ctrlmode_in;
reg [AW-1:0] emesh_dstaddr_in;
reg [AW-1:0] emesh_srcaddr_in;
reg [DW-1:0] emesh_data_in;
//Test junk
reg [1:0] test_state;
//Pattern generator
//1.) Write some patterns through mi_interface
//2.) Write some patterns from emesh interface
always @ (negedge clk) begin
if(go)
begin
case(test_state[1:0])
2'b00://write entries
if(mi_addr[12:0]<13'h16)
begin
mi_en <= 1'b1;
mi_we[3:0] <= 4'b1111;
mi_addr[12:0] <= mi_addr[12:0] + 1'b1;
/* verilator lint_off WIDTH */
mi_din[31:0] <= mi_addr[0] ? (mi_addr[12:0]+32'hFFFFF000) : 32'hFFFFFFFF;
/* verilator lint_on WIDTH */
end
else
begin
test_state <= 2'b01;
mi_en <= 1'b0;
end
2'b01://
if(emesh_dstaddr_in[31:0]<32'h00800000)
begin
emesh_access_in <= 1'b1;
emesh_write_in <= 1'b1;
emesh_dstaddr_in[31:0] <= emesh_dstaddr_in[31:0] + 32'h00100001;
emesh_ctrlmode_in[3:0] <= 4'b1111;
emesh_datamode_in[1:0] <= 2'b11;
emesh_data_in[31:0] <= 32'h12345678;
emesh_srcaddr_in[31:0] <= 32'h55555555;
end
else
begin
test_state <= 2'b10;
emesh_access_in <= 1'b0;
end // else: !if(~done)
2'b10://init array
begin
mi_addr[5:0] <= mi_addr[5:0]-1'b1;
end
default : test_state <= test_state;
endcase // case (test_state[1:0])
end // if (go)
if (reset) begin
mi_we[3:0] <= 4'b0;
mi_en <= 1'b0;
mi_addr[12:0] <= 13'b0;
mi_din[31:0] <= 32'h55555000;
test_state[1:0] <= 2'b00;
emesh_access_in <= 1'b0;
emesh_write_in <= 1'b0;
emesh_ctrlmode_in[3:0] <= 4'b0;
emesh_datamode_in[1:0] <= 2'b0;
emesh_dstaddr_in[31:0] <= 32'b0;
emesh_srcaddr_in[31:0] <= 32'b0;
emesh_data_in[31:0] <= 32'b0;
mmu_en <= 1'b1;
end
end
wire done = (mi_addr[5:0]==6'b001101);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire emmu_access_out; // From emmu of emmu.v
wire [3:0] emmu_ctrlmode_out; // From emmu of emmu.v
wire [DW-1:0] emmu_data_out; // From emmu of emmu.v
wire [1:0] emmu_datamode_out; // From emmu of emmu.v
wire [63:0] emmu_dstaddr_out; // From emmu of emmu.v
wire [AW-1:0] emmu_srcaddr_out; // From emmu of emmu.v
wire emmu_write_out; // From emmu of emmu.v
wire [31:0] mi_dout; // From emmu of emmu.v
// End of automatics
/*AUTOWIRE*/
//DUT
emmu emmu(.mi_clk (clk),
/*AUTOINST*/
// Outputs
.mi_dout (mi_dout[31:0]),
.emmu_access_out (emmu_access_out),
.emmu_write_out (emmu_write_out),
.emmu_datamode_out (emmu_datamode_out[1:0]),
.emmu_ctrlmode_out (emmu_ctrlmode_out[3:0]),
.emmu_dstaddr_out (emmu_dstaddr_out[63:0]),
.emmu_srcaddr_out (emmu_srcaddr_out[AW-1:0]),
.emmu_data_out (emmu_data_out[DW-1:0]),
// Inputs
.clk (clk),
.mmu_en (mmu_en),
.mi_en (mi_en),
.mi_we (mi_we[3:0]),
.mi_addr ({3'b000,mi_addr[12:0]}),
.mi_din (mi_din[31:0]),
.emesh_access_in (emesh_access_in),
.emesh_write_in (emesh_write_in),
.emesh_datamode_in (emesh_datamode_in[1:0]),
.emesh_ctrlmode_in (emesh_ctrlmode_in[3:0]),
.emesh_dstaddr_in (emesh_dstaddr_in[AW-1:0]),
.emesh_srcaddr_in (emesh_srcaddr_in[AW-1:0]),
.emesh_data_in (emesh_data_in[DW-1:0]));
endmodule // dv_emmu
// Local Variables:
// verilog-library-directories:("." "../hdl")
// End:
|
// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the fifo_generator wrapper file when simulating
// the core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule
|
(* abc9_lut=1 *)
module LUT1(output F, input I0);
parameter [1:0] INIT = 0;
specify
(I0 => F) = (555, 902);
endspecify
assign F = I0 ? INIT[1] : INIT[0];
endmodule
(* abc9_lut=1 *)
module LUT2(output F, input I0, I1);
parameter [3:0] INIT = 0;
specify
(I0 => F) = (867, 1184);
(I1 => F) = (555, 902);
endspecify
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=1 *)
module LUT3(output F, input I0, I1, I2);
parameter [7:0] INIT = 0;
specify
(I0 => F) = (1054, 1486);
(I1 => F) = (867, 1184);
(I2 => F) = (555, 902);
endspecify
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=1 *)
module LUT4(output F, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
specify
(I0 => F) = (1054, 1486);
(I1 => F) = (1053, 1583);
(I2 => F) = (867, 1184);
(I3 => F) = (555, 902);
endspecify
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=2 *)
module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);
specify
(I0 => F) = (1187, 1638);
(I1 => F) = (1184, 1638);
(I2 => F) = (995, 1371);
(I3 => F) = (808, 1116);
(M0 => F) = (486, 680);
endspecify
endmodule
(* abc9_lut=4 *)
module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);
specify
(I0 => F) = (1187 + 136, 1638 + 255);
(I1 => F) = (1184 + 136, 1638 + 255);
(I2 => F) = (995 + 136, 1371 + 255);
(I3 => F) = (808 + 136, 1116 + 255);
(M0 => F) = (486 + 136, 680 + 255);
(M1 => F) = (478, 723);
endspecify
endmodule
(* abc9_lut=8 *)
module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);
specify
(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);
(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);
(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);
(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);
(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);
(M1 => F) = (478 + 136, 723 + 255);
(M2 => F) = (478, 723);
endspecify
endmodule
(* abc9_lut=16 *)
module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);
specify
(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);
(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);
(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);
(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);
(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);
(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);
(M2 => F) = (478 + 136, 723 + 255);
(M3 => F) = (478, 723);
endspecify
endmodule
module MUX2 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (141, 160);
(I1 => O) = (141, 160);
(S0 => O) = (486, 680);
endspecify
assign O = S0 ? I1 : I0;
endmodule
module MUX2_LUT5 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (141, 160);
(I1 => O) = (141, 160);
(S0 => O) = (486, 680);
endspecify
MUX2 mux2_lut5 (O, I0, I1, S0);
endmodule
module MUX2_LUT6 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (136, 255);
(I1 => O) = (136, 255);
(S0 => O) = (478, 723);
endspecify
MUX2 mux2_lut6 (O, I0, I1, S0);
endmodule
module MUX2_LUT7 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (136, 255);
(I1 => O) = (136, 255);
(S0 => O) = (478, 723);
endspecify
MUX2 mux2_lut7 (O, I0, I1, S0);
endmodule
module MUX2_LUT8 (O, I0, I1, S0);
input I0,I1;
input S0;
output O;
specify
(I0 => O) = (136, 255);
(I1 => O) = (136, 255);
(S0 => O) = (478, 723);
endspecify
MUX2 mux2_lut8 (O, I0, I1, S0);
endmodule
(* abc9_flop, lib_whitebox *)
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK, 576);
endspecify
always @(posedge CLK)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module DFFE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (CE)
Q <= D;
end
endmodule // DFFE (positive clock edge; clock enable)
(* abc9_box, lib_whitebox *)
module DFFS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK, 576);
$setup(SET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (SET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFS (positive clock edge; synchronous set)
(* abc9_box, lib_whitebox *)
module DFFSE (output reg Q, input D, CLK, CE, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
$setup(SET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (SET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
(* abc9_flop, lib_whitebox *)
module DFFR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK, 576);
$setup(RESET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFR (positive clock edge; synchronous reset)
(* abc9_flop, lib_whitebox *)
module DFFRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
$setup(RESET, posedge CLK, 63);
endspecify
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
(* abc9_box, lib_whitebox *)
module DFFP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, posedge CLK, 576);
endspecify
always @(posedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFP (positive clock edge; asynchronous preset)
(* abc9_box, lib_whitebox *)
module DFFPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
endspecify
always @(posedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
(* abc9_box, lib_whitebox *)
module DFFC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(posedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, posedge CLK, 576);
endspecify
always @(posedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFC (positive clock edge; asynchronous clear)
(* abc9_box, lib_whitebox *)
module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (posedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, posedge CLK &&& CE, 576);
$setup(CE, posedge CLK, 63);
endspecify
always @(posedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
(* abc9_flop, lib_whitebox *)
module DFFN (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
endspecify
always @(negedge CLK)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module DFFNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (CE)
Q <= D;
end
endmodule // DFFNE (negative clock edge; clock enable)
(* abc9_box, lib_whitebox *)
module DFFNS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
$setup(SET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (SET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFNS (negative clock edge; synchronous set)
(* abc9_box, lib_whitebox *)
module DFFNSE (output reg Q, input D, CLK, CE, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
$setup(SET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (SET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
(* abc9_flop, lib_whitebox *)
module DFFNR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
$setup(RESET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (RESET)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFNR (negative clock edge; synchronous reset)
(* abc9_flop, lib_whitebox *)
module DFFNRE (output reg Q, input D, CLK, CE, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
$setup(RESET, negedge CLK, 63);
endspecify
always @(negedge CLK) begin
if (RESET)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
(* abc9_box, lib_whitebox *)
module DFFNP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, negedge CLK, 576);
endspecify
always @(negedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else
Q <= D;
end
endmodule // DFFNP (negative clock edge; asynchronous preset)
(* abc9_box, lib_whitebox *)
module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(posedge PRESET => (Q : 1'b1)) = (1800, 2679);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
endspecify
always @(negedge CLK or posedge PRESET) begin
if(PRESET)
Q <= 1'b1;
else if (CE)
Q <= D;
end
endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
(* abc9_box, lib_whitebox *)
module DFFNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, negedge CLK, 576);
endspecify
always @(negedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFNC (negative clock edge; asynchronous clear)
(* abc9_box, lib_whitebox *)
module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
$setup(D, negedge CLK &&& CE, 576);
$setup(CE, negedge CLK, 63);
endspecify
always @(negedge CLK or posedge CLEAR) begin
if(CLEAR)
Q <= 1'b0;
else if (CE)
Q <= D;
end
endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
// TODO add more DFF sim cells
module VCC(output V);
assign V = 1;
endmodule
module GND(output G);
assign G = 0;
endmodule
module IBUF(output O, input I);
specify
(I => O) = 0;
endspecify
assign O = I;
endmodule
module OBUF(output O, input I);
specify
(I => O) = 0;
endspecify
assign O = I;
endmodule
module TBUF (O, I, OEN);
input I, OEN;
output O;
assign O = OEN ? 1'bz : I;
endmodule
module IOBUF (O, IO, I, OEN);
input I,OEN;
output O;
inout IO;
assign IO = OEN ? 1'bz : I;
assign I = IO;
endmodule
module TLVDS_OBUF (I, O, OB);
input I;
output O;
output OB;
assign O = I;
assign OB = ~I;
endmodule
(* blackbox *)
module ODDR(D0, D1, TX, CLK, Q0, Q1);
input D0;
input D1;
input TX;
input CLK;
output Q0;
output Q1;
parameter TXCLK_POL = 0;
parameter INIT = 0;
endmodule
(* blackbox *)
module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
input D0;
input D1;
input CLEAR;
input TX;
input CLK;
output Q0;
output Q1;
parameter TXCLK_POL = 0;
parameter INIT = 0;
endmodule
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule
(* abc9_box, lib_whitebox *)
module ALU (SUM, COUT, I0, I1, I3, CIN);
input I0;
input I1;
input I3;
(* abc9_carry *) input CIN;
output SUM;
(* abc9_carry *) output COUT;
localparam ADD = 0;
localparam SUB = 1;
localparam ADDSUB = 2;
localparam NE = 3;
localparam GE = 4;
localparam LE = 5;
localparam CUP = 6;
localparam CDN = 7;
localparam CUPCDN = 8;
localparam MULT = 9;
parameter ALU_MODE = 0;
reg S, C;
specify
(I0 => SUM) = (1043, 1432);
(I1 => SUM) = (775, 1049);
(I3 => SUM) = (751, 1010);
(CIN => SUM) = (694, 811);
(I0 => COUT) = (1010, 1380);
(I1 => COUT) = (1021, 1505);
(I3 => COUT) = (483, 792);
(CIN => COUT) = (49, 82);
endspecify
assign SUM = S ^ CIN;
assign COUT = S? CIN : C;
always @* begin
case (ALU_MODE)
ADD: begin
S = I0 ^ I1;
C = I0;
end
SUB: begin
S = I0 ^ ~I1;
C = I0;
end
ADDSUB: begin
S = I3? I0 ^ I1 : I0 ^ ~I1;
C = I0;
end
NE: begin
S = I0 ^ ~I1;
C = 1'b1;
end
GE: begin
S = I0 ^ ~I1;
C = I0;
end
LE: begin
S = ~I0 ^ I1;
C = I1;
end
CUP: begin
S = I0;
C = 1'b0;
end
CDN: begin
S = ~I0;
C = 1'b1;
end
CUPCDN: begin
S = I3? I0 : ~I0;
C = I0;
end
MULT: begin
S = I0 & I1;
C = I0 & I1;
end
endcase
end
endmodule
module RAM16S1 (DO, DI, AD, WRE, CLK);
parameter INIT_0 = 16'h0000;
input [3:0] AD;
input DI;
output DO;
input CLK;
input WRE;
specify
(AD *> DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(AD, posedge CLK, 62);
(posedge CLK => (DO : 1'bx)) = (474, 565);
endspecify
reg [15:0] mem;
initial begin
mem = INIT_0;
end
assign DO = mem[AD];
always @(posedge CLK) begin
if (WRE) begin
mem[AD] <= DI;
end
end
endmodule
module RAM16S2 (DO, DI, AD, WRE, CLK);
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
input [3:0] AD;
input [1:0] DI;
output [1:0] DO;
input CLK;
input WRE;
specify
(AD *> DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(AD, posedge CLK, 62);
(posedge CLK => (DO : 2'bx)) = (474, 565);
endspecify
reg [15:0] mem0, mem1;
initial begin
mem0 = INIT_0;
mem1 = INIT_1;
end
assign DO[0] = mem0[AD];
assign DO[1] = mem1[AD];
always @(posedge CLK) begin
if (WRE) begin
mem0[AD] <= DI[0];
mem1[AD] <= DI[1];
end
end
endmodule
module RAM16S4 (DO, DI, AD, WRE, CLK);
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
parameter INIT_2 = 16'h0000;
parameter INIT_3 = 16'h0000;
input [3:0] AD;
input [3:0] DI;
output [3:0] DO;
input CLK;
input WRE;
specify
(AD *> DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(AD, posedge CLK, 62);
(posedge CLK => (DO : 4'bx)) = (474, 565);
endspecify
reg [15:0] mem0, mem1, mem2, mem3;
initial begin
mem0 = INIT_0;
mem1 = INIT_1;
mem2 = INIT_2;
mem3 = INIT_3;
end
assign DO[0] = mem0[AD];
assign DO[1] = mem1[AD];
assign DO[2] = mem2[AD];
assign DO[3] = mem3[AD];
always @(posedge CLK) begin
if (WRE) begin
mem0[AD] <= DI[0];
mem1[AD] <= DI[1];
mem2[AD] <= DI[2];
mem3[AD] <= DI[3];
end
end
endmodule
module RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);
parameter INIT_0 = 16'h0000;
input [3:0] WAD;
input [3:0] RAD;
input DI;
output DO;
input CLK;
input WRE;
specify
(RAD *> DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(WAD, posedge CLK, 62);
(posedge CLK => (DO : 1'bx)) = (474, 565);
endspecify
reg [15:0] mem;
initial begin
mem = INIT_0;
end
assign DO = mem[RAD];
always @(posedge CLK) begin
if (WRE) begin
mem[WAD] <= DI;
end
end
endmodule
module RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
input [3:0] WAD;
input [3:0] RAD;
input [1:0] DI;
output [1:0] DO;
input CLK;
input WRE;
specify
(RAD *> DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(WAD, posedge CLK, 62);
(posedge CLK => (DO : 2'bx)) = (474, 565);
endspecify
reg [15:0] mem0, mem1;
initial begin
mem0 = INIT_0;
mem1 = INIT_1;
end
assign DO[0] = mem0[RAD];
assign DO[1] = mem1[RAD];
always @(posedge CLK) begin
if (WRE) begin
mem0[WAD] <= DI[0];
mem1[WAD] <= DI[1];
end
end
endmodule
module RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
parameter INIT_2 = 16'h0000;
parameter INIT_3 = 16'h0000;
input [3:0] WAD;
input [3:0] RAD;
input [3:0] DI;
output [3:0] DO;
input CLK;
input WRE;
specify
(RAD *> DO) = (270, 405);
$setup(DI, posedge CLK, 62);
$setup(WRE, posedge CLK, 62);
$setup(WAD, posedge CLK, 62);
(posedge CLK => (DO : 4'bx)) = (474, 565);
endspecify
reg [15:0] mem0, mem1, mem2, mem3;
initial begin
mem0 = INIT_0;
mem1 = INIT_1;
mem2 = INIT_2;
mem3 = INIT_3;
end
assign DO[0] = mem0[RAD];
assign DO[1] = mem1[RAD];
assign DO[2] = mem2[RAD];
assign DO[3] = mem3[RAD];
always @(posedge CLK) begin
if (WRE) begin
mem0[WAD] <= DI[0];
mem1[WAD] <= DI[1];
mem2[WAD] <= DI[2];
mem3[WAD] <= DI[3];
end
end
endmodule
(* blackbox *)
module SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);
// 1 Enables output pipeline registers.
parameter READ_MODE = 1'b0;
// 0: no read on write, 1: transparent, 2: read-before-write
parameter WRITE_MODE = 2'b00;
parameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0;
parameter INIT_RAM_01 = 256'h0;
parameter INIT_RAM_02 = 256'h0;
parameter INIT_RAM_03 = 256'h0;
parameter INIT_RAM_04 = 256'h0;
parameter INIT_RAM_05 = 256'h0;
parameter INIT_RAM_06 = 256'h0;
parameter INIT_RAM_07 = 256'h0;
parameter INIT_RAM_08 = 256'h0;
parameter INIT_RAM_09 = 256'h0;
parameter INIT_RAM_0A = 256'h0;
parameter INIT_RAM_0B = 256'h0;
parameter INIT_RAM_0C = 256'h0;
parameter INIT_RAM_0D = 256'h0;
parameter INIT_RAM_0E = 256'h0;
parameter INIT_RAM_0F = 256'h0;
parameter INIT_RAM_10 = 256'h0;
parameter INIT_RAM_11 = 256'h0;
parameter INIT_RAM_12 = 256'h0;
parameter INIT_RAM_13 = 256'h0;
parameter INIT_RAM_14 = 256'h0;
parameter INIT_RAM_15 = 256'h0;
parameter INIT_RAM_16 = 256'h0;
parameter INIT_RAM_17 = 256'h0;
parameter INIT_RAM_18 = 256'h0;
parameter INIT_RAM_19 = 256'h0;
parameter INIT_RAM_1A = 256'h0;
parameter INIT_RAM_1B = 256'h0;
parameter INIT_RAM_1C = 256'h0;
parameter INIT_RAM_1D = 256'h0;
parameter INIT_RAM_1E = 256'h0;
parameter INIT_RAM_1F = 256'h0;
parameter INIT_RAM_20 = 256'h0;
parameter INIT_RAM_21 = 256'h0;
parameter INIT_RAM_22 = 256'h0;
parameter INIT_RAM_23 = 256'h0;
parameter INIT_RAM_24 = 256'h0;
parameter INIT_RAM_25 = 256'h0;
parameter INIT_RAM_26 = 256'h0;
parameter INIT_RAM_27 = 256'h0;
parameter INIT_RAM_28 = 256'h0;
parameter INIT_RAM_29 = 256'h0;
parameter INIT_RAM_2A = 256'h0;
parameter INIT_RAM_2B = 256'h0;
parameter INIT_RAM_2C = 256'h0;
parameter INIT_RAM_2D = 256'h0;
parameter INIT_RAM_2E = 256'h0;
parameter INIT_RAM_2F = 256'h0;
parameter INIT_RAM_30 = 256'h0;
parameter INIT_RAM_31 = 256'h0;
parameter INIT_RAM_32 = 256'h0;
parameter INIT_RAM_33 = 256'h0;
parameter INIT_RAM_34 = 256'h0;
parameter INIT_RAM_35 = 256'h0;
parameter INIT_RAM_36 = 256'h0;
parameter INIT_RAM_37 = 256'h0;
parameter INIT_RAM_38 = 256'h0;
parameter INIT_RAM_39 = 256'h0;
parameter INIT_RAM_3A = 256'h0;
parameter INIT_RAM_3B = 256'h0;
parameter INIT_RAM_3C = 256'h0;
parameter INIT_RAM_3D = 256'h0;
parameter INIT_RAM_3E = 256'h0;
parameter INIT_RAM_3F = 256'h0;
output [31:0] DO;
input [31:0] DI;
input [2:0] BLKSEL;
input [13:0] AD;
input WRE;
input CLK;
input CE;
input OCE;
input RESET;
endmodule
(* blackbox *)
module SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);
// 1 Enables output pipeline registers.
parameter READ_MODE = 1'b0;
// 0: no read on write, 1: transparent, 2: read-before-write
parameter WRITE_MODE = 2'b00;
parameter BIT_WIDTH = 36; // 9, 18, 36
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h0;
parameter INIT_RAM_01 = 288'h0;
parameter INIT_RAM_02 = 288'h0;
parameter INIT_RAM_03 = 288'h0;
parameter INIT_RAM_04 = 288'h0;
parameter INIT_RAM_05 = 288'h0;
parameter INIT_RAM_06 = 288'h0;
parameter INIT_RAM_07 = 288'h0;
parameter INIT_RAM_08 = 288'h0;
parameter INIT_RAM_09 = 288'h0;
parameter INIT_RAM_0A = 288'h0;
parameter INIT_RAM_0B = 288'h0;
parameter INIT_RAM_0C = 288'h0;
parameter INIT_RAM_0D = 288'h0;
parameter INIT_RAM_0E = 288'h0;
parameter INIT_RAM_0F = 288'h0;
parameter INIT_RAM_10 = 288'h0;
parameter INIT_RAM_11 = 288'h0;
parameter INIT_RAM_12 = 288'h0;
parameter INIT_RAM_13 = 288'h0;
parameter INIT_RAM_14 = 288'h0;
parameter INIT_RAM_15 = 288'h0;
parameter INIT_RAM_16 = 288'h0;
parameter INIT_RAM_17 = 288'h0;
parameter INIT_RAM_18 = 288'h0;
parameter INIT_RAM_19 = 288'h0;
parameter INIT_RAM_1A = 288'h0;
parameter INIT_RAM_1B = 288'h0;
parameter INIT_RAM_1C = 288'h0;
parameter INIT_RAM_1D = 288'h0;
parameter INIT_RAM_1E = 288'h0;
parameter INIT_RAM_1F = 288'h0;
parameter INIT_RAM_20 = 288'h0;
parameter INIT_RAM_21 = 288'h0;
parameter INIT_RAM_22 = 288'h0;
parameter INIT_RAM_23 = 288'h0;
parameter INIT_RAM_24 = 288'h0;
parameter INIT_RAM_25 = 288'h0;
parameter INIT_RAM_26 = 288'h0;
parameter INIT_RAM_27 = 288'h0;
parameter INIT_RAM_28 = 288'h0;
parameter INIT_RAM_29 = 288'h0;
parameter INIT_RAM_2A = 288'h0;
parameter INIT_RAM_2B = 288'h0;
parameter INIT_RAM_2C = 288'h0;
parameter INIT_RAM_2D = 288'h0;
parameter INIT_RAM_2E = 288'h0;
parameter INIT_RAM_2F = 288'h0;
parameter INIT_RAM_30 = 288'h0;
parameter INIT_RAM_31 = 288'h0;
parameter INIT_RAM_32 = 288'h0;
parameter INIT_RAM_33 = 288'h0;
parameter INIT_RAM_34 = 288'h0;
parameter INIT_RAM_35 = 288'h0;
parameter INIT_RAM_36 = 288'h0;
parameter INIT_RAM_37 = 288'h0;
parameter INIT_RAM_38 = 288'h0;
parameter INIT_RAM_39 = 288'h0;
parameter INIT_RAM_3A = 288'h0;
parameter INIT_RAM_3B = 288'h0;
parameter INIT_RAM_3C = 288'h0;
parameter INIT_RAM_3D = 288'h0;
parameter INIT_RAM_3E = 288'h0;
parameter INIT_RAM_3F = 288'h0;
output [35:0] DO;
input [35:0] DI;
input [2:0] BLKSEL;
input [13:0] AD;
input WRE;
input CLK;
input CE;
input OCE;
input RESET;
endmodule
(* blackbox *)
module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0;
parameter INIT_RAM_01 = 256'h0;
parameter INIT_RAM_02 = 256'h0;
parameter INIT_RAM_03 = 256'h0;
parameter INIT_RAM_04 = 256'h0;
parameter INIT_RAM_05 = 256'h0;
parameter INIT_RAM_06 = 256'h0;
parameter INIT_RAM_07 = 256'h0;
parameter INIT_RAM_08 = 256'h0;
parameter INIT_RAM_09 = 256'h0;
parameter INIT_RAM_0A = 256'h0;
parameter INIT_RAM_0B = 256'h0;
parameter INIT_RAM_0C = 256'h0;
parameter INIT_RAM_0D = 256'h0;
parameter INIT_RAM_0E = 256'h0;
parameter INIT_RAM_0F = 256'h0;
parameter INIT_RAM_10 = 256'h0;
parameter INIT_RAM_11 = 256'h0;
parameter INIT_RAM_12 = 256'h0;
parameter INIT_RAM_13 = 256'h0;
parameter INIT_RAM_14 = 256'h0;
parameter INIT_RAM_15 = 256'h0;
parameter INIT_RAM_16 = 256'h0;
parameter INIT_RAM_17 = 256'h0;
parameter INIT_RAM_18 = 256'h0;
parameter INIT_RAM_19 = 256'h0;
parameter INIT_RAM_1A = 256'h0;
parameter INIT_RAM_1B = 256'h0;
parameter INIT_RAM_1C = 256'h0;
parameter INIT_RAM_1D = 256'h0;
parameter INIT_RAM_1E = 256'h0;
parameter INIT_RAM_1F = 256'h0;
parameter INIT_RAM_20 = 256'h0;
parameter INIT_RAM_21 = 256'h0;
parameter INIT_RAM_22 = 256'h0;
parameter INIT_RAM_23 = 256'h0;
parameter INIT_RAM_24 = 256'h0;
parameter INIT_RAM_25 = 256'h0;
parameter INIT_RAM_26 = 256'h0;
parameter INIT_RAM_27 = 256'h0;
parameter INIT_RAM_28 = 256'h0;
parameter INIT_RAM_29 = 256'h0;
parameter INIT_RAM_2A = 256'h0;
parameter INIT_RAM_2B = 256'h0;
parameter INIT_RAM_2C = 256'h0;
parameter INIT_RAM_2D = 256'h0;
parameter INIT_RAM_2E = 256'h0;
parameter INIT_RAM_2F = 256'h0;
parameter INIT_RAM_30 = 256'h0;
parameter INIT_RAM_31 = 256'h0;
parameter INIT_RAM_32 = 256'h0;
parameter INIT_RAM_33 = 256'h0;
parameter INIT_RAM_34 = 256'h0;
parameter INIT_RAM_35 = 256'h0;
parameter INIT_RAM_36 = 256'h0;
parameter INIT_RAM_37 = 256'h0;
parameter INIT_RAM_38 = 256'h0;
parameter INIT_RAM_39 = 256'h0;
parameter INIT_RAM_3A = 256'h0;
parameter INIT_RAM_3B = 256'h0;
parameter INIT_RAM_3C = 256'h0;
parameter INIT_RAM_3D = 256'h0;
parameter INIT_RAM_3E = 256'h0;
parameter INIT_RAM_3F = 256'h0;
output [31:0] DO;
input [31:0] DI;
input [2:0] BLKSEL;
input [13:0] ADA, ADB;
input WREA, WREB;
input CLKA, CLKB;
input CEA, CEB;
input OCE;
input RESETA, RESETB;
specify
(posedge CLKB => (DO : DI)) = (419, 493);
$setup(RESETA, posedge CLKA, 62);
$setup(RESETB, posedge CLKB, 62);
$setup(OCE, posedge CLKB, 62);
$setup(CEA, posedge CLKA, 62);
$setup(CEB, posedge CLKB, 62);
$setup(OCE, posedge CLKB, 62);
$setup(WREA, posedge CLKA, 62);
$setup(WREB, posedge CLKB, 62);
$setup(DI, posedge CLKA, 62);
$setup(ADA, posedge CLKA, 62);
$setup(ADB, posedge CLKB, 62);
$setup(BLKSEL, posedge CLKA, 62);
endspecify
endmodule
(* blackbox *)
module SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36; // 9, 18, 36
parameter BIT_WIDTH_1 = 36; // 9, 18, 36
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h0;
parameter INIT_RAM_01 = 288'h0;
parameter INIT_RAM_02 = 288'h0;
parameter INIT_RAM_03 = 288'h0;
parameter INIT_RAM_04 = 288'h0;
parameter INIT_RAM_05 = 288'h0;
parameter INIT_RAM_06 = 288'h0;
parameter INIT_RAM_07 = 288'h0;
parameter INIT_RAM_08 = 288'h0;
parameter INIT_RAM_09 = 288'h0;
parameter INIT_RAM_0A = 288'h0;
parameter INIT_RAM_0B = 288'h0;
parameter INIT_RAM_0C = 288'h0;
parameter INIT_RAM_0D = 288'h0;
parameter INIT_RAM_0E = 288'h0;
parameter INIT_RAM_0F = 288'h0;
parameter INIT_RAM_10 = 288'h0;
parameter INIT_RAM_11 = 288'h0;
parameter INIT_RAM_12 = 288'h0;
parameter INIT_RAM_13 = 288'h0;
parameter INIT_RAM_14 = 288'h0;
parameter INIT_RAM_15 = 288'h0;
parameter INIT_RAM_16 = 288'h0;
parameter INIT_RAM_17 = 288'h0;
parameter INIT_RAM_18 = 288'h0;
parameter INIT_RAM_19 = 288'h0;
parameter INIT_RAM_1A = 288'h0;
parameter INIT_RAM_1B = 288'h0;
parameter INIT_RAM_1C = 288'h0;
parameter INIT_RAM_1D = 288'h0;
parameter INIT_RAM_1E = 288'h0;
parameter INIT_RAM_1F = 288'h0;
parameter INIT_RAM_20 = 288'h0;
parameter INIT_RAM_21 = 288'h0;
parameter INIT_RAM_22 = 288'h0;
parameter INIT_RAM_23 = 288'h0;
parameter INIT_RAM_24 = 288'h0;
parameter INIT_RAM_25 = 288'h0;
parameter INIT_RAM_26 = 288'h0;
parameter INIT_RAM_27 = 288'h0;
parameter INIT_RAM_28 = 288'h0;
parameter INIT_RAM_29 = 288'h0;
parameter INIT_RAM_2A = 288'h0;
parameter INIT_RAM_2B = 288'h0;
parameter INIT_RAM_2C = 288'h0;
parameter INIT_RAM_2D = 288'h0;
parameter INIT_RAM_2E = 288'h0;
parameter INIT_RAM_2F = 288'h0;
parameter INIT_RAM_30 = 288'h0;
parameter INIT_RAM_31 = 288'h0;
parameter INIT_RAM_32 = 288'h0;
parameter INIT_RAM_33 = 288'h0;
parameter INIT_RAM_34 = 288'h0;
parameter INIT_RAM_35 = 288'h0;
parameter INIT_RAM_36 = 288'h0;
parameter INIT_RAM_37 = 288'h0;
parameter INIT_RAM_38 = 288'h0;
parameter INIT_RAM_39 = 288'h0;
parameter INIT_RAM_3A = 288'h0;
parameter INIT_RAM_3B = 288'h0;
parameter INIT_RAM_3C = 288'h0;
parameter INIT_RAM_3D = 288'h0;
parameter INIT_RAM_3E = 288'h0;
parameter INIT_RAM_3F = 288'h0;
output [35:0] DO;
input [35:0] DI;
input [2:0] BLKSEL;
input [13:0] ADA, ADB;
input WREA, WREB;
input CLKA, CLKB;
input CEA, CEB;
input OCE;
input RESETA, RESETB;
specify
(posedge CLKB => (DO : DI)) = (419, 493);
$setup(RESETA, posedge CLKA, 62);
$setup(RESETB, posedge CLKB, 62);
$setup(OCE, posedge CLKB, 62);
$setup(CEA, posedge CLKA, 62);
$setup(CEB, posedge CLKB, 62);
$setup(OCE, posedge CLKB, 62);
$setup(WREA, posedge CLKA, 62);
$setup(WREB, posedge CLKB, 62);
$setup(DI, posedge CLKA, 62);
$setup(ADA, posedge CLKA, 62);
$setup(ADB, posedge CLKB, 62);
$setup(BLKSEL, posedge CLKA, 62);
endspecify
endmodule
(* blackbox *)
module DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16
parameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0;
parameter INIT_RAM_01 = 256'h0;
parameter INIT_RAM_02 = 256'h0;
parameter INIT_RAM_03 = 256'h0;
parameter INIT_RAM_04 = 256'h0;
parameter INIT_RAM_05 = 256'h0;
parameter INIT_RAM_06 = 256'h0;
parameter INIT_RAM_07 = 256'h0;
parameter INIT_RAM_08 = 256'h0;
parameter INIT_RAM_09 = 256'h0;
parameter INIT_RAM_0A = 256'h0;
parameter INIT_RAM_0B = 256'h0;
parameter INIT_RAM_0C = 256'h0;
parameter INIT_RAM_0D = 256'h0;
parameter INIT_RAM_0E = 256'h0;
parameter INIT_RAM_0F = 256'h0;
parameter INIT_RAM_10 = 256'h0;
parameter INIT_RAM_11 = 256'h0;
parameter INIT_RAM_12 = 256'h0;
parameter INIT_RAM_13 = 256'h0;
parameter INIT_RAM_14 = 256'h0;
parameter INIT_RAM_15 = 256'h0;
parameter INIT_RAM_16 = 256'h0;
parameter INIT_RAM_17 = 256'h0;
parameter INIT_RAM_18 = 256'h0;
parameter INIT_RAM_19 = 256'h0;
parameter INIT_RAM_1A = 256'h0;
parameter INIT_RAM_1B = 256'h0;
parameter INIT_RAM_1C = 256'h0;
parameter INIT_RAM_1D = 256'h0;
parameter INIT_RAM_1E = 256'h0;
parameter INIT_RAM_1F = 256'h0;
parameter INIT_RAM_20 = 256'h0;
parameter INIT_RAM_21 = 256'h0;
parameter INIT_RAM_22 = 256'h0;
parameter INIT_RAM_23 = 256'h0;
parameter INIT_RAM_24 = 256'h0;
parameter INIT_RAM_25 = 256'h0;
parameter INIT_RAM_26 = 256'h0;
parameter INIT_RAM_27 = 256'h0;
parameter INIT_RAM_28 = 256'h0;
parameter INIT_RAM_29 = 256'h0;
parameter INIT_RAM_2A = 256'h0;
parameter INIT_RAM_2B = 256'h0;
parameter INIT_RAM_2C = 256'h0;
parameter INIT_RAM_2D = 256'h0;
parameter INIT_RAM_2E = 256'h0;
parameter INIT_RAM_2F = 256'h0;
parameter INIT_RAM_30 = 256'h0;
parameter INIT_RAM_31 = 256'h0;
parameter INIT_RAM_32 = 256'h0;
parameter INIT_RAM_33 = 256'h0;
parameter INIT_RAM_34 = 256'h0;
parameter INIT_RAM_35 = 256'h0;
parameter INIT_RAM_36 = 256'h0;
parameter INIT_RAM_37 = 256'h0;
parameter INIT_RAM_38 = 256'h0;
parameter INIT_RAM_39 = 256'h0;
parameter INIT_RAM_3A = 256'h0;
parameter INIT_RAM_3B = 256'h0;
parameter INIT_RAM_3C = 256'h0;
parameter INIT_RAM_3D = 256'h0;
parameter INIT_RAM_3E = 256'h0;
parameter INIT_RAM_3F = 256'h0;
output [15:0] DOA, DOB;
input [15:0] DIA, DIB;
input [2:0] BLKSEL;
input [13:0] ADA, ADB;
input WREA, WREB;
input CLKA, CLKB;
input CEA, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
endmodule
(* blackbox *)
module DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18; // 9, 18
parameter BIT_WIDTH_1 = 18; // 9, 18
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h0;
parameter INIT_RAM_01 = 288'h0;
parameter INIT_RAM_02 = 288'h0;
parameter INIT_RAM_03 = 288'h0;
parameter INIT_RAM_04 = 288'h0;
parameter INIT_RAM_05 = 288'h0;
parameter INIT_RAM_06 = 288'h0;
parameter INIT_RAM_07 = 288'h0;
parameter INIT_RAM_08 = 288'h0;
parameter INIT_RAM_09 = 288'h0;
parameter INIT_RAM_0A = 288'h0;
parameter INIT_RAM_0B = 288'h0;
parameter INIT_RAM_0C = 288'h0;
parameter INIT_RAM_0D = 288'h0;
parameter INIT_RAM_0E = 288'h0;
parameter INIT_RAM_0F = 288'h0;
parameter INIT_RAM_10 = 288'h0;
parameter INIT_RAM_11 = 288'h0;
parameter INIT_RAM_12 = 288'h0;
parameter INIT_RAM_13 = 288'h0;
parameter INIT_RAM_14 = 288'h0;
parameter INIT_RAM_15 = 288'h0;
parameter INIT_RAM_16 = 288'h0;
parameter INIT_RAM_17 = 288'h0;
parameter INIT_RAM_18 = 288'h0;
parameter INIT_RAM_19 = 288'h0;
parameter INIT_RAM_1A = 288'h0;
parameter INIT_RAM_1B = 288'h0;
parameter INIT_RAM_1C = 288'h0;
parameter INIT_RAM_1D = 288'h0;
parameter INIT_RAM_1E = 288'h0;
parameter INIT_RAM_1F = 288'h0;
parameter INIT_RAM_20 = 288'h0;
parameter INIT_RAM_21 = 288'h0;
parameter INIT_RAM_22 = 288'h0;
parameter INIT_RAM_23 = 288'h0;
parameter INIT_RAM_24 = 288'h0;
parameter INIT_RAM_25 = 288'h0;
parameter INIT_RAM_26 = 288'h0;
parameter INIT_RAM_27 = 288'h0;
parameter INIT_RAM_28 = 288'h0;
parameter INIT_RAM_29 = 288'h0;
parameter INIT_RAM_2A = 288'h0;
parameter INIT_RAM_2B = 288'h0;
parameter INIT_RAM_2C = 288'h0;
parameter INIT_RAM_2D = 288'h0;
parameter INIT_RAM_2E = 288'h0;
parameter INIT_RAM_2F = 288'h0;
parameter INIT_RAM_30 = 288'h0;
parameter INIT_RAM_31 = 288'h0;
parameter INIT_RAM_32 = 288'h0;
parameter INIT_RAM_33 = 288'h0;
parameter INIT_RAM_34 = 288'h0;
parameter INIT_RAM_35 = 288'h0;
parameter INIT_RAM_36 = 288'h0;
parameter INIT_RAM_37 = 288'h0;
parameter INIT_RAM_38 = 288'h0;
parameter INIT_RAM_39 = 288'h0;
parameter INIT_RAM_3A = 288'h0;
parameter INIT_RAM_3B = 288'h0;
parameter INIT_RAM_3C = 288'h0;
parameter INIT_RAM_3D = 288'h0;
parameter INIT_RAM_3E = 288'h0;
parameter INIT_RAM_3F = 288'h0;
output [17:0] DOA, DOB;
input [17:0] DIA, DIB;
input [2:0] BLKSEL;
input [13:0] ADA, ADB;
input WREA, WREB;
input CLKA, CLKB;
input CEA, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
endmodule
(* blackbox *)
module rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);
input CLKIN;
input CLKFB;
input RESET;
input RESET_P;
input [5:0] FBDSEL;
input [5:0] IDSEL;
input [5:0] ODSEL;
input [3:0] PSDA,FDLY;
input [3:0] DUTYDA;
output CLKOUT;
output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0"; // frequency of CLKIN
parameter DYN_IDIV_SEL= "false"; // true:IDSEL, false:IDIV_SEL
parameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64
parameter DYN_FBDIV_SEL= "false"; // true:FBDSEL, false:FBDIV_SEL
parameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64
parameter DYN_ODIV_SEL= "false"; // true:ODSEL, false:ODIV_SEL
parameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false"; // true:PSDA or DUTYDA or FDA, false: DA_SEL
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only
parameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only
parameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4
parameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2
parameter CLKFB_SEL = "internal"; // "internal", "external"
parameter CLKOUT_BYPASS = "false"; // "true", "false"
parameter CLKOUTP_BYPASS = "false"; // "true", "false"
parameter CLKOUTD_BYPASS = "false"; // "true", "false"
parameter DYN_SDIV_SEL = 2; // 2~128, only even numbers
parameter CLKOUTD_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
parameter CLKOUTD3_SRC = "CLKOUT"; // CLKOUT, CLKOUTP
parameter DEVICE = "GW1N-1"; // "GW1N-1", "GW1N-4", "GW1N-9", "GW1NR-4", "GW1NR-9", "GW1N-4B", "GW1NR-4B", "GW1NS-2", "GW1NS-2C", "GW1NZ-1", "GW1NSR-2", "GW1NSR-2C", "GW1N-1S", "GW1NSE-2C", "GW1NRF-4B", "GW1N-9C", "GW1NR-9C", "GW1N-4C", "GW1NR-4C"
endmodule
(* blackbox *)
module OSC(OSCOUT);
output OSCOUT;
parameter FREQ_DIV = 100;
parameter DEVICE = "GW1N-4";
endmodule
(* blackbox *)
module OSCZ(OSCOUT, OSCEN);
input OSCEN;
output OSCOUT;
parameter FREQ_DIV = 100;
endmodule
(* blackbox *)
module OSCF(OSCOUT, OSCOUT30M, OSCEN);
input OSCEN;
output OSCOUT;
output OSCOUT30M;
parameter FREQ_DIV = 100;
endmodule
(* blackbox *)
module OSCH(OSCOUT);
output OSCOUT;
parameter FREQ_DIV = 96;
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
//rd0 - 128/64/32 bits wide (can be unaligned)
//rd1 - 32 bits wide
//rd2 - 32 bits wide
//wr0 - 128/64/32 bits wide (4 bit enable) (can be unaligned)
module reg_1024x32b_3r_1w (/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_data, clk
);
output [127:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [9:0] rd0_addr;
input [9:0] rd1_addr;
input [9:0] rd2_addr;
input [9:0] wr0_addr;
input [3:0] wr0_en;
input [127:0] wr0_data;
input clk;
/////////////////////////////////////////
reg [127:0] rd0_data;
reg [31:0] rd1_data;
reg [31:0] rd2_data;
/////////////////////////////////////////
//Muxing for rd0
wire [9:0] rd0_addr_plus1;
wire [9:0] rd0_addr_plus2;
wire [9:0] rd0_addr_plus3;
assign rd0_addr_plus1 = rd0_addr + 1'b1;
assign rd0_addr_plus2 = rd0_addr + 2'b10;
assign rd0_addr_plus3 = rd0_addr + 2'b11;
wire [31:0] rd0_data_bank0;
wire [31:0] rd0_data_bank1;
wire [31:0] rd0_data_bank2;
wire [31:0] rd0_data_bank3;
reg [7:0] rd0_addr_bank0;
reg [7:0] rd0_addr_bank1;
reg [7:0] rd0_addr_bank2;
reg [7:0] rd0_addr_bank3;
wire [9:0] rd0_addr_last;
wire [9:0] rd1_addr_last;
wire [9:0] rd2_addr_last;
dff rd_addr_data_path_delay[10+10+10-1:0]
(.q({rd0_addr_last, rd1_addr_last, rd2_addr_last}),
.d({rd0_addr, rd1_addr, rd2_addr}),
.clk(clk),
.rst(1'b0));
//Bank distribution for 128/64/32 bit read port
// Address path
always @(rd0_addr or rd0_addr_plus1 or rd0_addr_plus2 or rd0_addr_plus3)
begin
casex(rd0_addr[1:0])
2'b00:
begin
rd0_addr_bank0 <= rd0_addr[9:2];
rd0_addr_bank1 <= rd0_addr_plus1[9:2];
rd0_addr_bank2 <= rd0_addr_plus2[9:2];
rd0_addr_bank3 <= rd0_addr_plus3[9:2];
end
2'b01:
begin
rd0_addr_bank0 <= rd0_addr_plus3[9:2];
rd0_addr_bank1 <= rd0_addr[9:2];
rd0_addr_bank2 <= rd0_addr_plus1[9:2];
rd0_addr_bank3 <= rd0_addr_plus2[9:2];
end
2'b10:
begin
rd0_addr_bank0 <= rd0_addr_plus2[9:2];
rd0_addr_bank1 <= rd0_addr_plus3[9:2];
rd0_addr_bank2 <= rd0_addr[9:2];
rd0_addr_bank3 <= rd0_addr_plus1[9:2];
end
2'b11:
begin
rd0_addr_bank0 <= rd0_addr_plus1[9:2];
rd0_addr_bank1 <= rd0_addr_plus2[9:2];
rd0_addr_bank2 <= rd0_addr_plus3[9:2];
rd0_addr_bank3 <= rd0_addr[9:2];
end
default:
begin
rd0_addr_bank0 <= {8{1'bx}};
rd0_addr_bank1 <= {8{1'bx}};
rd0_addr_bank2 <= {8{1'bx}};
rd0_addr_bank3 <= {8{1'bx}};
end
endcase
end // always @ (rd0_addr or rd0_addr_plus1 or rd0_addr_plus2 or rd0_addr_plus3...
// Rd data path
always @(rd0_addr_last or rd0_data_bank0 or rd0_data_bank1 or
rd0_data_bank2 or rd0_data_bank3)
begin
casex(rd0_addr_last[1:0])
2'b00:
begin
rd0_data <= {rd0_data_bank3,rd0_data_bank2,
rd0_data_bank1,rd0_data_bank0};
end
2'b01:
begin
rd0_data <= {rd0_data_bank0,rd0_data_bank3,
rd0_data_bank2,rd0_data_bank1};
end
2'b10:
begin
rd0_data <= {rd0_data_bank1,rd0_data_bank0,
rd0_data_bank3,rd0_data_bank2};
end
2'b11:
begin
rd0_data <= {rd0_data_bank2,rd0_data_bank1,
rd0_data_bank0,rd0_data_bank3};
end
default:
begin
rd0_data <= {128{1'bx}};
end
endcase
end
/////////////////////////////////////////
//Muxing for rd1
wire [31:0] rd1_data_bank0;
wire [31:0] rd1_data_bank1;
wire [31:0] rd1_data_bank2;
wire [31:0] rd1_data_bank3;
always @(rd1_addr_last or rd1_data_bank0 or rd1_data_bank1 or
rd1_data_bank2 or rd1_data_bank3)
begin
casex(rd1_addr_last[1:0])
2'b00:
begin
rd1_data <= rd1_data_bank0;
end
2'b01:
begin
rd1_data <= rd1_data_bank1;
end
2'b10:
begin
rd1_data <= rd1_data_bank2;
end
2'b11:
begin
rd1_data <= rd1_data_bank3;
end
default:
begin
rd1_data <= {32{1'bx}};
end
endcase
end
/////////////////////////////////////////
//Muxing for rd2
wire [31:0] rd2_data_bank0;
wire [31:0] rd2_data_bank1;
wire [31:0] rd2_data_bank2;
wire [31:0] rd2_data_bank3;
always @(rd2_addr_last or rd2_data_bank0 or rd2_data_bank1 or
rd2_data_bank2 or rd2_data_bank3)
begin
casex(rd2_addr_last[1:0])
2'b00:
begin
rd2_data <= rd2_data_bank0;
end
2'b01:
begin
rd2_data <= rd2_data_bank1;
end
2'b10:
begin
rd2_data <= rd2_data_bank2;
end
2'b11:
begin
rd2_data <= rd2_data_bank3;
end
default:
begin
rd2_data <= {32{1'bx}};
end
endcase
end
/////////////////////////////////////////
//Muxing for wr1
reg [3:0] wr0_en_internal;
reg wr0_en_bank0;
reg wr0_en_bank1;
reg wr0_en_bank2;
reg wr0_en_bank3;
reg [7:0] wr0_addr_bank0;
reg [7:0] wr0_addr_bank1;
reg [7:0] wr0_addr_bank2;
reg [7:0] wr0_addr_bank3;
reg [31:0] wr0_data_bank0;
reg [31:0] wr0_data_bank1;
reg [31:0] wr0_data_bank2;
reg [31:0] wr0_data_bank3;
wire [9:0] wr0_addr_plus1;
wire [9:0] wr0_addr_plus2;
wire [9:0] wr0_addr_plus3;
assign wr0_addr_plus1 = wr0_addr + 1'b1;
assign wr0_addr_plus2 = wr0_addr + 2'b10;
assign wr0_addr_plus3 = wr0_addr + 2'b11;
always @(wr0_addr or wr0_addr_plus1 or wr0_addr_plus2 or wr0_addr_plus3 or wr0_data)
begin
casex(wr0_addr[1:0])
2'b00:
begin
wr0_addr_bank0 <= wr0_addr[9:2];
wr0_addr_bank1 <= wr0_addr_plus1[9:2];
wr0_addr_bank2 <= wr0_addr_plus2[9:2];
wr0_addr_bank3 <= wr0_addr_plus3[9:2];
wr0_data_bank0 <= wr0_data[31:0];
wr0_data_bank1 <= wr0_data[63:32];
wr0_data_bank2 <= wr0_data[95:64];
wr0_data_bank3 <= wr0_data[127:96];
wr0_en_internal <= 4'b0001;
end
2'b01:
begin
wr0_addr_bank0 <= wr0_addr_plus3[9:2];
wr0_addr_bank1 <= wr0_addr[9:2];
wr0_addr_bank2 <= wr0_addr_plus1[9:2];
wr0_addr_bank3 <= wr0_addr_plus2[9:2];
wr0_data_bank0 <= wr0_data[127:96];
wr0_data_bank1 <= wr0_data[31:0];
wr0_data_bank2 <= wr0_data[63:32];
wr0_data_bank3 <= wr0_data[95:64];
wr0_en_internal <= 4'b0010;
end
2'b10:
begin
wr0_addr_bank0 <= wr0_addr_plus2[9:2];
wr0_addr_bank1 <= wr0_addr_plus3[9:2];
wr0_addr_bank2 <= wr0_addr[9:2];
wr0_addr_bank3 <= wr0_addr_plus1[9:2];
wr0_data_bank0 <= wr0_data[95:64];
wr0_data_bank1 <= wr0_data[127:96];
wr0_data_bank2 <= wr0_data[31:0];
wr0_data_bank3 <= wr0_data[63:32];
wr0_en_internal <= 4'b0100;
end
2'b11:
begin
wr0_addr_bank0 <= wr0_addr_plus1[9:2];
wr0_addr_bank1 <= wr0_addr_plus2[9:2];
wr0_addr_bank2 <= wr0_addr_plus3[9:2];
wr0_addr_bank3 <= wr0_addr[9:2];
wr0_data_bank0 <= wr0_data[63:32];
wr0_data_bank1 <= wr0_data[95:64];
wr0_data_bank2 <= wr0_data[127:96];
wr0_data_bank3 <= wr0_data[31:0];
wr0_en_internal <= 4'b1000;
end
default:
begin
wr0_addr_bank0 <= {8{1'bx}};
wr0_addr_bank1 <= {8{1'bx}};
wr0_addr_bank2 <= {8{1'bx}};
wr0_addr_bank3 <= {8{1'bx}};
wr0_data_bank0 <= {32{1'bx}};
wr0_data_bank1 <= {32{1'bx}};
wr0_data_bank2 <= {32{1'bx}};
wr0_data_bank3 <= {32{1'bx}};
wr0_en_internal <= {4{1'bx}};
end
endcase
end
always @(wr0_en_internal or wr0_en)
begin
casex(wr0_en)
4'b0000:
begin
wr0_en_bank0 <= 1'b0;
wr0_en_bank1 <= 1'b0;
wr0_en_bank2 <= 1'b0;
wr0_en_bank3 <= 1'b0;
end
4'b0001:
begin
wr0_en_bank0 <= wr0_en_internal[0];
wr0_en_bank1 <= wr0_en_internal[1];
wr0_en_bank2 <= wr0_en_internal[2];
wr0_en_bank3 <= wr0_en_internal[3];
end
4'b0011:
begin
wr0_en_bank0 <= wr0_en_internal[0] | wr0_en_internal[3];
wr0_en_bank1 <= wr0_en_internal[1] | wr0_en_internal[0];
wr0_en_bank2 <= wr0_en_internal[2] | wr0_en_internal[1];
wr0_en_bank3 <= wr0_en_internal[3] | wr0_en_internal[2];
end
4'b1111:
begin
wr0_en_bank0 <= 1'b1;
wr0_en_bank1 <= 1'b1;
wr0_en_bank2 <= 1'b1;
wr0_en_bank3 <= 1'b1;
end
default:
begin
wr0_en_bank0 <= 1'bx;
wr0_en_bank1 <= 1'bx;
wr0_en_bank2 <= 1'bx;
wr0_en_bank3 <= 1'bx;
end
endcase
end
/////////////////////////////////////////
reg_256x32b_3r_1w bank0(
.rd0_addr(rd0_addr_bank0),
.rd0_data(rd0_data_bank0),
.rd1_addr(rd1_addr[9:2]),
.rd1_data(rd1_data_bank0),
.rd2_addr(rd2_addr[9:2]),
.rd2_data(rd2_data_bank0),
.wr0_addr(wr0_addr_bank0),
.wr0_en(wr0_en_bank0),
.wr0_data(wr0_data_bank0),
.clk(clk)
);
reg_256x32b_3r_1w bank1(
.rd0_addr(rd0_addr_bank1),
.rd0_data(rd0_data_bank1),
.rd1_addr(rd1_addr[9:2]),
.rd1_data(rd1_data_bank1),
.rd2_addr(rd2_addr[9:2]),
.rd2_data(rd2_data_bank1),
.wr0_addr(wr0_addr_bank1),
.wr0_en(wr0_en_bank1),
.wr0_data(wr0_data_bank1),
.clk(clk)
);
reg_256x32b_3r_1w bank2(
.rd0_addr(rd0_addr_bank2),
.rd0_data(rd0_data_bank2),
.rd1_addr(rd1_addr[9:2]),
.rd1_data(rd1_data_bank2),
.rd2_addr(rd2_addr[9:2]),
.rd2_data(rd2_data_bank2),
.wr0_addr(wr0_addr_bank2),
.wr0_en(wr0_en_bank2),
.wr0_data(wr0_data_bank2),
.clk(clk)
);
reg_256x32b_3r_1w bank3(
.rd0_addr(rd0_addr_bank3),
.rd0_data(rd0_data_bank3),
.rd1_addr(rd1_addr[9:2]),
.rd1_data(rd1_data_bank3),
.rd2_addr(rd2_addr[9:2]),
.rd2_data(rd2_data_bank3),
.wr0_addr(wr0_addr_bank3),
.wr0_en(wr0_en_bank3),
.wr0_data(wr0_data_bank3),
.clk(clk)
);
/////////////////////////////////////////
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ns/1ps
module bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCNFG2RD_EN = 2,
parameter nCNFG2WR = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
wtr_inhbt_config_r, was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, io_config_valid_r, io_config_strobe,
io_config, inhbt_wr_config, inhbt_rd_r, inhbt_rd_config,
inhbt_act_faw_r, idle_cnt, hi_priority, dq_busy_data,
dfi_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input dfi_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input inhbt_rd_config; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd_r; // To bank_state0 of bank_state.v
input inhbt_wr_config; // To bank_state0 of bank_state.v
input [RANK_WIDTH:0] io_config; // To bank_state0 of bank_state.v
input io_config_strobe; // To bank_state0 of bank_state.v
input io_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] wtr_inhbt_config_r; // To bank_state0 of bank_state.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.rtc (rtc),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.dfi_rddata_valid (dfi_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.io_config_strobe (io_config_strobe),
.io_config_valid_r (io_config_valid_r),
.io_config (io_config[RANK_WIDTH:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "riffa.vh"
module channel
#(
parameter C_DATA_WIDTH = 128,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
generate
if(C_DATA_WIDTH == 32) begin
channel_32
#(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(/*AUTOINST*/
// Outputs
.SG_RX_BUF_RECVD (SG_RX_BUF_RECVD),
.SG_TX_BUF_RECVD (SG_TX_BUF_RECVD),
.TXN_RX_DONE_LEN (TXN_RX_DONE_LEN[31:0]),
.TXN_RX_DONE (TXN_RX_DONE),
.TXN_TX (TXN_TX),
.TXN_TX_LEN (TXN_TX_LEN[31:0]),
.TXN_TX_OFF_LAST (TXN_TX_OFF_LAST[31:0]),
.TXN_TX_DONE_LEN (TXN_TX_DONE_LEN[31:0]),
.TXN_TX_DONE (TXN_TX_DONE),
.RX_REQ (RX_REQ),
.RX_REQ_TAG (RX_REQ_TAG[1:0]),
.RX_REQ_ADDR (RX_REQ_ADDR[63:0]),
.RX_REQ_LEN (RX_REQ_LEN[9:0]),
.TX_REQ (TX_REQ),
.TX_ADDR (TX_ADDR[63:0]),
.TX_LEN (TX_LEN[9:0]),
.TX_DATA (TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX (CHNL_RX),
.CHNL_RX_LAST (CHNL_RX_LAST),
.CHNL_RX_LEN (CHNL_RX_LEN[31:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[30:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID),
.CHNL_TX_ACK (CHNL_TX_ACK),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN),
// Inputs
.CLK (CLK),
.RST (RST),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.PIO_DATA (PIO_DATA[31:0]),
.ENG_DATA (ENG_DATA[C_DATA_WIDTH-1:0]),
.SG_RX_BUF_LEN_VALID (SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID (SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID (SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_LEN_VALID (SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID (SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID (SG_TX_BUF_ADDR_LO_VALID),
.TXN_RX_LEN_VALID (TXN_RX_LEN_VALID),
.TXN_RX_OFF_LAST_VALID (TXN_RX_OFF_LAST_VALID),
.TXN_RX_DONE_ACK (TXN_RX_DONE_ACK),
.TXN_TX_ACK (TXN_TX_ACK),
.TXN_TX_DONE_ACK (TXN_TX_DONE_ACK),
.RX_REQ_ACK (RX_REQ_ACK),
.TX_REQ_ACK (TX_REQ_ACK),
.TX_DATA_REN (TX_DATA_REN),
.TX_SENT (TX_SENT),
.MAIN_DATA_EN (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.MAIN_DONE (MAIN_DONE),
.MAIN_ERR (MAIN_ERR),
.SG_RX_DATA_EN (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_RX_DONE (SG_RX_DONE),
.SG_RX_ERR (SG_RX_ERR),
.SG_TX_DATA_EN (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_TX_DONE (SG_TX_DONE),
.SG_TX_ERR (SG_TX_ERR),
.CHNL_RX_CLK (CHNL_RX_CLK),
.CHNL_RX_ACK (CHNL_RX_ACK),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN),
.CHNL_TX_CLK (CHNL_TX_CLK),
.CHNL_TX (CHNL_TX),
.CHNL_TX_LAST (CHNL_TX_LAST),
.CHNL_TX_LEN (CHNL_TX_LEN[31:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[30:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID));
end else if(C_DATA_WIDTH == 64) begin
channel_64
#(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(/*AUTOINST*/
// Outputs
.SG_RX_BUF_RECVD (SG_RX_BUF_RECVD),
.SG_TX_BUF_RECVD (SG_TX_BUF_RECVD),
.TXN_RX_DONE_LEN (TXN_RX_DONE_LEN[31:0]),
.TXN_RX_DONE (TXN_RX_DONE),
.TXN_TX (TXN_TX),
.TXN_TX_LEN (TXN_TX_LEN[31:0]),
.TXN_TX_OFF_LAST (TXN_TX_OFF_LAST[31:0]),
.TXN_TX_DONE_LEN (TXN_TX_DONE_LEN[31:0]),
.TXN_TX_DONE (TXN_TX_DONE),
.RX_REQ (RX_REQ),
.RX_REQ_TAG (RX_REQ_TAG[1:0]),
.RX_REQ_ADDR (RX_REQ_ADDR[63:0]),
.RX_REQ_LEN (RX_REQ_LEN[9:0]),
.TX_REQ (TX_REQ),
.TX_ADDR (TX_ADDR[63:0]),
.TX_LEN (TX_LEN[9:0]),
.TX_DATA (TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX (CHNL_RX),
.CHNL_RX_LAST (CHNL_RX_LAST),
.CHNL_RX_LEN (CHNL_RX_LEN[31:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[30:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID),
.CHNL_TX_ACK (CHNL_TX_ACK),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN),
// Inputs
.CLK (CLK),
.RST (RST),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.PIO_DATA (PIO_DATA[31:0]),
.ENG_DATA (ENG_DATA[C_DATA_WIDTH-1:0]),
.SG_RX_BUF_LEN_VALID (SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID (SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID (SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_LEN_VALID (SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID (SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID (SG_TX_BUF_ADDR_LO_VALID),
.TXN_RX_LEN_VALID (TXN_RX_LEN_VALID),
.TXN_RX_OFF_LAST_VALID (TXN_RX_OFF_LAST_VALID),
.TXN_RX_DONE_ACK (TXN_RX_DONE_ACK),
.TXN_TX_ACK (TXN_TX_ACK),
.TXN_TX_DONE_ACK (TXN_TX_DONE_ACK),
.RX_REQ_ACK (RX_REQ_ACK),
.TX_REQ_ACK (TX_REQ_ACK),
.TX_DATA_REN (TX_DATA_REN),
.TX_SENT (TX_SENT),
.MAIN_DATA_EN (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.MAIN_DONE (MAIN_DONE),
.MAIN_ERR (MAIN_ERR),
.SG_RX_DATA_EN (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_RX_DONE (SG_RX_DONE),
.SG_RX_ERR (SG_RX_ERR),
.SG_TX_DATA_EN (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_TX_DONE (SG_TX_DONE),
.SG_TX_ERR (SG_TX_ERR),
.CHNL_RX_CLK (CHNL_RX_CLK),
.CHNL_RX_ACK (CHNL_RX_ACK),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN),
.CHNL_TX_CLK (CHNL_TX_CLK),
.CHNL_TX (CHNL_TX),
.CHNL_TX_LAST (CHNL_TX_LAST),
.CHNL_TX_LEN (CHNL_TX_LEN[31:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[30:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID));
end else if(C_DATA_WIDTH == 128) begin
channel_128
#(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(/*AUTOINST*/
// Outputs
.SG_RX_BUF_RECVD (SG_RX_BUF_RECVD),
.SG_TX_BUF_RECVD (SG_TX_BUF_RECVD),
.TXN_RX_DONE_LEN (TXN_RX_DONE_LEN[31:0]),
.TXN_RX_DONE (TXN_RX_DONE),
.TXN_TX (TXN_TX),
.TXN_TX_LEN (TXN_TX_LEN[31:0]),
.TXN_TX_OFF_LAST (TXN_TX_OFF_LAST[31:0]),
.TXN_TX_DONE_LEN (TXN_TX_DONE_LEN[31:0]),
.TXN_TX_DONE (TXN_TX_DONE),
.RX_REQ (RX_REQ),
.RX_REQ_TAG (RX_REQ_TAG[1:0]),
.RX_REQ_ADDR (RX_REQ_ADDR[63:0]),
.RX_REQ_LEN (RX_REQ_LEN[9:0]),
.TX_REQ (TX_REQ),
.TX_ADDR (TX_ADDR[63:0]),
.TX_LEN (TX_LEN[9:0]),
.TX_DATA (TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX (CHNL_RX),
.CHNL_RX_LAST (CHNL_RX_LAST),
.CHNL_RX_LEN (CHNL_RX_LEN[31:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[30:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID),
.CHNL_TX_ACK (CHNL_TX_ACK),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN),
// Inputs
.CLK (CLK),
.RST (RST),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.PIO_DATA (PIO_DATA[31:0]),
.ENG_DATA (ENG_DATA[C_DATA_WIDTH-1:0]),
.SG_RX_BUF_LEN_VALID (SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID (SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID (SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_LEN_VALID (SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID (SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID (SG_TX_BUF_ADDR_LO_VALID),
.TXN_RX_LEN_VALID (TXN_RX_LEN_VALID),
.TXN_RX_OFF_LAST_VALID (TXN_RX_OFF_LAST_VALID),
.TXN_RX_DONE_ACK (TXN_RX_DONE_ACK),
.TXN_TX_ACK (TXN_TX_ACK),
.TXN_TX_DONE_ACK (TXN_TX_DONE_ACK),
.RX_REQ_ACK (RX_REQ_ACK),
.TX_REQ_ACK (TX_REQ_ACK),
.TX_DATA_REN (TX_DATA_REN),
.TX_SENT (TX_SENT),
.MAIN_DATA_EN (MAIN_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.MAIN_DONE (MAIN_DONE),
.MAIN_ERR (MAIN_ERR),
.SG_RX_DATA_EN (SG_RX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_RX_DONE (SG_RX_DONE),
.SG_RX_ERR (SG_RX_ERR),
.SG_TX_DATA_EN (SG_TX_DATA_EN[C_DATA_WORD_WIDTH-1:0]),
.SG_TX_DONE (SG_TX_DONE),
.SG_TX_ERR (SG_TX_ERR),
.CHNL_RX_CLK (CHNL_RX_CLK),
.CHNL_RX_ACK (CHNL_RX_ACK),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN),
.CHNL_TX_CLK (CHNL_TX_CLK),
.CHNL_TX (CHNL_TX),
.CHNL_TX_LAST (CHNL_TX_LAST),
.CHNL_TX_LEN (CHNL_TX_LEN[31:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[30:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[C_DATA_WIDTH-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID));
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "import")
// End:
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
module ram_test (
input clk,
input rst,
output reg [22:0] addr,
output reg rw,
output reg [31:0] data_in,
input [31:0] data_out,
input busy,
output reg in_valid,
input out_valid,
output [7:0] leds
);
localparam STATE_SIZE = 2;
localparam WRITE = 0,
READ = 1,
IDLE = 2;
reg [STATE_SIZE-1:0] state_d, state_q = WRITE;
reg [4:0] led_d, led_q;
reg [22:0] addr_d, addr_q;
reg [6:0] error_d, error_q;
reg [31:0] seed_d, seed_q;
assign leds = {led_q[4], error_q};
reg pn_rst, pn_next;
wire [31:0] pn;
pn_gen pn_gen (
.clk(clk),
.rst(pn_rst),
.next(pn_next),
.seed(seed_q),
.num(pn)
);
always @* begin
addr_d = addr_q;
led_d = led_q;
state_d = state_q;
error_d = error_q;
addr = 23'd0;
rw = 1'b0;
data_in = 32'h00;
in_valid = 1'b0;
pn_rst = 1'b0 | rst;
pn_next = 1'b0;
seed_d = seed_q;
case (state_q)
WRITE: begin
led_d[4] = 1'b0;
if (!busy) begin
pn_next = 1'b1;
addr_d = addr_q + 1'b1;
addr = addr_q;
rw = 1'b1;
data_in = pn;
in_valid = 1'b1;
if (addr_q == {23{1'b1}}) begin
addr_d = 8'b0;
state_d = READ;
pn_rst = 1'b1;
end
end
end
READ: begin
led_d[4] = 1'b1;
if (!busy) begin
addr_d = addr_q + 1'b1;
addr = addr_q;
in_valid = 1'b1;
if (addr_q == {23{1'b1}}-25'd10)
seed_d = seed_q + 1'b1;
if (addr_q == {23{1'b1}}) begin
addr_d = 8'b0;
state_d = WRITE;
pn_rst = 1'b1;
end
end
if (out_valid) begin
pn_next = 1'b1;
led_d[0] = pn[7:0] != data_out[7:0];
led_d[1] = pn[15:8] != data_out[15:8];
led_d[2] = pn[23:16] != data_out[23:16];
led_d[3] = pn[31:24] != data_out[31:24];
if (data_out != pn && error_q < {7{1'b1}})
error_d = error_q + 1'b1;
end
end
IDLE: begin
led_d[4] = 1'b0;
end
default: state_d = WRITE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= WRITE;
addr_q <= 8'd0;
error_q <= 7'b0;
seed_q <= 32'd0;
led_q <= 5'b0;
end else begin
state_q <= state_d;
addr_q <= addr_d;
error_q <= error_d;
seed_q <= seed_d;
led_q <= led_d;
end
end
endmodule
|
module packet_builder #(parameter NUM_CHAN = 1)(
// System
input rxclk,
input reset,
input [31:0] adctime,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
input [NUM_CHAN:0]chan_empty,
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
`define HEADER2 3'd2
`define TIMESTAMP 3'd3
`define FORWARD 3'd4
`define MAXPAYLOAD 504
`define PAYLOAD_LEN 8:0
`define TAG 12:9
`define MBZ 15:13
`define CHAN 4:0
`define RSSI 10:5
`define BURST 12:11
`define DROPPED 13
`define UNDERRUN 14
`define OVERRUN 15
reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg tstamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
//assign true_channel = (check_next == NUM_CHAN ? 5'h1f : {1'd0,check_next});
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
if (reset)
begin
overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
tstamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
//check if the channel is full
if(~chan_empty[check_next])
begin
if (have_space)
begin
//transmit if the usb buffer have space
//check if we should send
if (ready_to_send)
state <= #1 `HEADER1;
overrun[check_next] <= 0;
end
else
begin
state <= #1 `IDLE;
overrun[check_next] <= 1;
end
rd_select <= #1 check_next;
end
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end //end of `IDLE
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
`TIMESTAMP: begin
fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
tstamp_complete <= #1 ~tstamp_complete;
if (~tstamp_complete)
chan_rdreq <= #1 1;
state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
read_length <= #1 read_length + 9'd2;
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
if (read_length >= `MAXPAYLOAD)
begin
WR <= #1 0;
state <= #1 `IDLE;
chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
end
default: begin
//handling error state
state <= `IDLE;
end
endcase
end
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
test tt();
defparam foo = 3; /* This should generate a warning. */
defparam tt.foo = 4;
endmodule // main
module test;
parameter foo = 10;
reg [foo-1:0] bar;
initial begin
if ($bits(bar) != 4) begin
$display("FAILED -- $bits(bar) = %d", $bits(bar));
$finish;
end
$display("PASSED");
end
endmodule // test
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx tick timer unit
Copyright (C) 2012 Authors
Author(s): Julius Baxter <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_ticktimer
(
input clk,
input rst,
output [31:0] spr_ttmr_o,
output [31:0] spr_ttcr_o,
// SPR Bus interface
input spr_access_i,
input spr_we_i,
input [15:0] spr_addr_i,
input [31:0] spr_dat_i,
output spr_bus_ack,
output [31:0] spr_dat_o
);
// Registers
reg [31:0] spr_ttmr;
reg [31:0] spr_ttcr;
wire spr_ttmr_access;
wire spr_ttcr_access;
// ttcr control wires
wire ttcr_clear;
wire ttcr_run;
wire ttcr_match;
assign spr_ttmr_o = spr_ttmr;
assign spr_ttcr_o = spr_ttcr;
assign spr_ttmr_access =
spr_access_i &
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_TTMR_ADDR));
assign spr_ttcr_access =
spr_access_i &
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_TTCR_ADDR));
assign spr_bus_ack = spr_access_i;
assign spr_dat_o = (spr_access_i & spr_ttcr_access) ? spr_ttcr :
(spr_access_i & spr_ttmr_access) ? spr_ttmr : 0;
assign ttcr_match = spr_ttcr[27:0] == spr_ttmr[27:0];
// Timer SPR control
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_ttmr <= 0;
else if (spr_we_i & spr_ttmr_access)
spr_ttmr <= spr_dat_i[31:0];
else if (ttcr_match & spr_ttmr[29])
spr_ttmr[28] <= 1; // Generate interrupt
// Modes (spr_ttmr[31:30]):
// 00 Tick timer is disabled.
// 01 Timer is restarted on ttcr_match.
// 10 Timer stops when ttcr_match is true.
// 11 Timer does not stop when ttcr_match is true
assign ttcr_clear = (spr_ttmr[31:30] == 2'b01) & ttcr_match;
assign ttcr_run = (spr_ttmr[31:30] != 2'b00) & !ttcr_match |
(spr_ttmr[31:30] == 2'b11);
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_ttcr <= 0;
else if (spr_we_i & spr_ttcr_access)
spr_ttcr <= spr_dat_i[31:0];
else if (ttcr_clear)
spr_ttcr <= 0;
else if (ttcr_run)
spr_ttcr <= spr_ttcr + 1;
endmodule // mor1kx_ticktimer
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MEMC
// / / Filename: memc_traffic_gen.v
// /___/ /\ Date Last Modified: $Date:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6/Virtex6
//Design Name: memc_traffic_gen
//Purpose: This is top level module of memory traffic generator which can
// generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
// hard memory controller core.
//Reference:
//Revision History: 1.1 Brought out internal signals cmp_data and cmp_error as outputs.
// 1.2 7/1/2009 Added EYE_TEST parameter for signal SI probing.
// 1.3 10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6.
// Any comparison error on user read data bus are mapped back to
// dq bus. The cumulative_dq_lane_error accumulate any errors on
// DQ bus. And the dq_error_bytelane_cmp shows error during current
// command cycle. The error can be cleared by input signal "manual_clear_error".
// 1.4 7/29/10 Support virtex Back-to-back commands over user interface.
//
// 1/4/2012 Added vio_percent_write (instr_mode == 4) to
// let user specify percentage of write commands out of mix
// write/read commands.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_memc_traffic_gen #
(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6"
parameter MEM_TYPE = "DDR3",
parameter SIMULATION = "FALSE",
parameter tCK = 2500,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen.
// This traffic gen doesn't support DDR3 OTF Burst mode.
parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE"
// VIRTEX6: "BI_MODE"
parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30
parameter BANK_WIDTH = 3,
parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0
// memory type specific
parameter MEM_COL_WIDTH = 10, // memory column width
parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16;
// Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144
parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern
// SEL_VICTIM_LINE is only for V6.
// Virtex 6 option: 8,9,16,17,32,36,64,72
parameter DWIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128;
// Virtex 6 Always: 4* NUM_DQ_PINS
// the following parameter is to limit the range of generated PRBS Address
//
// e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with
// PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset.
// PRBS_EADDR = 32'h0000_7fff
// PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to
// zero out the LFSR[31:15]
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00005000,
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals.
// Traffic Generator will only write to one single location and no
// read transactions will be generated.
)
(
input clk_i,
input rst_i,
input run_traffic_i,
input single_operation,
input manual_clear_error,
input [5:0] cmds_gap_delay_value, // control delay gap between each sucessive
input [3:0] vio_instr_mode_value,
input [3:0] vio_percent_write,
// burst commands.
// *** runtime parameter ***
input mem_pattern_init_done_i,
input [31:0] start_addr_i, // define the start of address
input [31:0] end_addr_i, // define upper limit addressboundary
input [31:0] cmd_seed_i, // seed for cmd PRBS generators
input [31:0] data_seed_i, // data seed will be added to generated address
// for PRBS data generation
// seed for cmd PRBS generators
input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered.
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface
// "01" = fixed address from the fixed_addr input
// "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "11" = sequential
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
input [3:0] instr_mode_i, // "0000" = BRAM
// "0001" = Fixed; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0110" = PRBS
// "1111" = Read Only from Address 0 . Expecting phy calibration data pattern.
input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
input [3:0] data_mode_i, // "000" = address as data
// "001" = hammer
// "010" = neighbour
// "011" = prbs
// "100" = walking 0's
// "101" = walking 1's
// "110" =
// "111" =
input wr_data_mask_gen_i, // "1": turn on wr_data_mask generation
// random follow by walking 1's
input mode_load_i,
// fixed pattern inputs interface
input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64
input [2:0] fixed_instr_i, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
input [31:0] fixed_addr_i, // only upper 30 bits will be used
input [31:0] fixed_data_i, //
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
/////////////////////////////////////////////////////////////////////////////
// MCB INTERFACE
// interface to mcb command port
output memc_cmd_en_o,
output [2:0] memc_cmd_instr_o,
output [31:0] memc_cmd_addr_o,
output [5:0] memc_cmd_bl_o, // this output is for Spartan 6
input memc_cmd_full_i,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// interface to mcb wr data port
output memc_wr_en_o,
output [DWIDTH-1:0] memc_wr_data_o,
output memc_wr_data_end_o,
output [(DWIDTH/8) - 1:0] memc_wr_mask_o,
input memc_wr_full_i,
// interface to mcb rd data port
output memc_rd_en_o,
input [DWIDTH-1:0] memc_rd_data_i,
input memc_rd_empty_i,
/////////////////////////////////////////////////////////////////////////////
// status feedback
input counts_rst,
output reg [47:0] wr_data_counts,
output reg [47:0] rd_data_counts,
output cmp_error,
output cmp_data_valid,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped
output [DWIDTH-1:0] cmp_data,
output [DWIDTH-1:0] mem_rd_data,
// **** V6 Signals
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, // V6: latched error byte lane that occure on
// first error
//************************************************
// DQ bit error debug signals.
output [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error ,
output [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
//
output [NUM_DQ_PINS - 1:0] dq_r0_read_bit, // rising 0 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_f0_read_bit, // falling 0 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_r1_read_bit, // rising 1 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_f1_read_bit, // falling 1 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_r0_expect_bit, // rising 0 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_f0_expect_bit, // falling 0 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_r1_expect_bit, // rising 1 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_f1_expect_bit, // falling 1 read bits from internal expect data generator
output [31:0] error_addr // the command address of the returned data.
// Can use dq_rx_bit_error as write enable to latch the address.
);
wire [DWIDTH-1:0] rdpath_rd_data_i;
wire rdpath_data_valid_i;
wire memc_wr_en;
wire cmd2flow_valid;
wire [2:0] cmd2flow_cmd;
wire [31:0] cmd2flow_addr;
wire [BL_WIDTH-1:0] cmd2flow_bl;
wire last_word_wr;
wire flow2cmd_rdy;
wire [31:0] wr_addr;
wire [31:0] rd_addr;
wire [BL_WIDTH-1:0] wr_bl;
wire [BL_WIDTH-1:0] rd_bl;
reg run_traffic_reg;
wire wr_validB, wr_valid,wr_validC;
wire [31:0] bram_addr_i;
wire [2:0] bram_instr_i;
wire [5:0] bram_bl_i;
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
reg upper_end_matched;
reg [7:0] end_boundary_addr;
reg lower_end_matched;
wire [31:0] addr_o;
wire [31:0] m_addr;
wire dcount_rst;
wire [31:0] rd_addr_error;
wire rd_rdy;
//wire cmp_error;
wire cmd_full;
wire rd_mdata_fifo_rd_en;
wire rd_mdata_fifo_afull;
reg memc_wr_en_r;
wire memc_wr_data_end;
reg [DWIDTH-1:0] memc_rd_data_r;
wire [DWIDTH-1:0] memc_wr_data;
reg [DWIDTH-1:0] memc_wr_data_r;
wire wr_path_data_rdy_i;
//
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
reg [9:0] rst_ra,rst_rb /* synthesis syn_maxfan = 10 */;
wire mem_init_done;
reg [3:0] data_mode_r_a;
reg [3:0] data_mode_r_b;
reg [3:0] data_mode_r_c;
reg error_access_range = 1'b0;
wire [BL_WIDTH-1:0] memc_bl_o;
// generic parameters and need to be tested in both MCB mode and V7 Virtext Mode.
initial begin
if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8) && (MEM_BURST_LEN !== 2))
begin: NO_OTF_Warning_Error
$display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!");
$stop;
end
else
begin: Dummy1
end
end
always @ (memc_cmd_en_o,memc_cmd_addr_o,memc_cmd_bl_o,start_addr_i,end_addr_i)
if (memc_cmd_en_o &&
((FAMILY == "SPARTAN6" && memc_cmd_addr_o + 20) > end_addr_i[ADDR_WIDTH-1:0]) ||
((FAMILY == "VIRTEX6" && memc_cmd_addr_o ) > end_addr_i[ADDR_WIDTH-1:0])
)
begin
$display("Error ! Command access beyond address range");
$display("Assigned Address Space: Start_Address = 0x%h ; End_Addr = 0x%h",start_addr_i,end_addr_i);
$display("Attempted area = 0x%h",memc_cmd_addr_o + (memc_cmd_bl_o - 1) * (DWIDTH/8));
$stop;
end
else
begin: No_Error_Display
end
assign memc_cmd_bl_o = memc_bl_o[5:0];
always @ (posedge clk_i)
begin
data_mode_r_a <= #TCQ data_mode_i;
data_mode_r_b <= #TCQ data_mode_i;
data_mode_r_c <= #TCQ data_mode_i;
end
//reg GSR = 1'b0;
always @(rst_i)
begin
rst_ra = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
rst_rb = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
end
// register it . Just in case the calling modules didn't syn with clk_i
always @(posedge clk_i)
begin
run_traffic_reg <= #TCQ run_traffic_i;
end
assign bram_addr_i = {bram_cmd_i[29:0],2'b00};
assign bram_instr_i = bram_cmd_i[32:30];
assign bram_bl_i[5:0] = bram_cmd_i[38:33]; //41
//
//
reg COutc,COutd;
assign dcount_rst = counts_rst | rst_ra[0];
always @ (posedge clk_i)
begin
if (dcount_rst)
wr_data_counts <= #TCQ 'b0;
else if (memc_wr_en)
{COutc,wr_data_counts} <= #TCQ wr_data_counts + DWIDTH/8;
end
always @ (posedge clk_i)
begin
if (dcount_rst)
rd_data_counts <= #TCQ 'b0;
else if (memc_rd_en_o)
{COutd,rd_data_counts} <= #TCQ rd_data_counts + DWIDTH/8;
end
// **** for debug
// this part of logic is to check there are no commands been duplicated or dropped
// in the cmd_flow_control logic
generate
if (SIMULATION == "TRUE")
begin: cmd_check
wire fifo_error;
wire [31:0] xfer_addr;
wire [BL_WIDTH-1:0] xfer_cmd_bl;
wire cmd_fifo_rd;
assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid;
assign fifo_error = ( xfer_addr != memc_cmd_addr_o) ? 1'b1: 1'b0;
wire cmd_fifo_empty;
//assign cmd_fifo_rd = memc_cmd_en_o & ~memc_cmd_full_i & ~cmd_fifo_empty;
assign cmd_fifo_rd = memc_cmd_en_o & ~cmd_fifo_empty;
mig_7series_v2_0_afifo #
(.TCQ (TCQ),
.DSIZE (32+BL_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
cmd_fifo
(
.wr_clk (clk_i),
.rst (rst_ra[0]),
.wr_en (cmd_fifo_wr),
.wr_data ({cmd2flow_bl,cmd2flow_addr}),
.rd_en (cmd_fifo_rd),
.rd_clk (clk_i),
.rd_data ({xfer_cmd_bl,xfer_addr}),
.full (cmd_fifo_full),
.almost_full (),
.empty (cmd_fifo_empty)
);
end
else
begin
assign fifo_error = 1'b0;
end
endgenerate
reg [31:0] end_addr_r;
always @ (posedge clk_i)
end_addr_r <= end_addr_i;
mig_7series_v2_0_cmd_gen
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.PORT_MODE (PORT_MODE),
.BANK_WIDTH (BANK_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.ADDR_WIDTH (ADDR_WIDTH),
.DWIDTH (DWIDTH),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ),
.PRBS_EADDR (PRBS_EADDR),
.PRBS_SADDR (PRBS_SADDR )
)
u_c_gen
(
.clk_i (clk_i),
.rst_i (rst_ra),
.reading_rd_data_i (memc_rd_en_o),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_percent_write (vio_percent_write),
.single_operation (single_operation),
.run_traffic_i (run_traffic_reg),
.mem_pattern_init_done_i (mem_pattern_init_done_i),
.start_addr_i (start_addr_i),
.end_addr_i (end_addr_r),
.cmd_seed_i (cmd_seed_i),
.load_seed_i (load_seed_i),
.addr_mode_i (addr_mode_i),
.data_mode_i (data_mode_r_a),
.instr_mode_i (instr_mode_i),
.bl_mode_i (bl_mode_i),
.mode_load_i (mode_load_i),
// fixed pattern inputs interface
.fixed_bl_i (fixed_bl_i),
.fixed_addr_i (fixed_addr_i),
.fixed_instr_i (fixed_instr_i),
// BRAM FIFO input : Holist vector inputs
.bram_addr_i (bram_addr_i),
.bram_instr_i (bram_instr_i ),
.bram_bl_i (bram_bl_i ),
.bram_valid_i (bram_valid_i ),
.bram_rdy_o (bram_rdy_o ),
.rdy_i (flow2cmd_rdy),
.instr_o (cmd2flow_cmd),
.addr_o (cmd2flow_addr),
.bl_o (cmd2flow_bl),
// .m_addr_o (m_addr),
.cmd_o_vld (cmd2flow_valid),
.mem_init_done_o (mem_init_done)
);
assign memc_cmd_addr_o = addr_o;
assign qdr_wr_cmd_o = memc_wr_en_r;
assign cmd_full = memc_cmd_full_i;
mig_7series_v2_0_memc_flow_vcontrol #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE)
)
memc_control
(
.clk_i (clk_i),
.rst_i (rst_ra),
.data_mode_i (data_mode_r_b),
.cmds_gap_delay_value (cmds_gap_delay_value),
.mcb_wr_full_i (memc_wr_full_i),
.cmd_rdy_o (flow2cmd_rdy),
.cmd_valid_i (cmd2flow_valid),
.cmd_i (cmd2flow_cmd),
.mem_pattern_init_done_i (mem_pattern_init_done_i),
.addr_i (cmd2flow_addr),
.bl_i (cmd2flow_bl),
// interface to memc_cmd port
.mcb_cmd_full (cmd_full),
.cmd_o (memc_cmd_instr_o),
.addr_o (addr_o),
.bl_o (memc_bl_o),
.cmd_en_o (memc_cmd_en_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// interface to write data path module
.mcb_wr_en_i (memc_wr_en),
.last_word_wr_i (last_word_wr),
.wdp_rdy_i (wr_rdy),//(wr_rdy),
.wdp_valid_o (wr_valid),
.wdp_validB_o (wr_validB),
.wdp_validC_o (wr_validC),
.wr_addr_o (wr_addr),
.wr_bl_o (wr_bl),
// interface to read data path module
.rdp_rdy_i (rd_rdy),// (rd_rdy),
.rdp_valid_o (rd_valid),
.rd_addr_o (rd_addr),
.rd_bl_o (rd_bl)
);
/* afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (5),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_rb[0]),
.wr_en (!memc_rd_empty_i),
.wr_data (memc_rd_data_i),
.rd_en (memc_rd_en_o),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.almost_full (rd_mdata_fifo_afull),
.empty (rd_mdata_fifo_empty)
);
*/
wire cmd_rd_en;
assign cmd_rd_en = memc_cmd_en_o;
assign rdpath_data_valid_i =!memc_rd_empty_i ;
assign rdpath_rd_data_i = memc_rd_data_i ;
generate
if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE")
begin : RD_PATH
mig_7series_v2_0_read_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (PRBS_SADDR),
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
.ADDR_WIDTH (ADDR_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.SIMULATION (SIMULATION)
)
read_data_path
(
.clk_i (clk_i),
.rst_i (rst_rb),
.manual_clear_error (manual_clear_error),
.cmd_rdy_o (rd_rdy),
.cmd_valid_i (rd_valid),
.memc_cmd_full_i (memc_cmd_full_i),
.prbs_fseed_i (data_seed_i),
.cmd_sent (memc_cmd_instr_o),
.bl_sent (memc_bl_o[5:0]),
.cmd_en_i (cmd_rd_en),
.vio_instr_mode_value (vio_instr_mode_value),
.data_mode_i (data_mode_r_b),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (rd_addr),
.bl_i (rd_bl),
.data_rdy_o (memc_rd_en_o),
.data_valid_i (rdpath_data_valid_i),
.data_i (rdpath_rd_data_i),
.data_error_o (cmp_error),
.cmp_data_valid (cmp_data_valid),
.cmp_data_o (cmp_data),
.rd_mdata_o (mem_rd_data ),
.cmp_addr_o (cmp_addr),
.cmp_bl_o (cmp_bl),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
//****************************************************
.cumlative_dq_lane_error_r (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error_r (cumlative_dq_r0_bit_error),
.cumlative_dq_f0_bit_error_r (cumlative_dq_f0_bit_error),
.cumlative_dq_r1_bit_error_r (cumlative_dq_r1_bit_error),
.cumlative_dq_f1_bit_error_r (cumlative_dq_f1_bit_error),
.dq_r0_bit_error_r (dq_r0_bit_error_r),
.dq_f0_bit_error_r (dq_f0_bit_error_r),
.dq_r1_bit_error_r (dq_r1_bit_error_r),
.dq_f1_bit_error_r (dq_f1_bit_error_r),
.dq_r0_read_bit_r (dq_r0_read_bit),
.dq_f0_read_bit_r (dq_f0_read_bit),
.dq_r1_read_bit_r (dq_r1_read_bit),
.dq_f1_read_bit_r (dq_f1_read_bit),
.dq_r0_expect_bit_r (dq_r0_expect_bit),
.dq_f0_expect_bit_r (dq_f0_expect_bit ),
.dq_r1_expect_bit_r (dq_r1_expect_bit),
.dq_f1_expect_bit_r (dq_f1_expect_bit ),
.error_addr_o (error_addr)
);
end
else
begin
assign cmp_error = 1'b0;
assign cmp_data_valid = 1'b0;
assign cmp_data ='b0;
end
endgenerate
assign wr_path_data_rdy_i = !(memc_wr_full_i ) ;//& (~memc_cmd_full_i);
generate
if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")
begin : WR_PATH
mig_7series_v2_0_write_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_TYPE (MEM_TYPE),
.START_ADDR (PRBS_SADDR),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
write_data_path
(
.clk_i(clk_i),
.rst_i (rst_rb),
.cmd_rdy_o (wr_rdy),
.cmd_valid_i (wr_valid),
.cmd_validB_i (wr_validB),
.cmd_validC_i (wr_validC),
.prbs_fseed_i (data_seed_i),
.mode_load_i (mode_load_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done),
.data_mode_i (data_mode_r_c),
.last_word_wr_o (last_word_wr),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.addr_i (wr_addr),
.bl_i (wr_bl),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (wr_path_data_rdy_i),
.data_valid_o (memc_wr_en),
.data_o (memc_wr_data),
.data_mask_o (memc_wr_mask_o),
.data_wr_end_o (memc_wr_data_end)
);
end
else
begin
assign memc_wr_en = 1'b0;
assign memc_wr_data = 'b0;
assign memc_wr_mask_o = 'b0;
end
endgenerate
generate
if (MEM_TYPE != "QDR2PLUS" && (FAMILY == "VIRTEX6" || FAMILY == "SPARTAN6" ))
begin: nonQDR_WR
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data ;
assign memc_wr_data_end_o = (nCK_PER_CLK == 4) ? memc_wr_data_end: memc_wr_data_end;
end
// QDR
else
begin: QDR_WR
always @ (posedge clk_i)
memc_wr_data_r <= memc_wr_data;
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data_r ;
assign memc_wr_data_end_o = memc_wr_data_end;
end
endgenerate
//QDR
always @ (posedge clk_i)
begin
if (memc_wr_full_i)
begin
memc_wr_en_r <= 1'b0;
end
else
begin
memc_wr_en_r <= memc_wr_en;
end
end
mig_7series_v2_0_tg_status
#(
.TCQ (TCQ),
.DWIDTH (DWIDTH)
)
tg_status
(
.clk_i (clk_i),
.rst_i (rst_ra[2]),
.manual_clear_error (manual_clear_error),
.data_error_i (cmp_error),
.cmp_data_i (cmp_data),
.rd_data_i (mem_rd_data ),
.cmp_addr_i (cmp_addr),
.cmp_bl_i (cmp_bl),
.mcb_cmd_full_i (memc_cmd_full_i),
.mcb_wr_full_i (memc_wr_full_i),
.mcb_rd_empty_i (memc_rd_empty_i),
.error_status (error_status),
.error (error)
);
endmodule // memc_traffic_gen
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_atan(clock, resetn, enable, dataa, result);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result;
fp_atan core(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(result[31]),
.exponentout(result[30:23]),
.mantissaout(result[22:0])
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_0_V
`define SKY130_FD_SC_LP__A31O_0_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_0 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_0_V
|
module fifo(/*AUTOARG*/);
input clk;
input rst_n;
output fifo_full_w;
input enqueue_w;
input [(DATA_WIDTH-1):0] data_in_w;
output data_valid_r;
input dequeue_w;
input [1:0] full_threshold;
output [(DATA_WIDTH-1):0] rdata_r;
endmodule
module req (p_clk, carb_rst_rnp, req_rp, len_rxp, deq_req, deq_len, deq_val);
input p_clk;
input carb_rst_rnp;
input [4:0] len_rxp;
input req_rp;
input deq_req;
output [4:0] deq_len;
output deq_val;
reg [5:0] fifo_entry1_rp;
reg [5:0] fifo_entry2_rp;
reg [4:0] deq_len;
reg deq_val;
endmodule
module pull( /*AUTOARG*/);
input clk;
input rst_rnpha;
input [4:0] lenar_rxp;
input rem_rpd;
input d_rews;
output [4:0] d_len;
output d_val;
/* req AUTO_TEMPLATE "\(g[a-z0-9]+\|g.*[0-9]\)" (
.p_clk (my_clk_@),
.len_rxp (carb_rst_rnp_@),
.carb_rst_rnp (pull_req1));
*/
req test432_gbe5(/*AUTOINST*/);
req gbe9_vreos(/*AUTOINST*/);
/* fifo AUTO_TEMPLATE "gbe[0-9]+_\([^\_]+\)" (
.clk (@_clk),
.\(.*data.*\) (@_\1),
.\(.*\)\(full\)\(.*\) (\1@\3),
.\(en\|de\)\(.\).+ (@_\1\2));
*/
fifo #(5) gbe2_pull_req (/*AUTOINST*/);
fifo #(5)
gbe1_pull_req_fifo( /*AUTOINST*/);
endmodule // pull_arb
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pcie_bram_7x.v
// Version : 3.2
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_io c1_data();
counter_io c2_data();
//counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells
counter_io c3_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data),
.i_value(4'h1));
counter_ansi c2 (.clkm(clk),
.c_data(c2_data),
.i_value(4'h2));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
end
if (cyc==3) begin
if (c1_data.get_lcl() != 12345) $stop;
end
if (cyc==20) begin
$write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface counter_io;
logic [3:0] value;
logic reset;
integer lcl;
task set_lcl (input integer a); lcl=a; endtask
function integer get_lcl (); return lcl; endfunction
endinterface
interface ifunused;
logic unused;
endinterface
module counter_ansi
(
input clkm,
counter_io c_data,
input logic [3:0] i_value
);
initial begin
c_data.set_lcl(12345);
end
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi(clkm, c_data, i_value);
input clkm;
counter_io c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
module modunused (ifunused ifinunused);
ifunused ifunused();
endmodule
|
module adc_ltc2308(
clk, // max 40mhz
// start measure
measure_start, // posedge triggle
measure_ch,
measure_done,
measure_dataread,
// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);
input clk;
// start measure
input measure_start;
input [2:0] measure_ch;
output reg measure_done;
output [11:0] measure_dataread;
output ADC_CONVST;
output ADC_SCK;
output reg ADC_SDI;
input ADC_SDO;
/////////////////////////////////
// Timing definition
// using 40MHz clock
// to acheive fsample = 500KHz
// ntcyc = 2us / 25ns = 80
`define DATA_BITS_NUM 12
`define CMD_BITS_NUM 6
`define CH_NUM 8
`define tWHCONV 3 // CONVST High Time, min 20 ns
`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52
// set 64 for suite for 1.6 us max
// +12 //data
`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below
// If the source impedance of the driving circuit is low, the ADC inputs can be driven directly.
//Otherwise, more acquisition time should be allowed for a source with higher impedance.
// for acheiving 500KHz fmax. set n cyc = 80.
`define tCONVST_HIGH_START 0
`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV)
`define tCONFIG_START (`tCONVST_HIGH_END)
`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1)
`define tCLK_START (`tCONVST_HIGH_START+`tCONV)
`define tCLK_END (`tCLK_START+`DATA_BITS_NUM)
`define tDONE (`tCLK_END+`tHCONVST)
// create triggle message: reset_n
reg pre_measure_start;
always @ (posedge clk)
begin
pre_measure_start <= measure_start;
end
wire reset_n;
assign reset_n = (~pre_measure_start & measure_start)?1'b0:1'b1;
// tick
reg [15:0] tick;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
tick <= 0;
else if (tick < `tDONE)
tick <= tick + 1;
end
/////////////////////////////////
// ADC_CONVST
assign ADC_CONVST = (tick >= `tCONVST_HIGH_START && tick < `tCONVST_HIGH_END)?1'b1:1'b0;
/////////////////////////////////
// ADC_SCK
reg clk_enable; // must sync to clk in clk low
always @ (negedge clk or negedge reset_n)
begin
if (~reset_n)
clk_enable <= 1'b0;
else if ((tick >= `tCLK_START && tick < `tCLK_END))
clk_enable <= 1'b1;
else
clk_enable <= 1'b0;
end
assign ADC_SCK = clk_enable?clk:1'b0;
///////////////////////////////
// read data
reg [(`DATA_BITS_NUM-1):0] read_data;
reg [3:0] write_pos;
assign measure_dataread = read_data;
always @ (negedge clk or negedge reset_n)
begin
if (~reset_n)
begin
read_data <= 0;
write_pos <= `DATA_BITS_NUM-1;
end
else if (clk_enable)
begin
read_data[write_pos] <= ADC_SDO;
write_pos <= write_pos - 1;
end
end
///////////////////////////////
// measure done
wire read_ch_done;
assign read_ch_done = (tick == `tDONE)?1'b1:1'b0;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
measure_done <= 1'b0;
else if (read_ch_done)
measure_done <= 1'b1;
end
///////////////////////////////
// adc channel config
// pre-build config command
reg [(`CMD_BITS_NUM-1):0] config_cmd;
`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar
`define SLP_MODE 1'b0 //1: enable sleep
always @(negedge reset_n)
begin
if (~reset_n)
begin
case (measure_ch)
0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE};
1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE};
2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE};
3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE};
4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE};
5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE};
6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE};
7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE};
default : config_cmd <= {4'hF, 2'b00};
endcase
end
end
// serial config command to adc chip
wire config_init;
wire config_enable;
wire config_done;
reg [2:0] sdi_index;
assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0;
assign config_enable = (tick > `tCLK_START && tick <= `tCONFIG_END)?1'b1:1'b0; // > because this is negative edge triggle
assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0;
always @(negedge clk)
begin
if (config_init)
begin
ADC_SDI <= config_cmd[`CMD_BITS_NUM-1];
sdi_index <= `CMD_BITS_NUM-2;
end
else if (config_enable)
begin
ADC_SDI <= config_cmd[sdi_index];
sdi_index <= sdi_index - 1;
end
else if (config_done)
ADC_SDI <= 1'b0; //
end
endmodule
|
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