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/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
`include "defines.v"
module kotku_ml403 (
`ifdef DEBUG
output rs_,
output rw_,
output e_,
output [7:4] db_,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
output trx_,
`endif
output tft_lcd_clk_,
output [ 1:0] tft_lcd_r_,
output [ 1:0] tft_lcd_g_,
output [ 1:0] tft_lcd_b_,
output tft_lcd_hsync_,
output tft_lcd_vsync_,
input sys_clk_in_,
output sram_clk_,
output [20:0] sram_flash_addr_,
inout [31:0] sram_flash_data_,
output sram_flash_oe_n_,
output sram_flash_we_n_,
output [ 3:0] sram_bw_,
output sram_cen_,
output sram_adv_ld_n_,
output flash_ce2_,
inout ps2_clk_,
inout ps2_data_
);
// Net declarations
wire clk;
wire sys_clk;
wire rst2;
wire rst_lck;
wire [15:0] dat_i;
wire [15:0] dat_o;
wire [19:1] adr;
wire we;
wire tga;
wire stb;
wire ack;
wire [15:0] io_dat_i;
wire [ 1:0] sel;
wire cyc;
wire [ 7:0] keyb_dat_o;
wire keyb_io_arena;
wire keyb_io_status;
wire keyb_arena;
wire [15:0] vdu_dat_o;
wire vdu_ack_o;
wire vdu_mem_arena;
wire vdu_io_arena;
wire vdu_arena;
wire [15:0] flash_dat_o;
wire flash_stb;
wire flash_ack;
wire flash_mem_arena;
wire flash_io_arena;
wire flash_arena;
wire [15:0] zbt_dat_o;
wire zbt_stb;
wire zbt_ack;
wire [20:0] flash_addr_;
wire [20:0] sram_addr_;
wire flash_we_n_;
wire sram_we_n_;
wire intr;
wire inta;
wire clk_100M;
wire rst;
wire [15:0] vdu_dat_i;
wire [11:1] vdu_adr_i;
wire vdu_we_i;
wire [ 1:0] vdu_sel_i;
wire vdu_stb_i;
wire vdu_tga_i;
wire [19:1] zbt_adr_i;
wire zbt_we_i;
wire [ 1:0] zbt_sel_i;
wire zbt_stb_i;
`ifdef DEBUG
reg [31:0] cnt_time;
wire [35:0] control0;
wire [ 5:0] funct;
wire [ 2:0] state, next_state;
wire [15:0] x, y;
wire [15:0] imm;
wire [63:0] f1, f2;
wire [15:0] m1, m2;
wire [19:0] pc;
wire [15:0] cs, ip;
wire [15:0] aluo;
wire [ 2:0] cnt;
wire op;
wire block;
wire cpu_block;
wire clk_921600;
wire [15:0] ax, dx, bp, si, es;
wire [15:0] c;
wire [ 3:0] addr_c;
wire [15:0] cpu_dat_o;
wire [15:0] d;
wire [ 3:0] addr_d;
wire byte_op;
wire [ 8:0] flags;
wire [15:0] dbg_vdu_dat_o;
wire [11:1] dbg_vdu_adr_o;
wire dbg_vdu_we_o;
wire dbg_vdu_stb_o;
wire [ 1:0] dbg_vdu_sel_o;
wire dbg_vdu_tga_o;
wire [19:1] dbg_zbt_adr_o;
wire dbg_zbt_we_o;
wire [ 1:0] dbg_zbt_sel_o;
wire dbg_zbt_stb_o;
wire [ 2:0] old_zet_st;
wire [ 4:0] pack;
wire [19:0] tr_dat;
wire tr_new_pc;
wire tr_st;
wire tr_stb;
wire tr_ack;
wire addr_st;
wire end_seq;
wire ext_int;
wire cpu_block2;
`endif
// Register declarations
reg [15:0] io_reg;
reg [ 1:0] vdu_stb_sync;
reg [ 1:0] vdu_ack_sync;
// Module instantiations
clock c0 (
.clk_100M (clk_100M),
.sys_clk_in_ (sys_clk_in_),
.clk (sys_clk),
.vdu_clk (tft_lcd_clk_),
.rst (rst_lck)
);
vdu vdu0 (
// Wishbone signals
.wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock
.wb_rst_i (rst2),
.wb_dat_i (vdu_dat_i),
.wb_dat_o (vdu_dat_o),
.wb_adr_i (vdu_adr_i),
.wb_we_i (vdu_we_i),
.wb_tga_i (vdu_tga_i),
.wb_sel_i (vdu_sel_i),
.wb_stb_i (vdu_stb_sync[1]),
.wb_cyc_i (vdu_stb_sync[1]),
.wb_ack_o (vdu_ack_o),
// VGA pad signals
.vga_red_o (tft_lcd_r_),
.vga_green_o (tft_lcd_g_),
.vga_blue_o (tft_lcd_b_),
.horiz_sync (tft_lcd_hsync_),
.vert_sync (tft_lcd_vsync_)
);
flash_cntrl fc0 (
// Wishbone slave interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (flash_dat_o),
.wb_adr_i (adr[16:1]),
.wb_we_i (we),
.wb_tga_i (tga),
.wb_stb_i (flash_stb),
.wb_cyc_i (flash_stb),
.wb_ack_o (flash_ack),
// Pad signals
.flash_addr_ (flash_addr_),
.flash_data_ (sram_flash_data_[15:0]),
.flash_we_n_ (flash_we_n_),
.flash_ce2_ (flash_ce2_)
);
zbt_cntrl zbt0 (
`ifdef DEBUG
.cnt (cnt),
.op (op),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst2),
.wb_dat_i (dat_o),
.wb_dat_o (zbt_dat_o),
.wb_adr_i (zbt_adr_i),
.wb_we_i (zbt_we_i),
.wb_sel_i (zbt_sel_i),
.wb_stb_i (zbt_stb_i),
.wb_cyc_i (zbt_stb_i),
.wb_ack_o (zbt_ack),
// Pad signals
.sram_clk_ (sram_clk_),
.sram_addr_ (sram_addr_),
.sram_data_ (sram_flash_data_),
.sram_we_n_ (sram_we_n_),
.sram_bw_ (sram_bw_),
.sram_cen_ (sram_cen_),
.sram_adv_ld_n_ (sram_adv_ld_n_)
);
ps2_keyb #(5900, // number of clks for 60usec.
13, // number of bits needed for 60usec. timer
126, // number of clks for debounce
7, // number of bits needed for debounce timer
0 // Trap the shift keys, no event generated
) keyboard0 ( // Instance name
.wb_clk_i (clk_100M),
.wb_rst_i (rst),
.wb_dat_o (keyb_dat_o),
.wb_tgc_o (intr),
.wb_tgc_i (inta),
.ps2_clk_ (ps2_clk_),
.ps2_data_ (ps2_data_)
);
/*
timer timer0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_tgc_o (intr),
.wb_tgc_i (inta)
);
*/
cpu zet_proc (
`ifdef DEBUG
.cs (cs),
.ip (ip),
.state (state),
.next_state (next_state),
.iralu (funct),
.x (x),
.y (y),
.imm (imm),
.aluo (aluo),
.ax (ax),
.dx (dx),
.bp (bp),
.si (si),
.es (es),
.dbg_block (cpu_block),
.c (c),
.addr_c (addr_c),
.cpu_dat_o (cpu_dat_o),
.d (d),
.byte_exec (byte_op),
.addr_d (addr_d),
.flags (flags),
.end_seq (end_seq),
.ext_int (ext_int),
.cpu_block (cpu_block2),
`endif
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta)
);
`ifdef DEBUG
// Module instantiations
icon icon0 (
.CONTROL0 (control0)
);
ila ila0 (
.CONTROL (control0),
.CLK (clk),
.TRIG0 (adr),
.TRIG1 ({dat_o,dat_i}),
.TRIG2 (pc),
.TRIG3 ({clk,we,tga,cyc,stb,ack}),
.TRIG4 (funct),
.TRIG5 ({state,next_state}),
.TRIG6 ({intr,inta,flags,byte_op,addr_d}),
// .TRIG7 (imm),
// .TRIG7 (tr_dat[15:0]),
.TRIG7 (d),
.TRIG8 ({x,y}),
.TRIG9 (aluo),
.TRIG10 (sram_flash_addr_),
.TRIG11 (sram_flash_data_),
.TRIG12 ({sram_flash_oe_n_, sram_flash_we_n_, sram_bw_,
sram_cen_, sram_adv_ld_n_, flash_ce2_}),
.TRIG13 (cnt),
.TRIG14 ({vdu_mem_arena,flash_mem_arena,flash_stb,zbt_stb,op}),
.TRIG15 (cnt_time)
// .TRIG15 ({block,trx_,rst2,rst,tr_ack,tr_stb,tr_st,tr_new_pc,addr_st,11'h0,pack,old_zet_st,tr_dat[19:16]})
);
lcd_display lcd0 (
.f1 (f1), // 1st row
.f2 (f2), // 2nd row
.m1 (m1), // 1st row mask
.m2 (m2), // 2nd row mask
.clk (clk_100M), // 100 Mhz clock
.rst (rst_lck),
// Pad signals
.lcd_rs_ (rs_),
.lcd_rw_ (rw_),
.lcd_e_ (e_),
.lcd_dat_ (db_)
);
hw_dbg dbg0 (
.clk (clk),
.rst_lck (rst2),
.rst (rst),
.butc_ (butc_),
.bute_ (bute_),
.butw_ (butw_),
.butn_ (butn_),
.buts_ (buts_),
.vdu_dat_o (dbg_vdu_dat_o),
.vdu_adr_o (dbg_vdu_adr_o),
.vdu_we_o (dbg_vdu_we_o),
.vdu_stb_o (dbg_vdu_stb_o),
.vdu_sel_o (dbg_vdu_sel_o),
.vdu_tga_o (dbg_vdu_tga_o),
.vdu_ack_i (vdu_ack_sync[1]),
.zbt_dat_i (zbt_dat_o),
.zbt_adr_o (dbg_zbt_adr_o),
.zbt_we_o (dbg_zbt_we_o),
.zbt_sel_o (dbg_zbt_sel_o),
.zbt_stb_o (dbg_zbt_stb_o),
.zbt_ack_i (zbt_ack)
);
clk_uart clk0 (
.clk_100M (clk_100M),
.rst (rst_lck),
.clk_921600 (clk_921600),
.rst2 (rst2)
);
pc_trace pc0 (
.old_zet_st (old_zet_st),
.dat (tr_dat),
.new_pc (tr_new_pc),
.st (tr_st),
.stb (tr_stb),
.ack (tr_ack),
.pack (pack),
.addr_st (addr_st),
.trx_ (trx_),
.clk (clk),
.rst (rst2),
.pc (pc),
.zet_st (state),
.block (block)
);
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc };
assign m1 = 16'b1011110111101010;
assign m2 = 16'b1111101110011111;
assign pc = (cs << 4) + ip;
assign vdu_dat_i = rst ? dbg_vdu_dat_o : dat_o;
assign vdu_adr_i = rst ? dbg_vdu_adr_o : adr[11:1];
assign vdu_we_i = rst ? dbg_vdu_we_o : we;
assign vdu_sel_i = rst ? dbg_vdu_sel_o : sel;
assign vdu_stb_i = rst ? dbg_vdu_stb_o : stb & cyc & vdu_arena;
assign vdu_tga_i = rst ? dbg_vdu_tga_o : tga;
assign zbt_adr_i = rst ? dbg_zbt_adr_o : adr;
assign zbt_we_i = rst ? dbg_zbt_we_o : we;
assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel;
assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb;
`ifdef DEBUG_TRACE
assign cpu_block = block;
`else
assign cpu_block = 1'b0;
`endif
`else
assign vdu_dat_i = dat_o;
assign vdu_adr_i = adr[11:1];
assign vdu_we_i = we;
assign vdu_sel_i = sel;
assign vdu_stb_i = stb & cyc & vdu_arena;
assign vdu_tga_i = tga;
assign zbt_adr_i = adr;
assign zbt_we_i = we;
assign zbt_sel_i = sel;
assign zbt_stb_i = zbt_stb;
assign rst2 = rst_lck;
`endif
`ifdef DEBUG_TRACE
assign clk = clk_921600;
`else
assign clk = sys_clk;
`endif
assign io_dat_i = flash_io_arena ? flash_dat_o
: (vdu_io_arena ? vdu_dat_o
: (keyb_io_arena ? keyb_dat_o
: (keyb_io_status ? 16'h10 : 16'h0)));
assign dat_i = inta ? 16'd9 : (tga ? io_dat_i
: (vdu_mem_arena ? vdu_dat_o
: (flash_mem_arena ? flash_dat_o : zbt_dat_o)));
assign flash_mem_arena = (adr[19:16]==4'hc || adr[19:16]==4'hf);
assign vdu_mem_arena = (adr[19:12]==8'hb8);
assign flash_io_arena = (adr[15:9]==7'b1110_000);
assign vdu_io_arena = (adr[15:4]==12'h03d) &&
((adr[3:1]==3'h2 && we)
|| (adr[3:1]==3'h5 && !we));
assign keyb_io_arena = (adr[15:1]==15'h0030 && !we);
// MS-DOS is reading IO address 0x64 to check the inhibit bit
assign keyb_io_status = (adr[15:1]==15'h0032 && !we);
assign flash_arena = (!tga & flash_mem_arena)
| (tga & flash_io_arena);
assign vdu_arena = (!tga & vdu_mem_arena)
| (tga & vdu_io_arena);
assign keyb_arena = (tga & keyb_io_arena);
assign flash_stb = flash_arena & stb & cyc;
assign zbt_stb = !vdu_mem_arena & !flash_mem_arena
& !tga & stb & cyc;
assign ack = tga ? (flash_io_arena ? flash_ack
: (vdu_io_arena ? vdu_ack_sync[1] : (stb & cyc)))
: (vdu_mem_arena ? vdu_ack_sync[1]
: (flash_mem_arena ? flash_ack : zbt_ack));
assign sram_flash_oe_n_ = 1'b0;
assign sram_flash_addr_ = flash_arena ? flash_addr_
: sram_addr_;
assign sram_flash_we_n_ = flash_arena ? flash_we_n_
: sram_we_n_;
// Behaviour
// vdu_stb_sync[0]
always @(posedge tft_lcd_clk_)
vdu_stb_sync[0] <= vdu_stb_i;
// vdu_stb_sync[1]
always @(posedge clk)
vdu_stb_sync[1] <= vdu_stb_sync[0];
// vdu_ack_sync[0]
always @(posedge clk) vdu_ack_sync[0] <= vdu_ack_o;
// vdu_ack_sync[1]
always @(posedge clk) vdu_ack_sync[1] <= vdu_ack_sync[0];
// io_reg
always @(posedge clk)
io_reg <= rst ? 16'h0
: ((tga && stb && cyc && we && adr[15:8]==8'hf1) ?
dat_o : io_reg );
`ifdef DEBUG
// cnt_time
always @(posedge clk)
cnt_time <= rst ? 32'h0 : (cnt_time + 32'h1);
`else
assign rst = rst_lck;
`endif
endmodule
|
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
//`include "regfile.v"
// Behavioral model for the FIFO queue
module FIFO(data_out, empty, full, data_in, push, pop, reset, clk);
// Definitions for the constants the SIPO convertor
// parameter PARAM_NAME = VALUE;
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
//parameter DEPTH = 3; // DEPTH = 2^DEPTH_P2 = 2^3
//parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// Output signals representing the end of the transaction
// Output of the FIFO queue
output [WIDTH-1:0] data_out;
// Indicate if circular FIFO is empty when HIGH
output empty;
// Indicate if circular FIFO is full when HIGH
output full;
// ===============================================================
// Input signals
// Input data coming in to the register file
input [WIDTH-1:0] data_in;
// Flag to indicate if data is to be added to the circular FIFO
input push;
// Flag to indicate if data is to be removed from the circular FIFO
input pop;
// Flag to indicate if the circular FIFO should be emptied
input reset;
// Clock signal for the circular FIFO
input clk;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [WIDTH-1:0] data_out; // Output signals
reg empty,full; // Output signal
// Addresses for write and read operations
reg [DEPTH-1:0] wraddr, rdaddr;
// Read pointer
//reg rd_ptr;
// Write pointer
//reg wr_ptr;
// Storage locations
reg [DEPTH-1:0] reg_file [WIDTH-1:0];
reg [DEPTH-1:0] num_elems;
// ===============================================================
// Definitions for the states in the FIFO queue
// parameter PARAM_NAME = VALUE;
// ===============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
/*
regfile rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
data_out,data_in,wraddr,rdaddr,push,clk);
*/
// ===============================================================
// When the signal is reset
always @(reset)
begin
data_out=8'd0;
empty=1'd0;
full=1'd0;
wraddr=8'd0;
rdaddr=8'd0;
num_elems=8'd0;
end
// ===============================================================
always @(posedge clk)
begin
// If push and pop are HIGH, perform no operations
if(push && (~full) && (~pop))
begin
reg_file[wraddr] = data_in;
wraddr=(wraddr+1)%DEPTH;
num_elems=num_elems+1;
if(empty)
begin
empty=1'd0;
end
// Is the circular FIFO full?
//if(wraddr==(rdaddr-1))
if((wraddr==rdaddr) &&(~empty) && (num_elems==DEPTH))
begin
// Yes...
full=1'd1;
end
else
begin
// NO...
full=1'd0;
end
end
else if(pop && (~empty) && (~push))
begin
data_out=reg_file[rdaddr];
rdaddr=(rdaddr+1)%DEPTH;
num_elems=num_elems-1;
if(full)
begin
full=1'd0;
end
// Is the circular FIFO empty?
if(wraddr==rdaddr)
begin
// Yes...
empty=1'd1;
end
else
begin
// NO...
empty=1'd0;
end
end
/*
else if(full)
begin
if((wraddr!=rdaddr) || (num_elems!=DEPTH) || (empty))
begin
// Yes...
full=1'd0;
end
end
else if(empty)
begin
if(wraddr!=rdaddr)
begin
// NO...
empty=1'd0;
end
end
else if(wraddr!=rdaddr)
begin
empty=1'd0;
full=1'd0;
end
*/
end
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* XGMII control/data deinterleave
*/
module xgmii_deinterleave
(
input wire [72:0] input_xgmii_dc,
output wire [63:0] output_xgmii_d,
output wire [7:0] output_xgmii_c
);
assign output_xgmii_d[7:0] = input_xgmii_dc[7:0];
assign output_xgmii_c[0] = input_xgmii_dc[8];
assign output_xgmii_d[15:8] = input_xgmii_dc[16:9];
assign output_xgmii_c[1] = input_xgmii_dc[17];
assign output_xgmii_d[23:16] = input_xgmii_dc[25:18];
assign output_xgmii_c[2] = input_xgmii_dc[26];
assign output_xgmii_d[31:24] = input_xgmii_dc[34:27];
assign output_xgmii_c[3] = input_xgmii_dc[35];
assign output_xgmii_d[39:32] = input_xgmii_dc[43:36];
assign output_xgmii_c[4] = input_xgmii_dc[44];
assign output_xgmii_d[47:40] = input_xgmii_dc[52:45];
assign output_xgmii_c[5] = input_xgmii_dc[53];
assign output_xgmii_d[55:48] = input_xgmii_dc[61:54];
assign output_xgmii_c[6] = input_xgmii_dc[62];
assign output_xgmii_d[63:56] = input_xgmii_dc[70:63];
assign output_xgmii_c[7] = input_xgmii_dc[71];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { [email protected], [email protected] } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
//// and Physical Medium Attachment (PMA) sublayer, type ////
//// 1000BASE-X"; see : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section3.pdf, Clause/Section 36. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
`include "ge_1000baseX_regs.v"
`include "ge_1000baseX_constants.v"
module ge_1000baseX #(
parameter PHY_ADDR = 5'b00000,
BASEX_AN_MODE = 0
)(
// Clocks
input rx_ck,
input tx_ck,
// Resets
input rx_reset,
input tx_reset,
// Startup interface
input startup_enable,
// RLK1221 receive TBI bus
input [9:0] tbi_rxd,
// TLK1221 transmit TBI bus
output [9:0] tbi_txd,
// Receive GMII bus
output [7:0] gmii_rxd,
output gmii_rx_dv,
output gmii_rx_er,
output gmii_col,
output reg gmii_cs,
// Transmit GMII bus
input [7:0] gmii_txd,
input gmii_tx_en,
input gmii_tx_er,
input repeater_mode,
// MDIO interface
input mdc_reset,
input mdio_i,
output mdio_o,
input mdc,
// DEBUG
output [31:0] debug
);
//////////////////////////////////////////////////////////////////////////////
// IEEE Std 802.3-2008 Clause 22 "Reconcilliation Sublayer (RS) and
// Media Independent Interface (MII)IEEE 802.3-2005 Clause 22
//////////////////////////////////////////////////////////////////////////////
wire mdio_in, mdio_out, mdio_oe;
wire [15:0] gmii_reg_wr;
wire [15:0] gmii_reg_rd;
wire [4:0] gmii_reg_addr;
wire gmii_reg_wr_strobe;
ge_1000baseX_mdio #(
.PHY_ADDR(PHY_ADDR)
) gmii_mdioi(
.reset(mdc_reset),
.mdc(mdc),
.mdio(mdio_in),
.mdio_out(mdio_out),
.mdio_oe(mdio_oe),
.data_addr(gmii_reg_addr),
.data_rd(gmii_reg_rd),
.data_wr(gmii_reg_wr),
.strobe_wr(gmii_reg_wr_strobe)
);
// MDIO tristate drivers.
//assign mdio = (mdio_oe) ? mdio_out : 1'bz;
assign mdio_o = (mdio_oe) ? mdio_out : 1'b0;
assign mdio_in = mdio_i;
//////////////////////////////////////////////////////////////////////////////
// IEEE 802.3-2008 1000BASE-X PCS OUI and version Number
//////////////////////////////////////////////////////////////////////////////
wire [23:0] IEEE_OUI = 24'ha1b2c3;
wire [7:0] version = { 4'b0000, 4'b0001 };
//////////////////////////////////////////////////////////////////////////////
// Aneg configuration registers
//////////////////////////////////////////////////////////////////////////////
wire [15:0] tx_config_reg; wire [15:0] rx_config_reg; wire rx_config_reg_set;
//////////////////////////////////////////////////////////////////////////////
// GMII register 0 - Basic Control - IEEE 802.3-8 1000BASE-X clause 37 page 35
//////////////////////////////////////////////////////////////////////////////
reg [15:0] gmii_reg_0;
wire mr_main_reset, mr_loopback, mr_restart_an, mr_an_enable;
assign mr_main_reset = gmii_reg_0[15];
assign mr_loopback = gmii_reg_0[14];
assign mr_an_enable = gmii_reg_0[12];
assign mr_restart_an = gmii_reg_0[9];
`ifdef MODEL_TECH
// Register 0 bit 11 (normally power-down) used in simulation
// to simulate fibre being inserted and removed
//
wire signal_detect_int = (gmii_reg_0[11]);
`else
wire signal_detect_int = 1'b1;
`endif
//////////////////////////////////////////////////////////////////////////////
// Safe versions of various signals in the RX clock domain
//////////////////////////////////////////////////////////////////////////////
reg [1:0] mr_main_reset_rxc, mr_loopback_rxc, mr_restart_an_rxc;
reg [1:0] signal_detect_rxc, mr_an_enable_rxc, startup_enable_rxc;
always @(posedge rx_ck, posedge rx_reset)
if (rx_reset) begin
mr_main_reset_rxc <= 2'b00; mr_loopback_rxc <= 2'b00;
mr_restart_an_rxc <= 2'b00; mr_an_enable_rxc <= 2'b00;
signal_detect_rxc <= 2'b00; startup_enable_rxc <= 2'b00;
end
else begin
mr_main_reset_rxc <= { mr_main_reset_rxc[0], mr_main_reset };
mr_loopback_rxc <= { mr_loopback_rxc[0], mr_loopback };
mr_restart_an_rxc <= { mr_restart_an_rxc[0], mr_restart_an };
mr_an_enable_rxc <= { mr_an_enable_rxc[0], mr_an_enable };
signal_detect_rxc <= { signal_detect_rxc[0], signal_detect_int };
startup_enable_rxc <= { startup_enable_rxc[0], startup_enable };
end
// Speed select - when AN disabled
wire [1:0] speed_select = {gmii_reg_0[6], gmii_reg_0[13]};
`ifdef MODEL_TECH
`define GMII_REG_0_RESET {8'h19, 8'h40}
`else
`define GMII_REG_0_RESET {8'h11, 8'h40}
`endif
//////////////////////////////////////////////////////////////////////////////
// GMII register 1 - Basic Status - IEEE 802.3-5 1000baseLX clause 37 page 36
//////////////////////////////////////////////////////////////////////////////
wire mr_an_complete, sync_status;
`ifdef MODEL_TECH
// For simulation - sync_status is on gmii_reg 1 bit 7 - currently unused
wire [15:0] gmii_reg_1 = { 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
sync_status, 1'b1, mr_an_complete, 1'b0,
1'b1, signal_detect_rxc[1], 1'b0, 1'b0};
`else
wire [15:0] gmii_reg_1 = { 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
sync_status, 1'b1, mr_an_complete, 1'b0,
1'b1, signal_detect_rxc[1], 1'b0, 1'b0};
`endif
//////////////////////////////////////////////////////////////////////////////
// GMII register 2 - PHY Identifier 1 - IEEE 802.3-5 1000baseX
// clause 37 page 36
//////////////////////////////////////////////////////////////////////////////
wire [15:0] gmii_reg_2 = { IEEE_OUI[15:8], IEEE_OUI[23:16]};
//////////////////////////////////////////////////////////////////////////////
// --- GMII register 3 - PHY Identifier 2 - IEEE 802.3-5 1000baseX
// clause 37 page 36
//////////////////////////////////////////////////////////////////////////////
wire [15:0] gmii_reg_3 = { version, IEEE_OUI[7:0] };
//////////////////////////////////////////////////////////////////////////////
// GMII register 4 - Auto-Negotiation Advertisement - IEEE 802.3-5 1000baseX
// clause 37 page 37
//////////////////////////////////////////////////////////////////////////////
reg [15:0] gmii_reg_4;
wire [15:0] mr_adv_ability;
// See IEEE 802.3-5 1000baseLX clause 37 page 82 - Table 37-1 for these
assign mr_adv_ability = gmii_reg_4;
`define GMII_REG_4_RESET 16'b0000000000000001
//////////////////////////////////////////////////////////////////////////////
// GMII register 5 - Auto-Negotiation Link Partner Ability - IEEE 802.3-5
// 1000baseX clause 37 page 37
//////////////////////////////////////////////////////////////////////////////
wire [15:0] mr_lp_adv_ability;
wire [15:0] gmii_reg_5 = mr_lp_adv_ability;
//////////////////////////////////////////////////////////////////////////////
// GMII register 6 - Auto-Negotiation Expansion - IEEE 802.3-5 1000baseX
// clause 37 page 38
//////////////////////////////////////////////////////////////////////////////
wire [15:0] gmii_reg_6;
wire mr_np_abl, mr_page_rx;
assign gmii_reg_6 = { 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0,
mr_np_abl, 1'b0, mr_page_rx,1'b0};
//////////////////////////////////////////////////////////////////////////////
// GMII register 7 - Auto-Negotiation Link Partner Next Page - IEEE 802.3-5
// 1000baseX clause 37 page 38
//////////////////////////////////////////////////////////////////////////////
reg [15:0] gmii_reg_7;
wire[15:0] mr_np_tx;
assign mr_np_tx = gmii_reg_7;
`define GMII_REG_7_RESET 16'b0000000000000000
//////////////////////////////////////////////////////////////////////////////
// GMII register 8 - Auto-Negotiation Link Partner Next Page - IEEE 802.3-5
// 1000baseX clause 37 page 38
//////////////////////////////////////////////////////////////////////////////
wire [15:0] gmii_reg_8;
wire [15:0] mr_lp_np_rx;
assign gmii_reg_8 = mr_lp_np_rx;
//////////////////////////////////////////////////////////////////////////////
// GMII register 9 - DEBUG REG
//////////////////////////////////////////////////////////////////////////////
//debug
wire [4:0] debug_pcs_rx_present, debug_pcs_tx_present;
wire [3:0] debug_pcs_sync_present, debug_pcs_an_present;
wire [15:0] gmii_reg_9 = { 1'b1, 1'b1,
debug_pcs_an_present,
debug_pcs_rx_present,
debug_pcs_tx_present};
//////////////////////////////////////////////////////////////////////////////
// IEEE Std 802.3-2008 Clause 22 "Reconcilliation Sublayer (RS) and
// Media Independent Interface (MII)IEEE 802.3-2005 Clause 22
//////////////////////////////////////////////////////////////////////////////
// Read operations
assign gmii_reg_rd = (gmii_reg_addr == `GMII_BASIC_CTRL) ? gmii_reg_0 :
(gmii_reg_addr == `GMII_BASIC_STATUS) ? gmii_reg_1 :
(gmii_reg_addr == `GMII_PHY_ID1) ? gmii_reg_2 :
(gmii_reg_addr == `GMII_PHY_ID2) ? gmii_reg_3 :
(gmii_reg_addr == `GMII_AN_ADV) ? gmii_reg_4 :
(gmii_reg_addr == `GMII_AN_LP_ADV) ? gmii_reg_5 :
(gmii_reg_addr == `GMII_AN_EXPANSION) ? gmii_reg_6 :
(gmii_reg_addr == `GMII_AN_NP) ? gmii_reg_7 :
(gmii_reg_addr == `GMII_AN_LP_NP) ? gmii_reg_8 :
(gmii_reg_addr == `GMII_DEBUG) ? gmii_reg_9 : 5'b00000;
// Write operations
always @(posedge mdc or posedge mdc_reset)
if (mdc_reset)
begin
gmii_reg_0 <= `GMII_REG_0_RESET;
gmii_reg_4 <= `GMII_REG_4_RESET;
gmii_reg_7 <= `GMII_REG_7_RESET;
end
else
if (gmii_reg_wr_strobe)
begin
case (gmii_reg_addr)
`GMII_BASIC_CTRL : gmii_reg_0 <= gmii_reg_wr;
`GMII_AN_ADV : gmii_reg_4 <= gmii_reg_wr;
`GMII_AN_NP : gmii_reg_7 <= gmii_reg_wr;
endcase
end
else
begin
// mr_an_restart is self clearing
if (gmii_reg_0[9]) gmii_reg_0[9] <= 1'b0;
// mr_main_reset) is self clearing
else if (gmii_reg_0[15]) gmii_reg_0[15] <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////
// Status
//////////////////////////////////////////////////////////////////////////////
wire [2:0] xmit;
wire carrier_detect;
wire transmitting, receiving;
//////////////////////////////////////////////////////////////////////////////
// Generate GMII Carrier Sense - IEEE 802.3-2008 Clause 36 - 26.2.5.2.5
//////////////////////////////////////////////////////////////////////////////
always @(posedge rx_ck, posedge rx_reset)
if (rx_reset)
gmii_cs <= 1'b0;
else
if ((~repeater_mode & transmitting) | receiving) begin gmii_cs <= 1'b1; end
else if ((repeater_mode | ~transmitting) & ~receiving) begin gmii_cs <= 1'b0; end
//////////////////////////////////////////////////////////////////////////////
// delayed versions of 10b interface
//////////////////////////////////////////////////////////////////////////////
reg [9:0] tbi_rxd_d1, tbi_rxd_d2, tbi_rxd_d3, tbi_rxd_d4;
always @(posedge rx_ck, posedge rx_reset)
begin
tbi_rxd_d1 <= (rx_reset) ? 0 : tbi_rxd;
tbi_rxd_d2 <= (rx_reset) ? 0 : tbi_rxd_d1;
tbi_rxd_d3 <= (rx_reset) ? 0 : tbi_rxd_d2;
tbi_rxd_d4 <= (rx_reset) ? 0 : tbi_rxd_d3;
end
//////////////////////////////////////////////////////////////////////////////
/// 8b10 decoder module
//////////////////////////////////////////////////////////////////////////////
wire decoder_K, decoder_disparity_err, decoder_coding_err;
wire [7:0] decoder_8b_rxd;
decoder_8b10b decoder_8b10bi(
.RBYTECLK(rx_ck),
.reset(rx_reset),
// 10B input
.tbi(tbi_rxd_d1),
// Data/special code-group ctrl
.K_out(decoder_K),
// 8B output
.ebi(decoder_8b_rxd),
// Disparity error
.disparity_err(decoder_disparity_err),
// Disparity output
.disparity(decoder_disparity_out),
// Coding error
.coding_err(decoder_coding_err)
);
`ifdef MODEL_TECH
wire [4:0] decoder_8b_rxd_X;
wire [2:0] decoder_8b_rxd_Y;
assign {decoder_8b_rxd_Y, decoder_8b_rxd_X} = decoder_8b_rxd;
`endif
//////////////////////////////////////////////////////////////////////////////
// Instantiate 802.3-2005 PCS sync module - 802.3-2008 Clause 36
//////////////////////////////////////////////////////////////////////////////
wire sync_K, sync_rx_even;
wire [7:0] sync_8b_rxd;
`ifdef MODEL_TECH
wire [4:0] sync_8b_rxd_X = sync_8b_rxd[4:0];
wire [2:0] sync_8b_rxd_Y = sync_8b_rxd[7:5];
`endif
ge_1000baseX_sync ge_1000baseX_sync_i(
.ck(rx_ck), .reset(rx_reset),
.startup_enable(startup_enable_rxc[1]),
// 8B input from 8b10 decoder
.ebi_rxd(decoder_8b_rxd),
.ebi_K(decoder_K),
// 8B output from sync
.ebi_rxd_out(sync_8b_rxd),
.ebi_K_out(sync_K),
// Synchronisation status
.sync_status(sync_status),
.rx_even(sync_rx_even),
.decoder_disparity_err(decoder_disparity_err),
.decoder_coding_err(decoder_coding_err),
.loopback(mr_loopback_rxc[1]),
.debug_pcs_sync_present(debug_pcs_sync_present)
);
//////////////////////////////////////////////////////////////////////////////
// Carrier Detect - IEEE 802.3-2008 Section 36.2.5.1.4
//////////////////////////////////////////////////////////////////////////////
wire [5:0] sb; wire [3:0] fb;
wire RDn_cd_fail_match1, RDn_cd_fail_match2, RDn_cd_fail_match;
wire RDp_cd_fail_match1, RDp_cd_fail_match2, RDp_cd_fail_match;
assign sb[5:0] = tbi_rxd_d4[9:4];
assign fb[3:0] = tbi_rxd_d4[3:0];
assign RDn_cd_fail_match1 = ((sb == 6'b110000) & ((fb == 4'b0101) | (fb == 4'b0100) | (fb == 4'b0111) | (fb == 4'b0001) | (fb==4'b1101)));
assign RDn_cd_fail_match2 = ((fb == 4'b0101) & ((sb==6'b110001) |(sb==6'b110010) | (sb==6'b110100) | (sb==6'b111000) | (sb==6'b100000) | (sb==6'b010000)));
assign RDn_cd_fail_match = RDn_cd_fail_match1 | RDn_cd_fail_match2;
assign RDp_cd_fail_match1 = ((sb == 6'b001111) & ((fb==4'b1010)|(fb==4'b1011)|(fb==4'b1000)|(fb==4'b1110)|(fb==4'b0010)));
assign RDp_cd_fail_match2 = ((fb == 4'b1010) & ((sb==6'b001110)|(sb==6'b001101)|(sb==6'b001011)|(sb==6'b000111)|(sb==6'b011111)|(sb==6'b101111)));
assign RDp_cd_fail_match = RDp_cd_fail_match1 | RDp_cd_fail_match2;
assign carrier_detect = sync_rx_even & ~RDn_cd_fail_match & ~RDp_cd_fail_match;
//////////////////////////////////////////////////////////////////////////////
// 802.3-2008 1000baseX PCS autonegotiation (AN) module - 802.3-2008 Clause 37
//////////////////////////////////////////////////////////////////////////////
wire [2:0] rudi; // RX_UNITDATA.indicate messages
wire [17:0] debug_linktimer;
wire debug_an_restart_state;
assign debug = { 13'b0, debug_an_restart_state, debug_linktimer };
ge_1000baseX_an
#(
.BASEX_AN_MODE(BASEX_AN_MODE)
)
ge_1000baseX_an_i(
.ck(rx_ck),.reset(rx_reset),
.startup_enable(startup_enable_rxc[1]),
// Auto-negotiation ctrl
.xmit(xmit),
.rx_config(rx_config_reg),
.rx_config_set(rx_config_reg_set),
.tx_config(tx_config_reg),
// RX_UNITDATA.indicate messages
.rudi(rudi),
// Auto-negotiation /C/ and /I/ matching
.ability_match(ability_match),
.acknowledge_match(acknowledge_match),
.consistency_match(consistency_match),
.idle_match(idle_match),
// Synchronisation Status
.sync_status(sync_status),
// GMII Register 0 - AN Basic Control
.mr_main_reset(mr_main_reset_rxc[1]),
.mr_loopback(mr_loopback_rxc[1]),
.mr_restart_an(mr_restart_an_rxc[1]),
.mr_an_enable(mr_an_enable_rxc[1]),
// GMII Register 1 - AN Basic Status
.mr_an_complete(mr_an_complete),
// GMII register 4 - AN Advertisement
.mr_adv_ability(mr_adv_ability),
// GMII register 5 - AN Link Partner Ability
.mr_lp_adv_ability(mr_lp_adv_ability),
// GMII register 6 - AN Expansion
.mr_np_abl(mr_np_abl),
.mr_page_rx(mr_page_rx),
// GMII register 7 - AN Next Page
.mr_np_tx(mr_np_tx),
// GMII register 8 - AN Link Partner Next Page
.mr_lp_np_rx(mr_lp_np_rx),
.debug_pcs_an_present(debug_pcs_an_present),
.debug_linktimer(debug_linktimer),
.debug_an_restart_state(debug_an_restart_state)
);
wire tx_frame_pulse, frame_rx_pulse;
//////////////////////////////////////////////////////////////////////////////
// 802.3-2008 1000baseX PCS receive module - 802.3-2008 Clause 36
//////////////////////////////////////////////////////////////////////////////
ge_1000baseX_rx ge_1000base_rxi(
.ck(rx_ck), .reset(rx_reset),
// Receive 8B bus from sync module
.ebi_rxd(sync_8b_rxd),
.ebi_K(sync_K),
.rx_even(sync_rx_even),
.carrier_detect(carrier_detect),
.sync_status(sync_status),
// Receive frame pulse
.rx_frame_pulse(rx_frame_pulse),
// Receive GMII bus
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
// Auto-negotiation ctrl
.xmit(xmit),
.mr_main_reset(mr_main_reset_rxc[1]),
.rx_config(rx_config_reg),
.rx_config_set(rx_config_reg_set),
.rudi(rudi),
// Auto-negotiation /C/ and /I/ matching
.ability_match(ability_match),
.acknowledge_match(acknowledge_match),
.consistency_match(consistency_match),
.idle_match(idle_match),
.receiving(receiving),
.debug_pcs_rx_present(debug_pcs_rx_present)
);
//////////////////////////////////////////////////////////////////////////////
// Safe versions of various signals in the TX clock domain
//////////////////////////////////////////////////////////////////////////////
reg [1:0] mr_main_reset_txc, receiving_txc, signal_detect_txc, startup_enable_txc;
always @(posedge tx_ck, posedge tx_reset)
if (tx_reset) begin
mr_main_reset_txc <= 2'b00; receiving_txc <= 2'b00;
signal_detect_txc <= 2'b00; startup_enable_txc <= 2'b00;
end
else
begin
mr_main_reset_txc <= { mr_main_reset_txc[0], mr_main_reset };
receiving_txc <= { receiving_txc[0], receiving };
signal_detect_txc <= { signal_detect_txc[0], 1'b1 };
startup_enable_txc <= { startup_enable_txc[0], startup_enable };
end
reg [2:0] xmit_txc, xmit_txc0;
always @(posedge tx_ck, posedge tx_reset)
begin
xmit_txc <= (tx_reset) ? `XMIT_IDLE : xmit_txc0;
xmit_txc0 <= (tx_reset) ? `XMIT_IDLE : xmit;
end
//////////////////////////////////////////////////////////////////////////////
// 802.3-2008 1000baseX PCS transmit module 802.3-2008 Clause 36
//////////////////////////////////////////////////////////////////////////////
ge_1000baseX_tx ge_1000baseX_txi(
// --- TX clock and reset ---
.ck(tx_ck),
.reset(tx_reset),
// --- RLK1221 transmit TBI bus ---
.tbi_txd(tbi_txd),
// Transmit frame pulse
.tx_frame_pulse(tx_frame_pulse),
// --- Transmit GMII bus -
.gmii_tx_en_in(gmii_tx_en),
.gmii_tx_er_in(gmii_tx_er),
.gmii_txd_in(gmii_txd),
.gmii_col(gmii_col),
.receiving(receiving_txc[1]),
.transmitting(transmitting),
// --- Auto-negotiation ctrl ---
.xmit(xmit_txc),
.tx_config(tx_config_reg),
.mr_main_reset(mr_main_reset_txc[1]),
.debug_pcs_tx_present(debug_pcs_tx_present)
);
//////////////////////////////////////////////////////////////////////////////
// Frame transmit LED pulse
//////////////////////////////////////////////////////////////////////////////
reg [23:0] tx_led_counter;
reg tx_frame_pulse_latch;
reg tx_frame_activity;
always @(posedge tx_ck, posedge tx_reset)
if (tx_reset)
begin
tx_led_counter <= 0; tx_frame_activity <= 0; tx_frame_pulse_latch <= 1;
end
else
begin
tx_led_counter <= tx_led_counter + 1;
if (tx_frame_activity)
begin
if (~tx_led_counter[23]) begin tx_frame_pulse_latch <= 0;tx_frame_activity <= 0; end
end
else if (tx_led_counter[23] & tx_frame_pulse_latch) tx_frame_activity <= 1;
else if (tx_frame_pulse) tx_frame_pulse_latch <= 1;
end
//////////////////////////////////////////////////////////////////////////////
// Frame receive LED pulse
//////////////////////////////////////////////////////////////////////////////
reg [23:0] rx_led_counter;
reg rx_frame_pulse_latch;
reg rx_frame_activity;
always @(posedge rx_ck, posedge rx_reset)
if (rx_reset)
begin
rx_led_counter <= 0; rx_frame_activity <= 0; rx_frame_pulse_latch <= 1;
end
else
begin
rx_led_counter <= rx_led_counter + 1;
if (rx_frame_activity)
begin
if (~rx_led_counter[23]) begin rx_frame_pulse_latch <= 0;rx_frame_activity <= 0; end
end
else if (rx_led_counter[23] & rx_frame_pulse_latch) rx_frame_activity <= 1;
else if (rx_frame_pulse) rx_frame_pulse_latch <= 1;
end
wire fo_activity = rx_frame_activity | tx_frame_activity;
endmodule
|
// binary_vga_controller.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module binary_vga_controller (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) binary_vga_controller (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 09/01/2016 06:29:42 PM
// Design Name:
// Module Name: KOA_FPGA
// Project Name: Recursive Karatsuba Offman Multiplication
// Target Devices:
// Tool Versions:
// Description: RKOA optimization for DSP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KOA_FPGA
//#(parameter SW = 24)
#(parameter SW = 54)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if (SW<=18) begin
multiplier_C #(.W(SW)/*,.level(level1)*/) main(
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(sgf_result_o)
);
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_FPGA #(.SW(SW/2)/*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_FPGA #(.SW(SW/2)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
KOA_FPGA #(.SW(SW/2+1)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_FPGA #(.SW(SW/2)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_FPGA #(.SW((SW/2)+1)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_FPGA #(.SW(SW/2+2)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({leftside2,S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_PP_BLACKBOX_V
|
module sin_rom (
input wire [8:0] inadrs,
output wire [15:0] outsine);
assign outsine = sin_rom(inadrs);
function [15:0] sin_rom;
input [8:0] adrs;
begin
case (adrs)
9'D0 : sin_rom = 0 ;
9'D1 : sin_rom = 201 ;
9'D2 : sin_rom = 402 ;
9'D3 : sin_rom = 604 ;
9'D4 : sin_rom = 805 ;
9'D5 : sin_rom = 1007 ;
9'D6 : sin_rom = 1208 ;
9'D7 : sin_rom = 1410 ;
9'D8 : sin_rom = 1611 ;
9'D9 : sin_rom = 1812 ;
9'D10 : sin_rom = 2014 ;
9'D11 : sin_rom = 2215 ;
9'D12 : sin_rom = 2416 ;
9'D13 : sin_rom = 2618 ;
9'D14 : sin_rom = 2819 ;
9'D15 : sin_rom = 3020 ;
9'D16 : sin_rom = 3221 ;
9'D17 : sin_rom = 3423 ;
9'D18 : sin_rom = 3624 ;
9'D19 : sin_rom = 3825 ;
9'D20 : sin_rom = 4026 ;
9'D21 : sin_rom = 4227 ;
9'D22 : sin_rom = 4428 ;
9'D23 : sin_rom = 4629 ;
9'D24 : sin_rom = 4830 ;
9'D25 : sin_rom = 5031 ;
9'D26 : sin_rom = 5232 ;
9'D27 : sin_rom = 5433 ;
9'D28 : sin_rom = 5633 ;
9'D29 : sin_rom = 5834 ;
9'D30 : sin_rom = 6035 ;
9'D31 : sin_rom = 6235 ;
9'D32 : sin_rom = 6436 ;
9'D33 : sin_rom = 6636 ;
9'D34 : sin_rom = 6837 ;
9'D35 : sin_rom = 7037 ;
9'D36 : sin_rom = 7237 ;
9'D37 : sin_rom = 7437 ;
9'D38 : sin_rom = 7637 ;
9'D39 : sin_rom = 7837 ;
9'D40 : sin_rom = 8037 ;
9'D41 : sin_rom = 8237 ;
9'D42 : sin_rom = 8437 ;
9'D43 : sin_rom = 8637 ;
9'D44 : sin_rom = 8837 ;
9'D45 : sin_rom = 9036 ;
9'D46 : sin_rom = 9236 ;
9'D47 : sin_rom = 9435 ;
9'D48 : sin_rom = 9634 ;
9'D49 : sin_rom = 9834 ;
9'D50 : sin_rom = 10033 ;
9'D51 : sin_rom = 10232 ;
9'D52 : sin_rom = 10431 ;
9'D53 : sin_rom = 10629 ;
9'D54 : sin_rom = 10828 ;
9'D55 : sin_rom = 11027 ;
9'D56 : sin_rom = 11225 ;
9'D57 : sin_rom = 11424 ;
9'D58 : sin_rom = 11622 ;
9'D59 : sin_rom = 11820 ;
9'D60 : sin_rom = 12018 ;
9'D61 : sin_rom = 12216 ;
9'D62 : sin_rom = 12414 ;
9'D63 : sin_rom = 12612 ;
9'D64 : sin_rom = 12810 ;
9'D65 : sin_rom = 13007 ;
9'D66 : sin_rom = 13205 ;
9'D67 : sin_rom = 13402 ;
9'D68 : sin_rom = 13599 ;
9'D69 : sin_rom = 13796 ;
9'D70 : sin_rom = 13993 ;
9'D71 : sin_rom = 14190 ;
9'D72 : sin_rom = 14386 ;
9'D73 : sin_rom = 14583 ;
9'D74 : sin_rom = 14779 ;
9'D75 : sin_rom = 14975 ;
9'D76 : sin_rom = 15171 ;
9'D77 : sin_rom = 15367 ;
9'D78 : sin_rom = 15563 ;
9'D79 : sin_rom = 15759 ;
9'D80 : sin_rom = 15954 ;
9'D81 : sin_rom = 16149 ;
9'D82 : sin_rom = 16344 ;
9'D83 : sin_rom = 16539 ;
9'D84 : sin_rom = 16734 ;
9'D85 : sin_rom = 16929 ;
9'D86 : sin_rom = 17124 ;
9'D87 : sin_rom = 17318 ;
9'D88 : sin_rom = 17512 ;
9'D89 : sin_rom = 17706 ;
9'D90 : sin_rom = 17900 ;
9'D91 : sin_rom = 18094 ;
9'D92 : sin_rom = 18287 ;
9'D93 : sin_rom = 18481 ;
9'D94 : sin_rom = 18674 ;
9'D95 : sin_rom = 18867 ;
9'D96 : sin_rom = 19060 ;
9'D97 : sin_rom = 19252 ;
9'D98 : sin_rom = 19445 ;
9'D99 : sin_rom = 19637 ;
9'D100 : sin_rom = 19829 ;
9'D101 : sin_rom = 20021 ;
9'D102 : sin_rom = 20213 ;
9'D103 : sin_rom = 20404 ;
9'D104 : sin_rom = 20596 ;
9'D105 : sin_rom = 20787 ;
9'D106 : sin_rom = 20978 ;
9'D107 : sin_rom = 21169 ;
9'D108 : sin_rom = 21359 ;
9'D109 : sin_rom = 21550 ;
9'D110 : sin_rom = 21740 ;
9'D111 : sin_rom = 21930 ;
9'D112 : sin_rom = 22119 ;
9'D113 : sin_rom = 22309 ;
9'D114 : sin_rom = 22498 ;
9'D115 : sin_rom = 22687 ;
9'D116 : sin_rom = 22876 ;
9'D117 : sin_rom = 23065 ;
9'D118 : sin_rom = 23253 ;
9'D119 : sin_rom = 23442 ;
9'D120 : sin_rom = 23630 ;
9'D121 : sin_rom = 23817 ;
9'D122 : sin_rom = 24005 ;
9'D123 : sin_rom = 24192 ;
9'D124 : sin_rom = 24379 ;
9'D125 : sin_rom = 24566 ;
9'D126 : sin_rom = 24753 ;
9'D127 : sin_rom = 24939 ;
9'D128 : sin_rom = 25126 ;
9'D129 : sin_rom = 25312 ;
9'D130 : sin_rom = 25497 ;
9'D131 : sin_rom = 25683 ;
9'D132 : sin_rom = 25868 ;
9'D133 : sin_rom = 26053 ;
9'D134 : sin_rom = 26238 ;
9'D135 : sin_rom = 26422 ;
9'D136 : sin_rom = 26606 ;
9'D137 : sin_rom = 26790 ;
9'D138 : sin_rom = 26974 ;
9'D139 : sin_rom = 27157 ;
9'D140 : sin_rom = 27341 ;
9'D141 : sin_rom = 27524 ;
9'D142 : sin_rom = 27706 ;
9'D143 : sin_rom = 27889 ;
9'D144 : sin_rom = 28071 ;
9'D145 : sin_rom = 28253 ;
9'D146 : sin_rom = 28435 ;
9'D147 : sin_rom = 28616 ;
9'D148 : sin_rom = 28797 ;
9'D149 : sin_rom = 28978 ;
9'D150 : sin_rom = 29158 ;
9'D151 : sin_rom = 29339 ;
9'D152 : sin_rom = 29519 ;
9'D153 : sin_rom = 29698 ;
9'D154 : sin_rom = 29878 ;
9'D155 : sin_rom = 30057 ;
9'D156 : sin_rom = 30236 ;
9'D157 : sin_rom = 30414 ;
9'D158 : sin_rom = 30593 ;
9'D159 : sin_rom = 30771 ;
9'D160 : sin_rom = 30948 ;
9'D161 : sin_rom = 31126 ;
9'D162 : sin_rom = 31303 ;
9'D163 : sin_rom = 31480 ;
9'D164 : sin_rom = 31656 ;
9'D165 : sin_rom = 31833 ;
9'D166 : sin_rom = 32009 ;
9'D167 : sin_rom = 32184 ;
9'D168 : sin_rom = 32360 ;
9'D169 : sin_rom = 32535 ;
9'D170 : sin_rom = 32709 ;
9'D171 : sin_rom = 32884 ;
9'D172 : sin_rom = 33058 ;
9'D173 : sin_rom = 33232 ;
9'D174 : sin_rom = 33405 ;
9'D175 : sin_rom = 33578 ;
9'D176 : sin_rom = 33751 ;
9'D177 : sin_rom = 33924 ;
9'D178 : sin_rom = 34096 ;
9'D179 : sin_rom = 34268 ;
9'D180 : sin_rom = 34439 ;
9'D181 : sin_rom = 34611 ;
9'D182 : sin_rom = 34781 ;
9'D183 : sin_rom = 34952 ;
9'D184 : sin_rom = 35122 ;
9'D185 : sin_rom = 35292 ;
9'D186 : sin_rom = 35462 ;
9'D187 : sin_rom = 35631 ;
9'D188 : sin_rom = 35800 ;
9'D189 : sin_rom = 35968 ;
9'D190 : sin_rom = 36137 ;
9'D191 : sin_rom = 36305 ;
9'D192 : sin_rom = 36472 ;
9'D193 : sin_rom = 36639 ;
9'D194 : sin_rom = 36806 ;
9'D195 : sin_rom = 36973 ;
9'D196 : sin_rom = 37139 ;
9'D197 : sin_rom = 37305 ;
9'D198 : sin_rom = 37470 ;
9'D199 : sin_rom = 37635 ;
9'D200 : sin_rom = 37800 ;
9'D201 : sin_rom = 37964 ;
9'D202 : sin_rom = 38128 ;
9'D203 : sin_rom = 38292 ;
9'D204 : sin_rom = 38455 ;
9'D205 : sin_rom = 38618 ;
9'D206 : sin_rom = 38781 ;
9'D207 : sin_rom = 38943 ;
9'D208 : sin_rom = 39105 ;
9'D209 : sin_rom = 39266 ;
9'D210 : sin_rom = 39428 ;
9'D211 : sin_rom = 39588 ;
9'D212 : sin_rom = 39749 ;
9'D213 : sin_rom = 39909 ;
9'D214 : sin_rom = 40068 ;
9'D215 : sin_rom = 40227 ;
9'D216 : sin_rom = 40386 ;
9'D217 : sin_rom = 40545 ;
9'D218 : sin_rom = 40703 ;
9'D219 : sin_rom = 40861 ;
9'D220 : sin_rom = 41018 ;
9'D221 : sin_rom = 41175 ;
9'D222 : sin_rom = 41331 ;
9'D223 : sin_rom = 41487 ;
9'D224 : sin_rom = 41643 ;
9'D225 : sin_rom = 41799 ;
9'D226 : sin_rom = 41954 ;
9'D227 : sin_rom = 42108 ;
9'D228 : sin_rom = 42262 ;
9'D229 : sin_rom = 42416 ;
9'D230 : sin_rom = 42569 ;
9'D231 : sin_rom = 42722 ;
9'D232 : sin_rom = 42875 ;
9'D233 : sin_rom = 43027 ;
9'D234 : sin_rom = 43179 ;
9'D235 : sin_rom = 43330 ;
9'D236 : sin_rom = 43481 ;
9'D237 : sin_rom = 43632 ;
9'D238 : sin_rom = 43782 ;
9'D239 : sin_rom = 43931 ;
9'D240 : sin_rom = 44081 ;
9'D241 : sin_rom = 44230 ;
9'D242 : sin_rom = 44378 ;
9'D243 : sin_rom = 44526 ;
9'D244 : sin_rom = 44674 ;
9'D245 : sin_rom = 44821 ;
9'D246 : sin_rom = 44968 ;
9'D247 : sin_rom = 45114 ;
9'D248 : sin_rom = 45260 ;
9'D249 : sin_rom = 45405 ;
9'D250 : sin_rom = 45550 ;
9'D251 : sin_rom = 45695 ;
9'D252 : sin_rom = 45839 ;
9'D253 : sin_rom = 45983 ;
9'D254 : sin_rom = 46126 ;
9'D255 : sin_rom = 46269 ;
9'D256 : sin_rom = 46412 ;
9'D257 : sin_rom = 46554 ;
9'D258 : sin_rom = 46695 ;
9'D259 : sin_rom = 46836 ;
9'D260 : sin_rom = 46977 ;
9'D261 : sin_rom = 47117 ;
9'D262 : sin_rom = 47257 ;
9'D263 : sin_rom = 47396 ;
9'D264 : sin_rom = 47535 ;
9'D265 : sin_rom = 47674 ;
9'D266 : sin_rom = 47812 ;
9'D267 : sin_rom = 47949 ;
9'D268 : sin_rom = 48086 ;
9'D269 : sin_rom = 48223 ;
9'D270 : sin_rom = 48359 ;
9'D271 : sin_rom = 48495 ;
9'D272 : sin_rom = 48630 ;
9'D273 : sin_rom = 48765 ;
9'D274 : sin_rom = 48899 ;
9'D275 : sin_rom = 49033 ;
9'D276 : sin_rom = 49167 ;
9'D277 : sin_rom = 49300 ;
9'D278 : sin_rom = 49432 ;
9'D279 : sin_rom = 49564 ;
9'D280 : sin_rom = 49696 ;
9'D281 : sin_rom = 49827 ;
9'D282 : sin_rom = 49958 ;
9'D283 : sin_rom = 50088 ;
9'D284 : sin_rom = 50217 ;
9'D285 : sin_rom = 50347 ;
9'D286 : sin_rom = 50475 ;
9'D287 : sin_rom = 50604 ;
9'D288 : sin_rom = 50731 ;
9'D289 : sin_rom = 50859 ;
9'D290 : sin_rom = 50985 ;
9'D291 : sin_rom = 51112 ;
9'D292 : sin_rom = 51238 ;
9'D293 : sin_rom = 51363 ;
9'D294 : sin_rom = 51488 ;
9'D295 : sin_rom = 51612 ;
9'D296 : sin_rom = 51736 ;
9'D297 : sin_rom = 51860 ;
9'D298 : sin_rom = 51982 ;
9'D299 : sin_rom = 52105 ;
9'D300 : sin_rom = 52227 ;
9'D301 : sin_rom = 52348 ;
9'D302 : sin_rom = 52469 ;
9'D303 : sin_rom = 52590 ;
9'D304 : sin_rom = 52710 ;
9'D305 : sin_rom = 52829 ;
9'D306 : sin_rom = 52948 ;
9'D307 : sin_rom = 53067 ;
9'D308 : sin_rom = 53185 ;
9'D309 : sin_rom = 53302 ;
9'D310 : sin_rom = 53419 ;
9'D311 : sin_rom = 53535 ;
9'D312 : sin_rom = 53651 ;
9'D313 : sin_rom = 53767 ;
9'D314 : sin_rom = 53882 ;
9'D315 : sin_rom = 53996 ;
9'D316 : sin_rom = 54110 ;
9'D317 : sin_rom = 54223 ;
9'D318 : sin_rom = 54336 ;
9'D319 : sin_rom = 54449 ;
9'D320 : sin_rom = 54561 ;
9'D321 : sin_rom = 54672 ;
9'D322 : sin_rom = 54783 ;
9'D323 : sin_rom = 54893 ;
9'D324 : sin_rom = 55003 ;
9'D325 : sin_rom = 55112 ;
9'D326 : sin_rom = 55221 ;
9'D327 : sin_rom = 55329 ;
9'D328 : sin_rom = 55437 ;
9'D329 : sin_rom = 55544 ;
9'D330 : sin_rom = 55651 ;
9'D331 : sin_rom = 55757 ;
9'D332 : sin_rom = 55862 ;
9'D333 : sin_rom = 55967 ;
9'D334 : sin_rom = 56072 ;
9'D335 : sin_rom = 56176 ;
9'D336 : sin_rom = 56279 ;
9'D337 : sin_rom = 56382 ;
9'D338 : sin_rom = 56485 ;
9'D339 : sin_rom = 56587 ;
9'D340 : sin_rom = 56688 ;
9'D341 : sin_rom = 56789 ;
9'D342 : sin_rom = 56889 ;
9'D343 : sin_rom = 56989 ;
9'D344 : sin_rom = 57088 ;
9'D345 : sin_rom = 57187 ;
9'D346 : sin_rom = 57285 ;
9'D347 : sin_rom = 57382 ;
9'D348 : sin_rom = 57480 ;
9'D349 : sin_rom = 57576 ;
9'D350 : sin_rom = 57672 ;
9'D351 : sin_rom = 57767 ;
9'D352 : sin_rom = 57862 ;
9'D353 : sin_rom = 57957 ;
9'D354 : sin_rom = 58050 ;
9'D355 : sin_rom = 58144 ;
9'D356 : sin_rom = 58236 ;
9'D357 : sin_rom = 58328 ;
9'D358 : sin_rom = 58420 ;
9'D359 : sin_rom = 58511 ;
9'D360 : sin_rom = 58601 ;
9'D361 : sin_rom = 58691 ;
9'D362 : sin_rom = 58781 ;
9'D363 : sin_rom = 58869 ;
9'D364 : sin_rom = 58958 ;
9'D365 : sin_rom = 59045 ;
9'D366 : sin_rom = 59133 ;
9'D367 : sin_rom = 59219 ;
9'D368 : sin_rom = 59305 ;
9'D369 : sin_rom = 59391 ;
9'D370 : sin_rom = 59475 ;
9'D371 : sin_rom = 59560 ;
9'D372 : sin_rom = 59644 ;
9'D373 : sin_rom = 59727 ;
9'D374 : sin_rom = 59809 ;
9'D375 : sin_rom = 59891 ;
9'D376 : sin_rom = 59973 ;
9'D377 : sin_rom = 60054 ;
9'D378 : sin_rom = 60134 ;
9'D379 : sin_rom = 60214 ;
9'D380 : sin_rom = 60293 ;
9'D381 : sin_rom = 60372 ;
9'D382 : sin_rom = 60450 ;
9'D383 : sin_rom = 60528 ;
9'D384 : sin_rom = 60605 ;
9'D385 : sin_rom = 60681 ;
9'D386 : sin_rom = 60757 ;
9'D387 : sin_rom = 60832 ;
9'D388 : sin_rom = 60907 ;
9'D389 : sin_rom = 60981 ;
9'D390 : sin_rom = 61054 ;
9'D391 : sin_rom = 61127 ;
9'D392 : sin_rom = 61199 ;
9'D393 : sin_rom = 61271 ;
9'D394 : sin_rom = 61342 ;
9'D395 : sin_rom = 61413 ;
9'D396 : sin_rom = 61483 ;
9'D397 : sin_rom = 61553 ;
9'D398 : sin_rom = 61621 ;
9'D399 : sin_rom = 61690 ;
9'D400 : sin_rom = 61757 ;
9'D401 : sin_rom = 61824 ;
9'D402 : sin_rom = 61891 ;
9'D403 : sin_rom = 61957 ;
9'D404 : sin_rom = 62022 ;
9'D405 : sin_rom = 62087 ;
9'D406 : sin_rom = 62151 ;
9'D407 : sin_rom = 62215 ;
9'D408 : sin_rom = 62278 ;
9'D409 : sin_rom = 62340 ;
9'D410 : sin_rom = 62402 ;
9'D411 : sin_rom = 62463 ;
9'D412 : sin_rom = 62524 ;
9'D413 : sin_rom = 62584 ;
9'D414 : sin_rom = 62644 ;
9'D415 : sin_rom = 62703 ;
9'D416 : sin_rom = 62761 ;
9'D417 : sin_rom = 62819 ;
9'D418 : sin_rom = 62876 ;
9'D419 : sin_rom = 62932 ;
9'D420 : sin_rom = 62988 ;
9'D421 : sin_rom = 63043 ;
9'D422 : sin_rom = 63098 ;
9'D423 : sin_rom = 63152 ;
9'D424 : sin_rom = 63206 ;
9'D425 : sin_rom = 63259 ;
9'D426 : sin_rom = 63311 ;
9'D427 : sin_rom = 63363 ;
9'D428 : sin_rom = 63414 ;
9'D429 : sin_rom = 63465 ;
9'D430 : sin_rom = 63514 ;
9'D431 : sin_rom = 63564 ;
9'D432 : sin_rom = 63613 ;
9'D433 : sin_rom = 63661 ;
9'D434 : sin_rom = 63708 ;
9'D435 : sin_rom = 63755 ;
9'D436 : sin_rom = 63802 ;
9'D437 : sin_rom = 63847 ;
9'D438 : sin_rom = 63892 ;
9'D439 : sin_rom = 63937 ;
9'D440 : sin_rom = 63981 ;
9'D441 : sin_rom = 64024 ;
9'D442 : sin_rom = 64067 ;
9'D443 : sin_rom = 64109 ;
9'D444 : sin_rom = 64150 ;
9'D445 : sin_rom = 64191 ;
9'D446 : sin_rom = 64232 ;
9'D447 : sin_rom = 64271 ;
9'D448 : sin_rom = 64310 ;
9'D449 : sin_rom = 64349 ;
9'D450 : sin_rom = 64387 ;
9'D451 : sin_rom = 64424 ;
9'D452 : sin_rom = 64461 ;
9'D453 : sin_rom = 64497 ;
9'D454 : sin_rom = 64532 ;
9'D455 : sin_rom = 64567 ;
9'D456 : sin_rom = 64601 ;
9'D457 : sin_rom = 64635 ;
9'D458 : sin_rom = 64668 ;
9'D459 : sin_rom = 64700 ;
9'D460 : sin_rom = 64732 ;
9'D461 : sin_rom = 64763 ;
9'D462 : sin_rom = 64793 ;
9'D463 : sin_rom = 64823 ;
9'D464 : sin_rom = 64853 ;
9'D465 : sin_rom = 64881 ;
9'D466 : sin_rom = 64909 ;
9'D467 : sin_rom = 64937 ;
9'D468 : sin_rom = 64964 ;
9'D469 : sin_rom = 64990 ;
9'D470 : sin_rom = 65016 ;
9'D471 : sin_rom = 65041 ;
9'D472 : sin_rom = 65065 ;
9'D473 : sin_rom = 65089 ;
9'D474 : sin_rom = 65112 ;
9'D475 : sin_rom = 65135 ;
9'D476 : sin_rom = 65157 ;
9'D477 : sin_rom = 65178 ;
9'D478 : sin_rom = 65199 ;
9'D479 : sin_rom = 65219 ;
9'D480 : sin_rom = 65238 ;
9'D481 : sin_rom = 65257 ;
9'D482 : sin_rom = 65275 ;
9'D483 : sin_rom = 65293 ;
9'D484 : sin_rom = 65310 ;
9'D485 : sin_rom = 65326 ;
9'D486 : sin_rom = 65342 ;
9'D487 : sin_rom = 65357 ;
9'D488 : sin_rom = 65372 ;
9'D489 : sin_rom = 65386 ;
9'D490 : sin_rom = 65399 ;
9'D491 : sin_rom = 65412 ;
9'D492 : sin_rom = 65424 ;
9'D493 : sin_rom = 65435 ;
9'D494 : sin_rom = 65446 ;
9'D495 : sin_rom = 65456 ;
9'D496 : sin_rom = 65466 ;
9'D497 : sin_rom = 65475 ;
9'D498 : sin_rom = 65483 ;
9'D499 : sin_rom = 65491 ;
9'D500 : sin_rom = 65498 ;
9'D501 : sin_rom = 65505 ;
9'D502 : sin_rom = 65510 ;
9'D503 : sin_rom = 65516 ;
9'D504 : sin_rom = 65520 ;
9'D505 : sin_rom = 65524 ;
9'D506 : sin_rom = 65528 ;
9'D507 : sin_rom = 65531 ;
9'D508 : sin_rom = 65533 ;
9'D509 : sin_rom = 65534 ;
9'D510 : sin_rom = 65535 ;
9'D511 : sin_rom = 65535 ;
default : sin_rom = 0 ;
endcase
end
endfunction
endmodule
|
// bfloat16 (FP16B) multiplier.
module FP16BMulS0Of2(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
output ret_0,
output [7:0] ret_1,
output [7:0] ret_2,
output [8:0] ret_3);
wire s0;
wire s1;
wire [7:0] e0;
wire [7:0] e1;
wire [6:0] f0;
wire [6:0] f1;
wire [7:0] ff0;
wire [7:0] ff1;
wire [15:0] z;
wire [8:0] zz;
assign s0 = arg_0[15:15];
assign s1 = arg_1[15:15];
assign e0 = arg_0[14:7];
assign e1 = arg_1[14:7];
assign f0 = arg_0[6:0];
assign f1 = arg_1[6:0];
// sign
assign ret_0 = s0 ^ s1;
// exponent
assign ret_1 = e0;
assign ret_2 = e1;
assign ff0 = {(e0 == 0 ? 1'b0 : 1'b1), f0};
assign ff1 = {(e1 == 0 ? 1'b0 : 1'b1), f1};
assign z = ff0 * ff1;
assign zz = z[15:7];
// fraction
assign ret_3 = zz;
endmodule // FP16BMulS0Of2
module FP16BMulS1Of2(
input clk,
input rst,
input arg_0,
input [7:0] arg_1,
input [7:0] arg_2,
input [8:0] arg_3,
output [15:0] ret_0);
wire s;
wire c;
wire [6:0] fc;
wire [6:0] uc;
wire [9:0] e10;
wire [7:0] e;
wire underflow;
wire overflow;
wire infinput;
assign s = arg_0;
assign c = arg_3[8:8];
assign e10 = arg_1 + arg_2 - 127 + c;
assign fc = c ? arg_3[7:1] : arg_3[6:0];
assign infinput = (arg_1 == 255) || (arg_2 == 255);
// e10[9:9] negative by subtraction.
// e10[8:8] overflow (> 255) by addition.
assign underflow = e10[9:9];
assign overflow = !underflow && (e10[8:8] || e10[7:0] == 255 || infinput);
assign e = underflow ? 0 : (overflow ? 255 : e10[7:0]);
assign uc = (underflow || e10[7:0] == 0) ? 0 : fc;
assign ret_0 = {s, e, uc};
endmodule // FP16BMulS1Of2
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`include "verilated.v"
module t_case_write2_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
`define FD_BITS 31:0
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : $fwrite (fd, " 0");
7'h01 : $fwrite (fd, " 1");
7'h02 : $fwrite (fd, " 2");
7'h03 : $fwrite (fd, " 3");
7'h04 : $fwrite (fd, " 4");
7'h05 : $fwrite (fd, " 5");
7'h06 : $fwrite (fd, " 6");
7'h07 : $fwrite (fd, " 7");
7'h08 : $fwrite (fd, " 8");
7'h09 : $fwrite (fd, " 9");
7'h0a : $fwrite (fd, " 10");
7'h0b : $fwrite (fd, " 11");
7'h0c : $fwrite (fd, " 12");
7'h0d : $fwrite (fd, " 13");
7'h0e : $fwrite (fd, " 14");
7'h0f : $fwrite (fd, " 15");
7'h10 : $fwrite (fd, " 16");
7'h11 : $fwrite (fd, " 17");
7'h12 : $fwrite (fd, " 18");
7'h13 : $fwrite (fd, " 19");
7'h14 : $fwrite (fd, " 20");
7'h15 : $fwrite (fd, " 21");
7'h16 : $fwrite (fd, " 22");
7'h17 : $fwrite (fd, " 23");
7'h18 : $fwrite (fd, " 24");
7'h19 : $fwrite (fd, " 25");
7'h1a : $fwrite (fd, " 26");
7'h1b : $fwrite (fd, " 27");
7'h1c : $fwrite (fd, " 28");
7'h1d : $fwrite (fd, " 29");
7'h1e : $fwrite (fd, " 30");
7'h1f : $fwrite (fd, " 31");
7'h20 : $fwrite (fd, " 32");
7'h21 : $fwrite (fd, " 33");
7'h22 : $fwrite (fd, " 34");
7'h23 : $fwrite (fd, " 35");
7'h24 : $fwrite (fd, " 36");
7'h25 : $fwrite (fd, " 37");
7'h26 : $fwrite (fd, " 38");
7'h27 : $fwrite (fd, " 39");
7'h28 : $fwrite (fd, " 40");
7'h29 : $fwrite (fd, " 41");
7'h2a : $fwrite (fd, " 42");
7'h2b : $fwrite (fd, " 43");
7'h2c : $fwrite (fd, " 44");
7'h2d : $fwrite (fd, " 45");
7'h2e : $fwrite (fd, " 46");
7'h2f : $fwrite (fd, " 47");
7'h30 : $fwrite (fd, " 48");
7'h31 : $fwrite (fd, " 49");
7'h32 : $fwrite (fd, " 50");
7'h33 : $fwrite (fd, " 51");
7'h34 : $fwrite (fd, " 52");
7'h35 : $fwrite (fd, " 53");
7'h36 : $fwrite (fd, " 54");
7'h37 : $fwrite (fd, " 55");
7'h38 : $fwrite (fd, " 56");
7'h39 : $fwrite (fd, " 57");
7'h3a : $fwrite (fd, " 58");
7'h3b : $fwrite (fd, " 59");
7'h3c : $fwrite (fd, " 60");
7'h3d : $fwrite (fd, " 61");
7'h3e : $fwrite (fd, " 62");
7'h3f : $fwrite (fd, " 63");
7'h40 : $fwrite (fd, " 64");
7'h41 : $fwrite (fd, " 65");
7'h42 : $fwrite (fd, " 66");
7'h43 : $fwrite (fd, " 67");
7'h44 : $fwrite (fd, " 68");
7'h45 : $fwrite (fd, " 69");
7'h46 : $fwrite (fd, " 70");
7'h47 : $fwrite (fd, " 71");
7'h48 : $fwrite (fd, " 72");
7'h49 : $fwrite (fd, " 73");
7'h4a : $fwrite (fd, " 74");
7'h4b : $fwrite (fd, " 75");
7'h4c : $fwrite (fd, " 76");
7'h4d : $fwrite (fd, " 77");
7'h4e : $fwrite (fd, " 78");
7'h4f : $fwrite (fd, " 79");
7'h50 : $fwrite (fd, " 80");
7'h51 : $fwrite (fd, " 81");
7'h52 : $fwrite (fd, " 82");
7'h53 : $fwrite (fd, " 83");
7'h54 : $fwrite (fd, " 84");
7'h55 : $fwrite (fd, " 85");
7'h56 : $fwrite (fd, " 86");
7'h57 : $fwrite (fd, " 87");
7'h58 : $fwrite (fd, " 88");
7'h59 : $fwrite (fd, " 89");
7'h5a : $fwrite (fd, " 90");
7'h5b : $fwrite (fd, " 91");
7'h5c : $fwrite (fd, " 92");
7'h5d : $fwrite (fd, " 93");
7'h5e : $fwrite (fd, " 94");
7'h5f : $fwrite (fd, " 95");
7'h60 : $fwrite (fd, " 96");
7'h61 : $fwrite (fd, " 97");
7'h62 : $fwrite (fd, " 98");
7'h63 : $fwrite (fd, " 99");
7'h64 : $fwrite (fd, " 100");
7'h65 : $fwrite (fd, " 101");
7'h66 : $fwrite (fd, " 102");
7'h67 : $fwrite (fd, " 103");
7'h68 : $fwrite (fd, " 104");
7'h69 : $fwrite (fd, " 105");
7'h6a : $fwrite (fd, " 106");
7'h6b : $fwrite (fd, " 107");
7'h6c : $fwrite (fd, " 108");
7'h6d : $fwrite (fd, " 109");
7'h6e : $fwrite (fd, " 110");
7'h6f : $fwrite (fd, " 111");
7'h70 : $fwrite (fd, " 112");
7'h71 : $fwrite (fd, " 113");
7'h72 : $fwrite (fd, " 114");
7'h73 : $fwrite (fd, " 115");
7'h74 : $fwrite (fd, " 116");
7'h75 : $fwrite (fd, " 117");
7'h76 : $fwrite (fd, " 118");
7'h77 : $fwrite (fd, " 119");
7'h78 : $fwrite (fd, " 120");
7'h79 : $fwrite (fd, " 121");
7'h7a : $fwrite (fd, " 122");
7'h7b : $fwrite (fd, " 123");
7'h7c : $fwrite (fd, " 124");
7'h7d : $fwrite (fd, " 125");
7'h7e : $fwrite (fd, " 126");
7'h7f : $fwrite (fd, " 127");
default:$fwrite (fd, " 128");
endcase
end
endtask
task ozonerb;
input [5:0] rb;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: $fwrite (fd, " 129");
default: ozonerab({1'b1, rb}, fd);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 130");
end
2'h1 :
begin
$fwrite (fd, " 131");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
2'h2 :
begin
skyway({4{im16[15]}}, fd);
skyway({4{im16[15]}}, fd);
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
$fwrite (fd, " 132");
end
2'h3 :
begin
$fwrite (fd, " 133");
skyway(im16[15:12], fd);
skyway(im16[11: 8], fd);
skyway(im16[ 7: 4], fd);
skyway(im16[ 3:0], fd);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (hex)
4'h0 : $fwrite (fd, " 134");
4'h1 : $fwrite (fd, " 135");
4'h2 : $fwrite (fd, " 136");
4'h3 : $fwrite (fd, " 137");
4'h4 : $fwrite (fd, " 138");
4'h5 : $fwrite (fd, " 139");
4'h6 : $fwrite (fd, " 140");
4'h7 : $fwrite (fd, " 141");
4'h8 : $fwrite (fd, " 142");
4'h9 : $fwrite (fd, " 143");
4'ha : $fwrite (fd, " 144");
4'hb : $fwrite (fd, " 145");
4'hc : $fwrite (fd, " 146");
4'hd : $fwrite (fd, " 147");
4'he : $fwrite (fd, " 148");
4'hf : $fwrite (fd, " 149");
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : $fwrite (fd, " 158");
3'h1 : $fwrite (fd, " 159");
3'h2 : $fwrite (fd, " 160");
3'h3 : $fwrite (fd, " 161");
3'h4 : $fwrite (fd, " 162");
3'h5 : $fwrite (fd, " 163");
3'h6 : $fwrite (fd, " 164");
3'h7 : $fwrite (fd, " 165");
endcase
end
endtask
task ozonejk;
input k;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (k)
$fwrite (fd, " 166");
else
$fwrite (fd, " 167");
end
endtask
task ozoneae;
input [ 2:0] ae;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ae)
3'b000 : $fwrite (fd, " 168");
3'b001 : $fwrite (fd, " 169");
3'b010 : $fwrite (fd, " 170");
3'b011 : $fwrite (fd, " 171");
3'b100 : $fwrite (fd, " 172");
3'b101 : $fwrite (fd, " 173");
3'b110 : $fwrite (fd, " 174");
3'b111 : $fwrite (fd, " 175");
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 176");
3'b000 : $fwrite (fd, " 177");
3'b010 : $fwrite (fd, " 178");
3'b100 : $fwrite (fd, " 179");
3'b110 : $fwrite (fd, " 180");
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : $fwrite (fd, " 181");
3'b000 : $fwrite (fd, " 182");
3'b010 : $fwrite (fd, " 183");
3'b100 : $fwrite (fd, " 184");
3'b110 : $fwrite (fd, " 185");
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
$fwrite (fd, " 186");
else
$fwrite (fd, " 187");
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 188");
2'b01 : $fwrite (fd, " 189");
2'b10 : $fwrite (fd, " 190");
2'b11 : $fwrite (fd, " 191");
endcase
4'h2 : $fwrite (fd, " 192");
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 193");
2'b01 : $fwrite (fd, " 194");
2'b10 : $fwrite (fd, " 195");
2'b11 : $fwrite (fd, " 196");
endcase
4'h4 :
if (foo[26])
$fwrite (fd, " 197");
else
$fwrite (fd, " 198");
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 199");
2'b01 : $fwrite (fd, " 200");
2'b10 : $fwrite (fd, " 201");
2'b11 : $fwrite (fd, " 202");
endcase
4'h6 : $fwrite (fd, " 203");
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 204");
2'b01 : $fwrite (fd, " 205");
2'b10 : $fwrite (fd, " 206");
2'b11 : $fwrite (fd, " 207");
endcase
4'h8 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 208");
2'b01 : $fwrite (fd, " 209");
2'b10 : $fwrite (fd, " 210");
2'b11 : $fwrite (fd, " 211");
endcase
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd, " 212");
2'b01 : $fwrite (fd, " 213");
2'b10 : $fwrite (fd, " 214");
2'b11 : $fwrite (fd, " 215");
endcase
4'ha :
if (foo[25])
$fwrite (fd, " 216");
else
$fwrite (fd, " 217");
4'hb :
if (foo[25])
$fwrite (fd, " 218");
else
$fwrite (fd, " 219");
4'hc :
if (foo[26])
$fwrite (fd, " 220");
else
$fwrite (fd, " 221");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd, " 222");
2'b01 : $fwrite (fd, " 223");
2'b10 : $fwrite (fd, " 224");
2'b11 : $fwrite (fd, " 225");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd, " 226");
2'b01 : $fwrite (fd, " 227");
2'b10 : $fwrite (fd, " 228");
2'b11 : $fwrite (fd, " 229");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 230");
2'b01 : $fwrite (fd, " 231");
2'b10 : $fwrite (fd, " 232");
2'b11 : $fwrite (fd, " 233");
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 234");
$fwrite (fd, " 235");
end
7'h01:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 236");
ozoneae(foo[17:15], fd);
$fwrite (fd," 237");
$fwrite (fd, " 238");
end
7'h02:
$fwrite (fd, " 239");
7'h03:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 240");
ozoneae(foo[17:15], fd);
$fwrite (fd," 241");
$fwrite (fd, " 242");
end
7'h04:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 243");
$fwrite (fd," 244");
end
7'h05:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 245");
ozoneae(foo[17:15], fd);
$fwrite (fd," 246");
end
7'h06:
$fwrite (fd, " 247");
7'h07:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 248");
ozoneae(foo[17:15], fd);
$fwrite (fd," 249");
end
7'h08:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 250");
ozoneae(foo[17:15], fd);
$fwrite (fd," 251");
end
7'h09:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 252");
ozoneae(foo[17:15], fd);
$fwrite (fd," 253");
end
7'h0a:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 254");
end
7'h0b:
begin
ozoneae(foo[17:15], fd);
$fwrite (fd," 255");
end
7'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 256");
end
7'h0d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 257");
ozoneae(foo[17:15], fd);
$fwrite (fd," 258");
end
7'h0e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 259");
ozoneae(foo[17:15], fd);
$fwrite (fd," 260");
end
7'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 261");
ozoneae(foo[17:15], fd);
$fwrite (fd," 262");
end
7'h10:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 263");
ozoneae(foo[17:15], fd);
$fwrite (fd," 264");
$fwrite (fd, " 265");
$fwrite (fd, " 266");
end
7'h11:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 267");
ozoneae(foo[17:15], fd);
$fwrite (fd," 268");
$fwrite (fd, " 269");
$fwrite (fd, " 270");
end
7'h12:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 271");
ozoneae(foo[17:15], fd);
$fwrite (fd," 272");
$fwrite (fd, " 273");
$fwrite (fd, " 274");
end
7'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 275");
ozoneae(foo[17:15], fd);
$fwrite (fd," 276");
$fwrite (fd, " 277");
$fwrite (fd, " 278");
end
7'h14:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 279");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 280");
ozoneape(foo[20:18], fd);
$fwrite (fd," 281");
ozoneape(foo[17:15], fd);
$fwrite (fd," 282");
$fwrite (fd, " 283");
$fwrite (fd, " 284");
end
7'h15:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 285");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 286");
ozoneape(foo[20:18], fd);
$fwrite (fd," 287");
ozoneape(foo[17:15], fd);
$fwrite (fd," 288");
$fwrite (fd, " 289");
$fwrite (fd, " 290");
end
7'h16:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 291");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 292");
ozoneape(foo[20:18], fd);
$fwrite (fd," 293");
ozoneape(foo[17:15], fd);
$fwrite (fd," 294");
$fwrite (fd, " 295");
$fwrite (fd, " 296");
end
7'h17:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 297");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 298");
ozoneape(foo[20:18], fd);
$fwrite (fd," 299");
ozoneape(foo[17:15], fd);
$fwrite (fd," 300");
$fwrite (fd, " 301");
$fwrite (fd, " 302");
end
7'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 303");
ozoneae(foo[17:15], fd);
$fwrite (fd," 304");
$fwrite (fd, " 305");
$fwrite (fd, " 306");
end
7'h19:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 307");
ozoneae(foo[17:15], fd);
$fwrite (fd," 308");
$fwrite (fd, " 309");
$fwrite (fd, " 310");
end
7'h1a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 311");
ozoneae(foo[17:15], fd);
$fwrite (fd," 312");
$fwrite (fd, " 313");
$fwrite (fd, " 314");
end
7'h1b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 315");
ozoneae(foo[17:15], fd);
$fwrite (fd," 316");
$fwrite (fd, " 317");
$fwrite (fd, " 318");
end
7'h1c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 319");
ozoneae(foo[17:15], fd);
$fwrite (fd," 320");
$fwrite (fd, " 321");
$fwrite (fd, " 322");
end
7'h1d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 323");
ozoneae(foo[17:15], fd);
$fwrite (fd," 324");
$fwrite (fd, " 325");
$fwrite (fd, " 326");
end
7'h1e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 327");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 328");
ozoneape(foo[20:18], fd);
$fwrite (fd," 329");
ozoneape(foo[17:15], fd);
$fwrite (fd," 330");
$fwrite (fd, " 331");
$fwrite (fd, " 332");
end
7'h1f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 333");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 334");
ozoneape(foo[20:18], fd);
$fwrite (fd," 335");
ozoneape(foo[17:15], fd);
$fwrite (fd," 336");
$fwrite (fd, " 337");
$fwrite (fd, " 338");
end
7'h20:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 339");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 340");
ozoneape(foo[20:18], fd);
$fwrite (fd," 341");
ozoneape(foo[17:15], fd);
$fwrite (fd," 342");
$fwrite (fd, " 343");
$fwrite (fd, " 344");
end
7'h21:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 345");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 346");
ozoneape(foo[20:18], fd);
$fwrite (fd," 347");
ozoneape(foo[17:15], fd);
$fwrite (fd," 348");
$fwrite (fd, " 349");
$fwrite (fd, " 350");
end
7'h22:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 351");
ozoneae(foo[17:15], fd);
$fwrite (fd," 352");
$fwrite (fd, " 353");
$fwrite (fd, " 354");
end
7'h23:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 355");
ozoneae(foo[17:15], fd);
$fwrite (fd," 356");
$fwrite (fd, " 357");
$fwrite (fd, " 358");
end
7'h24:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 359");
ozoneae(foo[17:15], fd);
$fwrite (fd," 360");
$fwrite (fd, " 361");
$fwrite (fd, " 362");
end
7'h25:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 363");
ozoneae(foo[17:15], fd);
$fwrite (fd," 364");
$fwrite (fd, " 365");
$fwrite (fd, " 366");
end
7'h26:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 367");
ozoneae(foo[17:15], fd);
$fwrite (fd," 368");
$fwrite (fd, " 369");
$fwrite (fd, " 370");
end
7'h27:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 371");
ozoneae(foo[17:15], fd);
$fwrite (fd," 372");
$fwrite (fd, " 373");
$fwrite (fd, " 374");
end
7'h28:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 375");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 376");
ozoneape(foo[20:18], fd);
$fwrite (fd," 377");
ozoneape(foo[17:15], fd);
$fwrite (fd," 378");
$fwrite (fd, " 379");
$fwrite (fd, " 380");
end
7'h29:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 381");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 382");
ozoneape(foo[20:18], fd);
$fwrite (fd," 383");
ozoneape(foo[17:15], fd);
$fwrite (fd," 384");
$fwrite (fd, " 385");
$fwrite (fd, " 386");
end
7'h2a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 387");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 388");
ozoneape(foo[20:18], fd);
$fwrite (fd," 389");
ozoneape(foo[17:15], fd);
$fwrite (fd," 390");
$fwrite (fd, " 391");
$fwrite (fd, " 392");
end
7'h2b:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 393");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 394");
ozoneape(foo[20:18], fd);
$fwrite (fd," 395");
ozoneape(foo[17:15], fd);
$fwrite (fd," 396");
$fwrite (fd, " 397");
$fwrite (fd, " 398");
end
7'h2c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 399");
ozoneae(foo[17:15], fd);
$fwrite (fd," 400");
$fwrite (fd, " 401");
$fwrite (fd, " 402");
end
7'h2d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 403");
ozoneae(foo[17:15], fd);
$fwrite (fd," 404");
$fwrite (fd, " 405");
$fwrite (fd, " 406");
end
7'h2e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 407");
ozoneae(foo[17:15], fd);
$fwrite (fd," 408");
$fwrite (fd, " 409");
$fwrite (fd, " 410");
end
7'h2f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 411");
ozoneae(foo[17:15], fd);
$fwrite (fd," 412");
$fwrite (fd, " 413");
$fwrite (fd, " 414");
end
7'h30:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 415");
ozoneae(foo[17:15], fd);
$fwrite (fd," 416");
$fwrite (fd, " 417");
$fwrite (fd, " 418");
end
7'h31:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 419");
ozoneae(foo[17:15], fd);
$fwrite (fd," 420");
$fwrite (fd, " 421");
$fwrite (fd, " 422");
end
7'h32:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 423");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 424");
ozoneape(foo[20:18], fd);
$fwrite (fd," 425");
ozoneape(foo[17:15], fd);
$fwrite (fd," 426");
$fwrite (fd, " 427");
$fwrite (fd, " 428");
end
7'h33:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 429");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 430");
ozoneape(foo[20:18], fd);
$fwrite (fd," 431");
ozoneape(foo[17:15], fd);
$fwrite (fd," 432");
$fwrite (fd, " 433");
$fwrite (fd, " 434");
end
7'h34:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 435");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 436");
ozoneape(foo[20:18], fd);
$fwrite (fd," 437");
ozoneape(foo[17:15], fd);
$fwrite (fd," 438");
$fwrite (fd, " 439");
$fwrite (fd, " 440");
end
7'h35:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 441");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 442");
ozoneape(foo[20:18], fd);
$fwrite (fd," 443");
ozoneape(foo[17:15], fd);
$fwrite (fd," 444");
$fwrite (fd, " 445");
$fwrite (fd, " 446");
end
7'h36:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 447");
ozoneae(foo[17:15], fd);
$fwrite (fd," 448");
$fwrite (fd, " 449");
$fwrite (fd, " 450");
end
7'h37:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 451");
ozoneae(foo[17:15], fd);
$fwrite (fd," 452");
$fwrite (fd, " 453");
$fwrite (fd, " 454");
end
7'h38:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 455");
ozoneae(foo[17:15], fd);
$fwrite (fd," 456");
$fwrite (fd, " 457");
end
7'h39:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 458");
ozoneae(foo[17:15], fd);
$fwrite (fd," 459");
$fwrite (fd, " 460");
end
7'h3a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 461");
ozoneae(foo[17:15], fd);
$fwrite (fd," 462");
$fwrite (fd, " 463");
end
7'h3b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 464");
ozoneae(foo[17:15], fd);
$fwrite (fd," 465");
$fwrite (fd, " 466");
end
7'h3c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 467");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 468");
ozoneape(foo[20:18], fd);
$fwrite (fd," 469");
ozoneape(foo[17:15], fd);
$fwrite (fd," 470");
$fwrite (fd, " 471");
end
7'h3d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 472");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 473");
ozoneape(foo[20:18], fd);
$fwrite (fd," 474");
ozoneape(foo[17:15], fd);
$fwrite (fd," 475");
$fwrite (fd, " 476");
end
7'h3e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 477");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 478");
ozoneape(foo[20:18], fd);
$fwrite (fd," 479");
ozoneape(foo[17:15], fd);
$fwrite (fd," 480");
$fwrite (fd, " 481");
end
7'h3f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 482");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 483");
ozoneape(foo[20:18], fd);
$fwrite (fd," 484");
ozoneape(foo[17:15], fd);
$fwrite (fd," 485");
$fwrite (fd, " 486");
end
7'h40:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 487");
ozoneae(foo[17:15], fd);
$fwrite (fd," 488");
$fwrite (fd, " 489");
$fwrite (fd, " 490");
end
7'h41:
begin
$fwrite (fd, " 491");
$fwrite (fd, " 492");
end
7'h42:
begin
$fwrite (fd, " 493");
$fwrite (fd, " 494");
end
7'h43:
begin
$fwrite (fd, " 495");
$fwrite (fd, " 496");
end
7'h44:
begin
$fwrite (fd, " 497");
$fwrite (fd, " 498");
end
7'h45:
$fwrite (fd, " 499");
7'h46:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 500");
$fwrite (fd, " 501");
$fwrite (fd, " 502");
end
7'h47:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 503");
ozoneae(foo[17:15], fd);
$fwrite (fd," 504");
ozoneape(foo[20:18], fd);
$fwrite (fd," 505");
ozoneape(foo[20:18], fd);
$fwrite (fd," 506");
$fwrite (fd, " 507");
$fwrite (fd, " 508");
end
7'h48:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 509");
ozoneape(foo[20:18], fd);
$fwrite (fd," 510");
ozoneape(foo[20:18], fd);
$fwrite (fd," 511");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 512");
ozoneape(foo[17:15], fd);
$fwrite (fd," 513");
end
7'h49:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 514");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 515");
ozoneape(foo[17:15], fd);
$fwrite (fd," 516");
end
7'h4a:
$fwrite (fd," 517");
7'h4b:
$fwrite (fd, " 518");
7'h4c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 519");
$fwrite (fd, " 520");
$fwrite (fd, " 521");
end
7'h4d:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 522");
ozoneae(foo[17:15], fd);
$fwrite (fd," 523");
ozoneape(foo[20:18], fd);
$fwrite (fd," 524");
ozoneape(foo[20:18], fd);
$fwrite (fd," 525");
$fwrite (fd, " 526");
$fwrite (fd, " 527");
end
7'h4e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 528");
ozoneae(foo[17:15], fd);
$fwrite (fd," 529");
ozoneape(foo[20:18], fd);
$fwrite (fd," 530");
ozoneape(foo[20:18], fd);
$fwrite (fd," 531");
end
7'h4f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 532");
end
7'h50:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 533");
ozoneae(foo[17:15], fd);
$fwrite (fd," 534");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 535");
ozoneae(foo[17:15], fd);
$fwrite (fd," 536");
ozoneape(foo[20:18], fd);
$fwrite (fd," 537");
ozoneae(foo[17:15], fd);
$fwrite (fd," 538");
ozoneape(foo[20:18], fd);
$fwrite (fd," 539");
ozoneae(foo[17:15], fd);
$fwrite (fd," 540");
end
7'h51:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 541");
ozoneape(foo[20:18], fd);
$fwrite (fd," 542");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 543");
ozoneape(foo[20:18], fd);
$fwrite (fd," 544");
ozoneae(foo[17:15], fd);
$fwrite (fd," 545");
end
7'h52:
$fwrite (fd, " 546");
7'h53:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 547");
end
7'h54:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 548");
ozoneae(foo[17:15], fd);
$fwrite (fd," 549");
end
7'h55:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 550");
ozoneae(foo[17:15], fd);
$fwrite (fd," 551");
end
7'h56:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 552");
ozoneae(foo[17:15], fd);
$fwrite (fd," 553");
$fwrite (fd, " 554");
end
7'h57:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 555");
ozoneae(foo[17:15], fd);
$fwrite (fd," 556");
ozoneape(foo[20:18], fd);
$fwrite (fd," 557");
ozoneape(foo[20:18], fd);
$fwrite (fd," 558");
end
7'h58:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 559");
end
7'h59:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 560");
ozoneae(foo[17:15], fd);
$fwrite (fd," 561");
ozoneape(foo[20:18], fd);
$fwrite (fd," 562");
ozoneape(foo[20:18], fd);
$fwrite (fd," 563");
end
7'h5a:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 564");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 565");
end
7'h5b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 566");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 567");
end
7'h5c:
begin
$fwrite (fd," 568");
ozoneape(foo[17:15], fd);
$fwrite (fd," 569");
$fwrite (fd," 570");
ozoneape(foo[17:15], fd);
$fwrite (fd," 571");
ozoneae(foo[20:18], fd);
$fwrite (fd," 572");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 573");
end
7'h5d:
begin
$fwrite (fd," 574");
ozoneape(foo[17:15], fd);
$fwrite (fd," 575");
$fwrite (fd," 576");
ozoneape(foo[17:15], fd);
$fwrite (fd," 577");
ozoneae(foo[20:18], fd);
$fwrite (fd," 578");
ozoneaee(foo[17:15], fd);
$fwrite (fd, " 579");
end
7'h5e:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 580");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 581");
end
7'h5f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 582");
ozoneae(foo[17:15], fd);
$fwrite (fd," 583");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 584");
ozoneae(foo[17:15], fd);
$fwrite (fd," 585");
ozoneape(foo[20:18], fd);
$fwrite (fd," 586");
ozoneae(foo[17:15], fd);
$fwrite (fd," 587");
ozoneape(foo[20:18], fd);
$fwrite (fd," 588");
ozoneae(foo[17:15], fd);
$fwrite (fd," 589");
end
7'h60:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 590");
ozoneae(foo[17:15], fd);
$fwrite (fd," 591");
end
7'h61:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 592");
ozoneae(foo[17:15], fd);
$fwrite (fd," 593");
end
7'h62:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 594");
ozoneae(foo[17:15], fd);
$fwrite (fd," 595");
end
7'h63:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 596");
ozoneae(foo[17:15], fd);
$fwrite (fd," 597");
end
7'h64:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 598");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 599");
ozoneape(foo[20:18], fd);
$fwrite (fd," 600");
ozoneape(foo[17:15], fd);
$fwrite (fd," 601");
end
7'h65:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 602");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 603");
ozoneape(foo[20:18], fd);
$fwrite (fd," 604");
ozoneape(foo[17:15], fd);
$fwrite (fd," 605");
end
7'h66:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 606");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 607");
ozoneape(foo[20:18], fd);
$fwrite (fd," 608");
ozoneape(foo[17:15], fd);
$fwrite (fd," 609");
end
7'h67:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 610");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 611");
ozoneape(foo[20:18], fd);
$fwrite (fd," 612");
ozoneape(foo[17:15], fd);
$fwrite (fd," 613");
end
7'h68:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 614");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 615");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 616");
ozoneape(foo[20:18], fd);
$fwrite (fd," 617");
ozoneape(foo[20:18], fd);
$fwrite (fd," 618");
ozoneape(foo[17:15], fd);
end
7'h69:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 619");
ozoneae(foo[17:15], fd);
$fwrite (fd," 620");
ozoneae(foo[20:18], fd);
$fwrite (fd," 621");
end
7'h6a:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 622");
ozoneae(foo[17:15], fd);
$fwrite (fd," 623");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 624");
ozoneape(foo[20:18], fd);
$fwrite (fd," 625");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 626");
ozoneae(foo[17:15], fd);
end
7'h6b:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 627");
ozoneae(foo[17:15], fd);
$fwrite (fd," 628");
ozoneae(foo[20:18], fd);
$fwrite (fd," 629");
end
7'h6c:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 630");
ozoneae(foo[17:15], fd);
$fwrite (fd," 631");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 632");
ozoneape(foo[20:18], fd);
$fwrite (fd," 633");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 634");
ozoneae(foo[17:15], fd);
end
7'h6d:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 635");
ozoneae(foo[17:15], fd);
$fwrite (fd," 636");
ozoneae(foo[20:18], fd);
$fwrite (fd," 637");
end
7'h6e:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 638");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 639");
ozoneape(foo[20:18], fd);
$fwrite (fd," 640");
ozoneape(foo[17:15], fd);
$fwrite (fd," 641");
end
7'h6f:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 642");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 643");
ozoneape(foo[20:18], fd);
$fwrite (fd," 644");
ozoneape(foo[17:15], fd);
$fwrite (fd," 645");
end
7'h70:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 646");
ozoneae(foo[20:18], fd);
$fwrite (fd," 647");
ozoneae(foo[17:15], fd);
$fwrite (fd," 648");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 649");
end
7'h71:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 650");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 651");
end
7'h72:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 652");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 653");
end
7'h73:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 654");
ozoneae(foo[20:18], fd);
$fwrite (fd," 655");
ozoneae(foo[17:15], fd);
end
7'h74:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 656");
ozoneae(foo[20:18], fd);
$fwrite (fd," 657");
ozoneae(foo[17:15], fd);
end
7'h75:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 658");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 659");
ozoneape(foo[20:18], fd);
$fwrite (fd," 660");
ozoneape(foo[17:15], fd);
$fwrite (fd," 661");
$fwrite (fd, " 662");
$fwrite (fd, " 663");
end
7'h76:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 664");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 665");
ozoneaee(foo[20:18], fd);
$fwrite (fd," 666");
ozoneape(foo[20:18], fd);
$fwrite (fd," 667");
ozoneape(foo[17:15], fd);
$fwrite (fd," 668");
ozoneape(foo[20:18], fd);
$fwrite (fd," 669");
end
7'h77:
begin
ozoneaee(foo[20:18], fd);
$fwrite (fd," 670");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 671");
ozoneaee(foo[17:15], fd);
$fwrite (fd," 672");
ozoneape(foo[20:18], fd);
$fwrite (fd," 673");
ozoneape(foo[17:15], fd);
$fwrite (fd," 674");
ozoneape(foo[17:15], fd);
$fwrite (fd," 675");
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
$fwrite (fd," 676");
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : $fwrite (fd," 677");
2'b01 : $fwrite (fd," 678");
2'b10 : $fwrite (fd," 679");
2'b11 : $fwrite (fd," 680");
endcase
4'h1 :
case (foo[26:25])
2'b00 : $fwrite (fd," 681");
2'b01 : $fwrite (fd," 682");
2'b10 : $fwrite (fd," 683");
2'b11 : $fwrite (fd," 684");
endcase
4'h2 :
case (foo[26:25])
2'b00 : $fwrite (fd," 685");
2'b01 : $fwrite (fd," 686");
2'b10 : $fwrite (fd," 687");
2'b11 : $fwrite (fd," 688");
endcase
4'h3 :
case (foo[26:25])
2'b00 : $fwrite (fd," 689");
2'b01 : $fwrite (fd," 690");
2'b10 : $fwrite (fd," 691");
2'b11 : $fwrite (fd," 692");
endcase
4'h4 :
case (foo[26:25])
2'b00 : $fwrite (fd," 693");
2'b01 : $fwrite (fd," 694");
2'b10 : $fwrite (fd," 695");
2'b11 : $fwrite (fd," 696");
endcase
4'h5 :
case (foo[26:25])
2'b00 : $fwrite (fd," 697");
2'b01 : $fwrite (fd," 698");
2'b10 : $fwrite (fd," 699");
2'b11 : $fwrite (fd," 700");
endcase
4'h6 :
case (foo[26:25])
2'b00 : $fwrite (fd," 701");
2'b01 : $fwrite (fd," 702");
2'b10 : $fwrite (fd," 703");
2'b11 : $fwrite (fd," 704");
endcase
4'h7 :
case (foo[26:25])
2'b00 : $fwrite (fd," 705");
2'b01 : $fwrite (fd," 706");
2'b10 : $fwrite (fd," 707");
2'b11 : $fwrite (fd," 708");
endcase
4'h8 :
if (foo[26])
$fwrite (fd," 709");
else
$fwrite (fd," 710");
4'h9 :
case (foo[26:25])
2'b00 : $fwrite (fd," 711");
2'b01 : $fwrite (fd," 712");
2'b10 : $fwrite (fd," 713");
2'b11 : $fwrite (fd," 714");
endcase
4'ha :
case (foo[26:25])
2'b00 : $fwrite (fd," 715");
2'b01 : $fwrite (fd," 716");
2'b10 : $fwrite (fd," 717");
2'b11 : $fwrite (fd," 718");
endcase
4'hb :
case (foo[26:25])
2'b00 : $fwrite (fd," 719");
2'b01 : $fwrite (fd," 720");
2'b10 : $fwrite (fd," 721");
2'b11 : $fwrite (fd," 722");
endcase
4'hc :
if (foo[26])
$fwrite (fd," 723");
else
$fwrite (fd," 724");
4'hd :
case (foo[26:25])
2'b00 : $fwrite (fd," 725");
2'b01 : $fwrite (fd," 726");
2'b10 : $fwrite (fd," 727");
2'b11 : $fwrite (fd," 728");
endcase
4'he :
case (foo[26:25])
2'b00 : $fwrite (fd," 729");
2'b01 : $fwrite (fd," 730");
2'b10 : $fwrite (fd," 731");
2'b11 : $fwrite (fd," 732");
endcase
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd," 733");
2'b01 : $fwrite (fd," 734");
2'b10 : $fwrite (fd," 735");
2'b11 : $fwrite (fd," 736");
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 737");
ozoneae(foo[17:15], fd);
$fwrite (fd," 738");
end
5'h01 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 739");
ozoneae(foo[17:15], fd);
$fwrite (fd," 740");
end
5'h02 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 741");
ozoneae(foo[17:15], fd);
$fwrite (fd," 742");
end
5'h03 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 743");
ozoneae(foo[17:15], fd);
$fwrite (fd," 744");
end
5'h04 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 745");
ozoneae(foo[17:15], fd);
$fwrite (fd," 746");
end
5'h05 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 747");
ozoneae(foo[17:15], fd);
$fwrite (fd," 748");
end
5'h06 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 749");
ozoneae(foo[17:15], fd);
$fwrite (fd," 750");
end
5'h07 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 751");
ozoneae(foo[17:15], fd);
$fwrite (fd," 752");
end
5'h08 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 753");
if (foo[ 6])
$fwrite (fd," 754");
else
$fwrite (fd," 755");
end
5'h09 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 756");
ozoneae(foo[17:15], fd);
$fwrite (fd," 757");
end
5'h0a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 758");
ozoneae(foo[17:15], fd);
end
5'h0b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 759");
ozoneae(foo[17:15], fd);
$fwrite (fd," 760");
end
5'h0c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 761");
end
5'h0d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 762");
ozoneae(foo[17:15], fd);
$fwrite (fd," 763");
end
5'h0e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 764");
ozoneae(foo[17:15], fd);
end
5'h0f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 765");
ozoneae(foo[17:15], fd);
end
5'h10 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 766");
ozoneae(foo[17:15], fd);
$fwrite (fd," 767");
end
5'h11 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 768");
ozoneae(foo[17:15], fd);
$fwrite (fd," 769");
end
5'h18 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 770");
if (foo[ 6])
$fwrite (fd," 771");
else
$fwrite (fd," 772");
end
5'h1a :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 773");
ozoneae(foo[17:15], fd);
$fwrite (fd," 774");
end
5'h1b :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 775");
ozoneae(foo[17:15], fd);
$fwrite (fd," 776");
if (foo[ 6])
$fwrite (fd," 777");
else
$fwrite (fd," 778");
$fwrite (fd," 779");
end
5'h1c :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 780");
end
5'h1d :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 781");
if (foo[ 6])
$fwrite (fd," 782");
else
$fwrite (fd," 783");
$fwrite (fd," 784");
end
5'h1e :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 785");
if (foo[ 6])
$fwrite (fd," 786");
else
$fwrite (fd," 787");
$fwrite (fd," 788");
end
5'h1f :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 789");
ozoneae(foo[17:15], fd);
$fwrite (fd," 790");
if (foo[ 6])
$fwrite (fd," 791");
else
$fwrite (fd," 792");
$fwrite (fd," 793");
end
default :
$fwrite (fd," 794");
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], fd);
case (foo[22:21])
2'h0: $fwrite (fd," 795");
2'h1: $fwrite (fd," 796");
2'h2: $fwrite (fd," 797");
endcase
ozoneae(foo[17:15], fd);
$fwrite (fd," 798");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 799");
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 800");
ozoneae(foo[17:15], fd);
case (foo[23:21])
3'h0: $fwrite (fd," 801");
3'h1: $fwrite (fd," 802");
3'h5: $fwrite (fd," 803");
3'h6: $fwrite (fd," 804");
3'h7: $fwrite (fd," 805");
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], fd);
if (foo[21])
$fwrite (fd," 806");
else
$fwrite (fd," 807");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
end
5'h0c:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 808");
if (foo[ 9])
ozoneae(foo[ 8: 6], fd);
else
ozonef3e_te(foo[ 8: 6], fd);
$fwrite (fd," 809");
ozoneae(foo[17:15], fd);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 810");
ozoneae(foo[17:15], fd);
case (foo[22:21])
2'h0,
2'h2:
$fwrite (fd," 811");
2'h1,
2'h3:
$fwrite (fd," 812");
endcase
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 813");
ozoneae((foo[20:18]+1), fd);
$fwrite (fd," 814");
ozoneae((foo[17:15]+1), fd);
case (foo[22:21])
2'h0,
2'h3:
$fwrite (fd," 815");
2'h1,
2'h2:
$fwrite (fd," 816");
endcase
ozoneae((foo[ 8: 6]+1), fd);
end
5'h18:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd," 817");
ozoneae(foo[17:15], fd);
$fwrite (fd," 818");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd," 819");
ozoneae(foo[20:18], fd);
$fwrite (fd," 820");
ozoneae(foo[17:15], fd);
$fwrite (fd," 821");
ozoneae(foo[ 8: 6], fd);
end
default :
$fwrite (fd," 822");
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (te)
3'b100 : $fwrite (fd, " 823");
3'b101 : $fwrite (fd, " 824");
3'b110 : $fwrite (fd, " 825");
default: $fwrite (fd, " 826");
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ate)
3'b000 : $fwrite (fd, " 827");
3'b001 : $fwrite (fd, " 828");
3'b010 : $fwrite (fd, " 829");
3'b011 : $fwrite (fd, " 830");
3'b100 : $fwrite (fd, " 831");
3'b101 : $fwrite (fd, " 832");
3'b110 : $fwrite (fd, " 833");
3'b111 : $fwrite (fd, " 834");
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
$fwrite (fd, " 835");
5'h01,
5'h05 :
$fwrite (fd, " 836");
5'h02,
5'h06 :
$fwrite (fd, " 837");
5'h03,
5'h07 :
$fwrite (fd, " 838");
5'h08,
5'h18 :
$fwrite (fd, " 839");
5'h09,
5'h19 :
$fwrite (fd, " 840");
5'h0a,
5'h1a :
$fwrite (fd, " 841");
5'h0b :
$fwrite (fd, " 842");
5'h1b :
$fwrite (fd, " 843");
5'h0c,
5'h1c :
$fwrite (fd, " 844");
5'h0d,
5'h1d :
$fwrite (fd, " 845");
5'h1e :
$fwrite (fd, " 846");
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
input [`FD_BITS] fd;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : $fwrite (fd, " 847");
2'b01 : $fwrite (fd, " 848");
2'b10 : $fwrite (fd, " 849");
2'b11 : $fwrite (fd, " 850");
endcase
4'h1:
case (foo[26:25])
2'b00 : $fwrite (fd, " 851");
2'b01 : $fwrite (fd, " 852");
2'b10 : $fwrite (fd, " 853");
2'b11 : $fwrite (fd, " 854");
endcase
4'h2:
case (foo[26:25])
2'b00 : $fwrite (fd, " 855");
2'b01 : $fwrite (fd, " 856");
2'b10 : $fwrite (fd, " 857");
2'b11 : $fwrite (fd, " 858");
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : $fwrite (fd, " 859");
2'b01 : $fwrite (fd, " 860");
2'b10 : $fwrite (fd, " 861");
2'b11 : $fwrite (fd, " 862");
endcase
4'ha,
4'hb :
if (foo[25])
$fwrite (fd, " 863");
else
$fwrite (fd, " 864");
4'hc :
if (foo[26])
$fwrite (fd, " 865");
else
$fwrite (fd, " 866");
default :
begin
$fwrite (fd, " 867");
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
$fwrite (fd, " 868");
4'h9 :
$fwrite (fd, " 869");
4'ha,
4'he :
$fwrite (fd, " 870");
4'hb,
4'hf :
$fwrite (fd, " 871");
4'hd :
$fwrite (fd, " 872");
endcase
if (foo[20])
case (foo[18:16])
3'b000 : $fwrite (fd, " 873");
3'b100 : $fwrite (fd, " 874");
default: $fwrite (fd, " 875");
endcase
else
ozoneae(foo[18:16], fd);
if (foo[24:21] === 4'hc)
if (foo[25])
$fwrite (fd, " 876");
else
$fwrite (fd, " 877");
case (foo[24:21])
4'h0,
4'h1,
4'h2:
$fwrite (fd, " 878");
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : $fwrite (fd, " 879");
2'h1 : $fwrite (fd, " 880");
2'h2 : $fwrite (fd, " 881");
2'h3 : $fwrite (fd, " 882");
endcase
case (foo[17:16])
2'h1 : $fwrite (fd, " 883");
2'h2 : $fwrite (fd, " 884");
2'h3 : $fwrite (fd, " 885");
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rme)
3'h0 : $fwrite (fd, " 886");
3'h1 : $fwrite (fd, " 887");
3'h2 : $fwrite (fd, " 888");
3'h3 : $fwrite (fd, " 889");
3'h4 : $fwrite (fd, " 890");
3'h5 : $fwrite (fd, " 891");
3'h6 : $fwrite (fd, " 892");
3'h7 : $fwrite (fd, " 893");
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 894");
ozonerme(ye[5:3], fd);
case ({ye[ 2:0], l})
4'h2,
4'ha: $fwrite (fd, " 895");
4'h4,
4'hb: $fwrite (fd, " 896");
4'h6,
4'he: $fwrite (fd, " 897");
4'h8,
4'hc: $fwrite (fd, " 898");
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
$fwrite (fd, " 899");
ozonerme(ye[5:3], fd);
ozonef1e_inc_dec(ye[5:0], l , fd);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
$fwrite (fd, " 900");
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: $fwrite (fd, " 901");
4'h4,
4'h5,
4'hb: $fwrite (fd, " 902");
4'h6,
4'h7,
4'he: $fwrite (fd, " 903");
4'h8,
4'h9,
4'hc: $fwrite (fd, " 904");
4'hf: $fwrite (fd, " 905");
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: $fwrite (fd, " 906");
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: $fwrite (fd, " 907");
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : $fwrite (fd, " 908");
1'b1 : $fwrite (fd, " 909");
endcase
case (xe[ 2:0])
3'h1,
3'h5: $fwrite (fd, " 910");
3'h2,
3'h6: $fwrite (fd, " 911");
3'h3,
3'h7: $fwrite (fd, " 912");
3'h4: $fwrite (fd, " 913");
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (rp)
3'h0 : $fwrite (fd, " 914");
3'h1 : $fwrite (fd, " 915");
3'h2 : $fwrite (fd, " 916");
3'h3 : $fwrite (fd, " 917");
3'h4 : $fwrite (fd, " 918");
3'h5 : $fwrite (fd, " 919");
3'h6 : $fwrite (fd, " 920");
3'h7 : $fwrite (fd, " 921");
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (ry)
4'h0 : $fwrite (fd, " 922");
4'h1 : $fwrite (fd, " 923");
4'h2 : $fwrite (fd, " 924");
4'h3 : $fwrite (fd, " 925");
4'h4 : $fwrite (fd, " 926");
4'h5 : $fwrite (fd, " 927");
4'h6 : $fwrite (fd, " 928");
4'h7 : $fwrite (fd, " 929");
4'h8 : $fwrite (fd, " 930");
4'h9 : $fwrite (fd, " 931");
4'ha : $fwrite (fd, " 932");
4'hb : $fwrite (fd, " 933");
4'hc : $fwrite (fd, " 934");
4'hd : $fwrite (fd, " 935");
4'he : $fwrite (fd, " 936");
4'hf : $fwrite (fd, " 937");
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : $fwrite (fd, " 938");
2'h1 : $fwrite (fd, " 939");
2'h2 : $fwrite (fd, " 940");
2'h3 : $fwrite (fd, " 941");
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: $fwrite (fd, " 942");
5'b001??: $fwrite (fd, " 943");
5'b?10??: $fwrite (fd, " 944");
5'b0110?: $fwrite (fd, " 945");
5'b01110: $fwrite (fd, " 946");
5'b01111: $fwrite (fd, " 947");
5'b10???: $fwrite (fd, " 948");
5'b11100: $fwrite (fd, " 949");
5'b11101: $fwrite (fd, " 950");
5'b11110: $fwrite (fd, " 951");
5'b11111: $fwrite (fd, " 952");
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (con)
5'h00 : $fwrite (fd, " 953");
5'h01 : $fwrite (fd, " 954");
5'h02 : $fwrite (fd, " 955");
5'h03 : $fwrite (fd, " 956");
5'h04 : $fwrite (fd, " 957");
5'h05 : $fwrite (fd, " 958");
5'h06 : $fwrite (fd, " 959");
5'h07 : $fwrite (fd, " 960");
5'h08 : $fwrite (fd, " 961");
5'h09 : $fwrite (fd, " 962");
5'h0a : $fwrite (fd, " 963");
5'h0b : $fwrite (fd, " 964");
5'h0c : $fwrite (fd, " 965");
5'h0d : $fwrite (fd, " 966");
5'h0e : $fwrite (fd, " 967");
5'h0f : $fwrite (fd, " 968");
5'h10 : $fwrite (fd, " 969");
5'h11 : $fwrite (fd, " 970");
5'h12 : $fwrite (fd, " 971");
5'h13 : $fwrite (fd, " 972");
5'h14 : $fwrite (fd, " 973");
5'h15 : $fwrite (fd, " 974");
5'h16 : $fwrite (fd, " 975");
5'h17 : $fwrite (fd, " 976");
5'h18 : $fwrite (fd, " 977");
5'h19 : $fwrite (fd, " 978");
5'h1a : $fwrite (fd, " 979");
5'h1b : $fwrite (fd, " 980");
5'h1c : $fwrite (fd, " 981");
5'h1d : $fwrite (fd, " 982");
5'h1e : $fwrite (fd, " 983");
5'h1f : $fwrite (fd, " 984");
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : $fwrite (fd, " 985");
4'h1 : $fwrite (fd, " 986");
4'h2 : $fwrite (fd, " 987");
4'h3 : $fwrite (fd, " 988");
4'h4 : $fwrite (fd, " 989");
4'h5 : $fwrite (fd, " 990");
4'h6 : $fwrite (fd, " 991");
4'h7 : $fwrite (fd, " 992");
4'h8 : $fwrite (fd, " 993");
4'h9 : $fwrite (fd, " 994");
4'ha : $fwrite (fd, " 995");
4'hb : $fwrite (fd, " 996");
4'hc : $fwrite (fd, " 997");
4'hd : $fwrite (fd, " 998");
4'he : $fwrite (fd, " 999");
4'hf : $fwrite (fd, " 1000");
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : $fwrite (fd, " 1001");
2'h1 : $fwrite (fd, " 1002");
2'h2 : $fwrite (fd, " 1003");
2'h3 : $fwrite (fd, " 1004");
endcase
end
endtask
task ozoneacc;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1005");
2'h1 : $fwrite (fd, " 1006");
endcase
end
endtask
task ozonehl;
input foo;
input [`FD_BITS] fd;
// verilator no_inline_task
begin
case (foo)
2'h0 : $fwrite (fd, " 1007");
2'h1 : $fwrite (fd, " 1008");
endcase
end
endtask
task dude;
input [`FD_BITS] fd;
// verilator no_inline_task
$fwrite(fd," dude");
endtask
task big_case;
input [ `FD_BITS] fd;
input [ 31:0] foo;
// verilator no_inline_task
begin
$fwrite(fd," 1009");
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1011");
ozoneacc(~foo[26], fd);
ozonehl(foo[20], fd);
$fwrite (fd, " 1012");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1013");
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1014");
ozonerx(foo, fd);
$fwrite (fd, " 1015");
$fwrite (fd, " 1016:%x", foo[20]);
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1017");
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1018");
ozonerx(foo, fd);
$fwrite (fd, " 1019");
$fwrite (fd, " 1020");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1021");
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1022");
if (foo[20])
begin
$fwrite (fd, " 1023");
ozoneacc(foo[18], fd);
$fwrite (fd, " 1024");
$fwrite (fd, " 1025");
if (foo[19])
$fwrite (fd, " 1026");
else
$fwrite (fd, " 1027");
end
else
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1028");
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1029");
$fwrite (fd, " 1030");
ozonehl(foo[20], fd);
$fwrite (fd, " 1031");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1032");
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1033");
$fwrite (fd, " 1034");
ozonehl(foo[20], fd);
$fwrite (fd, " 1035");
ozonerx(foo, fd);
dude(fd);
$fwrite (fd, " 1036");
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1037");
ozonerx(foo, fd);
$fwrite (fd, " 1038");
$fwrite (fd, " 1039");
ozonehl(foo[20], fd);
dude(fd);
$fwrite (fd, " 1040");
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, fd);
$fwrite (fd, " 1041");
$fwrite (fd, " 1042");
ozonerx(foo, fd);
$fwrite (fd, " 1043");
if (foo[20])
$fwrite (fd, " 1044");
else
$fwrite (fd, " 1045");
dude(fd);
$fwrite (fd, " 1046");
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
$fwrite (fd, " 1047");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1048");
ozonef1e(foo, fd);
dude(fd);
$fwrite (fd, " 1049");
end
7'b00_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1050");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
$fwrite (fd, " 1051");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b01:
begin
$fwrite (fd, " 1052");
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
end
2'b10:
begin
$fwrite (fd, " 1053");
ozoneae(foo[14:12], fd);
end
2'b11: $fwrite (fd, " 1054");
endcase
dude(fd);
$fwrite (fd, " 1055");
end
7'b01_?_110_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1056");
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1057");
end
2'b01:
begin
ozoneae(foo[14:12], fd);
ozonehl(foo[ 5], fd);
$fwrite (fd, " 1058");
end
2'b10:
begin
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1059");
end
2'b11: $fwrite (fd, " 1060");
endcase
dude(fd);
$fwrite (fd, " 1061");
end
7'b10_0_110_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1062");
$fwrite (fd, " 1063");
if (foo[12])
$fwrite (fd, " 1064");
else
ozonerab({4'b1001, foo[14:12]}, fd);
dude(fd);
$fwrite (fd, " 1065");
end
7'b10_0_110_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1066");
if (foo[12])
$fwrite (fd, " 1067");
else
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1068");
dude(fd);
$fwrite (fd, " 1069");
end
7'b??_?_000_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1070");
$fwrite (fd, " 1071");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1072");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1073");
end
7'b??_?_100_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1074");
$fwrite (fd, " 1075");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1076");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1077");
end
7'b??_?_001_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1078");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1079");
$fwrite (fd, " 1080");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1081");
end
7'b??_?_011_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1082");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1083");
$fwrite (fd, " 1084");
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1085");
end
7'b??_?_101_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1086");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1087");
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1088");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
$fwrite (fd, " 1089");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1090");
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1091");
if (foo[ 6])
$fwrite (fd, " 1092");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
$fwrite (fd, " 1093");
$fwrite (fd, " 1094");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1095");
endcase
dude(fd);
$fwrite (fd, " 1096");
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1097");
ozonef1e_ye(foo[14:9],foo[ 5], fd);
$fwrite (fd, " 1098");
ozoneae(foo[ 8: 6], fd);
ozonef1e_hl(foo[11:9],foo[ 5], fd);
dude(fd);
$fwrite (fd, " 1099");
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1100");
$fwrite (fd, " 1101");
ozonerme(foo[14:12], fd);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0, fd);
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1102");
endcase
$fwrite (fd, " 1103");
if (foo[ 6])
$fwrite (fd, " 1104");
else
ozonerab({4'b1001, foo[ 8: 6]}, fd);
dude(fd);
$fwrite (fd, " 1105");
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1106");
case (foo[11:9])
3'h2:
begin
$fwrite (fd, " 1107");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1108");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1109");
end
3'h6:
begin
$fwrite (fd, " 1110");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1111");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1112");
end
3'h0:
begin
$fwrite (fd, " 1113");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1114");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1115");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1116");
else
ozonexe(foo[ 8: 5], fd);
end
3'h1:
begin
$fwrite (fd, " 1117");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1118");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1119");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1120");
else
ozonexe(foo[ 8: 5], fd);
end
3'h4:
begin
$fwrite (fd, " 1121");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1122");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1123");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1124");
else
ozonexe(foo[ 8: 5], fd);
end
3'h5:
begin
$fwrite (fd, " 1125");
if (foo[14:12] == 3'h0)
$fwrite (fd, " 1126");
else
ozonerme(foo[14:12], fd);
$fwrite (fd, " 1127");
if (foo[ 7: 5] >= 3'h5)
$fwrite (fd, " 1128");
else
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1129");
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1130");
$fwrite (fd, " 1131");
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1132");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1133");
end
6'b???_11_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1134");
ozoneae(foo[14:12], fd);
ozonef1e_hl(foo[ 7: 5],foo[ 9], fd);
$fwrite (fd, " 1135");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1136");
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1137");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1138");
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
$fwrite (fd, " 1139");
else
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1140");
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1141");
$fwrite (fd, " 1142");
ozonerab({4'b1001, foo[14:12]}, fd);
$fwrite (fd, " 1143");
$fwrite (fd, " 1144");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1145");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1146");
end
6'b???_00_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1147");
if (foo[ 9])
begin
$fwrite (fd, " 1148");
ozoneae(foo[14:12], fd);
end
else
begin
$fwrite (fd, " 1149");
ozoneae(foo[14:12], fd);
$fwrite (fd, " 1150");
end
$fwrite (fd, " 1151");
$fwrite (fd, " 1152");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1153");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1154");
end
6'b???_01_?:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1155");
ozoneae(foo[14:12], fd);
if (foo[ 9])
$fwrite (fd, " 1156");
else
$fwrite (fd, " 1157");
$fwrite (fd, " 1158");
$fwrite (fd, " 1159");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1160");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1161");
end
6'b011_10_0:
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1162");
case (foo[ 8: 5])
4'h0: $fwrite (fd, " 1163");
4'h1: $fwrite (fd, " 1164");
4'h2: $fwrite (fd, " 1165");
4'h3: $fwrite (fd, " 1166");
4'h4: $fwrite (fd, " 1167");
4'h5: $fwrite (fd, " 1168");
4'h8: $fwrite (fd, " 1169");
4'h9: $fwrite (fd, " 1170");
4'ha: $fwrite (fd, " 1171");
4'hb: $fwrite (fd, " 1172");
4'hc: $fwrite (fd, " 1173");
4'hd: $fwrite (fd, " 1174");
default: $fwrite (fd, " 1175");
endcase
dude(fd);
$fwrite (fd, " 1176");
end
default: $fwrite (fd, " 1177");
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1178");
$fwrite (fd, " 1179");
ozonef1e_hl(foo[11:9], foo[0], fd);
$fwrite (fd, " 1180");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1181");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1182");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1183");
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1184");
$fwrite (fd, " 1185");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1186");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1187");
$fwrite (fd, " 1188");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1189");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1190");
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1191");
ozonef1e_ye(foo[14:9],foo[ 0], fd);
$fwrite (fd, " 1192");
$fwrite (fd, " 1193");
ozonef1e_hl(foo[11:9],foo[0], fd);
$fwrite (fd, " 1194");
$fwrite (fd, " 1195");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1196");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1197");
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1198");
$fwrite (fd, " 1199");
ozonef1e_h(foo[11:9], fd);
$fwrite (fd, " 1200");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1201");
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
$fwrite (fd, " 1202");
default:
begin
$fwrite (fd, " 1203");
$fwrite (fd, " 1204");
ozonexe(foo[ 8: 5], fd);
end
endcase
dude(fd);
$fwrite (fd, " 1205");
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1206");
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
$fwrite (fd, " 1207");
default:
begin
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1208");
$fwrite (fd, " 1209");
end
endcase
$fwrite (fd, " 1210");
$fwrite (fd, " 1211");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1212");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1213");
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1214");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1215");
$fwrite (fd, " 1216");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1217");
$fwrite (fd, " 1218");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1219");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1220");
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, fd);
$fwrite (fd, " 1221");
ozonef1e_ye(foo[14:9],1'b0, fd);
$fwrite (fd, " 1222");
$fwrite (fd, " 1223");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1224");
$fwrite (fd, " 1225");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1226");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite (fd, " 1227");
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
$fwrite (fd," 1228");
else
$fwrite (fd," 1229");
ozonecon(foo[20:16], fd);
$fwrite (fd, " 1230");
ozonef2(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1231");
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
$fwrite (fd," 1232");
else
$fwrite (fd," 1233");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1234");
ozonef2e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1235");
end
else
begin
$fwrite (fd, " 1236");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1237");
ozonef3e(foo[31:0], fd);
dude(fd);
$fwrite (fd, " 1238");
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], fd);
dude(fd);
$fwrite(fd, " 1239");
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1241");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1242");
dude(fd);
$fwrite(fd, " 1243");
end
5'b0_01??:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1244");
ozoneacc(foo[25], fd);
ozonebmuop(foo[24:20], fd);
ozonearm(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1245");
end
5'b0_1011:
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1246");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1247");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1248");
dude(fd);
$fwrite(fd, " 1249");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1250");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1251");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1252");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1253");
dude(fd);
$fwrite(fd, " 1254");
end
5'b0_1111 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1255");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1256");
ozoneae(foo[18:16], fd);
dude(fd);
$fwrite(fd, " 1257");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], fd);
$fwrite (fd, " 1258");
ozonebmuop(foo[24:20], fd);
$fwrite (fd, " 1259");
ozoneacc(foo[25], fd);
$fwrite (fd, " 1260");
ozonearm(foo[18:16], fd);
$fwrite (fd, " 1261");
dude(fd);
$fwrite(fd, " 1262");
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1263");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1264");
ozoneae(foo[18:16], fd);
$fwrite (fd, " 1265");
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3:0], fd);
$fwrite (fd, " 1266");
dude(fd);
$fwrite(fd, " 1267");
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], fd);
$fwrite (fd, " 1268");
if (foo[23:21] == 3'b100)
$fwrite (fd, " 1269");
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1270");
else
$fwrite (fd, " 1271");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1272");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1273");
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], fd);
if (foo[19])
$fwrite (fd, " 1274");
else
$fwrite (fd, " 1275");
ozonef3f4imop(foo[23:19], fd);
$fwrite (fd, " 1276");
ozonef3f4_iext(foo[20:19], foo[15:0], fd);
dude(fd);
$fwrite(fd, " 1277");
end
endcase
17'b00_1000_?_????_11_0011 :
begin
$fwrite (fd," 1278");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1279");
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1281");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1282");
dude(fd);
$fwrite(fd, " 1283");
end
5'b0_01??:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1284");
ozoneae(foo[17:15], fd);
ozonebmuop(foo[25:21], fd);
ozonearm(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1285");
end
5'b0_1011:
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1286");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1287");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1288");
dude(fd);
$fwrite(fd, " 1289");
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1290");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1291");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1292");
ozoneae(foo[ 8: 6], fd);
$fwrite (fd, " 1293");
dude(fd);
$fwrite(fd, " 1294");
end
5'b0_1111 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1295");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1296");
ozoneae(foo[ 8: 6], fd);
dude(fd);
$fwrite(fd, " 1297");
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], fd);
$fwrite (fd, " 1298");
ozonebmuop(foo[25:21], fd);
$fwrite (fd, " 1299");
ozoneae(foo[17:15], fd);
$fwrite (fd, " 1300");
ozonearm(foo[ 8: 6], fd);
$fwrite (fd, " 1301");
dude(fd);
$fwrite(fd, " 1302");
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1303");
skyway(foo[19:16], fd);
dude(fd);
$fwrite(fd, " 1304");
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
$fwrite (fd, " 1305");
if (foo[26])
$fwrite (fd, " 1306");
else
$fwrite (fd, " 1307");
skyway(foo[19:16], fd);
$fwrite (fd, " 1308");
ozonerab({1'b0, foo[25:20]}, fd);
end
else
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1309");
if (foo[26])
$fwrite (fd, " 1310");
else
$fwrite (fd, " 1311");
skyway(foo[19:16], fd);
$fwrite (fd, " 1312");
end
dude(fd);
$fwrite(fd, " 1313");
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], fd);
$fwrite (fd, " 1314");
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
end
else
begin
ozoneae(foo[18:16], fd);
ozonehl(foo[19], fd);
$fwrite (fd, " 1315");
ozonerb(foo[25:20], fd);
end
dude(fd);
$fwrite(fd, " 1316");
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, fd);
$fwrite (fd, " 1317");
ozonerx(foo, fd);
end
else
begin
ozonerx(foo, fd);
$fwrite (fd, " 1318");
ozonerab({1'b0, foo[25:20]}, fd);
end
dude(fd);
$fwrite(fd, " 1319");
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], fd);
$fwrite (fd, " 1320");
skyway(foo[19:16], fd);
skyway(foo[15:12], fd);
skyway(foo[11: 8], fd);
skyway(foo[ 7: 4], fd);
skyway(foo[ 3: 0], fd);
dude(fd);
$fwrite(fd, " 1321");
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1322");
end
3'b01?:
begin
$fwrite (fd, " 1323");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1324");
else
ozonerab(foo[22:16], fd);
end
3'b110:
$fwrite (fd, " 1325");
3'b10?:
begin
$fwrite (fd, " 1326");
if (foo[22:16]>=7'h60)
$fwrite (fd, " 1327");
else
ozonerab(foo[22:16], fd);
end
3'b111:
begin
$fwrite (fd, " 1328");
ozonerab(foo[22:16], fd);
$fwrite (fd, " 1329");
end
endcase
dude(fd);
$fwrite(fd, " 1330");
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
$fwrite (fd, " 1331");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1332");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1333");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1334");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1335");
$fwrite (fd, " 1336");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1337");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
$fwrite (fd, " 1338");
end
dude(fd);
$fwrite(fd, " 1339");
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
$fwrite (fd, " 1340");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1341");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1342");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1343");
else
ozonerab(foo[26:20], fd);
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1344");
$fwrite (fd, " 1345");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1346");
ozonejk(foo[ 5], fd);
$fwrite (fd, " 1347");
end
dude(fd);
$fwrite(fd, " 1348");
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1350");
ozoneye(foo[14: 9],foo[ 5], fd);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], fd);
$fwrite (fd, " 1351");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1352");
else
ozonerab(foo[26:20], fd);
end
dude(fd);
$fwrite(fd, " 1353");
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, fd);
$fwrite (fd, " 1355");
ozonef1e_h(foo[11: 9], fd);
$fwrite (fd, " 1356");
ozonef1e_h(foo[ 7: 5], fd);
$fwrite (fd, " 1357");
ozonexe(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1358");
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
$fwrite (fd, " 1360");
if (foo[26:20]>=7'h60)
$fwrite (fd, " 1361");
else
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1362");
$fwrite (fd, " 1363");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1364");
end
else
begin
ozonerab(foo[26:20], fd);
$fwrite (fd, " 1365");
$fwrite (fd, " 1366");
skyway({1'b0,foo[18:16]}, fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1367");
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, fd);
$fwrite (fd, " 1369");
ozonerab({1'b0,foo[25:20]}, fd);
dude(fd);
$fwrite(fd, " 1370");
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
$fwrite (fd," 1371");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1372");
ozonerab({foo[ 9: 7],foo[19:16]}, fd);
$fwrite (fd, " 1373");
ozonerab({foo[26:20]}, fd);
dude(fd);
$fwrite(fd, " 1374");
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1376");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1377");
skyway(foo[19:16], fd);
skyway({foo[15],foo[11: 9]}, fd);
skyway(foo[ 8: 5], fd);
dude(fd);
$fwrite(fd, " 1378");
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], fd);
$fwrite (fd, " 1379");
ozonerp(foo[14:12], fd);
$fwrite (fd, " 1380");
ozonejk(foo[ 5], fd);
dude(fd);
$fwrite(fd, " 1381");
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%x", foo[27:16]);
else
$fwrite(fd, " 1384:%x", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%x", foo[27: 8]);
else
$fwrite(fd, " 1386:%x", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
$fwrite (fd," 1388");
ozonecon(foo[14:10], fd);
$fwrite (fd, " 1389");
if (foo[15])
$fwrite (fd, " 1390");
else
$fwrite (fd, " 1391");
skyway(foo[27:24], fd);
skyway(foo[23:20], fd);
skyway(foo[19:16], fd);
skyway(foo[ 9: 6], fd);
dude(fd);
$fwrite(fd, " 1392");
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
$fwrite (fd," 1393");
ozonecon(foo[20:16], fd);
case (foo[23:21])
3'h0 : $fwrite (fd, " 1394");
3'h1 : $fwrite (fd, " 1395");
3'h2 : $fwrite (fd, " 1396");
3'h3 : $fwrite (fd, " 1397");
3'h4 : $fwrite (fd, " 1398");
3'h5 : $fwrite (fd, " 1399");
3'h6 : $fwrite (fd, " 1400");
3'h7 : $fwrite (fd, " 1401");
endcase
dude(fd);
$fwrite(fd, " 1402");
end
4'b0000 :
$fwrite(fd, " 1403:%x", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%x", foo[22:16]);
else
$fwrite(fd, " 1409:%x", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
module GE_patch
(
SYS_CLK,
GMII_TXCLK,
GMII_GTXCLK,
GMII_GE_IND,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_MDIO_O,
ENET0_MDIO_T,
GMII_MDIO
);
input SYS_CLK;
input GMII_TXCLK;
output GMII_GTXCLK;
input GMII_GE_IND;
output ENET0_GMII_TX_CLK;
output ENET0_MDIO_I;
input ENET0_MDIO_O;
input ENET0_MDIO_T;
inout GMII_MDIO;
// internal signal
wire clk_125M;
wire pll_locked;
wire pll_reset;
reg GMII_GE_IND_reg;
reg[27:0] GMII_GE_TIMER;
clk_wiz_0 pll
(
.clk_in1(SYS_CLK),
.clk_out1(clk_125M)
);
IOBUF GMII_MDIO_BUF
(
.I(ENET0_MDIO_O),
.IO(GMII_MDIO),
.O(ENET0_MDIO_I),
.T(ENET0_MDIO_T)
);
always @ (posedge clk_125M)
begin
if ( GMII_GE_IND==1'b1 ) begin
GMII_GE_IND_reg <= 1'b1;
GMII_GE_TIMER <= 28'h0000000;
end
else begin
if ( GMII_GE_TIMER==28'hffffff ) GMII_GE_IND_reg <= 1'b0;
else GMII_GE_TIMER <= GMII_GE_TIMER+1'b1;
end
end
assign GMII_GTXCLK = clk_125M;
assign ENET0_GMII_TX_CLK = (GMII_GE_IND_reg==1'b1)? clk_125M:GMII_TXCLK;
endmodule
|
/*
* Rx_Header Module
* Author: Benjamin Huntsman
*
* This module controls the receiving and appropriate transimission of the
* TLP Header. This module is instantiated in the Rx_Engine and will control
* the loading of the TLP header into the Tx_Header_FIFO and into registers
* that will be holding the header data for translation into OCP Signals.
*/
module rx_fsm(
// Module Ports /*{{{*/
// Command Signals /*{{{*/
input wire rx_reset,
/*}}}*/
// PCIe Core AXI Interface/*{{{*/
input wire rx_clk, // clock for entire bridge
input wire rx_valid, //
input wire [keep_width - 1:0] rx_keep,
input wire rx_last,
output reg rx_ready,
/*}}}*/
// Tx Header AXI FIFO/*{{{*/
input wire tx_header_fifo_ready,
output reg tx_header_fifo_valid,
/*}}}*/
// OCP Registers/*{{{*/
input wire [1:0] optype, // Indicates that the header will be 4DW, not 3DW and if data is present or not
output reg [2:0] ocp_reg_ctl, // Controls the inputs to the OCP registers for translation and data
// OCP Controller/*{{{*/
input wire ocp_ready, // Indicates that the OCP interface is ready for transmission of data
output reg ocp_valid, // Indicates to the OCP interface that a transaction is ready
output reg ocp_readreq, // Indicates to the OCP interface that a read request is being made
output reg ocp_writereq // Indicates to the OCP interface that a write request is being made
/*}}}*/
);
/*}}}*/
/*}}}*/
// Declarations/*{{{*/
// Parameters for parameterization of module
parameter keep_width = 8;
// State encodings
localparam IDLE = 3'b000;
localparam H1 = 3'b001;
localparam H2 = 3'b010;
localparam DATA3 = 3'b011;
localparam DATA4 = 3'b100;
// State Registers
reg [3:0] state;
reg [3:0] next;
/*}}}*/
// Begin FSM Blocks/*{{{*/
// State transition logic/*{{{*/
always @(posedge clk) begin
if (reset) begin
state <= 4'b0; // Reset state value to zero
state[IDLE] <= 1'b1; end // Set to RESET state
else begin
state <= next; end // Transition to next state
end
/*}}}*/
// Next state logic/*{{{*/
always @(state) begin
next <= 4'b0;
case (1'b1)
// IDLE/*{{{*/
// System Idles while waiting for valid TLP to be presented
// Stays until rx_valid and tx_header_fifo_ready asserted
state[IDLE]: begin
if (rx_valid && tx_header_fifo_ready) begin // TLP ready to receive
next[H1] = 1'b1; end
else begin // Not valid so stay
next[IDLE] = 1'b1; end
end
/*}}}*/
// H1/*{{{*/
// First header slice transmitted
// Stays unless PCIe Core holds valid high and tx header fifo is
// ready
state[H1]: begin
if (rx_valid && tx_header_fifo_ready) begin // Received first slice, move to second
next[H2] = 1'b1; end
else begin // Not valid so stay
next[H1] = 1'b1; end
end
/*}}}*/
// H2/*{{{*/
// Second header slice transmitted
state[H2]: begin
if (rx_valid && tx_header_fifo_ready && optype[1]) begin
if (optype[0] == 0) begin // Mem write 3 DW, transmit data
next[DATA3] = 1'b1; end
else begin // Mem write 4 DW, transmit data
next[DATA4] = 1'b1; end
end
else if (rx_valid && tx_header_fifo_ready && rx_last) begin // Read op, only header
next[IDLE] = 1'b1; end
else begin // Not valid so stay
next[H2] = 1'b1; end
end
/*}}}*/
// Data transmission/*{{{*/
// Controls transmission of data on a 96 bit shift register
state[DATA3]: begin
if (rx_valid && ocp_ready && rx_last) begin // Written last data, finish operation
next[IDLE] = 1'b1; end
else begin // Still data left to transmit or not valid, so stay
next[DATA3] = 1'b1; end
state[DATA4]: begin
if (rx_valid && ocp_ready && rx_last) begin // Written last data, finish operation
next[IDLE] = 1'b1; end
else begin // Still data left to transmit or not valid, so stay
next[DATA4] = 1'b1; end
//*}}}*/
default: begin
next[IDLE] = 1'b1; end // If nothing matches return to default
endcase
end
/*}}}*/
// Output logic/*{{{*/
always @(posedge rx_clk) begin
case (1'b1)
// IDLE/*{{{*/
// System Idles while waiting for valid TLP to be presented
// All outputs should be set to default
state[IDLE]: begin // IDLE - Waiting for TLP
rx_ready <= 1'b0; // Rx waiting
tx_header_fifo_valid <= 1'b0; // Nothing being presented to tx header fifo
ocp_reg_ctl <= IDLE; // OCP registers do nothing
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
/*}}}*/
// H1/*{{{*/
// First header slice transmitted
state[H1]: begin
if (rx_valid && tx_header_fifo_ready) begin // Receiving first slice
rx_ready <= 1'b1; // Ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H1; // Slice goes into H1 OCP register
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else if (rx_valid && ~tx_header_fifo_ready) begin // Not ready to receive due to tx_header FIFO
rx_ready <= 1'b0; // Not ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H1; // Stay on H1
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else begin // Valid data not being presented
rx_ready <= 1'b0; // Not ready to receive due to no valid data
tx_header_fifo_valid <= 1'b0; // Not presenting valid data to tx fifo
ocp_reg_ctl <= H1; // Stay on H1
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
/*}}}*/
// H2/*{{{*/
// Second header slice transmitting
state[H2]: begin
if (rx_valid && tx_header_fifo_ready) begin // Receiving second slice
rx_ready <= 1'b1; // Ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H2; // Slice goes into H2 OCP register
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else if (rx_valid && ~tx_header_fifo_ready) begin // Not ready to receive due to tx_header FIFO
rx_ready <= 1'b0; // Not ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H2; // Stay on H2
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else begin // Valid data not being presented
rx_ready <= 1'b0; // Not ready to receive due to no valid data
tx_header_fifo_valid <= 1'b0; // Not presenting valid data to tx fifo
ocp_reg_ctl <= H2; // Stay on H2
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
/*}}}*/
// Data transmission/*{{{*/
// Controls transmission of data on a 96 bit shift register
state[DATA3]: begin
if (rx_valid && ocp_ready) begin // Writing data onto OCP lines
rx_ready <= 1'b1; // Ready to transmit data
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA3; // Stay on DATA3
ocp_valid <= 1'b1; // Data being presented to OCP interface
if (optype[1]) == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
else begin // No data transmitting due to OCP or no valid data
rx_ready <= 1'b0; // Not ready to transmit
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA3; // Stay on DATA3
ocp_valid <= rx_valid; // Data only being presented if valid on AXI int.
if (optype[1] == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
end
state[DATA4]: begin
if (rx_valid && ocp_ready) begin // Writing data onto OCP lines
rx_ready <= 1'b1; // Ready to transmit data
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA4; // Stay on DATA4
ocp_valid <= 1'b1; // Data being presented to OCP interface
if (optype[1] == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
else begin // No data transmitting due to OCP or no valid data
rx_ready <= 1'b0; // Not ready to transmit
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA4; // Stay on DATA4
ocp_valid <= rx_valid; // Data begin presented only if valid on AXI int.
if (optype[1] == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
end
//*}}}*/
// Default/*{{{*/
default: begin
next[IDLE] = 1'b1; end // If nothing matches return to default
endcase
end/*}}}*//*}}}*/
endmodule
|
`timescale 1ns / 1ps
module ov7670_top(
input clk,
output scl,
inout sda,
output ov7670_reset,
output pwdn,
output xclk,
input pclk,
input href,
input vsync,
input [7:0] data,
input M_AXIS_TREADY,
output M_AXIS_TVALID,
output M_AXIS_TLAST,
output M_AXIS_TUSER,
output [23:0] M_AXIS_TDATA);
// http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670
ov7670_controller controller(.clk(clk),
.sioc(scl),
.siod(sda),
.reset(ov7670_reset),
.pwdn(pwdn),
.xclk(xclk));
OV7670_CAPTURE_AXI_VDMA_STREAM ov7670_axi(.pclk(pclk),
.href(href),
.vsync(vsync),
.data(data),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TLAST(M_AXIS_TLAST),
.M_AXIS_TUSER(M_AXIS_TUSER),
.M_AXIS_TDATA(M_AXIS_TDATA));
endmodule
|
/********************************************/
/* minimig_de2_top.v */
/* Altera DE2 FPGA Top File */
/* */
/* 2012, [email protected] */
/********************************************/
`define MINIMIG_DE2
//`define SOC_SIM
`include "minimig_defines.vh"
module minimig_de2_top (
// clock inputs
input wire CLOCK_27, // 27 MHz
input wire CLOCK_50, // 50 MHz
input wire EXT_CLOCK, // External Clock
// USB JTAG Link
input wire TDI, // CPLD -> FPGA (data in)
input wire TCK, // CPLD -> FPGA (clk)
input wire TCS, // CPLD -> FPGA (CS)
output wire TDO, // FPGA -> CPLD (data out)
// push button inputs
input wire [ 4-1:0] KEY, // Pushbutton[3:0]
// switch inputs
input wire [ 10-1:0] SW, // Toggle Switch[9:0]
// 7-seg display outputs
output wire [ 7-1:0] HEX0, // Seven Segment Digit 0
output wire [ 7-1:0] HEX1, // Seven Segment Digit 1
output wire [ 7-1:0] HEX2, // Seven Segment Digit 2
output wire [ 7-1:0] HEX3, // Seven Segment Digit 3
// LED outputs
output wire [ 8-1:0] LEDG, // LED Green[7:0]
output wire [ 10-1:0] LEDR, // LED Red[9:0]
// UART
output wire UART_TXD, // UART Transmitter
input wire UART_RXD, // UART Receiver
// I2C
inout wire I2C_SDAT, // I2C Data
output wire I2C_SCLK, // I2C Clock
// PS2
inout wire PS2_DAT, // PS2 Keyboard Data
inout wire PS2_CLK, // PS2 Keyboard Clock
inout wire PS2_MDAT, // PS2 Mouse Data
inout wire PS2_MCLK, // PS2 Mouse Clock
// VGA
output wire VGA_HS, // VGA H_SYNC
output wire VGA_VS, // VGA V_SYNC
output wire [ 10-1:0] VGA_R, // VGA Red[3:0]
output wire [ 10-1:0] VGA_G, // VGA Green[3:0]
output wire [ 10-1:0] VGA_B, // VGA Blue[3:0]
output wire VGA_SYNC, // VGA Sync signal
output wire VGA_BLANK, // VGA blanking signal
output wire VGA_CLK, // VGA clock
// Audio CODEC
inout wire AUD_ADCLRCK, // Audio CODEC ADC LR Clock
input wire AUD_ADCDAT, // Audio CODEC ADC Data
inout wire AUD_DACLRCK, // Audio CODEC DAC LR Clock
output wire AUD_DACDAT, // Audio CODEC DAC Data
inout wire AUD_BCLK, // Audio CODEC Bit-Stream Clock
output wire AUD_XCK, // Audio CODEC Chip Clock
// SD Card
input wire SD_DAT, // SD Card Data - spi MISO
output wire SD_DAT3, // SD Card Data 3 - spi CS
output wire SD_CMD, // SD Card Command Signal - spi MOSI
output wire SD_CLK, // SD Card Clock - spi CLK
// SRAM
inout wire [ 16-1:0] SRAM_DQ, // SRAM Data bus 16 Bits
output wire [ 18-1:0] SRAM_ADDR, // SRAM Address bus 18 Bits
output wire SRAM_UB_N, // SRAM High-byte Data Mask
output wire SRAM_LB_N, // SRAM Low-byte Data Mask
output wire SRAM_WE_N, // SRAM Write Enable
output wire SRAM_CE_N, // SRAM Chip Enable
output wire SRAM_OE_N, // SRAM Output Enable
// SDRAM
inout wire [ 16-1:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output wire [ 12-1:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
output wire DRAM_LDQM, // SDRAM Low-byte Data Mask
output wire DRAM_UDQM, // SDRAM High-byte Data Mask
output wire DRAM_WE_N, // SDRAM Write Enable
output wire DRAM_CAS_N, // SDRAM Column Address Strobe
output wire DRAM_RAS_N, // SDRAM Row Address Strobe
output wire DRAM_CS_N, // SDRAM Chip Select
output wire DRAM_BA_0, // SDRAM Bank Address 0
output wire DRAM_BA_1, // SDRAM Bank Address 1
output wire DRAM_CLK, // SDRAM Clock
output wire DRAM_CKE, // SDRAM Clock Enable
// FLASH
inout wire [ 8-1:0] FL_DQ, // FLASH Data bus 8 Bits
output wire [ 22-1:0] FL_ADDR, // FLASH Address bus 22 Bits
output wire FL_WE_N, // FLASH Write Enable
output wire FL_RST_N, // FLASH Reset
output wire FL_OE_N, // FLASH Output Enable
output wire FL_CE_N, // FLASH Chip Enable
// MINIMIG specific
input wire [ 6-1:0] Joya, // joystick port A
input wire [ 6-1:0] Joyb, // joystick port B
output wire AUDIOLEFT, // sigma-delta DAC output left
output wire AUDIORIGHT // sigma-delta DAC output right
);
////////////////////////////////////////
// internal signals //
////////////////////////////////////////
// clock
wire pll_in_clk;
wire clk_114;
wire clk_28;
wire clk_sdram;
wire pll_locked;
wire clk_7;
wire clk7_en;
wire c1;
wire c3;
wire cck;
wire [ 10-1:0] eclk;
wire clk_50;
// reset
wire pll_rst;
wire sdctl_rst;
wire rst_50;
wire rst_minimig;
wire rst_cpu;
// ctrl
wire rom_status;
wire ram_status;
wire reg_status;
wire dram_status;
wire ctrl_txd;
wire ctrl_rxd;
wire [ 22-1:0] dram_adr;
wire dram_cs;
wire dram_we;
wire [ 4-1:0] dram_sel;
wire [ 32-1:0] dram_dat_w;
wire [ 32-1:0] dram_dat_r;
wire dram_ack;
wire dram_err;
// bridge
wire [ 22-1:0] bridge_adr;
wire bridge_cs;
wire bridge_we;
wire [ 2-1:0] bridge_sel;
wire [ 16-1:0] bridge_dat_w;
wire [ 16-1:0] bridge_dat_r;
wire bridge_ack;
wire bridge_err;
// tg68
wire tg68_rst;
wire [ 16-1:0] tg68_dat_in;
wire [ 16-1:0] tg68_dat_out;
wire [ 32-1:0] tg68_adr;
wire [ 3-1:0] tg68_IPL;
wire tg68_dtack;
wire tg68_as;
wire tg68_uds;
wire tg68_lds;
wire tg68_rw;
wire tg68_ena7RD;
wire tg68_ena7WR;
wire tg68_enaWR;
wire [ 16-1:0] tg68_cout;
wire tg68_cpuena;
wire [ 4-1:0] cpu_config;
wire [ 6-1:0] memcfg;
wire vsync;
wire [ 32-1:0] tg68_cad;
wire [ 6-1:0] tg68_cpustate;
wire tg68_cdma;
wire tg68_clds;
wire tg68_cuds;
wire [ 32-1:0] tg68_VBR_out;
// minimig
wire minimig_rst_out;
wire [ 16-1:0] ram_data; // sram data bus
wire [ 16-1:0] ramdata_in; // sram data bus in
wire [ 22-1:1] ram_address; // sram address bus
wire _ram_bhe; // sram upper byte select
wire _ram_ble; // sram lower byte select
wire _ram_we; // sram write enable
wire _ram_oe; // sram output enable
wire _15khz; // scandoubler disable
wire sdo; // SPI data output
wire [ 15-1:0] ldata; // left DAC data
wire [ 15-1:0] rdata; // right DAC data
wire audio_left;
wire audio_right;
wire floppy_fwr;
wire floppy_frd;
wire hd_fwr;
wire hd_frd;
wire minimig_txd;
wire minimig_rxd;
// host bus
wire host_cs;
wire [ 24-1:0] host_adr;
wire host_we;
wire [ 2-1:0] host_bs;
wire [ 16-1:0] host_wdat;
wire [ 16-1:0] host_rdat;
wire host_ack;
// sdram
wire reset_out;
wire [ 4-1:0] sdram_cs;
wire [ 2-1:0] sdram_dqm;
wire [ 2-1:0] sdram_ba;
// audio
wire audio_lr_switch;
wire audio_lr_mix;
// ctrl
wire [ 16-1:0] SRAM_DAT_W;
wire [ 16-1:0] SRAM_DAT_R;
wire [ 8-1:0] FL_DAT_W;
wire [ 8-1:0] FL_DAT_R;
wire [ 4-1:0] SPI_CS_N;
wire SPI_DI;
wire rst_ext;
wire [ 4-1:0] ctrl_cfg;
wire [ 4-1:0] ctrl_status;
wire [ 4-1:0] sys_status;
// indicators
wire [ 8-1:0] track;
// uart
wire uart_sel;
////////////////////////////////////////
// input synchronizers //
////////////////////////////////////////
wire sw_9, sw_8, sw_7, sw_6, sw_5, sw_4, sw_3, sw_2, sw_1;
wire key_3, key_2, key_1, key_0;
i_sync #(.DW(4)) i_sync_sw_28 (
.clk (clk_28),
.i ({SW[9], SW[8], SW[7], SW[6]}),
.o ({sw_9, sw_8, sw_7, sw_6})
);
i_sync #(.DW(4)) i_sync_key_28 (
.clk (clk_28),
.i ({KEY[3], KEY[2], KEY[1], KEY[0]}),
.o ({key_3, key_2, key_1, key_0})
);
i_sync #(.DW(5)) i_sync_sw_50 (
.clk (clk_50),
.i ({SW[5], SW[4], SW[3], SW[2], SW[1]}),
.o ({sw_5, sw_4, sw_3, sw_2, sw_1})
);
i_sync #(.DW(4)) i_sync_ctrl_50 (
.clk (clk_50),
.i ({vsync, ~tg68_rst, minimig_rst_out, ~reset_out}),
.o (sys_status)
);
// temp
wire [3-1:0] cctrl;
i_sync #(.DW(3)) i_sync_key_28_tmp (
.clk (clk_28),
.i ({SW[3], SW[2], SW[1]}),
.o (cctrl)
);
// temp
////////////////////////////////////////
// toplevel assignments //
////////////////////////////////////////
// assign unused outputs
assign TDO = 1'b1;
// UART
assign uart_sel = sw_5;
assign UART_TXD = uart_sel ? ctrl_txd : minimig_txd;
assign ctrl_rxd = uart_sel ? UART_RXD : 1'b1;
assign minimig_rxd = uart_sel ? 1'b1 : UART_RXD;
// SD card
assign SD_DAT3 = SPI_CS_N[0];
// SRAM
assign SRAM_DQ = SRAM_OE_N ? SRAM_DAT_W : 16'bzzzzzzzzzzzzzzzz;
assign SRAM_DAT_R = SRAM_DQ;
// SDRAM
assign DRAM_CKE = 1'b1;
assign DRAM_CLK = clk_sdram;
assign DRAM_CS_N = sdram_cs[0];
assign DRAM_LDQM = sdram_dqm[0];
assign DRAM_UDQM = sdram_dqm[1];
assign DRAM_BA_0 = sdram_ba[0];
assign DRAM_BA_1 = sdram_ba[1];
// FLASH
assign FL_DQ = FL_OE_N ? FL_DAT_W : 8'bzzzzzzzz;
assign FL_DAT_R = FL_DQ;
// AUDIO
//`define MINIMIG_SERIAL_AUDIO
`ifdef MINIMIG_SERIAL_AUDIO
assign AUDIOLEFT = audio_left;
assign AUDIORIGHT = audio_right;
`else
assign AUDIOLEFT = 1'b0;
assign AUDIORIGHT = 1'b0;
`endif
// ctrl
assign SPI_DI = !SPI_CS_N[0] ? SD_DAT : sdo;
assign rst_ext = !KEY[0];
assign ctrl_cfg = {sw_4, sw_3, sw_2, sw_1};
// clock
assign pll_in_clk = CLOCK_27;
// reset
assign pll_rst = !SW[0];
assign sdctl_rst = pll_locked & SW[0];
// audio
assign audio_lr_switch = sw_7;
assign audio_lr_mix = sw_6;
// minimig
assign _15khz = sw_9;
// DE2 specific VGA wiring
assign VGA_R[5:0] = {VGA_R[9:6], VGA_R[9:8]};
assign VGA_G[5:0] = {VGA_G[9:6], VGA_G[9:8]};
assign VGA_B[5:0] = {VGA_B[9:6], VGA_B[9:8]};
assign VGA_BLANK = VGA_HS && VGA_VS;
assign VGA_SYNC = 0;
assign VGA_CLK = clk_28; //DRAM_CLK;
////////////////////////////////////////
// modules //
////////////////////////////////////////
//// control block ////
ctrl_top ctrl_top (
// system
.clk_in (CLOCK_50 ), // input 50MHz clock
.rst_ext (rst_ext ), // external reset input
.clk_out (clk_50 ), // output 50MHz clock from internal PLL
.rst_out (rst_50 ), // reset output from internal reset generator
.rst_minimig (rst_minimig ), // minimig reset output
.rst_cpu (rst_cpu ), // TG68K reset output
// config
.boot_sel (1'b0 ), // select FLASH boot location
.ctrl_cfg (ctrl_cfg ), // config for ctrl module
// status
.rom_status (rom_status ), // ROM slave activity
.ram_status (ram_status ), // RAM slave activity
.reg_status (reg_status ), // REG slave activity
.dram_status (dram_status ), // DRAM slave activity
.ctrl_status (ctrl_status ), // CTRL LEDs
.sys_status (sys_status ), // SYS status input
// SRAM interface
.sram_adr (SRAM_ADDR ), // SRAM address output
.sram_ce_n (SRAM_CE_N ), // SRAM chip enable output
.sram_we_n (SRAM_WE_N ), // SRAM write enable output
.sram_ub_n (SRAM_UB_N ), // SRAM upper byte select output
.sram_lb_n (SRAM_LB_N ), // SRAM lower byte select output
.sram_oe_n (SRAM_OE_N ), // SRAM output enable
.sram_dat_w (SRAM_DAT_W ), // SRAM write data
.sram_dat_r (SRAM_DAT_R ), // SRAM read data
// FLASH interface
.fl_adr (FL_ADDR ), // FLASH address output
.fl_ce_n (FL_CE_N ), // FLASH chip enable output
.fl_we_n (FL_WE_N ), // FLASH write enable output
.fl_oe_n (FL_OE_N ), // FLASH output enable
.fl_rst_n (FL_RST_N ), // FLASH reset
.fl_dat_w (FL_DAT_W ), // FLASH write data
.fl_dat_r (FL_DAT_R ), // FLASH read data
// DRAM interface
.dram_adr (dram_adr ),
.dram_cs (dram_cs ),
.dram_we (dram_we ),
.dram_sel (dram_sel ),
.dram_dat_w (dram_dat_w ),
.dram_dat_r (dram_dat_r ),
.dram_ack (dram_ack ),
.dram_err (dram_err ),
// UART
.uart_txd (ctrl_txd ), // UART transmit output
.uart_rxd (ctrl_rxd ), // UART receive input
// SPI
.spi_cs_n (SPI_CS_N ), // SPI chip select output
.spi_clk (SD_CLK ), // SPI clock
.spi_do (SD_CMD ), // SPI data input
.spi_di (SPI_DI ) // SPI data output
);
//// qmem async 32-to-16 bridge ////
`define CTRL_SDRAM_BRIDGE
`ifdef CTRL_SDRAM_BRIDGE
qmem_bridge #(
.MAW (22),
.MSW (4 ),
.MDW (32),
.SAW (22),
.SSW (2 ),
.SDW (16)
) qmem_bridge (
// master
.m_clk (clk_50 ),
.m_adr (dram_adr ),
.m_cs (dram_cs ),
.m_we (dram_we ),
.m_sel (dram_sel ),
.m_dat_w (dram_dat_w ),
.m_dat_r (dram_dat_r ),
.m_ack (dram_ack ),
.m_err (dram_err ),
// slave
.s_clk (clk_7 ),
.s_adr (bridge_adr ),
.s_cs (bridge_cs ),
.s_we (bridge_we ),
.s_sel (bridge_sel ),
.s_dat_w (bridge_dat_w ),
.s_dat_r (bridge_dat_r ),
.s_ack (bridge_ack ),
.s_err (bridge_err )
);
`else
assign dram_ack = 1'b1;
assign dram_err = 1'b0;
assign bridge_adr = 22'hxxxxxx;
assign bridge_cs = 1'b0;
assign bridge_we = 1'bx;
assign bridge_sel = 2'bxx;
assign bridge_dat_w = 16'hxxxx;
`endif // CTRL_SDRAM_BRIDGE
//// indicators ////
wire fifo_full;
indicators indicators(
.clk (clk_7 ),
.rst (~pll_locked ),
.track (track ),
.f_wr (floppy_fwr ),
.f_rd (floppy_frd ),
.h_wr (hd_fwr ),
.h_rd (hd_frd ),
.status ({rom_status, ram_status, reg_status, dram_status}),
.ctrl_status (ctrl_status ),
.sys_status (sys_status ),
.fifo_full (fifo_full),
.hex_0 (HEX0 ),
.hex_1 (HEX1 ),
.hex_2 (HEX2 ),
.hex_3 (HEX3 ),
.led_g (LEDG ),
.led_r (LEDR )
);
//// amiga clocks ////
amiga_clk amiga_clk (
.rst (pll_rst ), // async reset input
.clk_in (pll_in_clk ), // input clock ( 27.000000MHz)
.clk_114 (clk_114 ), // output clock c0 (114.750000MHz)
.clk_sdram (clk_sdram ), // output clock c2 (114.750000MHz, -146.25 deg)
.clk_28 (clk_28 ), // output clock c1 ( 28.687500MHz)
.clk_7 (clk_7 ), // output clock 7 ( 7.171875MHz)
.clk7_en (clk7_en ), // output clock 7 enable (on 28MHz clock domain)
.c1 (c1 ), // clk28m clock domain signal synchronous with clk signal
.c3 (c3 ), // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
.cck (cck ), // colour clock output (3.54 MHz)
.eclk (eclk ), // 0.709379 MHz clock enable output (clk domain pulse)
.locked (pll_locked ) // pll locked output
);
//// audio ////
audio_top audio_top (
.clk (clk_28 ), // 28MHz input clock
.rst_n (reset_out ), // active low reset (from sdram controller)
// config
.exchan (audio_lr_switch ), // switch audio left / right channel
.mix (audio_lr_mix ), // normal / centered mix (play some left channel on the right channel and vise-versa)
// audio shifter
.rdata (rdata ), // right channel sample data
.ldata (ldata ), // left channel sample data
.aud_bclk (AUD_BCLK ), // CODEC data clock
.aud_daclrck (AUD_DACLRCK ), // CODEC data clock
.aud_dacdat (AUD_DACDAT ), // CODEC data
.aud_xck (AUD_XCK ), // CODEC data clock
// I2C audio config
.i2c_sclk (I2C_SCLK ), // CODEC config clock
.i2c_sdat (I2C_SDAT ) // CODEC config data
);
//// TG68K main CPU ////
TG68K tg68k (
.clk (clk_114 ),
.reset (tg68_rst ),
.clkena_in (1'b1 ),
.IPL (tg68_IPL ),
.dtack (tg68_dtack ),
.vpa (1'b1 ),
.ein (1'b1 ),
.addr (tg68_adr ),
.data_read (tg68_dat_in ),
.data_write (tg68_dat_out ),
.as (tg68_as ),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.e ( ),
.vma ( ),
.wrd ( ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
.enaWRreg (tg68_enaWR ),
.fromram (tg68_cout ),
.ramready (tg68_cpuena ),
.cpu (cpu_config[1:0] ),
// .fastkick (cctrl[1]/*cpu_config[3]*/ ),
.memcfg (memcfg ),
.ramaddr (tg68_cad ),
.cpustate (tg68_cpustate ),
.nResetOut ( ),
.skipFetch ( ),
.cpuDMA (tg68_cdma ),
.ramlds (tg68_clds ),
.ramuds (tg68_cuds ),
.VBR_out (tg68_VBR_out )
);
/*
//// TG68 main CPU ////
TG68 tg68 (
.clk (clk_114 ),
.reset (tg68_rst ),
.clkena_in (1'b1 ),
.data_in (tg68_dat_in ),
.data_out (tg68_dat_out ),
.IPL (tg68_IPL ),
.dtack (tg68_dtack ),
.addr (tg68_adr ),
.as (tg68_as ),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.drive_data ( ),
.enaRDreg (tg68_ena7RD ),
.enaWRreg (tg68_ena7WR )
);
*/
//// sdram ////
sdram_ctrl sdram (
// sys
.sysclk (clk_114 ),
.c_7m (clk_7 ),
.reset_in (sdctl_rst ),
.cache_rst (tg68_rst ),
.reset_out (reset_out ),
.cache_ena (cctrl[0] ),
// sdram
.sdaddr (DRAM_ADDR ),
.sd_cs (sdram_cs ),
.ba (sdram_ba ),
.sd_we (DRAM_WE_N ),
.sd_ras (DRAM_RAS_N ),
.sd_cas (DRAM_CAS_N ),
.dqm (sdram_dqm ),
.sdata (DRAM_DQ ),
// host
.host_cs (bridge_cs ),
.host_adr ({2'b00, bridge_adr}),
.host_we (bridge_we ),
.host_bs (bridge_sel ),
.host_wdat (bridge_dat_w ),
.host_rdat (bridge_dat_r ),
.host_ack (bridge_ack ),
// chip
.chipAddr ({2'b00, ram_address[21:1]}),
.chipL (_ram_ble ),
.chipU (_ram_bhe ),
.chipRW (_ram_we ),
.chip_dma (_ram_oe ),
.chipWR (ram_data ),
.chipRD (ramdata_in ),
// cpu
.cpuAddr (tg68_cad[24:1] ),
.cpustate (tg68_cpustate ),
.cpuL (tg68_clds ),
.cpuU (tg68_cuds ),
.cpu_dma (tg68_cdma ),
.cpuWR (tg68_dat_out ),
.cpuRD (tg68_cout ),
.enaWRreg (tg68_enaWR ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
.cpuena (tg68_cpuena )
);
//// minimig top ////
Minimig1 minimig (
//m68k pins
.cpu_address (tg68_adr[23:1] ), // M68K address bus
.cpu_data (tg68_dat_in ), // M68K data bus
.cpudata_in (tg68_dat_out ), // M68K data in
._cpu_ipl (tg68_IPL ), // M68K interrupt request
._cpu_as (tg68_as ), // M68K address strobe
._cpu_uds (tg68_uds ), // M68K upper data strobe
._cpu_lds (tg68_lds ), // M68K lower data strobe
.cpu_r_w (tg68_rw ), // M68K read / write
._cpu_dtack (tg68_dtack ), // M68K data acknowledge
._cpu_reset (tg68_rst ), // M68K reset
.cpu_clk (clk_7 ), // M68K clock
.cpu_vbr (tg68_VBR_out ), // M68K VBR
//sram pins
.ram_data (ram_data ), // SRAM data bus
.ramdata_in (ramdata_in ), // SRAM data bus in
.ram_address (ram_address[21:1]), // SRAM address bus
._ram_bhe (_ram_bhe ), // SRAM upper byte select
._ram_ble (_ram_ble ), // SRAM lower byte select
._ram_we (_ram_we ), // SRAM write enable
._ram_oe (_ram_oe ), // SRAM output enable
//system pins
.rst_ext (rst_minimig ), // reset from ctrl block
.rst_out (minimig_rst_out ), // minimig reset status
.clk28m (clk_28 ), // output clock c1 ( 28.687500MHz)
.clk (clk_7 ), // output clock 7 ( 7.171875MHz)
.clk7_en (clk7_en ), // 7MHz clock enable
.c1 (c1 ), // clk28m clock domain signal synchronous with clk signal
.c3 (c3 ), // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
.cck (cck ), // colour clock output (3.54 MHz)
.eclk (eclk ), // 0.709379 MHz clock enable output (clk domain pulse)
//rs232 pins
.rxd (minimig_rxd ), // RS232 receive
.txd (minimig_txd ), // RS232 send
.cts (1'b0 ), // RS232 clear to send
.rts ( ), // RS232 request to send
//I/O
._joy1 (Joya ), // joystick 1 [fire2,fire,up,down,left,right] (default mouse port)
._joy2 (Joyb ), // joystick 2 [fire2,fire,up,down,left,right] (default joystick port)
.mouse_btn1 (key_3 ), // mouse button 1
.mouse_btn2 (key_2 ), // mouse button 2
._15khz (_15khz ), // scandoubler disable
.msdat (PS2_MDAT ), // PS2 mouse data
.msclk (PS2_MCLK ), // PS2 mouse clk
.kbddat (PS2_DAT ), // PS2 keyboard data
.kbdclk (PS2_CLK ), // PS2 keyboard clk
//host controller interface (SPI)
._scs (SPI_CS_N[3:1] ), // SPI chip select
.direct_sdi (SD_DAT ), // SD Card direct in
.sdi (SD_CMD ), // SPI data input
.sdo (sdo ), // SPI data output
.sck (SD_CLK ), // SPI clock
//video
._hsync (VGA_HS ), // horizontal sync
._vsync (VGA_VS ), // vertical sync
.red (VGA_R[9:6] ), // red
.green (VGA_G[9:6] ), // green
.blue (VGA_B[9:6] ), // blue
//audio
.left (audio_left ), // audio bitstream left
.right (audio_right ), // audio bitstream right
.ldata (ldata ), // left DAC data
.rdata (rdata ), // right DAC data
//user i/o
.cpu_config (cpu_config ), // CPU config
.memcfg (memcfg ), // memory config
.init_b (vsync ), // vertical sync for MCU (sync OSD update)
.fifo_full (fifo_full ),
// fifo / track display
.trackdisp (track ), // floppy track number
.secdisp ( ), // sector
.floppy_fwr (floppy_fwr ), // floppy fifo writing
.floppy_frd (floppy_frd ), // floppy fifo reading
.hd_fwr (hd_fwr ), // hd fifo writing
.hd_frd (hd_frd ) // hd fifo ading
);
endmodule
|
`timescale 1ns / 1ps
module testbench;
parameter SIZEIN = 16, SIZEOUT = 40;
reg clk, ce, rst;
reg signed [SIZEIN-1:0] a, b;
output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
output REF_overflow, overflow;
integer errcount = 0;
reg ERROR_FLAG = 0;
task clkcycle;
begin
#5;
clk = ~clk;
#10;
clk = ~clk;
#2;
ERROR_FLAG = 0;
if (REF_accum_out !== accum_out) begin
$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
errcount = errcount + 1;
ERROR_FLAG = 1;
end
if (REF_overflow !== overflow) begin
$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
errcount = errcount + 1;
ERROR_FLAG = 1;
end
#3;
end
endtask
initial begin
//$dumpfile("test_macc.vcd");
//$dumpvars(0, testbench);
#2;
clk = 1'b0;
ce = 1'b0;
a = 0;
b = 0;
rst = 1'b1;
repeat (10) begin
#10;
clk = 1'b1;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
#10;
clk = 1'b0;
end
rst = 1'b0;
repeat (10000) begin
clkcycle;
ce = 1; //$urandom & $urandom;
//rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
a = $urandom & ~(1 << (SIZEIN-1));
b = $urandom & ~(1 << (SIZEIN-1));
end
if (errcount == 0) begin
$display("All tests passed.");
$finish;
end else begin
$display("Caught %1d errors.", errcount);
$stop;
end
end
macc2 ref (
.clk(clk),
.ce(ce),
.rst(rst),
.a(a),
.b(b),
.accum_out(REF_accum_out),
.overflow(REF_overflow)
);
macc2_uut uut (
.clk(clk),
.ce(ce),
.rst(rst),
.a(a),
.b(b),
.accum_out(accum_out),
.overflow(overflow)
);
endmodule
|
//==========================================
// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
// Coder : Alex Claros F.
// Date : 15/May/2005.
// Notes : This implementation is based on the article
// 'Asynchronous FIFO in Virtex-II FPGAs'
// writen by Peter Alfke. This TechXclusive
// article can be downloaded from the
// Xilinx website. It has some minor modifications.
//=========================================
module minimac_asfifo
#(parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH))
//Reading port
(output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Writing port.
input wire [DATA_WIDTH-1:0] Data_in,
output reg Full_out,
input wire WriteEn_in,
input wire WClk,
input wire Clear_in);
/////Internal connections & variables//////
reg [DATA_WIDTH-1:0] Mem [FIFO_DEPTH-1:0];
wire [ADDRESS_WIDTH-1:0] pNextWordToWrite, pNextWordToRead;
wire EqualAddresses;
wire NextWriteAddressEn, NextReadAddressEn;
wire Set_Status, Rst_Status;
reg Status;
wire PresetFull, PresetEmpty;
//////////////Code///////////////
//Data ports logic:
//(Uses a dual-port RAM).
//'Data_out' logic:
assign Data_out = Mem[pNextWordToRead];
// always @ (posedge RClk)
// if (!PresetEmpty)
// Data_out <= Mem[pNextWordToRead];
// if (ReadEn_in & !Empty_out)
//'Data_in' logic:
always @ (posedge WClk)
if (WriteEn_in & !Full_out)
Mem[pNextWordToWrite] <= Data_in;
//Fifo addresses support logic:
//'Next Addresses' enable logic:
assign NextWriteAddressEn = WriteEn_in & ~Full_out;
assign NextReadAddressEn = ReadEn_in & ~Empty_out;
//Addreses (Gray counters) logic:
minimac_graycounter #(
.COUNTER_WIDTH( ADDRESS_WIDTH )
) GrayCounter_pWr (
.GrayCount_out(pNextWordToWrite),
.Enable_in(NextWriteAddressEn),
.Clear_in(Clear_in),
.Clk(WClk)
);
minimac_graycounter #(
.COUNTER_WIDTH( ADDRESS_WIDTH )
) GrayCounter_pRd (
.GrayCount_out(pNextWordToRead),
.Enable_in(NextReadAddressEn),
.Clear_in(Clear_in),
.Clk(RClk)
);
//'EqualAddresses' logic:
assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
//'Quadrant selectors' logic:
assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ^ pNextWordToRead[ADDRESS_WIDTH-2]);
assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^ pNextWordToRead[ADDRESS_WIDTH-1]) &
(pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
//'Status' latch logic:
always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
if (Rst_Status | Clear_in)
Status = 0; //Going 'Empty'.
else if (Set_Status)
Status = 1; //Going 'Full'.
//'Full_out' logic for the writing port:
assign PresetFull = Status & EqualAddresses; //'Full' Fifo.
always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
if (PresetFull)
Full_out <= 1;
else
Full_out <= 0;
//'Empty_out' logic for the reading port:
assign PresetEmpty = ~Status & EqualAddresses; //'Empty' Fifo.
always @ (posedge RClk, posedge PresetEmpty) //D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty)
Empty_out <= 1;
else
Empty_out <= 0;
endmodule
|
/*** Defines ***/
/*System because it's special*/
`define OPC_SYS 5'b110000;
module decode_32(
input[31:0] insn_in, //input instruction
input reset_in, //input reset line
input clk_in, //input clock
input[31:0] insn_pc_in, //input program counter address
input stall_in, //input stall signal
/*Operand output connections*/
output reg [4:0] reg_select_out, //output register bank select
output reg [4:0] rsa_out, //output of register a address
output reg [4:0] rsb_out, //output of register b address
output reg [4:0] rd_out, //output of destination register address
output reg [20:0] imm_out, //output of immediate value
//using largest immediate value
//size
/*Control Signals*/
output reg [3:0] aluop_out,
output reg jlnk_out,
output reg pc_change_rel_out,
output reg pc_change_abs_out,
output reg mem_read_out,
output reg mem_write_out,
/*Flag outputs*/
output reg nri_flg_out, //output of 'not real instruction' flag
output reg [1:0] branch_funct_out, //branch function; taken from the funct field
output reg stall_out,
/*System instruction signals*/
output reg memsync_out,
output reg syscall_out,
output reg pem_inc_req_out,
output reg pem_dec_req_out,
output reg [7:0] sysreg_addr_out, //for reading and writing to system registers
output reg [7:0] sysreg_data_out,
input [7:0] sysreg_data_in,
/* Misc. Outputs*/
output reg [31:0] insn_pc_out,
/*Co-processor connections*/
output reg [30:0] cp_insn_out
);
/* Pipeline information */
localparam PIPELINE_LENGTH = 5;
localparam PIPELINEL_2 = $clog2(PIPELINE_LENGTH);
/*Defining opcodes to make things easier*/
localparam OPC_INT = 5'b010011;
localparam OPC_IMM = 5'b010110;
localparam OPC_LI = 5'b010000;
localparam OPC_BRANCH = 5'b001101;
localparam OPC_JMP = 5'b001100;
localparam OPC_JLNK = 5'b000100;
localparam OPC_LD = 5'b011110;
localparam OPC_ST = 5'b011101;
/*Wire connections*/
wire[5:0] opcode_w;
wire[4:0] rsa_addr_w;
wire[4:0] rsb_addr_w;
wire[4:0] rd_addr_w;
wire[3:0] aluop_w;
/*Funct Variants*/
wire[1:0] funct_ld_w;
wire[1:0] funct_st_w;
wire[3:0] dsel_li_w;
wire[1:0] funct_b_w;
wire[7:0] funct_sys_w;
/*Immediate Variants*/
wire[11:0] imm_i_w;
wire[13:0] imm_ld_w;
wire[15:0] imm_li_w;
wire[13:0] imm_st_w;
wire[20:0] imm_j_w;
wire[13:0] imm_b_w;
wire[7:0] imm_sys_w;
/*OPCode generated signals*/
/*Resouce usage*/
wire use_alu_w;
wire is_cp_insn_w; //is coprocessor instruction
wire pc_change_w; //instruction can change the pc
wire mem_access_w;
wire pc_link_w; //jump that requires linking to ra
wire sys_insn_w;
/*secondary calculated resource usage*/
wire mem_read_req_w;
wire mem_write_req_w;
wire pc_abs_w;
wire pc_rel_w;
wire memsync_w;
/*ALU op signal selection*/
wire aluop_intsig_w; // integer/register operation field used
wire aluop_addsig_w; // fixed add operation
wire aluop_bsig_w; // branch operation decode value
/*Operand usage*/
wire use_rd_w;
wire use_rsa_w;
wire use_rsb_w;
wire use_imm_w;
wire [4:0] imm_sel_w;
/*Assignments*/
assign opcode_w = insn_in[31:26];
assign rsa_addr_w = insn_in[20:16];
assign rsb_addr_w = insn_in[15:11];
assign rd_addr_w = insn_in[25:21];
assign aluop_w = insn_in[3:0];
assign funct_ld_w = insn_in[15:14];
assign funct_st_w = insn_in[25:24];
assign dsel_li_w = insn_in[20:16];
assign funct_b_w = insn_in[1:0];
assign funct_sys_w = insn_in[15:8];
assign imm_i_w = insn_in[15:4];
assign imm_ld_w = insn_in[13:0];
assign imm_li_w = insn_in[15:0];
assign imm_st_w = {insn_in[13:11],insn_in[10:0]};
assign imm_j_w = {insn_in[25:21],insn_in[15:0]};
assign imm_b_w = {insn_in[25:21],insn_in[10:2]};
assign imm_sys_w = insn_in[7:0];
assign imm_sel_w = (use_imm_w) ?opcode_w[4:0] : 5'b0; //if using immediate, need to determine output
assign is_cp_insn_w = opcode_w[5];
assign pc_change_w = ~opcode_w[4];
assign mem_access_w = opcode_w[4] & opcode_w[3];
assign pc_link_w = ~(opcode_w[4] | opcode_w[3]);
assign sys_insn_w = is_cp_insn_w & opcode_w[4];
assign memsync_w = (sys_insn_w && ( (funct_sys_w & 8'h04) || (funct_sys_w & 8'b0 ) )); //if sync or syscall, need to sync memory
assign use_rd_w = (opcode_w[1] | opcode_w[0]) & (~opcode_w[2] | opcode_w[1]);
assign use_rsa_w = (opcode_w[2] | opcode_w[1]);
assign use_rsb_w = (opcode_w[2] & opcode_w[0]) | ( opcode_w[1] & opcode_w[0] );
assign use_imm_w = (opcode_w[2] | ~opcode_w[1]);
assign aluop_intsig_w = (opcode_w[4] & opcode_w[1]) & ~(opcode_w[5] & opcode_w[3]) & (opcode_w[2] ^ opcode_w[0]); //used for imm and int
assign aluop_addsig_w = pc_rel_w;//used for jump (relative)
assign aluop_bsig_w = (pc_change_w) & (use_rsb_w); //is a branch
/*Memory read/write signal creation*/
/*use_rsb has simpler gate usage, which is better than using use_rd for
* determining read or writes */
assign mem_write_req_w = (mem_access_w & use_rsb_w); //store instructions use rsb, not rd
assign mem_read_req_w = (mem_access_w & ~use_rsb_w); //load instructions use rd, not rsb
assign pc_rel_w = (pc_change_w & ( (opcode_w[2:0] && 3'b101) || (rsa_addr_w == (5'b0)) ) ); //not jr/jrl or branch
assign pc_abs_w = (pc_change_w & ~( (opcode_w[2:0] && 3'b101) || (rsa_addr_w == (5'b0)) ) );
/* Internal registers*/
reg [PIPELINEL_2 - 1 : 0] memstall_count; //counter for stalls in pipeline
/*** LOGIC SECTION ****/
always@(~reset_in or stall_in) begin //while in reset or stalling
reg_select_out <= 5'b0; //output register bank select
rsa_out <= 5'b0; //output of register a address
rsb_out <= 5'b0; //output of register b address
rd_out <= 5'b0; //output of destination register address
imm_out <= 21'b0; //output of immediate value
//using largest immediate value
//size
aluop_out <= 4'b0;
jlnk_out <= 1'b0;
pc_change_rel_out <= 1'b0;
pc_change_abs_out <= 1'b0;
mem_read_out <= 1'b0;
mem_write_out <= 1'b0;
nri_flg_out <= 1'b0; //output of 'not real instruction' flag
branch_funct_out <= 2'b0; //branch function; taken from the funct field
memsync_out <= 1'b0;
syscall_out <= 1'b0;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
sysreg_addr_out <= 8'b0;
sysreg_data_out <= 8'b0;
insn_pc_out <= 32'h0;
cp_insn_out <= 32'h0;
stall_out <= 1'b0;
end
always@(posedge clk_in, reset_in, ~stall_in) begin //make sure that reset has to be high for this to work
/*** Determining ALUOP value ***/
if (aluop_intsig_w) begin //uses ALUOP field
aluop_out = aluop_w;
end else if (aluop_addsig_w) begin //just add, so jumps
aluop_out = 4'b0000;
end else if (aluop_bsig_w) begin //branches, so need to decode the funct field
aluop_out = 4'b1100; //like compare insn, but does different things
end else begin
aluop_out = 4'b1111; //unused code, use as nop? need to define in documentation
end
/*Branch funct assignment*/
branch_funct_out = (aluop_bsig_w) ? (funct_b_w) : (2'b0);
/*Co-processor instruction output to co-processor decode*/
cp_insn_out <= (is_cp_insn_w) ? insn_in : 30'b0; //if is a co-processor instruction, output instruction to
//co-processor decoder
/*Memory access signal output*/
mem_write_out <= mem_write_req_w;
mem_read_out <= mem_read_req_w;
pc_change_rel_out <= pc_rel_w;
pc_change_abs_out <= pc_abs_w;
/*Register selection and outputs*/
if(imm_sel_w == OPC_LI) begin //determine which register bank to use, from DSEL
reg_select_out <= { 1'b0, dsel_li_w}; //lower 2 bits determine file, upper two bits determine signed, upper or lower 16 bits
end else if(sys_insn_w && ( funct_sys_w & (8'h02 ))) begin //if system instruction, need to check if accessing system registers, last two bits matter here
reg_select_out <= 5'b10000; //upper most bit is for accessing special purpose registers; maps to memory address to make 8 bit registers easier
end else begin //everything else should just use general purpose register file
reg_select_out <= 5'b0;
end
rsa_out <= (use_rsa_w) ? rsa_addr_w : 5'b0;
rsb_out <= (use_rsb_w) ? rsb_addr_w : 5'b0;
rd_out <= (use_rd_w ) ? rd_addr_w : 5'b0;
insn_pc_out <= insn_pc_in; //may need to alter this value, but unsure so leave it
/*** Selecting immediate values ***/
if(!is_cp_insn_w) begin
case (imm_sel_w) //figure out what immediate value to use
OPC_IMM: imm_out <= {9'b0 ,imm_i_w};
OPC_LD: imm_out <= {7'b0, imm_ld_w};
OPC_ST: imm_out <= {7'b0, imm_st_w};
OPC_LI: imm_out <= {6'b0, imm_li_w};
OPC_JMP: imm_out <= imm_j_w;
OPC_JLNK: imm_out <= imm_j_w;
OPC_BRANCH: imm_out <= {7'b0, imm_b_w};
default: imm_out <= 21'b0; //this may be redundant or cause errors, not sure yet
endcase
/*co processor instruction immediates; right now just system insn due to direct
* affects on main core pipeline */
end else if(opcode_w[5] & opcode_w[4] & ~(opcode_w[3] | opcode_w[2] | opcode_w[1] | opcode_w[0] ) )begin
/*just system instructions*/
imm_out <= imm_sys_w;
end else begin
imm_out <= 21'b0; //no immediate, default to 0's
end
/*System decoding*/
if( sys_insn_w) begin //if actually a system instruction
case (funct_sys_w)
8'h00: begin //system call
syscall_out <= 1'b1;
memsync_out <= 1'b0;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
end
// 8'h01: begin //system return
// end
8'h04: begin //memory sync
syscall_out <= 1'b0;
memsync_out <= 1'b1;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
stall_out <= 1'b1;
end
default: begin
syscall_out <= 1'b0;
memsync_out <= 1'b0;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
end
endcase
end
/* Ensure stall_out from memory sync doesn't make the pipeline get stuck */
if(memsync_w) begin
if(memstall_count > PIPELINE_LENGTH) begin
memstall_count <= 0;
memsync_out <= 1'b0;
end
else begin
memstall_count = memstall_count + 1;
end
end
end
endmodule
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// axis to vector
// A generic module to merge all axis 'data' signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_1_util_axis2vector
//
//--------------------------------------------------------------------------
`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_util_axis2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// inputs
input wire [C_TDATA_WIDTH-1:0] TDATA,
input wire [C_TDATA_WIDTH/8-1:0] TSTRB,
input wire [C_TDATA_WIDTH/8-1:0] TKEEP,
input wire TLAST,
input wire [C_TID_WIDTH-1:0] TID,
input wire [C_TDEST_WIDTH-1:0] TDEST,
input wire [C_TUSER_WIDTH-1:0] TUSER,
// outputs
output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA;
end else begin : no_gen_tdata
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB;
end else begin : no_gen_tstrb
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP;
end else begin : no_gen_tkeep
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST;
end else begin : no_gen_tlast
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID;
end else begin : no_gen_tid
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST;
end else begin : no_gen_tdest
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER;
end else begin : no_gen_tuser
// Do nothing
end
endgenerate
endmodule
`default_nettype wire
`endif
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define low_pos(x,y) `high_pos(x,y) - 63
`define high_pos(x,y) 1599 - 64*(5*y+x)
`define add_1(x) (x == 4 ? 0 : x + 1)
`define add_2(x) (x == 3 ? 0 : x == 4 ? 1 : x + 2)
`define sub_1(x) (x == 0 ? 4 : x - 1)
`define rot_up(in, n) {in[63-n:0], in[63:63-n+1]}
`define rot_up_1(in) {in[62:0], in[63]}
module round(in, round_const, out);
input [1599:0] in;
input [63:0] round_const;
output [1599:0] out;
wire [63:0] a[4:0][4:0];
wire [63:0] b[4:0];
wire [63:0] c[4:0][4:0], d[4:0][4:0], e[4:0][4:0], f[4:0][4:0], g[4:0][4:0];
genvar x, y;
/* assign "a[x][y][z] == in[w(5y+x)+z]" */
generate
for(y=0; y<5; y=y+1)
begin : L0
for(x=0; x<5; x=x+1)
begin : L1
assign a[x][y] = in[`high_pos(x,y) : `low_pos(x,y)];
end
end
endgenerate
/* calc "b[x] == a[x][0] ^ a[x][1] ^ ... ^ a[x][4]" */
generate
for(x=0; x<5; x=x+1)
begin : L2
assign b[x] = a[x][0] ^ a[x][1] ^ a[x][2] ^ a[x][3] ^ a[x][4];
end
endgenerate
/* calc "c == theta(a)" */
generate
for(y=0; y<5; y=y+1)
begin : L3
for(x=0; x<5; x=x+1)
begin : L4
assign c[x][y] = a[x][y] ^ b[`sub_1(x)] ^ `rot_up_1(b[`add_1(x)]);
end
end
endgenerate
/* calc "d == rho(c)" */
assign d[0][0] = c[0][0];
assign d[1][0] = `rot_up_1(c[1][0]);
assign d[2][0] = `rot_up(c[2][0], 62);
assign d[3][0] = `rot_up(c[3][0], 28);
assign d[4][0] = `rot_up(c[4][0], 27);
assign d[0][1] = `rot_up(c[0][1], 36);
assign d[1][1] = `rot_up(c[1][1], 44);
assign d[2][1] = `rot_up(c[2][1], 6);
assign d[3][1] = `rot_up(c[3][1], 55);
assign d[4][1] = `rot_up(c[4][1], 20);
assign d[0][2] = `rot_up(c[0][2], 3);
assign d[1][2] = `rot_up(c[1][2], 10);
assign d[2][2] = `rot_up(c[2][2], 43);
assign d[3][2] = `rot_up(c[3][2], 25);
assign d[4][2] = `rot_up(c[4][2], 39);
assign d[0][3] = `rot_up(c[0][3], 41);
assign d[1][3] = `rot_up(c[1][3], 45);
assign d[2][3] = `rot_up(c[2][3], 15);
assign d[3][3] = `rot_up(c[3][3], 21);
assign d[4][3] = `rot_up(c[4][3], 8);
assign d[0][4] = `rot_up(c[0][4], 18);
assign d[1][4] = `rot_up(c[1][4], 2);
assign d[2][4] = `rot_up(c[2][4], 61);
assign d[3][4] = `rot_up(c[3][4], 56);
assign d[4][4] = `rot_up(c[4][4], 14);
/* calc "e == pi(d)" */
assign e[0][0] = d[0][0];
assign e[0][2] = d[1][0];
assign e[0][4] = d[2][0];
assign e[0][1] = d[3][0];
assign e[0][3] = d[4][0];
assign e[1][3] = d[0][1];
assign e[1][0] = d[1][1];
assign e[1][2] = d[2][1];
assign e[1][4] = d[3][1];
assign e[1][1] = d[4][1];
assign e[2][1] = d[0][2];
assign e[2][3] = d[1][2];
assign e[2][0] = d[2][2];
assign e[2][2] = d[3][2];
assign e[2][4] = d[4][2];
assign e[3][4] = d[0][3];
assign e[3][1] = d[1][3];
assign e[3][3] = d[2][3];
assign e[3][0] = d[3][3];
assign e[3][2] = d[4][3];
assign e[4][2] = d[0][4];
assign e[4][4] = d[1][4];
assign e[4][1] = d[2][4];
assign e[4][3] = d[3][4];
assign e[4][0] = d[4][4];
/* calc "f = chi(e)" */
generate
for(y=0; y<5; y=y+1)
begin : L5
for(x=0; x<5; x=x+1)
begin : L6
assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]);
end
end
endgenerate
/* calc "g = iota(f)" */
generate
for(x=0; x<64; x=x+1)
begin : L60
if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63)
assign g[0][0][x] = f[0][0][x] ^ round_const[x];
else
assign g[0][0][x] = f[0][0][x];
end
endgenerate
generate
for(y=0; y<5; y=y+1)
begin : L7
for(x=0; x<5; x=x+1)
begin : L8
if(x!=0 || y!=0)
assign g[x][y] = f[x][y];
end
end
endgenerate
/* assign "out[w(5y+x)+z] == out_var[x][y][z]" */
generate
for(y=0; y<5; y=y+1)
begin : L99
for(x=0; x<5; x=x+1)
begin : L100
assign out[`high_pos(x,y) : `low_pos(x,y)] = g[x][y];
end
end
endgenerate
endmodule
`undef low_pos
`undef high_pos
`undef add_1
`undef add_2
`undef sub_1
`undef rot_up
`undef rot_up_1
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_wrlvl_off_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter nCK_PER_CLK = 2,
parameter CLK_PERIOD = 4,
parameter PO_INITIAL_DLY= 46,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter N_CTL_LANES = 3
)
(
input clk,
input rst,
input pi_fine_dly_dec_done,
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_s2_incdec_f,
output reg po_en_s2_f,
// Inc/dec Phaser_Out coarse delay line
output reg po_s2_incdec_c,
output reg po_en_s2_c,
// Completed adjusting delays for dq, dqs for tdqss
output po_ck_addr_cmd_delay_done,
// completed decrementing initialPO delays
output po_dec_done,
output phy_ctl_rdy_dly
);
localparam TAP_LIMIT = 63;
// PO fine delay tap resolution change by frequency. tCK > 2500, need
// twice the amount of taps
// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY;
// coarse delay tap is added DQ/DQS to meet the TDQSS specification.
localparam TDQSS_DLY = (tCK > 2500 )? 2: 1;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] po_delay_cnt_r;
reg po_cnt_inc;
reg cmd_delay_start_r1;
reg cmd_delay_start_r2;
reg cmd_delay_start_r3;
reg cmd_delay_start_r4;
reg cmd_delay_start_r5;
reg cmd_delay_start_r6;
reg po_delay_done;
reg po_delay_done_r1;
reg po_delay_done_r2;
reg po_delay_done_r3;
reg po_delay_done_r4;
reg pi_fine_dly_dec_done_r;
reg po_en_stg2_c;
reg po_en_stg2_f;
reg po_stg2_incdec_c;
reg po_stg2_f_incdec;
reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r;
reg [DQS_CNT_WIDTH:0] lane_cnt_po_r;
reg [5:0] delay_cnt_r;
always @(posedge clk) begin
cmd_delay_start_r1 <= #TCQ cmd_delay_start;
cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1;
cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2;
cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3;
cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4;
cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5;
pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done;
end
assign phy_ctl_rdy_dly = cmd_delay_start_r6;
// logic for decrementing initial fine delay taps for all PO
// Decrement done for add, ctrl and data phaser outs
assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || po_delay_done) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end else if (po_delay_cnt_r > 6'd0) begin
po_en_stg2_f <= #TCQ ~po_en_stg2_f;
end
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0))
// set all the PO delays to 31. Decrement from 46 to 31.
// Requirement comes from dqs_found logic
po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31);
else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0))
po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_po_r <= #TCQ 'd0;
else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1))
lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1;
always @(posedge clk)
if (rst || ~cmd_delay_start_r6 )
po_delay_done <= #TCQ 1'b0;
else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0))
po_delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
po_delay_done_r1 <= #TCQ po_delay_done;
po_delay_done_r2 <= #TCQ po_delay_done_r1;
po_delay_done_r3 <= #TCQ po_delay_done_r2;
po_delay_done_r4 <= #TCQ po_delay_done_r3;
end
// logic to select between all PO delays and data path delay.
always @(posedge clk) begin
po_s2_incdec_f <= #TCQ po_stg2_f_incdec;
po_en_s2_f <= #TCQ po_en_stg2_f;
end
// Logic to add 1/4 taps amount of delay to data path for tdqss.
// After all the initial PO delays are decremented the 1/4 delay will
// be added. Coarse delay taps will be added here .
// Delay added only to data path
assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r
: delay_done_r4;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin
po_stg2_incdec_c <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b0;
end else if (delay_cnt_r > 6'd0) begin
po_en_stg2_c <= #TCQ ~po_en_stg2_c;
end
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0))
delay_cnt_r <= #TCQ TDQSS_DLY;
else if ( po_en_stg2_c && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
always @(posedge clk)
if (rst)
lane_cnt_dqs_c_r <= #TCQ 'd0;
else if ( po_en_stg2_c && (delay_cnt_r == 6'd1))
lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1;
always @(posedge clk)
if (rst || ~pi_fine_dly_dec_done_r)
delay_done <= #TCQ 1'b0;
else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0))
delay_done <= #TCQ 1'b1;
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
always @(posedge clk) begin
po_s2_incdec_c <= #TCQ po_stg2_incdec_c;
po_en_s2_c <= #TCQ po_en_stg2_c;
ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration meta controller.
//
// Compute center of the window set up with with the ktap_left,
// ktap_right dance (hereafter "the window"). Also compute center of the
// edge (hereafter "the edge") to be aligned in the center
// of this window.
//
// Following the ktap_left/right dance, the to be centered edge is
// always left at the right edge of the window
// if SCANFROMRIGHT == 1, and the left edge otherwise.
//
// An assumption is the rise(0) case has a window wider than the noise on the
// edge. The noise case with the possibly narrow window
// will always be shifted by 90. And the fall(180) case is shifted by
// 90 twice. Hence when we start, we can assume the center of the
// edge is to the right/left of the the window center.
//
// The actual hardware does not necessarily monotonically appear to
// move the window centers. Because of noise, it is possible for the
// centered edge to move opposite the expected direction with a tap increment.
//
// This problem is solved by computing the absolute difference between
// the centers and the circular distance between the centers. These will
// be the same until the difference transits through zero. Then the circular
// difference will jump to almost the value of TAPSPERKCLK.
//
// The window center computation is done at 1/2 tap increments to maintain
// resolution through the divide by 2 for centering.
//
// There is a corner case of when the shift is greater than 180 degress. In
// this case the absolute difference and the circular difference will be
// unequal at the beginning of the alignment. This is solved by latching
// if they are equal at the end of each cycle. The completion must see
// that they were equal in the previous cycle, but are not equal in this cycle.
//
// Since the phaser out steps are of unknown size, it is possible to overshoot
// the center. The previous difference is recorded and if its less than the current
// difference, poc_backup is driven high.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_meta #
(parameter SCANFROMRIGHT = 0,
parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
mmcm_edge_detect_done, poc_backup, mmcm_lbclk_edge_aligned,
// Inputs
rst, clk, mmcm_edge_detect_rdy, run, run_polarity, run_end,
rise_lead_right, rise_trail_left, rise_lead_center,
rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,
use_noise_window, ktap_at_right_edge, ktap_at_left_edge
);
localparam NINETY = TAPSPERKCLK/4;
function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a,
input [1:0] b,
input integer base);
integer offset_ii;
begin
offset_ii = (a + b * NINETY) < base
? (a + b * NINETY)
: (a + b * NINETY - base);
offset = offset_ii[TAPCNTRWIDTH-1:0];
end
endfunction // offset
function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base-b;
end
endfunction // mod_sub
function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left,
input [TAPCNTRWIDTH-1:0] diff,
input integer base);
integer center_ii;
begin
center_ii = ({left, 1'b0} + diff < base * 2)
? {left, 1'b0} + diff + 32'h0
: {left, 1'b0} + diff - base * 2;
center = center_ii[TAPCNTRWIDTH:0];
end
endfunction // center
input rst;
input clk;
input mmcm_edge_detect_rdy;
wire reset_run_ends = rst || ~mmcm_edge_detect_rdy;
// This input used only for the SVA.
input [TAPCNTRWIDTH-1:0] run;
input run_end;
reg run_end_r, run_end_r1, run_end_r2, run_end_r3;
always @(posedge clk) run_end_r <= #TCQ run_end;
always @(posedge clk) run_end_r1 <= #TCQ run_end_r;
always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;
always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;
input run_polarity;
reg run_polarity_held_ns, run_polarity_held_r;
always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;
always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;
reg [1:0] run_ends_r;
reg [1:0] run_ends_ns;
always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;
always @(*) begin
run_ends_ns = run_ends_r;
if (reset_run_ends) run_ends_ns = 2'b0;
else case (run_ends_r)
2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};
2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};
endcase // case (run_ends_r)
end
reg done_r;
wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;
always @(posedge clk) done_r <= #TCQ done_ns;
output mmcm_edge_detect_done;
assign mmcm_edge_detect_done = done_r;
input [TAPCNTRWIDTH-1:0] rise_lead_right;
input [TAPCNTRWIDTH-1:0] rise_trail_left;
input [TAPCNTRWIDTH-1:0] rise_lead_center;
input [TAPCNTRWIDTH-1:0] rise_trail_center;
input [TAPCNTRWIDTH-1:0] rise_trail_right;
input [TAPCNTRWIDTH-1:0] rise_lead_left;
input [1:0] ninety_offsets;
wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;
wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);
wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;
always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;
always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;
wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] edge_diff_r;
always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;
wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] edge_center_r;
always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;
input use_noise_window;
wire [TAPCNTRWIDTH-1:0] left = use_noise_window ? rise_lead_left : rise_trail_left;
wire [TAPCNTRWIDTH-1:0] right = use_noise_window ? rise_trail_right : rise_lead_right;
wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] center_diff_r;
always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;
wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] window_center_r;
always @(posedge clk) window_center_r <= #TCQ window_center_ns;
localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;
wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};
wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};
wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center
? right_center - left_center
: right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;
reg [TAPCNTRWIDTH+1:0] diff_r;
always @(posedge clk) diff_r <= #TCQ diff_ns;
wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2
? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r
: diff_r;
reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;
always @(posedge clk) prev_r <= #TCQ prev_ns;
always @(*) prev_ns = done_ns ? diff_r : prev_r;
input ktap_at_right_edge;
input ktap_at_left_edge;
wire centering = !(ktap_at_right_edge || ktap_at_left_edge);
wire diffs_eq = abs_diff == diff_r;
reg diffs_eq_ns, diffs_eq_r;
always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);
always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;
reg edge_aligned_r;
reg prev_valid_ns, prev_valid_r;
always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;
always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;
wire indicate_alignment = ~rst && centering && done_ns;
wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);
always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;
reg poc_backup_r;
wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
output poc_backup;
assign poc_backup = poc_backup_r;
output mmcm_lbclk_edge_aligned;
assign mmcm_lbclk_edge_aligned = edge_aligned_r;
endmodule // mig_7series_v2_3_poc_meta
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
/**
* top_gpio_ovtv2: General Purpose I/0.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpio_ovtv2 (
OUT ,
OE_N ,
HLD_H_N ,
ENABLE_H ,
ENABLE_INP_H ,
ENABLE_VDDA_H ,
ENABLE_VDDIO ,
ENABLE_VSWITCH_H,
INP_DIS ,
VTRIP_SEL ,
HYS_TRIM ,
SLOW ,
SLEW_CTL ,
HLD_OVR ,
ANALOG_EN ,
ANALOG_SEL ,
ANALOG_POL ,
DM ,
IB_MODE_SEL ,
VINREF ,
PAD ,
PAD_A_NOESD_H ,
PAD_A_ESD_0_H ,
PAD_A_ESD_1_H ,
AMUXBUS_A ,
AMUXBUS_B ,
IN ,
IN_H ,
TIE_HI_ESD ,
TIE_LO_ESD ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
input OUT ;
input OE_N ;
input HLD_H_N ;
input ENABLE_H ;
input ENABLE_INP_H ;
input ENABLE_VDDA_H ;
input ENABLE_VDDIO ;
input ENABLE_VSWITCH_H;
input INP_DIS ;
input VTRIP_SEL ;
input HYS_TRIM ;
input SLOW ;
input [1:0] SLEW_CTL ;
input HLD_OVR ;
input ANALOG_EN ;
input ANALOG_SEL ;
input ANALOG_POL ;
input [2:0] DM ;
input [1:0] IB_MODE_SEL ;
input VINREF ;
inout PAD ;
inout PAD_A_NOESD_H ;
inout PAD_A_ESD_0_H ;
inout PAD_A_ESD_1_H ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
output IN ;
output IN_H ;
output TIE_HI_ESD ;
output TIE_LO_ESD ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
|
module mainlogic(rst_n,switch1,switch2,switch3,distance,speed,triangle,led1,led2,speed_control,voice,clk,out_num,angle_control);
input switch1,switch2,switch3,rst_n,clk;
input [9:0]distance,speed;
input [15:0]triangle;
output reg led1,led2,voice;
output reg[15:0]speed_control,angle_control;
parameter SPEED_LOW=0;
parameter SPEED_NORMAL=2000;
reg[9:0]timed;
wire[9:0]temp_time;
output reg[9:0]out_num;
div_rill u1(.a(distance),.b(speed),.shang(temp_time),.yushu());
always @(posedge clk or negedge rst_n)
begin
timed<=temp_time;
if(!rst_n)begin led1<=0;led2<=0;voice<=0;out_num<=0;speed_control<=SPEED_NORMAL; angle_control<=1500; timed<=10; end
else begin if(switch1==1'b1)begin out_num<=distance;end
else begin
if(switch2==1)begin out_num<=speed;end
else begin out_num<=0;end
end
// if(timed<=10'd30)begin speed_control<=(speed_control<=SPEED_LOW)?SPEED_LOW:(speed_control-50); led1<=1;end
// else begin led1<=0;end
if(distance<=60 && distance>=5)begin angle_control<=1000; speed_control<=SPEED_LOW; voice<=1; end
else begin angle_control<=1500;speed_control<=SPEED_NORMAL;end
if($signed(triangle)>16'sd10000)begin led2<=1;voice<=1;speed_control<=SPEED_LOW; end
else begin voice<=0;led2<=0; speed_control<=SPEED_NORMAL; end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_1_V
`define SKY130_FD_SC_LS__NAND3B_1_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_1 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_1 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_1_V
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always # (mintypmax_dly) reg_lvalue ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
#30;
$display("PASSED\n");
$finish;
end
always # (3:10:15) ;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_register_slice_v2_1_axi_register_slice,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "OpenSSD2_s00_regslice_0,axi_register_slice_v2_1_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "OpenSSD2_s00_regslice_0,axi_register_slice_v2_1_axi_register_slice,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=1,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_s00_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// $Id: rtr_flow_ctrl_input.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// flow control interface (receive side)
//==============================================================================
module rtr_flow_ctrl_input
(clk, reset, active, flow_ctrl_in, fc_event_valid_out,
fc_event_sel_out_ovc);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of VCs
parameter num_vcs = 4;
// select type of flow control
parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
parameter reset_type = `RESET_TYPE_ASYNC;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
-1;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
input clk;
input reset;
input active;
// incoming flow control data
input [0:flow_ctrl_width-1] flow_ctrl_in;
// flow control event valid
output fc_event_valid_out;
wire fc_event_valid_out;
// flow control event selector
output [0:num_vcs-1] fc_event_sel_out_ovc;
wire [0:num_vcs-1] fc_event_sel_out_ovc;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
generate
case(flow_ctrl_type)
`FLOW_CTRL_TYPE_CREDIT:
begin
wire cred_valid_q;
// NOTE: This register needs to be cleared after a credit has been
// received; consequently, we must extend the activity period
// accordingly. As creating a separate clock gating domain for a
// single register is liekly inefficient, this will probably mean
// that it will end up being free-running. If we could change
// things such that credits are transmitted using edge-based
// signaling (i.e., transitions), this could be avoided.
wire cred_active;
assign cred_active = active | cred_valid_q;
wire cred_valid_s;
assign cred_valid_s = flow_ctrl_in[0];
c_dff
#(.width(1),
.reset_type(reset_type))
cred_validq
(.clk(clk),
.reset(reset),
.active(cred_active),
.d(cred_valid_s),
.q(cred_valid_q));
assign fc_event_valid_out = cred_valid_q;
if(num_vcs > 1)
begin
wire [0:vc_idx_width-1] cred_vc_s, cred_vc_q;
assign cred_vc_s = flow_ctrl_in[1:vc_idx_width];
c_dff
#(.width(vc_idx_width),
.reset_type(reset_type))
cred_vcq
(.clk(clk),
.reset(1'b0),
.active(active),
.d(cred_vc_s),
.q(cred_vc_q));
c_decode
#(.num_ports(num_vcs))
fc_event_sel_out_ovc_dec
(.data_in(cred_vc_q),
.data_out(fc_event_sel_out_ovc));
end
else
assign fc_event_sel_out_ovc = 1'b1;
end
endcase
endgenerate
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : ram_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
module ram_frame_row_32x480 (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=9;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule |
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
Copyright 2016 Cornell University
Copyright 2017 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Websites: http://nuprl.org/html/verification/
http://nuprl.org/html/Nuprl2Coq
https://github.com/vrahli/NuprlInCoq
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export Eqdep.
Require Export FunctionalExtensionality.
Require Export terms.
(** printing # $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(** printing $ $\times$ #×# *)
(** printing & $\times$ #×# *)
(* begin hide *)
Inductive obool : Type :=
| otrue : obool
| ofalse : obool
| obseq : (nat -> obool) -> obool.
Definition bool2obool (b : bool) : obool :=
if b then otrue else ofalse.
Fixpoint oband (ob1 ob2 : obool) : obool :=
match ob1 with
| otrue => ob2
| ofalse => ob1
| obseq f =>
match ob2 with
| otrue => ob1
| ofalse => ob2
| obseq g => obseq (fun n => oband (f n) (g n))
end
end.
Fixpoint oball (l : list obool) : obool :=
match l with
| [] => otrue
| o :: l => oband o (oball l)
end.
Fixpoint term2otrue {o} (t : @NTerm o) : obool :=
match t with
| vterm _ => otrue
| sterm f => obseq (fun n => term2otrue (f n))
| oterm op bts => oball (map bterm2otrue bts)
end
with bterm2otrue {o} (bt : BTerm) : obool :=
match bt with
| bterm vars t => term2otrue t
end.
Fixpoint no_const {o} (t : @NTerm o) : bool :=
match t with
| vterm _ => true
| sterm _ => true (* what else can we do? *)
| oterm o bs => no_const_o o && ball (map no_const_b bs)
end
with no_const_b {o} (bt : @BTerm o) : bool :=
match bt with
| bterm _ t => no_const t
end.
Fixpoint no_oconst {o} (t : @NTerm o) : obool :=
match t with
| vterm _ => otrue
| sterm f => obseq (fun n => no_oconst (f n))
| oterm o bs => oband (bool2obool (no_const_o o)) (oball (map no_oconst_b bs))
end
with no_oconst_b {o} (bt : @BTerm o) : obool :=
match bt with
| bterm _ t => no_oconst t
end.
Lemma fold_nobnd {p} :
forall t : @NTerm p, bterm [] t = nobnd t.
Proof.
unfold nobnd; auto.
Qed.
Definition mk_ntseq {o} (f : @ntseq o) := sterm f.
Definition mk_integer {p} n : @NTerm p := oterm (Can (Nint n)) [].
Definition mk_nseq {p} f : @NTerm p := oterm (Can (Nseq f)) [].
Definition mk_nat {p} (n : nat) : @NTerm p := mk_integer (Z_of_nat n).
Definition mk_uni {p} n : @NTerm p := oterm (Can (NUni n)) [].
Definition mk_tuni {p} n : @NTerm p := oterm (NCan NTUni) [nobnd n].
Definition mk_minus {p} n : @NTerm p := oterm (NCan NMinus) [nobnd n].
Definition mk_base {p} : @NTerm p := oterm (Can NBase) [].
Definition mk_int {p} : @NTerm p := oterm (Can NInt) [].
Definition mk_atom {p} : @NTerm p := oterm (Can NAtom) [].
Definition mk_uatom {p} : @NTerm p := oterm (Can NUAtom) [].
Definition mk_pair {p} (a b : @NTerm p) := oterm (Can NPair) [nobnd a , nobnd b].
Definition mk_sup {p} (a b : @NTerm p) := oterm (Can NSup) [nobnd a , nobnd b].
Definition mk_refl {p} (a : @NTerm p) := oterm (Can NRefl) [nobnd a].
Definition mk_texc {p} (T1 T2 : @NTerm p) := oterm (Can NTExc) [nobnd T1, nobnd T2].
Definition mk_union {p} (T1 T2 : @NTerm p) := oterm (Can NUnion) [nobnd T1, nobnd T2].
Definition mk_eunion {p} (T1 T2 : @NTerm p) := oterm (Can NEUnion) [nobnd T1, nobnd T2].
Definition mk_union2 {p} (T1 T2 : @NTerm p) := oterm (Can NUnion2) [nobnd T1, nobnd T2].
Definition mk_approx {p} (a b : @NTerm p) := oterm (Can NApprox) [nobnd a , nobnd b].
Definition mk_cequiv {p} (a b : @NTerm p) := oterm (Can NCequiv) [nobnd a , nobnd b].
Definition mk_compute {p} (a b n : @NTerm p) := oterm (Can NCompute) [nobnd a , nobnd b , nobnd n].
Definition mk_free_from_atom {p} (a b c : @NTerm p) :=
oterm (Can NFreeFromAtom) [nobnd a,nobnd b,nobnd c].
Definition mk_efree_from_atom {p} (a b c : @NTerm p) :=
oterm (Can NEFreeFromAtom) [nobnd a,nobnd b,nobnd c].
Definition mk_free_from_atoms {p} (T t : @NTerm p) :=
oterm (Can NFreeFromAtoms) [nobnd T, nobnd t].
Definition mk_requality {p} (t1 t2 T : @NTerm p) :=
oterm (Can NREquality) [nobnd t1,nobnd t2,nobnd T].
Definition mk_tequality {p} (t1 t2 : @NTerm p) :=
oterm (Can NTEquality) [nobnd t1,nobnd t2].
Definition mk_can_test {p} test (a b c : @NTerm p) :=
oterm (NCan (NCanTest test)) [nobnd a,nobnd b,nobnd c].
Definition mk_ispair {p} := @mk_can_test p CanIspair.
Definition mk_isint {p} := @mk_can_test p CanIsint.
Definition mk_isinl {p} := @mk_can_test p CanIsinl.
Definition mk_isinr {p} := @mk_can_test p CanIsinr.
Definition mk_isaxiom {p} := @mk_can_test p CanIsaxiom.
Definition mk_islambda {p} := @mk_can_test p CanIslambda.
Definition mk_isatom {p} := @mk_can_test p CanIsatom.
Definition mk_isuatom {p} := @mk_can_test p CanIsuatom.
Definition mk_rec {p} (v : NVar) (T : @NTerm p) :=
oterm (Can NRec) [bterm [v] T].
Definition mk_image {p} (T f : @NTerm p) :=
oterm (Can NImage) [nobnd T, nobnd f].
Definition mk_function {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NFunction) [nobnd T1, bterm [v] T2].
Definition mk_product {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NProduct) [nobnd T1, bterm [v] T2].
Definition mk_set {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NSet) [nobnd T1, bterm [v] T2].
Definition mk_tunion {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NTUnion) [nobnd T1, bterm [v] T2].
Definition mk_quotient {p} (T1 : @NTerm p) (v1 v2 : NVar) (T2 : NTerm) :=
oterm (Can NQuotient) [nobnd T1, bterm [v1,v2] T2].
Definition mk_isect {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NIsect) [nobnd T1, bterm [v] T2].
Definition mk_disect {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NDIsect) [nobnd T1, bterm [v] T2].
Definition mk_eisect {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NEIsect) [nobnd T1, bterm [v] T2].
Definition mk_w {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NW) [nobnd T1, bterm [v] T2].
Definition mk_m {p} (T1 : @NTerm p) (v : NVar) (T2 : NTerm) :=
oterm (Can NM) [nobnd T1, bterm [v] T2].
Definition mk_pw {p}
(P : @NTerm p)
(ap : NVar) (A : NTerm)
(bp : NVar) (ba : NVar) (B : NTerm)
(cp : NVar) (ca : NVar) (cb : NVar) (C : NTerm)
(p : NTerm) :=
oterm (Can NPW)
[ nobnd P,
bterm [ap] A,
bterm [bp; ba] B,
bterm [cp; ca; cb] C,
nobnd p
].
Definition mk_pm {p}
(P : @NTerm p)
(ap : NVar) (A : NTerm)
(bp : NVar) (ba : NVar) (B : NTerm)
(cp : NVar) (ca : NVar) (cb : NVar) (C : NTerm)
(p : NTerm) :=
oterm (Can NPM)
[ nobnd P,
bterm [ap] A,
bterm [bp; ba] B,
bterm [cp; ca; cb] C,
nobnd p
].
Definition mk_spread {p} (t1 : @NTerm p) (u v : NVar) (t2 : NTerm) :=
oterm (NCan NSpread) [nobnd t1, bterm [u, v] t2].
Definition mk_dsup {p} (t1 : @NTerm p) (u v : NVar) (t2 : NTerm) :=
oterm (NCan NDsup) [nobnd t1, bterm [u, v] t2].
Definition mk_decide {p} (t : @NTerm p) (u : NVar) (t1 : NTerm) (v : NVar) (t2 : NTerm) :=
oterm (NCan NDecide) [nobnd t, bterm [u] t1, bterm [v] t2].
Definition mk_cbv {p} (t1 : @NTerm p) (v : NVar) (t2 : NTerm) :=
oterm (NCan NCbv) [nobnd t1, bterm [v] t2].
Definition mk_try {p} (t1 : @NTerm p) (a : @NTerm p) (v : NVar) (t2 : NTerm) :=
oterm (NCan NTryCatch) [nobnd t1, nobnd a, bterm [v] t2].
Definition mk_fresh {p} (v : NVar) (t : @NTerm p) :=
oterm (NCan NFresh) [bterm [v] t].
Definition mk_sleep {p} (t : @NTerm p) := oterm (NCan NSleep) [nobnd t].
Definition mk_pertype {p} (R : @NTerm p) :=
oterm (Can NEPertype) [nobnd R].
Definition mk_ipertype {p} (R : @NTerm p) :=
oterm (Can NIPertype) [nobnd R].
Definition mk_spertype {p} (R : @NTerm p) :=
oterm (Can NSPertype) [nobnd R].
Definition mk_partial {p} (T : @NTerm p) :=
oterm (Can NPartial) [nobnd T].
Definition mk_admiss {p} (T : @NTerm p) :=
oterm (Can NAdmiss) [nobnd T].
Definition mk_mono {p} (T : @NTerm p) :=
oterm (Can NMono) [nobnd T].
Definition mk_less {p} (a b c d : @NTerm p) :=
oterm (NCan (NCompOp CompOpLess)) [nobnd a, nobnd b, nobnd c, nobnd d].
Definition mk_int_eq {p} (a b c d : @NTerm p) :=
oterm (NCan (NCompOp CompOpEq)) [nobnd a, nobnd b, nobnd c, nobnd d].
Definition mk_atom_eq {p} (a b c d : @NTerm p) :=
oterm (NCan (NCompOp CompOpEq)) [nobnd a, nobnd b, nobnd c, nobnd d].
Definition mk_parallel {p} (a b : @NTerm p) := oterm (NCan NParallel) [nobnd a, nobnd b].
Definition mk_add {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpAdd)) [nobnd a, nobnd b].
Definition mk_mul {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpMul)) [nobnd a, nobnd b].
Definition mk_sub {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpSub)) [nobnd a, nobnd b].
Definition mk_div {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpDiv)) [nobnd a, nobnd b].
Definition mk_rem {p} (a b : @NTerm p) := oterm (NCan (NArithOp ArithOpRem)) [nobnd a, nobnd b].
Definition mk_omega {p} : @NTerm p := oterm (Can NOmega) [].
Definition mk_constant_p {p} (x : get_pconstP p) := oterm (Can (NConstP x)) [].
Definition mk_constant_t {p} (x : get_pconstT p) := oterm (Can (NConstT x)) [].
(*
Definition mk_esquash (R : NTerm) :=
oterm (Can NEsquash) [nobnd R].
*)
(* Picks a variable that is not in the set of free variables of a given term *)
Definition newvar {p} (t : @NTerm p) := fresh_var (free_vars t).
Fixpoint free_vars_list {p} (terms : list (@NTerm p)) :=
match terms with
| [] => []
| t :: ts => free_vars t ++ free_vars_list ts
end.
Definition newvarlst {p} (ts : list (@NTerm p)) := fresh_var (free_vars_list ts).
Definition newvars {p} (n : nat) (ts : list (@NTerm p)) :=
fresh_distinct_vars n (free_vars_list ts).
Definition newvars2 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
(v1, v2).
Definition newvars3 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
(v1, v2, v3).
Definition newvars4 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
let v4 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3]) in
(v1, v2, v3, v4).
Definition newvars5 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
let v4 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3]) in
let v5 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4]) in
(v1, v2, v3, v4, v5).
Definition newvars6 {p} (terms : list (@NTerm p)) :=
let v1 := newvarlst terms in
let v2 := newvarlst (terms ++ [mk_var v1]) in
let v3 := newvarlst (terms ++ [mk_var v1, mk_var v2]) in
let v4 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3]) in
let v5 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4]) in
let v6 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4, mk_var v5]) in
(v1, v2, v3, v4, v5, v6).
Definition newvars7 {p} (terms : list (@NTerm p)) :=
match newvars6 terms with
| (v1,v2,v3,v4,v5,v6) =>
let v7 := newvarlst (terms ++ [mk_var v1, mk_var v2, mk_var v3, mk_var v4, mk_var v5, mk_var v6]) in
(v1, v2, v3, v4, v5, v6, v7)
end.
(* --- non primitives --- *)
Definition mk_id {p} : @NTerm p := mk_lam nvarx (mk_var nvarx).
Definition mk_bottom {p} : @NTerm p := mk_fix mk_id.
Definition mk_bot {p} : @NTerm p := mk_bottom.
Definition mk_vbot {p} v : @NTerm p := mk_fix (mk_lam v (mk_var v)).
Definition mk_false {p} : @NTerm p := mk_approx mk_axiom mk_bot.
Definition mk_true {p} : @NTerm p := mk_approx mk_axiom mk_axiom.
Definition mk_void {p} : @NTerm p := mk_false.
Definition mk_unit {p} : @NTerm p := mk_true.
Definition mk_btrue {p} : @NTerm p := mk_inl mk_axiom.
Definition mk_bfalse {p} : @NTerm p := mk_inr mk_axiom.
Definition mk_ite {p} (a b c : @NTerm p) :=
mk_decide a (newvar b) b (newvar c) c.
Definition mk_tt {p} : @NTerm p := mk_btrue.
Definition mk_ff {p} : @NTerm p := mk_bfalse.
Definition mk_pi1 {p} (t : @NTerm p) := mk_spread t nvarx nvary (mk_var nvarx).
Definition mk_pi2 {p} (t : @NTerm p) := mk_spread t nvarx nvary (mk_var nvary).
Definition mk_outl {p} (t : @NTerm p) := mk_decide t nvarx (mk_var nvarx) nvary mk_bot.
Definition mk_outr {p} (t : @NTerm p) := mk_decide t nvarx mk_bot nvary (mk_var nvary).
Definition mk_halts {p} (t : @NTerm p) := mk_approx mk_axiom (mk_cbv t nvarx mk_axiom).
Definition mk_uall {p} := @mk_isect p.
Definition mk_all {p} := @mk_function p.
Definition mk_exists {p} := @mk_product p.
Definition mk_top {p} : @NTerm p := mk_isect mk_false nvarx mk_false.
Definition mk_member {p} (t T : @NTerm p) := mk_equality t t T.
Definition mk_rmember {p} (t T : @NTerm p) := mk_requality t t T.
Definition mk_type {p} (t : @NTerm p) := mk_tequality t t.
Definition mk_bool {p} : @NTerm p := mk_union mk_unit mk_unit.
Definition mk_apply2 {p} (R x y : @NTerm p) := mk_apply (mk_apply R x) y.
Definition mk_apply3 {p} (f a b c : @NTerm p) :=
mk_apply (mk_apply (mk_apply f a) b) c.
Definition mk_apply4 {p} (f a b c d : @NTerm p) :=
mk_apply (mk_apply (mk_apply (mk_apply f a) b) c) d.
Definition mk_squash {p} (T : @NTerm p) := mk_image T (mk_lam nvarx mk_axiom).
Definition mk_lam3 {p} v1 v2 v3 (b : @NTerm p) := mk_lam v1 (mk_lam v2 (mk_lam v3 b)).
Definition mk_less_than {p} (a b : @NTerm p) := mk_less a b mk_true mk_false.
Definition mk_or {p} (A B : @NTerm p) := mk_union A B.
Definition mk_eor {p} (A B : @NTerm p) := mk_eunion A B.
Definition mk_zero {p} : @NTerm p := mk_nat 0.
Definition mk_one {p} : @NTerm p := mk_nat 1.
Definition mk_two {p} : @NTerm p := mk_nat 2.
(*
Definition mk_fun (T1 : NTerm) (T2 : NTerm) :=
oterm (Can NFunction) [nobnd T1, bterm [v] T2].
Definition mk_product (T1 : NTerm) (v : NVar) (T2 : NTerm) :=
oterm (Can NProduct) [nobnd T1, bterm [v] T2].
*)
(* --- foldings --- *)
Lemma fold_integer {p} :
forall i, oterm (Can (Nint i)) [] = @mk_integer p i.
Proof. sp. Qed.
Lemma fold_nseq {p} :
forall f, oterm (Can (Nseq f)) [] = @mk_nseq p f.
Proof. sp. Qed.
Lemma fold_ntseq {o} :
forall (f : @ntseq o), sterm f = mk_ntseq f.
Proof. sp. Qed.
Lemma fold_token {p} :
forall s, oterm (Can (NTok s)) [] = @mk_token p s.
Proof. sp. Qed.
Lemma fold_utoken {p} :
forall u, oterm (Can (NUTok u)) [] = @mk_utoken p u.
Proof. sp. Qed.
Lemma fold_atom {p} :
oterm (Can NAtom) [] = @mk_atom p.
Proof. sp. Qed.
Lemma fold_uatom {p} :
oterm (Can NUAtom) [] = @mk_uatom p.
Proof. sp. Qed.
Lemma fold_lam {p} :
forall v (b : @NTerm p), oterm (Can NLambda) [bterm [v] b] = mk_lam v b.
Proof. sp. Qed.
Lemma fold_apply {p} :
forall (a b : @NTerm p), oterm (NCan NApply) [ nobnd a, nobnd b ] = mk_apply a b.
Proof. sp. Qed.
Lemma fold_eapply {p} :
forall (a b : @NTerm p), oterm (NCan NEApply) [ nobnd a, nobnd b ] = mk_eapply a b.
Proof. sp. Qed.
(*
Lemma fold_apseq {p} :
forall f (a : @NTerm p), oterm (NCan (NApseq f)) [ nobnd a ] = mk_apseq f a.
Proof. sp. Qed.
*)
Lemma fold_decide {p} :
forall (d : @NTerm p) x f y g,
oterm (NCan NDecide) [nobnd d, bterm [x] f, bterm [y] g]
= mk_decide d x f y g.
Proof. sp. Qed.
Lemma fold_spread {p} :
forall (a : @NTerm p) x y b,
oterm (NCan NSpread) [nobnd a, bterm [x,y] b]
= mk_spread a x y b.
Proof. sp. Qed.
Lemma fold_dsup {p} :
forall (a : @NTerm p) x y b,
oterm (NCan NDsup) [nobnd a, bterm [x,y] b]
= mk_dsup a x y b.
Proof. sp. Qed.
Lemma fold_approx {p} :
forall (a b : @NTerm p), oterm (Can NApprox) [ nobnd a, nobnd b ] = mk_approx a b.
Proof. sp. Qed.
Lemma fold_cequiv {p} :
forall (a b : @NTerm p), oterm (Can NCequiv) [ nobnd a, nobnd b ] = mk_cequiv a b.
Proof. sp. Qed.
Lemma fold_pertype {p} :
forall (a : @NTerm p), oterm (Can NEPertype) [ nobnd a ] = mk_pertype a.
Proof. sp. Qed.
Lemma fold_ipertype {p} :
forall (a : @NTerm p), oterm (Can NIPertype) [ nobnd a ] = mk_ipertype a.
Proof. sp. Qed.
Lemma fold_spertype {p} :
forall (a : @NTerm p), oterm (Can NSPertype) [ nobnd a ] = mk_spertype a.
Proof. sp. Qed.
Lemma fold_tuni {p} :
forall (a : @NTerm p), oterm (NCan NTUni) [ nobnd a ] = mk_tuni a.
Proof. sp. Qed.
Lemma fold_minus {p} :
forall (a : @NTerm p), oterm (NCan NMinus) [ nobnd a ] = mk_minus a.
Proof. sp. Qed.
Lemma fold_admiss {p} :
forall (a : @NTerm p), oterm (Can NAdmiss) [ nobnd a ] = mk_admiss a.
Proof. sp. Qed.
Lemma fold_mono {p} :
forall (a : @NTerm p), oterm (Can NMono) [ nobnd a ] = mk_mono a.
Proof. sp. Qed.
Lemma fold_partial {p} :
forall (a : @NTerm p), oterm (Can NPartial) [ nobnd a ] = mk_partial a.
Proof. sp. Qed.
(*
Lemma fold_esquash :
forall a, oterm (Can NEsquash) [ nobnd a ] = mk_esquash a.
Proof.
sp.
Qed.
*)
Lemma fold_compute {p} :
forall (a b n : @NTerm p),
oterm (Can NCompute) [ nobnd a, nobnd b, nobnd n ]
= mk_compute a b n.
Proof. sp. Qed.
Lemma fold_equality {p} :
forall (a b c : @NTerm p),
oterm (Can NEquality) [ nobnd a, nobnd b, nobnd c ]
= mk_equality a b c.
Proof. sp. Qed.
Lemma fold_requality {p} :
forall (a b c : @NTerm p),
oterm (Can NREquality) [ nobnd a, nobnd b, nobnd c ]
= mk_requality a b c.
Proof. sp. Qed.
Lemma fold_free_from_atom {p} :
forall (a b c : @NTerm p),
oterm (Can NFreeFromAtom) [ nobnd a, nobnd b, nobnd c ]
= mk_free_from_atom a b c.
Proof. sp. Qed.
Lemma fold_efree_from_atom {p} :
forall (a b c : @NTerm p),
oterm (Can NEFreeFromAtom) [ nobnd a, nobnd b, nobnd c ]
= mk_efree_from_atom a b c.
Proof. sp. Qed.
Lemma fold_free_from_atoms {p} :
forall (a b : @NTerm p),
oterm (Can NFreeFromAtoms) [ nobnd a, nobnd b ]
= mk_free_from_atoms a b.
Proof. sp. Qed.
Lemma fold_tequality {p} :
forall (a b : @NTerm p),
oterm (Can NTEquality) [ nobnd a, nobnd b ]
= mk_tequality a b.
Proof. sp. Qed.
Lemma fold_base {p} :
oterm (Can NBase) [] = @mk_base p.
Proof. sp. Qed.
Lemma fold_member {p} :
forall (t T : @NTerm p),
mk_equality t t T = mk_member t T.
Proof. sp. Qed.
Lemma fold_rmember {p} :
forall (t T : @NTerm p),
mk_requality t t T = mk_rmember t T.
Proof. sp. Qed.
Lemma fold_mk_type {p} :
forall (t : @NTerm p),
mk_tequality t t = mk_type t.
Proof. sp. Qed.
Lemma fold_cbv {p} :
forall (t1 : @NTerm p) v t2,
oterm (NCan NCbv) [nobnd t1, bterm [v] t2] = mk_cbv t1 v t2.
Proof. sp. Qed.
Lemma fold_try {p} :
forall (t1 : @NTerm p) a v t2,
oterm (NCan NTryCatch) [nobnd t1, nobnd a, bterm [v] t2] = mk_try t1 a v t2.
Proof. sp. Qed.
Lemma fold_fresh {p} :
forall v (t : @NTerm p),
oterm (NCan NFresh) [bterm [v] t] = mk_fresh v t.
Proof. sp. Qed.
Lemma fold_sleep {p} :
forall (t : @NTerm p), oterm (NCan NSleep) [nobnd t] = mk_sleep t.
Proof. sp. Qed.
Lemma fold_halts {p} :
forall (t : @NTerm p),
mk_approx mk_axiom (mk_cbv t nvarx mk_axiom) = mk_halts t.
Proof. sp. Qed.
Lemma fold_function {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NFunction) [nobnd t1, bterm [v] t2] = mk_function t1 v t2.
Proof. sp. Qed.
Lemma fold_isect {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NIsect) [nobnd t1, bterm [v] t2] = mk_isect t1 v t2.
Proof.
sp.
Qed.
Lemma fold_disect {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NDIsect) [nobnd t1, bterm [v] t2] = mk_disect t1 v t2.
Proof.
sp.
Qed.
Lemma fold_eisect {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NEIsect) [nobnd t1, bterm [v] t2] = mk_eisect t1 v t2.
Proof.
sp.
Qed.
Lemma fold_w {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NW) [nobnd t1, bterm [v] t2] = mk_w t1 v t2.
Proof.
sp.
Qed.
Lemma fold_m {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NM) [nobnd t1, bterm [v] t2] = mk_m t1 v t2.
Proof.
sp.
Qed.
Lemma fold_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
oterm (Can NPW)
[nobnd P,
bterm [ap] A,
bterm [bp,ba] B,
bterm [cp,ca,cb] C,
nobnd p
]
= mk_pw P ap A bp ba B cp ca cb C p.
Proof.
sp.
Qed.
Lemma fold_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
oterm (Can NPM)
[nobnd P,
bterm [ap] A,
bterm [bp,ba] B,
bterm [cp,ca,cb] C,
nobnd p
]
= mk_pm P ap A bp ba B cp ca cb C p.
Proof.
sp.
Qed.
Lemma fold_product {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NProduct) [nobnd t1, bterm [v] t2] = mk_product t1 v t2.
Proof.
sp.
Qed.
Lemma fold_set {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NSet) [nobnd t1, bterm [v] t2] = mk_set t1 v t2.
Proof.
sp.
Qed.
Lemma fold_texc {p} :
forall (t1 t2 : @NTerm p),
oterm (Can NTExc) [nobnd t1, nobnd t2] = mk_texc t1 t2.
Proof.
sp.
Qed.
Lemma fold_union {p} :
forall (t1 : @NTerm p) t2,
oterm (Can NUnion) [nobnd t1, nobnd t2] = mk_union t1 t2.
Proof.
sp.
Qed.
Lemma fold_eunion {p} :
forall (t1 : @NTerm p) t2,
oterm (Can NEUnion) [nobnd t1, nobnd t2] = mk_eunion t1 t2.
Proof.
sp.
Qed.
Lemma fold_union2 {p} :
forall (t1 : @NTerm p) t2,
oterm (Can NUnion2) [nobnd t1, nobnd t2] = mk_union2 t1 t2.
Proof.
sp.
Qed.
Lemma fold_tunion {p} :
forall (t1 : @NTerm p) v t2,
oterm (Can NTUnion) [nobnd t1, bterm [v] t2] = mk_tunion t1 v t2.
Proof.
sp.
Qed.
Lemma fold_quotient {p} :
forall (t1 : @NTerm p) v1 v2 t2,
oterm (Can NQuotient) [nobnd t1, bterm [v1;v2] t2] = mk_quotient t1 v1 v2 t2.
Proof.
sp.
Qed.
Lemma fold_pair {p} :
forall (a b : @NTerm p), oterm (Can NPair) [ nobnd a, nobnd b ] = mk_pair a b.
Proof.
sp.
Qed.
Lemma fold_ispair {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIspair)) [ nobnd a, nobnd b, nobnd c ]
= mk_ispair a b c.
Proof. sp. Qed.
Lemma fold_isinl {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsinl)) [ nobnd a, nobnd b, nobnd c ]
= mk_isinl a b c.
Proof. sp. Qed.
Lemma fold_isinr {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsinr)) [ nobnd a, nobnd b, nobnd c ]
= mk_isinr a b c.
Proof. sp. Qed.
Lemma fold_isaxiom {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsaxiom)) [ nobnd a, nobnd b, nobnd c ]
= mk_isaxiom a b c.
Proof. sp. Qed.
Lemma fold_isint {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIsint)) [ nobnd a, nobnd b, nobnd c ]
= mk_isint a b c.
Proof. sp. Qed.
Lemma fold_islambda {p} :
forall (a b c : @NTerm p),
oterm (NCan (NCanTest CanIslambda)) [ nobnd a, nobnd b, nobnd c ]
= mk_islambda a b c.
Proof. sp. Qed.
Lemma fold_sup {p} :
forall (a b : @NTerm p), oterm (Can NSup) [ nobnd a, nobnd b ] = mk_sup a b.
Proof. sp. Qed.
Lemma fold_refl {p} :
forall (a : @NTerm p), oterm (Can NRefl) [ nobnd a ] = mk_refl a.
Proof. sp. Qed.
Lemma fold_exception {p} :
forall a (e : @NTerm p), oterm Exc [ nobnd a, nobnd e ] = mk_exception a e.
Proof. sp. Qed.
Lemma fold_fix {p} :
forall (f : @NTerm p), oterm (NCan NFix) [ nobnd f ] = mk_fix f.
Proof. sp. Qed.
Lemma fold_parallel {p} :
forall (a b : @NTerm p), oterm (NCan NParallel) [ nobnd a, nobnd b ] = mk_parallel a b.
Proof. sp. Qed.
(* ------ SIMPLE CHECKERS ON TERMS ------ *)
Definition ispair {p} (t : @NTerm p) :=
match t with
| (| a , b |) => true
| _ => false
end.
(* ------ SIMPLE OPERATORS ON TERMS ------ *)
(*
Fixpoint depth (t : NTerm) : nat :=
match t with
| vterm _ => 1
| oterm op bterms => lsum map depth_bterm bterms
end
with depth_bterm (lv : list NVar) (nt : NTerm) :=
match bt with
| bterm lv nt => depth nt
end.
*)
(* ------ INDUCTION ON TERMS ------ *)
(* Some of the ordinal stuff comes from
https://github.com/martijnvermaat/infinitary-rewriting-coq/blob/master/Ordinal.v
*)
Definition IsTypeOpid {p} (opid : @Opid p) : bool :=
match opid with
| Can (NUni _) => true
| Can NEquality => true
| Can NREquality => true
| Can NTEquality => true
| Can NInt => true
| Can NAtom => true
| Can NBase => true
| Can NFunction => true
| Can NProduct => true
| Can NSet => true
| Can NQuotient => true
| Can NIsect => true
| Can NDIsect => true
| Can NEIsect => true
| Can NW => true
| Can NEPertype => true
| Can NIPertype => true
| Can NSPertype => true
| Can NPartial => true
| Can NTExc => true
| Can NUnion => true
| Can NEUnion => true
| Can NUnion2 => true
| Can NTUnion => true
| Can NApprox => true
| Can NCequiv => true
| Can NCompute => true
| Can NRec => true
| Can NImage => true
| _ => false
end.
Definition IsType {p} (t : @NTerm p) : bool :=
match t with
| vterm _ => false
| sterm _ => false
| oterm opid _ => IsTypeOpid opid
end.
Lemma num_bvars_on_bterm {p} :
forall l (n : @NTerm p),
num_bvars (bterm l n) = length l.
Proof.
unfold num_bvars; simpl; sp.
Qed.
Definition no_vars_like {o} (t : @NTerm o) :=
closed t # noutokens t.
Definition no_vars_like_b {o} (t : @NTerm o) : bool :=
nullb (free_vars t) && nullb (get_utokens t).
Fixpoint wft {o} (t : @NTerm o) : obool :=
match t with
| vterm _ => otrue
| sterm f => obseq (fun n => oband (bool2obool (no_vars_like_b (f n))) (wft (f n)))
| oterm op bts =>
oband (bool2obool (beq_list eq_nat_dec (map (num_bvars) bts) (OpBindings op)))
(oball (map wftb bts))
end
with wftb {p} (bt : BTerm) : obool :=
match bt with
| bterm vars t => wft t
end.
Definition wf_term {p} (t : @NTerm p) := wft t = term2otrue t.
Lemma fold_wf_term {o} : forall t : @NTerm o, wft t = term2otrue t <=> wf_term t.
Proof. sp. Qed.
Definition wf_bterm {p} (b : @BTerm p) := wftb b = bterm2otrue b.
Lemma wf_term_proof_irrelevance {p} :
forall (t : @NTerm p),
forall x y : wf_term t,
x = y.
Proof.
intros.
apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : wf_term ?t , H2 : wf_term ?t |- _ ] =>
pose proof (wf_term_proof_irrelevance t H2 H1) as h; subst
end : pi.
Definition wf_term_extract {p} :=
fun (t : @NTerm p) (x : wf_term t) =>
match x return (x = match x with
| eq_refl => eq_refl (wft t)
end)
with
| eq_refl => eq_refl eq_refl
end.
(*
Definition wf_term_extract1 :=
fun (t : NTerm) (x : wf_term t) =>
match x in _ = b return match b with
| true => x = eq_refl (wft t)
end
with
| eq_refl => eq_refl eq_refl
end.
Lemma wf_term_extract2 :
forall t : NTerm,
forall x : wf_term t,
x = eq_refl (wft t).
*)
(*Lemma yyy : forall A (x : A) (pf : x = x), pf = eq_refl x.
Lemma xxx : forall t (x : wft t = true), x = eq_refl (wft t).*)
Lemma oball_ofalse :
forall (l : list obool),
oball l = ofalse -> LIn ofalse l.
Proof.
induction l; introv h; allsimpl; ginv.
destruct a; allsimpl; ginv.
remember (oball l) as obl; destruct obl; ginv.
Qed.
Lemma term2otrue_not_ofalse {o} :
forall (t : @NTerm o),
term2otrue t = ofalse -> False.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; introv h; ginv.
apply oball_ofalse in h.
rw in_map_iff in h; exrepnd.
destruct a as [l t].
applydup ind in h1; tcsp.
Qed.
Lemma bterm2otrue_not_ofalse {o} :
forall (b : @BTerm o),
bterm2otrue b = ofalse -> False.
Proof.
introv e.
destruct b as [l t]; allsimpl.
apply term2otrue_not_ofalse in e; sp.
Qed.
Lemma wft_otrue_implies_term2otrue_otrue {o} :
forall (t : @NTerm o),
wft t = otrue
-> term2otrue t = otrue.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; introv e; ginv.
remember (beq_list eq_nat_dec (map num_bvars bs) (OpBindings op)) as b.
destruct b; allsimpl; ginv.
clear Heqb.
clear op.
induction bs; allsimpl; ginv.
destruct a as [l t]; allsimpl.
autodimp IHbs hyp.
{ introv q h; apply (ind nt lv); auto. }
remember (wft t) as ob1; symmetry in Heqob1; destruct ob1; allsimpl; ginv.
- pose proof (ind t l) as h; repeat (autodimp h hyp).
rw h; simpl; auto.
- remember (oball (map wftb bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv.
Qed.
Lemma oball_map_bterm2otrue_not_ofalse {o} :
forall (bs : list (@BTerm o)),
oball (map bterm2otrue bs) = ofalse -> False.
Proof.
induction bs; allsimpl; introv e; ginv.
remember (bterm2otrue a) as ob1; symmetry in Heqob1.
destruct ob1; allsimpl; ginv.
- apply bterm2otrue_not_ofalse in Heqob1; sp.
- remember (oball (map bterm2otrue bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv.
Qed.
Lemma oball_map_wftb_otrue_implies {o} :
forall (bs : list (@BTerm o)),
oball (map wftb bs) = otrue
-> oball (map bterm2otrue bs) = otrue.
Proof.
induction bs; allsimpl; introv e; auto.
destruct a as [l t]; allsimpl.
remember (wft t) as ob; symmetry in Heqob; destruct ob; allsimpl; ginv; tcsp.
- rw @wft_otrue_implies_term2otrue_otrue; auto.
- remember (oball (map wftb bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv; tcsp.
Qed.
Lemma wft_obseq_implies_term2otrue_obseq {o} :
forall (t : @NTerm o) (f : nat -> obool),
wft t = obseq f
-> {g : nat -> obool & term2otrue t = obseq g}.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; introv e; ginv.
- eexists; eauto.
- remember (beq_list eq_nat_dec (map num_bvars bs) (OpBindings op)) as b.
destruct b; allsimpl; ginv.
clear Heqb.
clear op.
revert dependent f.
induction bs; allsimpl; introv e; ginv.
destruct a as [l t]; allsimpl.
autodimp IHbs hyp.
{ introv i; apply (ind nt lv); auto. }
remember (wft t) as ob1; symmetry in Heqob1; destruct ob1; allsimpl; ginv.
+ pose proof (IHbs f) as q; clear IHbs.
autodimp q hyp; exrepnd.
applydup @wft_otrue_implies_term2otrue_otrue in Heqob1; rw Heqob0; simpl.
eexists; eauto.
+ remember (oball (map wftb bs)) as ob2; symmetry in Heqob2.
destruct ob2; allsimpl; ginv.
* clear IHbs.
pose proof (ind t l) as h; clear ind; autodimp h hyp.
pose proof (h f) as q; clear h; autodimp q hyp; exrepnd.
rw q0; simpl.
rw @oball_map_wftb_otrue_implies; auto.
eexists; eauto.
* pose proof (IHbs o1) as q; clear IHbs; autodimp q hyp; exrepnd.
rw q0.
pose proof (ind t l) as h; clear ind; autodimp h hyp.
apply h in Heqob1; exrepnd; clear h.
rw Heqob0; simpl.
eexists; eauto.
Qed.
Lemma oband_of_obseq :
forall s1 s2,
oband (obseq s1) (obseq s2)
= obseq (fun n => oband (s1 n) (s2 n)).
Proof.
sp.
Qed.
Fixpoint isotrue (o : obool) : Prop :=
match o with
| otrue => True
| ofalse => False
| obseq f => forall n, isotrue (f n)
end.
Lemma isotrue_oband :
forall o1 o2, isotrue (oband o1 o2) <=> (isotrue o1 # isotrue o2).
Proof.
induction o1 as [|?|f ind]; introv; split; intro isob; allsimpl; try dands; tcsp.
- introv.
destruct o2; allsimpl; tcsp.
pose proof (isob n) as h.
apply ind in h; sp.
- destruct o2; allsimpl; tcsp.
introv.
pose proof (isob n) as h.
apply ind in h; sp.
- repnd.
destruct o2; allsimpl; tcsp.
introv.
apply ind; dands; auto.
Qed.
Lemma isotrue_oball :
forall l o, isotrue (oball l) -> LIn o l -> isotrue o.
Proof.
induction l; introv ib io; allsimpl; tcsp.
allrw @isotrue_oband; repnd.
repndors; subst; auto.
Qed.
Lemma isotrue_oball_iff :
forall l, isotrue (oball l) <=> (forall o, LIn o l -> isotrue o).
Proof.
induction l; split; introv h; introv; allsimpl; tcsp.
- intro q.
allrw @isotrue_oband; repnd.
repndors; subst; auto.
rw IHl in h.
apply h in q; auto.
- apply isotrue_oband; dands; auto.
apply IHl; introv i.
apply h; sp.
Qed.
Lemma isotrue_oball_map_wftb_implies {o} :
forall (bs : list (@BTerm o)) b,
isotrue (oball (map wftb bs))
-> LIn b bs
-> isotrue (wftb b).
Proof.
introv ibo ib.
eapply isotrue_oball;[exact ibo|].
rw in_map_iff.
eexists; dands; eauto.
Qed.
Lemma isotrue_term2otrue {o} :
forall (t : @NTerm o), isotrue (term2otrue t).
Proof.
nterm_ind t as [v|f inf|op bs ind] Case; allsimpl; auto.
apply isotrue_oball_iff; introv i.
allrw in_map_iff; exrepnd; subst.
destruct a as [l t]; allsimpl.
eapply ind; eauto.
Qed.
Lemma isotrue_oball_map_bterm2otrue {o} :
forall (bs : list (@BTerm o)),
isotrue (oball (map bterm2otrue bs)).
Proof.
introv.
eapply isotrue_oball_iff; introv i.
allrw in_map_iff; exrepnd; subst.
destruct a; simpl.
apply isotrue_term2otrue.
Qed.
Lemma isotrue_bool2obool :
forall b, isotrue (bool2obool b) -> b = true.
Proof.
introv h; destruct b; allsimpl; auto.
Qed.
Lemma isotrue_wft_implies_eq_term2otrue {o} :
forall (t : @NTerm o), isotrue (wft t) -> wft t = term2otrue t.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv iso; allsimpl; auto.
- Case "sterm".
f_equal.
apply functional_extensionality.
introv.
pose proof (iso x) as h.
allrw isotrue_oband; repnd.
apply isotrue_bool2obool in h0; rw h0; simpl.
apply ind; auto.
- Case "oterm".
allrw isotrue_oband; repnd.
apply isotrue_bool2obool in iso0.
rw iso0; simpl.
f_equal.
apply eq_maps; introv i.
destruct x as [l t]; allsimpl.
allrw isotrue_oball_iff.
eapply ind; eauto.
apply iso.
rw in_map_iff; eexists; eauto.
Qed.
Lemma oball_map_wftb_eq_otrue_implies {o} :
forall (bs : list (@BTerm o)) b,
oball (map wftb bs) = oball (map bterm2otrue bs)
-> LIn b bs
-> wftb b = bterm2otrue b.
Proof.
introv e i.
pose proof (isotrue_oball_map_wftb_implies bs b) as h.
repeat (autodimp h hyp);[rw e;apply isotrue_oball_map_bterm2otrue|].
destruct b; allsimpl.
apply isotrue_wft_implies_eq_term2otrue; auto.
Qed.
Lemma no_vars_like_b_true_iff {o} :
forall (t : @NTerm o), no_vars_like_b t = true <=> (closed t # noutokens t).
Proof.
introv; unfold no_vars_like_b, closed, noutokens.
rw @andb_eq_true.
allrw @assert_nullb.
allrw @null_iff_nil; sp.
Qed.
Lemma implies_no_vars_like_b_true {o} :
forall (t : @NTerm o),
closed t
-> noutokens t
-> no_vars_like_b t = true.
Proof.
introv cl nu.
apply no_vars_like_b_true_iff; sp.
Qed.
Lemma nt_wf_eq {p} :
forall (t : @NTerm p),
nt_wf t <=> wf_term t.
Proof.
unfold wf_term.
nterm_ind t as [|f ind|o lbt ind] Case; simpl; intros.
- Case "vterm".
split; sp.
- Case "sterm".
split_iff SCase.
+ SCase "->".
introv wf.
inversion wf as [|g imp|]; subst.
f_equal.
apply functional_extensionality.
introv.
pose proof (imp x) as h; clear imp; repnd.
rw @implies_no_vars_like_b_true; simpl; auto.
apply ind; auto.
+ SCase "<-".
introv wf.
constructor; introv.
inversion wf as [w]; clear wf.
apply equal_f with (x := n) in w.
remember (no_vars_like_b (f n)) as nv; symmetry in Heqnv; destruct nv; allsimpl.
* apply no_vars_like_b_true_iff in Heqnv; repnd; dands; auto.
apply ind in w; dands; auto.
* symmetry in w; apply term2otrue_not_ofalse in w; sp.
- Case "oterm".
split_iff SCase.
+ SCase "->"; intro w.
inversion w as [|?|? ? imp e]; subst.
allrw.
rewrite beq_list_refl; simpl.
f_equal.
apply eq_maps; introv i.
destruct x as [l t]; simpl.
applydup ind in i.
applydup imp in i.
inversion i1 as [? ? ntw]; subst; clear i1.
apply i0 in ntw; auto.
+ SCase "<-".
introv q.
remember (beq_list eq_nat_dec (map num_bvars lbt) (OpBindings o)) as b.
symmetry in Heqb.
destruct b; allsimpl; tcsp;
[|symmetry in q; apply oball_ofalse in q; allrw in_map_iff; exrepnd;
destruct a; allsimpl;
symmetry in q0; apply term2otrue_not_ofalse in q0; sp].
constructor; tcsp.
{ introv i.
destruct l as [l t].
constructor.
applydup ind in i.
apply i0.
eapply oball_map_wftb_eq_otrue_implies in q;[|exact i].
allsimpl; auto. }
apply assert_beq_list in Heqb; auto.
Qed.
Lemma nt_wf_implies {p} :
forall (t : @NTerm p), nt_wf t -> wf_term t.
Proof.
sp; apply nt_wf_eq; sp.
Qed.
Lemma wf_term_eq {p} :
forall (t : @NTerm p), wf_term t <=> nt_wf t.
Proof.
intro; generalize (nt_wf_eq t); sp.
symm; auto.
Qed.
Lemma bt_wf_eq {p} :
forall (bt : @BTerm p), bt_wf bt <=> wf_bterm bt.
Proof.
sp; split; intro w.
inversion w; subst; unfold wf_bterm; simpl.
fold (wf_term nt).
apply wf_term_eq; auto.
destruct bt; allunfold (@wf_bterm p); allsimpl.
fold (wf_term n) in w.
constructor.
apply nt_wf_eq; auto.
Qed.
(*
Inductive nt_wfb (t:NTerm) : bool :=
match t with
| vterm _ => true
| bterm _ rt => nt_wfb rt
| oterm o lnt : (eq map (num_bvars) lnt OpBindings o).
*)
Definition closedb {p} (t : @NTerm p) : bool := nullb (free_vars(t)).
Definition closed_bt {p} (bt : @BTerm p) := free_vars_bterm bt = [].
(* end hide *)
Definition isprogram_bt {p} (bt : @BTerm p) := closed_bt bt # bt_wf bt.
(** Our definition [isprog] below is is logically equivalent to [isprogram],
but unlike [isprogram], it is easy to prove that
for any [t], all members(proofs) of [isprog t] are equal.
An interested reader can look at the lemma
%\coqexternalref{UIP\_dec}
{http://coq.inria.fr/distrib/8.4pl2/stdlib/Coq.Logic.Eqdep\_dec}
{\coqdocdefinition{UIP\_dec}}% from that standard library.
As mentioned before, clicking on the lemma name in
the previous sentence should open
the corresponding webpage of the Coq standard library.
Instead, one can also look at the lemma [isprog_eq] below and
safely ignore these technicalites.
*)
Definition isprog {p} (t : @NTerm p) :=
assert (nullb (free_vars t)) # wf_term t.
(* begin hide *)
Definition isprog_bt {p} (bt : @BTerm p) :=
assert (nullb (free_vars_bterm bt)) # wf_bterm bt.
Definition isprog_vars {p} (vs : list NVar) (t : @NTerm p) :=
assert (sub_vars (free_vars t) vs) # wf_term t.
Lemma closed_nt {p} :
forall (op : @Opid p) bts,
closed (oterm op bts)
<=>
forall bt, LIn bt bts -> closed_bt bt.
Proof.
sp; unfold closed, closed_bt; simpl; trw flat_map_empty; split; sp.
Qed.
Lemma closed_nt0 {p} :
forall (o : @Opid p) nt, closed (oterm o [bterm [] nt]) -> closed nt.
Proof.
intros. unfold closed in H. simpl in H. apply app_eq_nil in H. repnd.
clears_last. rewrite remove_var_nil in H0. auto.
Qed.
Lemma closed_null_free_vars {p} :
forall (t : @NTerm p),
closed t <=> null (free_vars t).
Proof.
unfold closed; sp.
trw null_iff_nil; sp.
Qed.
Lemma isprog_proof_irrelevance {p} :
forall (t : @NTerm p),
forall x y : isprog t,
x = y.
Proof.
intros.
destruct x, y.
f_equal; apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : isprog ?t , H2 : isprog ?t |- _ ] =>
pose proof (isprog_proof_irrelevance t H2 H1) as h; subst
end : pi.
Lemma isprog_vars_proof_irrelevance {p} :
forall (t : @NTerm p) vs,
forall x y : isprog_vars vs t,
x = y.
Proof.
intros.
destruct x, y.
f_equal; apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : isprog_vars ?vs ?t , H2 : isprog_vars ?vs ?t |- _ ] =>
pose proof (isprog_vars_proof_irrelevance t vs H2 H1) as h; subst
end : pi.
Ltac irr_step :=
match goal with
| [ H1 : isprog ?a, H2 : isprog ?a |- _ ] =>
assert (H2 = H1) by apply isprog_proof_irrelevance; subst
| [ H1 : isprog_vars ?vs ?a, H2 : isprog_vars ?vs ?a |- _ ] =>
assert (H2 = H1) by apply isprog_vars_proof_irrelevance; subst
end.
Ltac irr := repeat irr_step.
Ltac abs_bool2obool n :=
match goal with
| [ H : context[bool2obool ?b] |- _ ] => remember b as n
end.
Lemma assert_true_iff : assert true <=> True.
Proof.
unfold assert; simpl; split; sp.
Qed.
Lemma assert_false_iff : assert false <=> False.
Proof.
unfold assert; simpl; split; sp.
Qed.
Lemma isprogram_eq {p} :
forall (t : @NTerm p),
isprogram t <=> isprog t.
Proof.
unfold isprog, isprogram.
nterm_ind t as [v|f ind|op bs ind] Case; simpl; intros.
- Case "vterm".
rw assert_false_iff.
rw @wf_term_eq.
unfold closed; simpl.
split; intro h; repnd; dands; tcsp.
- Case "sterm".
rw @wf_term_eq.
rw assert_true_iff.
split; intro h; repnd; dands; allsimpl; tcsp.
- Case "oterm".
rw @wf_term_eq.
rw @assert_nullb.
allrw null_iff_nil.
split_iff SCase; tcsp.
Qed.
Lemma isprogram_implies {p} :
forall (t : @NTerm p), isprogram t -> isprog t.
Proof.
sp; apply isprogram_eq; sp.
Qed.
Lemma isprog_implies {p} :
forall t : @NTerm p, isprog t -> isprogram t.
Proof.
sp; apply isprogram_eq; sp.
Qed.
(* end hide *)
Lemma isprog_eq {p} :
forall (t : @NTerm p), isprog t <=> isprogram t.
Proof.
intro; symm; apply isprogram_eq; auto.
Qed.
(* begin hide *)
Lemma isprogram_bt_eq {p} :
forall (bt : @BTerm p),
isprogram_bt bt <=> isprog_bt bt.
Proof.
introv; unfold isprogram_bt, isprog_bt, closed_bt; split; intro h;
repnd; dands; auto.
- allrw; simpl.
apply assert_true_iff; auto.
- apply bt_wf_eq; auto.
- allrw assert_nullb.
allrw null_iff_nil; auto.
- apply bt_wf_eq; auto.
Qed.
Lemma isprog_vars_eq {p} :
forall (t : @NTerm p) vs,
isprog_vars vs t <=> subvars (free_vars t) vs # nt_wf t.
Proof.
unfold isprog_vars; sp.
rw @nt_wf_eq; sp.
Qed.
Lemma isprog_vars_if_isprog {p} :
forall vs (t : @NTerm p), isprog t -> isprog_vars vs t.
Proof.
introv ip.
rw @isprog_vars_eq.
rw @isprog_eq in ip.
destruct ip; sp.
allunfold @closed; allrw; sp.
Qed.
Lemma isprog_vars_app_l {p} :
forall (t : @NTerm p) vs1 vs2,
isprog_vars vs2 t
-> isprog_vars (vs1 ++ vs2) t.
Proof.
sp; alltrewrite (@isprog_vars_eq p); sp.
alltrewrite subvars_eq.
apply subset_app_l; sp.
Qed.
Definition areprograms {p} (ts : list (@NTerm p)) :=
forall t, LIn t ts -> isprogram t.
Lemma areprograms_nil {p} : @areprograms p [].
Proof.
unfold areprograms; simpl; sp.
Qed.
Lemma areprograms_snoc {p} :
forall (t : @NTerm p) ts,
areprograms (snoc ts t) <=> areprograms ts # isprogram t.
Proof.
unfold areprograms; sp; split; sp; try (apply_hyp; rw in_snoc; sp).
alltrewrite in_snoc; sp; subst; sp.
Qed.
Lemma areprograms_cons {p} :
forall (t : @NTerm p) ts, areprograms (t :: ts) <=> isprogram t # areprograms ts.
Proof.
unfold areprograms; sp; simpl; split; sp; subst; sp.
Qed.
Lemma areprograms_app {p} :
forall (ts1 ts2 : list (@NTerm p)),
areprograms (ts1 ++ ts2) <=> areprograms ts1 # areprograms ts2.
Proof.
unfold areprograms; sp; split; sp.
apply_hyp; rw in_app_iff; sp.
apply_hyp; rw in_app_iff; sp.
alltrewrite in_app_iff; sp.
Qed.
Lemma isprogram_vterm {p} :
forall v, @isprogram p (vterm v) <=> False.
Proof.
unfold isprogram, closed; simpl; sp; split; sp.
Qed.
(*
Ltac repnd :=
repeat match goal with
| [ H : _ # _ |- _ ] =>
let name := fresh H in destruct H as [name H]
| [ H : _ # _ |- _ ] =>
let name := fresh H in destruct H as [name H]
end.
*)
Theorem isprogram_ot_iff {p} :
forall (o : @Opid p) bts,
isprogram (oterm o bts)
<=>
(map num_bvars bts = OpBindings o
# forall bt, LIn bt bts -> isprogram_bt bt).
Proof.
intros. sp_iff Case.
- Case "->".
intros Hisp.
unfold isprogram in Hisp. repnd.
inverts Hisp0 as Hflat. inverts Hisp.
split;auto. intros bt Hin.
unfold isprogram_bt.
rw flat_map_empty in Hflat.
apply_in_hyp pp; sp.
- Case "<-".
intros eq; destruct eq as [Hmap Hstclose].
unfold isprogram, closed.
split; try (constructor); auto;
try (simpl; apply flat_map_empty);
intros a ain;
apply Hstclose in ain; inversion ain; sp.
Qed.
Theorem nt_wf_ot_implies {p} :
forall lv (o : @Opid p) nt1 bts,
nt_wf (oterm o bts)
-> LIn (bterm lv nt1) bts
-> nt_wf nt1.
Proof. intros ? ? ? ? Hwf Hin. inverts Hwf as Hwf Hmap.
assert (bt_wf (bterm lv nt1)) as Hbf by (apply Hwf; auto).
inverts Hbf. auto.
Qed.
Lemma newvar_prop {p} :
forall (t : @NTerm p), ! LIn (newvar t) (free_vars t).
Proof.
unfold newvar; sp.
allapply fresh_var_not_in; sp.
Qed.
Lemma newvar_not_in_free_vars {p} :
forall (t : @NTerm p),
! LIn nvarx (free_vars t)
-> newvar t = nvarx.
Proof.
sp.
unfold newvar.
apply fresh_var_nvarx; sp.
Qed.
Lemma newvar_prog {p} :
forall (t : @NTerm p),
isprog t
-> newvar t = nvarx.
Proof.
sp.
unfold newvar.
apply isprog_eq in H.
inversion H.
unfold closed in H0.
rewrite H0; sp.
Qed.
Definition mk_vsubtype {p} (A : @NTerm p) v B := mk_member mk_id (mk_function A v B).
Definition mk_subtype {p} (A : @NTerm p) B := mk_vsubtype A (newvar B) B.
(* non-dependent function type *)
Definition mk_fun {p} (A B : @NTerm p) := mk_function A (newvar B) B.
(* non-dependent uniform function type *)
Definition mk_ufun {p} (A B : @NTerm p) := mk_isect A (newvar B) B.
(* non-dependent extensional uniform function type *)
Definition mk_eufun {p} (A B : @NTerm p) := mk_eisect A (newvar B) B.
(* non-dependent product type *)
Definition mk_prod {p} (A B : @NTerm p) := mk_product A (newvar B) B.
Definition mk_subtype_rel {p} (A B : @NTerm p) := mk_member mk_id (mk_fun A B).
Definition mk_iff {p} (a b : @NTerm p) := mk_prod (mk_fun a b) (mk_fun b a).
Definition mk_not {p} (P : @NTerm p) := mk_fun P mk_void.
Definition mk_le {p} (a b : @NTerm p) := mk_not (mk_less_than b a).
Definition mk_tnat {p} : @NTerm p := mk_set mk_int nvary (mk_le mk_zero (mk_var nvary)).
Definition mk_nat_sub {p} n : @NTerm p :=
mk_set mk_tnat nvarx (mk_less_than (mk_var nvarx) n).
Definition mk_dec {p} (P : @NTerm p) := mk_or P (mk_not P).
Definition mk_plus1 {p} n : @NTerm p := mk_add n mk_one.
(** A value is a program with a canonical operator *)
Inductive isvalue {p} : @NTerm p -> Type :=
| isv_can :
forall t,
isprogram t
-> iscan t
-> isvalue t.
Hint Constructors isvalue.
Inductive isovalue {p} : @NTerm p -> Prop :=
| isovl :
forall t,
nt_wf t
-> iscan t
-> isovalue t.
Hint Constructors isovalue.
Lemma isvalue_closed {p} :
forall (t : @NTerm p), isvalue t -> closed t.
Proof.
introv isv; inversion isv; allunfold @isprogram; sp.
Qed.
Lemma isvalue_program {p} :
forall (t : @NTerm p), isvalue t -> isprogram t.
Proof.
introv isv; inversion isv; sp.
Qed.
Lemma isvalue_mk_lam {p} :
forall v (b : @NTerm p), isprog_vars [v] b -> isvalue (mk_lam v b).
Proof.
intros; repeat constructor; simpl; sp; subst.
rw @isprog_vars_eq in H; sp.
unfold closed; simpl; rewrite app_nil_r.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
allrw subvars_eq.
allrw subset_singleton_r.
unfold subset in H0; allsimpl.
apply_in_hyp pp; sp.
rw @isprog_vars_eq in H; sp.
Qed.
Lemma isvalue_mk_int {p} : @isvalue p mk_int.
Proof.
repeat constructor; simpl; sp.
Qed.
Theorem isprogram_int {p} : @isprogram p mk_int.
Proof.
repeat constructor; simpl; sp.
Qed.
Theorem isprog_int {p} : @isprog p mk_int.
Proof.
repeat constructor.
Qed.
Theorem wf_int {p} : @wf_term p mk_int.
Proof.
sp.
Qed.
Lemma isprogram_mk_integer {p} : forall n : Z, @isprogram p (mk_integer n).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isprog_mk_integer' {p} : forall n : Z, @isprog p (mk_integer n).
Proof.
repeat constructor.
Qed.
Definition isprog_mk_integer {p} : forall n : Z, @isprog p (mk_integer n)
:= fun _ => (eq_refl,eq_refl).
Lemma isvalue_mk_integer {p} : forall n : Z, @isvalue p (mk_integer n).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isovalue_mk_integer {p} : forall n : Z, @isovalue p (mk_integer n).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma wf_mk_integer' {p} : forall n : Z, @wf_term p (mk_integer n).
Proof.
sp.
Qed.
Definition wf_mk_integer {p} : forall n : Z, @wf_term p (mk_integer n)
:= fun _ => eq_refl.
Lemma isprogram_mk_nat {p} : forall n : nat, @isprogram p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isprogram_mk_integer.
Qed.
Lemma isprog_mk_nat' {p} : forall n : nat, @isprog p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isprog_mk_integer.
Qed.
Definition isprog_mk_nat {p} : forall n : nat, @isprog p (mk_nat n)
:= fun _ => (eq_refl,eq_refl).
Lemma isvalue_mk_nat {p} : forall n : nat, @isvalue p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isvalue_mk_integer.
Qed.
Lemma isovalue_mk_nat {p} : forall n : nat, @isovalue p (mk_nat n).
Proof.
unfold mk_nat.
intros; apply isovalue_mk_integer.
Qed.
Lemma wf_mk_nat' {p} : forall n : nat, @wf_term p (mk_nat n).
Proof.
sp.
Qed.
Definition wf_mk_nat {p} : forall n : nat, @wf_term p (mk_nat n)
:= fun _ => eq_refl.
Lemma isprogram_mk_nseq {p} : forall f : nseq, @isprogram p (mk_nseq f).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isprog_mk_nseq {p} : forall f : nseq, @isprog p (mk_nseq f).
Proof.
repeat constructor.
Qed.
Lemma isvalue_mk_nseq {p} : forall f : nseq, @isvalue p (mk_nseq f).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_token {p} : forall s : String.string, @isvalue p (mk_token s).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_utoken {p} : forall u : get_patom_set p, @isvalue p (mk_utoken u).
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_atom {p} : @isvalue p mk_atom.
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isvalue_uatom {p} : @isvalue p mk_uatom.
Proof.
repeat constructor. intros; allsimpl; sp.
Qed.
Lemma isprogram_mk_uni {p} : forall n : nat, @isprogram p (mk_uni n).
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma isprog_mk_uni {p} : forall n : nat, @isprog p (mk_uni n).
Proof.
repeat constructor.
Qed.
Lemma isvalue_mk_uni {p} : forall n : nat, @isvalue p (mk_uni n).
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma wf_mk_uni {p} : forall n : nat, @wf_term p (mk_uni n).
Proof.
sp.
Qed.
Lemma wf_mk_var {p} : forall v, @wf_term p (mk_var v).
Proof.
sp.
Qed.
Lemma isprogram_axiom {p} : @isprogram p mk_axiom.
Proof.
repeat constructor; simpl; sp.
Qed.
Theorem isprog_axiom {p} : @isprog p mk_axiom.
Proof.
repeat constructor.
Qed.
Theorem isprog_bottom {p} : @isprog p mk_bottom.
Proof.
repeat constructor.
Qed.
Lemma isprogram_bottom {p} : @isprogram p mk_bottom.
Proof.
rw @isprogram_eq. repeat constructor.
Qed.
Theorem isvalue_axiom {p} : @isvalue p mk_axiom.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem wf_axiom {p} : @wf_term p mk_axiom.
Proof.
sp.
Qed.
Theorem isprogram_base {p} : @isprogram p mk_base.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem isprog_base {p} : @isprog p mk_base.
Proof.
repeat constructor.
Qed.
Lemma isvalue_base {p} : @isvalue p mk_base.
Proof.
repeat constructor; simpl; sp.
Qed.
Lemma wf_base {p} : @wf_term p mk_base.
Proof.
sp.
Qed.
Hint Immediate isvalue_mk_int.
Hint Immediate isprogram_int.
Hint Immediate isprog_int.
Hint Immediate wf_int : wf.
Hint Immediate isvalue_axiom.
Hint Immediate isprogram_axiom.
Hint Immediate isprog_axiom.
Hint Immediate isprog_bottom.
Hint Immediate isprogram_bottom.
Hint Immediate wf_axiom : wf.
Hint Immediate isvalue_base.
Hint Immediate isprogram_base.
Hint Immediate isprog_base.
Hint Immediate wf_base : wf.
Theorem wf_pertype {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_pertype a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Lemma isprogram_pertype {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_pertype a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_pertype; sp.
Qed.
Lemma isprogram_pertype_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_pertype a).
Proof.
intros; split; intro i.
apply isprogram_pertype; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
inversion w as [|?|o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_pertype {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_pertype a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_pertype; auto.
Qed.
Theorem wf_partial {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_partial a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_partial {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_partial a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_partial; sp.
Qed.
Lemma isprogram_partial_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_partial a).
Proof.
intros; split; intro i.
apply isprogram_partial; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_partial {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_partial a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_partial; auto.
Qed.
Theorem isprogram_admiss {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_admiss a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_partial; sp.
Qed.
Lemma isprogram_admiss_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_admiss a).
Proof.
intros; split; intro i.
apply isprogram_admiss; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_admiss {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_admiss a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_admiss; auto.
Qed.
Theorem isprogram_mono {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_mono a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_partial; sp.
Qed.
Lemma isprogram_mono_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_mono a).
Proof.
intros; split; intro i.
apply isprogram_mono; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_mono {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_mono a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_mono; auto.
Qed.
Theorem wf_ipertype {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_ipertype a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_ipertype {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_ipertype a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
rewrite X0; simpl.
rewrite remove_nvars_nil_r; sp.
apply nt_wf_eq.
apply nt_wf_eq in X.
apply wf_pertype; sp.
Qed.
Lemma isprogram_ipertype_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_ipertype a).
Proof.
intros; split; intro i.
apply isprogram_ipertype; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_ipertype {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_ipertype a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_ipertype; auto.
Qed.
Theorem wf_ipertype_iff {p} :
forall (a : @NTerm p), wf_term a <=> wf_term (mk_ipertype a).
Proof.
intros; split; intro i.
apply wf_ipertype; sp.
allrw @wf_term_eq.
inversion i as [|?|o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_ipertype {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_ipertype f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_ipertype_iff; split; sp.
Qed.
Theorem wf_spertype {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_spertype a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_spertype {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_spertype a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
rewrite X0; simpl.
rewrite remove_nvars_nil_r; sp.
apply nt_wf_eq.
apply nt_wf_eq in X.
apply wf_pertype; sp.
Qed.
Lemma isprogram_spertype_iff {p} :
forall (a : @NTerm p), isprogram a <=> isprogram (mk_spertype a).
Proof.
intros; split; intro i.
apply isprogram_spertype; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Theorem isprog_spertype {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_spertype a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_spertype; auto.
Qed.
Theorem wf_spertype_iff {p} :
forall (a : @NTerm p), wf_term a <=> wf_term (mk_spertype a).
Proof.
intros; split; intro i.
apply wf_spertype; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_spertype {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_spertype f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_spertype_iff; split; sp.
Qed.
Lemma wf_tuni {p} :
forall (a : @NTerm p), wf_term a -> wf_term (mk_tuni a).
Proof.
introv h.
apply nt_wf_eq; apply nt_wf_eq in h.
intros; inversion h; subst;
constructor; allsimpl; sp;
subst; auto; simpl; constructor; auto.
Qed.
Lemma isprogram_tuni {p} :
forall (a : @NTerm p), isprogram a -> isprogram (mk_tuni a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_tuni; sp.
Qed.
Lemma isprogram_tuni_iff {p} :
forall (a: @NTerm p), isprogram a <=> isprogram (mk_tuni a).
Proof.
intros; split; intro i.
apply isprogram_tuni; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_tuni {p} :
forall (a : @NTerm p), isprog a -> isprog (mk_tuni a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_tuni; auto.
Qed.
Theorem wf_tuni_iff {p} :
forall (a : @NTerm p), wf_term a <=> wf_term (mk_tuni a).
Proof.
intros; split; intro i.
apply wf_tuni; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_tuni {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_tuni f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_tuni_iff; split; sp.
Qed.
(*
Theorem wf_esquash :
forall a, wf_term a -> wf_term (mk_esquash a).
Proof.
intros.
apply nt_wf_eq; apply nt_wf_eq in H.
intros; inversion H; subst;
constructor; allsimpl; sp;
subst; auto; constructor; auto.
Qed.
Theorem isprogram_esquash :
forall a, isprogram a -> isprogram (mk_esquash a).
Proof.
sp; allunfold isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold closed.
rewrite X0; simpl.
rewrite remove_nvars_nil_r; sp.
apply nt_wf_eq.
apply nt_wf_eq in X.
apply wf_pertype; sp.
Qed.
Theorem isprog_esquash :
forall a, isprog a -> isprog (mk_esquash a).
Proof.
sp.
allrw isprog_eq.
apply isprogram_esquash; auto.
Qed.
*)
Theorem wf_image {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_image a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_image_iff {p} :
forall (a b : @NTerm p), (wf_term a # wf_term b) <=> wf_term (mk_image a b).
Proof.
intros; split; intro k.
apply wf_image; sp.
allrw <- @nt_wf_eq.
inversion k as [|?|i j u w]; subst; allsimpl.
generalize (u (nobnd a)) (u (nobnd b)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
inversion i1; subst; inversion i2; subst; sp.
Qed.
Lemma isprogram_image {p} :
forall (a b : @NTerm p), isprogram a -> isprogram b -> isprogram (mk_image a b).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_image; sp.
Qed.
Lemma isprogram_image_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_image a b).
Proof.
sp; split; intro k; try (apply isprogram_image; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?|o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)) (i (nobnd b)); intros e1 e2.
dest_imp e1 hyp.
dest_imp e2 hyp.
inversion e1; subst.
inversion e2; subst; sp.
Qed.
Theorem isprog_image {p} :
forall (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_image a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_image; auto.
Qed.
Theorem wf_apply {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_apply a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_apply {p} :
forall (a b : @NTerm p), isprogram a -> isprogram b -> isprogram (mk_apply a b).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_apply; sp.
Qed.
Lemma isprogram_apply_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_apply a b).
Proof.
sp; split; intro k; try (apply isprogram_apply; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)) (i (nobnd b)); intros e1 e2.
dest_imp e1 hyp.
dest_imp e2 hyp.
inversion e1; subst.
inversion e2; subst; sp.
Qed.
Theorem isprog_apply {p} :
forall (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_apply a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apply; auto.
Qed.
Theorem wf_apply2 {p} :
forall (f a b : @NTerm p),
wf_term f -> wf_term a -> wf_term b -> wf_term (mk_apply2 f a b).
Proof.
unfold mk_apply2; sp.
repeat (apply wf_apply); auto.
Qed.
Theorem isprogram_apply2 {p} :
forall (f a b : @NTerm p),
isprogram f -> isprogram a -> isprogram b -> isprogram (mk_apply2 f a b).
Proof.
unfold mk_apply2; sp.
repeat (apply isprogram_apply); auto.
Qed.
Theorem isprog_apply2 {p} :
forall (f a b : @NTerm p),
isprog f -> isprog a -> isprog b -> isprog (mk_apply2 f a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apply2; auto.
Qed.
Theorem wf_eapply {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_eapply a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_eapply {p} :
forall (a b : @NTerm p), isprogram a -> isprogram b -> isprogram (mk_eapply a b).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_eapply; sp.
Qed.
Lemma isprogram_eapply_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_eapply a b).
Proof.
sp; split; intro k; try (apply isprogram_eapply; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)) (i (nobnd b)); intros e1 e2.
dest_imp e1 hyp.
dest_imp e2 hyp.
inversion e1; subst.
inversion e2; subst; sp.
Qed.
Theorem isprog_eapply {p} :
forall (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_eapply a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_eapply; auto.
Qed.
(*
Lemma wf_apseq {p} :
forall f (a : @NTerm p), wf_term a -> wf_term (mk_apseq f a).
Proof.
introv w; allrw <- @nt_wf_eq.
constructor; simpl; tcsp; introv k; sp; subst; constructor; auto.
Qed.
Lemma isprogram_apseq {p} :
forall f (a : @NTerm p), isprogram a -> isprogram (mk_apseq f a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl.
rewrite remove_nvars_nil_r; sp.
allrw @nt_wf_eq.
apply wf_apseq; sp.
Qed.
Lemma isprogram_apseq_iff {p} :
forall f (a : @NTerm p), isprogram a <=> isprogram (mk_apseq f a).
Proof.
sp; split; intro k; try (apply isprogram_apseq; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repd.
unfold isprogram, closed; allrw.
inversion w as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)); intros e1.
dest_imp e1 hyp.
inversion e1; subst; sp.
Qed.
Lemma isprog_apseq {p} :
forall f (a : @NTerm p), isprog a -> isprog (mk_apseq f a).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apseq; auto.
Qed.
*)
(**useful for rewriting in complicated formulae*)
Theorem bt_wf_iff {p} :
forall lv (nt : @NTerm p),
bt_wf (bterm lv nt)
<=> nt_wf nt.
Proof. sp_iff Case; introv H.
Case "->". inverts H as Hwf; auto.
Case "<-". constructor; auto.
Qed.
Theorem wf_parallel {p} :
forall (a b : @NTerm p),
wf_term a
-> wf_term b
-> wf_term (mk_parallel a b).
Proof.
introv wa wb.
repeat (rw <- @nt_wf_eq).
constructor; allsimpl.
- introv i; repndors; tcsp; subst; allrw @bt_wf_iff; allrw @nt_wf_eq; auto.
- unfold num_bvars; simpl; auto.
Qed.
Lemma isprogram_parallel {p} :
forall (a b : @NTerm p),
isprogram a
-> isprogram b
-> isprogram (mk_parallel a b).
Proof.
introv pa pb.
destruct pa as [ca wa].
destruct pb as [cb wb].
constructor.
- unfold closed; simpl; allrw remove_nvars_nil_l; allrw app_nil_r.
rw ca; rw cb; auto.
- rw @nt_wf_eq; apply wf_parallel; rw <- @nt_wf_eq; auto.
Qed.
Lemma isprogram_parallel_iff {p} :
forall (a b : @NTerm p),
isprogram (mk_parallel a b) <=> (isprogram a # isprogram b).
Proof.
introv; split; intro k; try (apply isprogram_parallel; sp).
inversion k as [c w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
apply app_eq_nil_iff in c; repnd.
unfold isprogram; unfold closed; rw c0; rw c.
inversion w as [|?| o lnt i meq ]; subst; allsimpl; clear w.
pose proof (i (nobnd a)) as h1; pose proof (i (nobnd b)) as h2.
autodimp h1 hyp; autodimp h2 hyp.
allrw @bt_wf_iff.
dands; auto.
Qed.
Theorem isprog_parallel {p} :
forall (a b : @NTerm p),
isprog a
-> isprog b
-> isprog (mk_parallel a b).
Proof.
introv pa pb; allrw @isprog_eq.
apply isprogram_parallel; auto.
Qed.
Theorem closed_approx {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_approx a b).
Proof.
intros.
allunfold @closed; unfold mk_approx; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_cequiv {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_cequiv a b).
Proof.
intros.
allunfold @closed; unfold mk_cequiv; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_texc {p} :
forall (a b : @NTerm p),
closed a -> closed b -> closed (mk_texc a b).
Proof.
intros.
allunfold @closed; unfold mk_texc; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_union {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_union a b).
Proof.
intros.
allunfold @closed; unfold mk_union; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_eunion {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_eunion a b).
Proof.
intros.
allunfold @closed; unfold mk_eunion; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_union2 {p} :
forall (a b : @NTerm p), closed a -> closed b -> closed (mk_union2 a b).
Proof.
intros.
allunfold @closed; unfold mk_union2; simpl.
allrw; simpl; auto.
Qed.
Theorem closed_compute {p} :
forall (a b n : @NTerm p),
closed a -> closed b -> closed n -> closed (mk_compute a b n).
Proof.
intros.
allunfold @closed; unfold mk_compute; simpl.
allrw; simpl; sp.
Qed.
Theorem wf_approx {p} :
forall (a b : @NTerm p), wf_term a -> wf_term b -> wf_term (mk_approx a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_approx_iff {p} :
forall (a b : @NTerm p), (wf_term a # wf_term b) <=> wf_term (mk_approx a b).
Proof.
sp; split; intros k.
apply wf_approx; sp.
allrw @wf_term_eq.
inversion k as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)); generalize (i (nobnd b)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
inversion i1; inversion i2; sp.
Qed.
Lemma isprogram_isinl {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_isinl a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_isinl_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_isinl a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_isinl; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_isinl {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_isinl a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_isinl; auto.
Qed.
Lemma isprogram_isinr {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_isinr a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_isinr_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_isinr a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_isinr; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_isinr {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_isinr a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_isinr; auto.
Qed.
Lemma isprogram_isaxiom {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_isaxiom a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_isaxiom_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_isaxiom a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_isaxiom; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_isaxiom {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_isaxiom a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_isaxiom; auto.
Qed.
Lemma isprogram_islambda {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_islambda a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_islambda_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_islambda a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_islambda; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_islambda {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_islambda a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_islambda; auto.
Qed.
Lemma isprogram_can_test {p} :
forall test (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_can_test test a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_ispair {p} :
forall (a b c : @NTerm p),
isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_ispair a b c).
Proof.
introv ipa ipb ipc.
allunfold @isprogram; repnd; allunfold @closed; simpl; allrw; simpl; sp.
constructor; sp; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma isprogram_can_test_iff {p} :
forall test (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_can_test test a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_can_test; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_can_test {p} :
forall test (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_can_test test a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_can_test; auto.
Qed.
Lemma isprogram_ispair_iff {p} :
forall (a b c : @NTerm p),
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_ispair a b c).
Proof.
introv; split; intro i; repnd.
apply isprogram_ispair; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Theorem isprog_ispair {p} :
forall (a b c : @NTerm p),
isprog a
-> isprog b
-> isprog c
-> isprog (mk_ispair a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_ispair; auto.
Qed.
Lemma isprogram_approx {p} :
forall (a b : @NTerm p),
isprogram a -> isprogram b -> isprogram (mk_approx a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_approx; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Lemma isprogram_approx_iff {p} :
forall (a b : @NTerm p), (isprogram a # isprogram b) <=> isprogram (mk_approx a b).
Proof.
intros; split; intro i.
apply isprogram_approx; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Theorem isprog_approx {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_approx a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_approx; auto.
Qed.
Theorem wf_cequiv {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_cequiv a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem isprogram_cequiv {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_cequiv a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_cequiv; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Lemma isprogram_cequiv_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_cequiv a b).
Proof.
intros; split; intro i.
apply isprogram_cequiv; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Theorem isprog_cequiv {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_cequiv a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_cequiv; auto.
Qed.
Theorem isprogram_texc {p} :
forall a b : @NTerm p,
isprogram a -> isprogram b -> isprogram (mk_texc a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_texc; auto.
constructor; auto. intros ? Hin.
allsimpl; repndors; tcsp; subst;
try (constructor;auto).
Qed.
Theorem isprog_texc {p} :
forall a b : @NTerm p,
isprog a -> isprog b -> isprog (mk_texc a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_texc; auto.
Qed.
Theorem isprogram_union {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_union a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_union; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Theorem isprog_union {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_union a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_union; auto.
Qed.
Theorem isprogram_eunion {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_eunion a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_eunion; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Theorem isprog_eunion {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_eunion a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_eunion; auto.
Qed.
Theorem isprogram_union2 {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isprogram (mk_union2 a b).
Proof.
intros. allunfold @isprogram. repnd. split. apply closed_union2; auto.
constructor; auto. intros ? Hin.
inverts Hin as [Hgarbage | Hin]; subst;
try (constructor;auto).
inversion Hin.
Qed.
Theorem isprog_union2 {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_union2 a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_union2; auto.
Qed.
Theorem isprogram_compute {p} :
forall a b n : @NTerm p,
isprogram a -> isprogram b -> isprogram n -> isprogram (mk_compute a b n).
Proof.
unfold isprogram, closed; sp; simpl; allrw; allsimpl; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Theorem isprog_compute {p} :
forall a b n : @NTerm p,
isprog a -> isprog b -> isprog n -> isprog (mk_compute a b n).
Proof.
sp; allrw @isprog_eq.
apply isprogram_compute; auto.
Qed.
Theorem isvalue_approx {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_approx a b).
Proof.
intros; constructor; simpl; auto.
fold (mk_approx a b).
apply isprogram_approx; auto.
Qed.
Theorem isovalue_approx {p} :
forall a b : @NTerm p, nt_wf a -> nt_wf b -> isovalue (mk_approx a b).
Proof.
intros; constructor; simpl; auto.
fold (mk_approx a b).
allrw @nt_wf_eq.
apply wf_approx; auto.
Qed.
Theorem isvalue_cequiv {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_cequiv a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_cequiv; auto.
Qed.
Theorem isovalue_cequiv {p} :
forall a b : @NTerm p, nt_wf a -> nt_wf b -> isovalue (mk_cequiv a b).
Proof.
intros; constructor; simpl; auto.
allrw @nt_wf_eq.
apply wf_approx; auto.
Qed.
Theorem isvalue_texc {p} :
forall a b : @NTerm p,
isprogram a -> isprogram b -> isvalue (mk_texc a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_texc; auto.
Qed.
Theorem isvalue_union {p} :
forall a b :@NTerm p, isprogram a -> isprogram b -> isvalue (mk_union a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_union; auto.
Qed.
Theorem isvalue_eunion {p} :
forall a b :@NTerm p, isprogram a -> isprogram b -> isvalue (mk_eunion a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_eunion; auto.
Qed.
Theorem isvalue_union2 {p} :
forall a b :@NTerm p, isprogram a -> isprogram b -> isvalue (mk_union2 a b).
Proof.
intros; constructor; simpl; auto.
apply isprogram_union2; auto.
Qed.
Theorem isvalue_image {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_image a b).
Proof.
intros; constructor; simpl; auto; apply isprogram_image; auto.
Qed.
Theorem isvalue_pertype {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_pertype a).
Proof.
intros; constructor; simpl; auto; apply isprogram_pertype; auto.
Qed.
Theorem isvalue_partial {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_partial a).
Proof.
intros; constructor; simpl; auto; apply isprogram_partial; auto.
Qed.
Theorem isvalue_ipertype {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_ipertype a).
Proof.
intros; constructor; simpl; auto.
fold (mk_ipertype a).
apply isprogram_ipertype; auto.
Qed.
Theorem isvalue_spertype {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_spertype a).
Proof.
intros; constructor; simpl; auto.
fold (mk_spertype a).
apply isprogram_spertype; auto.
Qed.
(*
Theorem isvalue_tuni :
forall a, isprogram a -> isvalue (mk_tuni a).
Proof.
intros; constructor; apply isprogram_tuni; auto.
Qed.
*)
(*
Theorem isvalue_esquash :
forall a, isprogram a -> isvalue (mk_esquash a).
Proof.
intros. constructor. fold (mk_esquash a).
apply isprogram_esquash; auto.
Qed.
*)
Lemma wf_free_from_atom {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_free_from_atom a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_efree_from_atom {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_efree_from_atom a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_free_from_atoms {p} :
forall T t : @NTerm p,
wf_term T -> wf_term t -> wf_term (mk_free_from_atoms T t).
Proof.
introv wT wt; allrw <- @nt_wf_eq.
inversion wT; inversion wt; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma oball_map_wftb_eq_otrue_implies_wf_term {o} :
forall (bs : list (@BTerm o)) t,
oball (map wftb bs) = oball (map bterm2otrue bs)
-> LIn (nobnd t) bs
-> wf_term t.
Proof.
introv e i.
eapply oball_map_wftb_eq_otrue_implies in e;[|exact i].
allsimpl; auto.
Qed.
Lemma wf_free_from_atom_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_free_from_atom a b T).
Proof.
sp; split; introv h; repnd.
- apply wf_free_from_atom; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_free_from_atom_iff2 {p} :
forall a b T : @NTerm p,
wf_term (mk_free_from_atom a b T) <=> (wf_term a # wf_term b # wf_term T).
Proof.
intros; rw @wf_free_from_atom_iff; sp.
Qed.
Lemma wf_efree_from_atom_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_efree_from_atom a b T).
Proof.
sp; split; introv h; repnd.
- apply wf_efree_from_atom; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_efree_from_atom_iff2 {p} :
forall a b T : @NTerm p,
wf_term (mk_efree_from_atom a b T) <=> (wf_term a # wf_term b # wf_term T).
Proof.
intros; rw @wf_efree_from_atom_iff; sp.
Qed.
Lemma wf_free_from_atoms_iff {p} :
forall T t : @NTerm p,
(wf_term T # wf_term t) <=> wf_term (mk_free_from_atoms T t).
Proof.
sp; split; introv h; repnd.
- apply wf_free_from_atoms; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_free_from_atoms_iff2 {p} :
forall T t : @NTerm p,
wf_term (mk_free_from_atoms T t) <=> (wf_term T # wf_term t).
Proof.
intros; rw @wf_free_from_atoms_iff; sp.
Qed.
Lemma wf_equality {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_equality a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_equality_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_equality a b T).
Proof.
sp; split; introv h; repnd.
- apply wf_equality; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_equality_iff2 {p} :
forall a b T : @NTerm p,
wf_term (mk_equality a b T) <=> (wf_term a # wf_term b # wf_term T).
Proof.
intros; rw @wf_equality_iff; sp.
Qed.
Lemma wf_member {p} :
forall a T : @NTerm p,
wf_term a -> wf_term T -> wf_term (mk_member a T).
Proof.
sp; unfold mk_member; apply wf_equality; sp.
Qed.
Lemma wf_member_iff {p} :
forall a T : @NTerm p, (wf_term a # wf_term T) <=> wf_term (mk_member a T).
Proof.
sp; split; intro i.
apply wf_member; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd T)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_member_iff2 {p} :
forall a T : @NTerm p, wf_term (mk_member a T) <=> (wf_term a # wf_term T).
Proof.
intros; rw @wf_member_iff; sp.
Qed.
Lemma wf_requality {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_requality a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_requality_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_requality a b T).
Proof.
sp; split; introv h; repnd.
- apply wf_equality; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_requality_iff2 {p} :
forall a b T : @NTerm p,
wf_term (mk_requality a b T) <=> (wf_term a # wf_term b # wf_term T).
Proof.
intros; rw @wf_requality_iff; sp.
Qed.
Lemma wf_rmember {p} :
forall a T : @NTerm p,
wf_term a -> wf_term T -> wf_term (mk_rmember a T).
Proof.
sp; unfold mk_member; apply wf_requality; sp.
Qed.
Lemma wf_rmember_iff {p} :
forall a T : @NTerm p, (wf_term a # wf_term T) <=> wf_term (mk_rmember a T).
Proof.
sp; split; intro i.
{ apply wf_rmember; sp. }
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd T)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_rmember_iff2 {p} :
forall a T : @NTerm p, wf_term (mk_rmember a T) <=> (wf_term a # wf_term T).
Proof.
intros; rw @wf_rmember_iff; sp.
Qed.
Lemma wf_tequality {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_tequality a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_tequality_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_tequality a b).
Proof.
sp; split; intro h.
- apply wf_tequality; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term;try (exact h); simpl; sp.
Qed.
Lemma wf_tequality_iff2 {p} :
forall a b : @NTerm p, wf_term (mk_tequality a b) <=> (wf_term a # wf_term b).
Proof.
intros; rw @wf_tequality_iff; sp.
Qed.
Lemma wf_type {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_type a).
Proof.
sp; apply wf_tequality; sp.
Qed.
Lemma wf_type_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_type a).
Proof.
sp; split; intro i.
apply wf_type; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
inversion i1; subst; sp.
Qed.
Lemma wf_type_iff2 {p} :
forall a : @NTerm p, wf_term (mk_type a) <=> wf_term a.
Proof.
intros; rw <- @wf_type_iff; sp.
Qed.
Lemma wf_lam {p} :
forall v (b : @NTerm p), wf_term b -> wf_term (mk_lam v b).
Proof.
intros v b; repeat (rw <- @nt_wf_eq).
intros ntb; inversion ntb; subst; constructor; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma wf_lam_iff {p} :
forall v (b : @NTerm p), (wf_term b) <=> wf_term (mk_lam v b).
Proof.
sp; split; intro i; try (apply wf_lam; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (bterm [v] b)); intros j.
dest_imp j hyp; sp.
inversion j; subst; sp.
Qed.
Lemma wf_id {p} : @wf_term p mk_id.
Proof.
apply wf_lam; sp.
Qed.
Hint Immediate wf_id : wf.
Lemma wf_squash {p} :
forall T : @NTerm p, wf_term (mk_squash T) <=> wf_term T.
Proof.
intro; unfold mk_squash; rw <- @wf_image_iff.
rw <- @wf_lam_iff; split; sp.
Qed.
Theorem wf_function {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_function a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_function_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_function a v b).
Proof.
sp; split; intro i; try (apply wf_function; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_subtype {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_subtype a b).
Proof.
sp; unfold mk_subtype, mk_vsubtype.
apply wf_member; sp.
apply wf_function; sp.
Qed.
Lemma wf_subtype_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_subtype a b).
Proof.
sp; split; intro.
apply wf_subtype; sp.
unfold mk_subtype, mk_vsubtype in H.
allrw <- @wf_member_iff; repd.
allrw <- @wf_function_iff; sp.
Qed.
Lemma wf_halts {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_halts a).
Proof.
sp; unfold mk_halts.
allrw @wf_term_eq.
constructor; repeat (allsimpl; sp; subst; repeat constructor).
Qed.
Lemma wf_halts_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_halts a).
Proof.
sp; split; intro i.
apply wf_halts; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst.
generalize (k (nobnd (mk_cbv a nvarx mk_axiom))); allsimpl; intro j.
dest_imp j hyp.
inversion j as [ lnv nt u ]; subst.
inversion u as [|?| o lnt pp q ]; subst; allsimpl.
generalize (pp (nobnd a)); intro r.
dest_imp r hyp.
inversion r; subst; sp.
Qed.
Lemma isprogram_free_from_atom {p} :
forall a b T : @NTerm p,
isprogram a
-> isprogram b
-> isprogram T
-> isprogram (mk_free_from_atom a b T).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_free_from_atom_iff {p} :
forall a b c : @NTerm p,
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_free_from_atom a b c).
Proof.
intros; split; intro i.
apply isprogram_free_from_atom; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprog_free_from_atom {p} :
forall a b T : @NTerm p,
isprog a
-> isprog b
-> isprog T
-> isprog (mk_free_from_atom a b T).
Proof.
sp; allrw @isprog_eq.
apply isprogram_free_from_atom; auto.
Qed.
Lemma isvalue_free_from_atom {p} :
forall a b T : @NTerm p,
isprogram (mk_free_from_atom a b T) -> isvalue (mk_free_from_atom a b T).
Proof. sp; constructor; sp.
Qed.
Lemma isprogram_efree_from_atom {p} :
forall a b T : @NTerm p,
isprogram a
-> isprogram b
-> isprogram T
-> isprogram (mk_efree_from_atom a b T).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_efree_from_atom_iff {p} :
forall a b c : @NTerm p,
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_efree_from_atom a b c).
Proof.
intros; split; intro i.
apply isprogram_efree_from_atom; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprog_efree_from_atom {p} :
forall a b T : @NTerm p,
isprog a
-> isprog b
-> isprog T
-> isprog (mk_efree_from_atom a b T).
Proof.
sp; allrw @isprog_eq.
apply isprogram_efree_from_atom; auto.
Qed.
Lemma isvalue_efree_from_atom {p} :
forall a b T : @NTerm p,
isprogram (mk_efree_from_atom a b T) -> isvalue (mk_efree_from_atom a b T).
Proof. sp; constructor; sp.
Qed.
Lemma isprogram_free_from_atoms {p} :
forall T t : @NTerm p,
isprogram T
-> isprogram t
-> isprogram (mk_free_from_atoms T t).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_free_from_atoms_iff {p} :
forall a b : @NTerm p,
(isprogram a # isprogram b) <=> isprogram (mk_free_from_atoms a b).
Proof.
intros; split; intro i.
apply isprogram_free_from_atoms; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_free_from_atoms {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_free_from_atoms a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_free_from_atoms; auto.
Qed.
Lemma isvalue_free_from_atoms {p} :
forall a b : @NTerm p,
isprogram (mk_free_from_atoms a b) -> isvalue (mk_free_from_atoms a b).
Proof. sp; constructor; sp.
Qed.
Lemma isprogram_equality {p} :
forall a b T : @NTerm p,
isprogram a
-> isprogram b
-> isprogram T
-> isprogram (mk_equality a b T).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_equality_iff {p} :
forall a b c : @NTerm p,
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_equality a b c).
Proof.
intros; split; intro i.
apply isprogram_equality; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprog_equality {p} :
forall a b T : @NTerm p,
isprog a
-> isprog b
-> isprog T
-> isprog (mk_equality a b T).
Proof.
sp; allrw @isprog_eq.
apply isprogram_equality; auto.
Qed.
Lemma isvalue_equality {p} :
forall a b T : @NTerm p,
isprogram (mk_equality a b T) -> isvalue (mk_equality a b T).
Proof.
intros; constructor; simpl; auto.
Qed.
Lemma isprogram_member {p} :
forall t T : @NTerm p,
isprogram t
-> isprogram T
-> isprogram (mk_member t T).
Proof.
unfold mk_member; sp.
apply isprogram_equality; sp.
Qed.
Lemma isprog_member {p} :
forall t T : @NTerm p,
isprog t
-> isprog T
-> isprog (mk_member t T).
Proof.
unfold mk_member; sp; apply isprog_equality; sp.
Qed.
Lemma isprogram_requality {p} :
forall a b T : @NTerm p,
isprogram a
-> isprogram b
-> isprogram T
-> isprogram (mk_requality a b T).
Proof.
repeat constructor.
{ unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp. }
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_requality_iff {p} :
forall a b c : @NTerm p,
(isprogram a # isprogram b # isprogram c) <=> isprogram (mk_requality a b c).
Proof.
intros; split; intro i.
apply isprogram_requality; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprog_requality {p} :
forall a b T : @NTerm p,
isprog a
-> isprog b
-> isprog T
-> isprog (mk_requality a b T).
Proof.
sp; allrw @isprog_eq.
apply isprogram_requality; auto.
Qed.
Lemma isvalue_requality {p} :
forall a b T : @NTerm p,
isprogram (mk_requality a b T) -> isvalue (mk_requality a b T).
Proof.
intros; constructor; simpl; auto.
Qed.
Lemma isprogram_rmember {p} :
forall t T : @NTerm p,
isprogram t
-> isprogram T
-> isprogram (mk_rmember t T).
Proof.
unfold mk_rmember; sp.
apply isprogram_requality; sp.
Qed.
Lemma isprog_rmember {p} :
forall t T : @NTerm p,
isprog t
-> isprog T
-> isprog (mk_rmember t T).
Proof.
unfold mk_rmember; sp; apply isprog_requality; sp.
Qed.
Lemma isprogram_tequality {p} :
forall a b : @NTerm p,
isprogram a
-> isprogram b
-> isprogram (mk_tequality a b).
Proof.
repeat constructor.
unfold closed; simpl.
allrw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @isprogram; allunfold @closed.
repeat (rewrite remove_nvars_nil_l); sp.
simpl; sp; allunfold @isprogram; sp; subst; constructor; auto.
Qed.
Lemma isprogram_tequality_iff {p} :
forall a b : @NTerm p,
(isprogram a # isprogram b) <=> isprogram (mk_tequality a b).
Proof.
intros; split; intro i.
apply isprogram_tequality; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_tequality {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_tequality a b).
Proof.
sp; allrw @isprog_eq.
apply isprogram_tequality; auto.
Qed.
Lemma isvalue_tequality {p} :
forall a b : @NTerm p, isprogram (mk_tequality a b) -> isvalue (mk_tequality a b).
Proof.
intros; constructor; simpl; auto.
Qed.
Lemma isprogram_type {p} :
forall t : @NTerm p, isprogram t -> isprogram (mk_type t).
Proof.
unfold mk_type; sp.
apply isprogram_tequality; sp.
Qed.
Lemma isprog_type {p} :
forall t : @NTerm p, isprog t -> isprog (mk_type t).
Proof.
unfold mk_type; sp; apply isprog_tequality; sp.
Qed.
Lemma isprogram_cbv {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_cbv a v b).
Proof.
sp.
repeat constructor; sp.
unfold closed; simpl.
rw remove_nvars_nil_l.
rewrite app_nil_r.
rw app_eq_nil_iff; sp.
allunfold @isprogram; allunfold @closed; sp.
allrw subvars_eq.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
allsimpl; sp; subst.
constructor; allunfold @isprogram; sp.
constructor; sp.
Qed.
Lemma isprogram_cbv_iff {p} :
forall (a : @NTerm p) v b,
isprogram (mk_cbv a v b)
<=> isprogram a
# subvars (free_vars b) [v]
# nt_wf b.
Proof.
sp; split; intros i.
inversion i as [ cl w ].
inversion w as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); simpl; intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst.
inversion cl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
unfold isprogram, closed.
onerw app_eq_nil_iff; repd; allrw; sp.
allrw <- null_iff_nil.
allrw null_remove_nvars; allsimpl.
rw subvars_eq.
unfold subset; sp; simpl.
try (complete (apply_in_hyp p; sp)).
apply isprogram_cbv; sp.
Qed.
Lemma isprog_cbv {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_cbv a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_cbv; sp.
Qed.
Lemma isprogram_halts {p} :
forall t : @NTerm p,
isprogram t
-> isprogram (mk_halts t).
Proof.
unfold mk_halts; sp.
apply isprogram_approx.
apply isprogram_axiom.
apply isprogram_cbv; sp.
allrw @nt_wf_eq; apply wf_axiom.
Qed.
Lemma isprog_halts {p} :
forall t : @NTerm p,
isprog t
-> isprog (mk_halts t).
Proof.
sp; allrw @isprog_eq.
apply isprogram_halts; sp.
Qed.
Lemma wf_cbv {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_cbv a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_cbv_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_cbv a v b).
Proof.
sp; split; intros i.
apply wf_cbv; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma wf_isect {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_isect a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_isect_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_isect a v b).
Proof.
sp; split; intro i; try (apply wf_isect; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_isect {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_isect a v b).
Proof.
sp.
unfold isprogram, mk_isect, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_isect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_isect a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_isect; sp.
Qed.
Lemma isprog_isect_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_isect a v b).
Proof.
introv; split; intro k; try (apply isprog_isect; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_disect {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_disect a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_disect_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_disect a v b).
Proof.
sp; split; intro i; try (apply wf_disect; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_disect {p} :
forall (a :@NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_disect a v b).
Proof.
sp.
unfold isprogram, mk_disect, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_disect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_disect a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_disect; sp.
Qed.
Lemma isprog_disect_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_disect a v b).
Proof.
introv; split; intro k; try (apply isprog_disect; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_eisect {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_eisect a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_eisect_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_eisect a v b).
Proof.
sp; split; intro i; try (apply wf_eisect; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_eisect {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_eisect a v b).
Proof.
sp.
unfold isprogram, mk_eisect, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_eisect {p} :
forall (a :@NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_eisect a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_eisect; sp.
Qed.
Lemma isprog_eisect_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_eisect a v b).
Proof.
introv; split; intro k; try (apply isprog_eisect; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_set {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_set a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_set_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_set a v b).
Proof.
sp; split; intro i; try (apply wf_set; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_set {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_set a v b).
Proof.
sp.
unfold isprogram, mk_set, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_set {p} :
forall (a :@NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_set a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_set; sp.
Qed.
Lemma isprog_set_iff {p} :
forall (a :@NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_set a v b).
Proof.
introv; split; intro k; try (apply isprog_set; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_tunion {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_tunion a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_tunion_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_tunion a v b).
Proof.
sp; split; intro i; try (apply wf_tunion; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_tunion {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_tunion a v b).
Proof.
sp.
unfold isprogram, mk_tunion, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_tunion {p} :
forall (a :@NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_tunion a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_tunion; sp.
Qed.
Lemma isprog_tunion_iff {p} :
forall (a :@NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_tunion a v b).
Proof.
introv; split; intro k; try (apply isprog_tunion; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_quotient {p} :
forall (a : @NTerm p) v1 v2 b,
wf_term a -> wf_term b -> wf_term (mk_quotient a v1 v2 b).
Proof.
intros a v1 v2 B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Theorem wf_quotient_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(wf_term a # wf_term b) <=> wf_term (mk_quotient a v1 v2 b).
Proof.
sp; split; intro i; try (apply wf_quotient; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v1,v2] b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_quotient {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram a
-> subvars (free_vars b) [v1,v2]
-> nt_wf b
-> isprogram (mk_quotient a v1 v2 b).
Proof.
sp.
unfold isprogram, mk_quotient, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp.
allrw subvars_prop; discover; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_quotient {p} :
forall (a : @NTerm p) v1 v2 b,
isprog a
-> isprog_vars [v1,v2] b
-> isprog (mk_quotient a v1 v2 b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_quotient; sp.
Qed.
Lemma isprog_quotient_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(isprog a # isprog_vars [v1,v2] b)
<=> isprog (mk_quotient a v1 v2 b).
Proof.
introv; split; intro k; try (apply isprog_quotient; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v1,v2] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v1 x); destruct (eq_var_dec v2 x); sp.
right; right; right; allsimpl; sp.
Qed.
Lemma wf_w {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_w a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_w_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_w a v b).
Proof.
sp; split; intro i; try (apply wf_w; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_w {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_w a v b).
Proof.
sp.
unfold isprogram, mk_w, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_w {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_w a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_w; sp.
Qed.
Lemma isprog_w_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_w a v b).
Proof.
introv; split; intro k; try (apply isprog_w; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma wf_m {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_m a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_m_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_m a v b).
Proof.
sp; split; intro i; try (apply wf_m; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_m {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_m a v b).
Proof.
sp.
unfold isprogram, mk_m, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_m {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_m a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_m; sp.
Qed.
Lemma wf_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
wf_term P
-> wf_term A
-> wf_term B
-> wf_term C
-> wf_term p
-> wf_term (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
introv wP wA wB wC wp; repeat (rw <- @nt_wf_eq).
inversion wP; inversion wA; inversion wB; inversion wC; inversion wp; constructor; sp;
allsimpl; sp; subst; unfold num_bvars; simpl; sp;
constructor; sp; rw @nt_wf_eq; sp.
Qed.
Lemma wf_pw_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
(wf_term P
# wf_term A
# wf_term B
# wf_term C
# wf_term q)
<=> wf_term (mk_pw P ap A bp ba B cp ca cb C q).
Proof.
sp; split; intro i; try (apply wf_pw; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd P))
(k (bterm [ap] A))
(k (bterm [bp,ba] B))
(k (bterm [cp,ca,cb] C))
(k (nobnd q));
intros i1 i2 i3 i4 i5.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
dest_imp i3 hyp; try (complete sp).
dest_imp i4 hyp; try (complete sp).
dest_imp i5 hyp; try (complete sp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst; sp.
Qed.
Lemma isprogram_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram P
-> subvars (free_vars A) [ap]
-> nt_wf A
-> subvars (free_vars B) [bp, ba]
-> nt_wf B
-> subvars (free_vars C) [cp, ca, cb]
-> nt_wf C
-> isprogram p
-> isprogram (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
unfold isprogram, mk_pw, closed; simpl; sp.
allrw <- null_iff_nil.
allrw null_app.
allrw remove_nvars_nil_l.
allrw <- @closed_null_free_vars.
allrw null_nil_iff.
allunfold @isprogram; sp;
try (complete (rw null_remove_nvars; simpl; sp;
allrw subvars_prop; allsimpl;
discover; sp)).
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp, ba] B
-> isprog_vars [cp, ca, cb] C
-> isprog p
-> isprog (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_pw; sp.
Qed.
Lemma wf_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
wf_term P
-> wf_term A
-> wf_term B
-> wf_term C
-> wf_term p
-> wf_term (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
introv wP wA wB wC wp; repeat (rw <- @nt_wf_eq).
inversion wP; inversion wA; inversion wB; inversion wC; inversion wp; constructor; sp;
allsimpl; sp; subst; unfold num_bvars; simpl; sp;
constructor; sp; rw @nt_wf_eq; sp.
Qed.
Lemma wf_pm_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
(wf_term P
# wf_term A
# wf_term B
# wf_term C
# wf_term q)
<=> wf_term (mk_pm P ap A bp ba B cp ca cb C q).
Proof.
sp; split; intro i; try (apply wf_pm; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd P))
(k (bterm [ap] A))
(k (bterm [bp,ba] B))
(k (bterm [cp,ca,cb] C))
(k (nobnd q));
intros i1 i2 i3 i4 i5.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
dest_imp i3 hyp; try (complete sp).
dest_imp i4 hyp; try (complete sp).
dest_imp i5 hyp; try (complete sp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst; sp.
Qed.
Lemma isprogram_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram P
-> subvars (free_vars A) [ap]
-> nt_wf A
-> subvars (free_vars B) [bp, ba]
-> nt_wf B
-> subvars (free_vars C) [cp, ca, cb]
-> nt_wf C
-> isprogram p
-> isprogram (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp.
unfold isprogram, mk_pw, closed; simpl; sp.
allrw <- null_iff_nil.
allrw null_app.
allrw remove_nvars_nil_l.
allrw <- @closed_null_free_vars.
allrw null_nil_iff.
allunfold @isprogram; sp;
try (complete (rw null_remove_nvars; simpl; sp;
allrw subvars_prop; allsimpl;
discover; sp)).
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp, ba] B
-> isprog_vars [cp, ca, cb] C
-> isprog p
-> isprog (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_pm; sp.
Qed.
Lemma isprogram_function {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_function a v b).
Proof.
sp.
unfold isprogram, mk_function, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_function {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_function a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_function; sp.
Qed.
Lemma isprog_function_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_function a v b).
Proof.
introv; split; intro k; try (apply isprog_function; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma isprogram_product {p} :
forall (a : @NTerm p) v b,
isprogram a
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_product a v b).
Proof.
sp.
unfold isprogram, mk_product, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw remove_nvars_nil_l).
rw <- @closed_null_free_vars.
rw null_nil_iff.
allunfold @isprogram; sp.
rw null_remove_nvars; simpl; sp; left.
allrw subvars_prop.
apply_in_hyp pp; allsimpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_product {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isprog (mk_product a v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_product; sp.
Qed.
Lemma isprog_product_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_product a v b).
Proof.
introv; split; intro k; try (apply isprog_product; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (autodimp i1 hyp).
repeat (autodimp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma isprogram_lam {p} :
forall v (b : @NTerm p),
isprog_vars [v] b
-> isprogram (mk_lam v b).
Proof.
sp.
allrw @isprog_vars_eq; sp.
constructor.
unfold closed; simpl.
rw app_nil_r.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
allrw subvars_eq.
allrw subset_singleton_r.
apply_in_hyp pp; sp.
constructor; allsimpl; sp; subst.
constructor; sp.
Qed.
Lemma isprog_lam {p} :
forall v (b : @NTerm p),
isprog_vars [v] b
-> isprog (mk_lam v b).
Proof.
sp; allrw @isprog_eq; apply isprogram_lam; sp.
Qed.
Lemma isprog_vars_var {p} :
forall v, @isprog_vars p [v] (mk_var v).
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
Qed.
Lemma isprog_vars_var_if {p} :
forall v vs, LIn v vs -> @isprog_vars p vs (mk_var v).
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
rw subvars_singleton_l; sp.
Qed.
Lemma isprog_vars_var_if2 {p} :
forall v vs, LIn v vs -> @isprog_vars p vs (mk_var v) <=> True.
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
rw subvars_singleton_l; sp.
Qed.
Lemma isprog_vars_var_iff {p} :
forall v vs, LIn v vs <=> @isprog_vars p vs (mk_var v).
Proof.
sp.
rw @isprog_vars_eq; simpl; sp.
rw subvars_singleton_l; sp; split; sp.
Qed.
Lemma isprog_id {p} :
@isprog p mk_id.
Proof.
unfold mk_id; sp; apply isprog_lam.
apply isprog_vars_var.
Qed.
Hint Immediate isprog_id.
Lemma isprog_vsubtype {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog b
-> isprog (mk_vsubtype a v b).
Proof.
unfold mk_vsubtype; sp.
apply isprog_member; sp.
apply isprog_function; sp.
allrw @isprog_eq.
inversion H0.
allunfold @closed.
allrw @isprog_vars_eq; simpl.
allrw; sp.
Qed.
Lemma isprog_subtype {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_subtype a b).
Proof.
unfold mk_subtype; sp.
apply isprog_member.
apply isprog_lam.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp; simpl.
apply isprog_function; sp.
allrw @isprog_eq.
inversion H0.
allunfold @closed.
rw @isprog_vars_eq; sp.
allrw; sp.
Qed.
Lemma isprog_fun {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_fun a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_function; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma isprog_ufun {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_ufun a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_isect; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma isprog_eufun {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_eufun a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_eisect; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma isprog_prod {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_prod a b).
Proof.
unfold mk_fun; introv ipa ipb.
apply isprog_product; sp.
allrw @isprog_vars_eq; sp; simpl.
allrw @isprog_eq.
inversion ipb.
allunfold @closed.
allrw; sp.
allrw @isprog_eq; allunfold @isprogram; sp.
Qed.
Lemma wf_rec {p} :
forall v (a : @NTerm p), wf_term a -> wf_term (mk_rec v a).
Proof.
intros v a; repeat (rw <- @nt_wf_eq).
intros nta; inversion nta; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_rec {p} :
forall v (a : @NTerm p),
subvars (free_vars a) [v]
-> nt_wf a
-> isprogram (mk_rec v a).
Proof.
sp.
unfold isprogram, mk_rec, closed; simpl; sp.
rw <- null_iff_nil.
repeat (rw null_app).
rw null_nil_iff.
allrw subvars_prop; allsimpl; sp.
rw null_remove_nvars; simpl; sp.
constructor; simpl; allunfold @isprogram; sp; subst; constructor; sp.
Qed.
Lemma isprog_rec {p} :
forall v (a : @NTerm p),
isprog_vars [v] a
-> isprog (mk_rec v a).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_rec; sp.
Qed.
Theorem wf_product {p} :
forall (a : @NTerm p) v b, wf_term a -> wf_term b -> wf_term (mk_product a v b).
Proof.
intros a v B; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_integer {p} :
forall i, @isprogram p (mk_integer i).
Proof.
introv.
repeat constructor; simpl; sp.
Qed.
Hint Immediate isprogram_integer.
Lemma isprogram_int_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (Can NInt) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [ cl w ].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil; allsimpl.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_nat_implies {p} :
forall (bterms : list (@BTerm p)) n,
isprogram (oterm (Can (Nint n)) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_nseq_implies {p} :
forall (bterms : list (@BTerm p)) f,
isprogram (oterm (Can (Nseq f)) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_integer_implies {p} :
forall (bterms : list (@BTerm p)) z,
isprogram (oterm (Can (Nint z)) bterms)
-> bterms = [].
Proof.
exact isprogram_nat_implies.
Qed.
Lemma isprogram_base_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (Can NBase) bterms)
-> bterms = [].
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?| o lnt k e]; subst; allsimpl.
allrw <- null_iff_nil.
allrw null_map.
allrw null_iff_nil; auto.
Qed.
Lemma isprogram_approx_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (Can NApprox) bterms)
-> {a, b : NTerm $
bterms = [nobnd a, nobnd b]}.
Proof.
introv isp; inversion isp as [cl w].
inversion w as [|?|o lnt k e]; subst; allsimpl.
destruct bterms; allsimpl; sp.
destruct bterms; allsimpl; sp.
destruct bterms; allsimpl; sp.
destruct b; destruct b0; allunfold @num_bvars; allsimpl.
inversion e as [len].
rewrite len in H.
repeat (allrw length0; subst; allsimpl).
unfold nobnd.
exists n n0; auto.
Qed.
(* ------ programs ------ *)
Definition WTerm {p} := { t : @NTerm p | wf_term t }.
Definition WBTerm {p} := { bt : @BTerm p | wf_bterm bt }.
(* end hide *)
(*
(* first of all, isprog is NOT a boolean. also, the reader will
be left wondering what UIP_dec is*)
where [isprog] is the Boolean version of [isprogram]
(using a Boolean version of [isprogram] makes it easy to prove that
closed terms are equal by proving that the underlying [NTerm]s are
equals using [UIP_dec]).
*)
(**
The [CTerm] type below is useful in compactly stating definitions
that are only meaningful for closed terms. A [CTerm] is a pair
of an [NTerm] [t] and a proof that [t] is closed.
This [CTerm] type will be handy in compactly
defining the Nuprl type system where types are defined as partial
equivalence relations on closed terms.
*)
Definition CTerm {p} := { t : @NTerm p | isprog t }.
Definition get_cterm {p} (t : @CTerm p) := let (a,_) := t in a.
(* begin hide *)
Definition BCTerm {p} := { bt : @BTerm p | isprog_bt bt }.
(* end hide *)
(**
We also define a type of terms that specifies what are the possible
free variables of its inhabitants. A term is a [(CVTerm vs)] term
if the set of its free variables is a subset of [vs]. This type is
also useful to define the Nuprl type system. For example, to define
a closed family of types such as a closed function type of the form
$\NUPRLfunction{x}{A}{\NUPRLsuba{B}{z}{x}}$, $A$ has to be closed
and the free variables of $B$ can only be $z$.
*)
Definition CVTerm {p} (vs : list NVar) := { t : @NTerm p | isprog_vars vs t }.
(* begin hide *)
Definition CVTerm3 {p} := forall a b c, @CVTerm p [a;b;c].
Definition mk_cvterm {p} (vs : list NVar) (t : @NTerm p) (p : isprog_vars vs t) :=
exist (isprog_vars vs) t p.
Ltac destruct_cterms :=
repeat match goal with
| [ H : CTerm |- _ ] => destruct H
| [ H : CVTerm _ |- _ ] => destruct H
end.
Ltac dest_cterm H :=
let t := type of H in
match goal with
| [ x : CTerm |- _ ] =>
match t with
| context[x] => destruct x
end
| [ x : CVTerm _ |- _ ] =>
match t with
| context[x] => destruct x
end
end.
(** A faster version of destruct_cterms. We avoid destructing all of them. *)
Ltac dest_cterms H := repeat (dest_cterm H).
Definition get_wterm {p} (t : @WTerm p) := let (a,_) := t in a.
Definition get_cvterm {p} (vs : list NVar) (t : @CVTerm p vs) := let (a,_) := t in a.
Definition get_bcterm {p} (bt : @BCTerm p) := let (a,_) := bt in a.
Lemma cterm_eq {p} :
forall t u : @CTerm p,
get_cterm t = get_cterm u
-> t = u.
Proof.
introv; destruct_cterms; simpl; sp; subst.
eauto with pi.
Qed.
Lemma cvterm_eq {p} :
forall vs (t u : @CVTerm p vs),
get_cvterm vs t = get_cvterm vs u
-> t = u.
Proof.
introv; destruct_cterms; simpl; sp; subst.
eauto with pi.
Qed.
Lemma wf_cterm {p} :
forall t, @wf_term p (get_cterm t).
Proof.
introv; destruct_cterms; simpl.
allrw @isprog_eq; allunfold @isprogram; repnd; allrw @nt_wf_eq; sp.
Qed.
Hint Immediate wf_cterm : wf.
Lemma free_vars_cterm {p} :
forall t : @CTerm p, free_vars (get_cterm t) = [].
Proof.
introv; destruct_cterms; simpl.
allrw @isprog_eq; allunfold @isprogram; repnd; allrw; sp.
Qed.
Definition mk_cterm {p} (t : @NTerm p) (p : isprogram t) : CTerm :=
exist isprog t (isprogram_implies t p).
Definition mk_ct {p} (t : @NTerm p) (p : isprog t) : CTerm := exist isprog t p.
Definition mk_wterm {p} (t : @NTerm p) (p : wf_term t) := exist wf_term t p.
Definition mk_wterm' {p} (t : @NTerm p) (p : nt_wf t) :=
exist wf_term t (nt_wf_implies t p).
Definition iscvalue {p} (t : @CTerm p) : Type :=
isvalue (get_cterm t).
Lemma mk_cv_pf {p} :
forall vs t,
@isprog_vars p vs (get_cterm t).
Proof.
destruct t; simpl.
rw @isprog_eq in i; destruct i.
rw @isprog_vars_eq; simpl; sp.
allunfold @closed.
allrw; sp.
Qed.
(** From a closed term, we can always make a term whose variables
* are contained in vs: *)
Definition mk_cv {p} (vs : list NVar) (t : @CTerm p) : CVTerm vs :=
exist (isprog_vars vs) (get_cterm t) (mk_cv_pf vs t).
Ltac clear_deps h :=
repeat match goal with
| [ H : context[h] |- _ ] => clear H
end.
Lemma programs_bt_to_program {p} :
forall bts : list (@BCTerm p),
forall op,
map (fun bt => num_bvars (get_bcterm bt)) bts = OpBindings op
-> isprogram (oterm op (map get_bcterm bts)).
Proof.
sp; unfold isprogram; sp.
allrw @closed_nt; sp.
allrw in_map_iff; sp; subst.
destruct a; destruct x; allsimpl.
clear_deps i.
rw <- @isprogram_bt_eq in i.
inversion i; sp.
constructor; sp.
allrw in_map_iff; sp; subst.
destruct a; destruct x; allsimpl.
clear_deps i.
rw <- @isprogram_bt_eq in i.
inversion i; sp.
rewrite <- H.
rewrite map_map; unfold compose; sp.
Qed.
Definition mkc_int {p} : @CTerm p :=
exist isprog mk_int isprog_int.
Definition mkw_int {p} : @WTerm p :=
exist wf_term mk_int wf_int.
Definition mkc_integer {p} (n : Z) : @CTerm p :=
exist isprog (mk_integer n) (isprog_mk_integer n).
Definition mkw_integer {p} (n : Z) : @WTerm p :=
exist wf_term (mk_integer n) (wf_mk_integer n).
Lemma mkc_integer_eq {p} :
forall a b,
@mkc_integer p a = mkc_integer b
-> a = b.
Proof.
unfold mkc_integer; sp.
inversion H; sp.
Qed.
Definition mkc_nseq {p} (f : nseq) : @CTerm p :=
exist isprog (mk_nseq f) (isprog_mk_nseq f).
Lemma mkc_nseq_eq {p} :
forall f g,
@mkc_nseq p f = mkc_nseq g
-> f = g.
Proof.
unfold mkc_nseq; sp.
inversion H; sp.
Qed.
Lemma isvalue_implies {p} :
forall t, @isvalue p t -> (iscan t # isprogram t).
Proof.
introv isv.
inversion isv; subst; simpl; dands; auto.
Qed.
Lemma isvalue_iff {p} :
forall t : @NTerm p, isvalue t <=> (iscan t # isprogram t).
Proof.
introv; split; intro k.
- apply isvalue_implies; auto.
- repnd; destruct t; allsimpl; tcsp.
Qed.
Definition isprog_nout {p} (t : @NTerm p) :=
assert (no_vars_like_b t) # wf_term t.
Definition isprog_ntseq {o} (f : @ntseq o) :=
forall n, isprog_nout (f n).
Lemma isprogram_mk_ntseq {o} :
forall f : @ntseq o,
isprog_ntseq f
-> isprogram (mk_ntseq f).
Proof.
introv imp.
repeat constructor; pose proof (imp n) as h;
unfold isprog_nout in h; repnd;
apply @no_vars_like_b_true_iff in h0; repnd; auto.
apply nt_wf_eq; auto.
Qed.
Lemma isprog_mk_ntseq {o} :
forall f : @ntseq o,
isprog_ntseq f
-> isprog (mk_ntseq f).
Proof.
introv imp.
apply isprog_eq.
apply isprogram_mk_ntseq; auto.
Qed.
Lemma isvalue_mk_ntseq {o} :
forall f : @ntseq o,
isprog_ntseq f
-> isvalue (mk_ntseq f).
Proof.
introv imp.
apply isvalue_iff; simpl; dands; auto.
apply isprogram_mk_ntseq; auto.
Qed.
Definition mkc_ntseq {o}
(f : @ntseq o)
(p : isprog_ntseq f) : CTerm :=
exist isprog (mk_ntseq f) (isprog_mk_ntseq f p).
Lemma mkc_ntseq_eq {o} :
forall (f g : @ntseq o) pf pg,
mkc_ntseq f pf = mkc_ntseq g pg
-> f = g.
Proof.
unfold mkc_ntseq; introv h.
inversion h; sp.
Qed.
Lemma isprog_nout_proof_irrelevance {p} :
forall (t : @NTerm p),
forall x y : isprog_nout t,
x = y.
Proof.
intros.
destruct x, y.
f_equal; apply UIP.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : isprog_nout ?t , H2 : isprog_nout ?t |- _ ] =>
pose proof (isprog_nout_proof_irrelevance t H2 H1) as h; subst
end : pi.
Lemma isprog_ntseq_proof_irrelevance {o} :
forall (f : @ntseq o) (p1 p2 : isprog_ntseq f),
p1 = p2.
Proof.
introv.
allunfold @isprog_ntseq.
apply functional_extensionality_dep.
introv.
remember (p1 x) as i1.
remember (p2 x) as i2.
eauto with pi.
Qed.
Definition isprog_atom {p} : @isprog p mk_atom := (eq_refl,eq_refl).
Definition isprog_uatom {p} : @isprog p mk_uatom := (eq_refl,eq_refl).
Definition isprog_token {p} :
forall s : String.string, @isprog p (mk_token s) := fun _ => (eq_refl,eq_refl).
Definition isprog_utoken {p} :
forall u : get_patom_set p, @isprog p (mk_utoken u) := fun _ => (eq_refl,eq_refl).
Definition mkc_atom {p} : @CTerm p :=
exist isprog mk_atom isprog_atom.
Definition mkc_token {p} (s : String.string) : @CTerm p :=
exist isprog (mk_token s) (isprog_token s).
Lemma mkc_token_eq {p} :
forall a b,
@mkc_token p a = mkc_token b
-> a = b.
Proof.
introv k; inversion k; sp.
Qed.
Definition mkc_uatom {p} : @CTerm p :=
exist isprog mk_uatom isprog_uatom.
Definition mkc_utoken {p} (u : get_patom_set p) : @CTerm p :=
exist isprog (mk_utoken u) (isprog_utoken u).
Lemma mkc_utoken_eq {p} :
forall a b : get_patom_set p,
@mkc_utoken p a = mkc_utoken b
-> a = b.
Proof.
introv k; inversion k; sp.
Qed.
Definition mkc_nat {p} (n : nat) : @CTerm p :=
exist isprog (mk_nat n) (isprog_mk_nat n).
Definition mkw_nat {p} (n : nat) : @WTerm p :=
exist wf_term (mk_nat n) (wf_mk_nat n).
Definition mkc_uni {p} (i : nat) : @CTerm p :=
exist isprog (mk_uni i) (isprog_mk_uni i).
Definition mkw_uni {p} (i : nat) : @WTerm p :=
exist wf_term (mk_uni i) (wf_mk_uni i).
Lemma mkc_uni_eq {p} :
forall a b,
@mkc_uni p a = mkc_uni b
-> a = b.
Proof.
unfold mkc_uni; sp.
inversion H; sp.
Qed.
Definition mkc_base {p} : @CTerm p :=
exist isprog mk_base isprog_base.
Definition mkw_base {p} : @WTerm p :=
exist wf_term mk_base wf_base.
Definition mkc_axiom {p} : @CTerm p :=
exist isprog mk_axiom isprog_axiom.
Definition mkw_axiom {p} : @WTerm p :=
exist wf_term mk_axiom wf_axiom.
Definition mkc_bottom {p} : @CTerm p :=
exist isprog mk_bottom isprog_bottom.
Lemma isprogram_pair {p} :
forall (a b : @NTerm p),
isprogram a
-> isprogram b
-> isprogram (mk_pair a b).
Proof.
introv pa pb.
inversion pa; inversion pb.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_pair {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_pair a b).
Proof.
sp; allrw @isprog_eq; apply isprogram_pair; sp.
Qed.
Definition mkc_pair {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_pair a b) (isprog_pair a b x y).
Theorem wf_sup {p} :
forall a b : @NTerm p, wf_term a -> wf_term b -> wf_term (mk_sup a b).
Proof.
intros a b; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_sup {p} :
forall a b : @NTerm p,
isprogram a
-> isprogram b
-> isprogram (mk_sup a b).
Proof.
introv pa pb.
inversion pa; inversion pb.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprogram_sup_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_sup a b).
Proof.
intros; split; intro i.
apply isprogram_sup; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_sup {p} :
forall a b : @NTerm p, isprog a -> isprog b -> isprog (mk_sup a b).
Proof.
sp; allrw @isprog_eq; apply isprogram_sup; sp.
Qed.
Definition mkc_sup {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_sup a b) (isprog_sup a b x y).
Lemma mkc_sup_eq {p} :
forall a b c d : @CTerm p,
mkc_sup a b = mkc_sup c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_sup.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_pair_eq {p} :
forall a b c d : @CTerm p,
mkc_pair a b = mkc_pair c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_pair.
inversion H; subst.
eauto with pi.
Qed.
Theorem wf_refl {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_refl a).
Proof.
intros a; repeat (rw <- @nt_wf_eq).
intros nta; inversion nta; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma isprogram_refl {p} :
forall a : @NTerm p,
isprogram a
-> isprogram (mk_refl a).
Proof.
introv pa.
inversion pa.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprogram_refl_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_refl a).
Proof.
intros; split; intro i.
apply isprogram_refl; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_refl {p} :
forall a : @NTerm p, isprog a -> isprog (mk_refl a).
Proof.
sp; allrw @isprog_eq; apply isprogram_refl; sp.
Qed.
Definition mkc_refl {p} (t1 : @CTerm p) : CTerm :=
let (a,x) := t1 in
exist isprog (mk_refl a) (isprog_refl a x).
Lemma mkc_refl_eq {p} :
forall a b : @CTerm p,
mkc_refl a = mkc_refl b
-> a = b.
Proof.
intros.
destruct a, b.
allunfold @mkc_refl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_texc {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_texc a b) (isprog_texc a b x y).
Lemma mkc_texc_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_texc A1 A2 = mkc_texc B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
dands; eauto with pi.
Qed.
Definition mkc_union {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_union a b) (isprog_union a b x y).
Lemma mkc_union_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_union A1 A2 = mkc_union B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_eunion {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_eunion a b) (isprog_eunion a b x y).
Lemma mkc_eunion_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_eunion A1 A2 = mkc_eunion B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_union2 {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_union2 a b) (isprog_union2 a b x y).
Lemma mkc_union2_eq {p} :
forall A1 A2 B1 B2 : @CTerm p,
mkc_union2 A1 A2 = mkc_union2 B1 B2
-> A1 = B1 # A2 = B2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma isprog_unit {p} : @isprog p mk_unit.
Proof.
unfold isprog; simpl.
rw assert_true_iff; dands; sp.
Qed.
Hint Immediate isprog_unit.
Definition mkc_bool {p} : @CTerm p :=
exist isprog mk_bool (isprog_union mk_unit mk_unit isprog_unit isprog_unit).
Lemma isprogram_inl {p} :
forall a : @NTerm p, isprogram a -> isprogram (mk_inl a).
Proof.
introv pa.
inversion pa.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_inl {p} :
forall a : @NTerm p, isprog a -> isprog (mk_inl a).
Proof.
sp; allrw @isprog_eq; apply isprogram_inl; sp.
Qed.
Definition mkc_inl {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in exist isprog (mk_inl a) (isprog_inl a x).
Lemma isprogram_inr {p} :
forall a : @NTerm p, isprogram a -> isprogram (mk_inr a).
Proof.
introv pa.
inversion pa.
constructor; simpl.
unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allunfold @closed; allrw; simpl; sp.
constructor; simpl; sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_inr {p} :
forall a : @NTerm p, isprog a -> isprog (mk_inr a).
Proof.
sp; allrw @isprog_eq; apply isprogram_inr; sp.
Qed.
Definition mkc_inr {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in exist isprog (mk_inr a) (isprog_inr a x).
Lemma mkc_inl_eq {p} :
forall a b : @CTerm p,
mkc_inl a = mkc_inl b
-> a = b.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_inr_eq {p} :
forall a b : @CTerm p,
mkc_inr a = mkc_inr b
-> a = b.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_pertype {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_pertype a) (isprog_pertype a x).
Definition mkw_pertype {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_pertype a) (wf_pertype a x).
Lemma mkc_pertype_eq {p} :
forall R1 R2 : @CTerm p, mkc_pertype R1 = mkc_pertype R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_partial {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_partial a) (isprog_partial a x).
Definition mkw_partial {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_partial a) (wf_partial a x).
Lemma mkc_partial_eq {p} :
forall R1 R2 : @CTerm p, mkc_partial R1 = mkc_partial R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_ipertype {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_ipertype a) (isprog_ipertype a x).
Definition mkw_ipertype {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_ipertype a) (wf_ipertype a x).
Lemma mkc_ipertype_eq {p} :
forall R1 R2 : @CTerm p, mkc_ipertype R1 = mkc_ipertype R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_spertype {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_spertype a) (isprog_spertype a x).
Definition mkw_spertype {p} (R : @WTerm p) : WTerm :=
let (a,x) := R in
exist wf_term (mk_spertype a) (wf_spertype a x).
Lemma mkc_spertype_eq {p} :
forall R1 R2 : @CTerm p, mkc_spertype R1 = mkc_spertype R2 -> R1 = R2.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto with pi.
Qed.
Definition mkc_tuni {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_tuni a) (isprog_tuni a x).
Lemma mkc_tuni_eq {p} :
forall R1 R2 : @CTerm p, mkc_tuni R1 = mkc_tuni R2 -> R1 = R2.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto with pi.
Qed.
Lemma wf_sleep {p} :
forall a : @NTerm p, wf_term a -> wf_term (mk_sleep a).
Proof.
introv h.
apply nt_wf_eq; apply nt_wf_eq in h.
intros; inversion h; subst;
constructor; allsimpl; sp;
subst; auto; simpl; constructor; auto.
Qed.
Lemma isprogram_sleep {p} :
forall a : @NTerm p, isprogram a -> isprogram (mk_sleep a).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_sleep; sp.
Qed.
Lemma isprogram_sleep_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_sleep a).
Proof.
intros; split; intro i.
apply isprogram_sleep; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_sleep {p} :
forall a : @NTerm p, isprog a -> isprog (mk_sleep a).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_sleep; auto.
Qed.
Definition mkc_sleep {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_sleep a) (isprog_sleep a x).
Lemma mkc_sleep_eq {p} :
forall a b : @CTerm p, mkc_sleep a = mkc_sleep b -> a = b.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto with pi.
Qed.
Lemma wf_exception {p} :
forall a (e : @NTerm p),
wf_term a
-> wf_term e
-> wf_term (mk_exception a e).
Proof.
introv h1 h2.
allrw <- @nt_wf_eq.
intros; inversion h1; inversion h2; subst;
constructor; allsimpl; sp;
subst; auto; simpl; constructor; auto.
Qed.
Lemma isprogram_exception {p} :
forall a (e : @NTerm p),
isprogram a
-> isprogram e
-> isprogram (mk_exception a e).
Proof.
sp; allunfold @isprogram; sp.
unfold closed.
simpl.
rw <- null_iff_nil.
repeat (rw null_app).
repeat (rw null_iff_nil).
allunfold @closed.
allrw; simpl; sp.
apply nt_wf_eq.
allrw @nt_wf_eq.
apply wf_exception; sp.
Qed.
Lemma isprogram_exception_iff {p} :
forall a (e : @NTerm p),
isprogram (mk_exception a e) <=> (isprogram a # isprogram e).
Proof.
intros; split; intro i.
- inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd e)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
inversion i2; subst; sp.
- apply isprogram_exception; sp.
Qed.
Lemma isprog_exception {p} :
forall a (e : @NTerm p),
isprog a
-> isprog e
-> isprog (mk_exception a e).
Proof.
sp.
allrw @isprog_eq.
apply isprogram_exception; auto.
Qed.
Definition mkc_exception {p} (a e : @CTerm p) : CTerm :=
let (u,y) := a in
let (t,x) := e in
exist isprog (mk_exception u t) (isprog_exception u t y x).
Lemma mkc_exception_eq {p} :
forall a b (t u : @CTerm p),
mkc_exception a t = mkc_exception b u
-> (a = b # t = u).
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
dands; eauto with pi.
Qed.
Lemma wf_try {p} :
forall (a : @NTerm p) x v b,
wf_term a
-> wf_term x
-> wf_term b
-> wf_term (mk_try a x v b).
Proof.
introv; repeat (rw <- @nt_wf_eq).
intros nta ntb; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_try_iff {p} :
forall (a : @NTerm p) x v b,
(wf_term a # wf_term x # wf_term b) <=> wf_term (mk_try a x v b).
Proof.
sp; split; intros i.
apply wf_try; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst.
generalize (k (nobnd a)) (k (nobnd x)) (k (bterm [v] b)); intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
inversion i1; inversion i2; inversion i3; subst; sp.
Qed.
Lemma isprogram_try {p} :
forall (a : @NTerm p) x v b,
isprogram a
-> isprogram x
-> subvars (free_vars b) [v]
-> nt_wf b
-> isprogram (mk_try a x v b).
Proof.
sp.
repeat constructor; sp.
- unfold closed; simpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; sp.
+ allunfold @isprogram; allunfold @closed; sp.
+ allunfold @isprogram; allunfold @closed; sp.
+ allrw subvars_eq.
rw <- null_iff_nil.
rw null_remove_nvars; simpl; sp.
- allsimpl; sp; subst.
+ constructor; allunfold @isprogram; sp.
+ constructor; allunfold @isprogram; sp.
+ constructor; sp.
Qed.
Lemma isprogram_try_iff {p} :
forall (a : @NTerm p) x v b,
isprogram (mk_try a x v b)
<=> isprogram a
# isprogram x
# subvars (free_vars b) [v]
# nt_wf b.
Proof.
sp; split; intros i.
- inversion i as [ cl w ].
inversion w as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd x)) (k (bterm [v] b)); simpl; intros i1 i2 i3.
dest_imp i1 hyp; dest_imp i2 hyp; dest_imp i3 hyp.
inversion i1; inversion i2; inversion i3; subst.
inversion cl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
unfold isprogram, closed.
onerw app_eq_nil_iff; repd; allrw; sp;
onerw app_eq_nil_iff; repd; allrw; sp.
allrw <- null_iff_nil.
allrw null_remove_nvars; allsimpl.
rw subvars_eq.
unfold subset; sp; simpl.
- apply isprogram_try; sp.
Qed.
Lemma isprogram_try_iff2 {p} :
forall (a : @NTerm p) x v b,
isprogram (mk_try a x v b)
<=> isprogram a # isprogram x # isprogram_bt (bterm [v] b).
Proof.
introv.
rw @isprogram_try_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma isprog_try {p} :
forall (a : @NTerm p) x v b,
isprog a
-> isprog x
-> isprog_vars [v] b
-> isprog (mk_try a x v b).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
apply isprogram_try; sp.
Qed.
Definition mkc_try {p} (t1 : @CTerm p) (n : @CTerm p) (v : NVar) (t2 : CVTerm [v]) : CTerm :=
let (a,x) := t1 in
let (c,z) := n in
let (b,y) := t2 in
exist isprog (mk_try a c v b) (isprog_try a c v b x z y).
(*
Definition mkc_esquash (R : CTerm) : CTerm :=
let (a,x) := R in
exist isprog (mk_esquash a) (isprog_esquash a x).
Definition mkw_esquash (R : WTerm) : WTerm :=
let (a,x) := R in
exist wf_term (mk_esquash a) (wf_esquash a x).
Lemma mkc_esquash_eq :
forall R1 R2, mkc_esquash R1 = mkc_esquash R2 -> R1 = R2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
assert (i = i0) by apply isprog_proof_irrelevance; subst; sp.
Qed.
*)
Definition mkc_isinl {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_isinl a b c) (isprog_isinl a b c x y z).
Lemma mkc_isinl_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinl a b c = mkc_isinl d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_isinr {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_isinr a b c) (isprog_isinr a b c x y z).
Lemma mkc_isinr_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinr a b c = mkc_isinr d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_ispair {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_ispair a b c) (isprog_ispair a b c x y z).
Lemma mkc_ispair_eq {p} :
forall a b c d e f : @CTerm p,
mkc_ispair a b c = mkc_ispair d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_isaxiom {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_isaxiom a b c) (isprog_isaxiom a b c x y z).
Lemma mkc_isaxiom_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinl a b c = mkc_isaxiom d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
Qed.
Definition mkc_islambda {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_islambda a b c) (isprog_islambda a b c x y z).
Lemma mkc_islambda_eq {p} :
forall a b c d e f : @CTerm p,
mkc_isinl a b c = mkc_islambda d e f
-> a = d # b = e # c = f.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
Qed.
Definition mkc_can_test {p} (test: CanonicalTest) (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_can_test test a b c) (isprog_can_test test a b c x y z).
Definition mk_approx_c {p} (t1 t2 : @CTerm p) : NTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
mk_approx a b.
Definition mkc_approx {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_approx a b) (isprog_approx a b x y).
Definition mkw_approx {p} (t1 t2 : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_approx a b) (wf_approx a b x y).
Lemma mkw_approx_eq {p} :
forall a b c d : @WTerm p,
mkw_approx a b = mkw_approx c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkw_approx.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_approx_eq {p} :
forall a b c d : @CTerm p,
mkc_approx a b = mkc_approx c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_approx.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_cequiv {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_cequiv a b) (isprog_cequiv a b x y).
Definition mkw_cequiv {p} (t1 t2 : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_cequiv a b) (wf_cequiv a b x y).
Lemma mkw_cequiv_eq {p} :
forall a b c d : @WTerm p,
mkw_cequiv a b = mkw_cequiv c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkw_cequiv.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_cequiv_eq {p} :
forall a b c d : @CTerm p,
mkc_cequiv a b = mkc_cequiv c d
-> a = c # b = d.
Proof.
intros.
destruct a, b, c, d.
allunfold @mkc_cequiv.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_compute {p} (t1 t2 n : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := n in
exist isprog (mk_compute a b c) (isprog_compute a b c x y z).
Lemma mkc_compute_eq {p} :
forall a b c d n m : @CTerm p,
mkc_compute a b n = mkc_compute c d m
-> a = c # b = d # n = m.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_image {p} (T F : @CTerm p) : CTerm :=
let (t,x) := T in
let (f,y) := F in
exist isprog (mk_image t f) (isprog_image t f x y).
Lemma mkc_image_eq {p} :
forall A1 A2 f1 f2 : @CTerm p,
mkc_image A1 f1 = mkc_image A2 f2
-> A1 = A2 # f1 = f2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
(* end hide *)
(**
Using the [CVTerm] and [CTerm] types we can define useful
abstraction to build closed versions of the various terms of our
computation system. For example, given a variable [v] and a term in
[CVTerm [v]], we can build a closed lambda abstraction. As an other
example, given two closed terms, we can build a closed application
term.
*)
Definition mkc_lam {p} (v : NVar) (b : @CVTerm p [v]) : CTerm :=
let (t,x) := b in
exist isprog (mk_lam v t) (isprog_lam v t x).
Definition mkc_apply {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_apply a b) (isprog_apply a b x y).
(* begin hide *)
Lemma mkc_apply_eq {p} :
forall t1 t2 t3 t4 : @CTerm p,
mkc_apply t1 t2 = mkc_apply t3 t4 -> t1 = t3 # t2 = t4.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
Definition mkw_apply {p} (t1 t2 : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_apply a b) (wf_apply a b x y).
Definition mkc_apply2 {p} (t0 t1 t2 : @CTerm p) : CTerm :=
let (f,z) := t0 in
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_apply2 f a b) (isprog_apply2 f a b z x y).
Lemma mkc_apply2_eq {p} :
forall t0 t1 t2 : @CTerm p,
mkc_apply2 t0 t1 t2 = mkc_apply (mkc_apply t0 t1) t2.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Theorem wf_apply3 {p} :
forall f a b c : @NTerm p,
wf_term f
-> wf_term a
-> wf_term b
-> wf_term c
-> wf_term (mk_apply3 f a b c).
Proof.
unfold mk_apply3; sp.
repeat (apply wf_apply); auto.
Qed.
Theorem isprogram_apply3 {p} :
forall f a b c : @NTerm p,
isprogram f
-> isprogram a
-> isprogram b
-> isprogram c
-> isprogram (mk_apply3 f a b c).
Proof.
unfold mk_apply3; sp.
repeat (apply isprogram_apply); auto.
Qed.
Theorem isprog_apply3 {p} :
forall f a b c : @NTerm p,
isprog f
-> isprog a
-> isprog b
-> isprog c
-> isprog (mk_apply3 f a b c).
Proof.
sp; allrw @isprog_eq.
apply isprogram_apply3; auto.
Qed.
Definition mkc_apply3 {p} (t0 t1 t2 t3 : @CTerm p) : CTerm :=
let (f,u) := t0 in
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_apply3 f a b c) (isprog_apply3 f a b c u x y z).
Lemma mkc_apply3_eq {p} :
forall t0 t1 t2 t3 : @CTerm p,
mkc_apply3 t0 t1 t2 t3 = mkc_apply (mkc_apply (mkc_apply t0 t1) t2) t3.
Proof.
intros; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_eapply {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_eapply a b) (isprog_eapply a b x y).
Lemma mkc_eapply_eq {p} :
forall t1 t2 t3 t4 : @CTerm p,
mkc_eapply t1 t2 = mkc_eapply t3 t4 -> t1 = t3 # t2 = t4.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
(*
Definition mkc_apseq {p} f (t : @CTerm p) : CTerm :=
let (a,x) := t in
exist isprog (mk_apseq f a) (isprog_apseq f a x).
Lemma mkc_apseq_eq {p} :
forall f1 f2 (t1 t2 : @CTerm p),
mkc_apseq f1 t1 = mkc_apseq f2 t2 -> f1 = f2 # t1 = t2.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
*)
(*Definition mkw_apply2 (t0 t1 t2 : WTerm) : WTerm :=
let (f,z) := t0 in
let (a,x) := t1 in
let (b,y) := t2 in
exist wf_term (mk_apply2 f a b) (wf_apply2 f a b z x y).*)
Definition mkc_free_from_atom {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_free_from_atom a b c) (isprog_free_from_atom a b c x y z).
Lemma mkc_free_from_atom_eq {p} :
forall a b c d e f : @CTerm p,
mkc_free_from_atom a b c = mkc_free_from_atom d e f
-> a = d # b = e # c = f.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto 6 with pi.
Qed.
Definition mkc_efree_from_atom {p} (t1 t2 t3 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := t3 in
exist isprog (mk_efree_from_atom a b c) (isprog_efree_from_atom a b c x y z).
Lemma mkc_efree_from_atom_eq {p} :
forall a b c d e f : @CTerm p,
mkc_efree_from_atom a b c = mkc_efree_from_atom d e f
-> a = d # b = e # c = f.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto 6 with pi.
Qed.
Definition mkc_free_from_atoms {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_free_from_atoms a b) (isprog_free_from_atoms a b x y).
Lemma mkc_free_from_atoms_eq {p} :
forall a b c d : @CTerm p,
mkc_free_from_atoms a b = mkc_free_from_atoms c d
-> a = c # b = d.
Proof.
introv h.
destruct_cterms; allsimpl.
inversion h; subst.
eauto 6 with pi.
Qed.
Definition mkc_equality {p} (t1 t2 T : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := T in
exist isprog (mk_equality a b c) (isprog_equality a b c x y z).
Definition mkw_equality {p} (t1 t2 T : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := T in
exist wf_term (mk_equality a b c) (wf_equality a b c x y z).
Lemma mkw_equality_eq {p} :
forall a b c d T U : @WTerm p,
mkw_equality a b T = mkw_equality c d U
-> a = c # b = d # T = U.
Proof.
intros.
destruct a, b, c, d, T, U.
allunfold @mkw_equality.
inversion H; subst.
eauto 6 with pi.
Qed.
Lemma mkc_equality_eq {p} :
forall a b c d T U : @CTerm p,
mkc_equality a b T = mkc_equality c d U
-> a = c # b = d # T = U.
Proof.
intros.
destruct a, b, c, d, T, U.
allunfold @mkc_equality.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_member {p} (t T : @CTerm p) : CTerm :=
let (a,x) := t in
let (b,y) := T in
exist isprog (mk_member a b) (isprog_member a b x y).
Lemma fold_mkc_member {p} :
forall t T : @CTerm p,
mkc_equality t t T = mkc_member t T.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_requality {p} (t1 t2 T : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := T in
exist isprog (mk_requality a b c) (isprog_requality a b c x y z).
Definition mkw_requality {p} (t1 t2 T : @WTerm p) : WTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
let (c,z) := T in
exist wf_term (mk_requality a b c) (wf_requality a b c x y z).
Lemma mkw_requality_eq {p} :
forall a b c d T U : @WTerm p,
mkw_requality a b T = mkw_requality c d U
-> a = c # b = d # T = U.
Proof.
intros.
destruct a, b, c, d, T, U.
allunfold @mkw_requality.
inversion H; subst.
eauto 6 with pi.
Qed.
Lemma mkc_requality_eq {p} :
forall a b c d T U : @CTerm p,
mkc_requality a b T = mkc_requality c d U
-> a = c # b = d # T = U.
Proof.
intros.
destruct a, b, c, d, T, U.
allunfold @mkc_requality.
inversion H; subst.
eauto 6 with pi.
Qed.
Definition mkc_rmember {p} (t T : @CTerm p) : CTerm :=
let (a,x) := t in
let (b,y) := T in
exist isprog (mk_rmember a b) (isprog_rmember a b x y).
Lemma fold_mkc_rmember {p} :
forall t T : @CTerm p,
mkc_requality t t T = mkc_rmember t T.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_tequality {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_tequality a b) (isprog_tequality a b x y).
Lemma mkc_tequality_eq {p} :
forall a b c d : @CTerm p,
mkc_tequality a b = mkc_tequality c d
-> a = c # b = d.
Proof.
intros.
destruct_cterms.
allunfold @mkc_tequality.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_type {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in exist isprog (mk_type a) (isprog_type a x).
Lemma fold_mkc_type {p} :
forall t : @CTerm p, mkc_tequality t t = mkc_type t.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_cbv {p} (t1 : @CTerm p) (v : NVar) (t2 : CVTerm [v]) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_cbv a v b) (isprog_cbv a v b x y).
Definition mkc_halts {p} (t : @CTerm p) : CTerm :=
let (a,x) := t in
exist isprog (mk_halts a) (isprog_halts a x).
Lemma isprog_vars_axiom {p} :
forall v,
@isprog_vars p [v] mk_axiom.
Proof.
unfold isprog_vars; sp.
Qed.
Definition mkcv_axiom {p} (v : NVar) : @CVTerm p [v] :=
exist (isprog_vars [v]) mk_axiom (isprog_vars_axiom v).
Lemma fold_mkc_halts {p} :
forall t : @CTerm p,
mkc_approx mkc_axiom (mkc_cbv t nvarx (mkcv_axiom nvarx)) = mkc_halts t.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Lemma isprogram_spread {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram a
-> subvars (free_vars b) [v1,v2]
-> nt_wf b
-> isprogram (mk_spread a v1 v2 b).
Proof.
unfold isprogram, closed; introv ipa sv ntb; repnd; simpl.
allrw; simpl.
allrw subvars_prop; allsimpl.
allrw app_nil_r.
rw <- null_iff_nil; rw null_remove_nvars.
dands.
introv i.
apply sv in i; sp.
constructor; simpl.
introv e; repdors; subst; try (complete sp).
constructor; sp.
constructor.
Qed.
Lemma isprog_spread {p} :
forall (a : @NTerm p) v1 v2 b,
isprog a
-> isprog_vars [v1,v2] b
-> isprog (mk_spread a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_eq.
allrw @isprog_vars_eq.
apply isprogram_spread; sp.
Qed.
Definition mkc_spread {p}
(t1 : @CTerm p)
(v1 v2 : NVar)
(t2 : CVTerm [v1,v2]) : CTerm :=
let (a,x1) := t1 in
let (b,x2) := t2 in
exist isprog (mk_spread a v1 v2 b) (isprog_spread a v1 v2 b x1 x2).
Lemma mkc_spread_eq1 {p} :
forall (a1 : @CTerm p) x1 y1 b1 a2 x2 y2 b2,
mkc_spread a1 x1 y1 b1 = mkc_spread a2 x2 y2 b2
-> a1 = a2 # x1 = x2 # y1 = y2.
Proof.
introv e.
destruct a1, a2, b1, b2.
allunfold @mkc_spread.
inversion e; subst.
eauto with pi.
Qed.
Lemma mkc_spread_eq2 {p} :
forall (a : @CTerm p) x y b1 b2,
mkc_spread a x y b1 = mkc_spread a x y b2
-> b1 = b2.
Proof.
introv e.
destruct a, b1, b2.
allunfold @mkc_spread.
inversion e; subst.
eauto with pi.
Qed.
Lemma isprogram_dsup {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram a
-> subvars (free_vars b) [v1,v2]
-> nt_wf b
-> isprogram (mk_dsup a v1 v2 b).
Proof.
unfold isprogram, closed; introv ipa sv ntb; repnd; simpl.
allrw; simpl.
allrw subvars_prop; allsimpl.
allrw app_nil_r.
rw <- null_iff_nil; rw null_remove_nvars.
dands.
introv i.
apply sv in i; sp.
constructor; simpl.
introv e; repdors; subst; try (complete sp).
constructor; sp.
constructor.
Qed.
Lemma isprog_dsup {p} :
forall (a : @NTerm p) v1 v2 b,
isprog a
-> isprog_vars [v1,v2] b
-> isprog (mk_dsup a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_eq.
allrw @isprog_vars_eq.
apply isprogram_dsup; sp.
Qed.
Definition mkc_dsup {p}
(t1 : @CTerm p)
(v1 v2 : NVar)
(t2 : CVTerm [v1,v2]) : CTerm :=
let (a,x1) := t1 in
let (b,x2) := t2 in
exist isprog (mk_dsup a v1 v2 b) (isprog_dsup a v1 v2 b x1 x2).
Lemma isprogram_decide {p} :
forall (a : @NTerm p) v1 a1 v2 a2,
isprogram a
-> subvars (free_vars a1) [v1]
-> nt_wf a1
-> subvars (free_vars a2) [v2]
-> nt_wf a2
-> isprogram (mk_decide a v1 a1 v2 a2).
Proof.
unfold isprogram, closed; introv ipa sv1 nt1 sv2 nt2; repnd; simpl.
allrw; simpl.
allrw subvars_eq.
unfold subset in sv1, sv2; sp.
assert (remove_nvars [v1] (free_vars a1) = []) as eq1.
rw <- null_iff_nil; rw null_remove_nvars; introv ia1.
apply sv1 in ia1; sp.
assert (remove_nvars [v2] (free_vars a2) = []) as eq2.
rw <- null_iff_nil; rw null_remove_nvars; introv ia2.
apply sv2 in ia2; sp.
rw eq1; rw eq2; sp.
repeat (constructor; simpl; sp; subst).
Qed.
Lemma isprog_decide {p} :
forall (a : @NTerm p) v1 a1 v2 a2,
isprog a
-> isprog_vars [v1] a1
-> isprog_vars [v2] a2
-> isprog (mk_decide a v1 a1 v2 a2).
Proof.
introv ipa ipa1 ipa2.
allrw @isprog_eq.
allrw @isprog_vars_eq.
apply isprogram_decide; sp.
Qed.
Definition mkc_decide {p}
(t : @CTerm p)
(v1 : NVar)
(t1 : CVTerm [v1])
(v2 : NVar)
(t2 : CVTerm [v2]) : CTerm :=
let (a,x) := t in
let (a1,x1) := t1 in
let (a2,x2) := t2 in
exist isprog (mk_decide a v1 a1 v2 a2) (isprog_decide a v1 a1 v2 a2 x x1 x2).
Definition mkc_ite {p} (a b c : @CTerm p) :=
let (t1,x1) := a in
let (t2,x2) := b in
let (t3,x3) := c in
exist isprog
(mk_decide t1 nvarx t2 nvarx t3)
(isprog_decide t1 nvarx t2 nvarx t3
x1
(isprog_vars_if_isprog [nvarx] t2 x2)
(isprog_vars_if_isprog [nvarx] t3 x3)).
Lemma mkc_ite_eq_mkc_decide {p} :
forall a b c : @CTerm p,
mkc_ite a b c = mkc_decide a nvarx (mk_cv [nvarx] b) nvarx (mk_cv [nvarx] c).
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_isect {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_isect a v b) (isprog_isect a v b x y).
Definition mkw_isect {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_isect a v b) (wf_isect a v b x y).
Lemma mkw_isect_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_isect a1 v1 b1 = mkw_isect a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_isect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_isect_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_isect a1 v1 b1 = mkc_isect a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_isect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_isect_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_isect a v b1 = mkc_isect a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_isect.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_uall {p} := @mkc_isect p.
Definition mkc_eisect {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_eisect a v b) (isprog_eisect a v b x y).
Lemma mkc_eisect_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_eisect a1 v1 b1 = mkc_eisect a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_eisect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_eisect_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_eisect a v b1 = mkc_eisect a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_eisect.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_disect {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_disect a v b) (isprog_disect a v b x y).
Definition mkw_disect {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_disect a v b) (wf_disect a v b x y).
Lemma mkw_disect_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_disect a1 v1 b1 = mkw_disect a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_disect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_disect_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_disect a1 v1 b1 = mkc_disect a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_disect.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_disect_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_disect a v b1 = mkc_disect a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_disect.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_set {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_set a v b) (isprog_set a v b x y).
Lemma mkc_set_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_set a1 v1 b1 = mkc_set a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_set.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_set_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_set a v b1 = mkc_set a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_set.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_tunion {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_tunion a v b) (isprog_tunion a v b x y).
Lemma mkc_tunion_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_tunion a1 v1 b1 = mkc_tunion a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_tunion.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_tunion_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_tunion a v b1 = mkc_tunion a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_tunion.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_quotient {p} (T1 : @CTerm p) (v1 v2 : NVar) (T2 : CVTerm [v1,v2]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_quotient a v1 v2 b) (isprog_quotient a v1 v2 b x y).
Lemma mkc_quotient_eq1 {p} :
forall (a1 : @CTerm p) v1 u1 b1 a2 v2 u2 b2,
mkc_quotient a1 v1 u1 b1 = mkc_quotient a2 v2 u2 b2
-> a1 = a2 # v1 = v2 # u1 = u2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_quotient.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_quotient_eq2 {p} :
forall (a : @CTerm p) v1 v2 b1 b2,
mkc_quotient a v1 v2 b1 = mkc_quotient a v1 v2 b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_quotient.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_w {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_w a v b) (isprog_w a v b x y).
Definition mkw_w {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_w a v b) (wf_w a v b x y).
Lemma mkw_w_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_w a1 v1 b1 = mkw_w a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_w.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_w_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_w a1 v1 b1 = mkc_w a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_w_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_w a v b1 = mkc_w a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_m {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_m a v b) (isprog_m a v b x y).
Definition mkw_m {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) : WTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_m a v b) (wf_w a v b x y).
Lemma mkw_m_eq {p} :
forall (a1 : @WTerm p) v1 b1 a2 v2 b2,
mkw_m a1 v1 b1 = mkw_m a2 v2 b2
-> a1 = a2 # v1 = v2 # b1 = b2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkw_m.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_m_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_m a1 v1 b1 = mkc_m a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_m_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_m a v b1 = mkc_m a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_w.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_pw {p}
(P : @CTerm p)
(ap : NVar) (A : CVTerm [ap])
(bp : NVar) (ba : NVar) (B : CVTerm [bp, ba])
(cp : NVar) (ca : NVar) (cb : NVar) (C : CVTerm [cp, ca, cb])
(p : CTerm) : CTerm :=
let (tP,wP) := P in
let (tA,wA) := A in
let (tB,wB) := B in
let (tC,wC) := C in
let (tp,wp) := p in
exist isprog
(mk_pw tP ap tA bp ba tB cp ca cb tC tp)
(isprog_pw tP ap tA bp ba tB cp ca cb tC tp wP wA wB wC wp).
Lemma mkc_pw_eq1 {p} :
forall (P1 : @CTerm p) ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2,
mkc_pw P1 ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
= mkc_pw P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2
-> P1 = P2
# p1 = p2
# ap1 = ap2
# bp1 = bp2
# ba1 = ba2
# cp1 = cp2
# ca1 = ca2
# cb1 = cb2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Lemma mkc_pw_eq2 {p} :
forall (P : @CTerm p) ap bp ba cp ca cb p A1 B1 C1 A2 B2 C2,
mkc_pw P ap A1 bp ba B1 cp ca cb C1 p
= mkc_pw P ap A2 bp ba B2 cp ca cb C2 p
-> A1 = A2 # B1 = B2 # C1 = C2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Lemma isprog_vars_pw {p} :
forall vs (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp, ba] B
-> isprog_vars [cp, ca, cb] C
-> isprog_vars vs p
-> isprog_vars vs (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
allrw @isprog_eq.
allrw @isprog_vars_eq; sp.
simpl.
allunfold @isprogram; repnd.
allrw subvars_app_l; allrw remove_nvars_nil_l; allrw; sp;
allrw subvars_prop; introv i; allrw in_remove_nvars; allrw in_single_iff;
repnd; discover; allrw in_single_iff; sp.
constructor; simpl; sp; subst; constructor; sp.
allunfold @isprogram; sp.
Qed.
Definition mkc_pw_vs {p}
(vs : list NVar)
(P : @CTerm p)
(ap : NVar) (A : CVTerm [ap])
(bp : NVar) (ba : NVar) (B : CVTerm [bp, ba])
(cp : NVar) (ca : NVar) (cb : NVar) (C : CVTerm [cp, ca, cb])
(p : CVTerm vs) : CVTerm vs :=
let (tP,wP) := P in
let (tA,wA) := A in
let (tB,wB) := B in
let (tC,wC) := C in
let (tp,wp) := p in
exist (isprog_vars vs)
(mk_pw tP ap tA bp ba tB cp ca cb tC tp)
(isprog_vars_pw vs tP ap tA bp ba tB cp ca cb tC tp wP wA wB wC wp).
Definition mkc_pm {p}
(P : @CTerm p)
(ap : NVar) (A : CVTerm [ap])
(bp : NVar) (ba : NVar) (B : CVTerm [bp, ba])
(cp : NVar) (ca : NVar) (cb : NVar) (C : CVTerm [cp, ca, cb])
(p : CTerm) : CTerm :=
let (tP,wP) := P in
let (tA,wA) := A in
let (tB,wB) := B in
let (tC,wC) := C in
let (tp,wp) := p in
exist isprog
(mk_pm tP ap tA bp ba tB cp ca cb tC tp)
(isprog_pm tP ap tA bp ba tB cp ca cb tC tp wP wA wB wC wp).
Lemma mkc_pm_eq1 {p} :
forall (P1 : @CTerm p) ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2,
mkc_pm P1 ap1 A1 bp1 ba1 B1 cp1 ca1 cb1 C1 p1
= mkc_pm P2 ap2 A2 bp2 ba2 B2 cp2 ca2 cb2 C2 p2
-> P1 = P2
# p1 = p2
# ap1 = ap2
# bp1 = bp2
# ba1 = ba2
# cp1 = cp2
# ca1 = ca2
# cb1 = cb2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Lemma mkc_pm_eq2 {p} :
forall (P : @CTerm p) ap bp ba cp ca cb p A1 B1 C1 A2 B2 C2,
mkc_pm P ap A1 bp ba B1 cp ca cb C1 p
= mkc_pm P ap A2 bp ba B2 cp ca cb C2 p
-> A1 = A2 # B1 = B2 # C1 = C2.
Proof.
introv e.
destruct_cterms; allsimpl.
inversion e; subst; irr; sp.
Qed.
Definition mkc_function {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_function a v b) (isprog_function a v b x y).
Definition mkw_function {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_function a v b) (wf_function a v b x y).
Lemma mkc_function_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_function a1 v1 b1 = mkc_function a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_function.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_function_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_function a v b1 = mkc_function a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_function.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_product {p} (T1 : @CTerm p) (v : NVar) (T2 : CVTerm [v]) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_product a v b) (isprog_product a v b x y).
Definition mkw_product {p} (T1 : @WTerm p) (v : NVar) (T2 : WTerm) :=
let (a,x) := T1 in
let (b,y) := T2 in
exist wf_term (mk_product a v b) (wf_product a v b x y).
Lemma mkc_product_eq1 {p} :
forall (a1 : @CTerm p) v1 b1 a2 v2 b2,
mkc_product a1 v1 b1 = mkc_product a2 v2 b2
-> a1 = a2 # v1 = v2.
Proof.
intros.
destruct a1, a2, b1, b2.
allunfold @mkc_product.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_product_eq2 {p} :
forall (a : @CTerm p) v b1 b2,
mkc_product a v b1 = mkc_product a v b2
-> b1 = b2.
Proof.
intros.
destruct a, b1, b2.
allunfold @mkc_product.
inversion H; subst.
eauto with pi.
Qed.
Definition mkc_var {p} (v : NVar) : @CVTerm p [v] :=
exist (isprog_vars [v]) (mk_var v) (isprog_vars_var v).
Definition mkc_vsubtype {p} (T1 : @CTerm p) (v : NVar) (T2 : CTerm) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_vsubtype a v b) (isprog_vsubtype a v b x y).
Definition mkc_subtype {p} (T1 : @CTerm p) (T2 : CTerm) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_subtype a b) (isprog_subtype a b x y).
(** newvar on closed terms *)
Definition cnewvar {p} (t : @CTerm p) := newvar (proj1_sig t).
Lemma cnewvar_eq {p} :
forall t : @CTerm p, cnewvar t = nvarx.
Proof.
destruct t; unfold cnewvar, newvar; simpl.
rw @isprog_eq in i.
inversion i.
unfold closed in H.
rewrite H.
unfold fresh_var; sp.
Qed.
Lemma isprog_vars_cvterm_var {p} :
forall v : NVar,
forall t : @CTerm p,
isprog_vars [v] (proj1_sig t).
Proof.
destruct t; unfold cnewvar.
rw @isprog_vars_eq; simpl.
rw @isprog_eq in i.
inversion i; sp.
unfold closed in H.
rewrite H; sp.
Qed.
Lemma isprog_vars_cvterm_newvar {p} :
forall t : @CTerm p,
isprog_vars [cnewvar t] (proj1_sig t).
Proof.
sp; apply isprog_vars_cvterm_var.
Qed.
(** Builds, from a closed term t, a term that has at most one free variable,
* namely v, which we know not to be in t.
* The term is the same. Only the proof of closeness changes. *)
Definition cvterm_var {p} (v : NVar) (t : @CTerm p) : CVTerm [v] :=
exist (isprog_vars [v])
(proj1_sig t)
(isprog_vars_cvterm_var v t).
Definition cvterm_newvar {p} (t : @CTerm p) : CVTerm [cnewvar t] :=
cvterm_var (cnewvar t) t.
Lemma mk_cv_as_cvterm_var {p} :
forall v (t : @CTerm p), mk_cv [v] t = cvterm_var v t.
Proof.
intros.
destruct_cterms.
apply cvterm_eq; simpl; auto.
Qed.
Definition mkc_fun {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_fun a b) (isprog_fun a b x y).
Lemma fold_mkc_fun {p} :
forall (A B : @CTerm p),
mkc_function A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_fun A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_ufun {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_ufun a b) (isprog_ufun a b x y).
Lemma fold_mkc_ufun {p} :
forall (A B : @CTerm p),
mkc_isect A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_ufun A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_eufun {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_eufun a b) (isprog_eufun a b x y).
Lemma fold_mkc_eufun {p} :
forall (A B : @CTerm p),
mkc_eisect A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_eufun A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_prod {p} (A B : @CTerm p) : CTerm :=
let (a,x) := A in
let (b,y) := B in
exist isprog (mk_prod a b) (isprog_prod a b x y).
Lemma fold_mkc_prod {p} :
forall (A B : @CTerm p),
mkc_product A (cnewvar B) (mk_cv [cnewvar B] B)
= mkc_prod A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_iff {p} (a b : @CTerm p) := mkc_prod (mkc_fun a b) (mkc_fun b a).
Definition mkc_id {p} : @CTerm p := mkc_lam nvarx (mkc_var nvarx).
Definition mkc_squash {p} (T : @CTerm p) :=
mkc_image T (mkc_lam nvarx (mk_cv [nvarx] mkc_axiom)).
Lemma get_cterm_mkc_squash {p} :
forall T : @CTerm p, get_cterm (mkc_squash T) = mk_squash (get_cterm T).
Proof.
intro; destruct_cterms; sp.
Qed.
Lemma isprogram_fix {p} :
forall t : @NTerm p, isprogram t -> isprogram (mk_fix t).
Proof.
introv isp.
repeat constructor; simpl; sp; subst.
unfold closed; simpl.
rewrite remove_nvars_nil_l.
rewrite app_nil_r.
inversion isp as [cl w]; sp.
inversion isp; sp.
Qed.
Lemma isprogram_fix_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_fix a).
Proof.
intros; split; intro i.
apply isprogram_fix; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprog_fix {p} :
forall t : @NTerm p, isprog t -> isprog (mk_fix t).
Proof.
intro; repeat (rw @isprog_eq); sp.
apply isprogram_fix; sp.
Qed.
Lemma wf_fix {p} : forall t : @NTerm p, wf_term t -> wf_term (mk_fix t).
Proof.
introv wt.
allrw @wf_term_eq.
constructor; simpl; sp; subst.
constructor; auto.
Qed.
Lemma wf_bot {p} : @wf_term p mk_bot.
Proof.
unfold mk_bot, mk_bottom.
apply wf_fix.
apply wf_id.
Qed.
Hint Immediate wf_bot : wf.
Lemma isprogram_bot {p} : @isprogram p mk_bot.
Proof.
unfold mk_bot, mk_bottom.
apply isprogram_fix.
apply isprogram_lam; simpl.
apply isprog_vars_var.
Qed.
Hint Immediate isprogram_bot.
Lemma isprogram_mk_bot {p} : @isprogram p mk_bot.
Proof.
apply isprogram_bot.
Qed.
Hint Immediate isprogram_mk_bot.
Lemma isprog_bot {p} : @isprog p mk_bot.
Proof.
rw @isprog_eq.
apply isprogram_bot.
Qed.
Hint Immediate isprog_bot.
Lemma wf_vbot {p} : forall v, @wf_term p (mk_vbot v).
Proof.
introv.
unfold mk_vbot.
apply wf_fix.
apply wf_lam; sp.
Qed.
Hint Immediate wf_vbot : wf.
Lemma isprogram_vbot {p} : forall v, @isprogram p (mk_vbot v).
Proof.
introv.
unfold mk_vbot.
apply isprogram_fix.
apply isprogram_lam; simpl.
apply isprog_vars_var.
Qed.
Hint Immediate isprogram_vbot.
Lemma isprog_vbot {p} : forall v, @isprog p (mk_vbot v).
Proof.
introv.
rw @isprog_eq.
apply isprogram_vbot.
Qed.
Hint Immediate isprog_vbot.
Lemma isprogram_mk_false {p} :
@isprogram p mk_false.
Proof.
unfold mk_false.
apply isprogram_approx.
apply isprogram_axiom.
apply isprogram_bot.
Qed.
Hint Immediate isprogram_mk_false.
Lemma isprog_mk_false {p} :
@isprog p mk_false.
Proof.
rw @isprog_eq.
apply isprogram_mk_false.
Qed.
Lemma wf_mk_false {p} :
@wf_term p mk_false.
Proof.
sp.
Qed.
Definition mkc_false {p} : @CTerm p :=
exist isprog mk_false isprog_mk_false.
Definition mkc_bot {p} : @CTerm p :=
exist isprog mk_bot isprog_bot.
Definition mkc_fix {p} (t : @CTerm p) :=
let (a,x) := t in
exist isprog (mk_fix a) (isprog_fix a x).
Lemma mkc_bot_eq {p} :
@mkc_bot p = mkc_fix mkc_id.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Lemma mkc_false_eq {p} :
@mkc_false p = mkc_approx mkc_axiom mkc_bot.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Theorem isprogram_void {p} : @isprogram p mk_void.
Proof.
unfold mk_void; apply isprogram_mk_false.
Qed.
Theorem isprog_void {p} : @isprog p mk_void.
Proof.
unfold mk_void; apply isprog_mk_false.
Qed.
Theorem wf_void {p} : @wf_term p mk_void.
Proof.
sp.
Qed.
Definition mkc_void {p} : @CTerm p := exist isprog mk_void isprog_void.
Definition mkc_unit {p} : @CTerm p := exist isprog mk_unit isprog_unit.
Lemma mkc_unit_eq {p} : @mkc_unit p = mkc_approx mkc_axiom mkc_axiom.
Proof.
apply cterm_eq; auto.
Qed.
(*
Lemma isprogram_void_implies :
forall bterms,
isprogram (oterm (Can NVoid) bterms)
-> bterms = [].
Proof.
sp; allunfold isprogram; sp.
inversion X; subst; allsimpl.
allrw <- null_iff_nil; allsimpl.
allrw null_map; sp.
Qed.
*)
Lemma fold_mkc_vsubtype {p} :
forall (A : @CTerm p) v B,
mkc_member mkc_id (mkc_function A v (cvterm_var v B))
= mkc_vsubtype A v B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Lemma fold_mkc_subtype {p} :
forall (A B : @CTerm p),
mkc_member mkc_id (mkc_function A (cnewvar B) (cvterm_newvar B))
= mkc_subtype A B.
Proof.
introv; destruct_cterms; apply cterm_eq; auto.
Qed.
Definition mkc_rec {p} (v : NVar) (t : @CVTerm p [v]) :=
let (a,x) := t in
exist isprog (mk_rec v a) (isprog_rec v a x).
Definition mkw_rec {p} (v : NVar) (t : @WTerm p) :=
let (a,x) := t in
exist wf_term (mk_rec v a) (wf_rec v a x).
Definition isvalue_wft {p} (t : @WTerm p) :=
let (a,_) := t in isvalue a.
Definition isovalue_wft {p} (t : @WTerm p) :=
let (a,_) := t in isovalue a.
Lemma isvalue_wft_mkw_approx {p} :
forall t : @WTerm p, isvalue_wft (mkw_approx t t).
Proof.
unfold isvalue_wft, mkw_approx; sp.
destruct t; simpl.
apply isvalue_approx.
Abort.
Lemma iscvalue_mkc_nat {p} : forall n : nat, @iscvalue p (mkc_nat n).
Proof.
repeat constructor; sp; allsimpl; sp.
Qed.
Theorem iscvalue_mkc_uni {p} : forall i : nat, @iscvalue p (mkc_uni i).
Proof.
repeat constructor; sp; allsimpl; sp.
Qed.
Lemma isvalue_wft_mkw_int {p} : @isvalue_wft p mkw_int.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma isovalue_wft_mkw_int {p} : @isovalue_wft p mkw_int.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma iscvalue_mkc_int {p} : @iscvalue p mkc_int.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Lemma isovalue_wft_mkw_axiom {p} : @isovalue_wft p mkw_axiom.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem iscvalue_mkc_axiom {p} : @iscvalue p mkc_axiom.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Theorem iscvalue_mkc_base {p} : @iscvalue p mkc_base.
Proof.
repeat constructor. intros. allsimpl; sp.
Qed.
Hint Immediate iscvalue_mkc_nat.
Hint Immediate iscvalue_mkc_uni.
Hint Immediate iscvalue_mkc_int.
Hint Immediate iscvalue_mkc_axiom.
Hint Immediate iscvalue_mkc_base.
Lemma isovalue_wft_mkw_approx {p} :
forall t1 t2 : @WTerm p, isovalue_wft (mkw_approx t1 t2).
Proof.
intro; destruct t1; destruct t2; simpl.
apply isovalue_approx; allrw @nt_wf_eq; auto.
Qed.
Lemma iscvalue_mkc_approx {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_approx t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_approx; allrw @isprog_eq; auto.
Qed.
Lemma isovalue_wft_mkw_cequiv {p} :
forall t1 t2 : @WTerm p, isovalue_wft (mkw_cequiv t1 t2).
Proof.
intro; destruct t1; destruct t2; simpl.
apply isovalue_cequiv; allrw @nt_wf_eq; auto.
Qed.
Lemma iscvalue_mkc_cequiv {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_cequiv t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_cequiv; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_texc {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_texc t1 t2).
Proof.
introv; destruct_cterms; unfold iscvalue; simpl.
apply isvalue_texc; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_union {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_union t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_union; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_eunion {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_eunion t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_eunion; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_union2 {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_union2 t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_union2; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_image {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_image t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_image; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_pertype {p} :
forall t : @CTerm p, iscvalue (mkc_pertype t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_pertype; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_partial {p} :
forall t : @CTerm p, iscvalue (mkc_partial t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_partial; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_ipertype {p} :
forall t : @CTerm p, iscvalue (mkc_ipertype t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_ipertype; allrw @isprog_eq; auto.
Qed.
Lemma iscvalue_mkc_spertype {p} :
forall t : @CTerm p, iscvalue (mkc_spertype t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_spertype; allrw @isprog_eq; auto.
Qed.
(*
Lemma iscvalue_mkc_tuni :
forall t, iscvalue (mkc_tuni t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_tuni; allrw isprog_eq; auto.
Qed.
*)
(*
Lemma iscvalue_mkc_esquash :
forall t, iscvalue (mkc_esquash t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_esquash; allrw isprog_eq; auto.
Qed.
*)
Lemma mkw_integer_eq_nat {p} :
forall n,
@mkw_integer p (Z.of_nat n) = mkw_nat n.
Proof.
sp.
Qed.
Lemma iscvalue_mkc_equality {p} :
forall t1 t2 T : @CTerm p, iscvalue (mkc_equality t1 t2 T).
Proof.
intro; destruct t1; destruct t2; destruct T; unfold iscvalue; simpl.
apply isvalue_equality; allrw @isprog_eq; auto.
apply isprogram_equality; sp.
Qed.
Lemma isvalue_function {p} :
forall (a : @NTerm p) v b, isprogram (mk_function a v b) -> isvalue (mk_function a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_product {p} :
forall (a : @NTerm p) v b, isprogram (mk_product a v b) -> isvalue (mk_product a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_isect {p} :
forall (a : @NTerm p) v b, isprogram (mk_isect a v b) -> isvalue (mk_isect a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_eisect {p} :
forall (a : @NTerm p) v b, isprogram (mk_eisect a v b) -> isvalue (mk_eisect a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_disect {p} :
forall (a : @NTerm p) v b, isprogram (mk_disect a v b) -> isvalue (mk_disect a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_set {p} :
forall (a : @NTerm p) v b, isprogram (mk_set a v b) -> isvalue (mk_set a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_tunion {p} :
forall (a : @NTerm p) v b, isprogram (mk_tunion a v b) -> isvalue (mk_tunion a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_w {p} :
forall (a : @NTerm p) v b, isprogram (mk_w a v b) -> isvalue (mk_w a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_m {p} :
forall (a : @NTerm p) v b, isprogram (mk_m a v b) -> isvalue (mk_m a v b).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram (mk_pw P ap A bp ba B cp ca cb C p)
-> isvalue (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp; constructor; sp.
Qed.
Lemma isvalue_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprogram (mk_pm P ap A bp ba B cp ca cb C p)
-> isvalue (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp; constructor; sp.
Qed.
Lemma implies_isvalue_function {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_function a v b).
Proof.
sp.
apply isvalue_function.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_function; sp.
Qed.
Lemma implies_isvalue_product {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_product a v b).
Proof.
sp.
apply isvalue_product.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_product; sp.
Qed.
Lemma implies_isvalue_isect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_isect a v b).
Proof.
sp.
apply isvalue_isect.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_isect; sp.
Qed.
Lemma implies_isvalue_eisect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_eisect a v b).
Proof.
sp.
apply isvalue_eisect.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_eisect; sp.
Qed.
Lemma implies_isvalue_disect {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_disect a v b).
Proof.
sp.
apply isvalue_disect.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_disect; sp.
Qed.
Lemma implies_isvalue_set {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_set a v b).
Proof.
sp.
apply isvalue_set.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_set; sp.
Qed.
Lemma implies_isvalue_tunion {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_tunion a v b).
Proof.
sp.
apply isvalue_tunion.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_tunion; sp.
Qed.
Lemma implies_isvalue_w {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_w a v b).
Proof.
sp.
apply isvalue_w.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_w; sp.
Qed.
Lemma implies_isvalue_m {p} :
forall (a : @NTerm p) v b,
isprog a
-> isprog_vars [v] b
-> isvalue (mk_m a v b).
Proof.
sp.
apply isvalue_m.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_m; sp.
Qed.
Lemma implies_isvalue_pw {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp,ba] B
-> isprog_vars [cp,ca,cb] C
-> isprog p
-> isvalue (mk_pw P ap A bp ba B cp ca cb C p).
Proof.
sp.
apply isvalue_pw.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_pw; sp.
Qed.
Lemma implies_isvalue_pm {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C p,
isprog P
-> isprog_vars [ap] A
-> isprog_vars [bp,ba] B
-> isprog_vars [cp,ca,cb] C
-> isprog p
-> isvalue (mk_pm P ap A bp ba B cp ca cb C p).
Proof.
sp.
apply isvalue_pm.
allrw @isprog_vars_eq; sp.
allrw @isprog_eq.
apply isprogram_pm; sp.
Qed.
Lemma iscvalue_mkc_function {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_function a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_function; sp.
Qed.
Hint Immediate iscvalue_mkc_function.
Lemma iscvalue_mkc_product {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_product a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_product; sp.
Qed.
Hint Immediate iscvalue_mkc_product.
Lemma iscvalue_mkc_isect {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_isect a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_isect; sp.
Qed.
Hint Immediate iscvalue_mkc_isect.
Lemma iscvalue_mkc_eisect {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_eisect a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_eisect; sp.
Qed.
Hint Immediate iscvalue_mkc_eisect.
Lemma iscvalue_mkc_disect {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_disect a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_disect; sp.
Qed.
Hint Immediate iscvalue_mkc_disect.
Lemma iscvalue_mkc_set {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_set a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_set; sp.
Qed.
Hint Immediate iscvalue_mkc_set.
Lemma iscvalue_mkc_tunion {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_tunion a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_tunion; sp.
Qed.
Hint Immediate iscvalue_mkc_tunion.
Lemma iscvalue_mkc_w {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_w a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_w; sp.
Qed.
Hint Immediate iscvalue_mkc_w.
Lemma iscvalue_mkc_m {p} :
forall (a : @CTerm p) v b, iscvalue (mkc_m a v b).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_m; sp.
Qed.
Hint Immediate iscvalue_mkc_m.
Lemma iscvalue_mkc_pw {p} :
forall (P : @CTerm p) ap A bp ba B cp ca cb C p,
iscvalue (mkc_pw P ap A bp ba B cp ca cb C p).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_pw; sp.
Qed.
Hint Immediate iscvalue_mkc_pw.
Lemma iscvalue_mkc_pm {p} :
forall (P : @CTerm p) ap A bp ba B cp ca cb C p,
iscvalue (mkc_pm P ap A bp ba B cp ca cb C p).
Proof.
sp; destruct_cterms; unfold iscvalue; simpl.
apply implies_isvalue_pm; sp.
Qed.
Hint Immediate iscvalue_mkc_pm.
(* ---------------------------------------------------- *)
Definition list_rel {A} {B} (R : A -> B -> Prop) (ll : list A) (lr : list B) :=
(length ll = length lr)
#
forall p1 p2 , LIn (p1, p2) (combine ll lr)
-> R p1 p2.
Definition default_nterm {o} : @NTerm o := mk_axiom.
Definition default_bt {o} : @BTerm o := bterm [] mk_axiom.
Definition bin_rel_nterm {o} := binrel_list (@default_nterm o).
Definition bin_rel_bterm {o} := binrel_list (@default_bt o).
(** gets the nth element of a list of bterms. if n is out of range, it returns the variable x
*)
Definition selectbt {p} (bts: list BTerm) (n:nat) : @BTerm p :=
nth n bts default_bt.
(* Howe defines T(L) as B_0(L) (no bterm constructor)
and T_0(L) as closed terms of T(L)
so, a term T_0(L) cannot have the vterm constructor
at the root
This a superset of T_0(L)
*)
Inductive not_vbterm {p} : @NTerm p -> Type :=
| nvbo : forall op bs, not_vbterm (oterm op bs)
| nvbs : forall f, not_vbterm (sterm f).
Hint Constructors not_vbterm.
(** this should not be required anymore. a closed NTerm is automatically not_vbterm. Proof below*)
Definition not_vbtermb {p} (t : @NTerm p) : bool :=
match t with
| vterm _ => false
| _ => true
end.
Theorem closed_notvb {p} : forall t: @NTerm p , closed t -> not_vbterm t.
Proof.
intros ? Hclose.
destruct t; allsimpl; auto.
unfold closed in Hclose. simpl in Hclose; ginv.
Qed.
Theorem selectbt_in {p} :
forall n (bts : list (@BTerm p)),
n < length bts -> LIn (selectbt bts n) bts.
Proof.
intros. unfold selectbt.
apply nth_in; auto.
Qed.
Lemma selectbt_cons {p} :
forall (bt : @BTerm p) bts n,
selectbt (bt :: bts) n = if beq_nat n 0 then bt else selectbt bts (n - 1).
Proof.
unfold selectbt; simpl; sp.
destruct n; simpl; sp.
destruct n; simpl; sp.
Qed.
(*
Theorem isprogram_bt_iff : forall (bt:BTerm ) , (isprogram_bt bt) <=>
forall (lnt : list NTerm) ,
(forall nt: NTerm, (LIn nt lnt) -> isprogram nt)
-> isprogram (apply_bterm bt lnt ).
intros. destruct bt as [lv nt].
induction nt as [v| c bts] using NTerm_better_ind;
[ Case_aux Case "vterm"
| Case_aux Case "oterm"
].
remember (memberb eq_var_dec v lv) as vinlv.
destruct vinlv. fold assert () in Heqvinlv.
sp_iff SCase.
SCase "->".
intros Hisp ? Hin.
*)
Lemma isvalue_wf {p} :
forall c (bts : list (@BTerm p)),
isvalue (oterm (Can c) bts)
-> map num_bvars bts = OpBindings (Can c).
Proof. intros ? ? Hval.
inverts Hval as Hpr. inverts Hpr as Hclose Hwf.
inverts Hwf; auto.
Qed.
Lemma isvalue_wf2 {p} : forall c (bts : list (@BTerm p)),
(isvalue (oterm (Can c) bts))
-> length bts= length(OpBindings (Can c)).
Proof. intros ? ? Hval. apply isvalue_wf in Hval.
(* fequalhyp H length. why does this fail*)
assert (length (map num_bvars bts) = length (OpBindings (Can c)))
as Hlen by (rewrite Hval; reflexivity) .
rewrite map_length in Hlen. auto.
Qed.
Lemma isprogram_wf3 {p} : forall o (bts : list (@BTerm p)),
(isprogram (oterm o bts))
-> forall n, (n<length bts) -> (num_bvars (selectbt bts n))= nth n (OpBindings o) 0.
Proof.
intros ? ? Hprog. apply isprogram_ot_iff in Hprog. repnd.
intros ? Hlt.
assert(nth n (map num_bvars bts) 0= nth n (OpBindings o) 0)
as Hnth by (rewrite Hprog0; reflexivity).
unfold selectbt.
instlemma (@map_nth
BTerm nat num_bvars
bts default_bt) as Hmapn.
assert((@num_bvars p default_bt) = 0) as h by sp.
rewrite h in Hmapn.
rewrite Hmapn in Hnth. auto.
Qed.
Lemma isvalue_wf3 {p} : forall o (bts : list (@BTerm p)),
(isvalue (oterm o bts))
-> forall n, (n<length bts) -> (num_bvars (selectbt bts n))= nth n (OpBindings o) 0.
Proof.
intros ? ? Hval ? Hlt.
inverts Hval as Hprog; apply @isprogram_wf3 with (n:=n) in Hprog; auto.
Qed.
Theorem var_not_prog {p} : forall v, @isprogram p (vterm v) -> void.
Proof.
unfold not. intros v Hpr.
inversion Hpr as [Hclose ?].
unfold closed in Hclose. simpl in Hclose. inversion Hclose.
Qed.
Lemma implies_isprogram_bt {p} :
forall bts : list (@BTerm p),
(forall l : BTerm, LIn l bts -> bt_wf l)
-> flat_map free_vars_bterm bts = []
-> forall bt : BTerm, LIn bt bts -> isprogram_bt bt.
Proof.
intros bts Hbf Hflat ? Hin.
unfold isprogram_bt, closed_bt; split; auto.
rw flat_map_empty in Hflat. apply Hflat; auto.
Qed.
Theorem ntbf_wf {p} :
forall nt : @NTerm p, (bt_wf (bterm [] nt)) -> nt_wf nt.
Proof.
introv Hin. inverts Hin. auto.
Qed.
Lemma implies_isprogram_bt0 {p} :
forall t : @NTerm p,
isprogram t
-> isprogram_bt (bterm [] t).
Proof.
unfold isprogram_bt, closed_bt, isprogram, closed; simpl; sp.
Qed.
Theorem is_program_ot_bts0 {p} :
forall o (nt : @NTerm p),
isprogram nt
-> OpBindings o = [0]
-> isprogram (oterm o [bterm [] nt]).
Proof.
introv Hpr Hop. allunfold @isprogram. repnd. split;auto. unfold closed. simpl.
rewrite app_nil_r. rewrite remove_var_nil. sp.
constructor; sp; allsimpl; sp; subst; sp.
Qed.
Theorem is_program_ot_nth_nobnd {p} :
forall o (nt1 : @NTerm p) bts,
isprogram (oterm o bts)
-> LIn (bterm [] nt1) bts
-> isprogram nt1.
Proof. intros ? ? ? Hisp Hin. apply isprogram_ot_iff in Hisp. repnd.
apply Hisp in Hin. inverts Hin as Hclose Hbf. inverts Hbf.
unfold closed_bt in Hclose. simpl in Hclose.
rewrite remove_var_nil in Hclose. split; auto.
Qed.
Theorem is_program_ot_fst_nobnd {p} :
forall o (nt1 : @NTerm p) bts,
isprogram (oterm o ((bterm [] nt1):: bts))
-> isprogram nt1.
Proof.
intros ? ? ? Hisp.
apply @is_program_ot_nth_nobnd with (nt1:=nt1) in Hisp; sp.
Qed.
Theorem is_program_ot_snd_nobnd {p} :
forall o bt1 (nt2 : @NTerm p) bts,
isprogram (oterm o ((bt1)::(bterm [] nt2):: bts))
-> isprogram nt2.
Proof. intros ? ? ? ? Hisp.
apply is_program_ot_nth_nobnd with (nt1:=nt2) in Hisp; simpl; sp.
Qed.
Theorem is_program_ot_subst1 {p} :
forall o (nt1 : @NTerm p) bts nt1r,
isprogram (oterm o ((bterm [] nt1):: bts))
-> isprogram nt1r
-> isprogram (oterm o ((bterm [] nt1r):: bts)).
Proof. intros ? ? ? ? Hisp Hispst. unfold isprogram.
unfold closed. simpl.
inverts Hisp as Hclos Hisp. unfold closed in Hclos. simpl in Hclos.
apply app_eq_nil in Hclos. repnd. rewrite remove_var_nil in Hclos0.
inverts Hispst as Hclosst Hispst. unfold closed in Hclosst.
rewrite remove_var_nil. rewrite Hclosst. rewrite Hclos. split;auto.
invertsn Hisp. constructor;auto.
intros ? Hin. inverts Hin. constructor; auto.
apply Hisp. right; auto.
Qed.
Theorem is_program_ot_subst2 {p} :
forall o bt1 (nt2 : @NTerm p) bts nt2r,
isprogram (oterm o (bt1::(bterm [] nt2):: bts))
-> isprogram nt2r
-> isprogram (oterm o (bt1::(bterm [] nt2r):: bts)).
Proof. intros ? ? ? ? ? Hisp Hispst. unfold isprogram.
unfold closed. simpl.
inverts Hisp as Hclos Hisp. inverts Hispst as Hclosst Hwfst.
allunfold @closed. simpl.
unfold closed in Hclos. allsimpl.
simpl_vlist. rewrite Hclosst. rewrite Hclos0.
simpl. split;auto.
inverts Hisp as Hisp Hm. constructor;simpl; auto.
intros ? Hin. dorn Hin;subst;auto. apply Hisp; auto.
left; auto.
dorn Hin; subst; auto.
apply Hisp. right;right;auto.
Qed.
Theorem is_program_ot_nth_wf {p} :
forall lv o (nt1 : @NTerm p) bts,
isprogram (oterm o bts)
-> LIn (bterm lv nt1) bts
-> nt_wf nt1.
Proof. intros ? ? ? ? Hisp Hin. apply isprogram_ot_iff in Hisp. repnd.
assert (isprogram_bt (bterm lv nt1)) as Hass by (apply Hisp; auto).
inverts Hass as Hass Hbt. inversion Hbt; auto.
Qed.
Lemma combine_vars_map_sp {p} :
forall vars,
combine vars (map vterm vars) = map (fun v => (v, @vterm p v)) vars.
Proof.
induction vars; simpl; sp.
rewrite IHvars; sp.
Qed.
Lemma combine_vars_map :
forall A,
forall f : NVar -> A,
forall vars,
combine vars (map f vars) = map (fun v => (v, f v)) vars.
Proof.
induction vars; simpl; sp.
rewrite IHvars; sp.
Qed.
Theorem in_selectbt {p} :
forall (bt : @BTerm p) bts,
LIn bt bts ->
{n : nat $ n < length bts # selectbt bts n = bt}.
Proof.
intros ? ? Hin. induction bts. inverts Hin.
invertsn Hin.
- exists 0. split; simpl; auto. omega.
- destruct IHbts; auto. exists (S x). repnd.
split; simpl; try omega. auto.
Qed.
(**useful for rewriting in complicated formulae*)
Theorem ntot_wf_iff {p} :
forall o (bts : list (@BTerm p)),
nt_wf (oterm o bts)
<=> map num_bvars bts = OpBindings o
# forall n : nat,
n < length bts -> bt_wf (selectbt bts n).
Proof. introv. sp_iff Case; introv H.
Case "->". inverts H as Hbf Hmap. split; auto.
introv Hlt. apply Hbf. apply selectbt_in; auto.
Case "<-". repnd. constructor; auto.
introv Hin. apply in_selectbt in Hin.
exrepnd. rw <- Hin0;auto.
Qed.
Definition nvarxbt {p} : @BTerm p := bterm [] (vterm nvarx) .
Lemma wf_cvterm {p} :
forall vs : list NVar,
forall t : @CVTerm p vs,
wf_term (get_cvterm vs t).
Proof.
destruct t; simpl.
rw @isprog_vars_eq in i; sp.
rw @wf_term_eq; sp.
Qed.
Lemma isprogram_get_cterm {p} :
forall a : @CTerm p, isprogram (get_cterm a).
Proof.
destruct a; sp; simpl.
rw @isprogram_eq; sp.
Qed.
Hint Immediate isprogram_get_cterm.
Lemma oterm_eq {p} :
forall (o1 o2 : @Opid p) l1 l2,
o1 = o2
-> l1 = l2
-> oterm o1 l1 = oterm o2 l2.
Proof.
sp; allrw; sp.
Qed.
Lemma bterm_eq {p} :
forall l1 l2 (n1 n2 : @NTerm p),
l1 = l2
-> n1 = n2
-> bterm l1 n1 = bterm l2 n2.
Proof.
sp; allrw; sp.
Qed.
Theorem selectbt_map {p} :
forall lbt n (f: @BTerm p -> @BTerm p),
n<length lbt
-> selectbt (map f lbt) n = f (selectbt lbt n).
Proof.
induction lbt; introv Hlt. inverts Hlt.
simpl. destruct n; subst. reflexivity.
allunfold @selectbt. allsimpl.
assert (n < (length lbt)) by omega.
auto.
Qed.
Theorem eq_maps_bt {p} :
forall (B : Type) (f : BTerm -> B)
(g : BTerm -> B) (la lc : list (@BTerm p)),
length la = length lc
-> (forall n : nat, n < length la
-> f (selectbt la n) = g (selectbt lc n))
-> map f la = map g lc.
Proof. unfold selectbt. introv H2 H3. apply eq_maps2 in H3; auto.
Qed.
Lemma vterm_inj {p} : injective_fun (@vterm p).
Proof.
introv Hf. inverts Hf. auto.
Qed.
Lemma map_eq_lift_vterm {p} :
forall lvi lvo,
map (@vterm p) lvi = map vterm lvo -> lvi = lvo.
Proof.
intros.
apply map_eq_injective with (f:=@vterm p); auto.
exact vterm_inj.
Qed.
Fixpoint no_seq {o} (t : @NTerm o) : bool :=
match t with
| vterm _ => true
| sterm f => false
| oterm op bs => no_seq_o op && ball (map no_seq_b bs)
end
with no_seq_b {o} (b : @BTerm o) : bool :=
match b with
| bterm _ t => no_seq t
end.
Lemma lin_lift_vterm {p} :
forall v lv,
LIn v lv <=> LIn (@vterm p v) (map vterm lv).
Proof.
induction lv; [sp | ]. simpl.
rw <- IHlv; split; intros hp; try (dorn hp); sp; subst; sp.
inverts hp. sp.
Qed.
Definition all_vars_bt {p} (bt : @BTerm p) :=
free_vars_bterm bt ++ bound_vars_bterm bt.
Lemma all_vars_ot {p} : forall (o : @Opid p) lbt, all_vars (oterm o lbt) =
flat_map all_vars_bt lbt.
Proof.
intros. unfold all_vars. simpl. unfold all_vars_bt.
Abort. (** they are only equal as bags*)
Theorem nil_remove_nvars_iff :
forall l1 l2 : list NVar,
(remove_nvars l1 l2) = [] <=> (forall x : NVar, LIn x l2 -> LIn x l1).
Proof.
intros. rw <- null_iff_nil. apply null_remove_nvars.
Qed.
Theorem nil_rv_single_iff: forall lv v ,
(remove_nvars lv [v]) = [] <=> (LIn v lv).
Proof.
intros. rw <- null_iff_nil. rw null_remove_nvars.
split; intro Hyp.
apply Hyp. left. auto.
introv Hin. apply in_list1 in Hin; subst; auto.
Qed.
Theorem selectbt_eq_in {p} :
forall lv (nt : @NTerm p) lbt n,
bterm lv nt = selectbt lbt n
-> n < length lbt
-> LIn (bterm lv nt) lbt.
Proof.
introv Heq Hlt. rw Heq.
apply selectbt_in; trivial.
Qed.
Lemma flat_map_closed_terms {p} :
forall lnt : list (@NTerm p), lforall closed lnt
-> flat_map free_vars lnt = [].
Proof.
unfold lforall, closed. introv Hfr.
apply flat_map_empty. trivial.
Qed.
Lemma flat_map_progs {p} :
forall lnt : list (@NTerm p), lforall isprogram lnt
-> flat_map free_vars lnt = [].
Proof.
unfold lforall, closed. introv Hfr.
apply flat_map_empty. introv Hin.
apply Hfr in Hin. inverts Hin. auto.
Qed.
Theorem disjoint_lbt_bt {p} :
forall vs lbt lv (nt : @NTerm p),
disjoint vs (flat_map bound_vars_bterm lbt)
-> LIn (bterm lv nt) lbt
-> disjoint vs lv.
Proof.
introv Hink1 Hin.
apply disjoint_sym in Hink1; rw disjoint_flat_map_l in Hink1.
apply Hink1 in Hin.
simpl in Hin. rw disjoint_app_l in Hin.
repnd; apply disjoint_sym. trivial.
Qed.
Tactic Notation "disjoint_reasoningv" :=
(allunfold all_vars); repeat( progress disjoint_reasoning).
Lemma isprog_vars_top {p} :
forall vs, @isprog_vars p vs mk_top.
Proof.
intro; rw @isprog_vars_eq; simpl.
repeat (rw remove_nvars_nil_l); repeat (rw app_nil_r); sp.
rw @nt_wf_eq; sp.
Qed.
Hint Immediate isprog_vars_top.
Lemma isprog_vars_mk_false {p} :
forall vs, @isprog_vars p vs mk_false.
Proof.
intro; rw @isprog_vars_eq; simpl.
repeat (rw remove_nvars_nil_l); repeat (rw app_nil_r); sp.
rw @nt_wf_eq; sp.
Qed.
Hint Immediate isprog_vars_mk_false.
Definition selectnt {p} (n:nat) (lnt : list NTerm): @NTerm p :=
nth n lnt (vterm nvarx).
Inductive nt_wf2 {p} : @NTerm p -> [univ] :=
| wfvt2 : forall nv : NVar, nt_wf2 (vterm nv)
| wfst2: forall f,
(forall n, nt_wf2 (f n) # closed (f n) # noutokens (f n))
-> nt_wf2 (sterm f)
| wfot2 : forall (o : Opid) (lnt : list BTerm),
length lnt = length (OpBindings o)
-> (forall n, n < (length lnt) ->
num_bvars (selectbt lnt n) = nth n (OpBindings o) 0
# bt_wf2 (selectbt lnt n))
-> nt_wf2 (oterm o lnt)
with bt_wf2 {p} : @BTerm p -> [univ] :=
wfbt2 : forall (lnv : list NVar) (nt : NTerm),
nt_wf2 nt -> bt_wf2 (bterm lnv nt).
Hint Constructors nt_wf2.
(** mainly for convenience in proofs *)
Theorem selectbt_in2 {p} :
forall (n : nat) (bts : list (@BTerm p)),
n < length bts -> { bt : BTerm & (LIn bt bts # (selectbt bts n)=bt) }.
Proof.
intros. exists (selectbt bts n).
split;auto. apply selectbt_in; trivial.
Defined.
Lemma nt_wf_nt_wf2 {p} : forall t : @NTerm p, (nt_wf t) <=> (nt_wf2 t).
Proof.
assert (0= num_bvars (bterm [] (@mk_axiom p))) as XX by auto.
nterm_ind1 t as [|f ind| o lbt Hind] Case; split; introv Hyp; auto.
- Case "sterm".
inversion Hyp as [|? imp|]; subst.
constructor; introv.
pose proof (imp n) as h; repnd; dands; auto.
apply ind; auto.
- Case "sterm".
inversion Hyp as [|? imp|]; subst.
constructor; introv.
pose proof (imp n) as h; repnd; dands; auto.
apply ind; auto.
- Case "oterm".
inverts Hyp as Hl Hyp. constructor. apply_length Hyp;sp.
introv hlt. unfold selectbt. rw <- Hyp.
rw XX.
rw map_nth; sp;[].
fold (selectbt lbt n).
pose proof (selectbt_in2 n lbt hlt) as Hbt.
exrepnd. destruct bt as [lv nt].
applydup Hind in Hbt1.
rw Hbt0. constructor.
apply Hl in Hbt1. inverts Hbt1.
sp3.
- inverts Hyp as Hl Hyp. constructor.
+ introv Hin. apply in_selectbt in Hin; auto;[].
exrepnd. applydup Hyp in Hin1.
rw Hin0 in Hin2. destruct l as [lv nt].
constructor. exrepnd. invertsn Hin2.
applysym @selectbt_in in Hin1. rw Hin0 in Hin1.
apply Hind in Hin1. sp3.
+ eapply (tiff_snd (eq_list2 _ 0 _ _)). rw map_length.
split; auto;[]. introv Hlt. apply Hyp in Hlt.
repnd. rw <- Hlt0.
rw XX. rw map_nth. sp.
Qed.
Lemma isprog_vars_decide {p} :
forall vs (a : @NTerm p) v1 a1 v2 a2,
isprog_vars vs a
-> isprog_vars (v1 :: vs) a1
-> isprog_vars (v2 :: vs) a2
-> isprog_vars vs (mk_decide a v1 a1 v2 a2).
Proof.
introv ipa ipa1 ipa2.
allrw @isprog_vars_eq; allsimpl.
allrw subvars_eq.
unfold subset in ipa, ipa1, ipa2; exrepd; sp.
unfold subset; introv i.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff;
allsimpl; sp;
discover; sp; subst; sp.
repeat (constructor; simpl; sp; subst).
Qed.
Lemma isprog_vars_spread {p} :
forall vs (a : @NTerm p) v1 v2 b,
isprog_vars vs a
-> isprog_vars (v1 :: v2 :: vs) b
-> isprog_vars vs (mk_spread a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw subvars_prop; repnd.
allrw remove_nvars_nil_l.
allrw app_nil_r.
dands.
introv i.
allrw in_app_iff.
allrw in_remove_nvars; allsimpl.
repdors; sp.
allrw not_over_or; repnd.
discover; sp.
constructor; simpl; try (constructor).
sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_vars_dsup {p} :
forall vs (a : @NTerm p) v1 v2 b,
isprog_vars vs a
-> isprog_vars (v1 :: v2 :: vs) b
-> isprog_vars vs (mk_dsup a v1 v2 b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw subvars_prop; repnd.
allrw remove_nvars_nil_l.
allrw app_nil_r.
dands.
introv i.
allrw in_app_iff.
allrw in_remove_nvars; allsimpl.
repdors; sp.
allrw not_over_or; repnd.
discover; sp.
constructor; simpl; try (constructor).
sp; subst; sp; constructor; sp.
Qed.
Lemma isprog_vars_cons {p} :
forall v vs (t : @NTerm p), isprog_vars vs t -> isprog_vars (v :: vs) t.
Proof.
introv ip.
allrw @isprog_vars_eq.
allrw subvars_eq; sp.
Qed.
Definition mkc_ite_vars {p} (vs : list NVar) (a b c : @CVTerm p vs) :=
let (t1,x1) := a in
let (t2,x2) := b in
let (t3,x3) := c in
exist (isprog_vars vs)
(mk_decide t1 nvarx t2 nvarx t3)
(isprog_vars_decide
vs
t1 nvarx t2 nvarx t3
x1
(isprog_vars_cons nvarx vs t2 x2)
(isprog_vars_cons nvarx vs t3 x3)).
Definition mkc_lamc {p} v (t :@CTerm p) := mkc_lam v (mk_cv [v] t).
Theorem isvalue_inl {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_inl a).
Proof.
intros; constructor; simpl; auto.
fold (mk_inl a).
apply isprogram_inl; auto.
Qed.
Lemma iscvalue_mkc_inl {p} :
forall t : @CTerm p, iscvalue (mkc_inl t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_inl; allrw @isprog_eq; auto.
Qed.
Theorem isvalue_inr {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_inr a).
Proof.
intros; constructor; simpl; auto. fold (mk_inr a).
apply isprogram_inr; auto.
Qed.
Lemma iscvalue_mkc_inr {p} :
forall t : @CTerm p, iscvalue (mkc_inr t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_inr; allrw @isprog_eq; auto.
Qed.
Theorem isvalue_sup {p} :
forall a b : @NTerm p, isprogram a -> isprogram b -> isvalue (mk_sup a b).
Proof.
intros; constructor; simpl; auto. fold (mk_sup a b).
apply isprogram_sup; auto.
Qed.
Lemma iscvalue_mkc_sup {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_sup t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_sup; allrw @isprog_eq; auto.
Qed.
Theorem isvalue_refl {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_refl a).
Proof.
intros; constructor; simpl; auto. fold (mk_refl a).
apply isprogram_refl; auto.
Qed.
Hint Resolve isvalue_refl : slow.
Lemma iscvalue_mkc_refl {p} :
forall t1 : @CTerm p, iscvalue (mkc_refl t1).
Proof.
intro; destruct t1; unfold iscvalue; simpl.
apply isvalue_refl; allrw @isprog_eq; auto.
Qed.
Hint Resolve iscvalue_mkc_refl : slow.
Definition is_inl {p} (t : @CTerm p) :=
match get_cterm t with
| vterm _ => false
| sterm _ => false
| oterm (Can (NInj NInl)) _ => true
| oterm _ _ => false
end.
Definition is_inr {p} (t : @CTerm p) :=
match get_cterm t with
| vterm _ => false
| sterm _ => false
| oterm (Can (NInj NInr)) _ => true
| oterm _ _ => false
end.
Lemma get_cterm_mkc_void {p} :
get_cterm mkc_void = @mk_void p.
Proof.
unfold mkc_void; simpl; sp.
Qed.
Lemma isvalue_mk_void {p} :
@isvalue p mk_void.
Proof.
apply isvalue_approx; sp.
Qed.
Hint Immediate isvalue_mk_void.
Definition mkc_idv {p} v : @CTerm p := mkc_lam v (mkc_var v).
Definition mkc_botv {p} v : @CTerm p := mkc_fix (mkc_idv v).
Definition mkc_voidv {p} v : @CTerm p := mkc_approx mkc_axiom (mkc_botv v).
Lemma wf_apply_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_apply a b).
Proof.
introv; split; intro i.
apply wf_apply; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd b)); intros k1 k2.
repeat (dest_imp k1 hyp).
repeat (dest_imp k2 hyp).
inversion k1; subst.
inversion k2; subst; sp.
Qed.
Lemma wf_apply2_iff {p} :
forall a b c : @NTerm p,
(wf_term a # wf_term b # wf_term c) <=> wf_term (mk_apply2 a b c).
Proof.
introv.
unfold mk_apply2.
allrw <- @wf_apply_iff; split; sp.
Qed.
Lemma isprog_vars_apply {p} :
forall (f a : @NTerm p) vs,
isprog_vars vs (mk_apply f a) <=> (isprog_vars vs f # isprog_vars vs a).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
rw subvars_app_l.
allrw <- @wf_term_eq.
allrw <- @wf_apply_iff; split; sp.
Qed.
Lemma isprog_vars_apply2 {p} :
forall (f a b :@NTerm p) vs,
isprog_vars vs (mk_apply2 f a b)
<=>
(isprog_vars vs f # isprog_vars vs a # isprog_vars vs b).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
repeat (rw app_nil_r).
repeat (rw subvars_app_l).
allrw <- @wf_term_eq.
allrw <- @wf_apply2_iff; split; sp.
Qed.
Lemma wf_eapply_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_eapply a b).
Proof.
introv; split; intro i.
apply wf_eapply; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd b)); intros k1 k2.
repeat (dest_imp k1 hyp).
repeat (dest_imp k2 hyp).
inversion k1; subst.
inversion k2; subst; sp.
Qed.
Lemma isprog_vars_eapply {p} :
forall (f a : @NTerm p) vs,
isprog_vars vs (mk_eapply f a) <=> (isprog_vars vs f # isprog_vars vs a).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
rw subvars_app_l.
allrw <- @wf_term_eq.
allrw <- @wf_eapply_iff; split; sp.
Qed.
(*
Lemma wf_apseq_iff {p} :
forall f (a : @NTerm p), wf_term a <=> wf_term (mk_apseq f a).
Proof.
introv; split; intro i.
apply wf_apseq; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intros k1.
repeat (dest_imp k1 hyp).
inversion k1; subst; sp.
Qed.
Lemma isprog_vars_apseq {p} :
forall f (a : @NTerm p) vs,
isprog_vars vs (mk_apseq f a) <=> isprog_vars vs a.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw @remove_nvars_nil_l).
rw @app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_apseq_iff; split; sp.
Qed.
*)
Lemma wf_parallel_iff {p} :
forall (a b : @NTerm p),
wf_term (mk_parallel a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro i; repnd; try (apply wf_parallel; complete sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl; clear i.
pose proof (k (nobnd a)) as h1; autodimp h1 hyp.
pose proof (k (nobnd b)) as h2; autodimp h2 hyp.
allrw @bt_wf_iff; dands; auto.
Qed.
Lemma isprog_vars_parallel {p} :
forall (a b : @NTerm p) vs,
isprog_vars vs (mk_parallel a b)
<=> (isprog_vars vs a # isprog_vars vs b).
Proof.
introv.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l.
allrw @nt_wf_eq.
allrw @wf_parallel_iff.
split; sp.
Qed.
Definition mkc_parallel {p} (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_parallel a b) (isprog_parallel a b x y).
Lemma mkc_parallel_eq {p} :
forall t1 t2 t3 t4 : @CTerm p,
mkc_parallel t1 t2 = mkc_parallel t3 t4 -> t1 = t3 # t2 = t4.
Proof.
introv e; destruct_cterms; allsimpl.
inversion e; subst.
irr; sp.
Qed.
Theorem wf_pertype_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_pertype a).
Proof.
intros; split; intro i.
apply wf_pertype; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_pertype {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_pertype f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_pertype_iff; split; sp.
Qed.
Theorem wf_partial_iff {p} :
forall a : @NTerm p, wf_term a <=> wf_term (mk_partial a).
Proof.
intros; split; intro i.
apply wf_partial; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)); intro j.
repeat (dest_imp j hyp).
inversion j; subst; sp.
Qed.
Lemma isprog_vars_partial {p} :
forall (f : @NTerm p) vs,
isprog_vars vs (mk_partial f) <=> isprog_vars vs f.
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
rw app_nil_r.
allrw <- @wf_term_eq.
allrw <- @wf_partial_iff; split; sp.
Qed.
Lemma isprog_vars_weak_l {p} :
forall vs v (t : @NTerm p),
isprog_vars vs t -> isprog_vars (snoc vs v) t.
Proof.
introv i.
allrw @isprog_vars_eq; sp.
apply subvars_snoc_weak; sp.
Qed.
Lemma isprog_vars_weak_r {p} :
forall vs v,
isprog_vars (snoc vs v) (@mk_var p v).
Proof.
introv.
allrw @isprog_vars_eq; sp; allsimpl.
rw subvars_singleton_l; rw in_snoc; sp.
Qed.
Hint Immediate isprog_vars_weak_r.
Lemma subset_snoc_swap_r :
forall T vs vs1 vs2 (v : T),
subset vs (snoc vs1 v ++ vs2)
<=>
subset vs (snoc (vs1 ++ vs2) v).
Proof.
introv; unfold subset; split; intro s; introv i;
apply s in i; allrw in_snoc; allrw in_app_iff; allrw in_snoc; sp.
Qed.
Lemma subvars_snoc_swap_r :
forall vs vs1 vs2 v,
subvars vs (snoc vs1 v ++ vs2)
<=>
subvars vs (snoc (vs1 ++ vs2) v).
Proof.
introv.
allrw subvars_eq.
apply subset_snoc_swap_r; sp.
Qed.
Lemma isprog_vars_snoc_swap {p} :
forall vs1 vs2 v (t : @NTerm p),
isprog_vars (snoc vs1 v ++ vs2) t
<=>
isprog_vars (snoc (vs1 ++ vs2) v) t.
Proof.
introv.
allrw @isprog_vars_eq; split; intro i; repnd; sp.
apply subvars_snoc_swap_r; sp.
apply subvars_snoc_swap_r; sp.
Qed.
Lemma isprog_vars_lam {p} :
forall vs v (b : @NTerm p),
isprog_vars (v :: vs) b
-> isprog_vars vs (mk_lam v b).
Proof.
introv ipv.
allrw @isprog_vars_eq; simpl.
rw app_nil_r.
allrw subvars_prop; sp.
allrw in_remove_nvars; allrw in_single_iff; allsimpl; sp.
apply_in_hyp pp; sp.
constructor; simpl; sp; subst.
constructor; sp.
Qed.
Lemma isprog_vars_isect {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_isect a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_eisect {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_eisect a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_base {p} :
forall vs, @isprog_vars p vs mk_base.
Proof.
intros.
rw @isprog_vars_eq; simpl; sp.
constructor; simpl; sp.
Qed.
Hint Immediate isprog_vars_base.
Lemma isprog_vars_free_from_atom {p} :
forall vs (a b T : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs T
-> isprog_vars vs (mk_free_from_atom a b T).
Proof.
introv ipa ipb ipt.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_efree_from_atom {p} :
forall vs (a b T : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs T
-> isprog_vars vs (mk_efree_from_atom a b T).
Proof.
introv ipa ipb ipt.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_free_from_atoms {p} :
forall vs (a b : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_free_from_atoms a b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_equality {p} :
forall vs (a b T : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs T
-> isprog_vars vs (mk_equality a b T).
Proof.
introv ipa ipb ipt.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_requality {p} :
forall vs (a b T : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs T
-> isprog_vars vs (mk_requality a b T).
Proof.
introv ipa ipb ipt.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_tequality {p} :
forall vs (a b : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_tequality a b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_mk_var {p} :
forall vs v, LIn v vs -> isprog_vars vs (@mk_var p v).
Proof.
intros.
rw @isprog_vars_eq; simpl; rw subvars_singleton_l; sp.
Qed.
Lemma isvalue_mk_unit {p} :
@isvalue p mk_unit.
Proof.
apply isvalue_approx; sp; apply isprogram_axiom.
Qed.
Hint Immediate isvalue_mk_unit.
Lemma mkc_void_eq_mkc_false {p} :
@mkc_void p = mkc_false.
Proof.
apply cterm_eq; auto.
Qed.
Lemma iscvalue_mkc_false {p} :
@iscvalue p mkc_false.
Proof.
unfold iscvalue, mkc_false; simpl; sp.
Qed.
Hint Immediate iscvalue_mkc_false.
Lemma isprogram_mk_true {p} :
@isprogram p mk_true.
Proof.
unfold mk_true.
apply isprogram_approx.
apply isprogram_axiom.
apply isprogram_axiom.
Qed.
Hint Immediate isprogram_mk_true.
Lemma isprog_mk_true {p} :
@isprog p mk_true.
Proof.
rw @isprog_eq.
apply isprogram_mk_true.
Qed.
Hint Immediate isprog_mk_true.
Definition mkc_true {p} : @CTerm p := exist isprog mk_true isprog_mk_true.
Lemma iscvalue_mkc_true {p} :
@iscvalue p mkc_true.
Proof.
unfold iscvalue, mkc_true; simpl; sp.
Qed.
Hint Immediate iscvalue_mkc_false.
Definition mkc_top {p} : @CTerm p :=
mkc_isect mkc_false nvarx (mk_cv [nvarx] mkc_false).
Lemma get_cterm_mkc_top {p} :
get_cterm mkc_top = @mk_top p.
Proof. sp. Qed.
Lemma mkc_true_eq {p} :
@mkc_true p = mkc_approx mkc_axiom mkc_axiom.
Proof.
apply cterm_eq; auto.
Qed.
Ltac rwselectbt :=
match goal with
|[ H1: bterm ?lv ?nt = selectbt ?lbt ?n , H2 : context [selectbt ?lbt ?n] |- _ ] => rewrite <- H1 in H2
|[ H1: selectbt ?lbt ?n = bterm ?lv ?nt , H2 : context [selectbt ?lbt ?n] |- _ ] => rewrite H1 in H2
|[ H1: bterm ?lv ?nt = selectbt ?lbt ?n |- context [selectbt ?lbt ?n] ] => rewrite <- H1
|[ H1: selectbt ?lbt ?n = bterm ?lv ?nt |- context [selectbt ?lbt ?n] ] => rewrite H1
end.
Lemma bin_rel_nterm_if_combine {o} :
forall (ts1 ts2 : list (@NTerm o)) R,
(forall t1 t2, LIn (t1,t2) (combine ts1 ts2) -> R t1 t2)
-> length ts1 = length ts2
-> bin_rel_nterm R ts1 ts2.
Proof.
unfold bin_rel_nterm, binrel_list; introv h e; dands; auto.
introv k.
apply h.
rw <- combine_nth; auto.
apply nth_in; auto.
rw combine_length; rw <- e.
rw Min.min_idempotent; auto.
Qed.
Theorem isprogram_ot_implies_eauto2 {p} :
forall (o : @Opid p) bts,
isprogram (oterm o bts)
-> (forall n, n< length bts -> isprogram_bt (selectbt bts n)).
Proof.
introv Hp Hlt. apply isprogram_ot_iff in Hp.
apply selectbt_in in Hlt. exrepnd.
eauto with slow.
Qed.
Lemma isprogram_bt_nobnd {p} :
forall (t : @NTerm p),
isprogram_bt (bterm [] t)
-> isprogram (t).
Proof.
unfold isprogram_bt, closed_bt, isprogram, closed; introns Hxx; spc; allsimpl.
inverts Hxx;sp.
Qed.
Lemma mkc_unit_eq_mkc_true {p} :
@mkc_unit p = mkc_true.
Proof.
apply cterm_eq; auto.
Qed.
Lemma free_vars_list_app {p} :
forall (ts1 ts2 : list (@NTerm p)),
free_vars_list (ts1 ++ ts2)
= free_vars_list ts1 ++ free_vars_list ts2.
Proof.
induction ts1; simpl; sp.
rw IHts1; simpl.
rw app_assoc; sp.
Qed.
Tactic Notation "ntermd" ident(h) "as" simple_intropattern(I) ident(c) :=
destruct h as I;
[ Case_aux c "vterm"
| Case_aux c "sterm"
| Case_aux c "oterm"
].
Ltac prove_or :=
try (left;cpx;fail);
try (right;cpx;fail);
try (left;left;cpx;fail);
try (left;right;cpx;fail);
try (right;left;cpx;fail);
try (right;right;cpx;fail).
Ltac fold_selectbt :=
match goal with
| [ |- context [nth ?n ?lbt (bterm [] mk_axiom)] ] => fold (selectbt lbt n)
| [ |- context [nth ?n ?lbt default_bt] ] => fold (selectbt lbt n)
end.
Hint Resolve nt_wf_implies : slow.
Hint Resolve nt_wf_eq: slow.
Hint Resolve is_program_ot_nth_nobnd : slow.
Lemma isprog_ntwf_eauto {p} : forall t : @NTerm p, isprogram t -> nt_wf t.
Proof. unfold isprogram. spc.
Qed.
Hint Resolve isprog_ntwf_eauto : slow.
Theorem isprogram_ot_if_eauto {p} :
forall (o : @Opid p) bts,
map num_bvars bts = OpBindings o
-> (forall bt, LIn bt bts -> isprogram_bt bt)
-> isprogram (oterm o bts).
Proof.
intros. apply isprogram_ot_iff;spc.
Qed.
Lemma isprogramd {p} :
forall v,
@isprogram p v
-> {f : ntseq & v = sterm f}
[+] {o : Opid $ {lbt : list BTerm $ v = oterm o lbt}}.
Proof.
introv Hpr.
invertsn Hpr.
destruct v; inverts Hpr.
- left; eexists; eauto.
- right; eexists; eexists; eauto.
Qed.
Lemma isprogram_noncan {p} :
forall v,
@isprogram p v
-> (isvalue v [+] isnoncan v [+] isexc v [+] isabs v [+] isseq v).
Proof.
introv Hp.
applydup @isprogramd in Hp.
repndors; exrepnd; subst; cpx.
destruct o; cpx.
Qed.
(*
Ltac d_isnoncan H :=
match type of H with
isnoncan ?t => let tlbt := fresh t "lbt" in let tnc := fresh t "nc" in
let tt := fresh "temp" in
destruct t as [tt|tt tlbt];[inverts H as H; fail|];
destruct tt as [tt|tnc]; [inverts H as H; fail|]
end.
*)
Hint Resolve isprogram_fix : slow.
Lemma fold_combine : forall {A B} (v:A) (t:B),
[(v,t)] = (combine [v] [t]).
Proof.
intros. simpl. auto.
Qed.
Lemma nvarx_nvary : nvarx <> nvary.
Proof.
allunfold nvarx.
allunfold nvary.
introv Hinc.
inverts Hinc.
Qed.
Hint Immediate nvarx_nvary : slow.
Lemma noncan_not_value {p} :
forall e : @NTerm p,
isnoncan e
-> isvalue e
-> False.
Proof.
introv Hisnc Hisv.
destruct e as [|?|o lbt]; allsimpl; cpx.
destruct o; cpx.
inverts Hisv; allsimpl; tcsp.
Qed.
Theorem isprogram_ot_if_eauto2 {p} :
forall (o : @Opid p) bts,
map num_bvars bts = OpBindings o
-> (forall n, n< length bts -> isprogram_bt (selectbt bts n))
-> isprogram (oterm o bts).
Proof.
introv Hn Hp. apply isprogram_ot_iff; dands; spcf.
introv Hin. apply in_selectbt in Hin. exrepnd.
eauto with slow.
rw <- Hin0.
eauto with slow.
Qed.
Hint Resolve isprogram_ot_if_eauto : slow.
Lemma newvars5_prop {p} :
forall v1 v2 v3 v4 v5 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5) = newvars5 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms ++ [v1])
# !LIn v3 (free_vars_list terms ++ [v1, v2])
# !LIn v4 (free_vars_list terms ++ [v1, v2, v3])
# !LIn v5 (free_vars_list terms ++ [v1, v2, v3, v4]).
Proof.
introv eq.
unfold newvars5 in eq; cpx.
unfold newvarlst; simpl; allrw @free_vars_list_app; simpl.
dands; apply fresh_var_not_in.
Qed.
Lemma newvars5_prop2 {p} :
forall v1 v2 v3 v4 v5 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5) = newvars5 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !LIn v3 (free_vars_list terms)
# !LIn v4 (free_vars_list terms)
# !LIn v5 (free_vars_list terms)
# !v1 = v2
# !v1 = v3
# !v1 = v4
# !v1 = v5
# !v2 = v3
# !v2 = v4
# !v2 = v5
# !v3 = v4
# !v3 = v5
# !v4 = v5.
Proof.
introv eq.
apply newvars5_prop in eq; repnd.
allrw in_app_iff; allsimpl.
repeat (apply not_over_or in eq; repnd).
repeat (apply not_over_or in eq1; repnd).
repeat (apply not_over_or in eq2; repnd).
repeat (apply not_over_or in eq3; repnd).
sp.
Qed.
Lemma newvars2_prop {p} :
forall v1 v2 (terms : list (@NTerm p)),
(v1, v2) = newvars2 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms ++ [v1]).
Proof.
introv eq.
unfold newvars2 in eq; cpx.
unfold newvarlst; simpl; allrw @free_vars_list_app; simpl.
dands; apply fresh_var_not_in.
Qed.
Lemma newvars2_prop2 {p} :
forall v1 v2 (terms : list (@NTerm p)),
(v1, v2) = newvars2 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !v1 = v2.
Proof.
introv eq.
apply newvars2_prop in eq; repnd.
allrw in_app_iff; allsimpl.
repeat (apply not_over_or in eq; repnd).
sp.
Qed.
Lemma newvars6_prop {p} :
forall v1 v2 v3 v4 v5 v6 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5, v6) = newvars6 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms ++ [v1])
# !LIn v3 (free_vars_list terms ++ [v1, v2])
# !LIn v4 (free_vars_list terms ++ [v1, v2, v3])
# !LIn v5 (free_vars_list terms ++ [v1, v2, v3, v4])
# !LIn v6 (free_vars_list terms ++ [v1, v2, v3, v4, v5]).
Proof.
introv eq.
unfold newvars6 in eq; cpx.
unfold newvarlst; simpl; allrw @free_vars_list_app; simpl.
dands; try (apply fresh_var_not_in).
Qed.
Lemma newvars6_prop2 {p} :
forall v1 v2 v3 v4 v5 v6 (terms : list (@NTerm p)),
(v1, v2, v3, v4, v5, v6) = newvars6 terms
-> !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !LIn v3 (free_vars_list terms)
# !LIn v4 (free_vars_list terms)
# !LIn v5 (free_vars_list terms)
# !LIn v6 (free_vars_list terms)
# !v1 = v2
# !v1 = v3
# !v1 = v4
# !v1 = v5
# !v1 = v6
# !v2 = v3
# !v2 = v4
# !v2 = v5
# !v2 = v6
# !v3 = v4
# !v3 = v5
# !v3 = v6
# !v4 = v5
# !v4 = v6
# !v5 = v6.
Proof.
introv eq.
apply newvars6_prop in eq; repnd.
allrw in_app_iff; allsimpl.
repeat (apply not_over_or in eq; repnd).
repeat (apply not_over_or in eq1; repnd).
repeat (apply not_over_or in eq2; repnd).
repeat (apply not_over_or in eq3; repnd).
repeat (apply not_over_or in eq4; repnd).
tcsp.
Qed.
Lemma newvarlst_prop {p} :
forall (ts : list (@NTerm p)), ! LIn (newvarlst ts) (free_vars_list ts).
Proof.
unfold newvarlst; sp.
allapply fresh_var_not_in; sp.
Qed.
Lemma newvars7_prop {o} :
forall (terms : list (@NTerm o)),
{v1 : NVar
& {v2 : NVar
& {v3 : NVar
& {v4 : NVar
& {v5 : NVar
& {v6 : NVar
& {v7 : NVar
& (v1,v2,v3,v4,v5,v6,v7) = newvars7 terms
# !LIn v1 (free_vars_list terms)
# !LIn v2 (free_vars_list terms)
# !LIn v3 (free_vars_list terms)
# !LIn v4 (free_vars_list terms)
# !LIn v5 (free_vars_list terms)
# !LIn v6 (free_vars_list terms)
# !LIn v7 (free_vars_list terms)
# !v1 = v2
# !v1 = v3
# !v1 = v4
# !v1 = v5
# !v1 = v6
# !v1 = v7
# !v2 = v3
# !v2 = v4
# !v2 = v5
# !v2 = v6
# !v2 = v7
# !v3 = v4
# !v3 = v5
# !v3 = v6
# !v3 = v7
# !v4 = v5
# !v4 = v6
# !v4 = v7
# !v5 = v6
# !v5 = v7
# !v6 = v7}}}}}}}.
Proof.
introv.
remember (newvars7 terms) as nv; sp.
sp.
unfold newvars7 in Heqnv.
remember (newvars6 terms) as nv'; sp.
apply newvars6_prop2 in Heqnv'; repnd.
ginv.
pose proof (newvarlst_prop
(terms ++
[mk_var nv'4, mk_var nv'3,
mk_var nv'2, mk_var nv'1,
mk_var nv'0, mk_var nv'])) as h.
remember (newvarlst
(terms ++
[mk_var nv'4, mk_var nv'3,
mk_var nv'2, mk_var nv'1,
mk_var nv'0, mk_var nv'])) as n.
clear Heqn.
allrw @free_vars_list_app; allsimpl.
allrw in_app_iff; allsimpl.
allrw not_over_or; repnd; GC.
eexists; eexists; eexists; eexists; eexists; eexists; eexists.
dands; eauto.
Qed.
Lemma mkc_inl_inr_eq {p} :
forall a b : @CTerm p, mkc_inl a = mkc_inr b -> False.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H.
Qed.
Lemma mkc_inr_inl_eq {p} :
forall a b : @CTerm p, mkc_inr a = mkc_inl b -> False.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H.
Qed.
Lemma closed_implies {p} :
forall t : @NTerm p,
closed t -> (forall x, !LIn x (free_vars t)).
Proof.
introv cl i; rw cl in i; sp.
Qed.
Lemma closed_iff {p} :
forall t : @NTerm p,
closed t <=> (forall x, !LIn x (free_vars t)).
Proof.
introv; split; intro k.
- apply closed_implies; auto.
- unfold closed.
apply subvars_nil_r.
rw subvars_prop; introv i.
apply k in i; sp.
Qed.
Lemma isprog_lam_iff {p} :
forall v (b : @NTerm p),
isprog_vars [v] b <=> isprog (mk_lam v b).
Proof.
introv; split; intro k.
apply isprog_lam; sp.
allrw @isprog_eq.
rw @isprog_vars_eq.
unfold isprogram in k; repnd.
inversion k as [|?| o lnt j meq ]; allsimpl; subst.
generalize (j (bterm [v] b)); intro u; dest_imp u hyp.
inversion u; subst; sp.
generalize (closed_implies (mk_lam v b) k0); intro i.
rw subvars_prop; introv y.
allsimpl.
destruct (eq_var_dec v x); sp.
allrw app_nil_r.
generalize (i x); intro pp.
allrw in_remove_nvars; allrw in_single_iff.
provefalse.
apply pp; sp.
Qed.
Lemma isprog_vars_lam_iff {p} :
forall v (b : @NTerm p) vs,
isprog_vars vs (mk_lam v b) <=> isprog_vars (vs ++ [v]) b.
Proof.
introv; split; intro k; allrw @isprog_vars_eq; allrw @nt_wf_eq; repnd; dands;
allrw <- @wf_lam_iff; try (complete sp); allsimpl; allrw app_nil_r; allrw subvars_prop;
introv i.
rw in_app_iff; rw in_single_iff.
destruct (eq_var_dec v x); sp.
generalize (k0 x).
rw in_remove_nvars; rw in_single_iff; intro j.
dest_imp j hyp.
rw in_remove_nvars in i; rw in_single_iff in i; repnd.
generalize (k0 x); intro j; dest_imp j hyp.
rw in_app_iff in j; rw in_single_iff in j; sp.
Qed.
Lemma isprog_vars_isect_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_isect a v b).
Proof.
introv; split; intro k.
apply isprog_vars_isect; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_isect_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_eisect_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_eisect a v b).
Proof.
introv; split; intro k.
apply isprog_vars_eisect; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_eisect_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_free_from_atom_iff {p} :
forall vs (a b T : @NTerm p),
(isprog_vars vs a # isprog_vars vs b # isprog_vars vs T)
<=> isprog_vars vs (mk_free_from_atom a b T).
Proof.
introv; split; intro k.
- apply isprog_vars_free_from_atom; sp.
- allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_free_from_atom_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_efree_from_atom_iff {p} :
forall vs (a b T : @NTerm p),
(isprog_vars vs a # isprog_vars vs b # isprog_vars vs T)
<=> isprog_vars vs (mk_efree_from_atom a b T).
Proof.
introv; split; intro k.
- apply isprog_vars_efree_from_atom; sp.
- allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_efree_from_atom_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_free_from_atoms_iff {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_free_from_atoms a b).
Proof.
introv; split; intro k.
- apply isprog_vars_free_from_atoms; sp.
- allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_free_from_atoms_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_equality_iff {p} :
forall vs (a b T : @NTerm p),
(isprog_vars vs a # isprog_vars vs b # isprog_vars vs T)
<=> isprog_vars vs (mk_equality a b T).
Proof.
introv; split; intro k.
apply isprog_vars_equality; sp.
allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_equality_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_requality_iff {p} :
forall vs (a b T : @NTerm p),
(isprog_vars vs a # isprog_vars vs b # isprog_vars vs T)
<=> isprog_vars vs (mk_requality a b T).
Proof.
introv; split; intro k.
apply isprog_vars_requality; sp.
allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_requality_iff.
allrw subvars_app_l; sp.
Qed.
Lemma isprog_vars_tequality_iff {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_tequality a b).
Proof.
introv; split; intro k.
apply isprog_vars_tequality; sp.
allrw @isprog_vars_eq; allsimpl; allrw @nt_wf_eq.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw <- @wf_tequality_iff.
allrw subvars_app_l; sp.
Qed.
Theorem isprog_pertype_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_pertype a).
Proof.
introv; split; intro k.
apply isprog_pertype; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_pertype_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma isprog_vars_base_iff {p} :
forall vs, @isprog_vars p vs mk_base <=> True.
Proof.
intros.
rw @isprog_vars_eq; simpl; sp; split; sp.
constructor; simpl; sp.
Qed.
Lemma isprog_vars_app1 {p} :
forall (t : @NTerm p) vs1 vs2,
isprog_vars vs1 t
-> isprog_vars (vs1 ++ vs2) t.
Proof.
sp; alltrewrite @isprog_vars_eq; sp.
alltrewrite subvars_eq.
apply subset_app_r; sp.
Qed.
Lemma isprog_vars_cons_if2 {p} :
forall v vs (t : @NTerm p),
isprog_vars (v :: vs) t
-> !LIn v (free_vars t)
-> isprog_vars vs t.
Proof.
introv ip ni.
allrw @isprog_vars_eq.
allrw subvars_prop; sp.
discover; allsimpl; sp; subst; sp.
Qed.
Lemma isprog_vars_cons_app1 {p} :
forall vs1 vs2 (t : @NTerm p),
isprog_vars (vs1 ++ vs2) t
-> (forall v, LIn v vs2 -> !LIn v (free_vars t))
-> isprog_vars vs1 t.
Proof.
introv ip ni.
allrw @isprog_vars_eq.
allrw subvars_prop; sp.
discover.
allrw in_app_iff; sp.
discover; sp.
Qed.
Ltac unfold_all_mk :=
allunfold mk_apply
;allunfold mk_eapply
(* ;allunfold mk_apseq*)
;allunfold mk_parallel
;allunfold mk_bottom
;allunfold mk_fix
;allunfold mk_id
;allunfold mk_lam
;allunfold mk_var
;allunfold mk_free_from_atom
;allunfold mk_efree_from_atom
;allunfold mk_free_from_atoms
;allunfold mk_equality
;allunfold mk_requality
;allunfold mk_tequality
;allunfold mk_cequiv
;allunfold mk_inl
;allunfold mk_inr
;allunfold mk_pair
;allunfold mk_sup
;allunfold mk_refl
;allunfold mk_int
;allunfold mk_uni
;allunfold mk_base
;allunfold mk_fun
;allunfold mk_set
;allunfold mk_texc
;allunfold mk_tunion
;allunfold mk_quotient
;allunfold mk_isect
;allunfold mk_disect
;allunfold mk_w
;allunfold mk_m
;allunfold mk_pw
;allunfold mk_pm
;allunfold mk_pertype
;allunfold mk_ipertype
;allunfold mk_spertype
;allunfold mk_tuni
;allunfold mk_partial
;allunfold mk_union
;allunfold mk_eunion
;allunfold mk_union2
;allunfold mk_approx
;allunfold mk_cequiv
;allunfold mk_compute
;allunfold mk_rec
;allunfold mk_image
;allunfold mk_admiss
;allunfold mk_mono
;allunfold nobnd.
Lemma isprogram_inl_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_inl a).
Proof.
intros; split; intro i.
apply isprogram_inl; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprogram_inr_iff {p} :
forall a : @NTerm p, isprogram a <=> isprogram (mk_inr a).
Proof.
intros; split; intro i.
apply isprogram_inr; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)); intros i1.
dest_imp i1 hyp.
unfold isprogram; allrw.
inversion i1; subst; sp.
Qed.
Lemma isprogram_texc_iff {p} :
forall a b : @NTerm p,
(isprogram a # isprogram b) <=> isprogram (mk_texc a b).
Proof.
intros; split; intro i.
apply isprogram_texc; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_union_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_union a b).
Proof.
intros; split; intro i.
apply isprogram_union; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_eunion_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_eunion a b).
Proof.
intros; split; intro i.
apply isprogram_eunion; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprogram_union2_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_union2 a b).
Proof.
intros; split; intro i.
apply isprogram_union2; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_m_iff {p} :
forall (a : @NTerm p) v b,
(isprog a # isprog_vars [v] b)
<=> isprog (mk_m a v b).
Proof.
introv; split; intro k; try (apply isprog_m; sp).
allrw @isprog_eq; allrw @isprog_vars_eq.
inversion k as [c w].
inversion w as [|?| o lnt j e ]; subst.
generalize (j (nobnd a)) (j (bterm [v] b)); intros i1 i2; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
unfold isprogram.
inversion c as [pp]; allrw remove_nvars_nil_l; allrw app_nil_r.
inversion i1; inversion i2; subst.
rw app_eq_nil_iff in pp; sp; subst; sp.
rw subvars_prop; simpl; introv i; allrw in_app_iff; allrw in_remove_nvars.
allrw in_single_iff.
destruct (eq_var_dec v x); sp.
right; right; sp.
Qed.
Lemma isprogram_pair_iff {p} :
forall a b : @NTerm p, (isprogram a # isprogram b) <=> isprogram (mk_pair a b).
Proof.
intros; split; intro i.
apply isprogram_pair; sp.
inversion i as [cl w].
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw app_eq_nil_iff; repnd; allrw.
inversion w as [|?| o lnt k meq ]; allsimpl; subst.
generalize (k (nobnd a)) (k (nobnd b)); intros i1 i2.
dest_imp i1 hyp; dest_imp i2 hyp.
unfold isprogram; allrw.
inversion i1; inversion i2; subst; sp.
Qed.
Definition mkc_admiss {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_admiss a) (isprog_admiss a x).
Theorem isvalue_admiss {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_admiss a).
Proof.
intros; constructor; simpl; auto; apply isprogram_admiss; auto.
Qed.
Lemma iscvalue_mkc_admiss {p} :
forall t : @CTerm p, iscvalue (mkc_admiss t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_admiss; allrw @isprog_eq; auto.
Qed.
Definition mkc_mono {p} (R : @CTerm p) : CTerm :=
let (a,x) := R in
exist isprog (mk_mono a) (isprog_mono a x).
Theorem isvalue_mono {p} :
forall a : @NTerm p, isprogram a -> isvalue (mk_mono a).
Proof.
intros; constructor; simpl; auto; apply isprogram_mono; auto.
Qed.
Lemma iscvalue_mkc_mono {p} :
forall t : @CTerm p, iscvalue (mkc_mono t).
Proof.
intro; destruct t; unfold iscvalue; simpl.
apply isvalue_mono; allrw @isprog_eq; auto.
Qed.
Lemma wf_cequiv_iff {p} :
forall a b : @NTerm p, (wf_term a # wf_term b) <=> wf_term (mk_cequiv a b).
Proof.
sp; split; intros k.
apply wf_cequiv; sp.
allrw @wf_term_eq.
inversion k as [|?| o lnt i meq ]; subst; allsimpl.
generalize (i (nobnd a)); generalize (i (nobnd b)); intros i1 i2.
dest_imp i1 hyp.
dest_imp i2 hyp.
inversion i1; inversion i2; sp.
Qed.
Definition mkc_or {p} (A B : @CTerm p) := mkc_union A B.
Definition mkc_eor {p} (A B : @CTerm p) := mkc_eunion A B.
Definition mkc_not {p} (P : @CTerm p) := mkc_fun P mkc_void.
Definition mkc_btrue {o} : @CTerm o := mkc_inl mkc_axiom.
Definition mkc_bfalse {o} : @CTerm o := mkc_inr mkc_axiom.
Lemma wf_fun {p} :
forall A B : @NTerm p, wf_term (mk_fun A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_ufun {p} :
forall A B : @NTerm p, wf_term (mk_ufun A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_eufun {p} :
forall A B : @NTerm p, wf_term (mk_eufun A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_prod {p} :
forall A B : @NTerm p, wf_term (mk_prod A B) <=> (wf_term A # wf_term B).
Proof.
introv.
split; intro w.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e ]; subst.
generalize (bw (nobnd A)) (bw (bterm [newvar B] B)); intros bw1 bw2; clear bw.
dest_imp bw1 hyp.
dest_imp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
rw <- @nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_not {p} :
forall A : @NTerm p, wf_term (mk_not A) <=> wf_term A.
Proof.
introv.
rw @wf_fun; split; sp.
Qed.
Lemma wf_subtype_rel {p} :
forall a b : @NTerm p,
wf_term a
-> wf_term b
-> wf_term (mk_subtype_rel a b).
Proof.
sp; unfold mk_subtype_rel.
apply wf_member; sp.
apply wf_fun; sp.
Qed.
Lemma wf_fun_iff {p} :
forall (a b : @NTerm p),
wf_term (mk_fun a b) <=> (wf_term a # wf_term b).
Proof.
introv.
unfold mk_fun.
rw <- @wf_function_iff; sp.
Qed.
Lemma wf_subtype_rel_iff {p} :
forall a b : @NTerm p,
wf_term (mk_subtype_rel a b) <=> (wf_term a # wf_term b).
Proof.
sp; split; intro.
- unfold mk_subtype_rel in H.
allrw <- @wf_member_iff; repd.
allrw @wf_fun_iff; sp.
- apply wf_subtype_rel; sp.
Qed.
Lemma isprog_subtype_rel {p} :
forall a b : @NTerm p,
isprog a
-> isprog b
-> isprog (mk_subtype_rel a b).
Proof.
unfold mk_subtype_rel; introv ispa ispb.
apply isprog_member; auto.
apply isprog_fun; auto.
Qed.
Definition mkc_subtype_rel {p} (T1 T2 : @CTerm p) : CTerm :=
let (a,x) := T1 in
let (b,y) := T2 in
exist isprog (mk_subtype_rel a b) (isprog_subtype_rel a b x y).
Ltac destruct_bterms :=
repeat match goal with
[bt : BTerm |- _] =>
let btlv := fresh bt "lv" in
let btnt := fresh bt "nt" in
destruct bt as [btlv btnt]
end.
Lemma mkc_admiss_eq {p} :
forall T1 T2 : @CTerm p, mkc_admiss T1 = mkc_admiss T2 -> T1 = T2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma mkc_mono_eq {p} :
forall T1 T2 : @CTerm p, mkc_mono T1 = mkc_mono T2 -> T1 = T2.
Proof.
intros.
destruct_cterms; allsimpl.
inversion H; subst.
eauto with pi.
Qed.
Lemma wf_less {p} :
forall a b c d : @NTerm p,
wf_term a
-> wf_term b
-> wf_term c
-> wf_term d
-> wf_term (mk_less a b c d).
Proof.
introv; repeat (rw <- @nt_wf_eq).
intros nta ntb ntc ntd; inversion nta; inversion ntb; inversion ntc; inversion ntd; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_less_iff {p} :
forall a b c d : @NTerm p,
(wf_term a # wf_term b # wf_term c # wf_term d) <=> wf_term (mk_less a b c d).
Proof.
introv; split; intro i.
apply wf_less; sp.
allrw @wf_term_eq.
inversion i as [|?| o lnt k e]; subst; allsimpl.
generalize (k (nobnd a)) (k (nobnd b)) (k (nobnd c)) (k (nobnd d)); intros k1 k2 k3 k4.
repeat (dest_imp k1 hyp).
repeat (dest_imp k2 hyp).
repeat (dest_imp k3 hyp).
repeat (dest_imp k4 hyp).
inversion k1; subst.
inversion k2; subst.
inversion k3; subst.
inversion k4; subst; sp.
Qed.
Lemma isprog_vars_less {p} :
forall (a b c d : @NTerm p) vs,
isprog_vars vs (mk_less a b c d)
<=> (isprog_vars vs a
# isprog_vars vs b
# isprog_vars vs c
# isprog_vars vs d).
Proof.
introv.
repeat (rw @isprog_vars_eq; simpl).
repeat (rw remove_nvars_nil_l).
repeat (rw app_nil_r).
repeat (rw subvars_app_l).
repeat (rw <- @wf_term_eq).
allrw <- @wf_less_iff; split; sp.
Qed.
Lemma isprog_vars_function {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_function a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_function_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_function a v b).
Proof.
introv; split; intro k.
apply isprog_vars_function; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_function_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_cons_newvar {p} :
forall (b : @NTerm p) vs,
isprog_vars (newvar b :: vs) b <=> isprog_vars vs b.
Proof.
introv; split; intro k.
allrw @isprog_vars_eq.
allrw subvars_prop; repnd; dands; auto.
introv i.
applydup k0 in i; simpl in i0; repdors; subst; auto.
apply newvar_prop in i; sp.
apply isprog_vars_cons; sp.
Qed.
Lemma isprog_vars_fun {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_fun a b).
Proof.
introv.
rw <- @isprog_vars_function_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_ufun {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_ufun a b).
Proof.
introv.
rw <- @isprog_vars_isect_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_eufun {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_eufun a b).
Proof.
introv.
rw <- @isprog_vars_eisect_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_product {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_product a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Theorem wf_product_iff {p} :
forall (a : @NTerm p) v b, (wf_term a # wf_term b) <=> wf_term (mk_product a v b).
Proof.
sp; split; intro i; try (apply wf_product; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (nobnd a)) (k (bterm [v] b)); intros i1 i2.
dest_imp i1 hyp; try (complete sp).
dest_imp i2 hyp; try (complete sp).
inversion i1; inversion i2; subst; sp.
Qed.
Lemma isprog_vars_product_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_product a v b).
Proof.
introv; split; intro k.
apply isprog_vars_product; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_product_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_prod {p} :
forall vs (a b : @NTerm p),
(isprog_vars vs a # isprog_vars vs b)
<=> isprog_vars vs (mk_prod a b).
Proof.
introv.
rw <- @isprog_vars_product_iff.
rw @isprog_vars_cons_newvar; sp.
Qed.
Lemma isprog_vars_set {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_set a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_set_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_set a v b).
Proof.
introv; split; intro k.
apply isprog_vars_set; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_set_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_tunion {p} :
forall vs (a : @NTerm p) v b,
isprog_vars vs a
-> isprog_vars (v :: vs) b
-> isprog_vars vs (mk_tunion a v b).
Proof.
introv ipa ipb.
allrw @isprog_vars_eq; allrw subvars_prop; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; sp.
allrw in_app_iff; allrw in_remove_nvars; allrw in_single_iff; sp.
discover; sp.
constructor; simpl; sp; subst; constructor; sp.
Qed.
Lemma isprog_vars_tunion_iff {p} :
forall vs (a : @NTerm p) v b,
(isprog_vars vs a # isprog_vars (v :: vs) b)
<=> isprog_vars vs (mk_tunion a v b).
Proof.
introv; split; intro k.
apply isprog_vars_tunion; sp.
allrw @isprog_vars_eq; allrw @nt_wf_eq.
allrw <- @wf_tunion_iff; repnd.
allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r.
allrw subvars_app_l.
allrw subvars_remove_nvars; sp.
provesv; allrw in_app_iff; allsimpl; sp.
Qed.
Lemma isprog_vars_void_iff {p} :
forall vs, @isprog_vars p vs mk_void <=> True.
Proof.
introv; split; intro k; auto.
Qed.
Lemma isprog_vars_true_iff {p} :
forall vs, @isprog_vars p vs mk_true <=> True.
Proof.
introv; split; intro k; auto.
rw @isprog_vars_eq; sp.
constructor; sp.
allsimpl; sp; subst; repeat constructor; simpl; sp.
Qed.
Lemma isprog_vars_false_iff {p} :
forall vs, @isprog_vars p vs mk_false <=> True.
Proof.
introv; split; intro k; auto.
Qed.
Lemma isprog_vars_le {p} :
forall (a b : @NTerm p) vs,
isprog_vars vs (mk_le a b) <=> (isprog_vars vs a # isprog_vars vs b).
Proof.
introv; unfold mk_le.
rw <- @isprog_vars_fun.
rw @isprog_vars_void_iff.
rw @isprog_vars_less.
rw @isprog_vars_false_iff.
rw @isprog_vars_true_iff.
split; sp.
Qed.
Lemma isprog_vars_zero {p} :
forall vs,
@isprog_vars p vs mk_zero.
Proof.
introv.
apply isprog_vars_eq; simpl; dands; tcsp.
constructor; simpl; tcsp.
Qed.
Hint Resolve isprog_vars_zero : slow.
Lemma isprog_tnat {p} : @isprog p mk_tnat.
Proof.
rw <- @isprog_set_iff.
dands; auto.
rw @isprog_vars_le; dands; eauto 3 with slow.
apply isprog_vars_var.
Qed.
Definition mkc_tnat {p} : @CTerm p := exist isprog mk_tnat isprog_tnat.
Lemma free_vars_fun {p} :
forall a b : @NTerm p, free_vars (mk_fun a b) = free_vars a ++ free_vars b.
Proof.
introv; simpl.
rw remove_nvars_nil_l.
rw app_nil_r.
assert (disjoint (free_vars b) [newvar b]) as disj.
apply disjoint_sym.
rw disjoint_singleton_l.
apply newvar_prop.
rw remove_nvars_unchanged in disj.
rw disj; auto.
Qed.
Lemma free_vars_ufun {p} :
forall a b : @NTerm p, free_vars (mk_ufun a b) = free_vars a ++ free_vars b.
Proof.
introv; simpl.
rw remove_nvars_nil_l.
rw app_nil_r.
assert (disjoint (free_vars b) [newvar b]) as disj.
apply disjoint_sym.
rw disjoint_singleton_l.
apply newvar_prop.
rw remove_nvars_unchanged in disj.
rw disj; auto.
Qed.
Lemma free_vars_eufun {p} :
forall a b : @NTerm p, free_vars (mk_eufun a b) = free_vars a ++ free_vars b.
Proof.
introv; simpl.
rw remove_nvars_nil_l.
rw app_nil_r.
assert (disjoint (free_vars b) [newvar b]) as disj.
apply disjoint_sym.
rw disjoint_singleton_l.
apply newvar_prop.
rw remove_nvars_unchanged in disj.
rw disj; auto.
Qed.
Lemma isprogram_mk_zero {p} :
@isprogram p mk_zero.
Proof.
repeat constructor; simpl; sp.
Qed.
Hint Immediate isprogram_mk_zero.
Lemma isprogram_mk_one {p} :
@isprogram p mk_one.
Proof.
repeat constructor; simpl; sp.
Qed.
Hint Immediate isprogram_mk_one.
Lemma isprog_mk_zero {p} :
@isprog p mk_zero.
Proof.
rw @isprog_eq.
apply isprogram_mk_zero.
Qed.
Hint Immediate isprog_mk_zero.
Definition mkc_zero {p} : @CTerm p := exist isprog mk_zero isprog_mk_zero.
Definition mk_eta_pair {p} (t : @NTerm p) := mk_pair (mk_pi1 t) (mk_pi2 t).
Definition mk_eta_inl {p} (t : @NTerm p) := mk_inl (mk_outl t).
Definition mk_eta_inr {p} (t : @NTerm p) := mk_inr (mk_outr t).
Lemma free_vars_mk_pertype {p} :
forall A : @NTerm p,
free_vars (mk_pertype A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma free_vars_mk_ipertype {p} :
forall A : @NTerm p,
free_vars (mk_ipertype A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma free_vars_mk_spertype {p} :
forall A : @NTerm p,
free_vars (mk_spertype A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma free_vars_mk_tuni {p} :
forall A : @NTerm p,
free_vars (mk_tuni A) = free_vars A.
Proof.
introv.
simpl.
rw remove_nvars_nil_l.
rw app_nil_r; auto.
Qed.
Lemma wf_isaxiom {p} :
forall a b c : @NTerm p,
wf_term (mk_isaxiom a b c) <=> (wf_term a # wf_term b # wf_term c).
Proof.
sp; split; intro k.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
- repnd.
unfold wf_term; simpl.
rw k0; rw k1; rw k; auto.
Qed.
Lemma nt_wf_isaxiom {p} :
forall a b c : @NTerm p,
nt_wf (mk_isaxiom a b c) <=> (nt_wf a # nt_wf b # nt_wf c).
Proof.
introv.
allrw @nt_wf_eq.
apply wf_isaxiom.
Qed.
Lemma isprog_vars_isaxiom {p} :
forall vs (a b c : @NTerm p),
isprog_vars vs (mk_isaxiom a b c)
<=>
(isprog_vars vs a
# isprog_vars vs b
# isprog_vars vs c).
Proof.
introv; split; intro k; repnd; allrw @isprog_vars_eq; allsimpl;
allrw remove_nvars_nil_l; allrw app_nil_r;
allrw subvars_app_l; allrw @nt_wf_isaxiom; sp.
Qed.
Lemma isprog_vars_halts {p} :
forall vs (a : @NTerm p), isprog_vars vs (mk_halts a) <=> isprog_vars vs a.
Proof.
introv.
allrw @isprog_vars_eq; simpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw @nt_wf_eq.
allrw <- @wf_halts_iff; sp.
Qed.
Lemma isprog_ipertype_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_ipertype a).
Proof.
introv; split; intro k.
apply isprog_ipertype; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_ipertype_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma isprog_spertype_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_spertype a).
Proof.
introv; split; intro k.
apply isprog_spertype; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_spertype_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma isprog_tuni_iff {p} :
forall a : @NTerm p, isprog a <=> isprog (mk_tuni a).
Proof.
introv; split; intro k.
apply isprog_tuni; sp.
allrw @isprog_eq; allunfold @isprogram; allrw @nt_wf_eq.
allrw <- @wf_tuni_iff; sp.
allunfold @closed; allsimpl.
allrw remove_nvars_nil_l.
allrw app_nil_r; sp.
Qed.
Lemma wf_pair {p} :
forall a b : @NTerm p, wf_term (mk_pair a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)) (bw (nobnd b)); simpl; intros bw1 bw2.
autodimp bw1 hyp.
autodimp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_spread {p} :
forall (a : @NTerm p) v1 v2 b,
wf_term (mk_spread a v1 v2 b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; sp.
allsimpl; sp; subst; constructor; allrw @nt_wf_eq; sp.
Qed.
Lemma wf_ispair {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_ispair a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_ispair_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_ispair a b T).
Proof.
sp; split; introv k.
- apply wf_ispair; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isinl {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_isinl a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_isinl_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinl a b T).
Proof.
introv; split; intro k.
- apply wf_isinl; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isinr {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_isinr a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_isinr_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinr a b T).
Proof.
introv; split; intro k.
- apply wf_isinl; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_islambda {p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_islambda a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_islambda_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinr a b T).
Proof.
introv; split; intro k.
- apply wf_islambda; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isaxiom_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isinr a b T).
Proof.
introv; split; intro k.
- apply wf_isaxiom; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma wf_isint{p} :
forall a b T : @NTerm p,
wf_term a -> wf_term b -> wf_term T -> wf_term (mk_isint a b T).
Proof.
intros a b T; repeat (rw <- @nt_wf_eq).
intros nta ntb ntt; inversion nta; inversion ntb; subst;
constructor; allsimpl; sp; subst; auto; constructor; auto.
Qed.
Lemma wf_isint_iff {p} :
forall a b T : @NTerm p,
(wf_term a # wf_term b # wf_term T) <=> wf_term (mk_isint a b T).
Proof.
introv; split; intro k.
- apply wf_isint; sp.
- dands; eapply oball_map_wftb_eq_otrue_implies_wf_term; try (exact k); simpl; sp.
Qed.
Lemma isprog_pi1 {p} :
forall t : @NTerm p, isprog t -> isprog (mk_pi1 t).
Proof.
introv ip.
apply isprog_spread; sp.
apply isprog_vars_var_iff; simpl; sp.
Qed.
Lemma isprog_pi2 {p} :
forall t : @NTerm p, isprog t -> isprog (mk_pi2 t).
Proof.
introv ip.
apply isprog_spread; sp.
apply isprog_vars_var_iff; simpl; sp.
Qed.
Lemma isprog_eta_pair {p} :
forall t : @NTerm p, isprog t -> isprog (mk_eta_pair t).
Proof.
introv ip.
unfold mk_eta_pair.
apply isprog_pair.
apply isprog_pi1; auto.
apply isprog_pi2; auto.
Qed.
Definition mkc_eta_pair {p} (t : @CTerm p) :=
let (a,p) := t in exist isprog (mk_eta_pair a) (isprog_eta_pair a p).
Lemma isprog_outl {p} :
forall t : @NTerm p, isprog t -> isprog (mk_outl t).
Proof.
introv ip.
apply isprog_decide; tcsp.
- apply isprog_vars_mk_var; tcsp.
- unfold isprog_vars; simpl; dands; tcsp.
Qed.
Lemma isprog_outr {p} :
forall t : @NTerm p, isprog t -> isprog (mk_outr t).
Proof.
introv ip.
apply isprog_decide; sp.
- unfold isprog_vars; simpl; dands; tcsp.
- apply isprog_vars_mk_var; tcsp.
Qed.
Lemma isprog_eta_inl {p} :
forall t : @NTerm p, isprog t -> isprog (mk_eta_inl t).
Proof.
introv ip.
unfold mk_eta_inl.
apply isprog_inl.
apply isprog_outl; auto.
Qed.
Lemma isprog_eta_inr {p} :
forall t : @NTerm p, isprog t -> isprog (mk_eta_inr t).
Proof.
introv ip.
unfold mk_eta_inr.
apply isprog_inr.
apply isprog_outl; auto.
Qed.
Definition mkc_eta_inl {p} (t : @CTerm p) :=
let (a,p) := t in exist isprog (mk_eta_inl a) (isprog_eta_inl a p).
Definition mkc_eta_inr {p} (t : @CTerm p) :=
let (a,p) := t in exist isprog (mk_eta_inr a) (isprog_eta_inr a p).
Lemma fold_pi1 {p} :
forall t : @NTerm p, mk_spread t nvarx nvary (mk_var nvarx) = mk_pi1 t.
Proof. sp. Qed.
Lemma fold_pi2 {p} :
forall t : @NTerm p, mk_spread t nvarx nvary (mk_var nvary) = mk_pi2 t.
Proof. sp. Qed.
Lemma fold_eta_pair {p} :
forall t : @NTerm p, mk_pair (mk_pi1 t) (mk_pi2 t) = mk_eta_pair t.
Proof. sp. Qed.
Lemma wf_pi1 {p} :
forall t : @NTerm p, wf_term (mk_pi1 t) <=> wf_term t.
Proof.
introv.
rw @wf_spread; split; sp.
Qed.
Lemma wf_pi2 {p} :
forall t : @NTerm p, wf_term (mk_pi2 t) <=> wf_term t.
Proof.
introv.
rw @wf_spread; split; sp.
Qed.
Lemma wf_eta_pair {p} :
forall t : @NTerm p, wf_term (mk_eta_pair t) <=> wf_term t.
Proof.
introv.
unfold mk_eta_pair.
rw @wf_pair.
rw @wf_pi1.
rw @wf_pi2.
split; sp.
Qed.
Lemma isprogram_spread_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(isprogram a
# subvars (free_vars b) [v1,v2]
# nt_wf b)
<=> isprogram (mk_spread a v1 v2 b).
Proof.
introv; split; intro isp; repnd.
apply isprogram_spread; auto.
inversion isp as [cl wf].
inversion wf as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
unfold closed in cl; simpl in cl; rw remove_nvars_nil_l in cl; rw app_nil_r in cl.
apply app_eq_nil in cl; repnd.
allfold (closed a).
dands; auto.
constructor; sp.
rw subvars_prop; introv i.
rw nil_remove_nvars_iff in cl.
apply cl in i; sp.
Qed.
Lemma isprogram_spread_iff2 {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram (mk_spread a v1 v2 b)
<=> isprogram a # isprogram_bt (bterm [v1, v2] b).
Proof.
introv.
rw <- @isprogram_spread_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma isprogram_dsup_iff {p} :
forall (a : @NTerm p) v1 v2 b,
(isprogram a
# subvars (free_vars b) [v1,v2]
# nt_wf b)
<=> isprogram (mk_dsup a v1 v2 b).
Proof.
introv; split; intro isp; repnd.
apply isprogram_dsup; auto.
inversion isp as [cl wf].
inversion wf as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
unfold closed in cl; simpl in cl; rw remove_nvars_nil_l in cl; rw app_nil_r in cl.
apply app_eq_nil in cl; repnd.
allfold (closed a).
dands; auto.
constructor; sp.
rw subvars_prop; introv i.
rw nil_remove_nvars_iff in cl.
apply cl in i; sp.
Qed.
Lemma isprogram_dsup_iff2 {p} :
forall (a : @NTerm p) v1 v2 b,
isprogram (mk_dsup a v1 v2 b)
<=> isprogram a # isprogram_bt (bterm [v1, v2] b).
Proof.
introv.
rw <- @isprogram_dsup_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma isprogram_decide_iff {p} :
forall (a : @NTerm p) v1 b1 v2 b2,
(isprogram a
# subvars (free_vars b1) [v1]
# subvars (free_vars b2) [v2]
# nt_wf b1
# nt_wf b2)
<=> isprogram (mk_decide a v1 b1 v2 b2).
Proof.
introv; split; intro isp; repnd.
apply isprogram_decide; auto.
inversion isp as [cl wf].
inversion wf as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1] b1)) (bwf (bterm [v2] b2)); clear bwf; intros bwf1 bwf2 bwf3.
autodimp bwf1 hyp; autodimp bwf2 hyp; autodimp bwf3 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
inversion bwf3; subst.
unfold closed in cl; simpl in cl; rw remove_nvars_nil_l in cl; rw app_nil_r in cl.
apply app_eq_nil in cl; repnd.
allfold (closed a).
apply app_eq_nil_iff in cl; repnd.
rw nil_remove_nvars_iff in cl1.
rw nil_remove_nvars_iff in cl.
dands; auto.
constructor; sp.
rw subvars_prop; sp.
rw subvars_prop; sp.
Qed.
Lemma isprogram_decide_iff2 {p} :
forall (a : @NTerm p) v1 b1 v2 b2,
isprogram (mk_decide a v1 b1 v2 b2)
<=> isprogram a # isprogram_bt (bterm [v1] b1) # isprogram_bt (bterm [v2] b2).
Proof.
introv.
rw <- @isprogram_decide_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
repeat (rw <- null_iff_nil).
repeat (rw null_remove_nvars).
repeat (rw subvars_prop).
split; intro k; repnd; dands; auto.
inversion k1; sp.
inversion k; sp.
Qed.
Lemma isprogram_outl {p} :
forall t : @NTerm p, isprogram (mk_outl t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_decide_iff; simpl; split; intro i; repnd; auto.
dands; auto.
pose proof (@isprogram_bot p) as X.
destruct X. auto.
Qed.
Lemma isprogram_outr {p} :
forall t : @NTerm p, isprogram (mk_outr t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_decide_iff; simpl; split; intro i; repnd; auto.
dands; auto.
pose proof (@isprogram_bot p) as X.
destruct X. auto.
Qed.
Lemma isprogram_pi1 {p} :
forall t : @NTerm p, isprogram (mk_pi1 t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_spread_iff; simpl; split; intro i; repnd; auto.
dands; auto.
rw subvars_cons_l; sp.
Qed.
Lemma isprogram_pi2 {p} :
forall t : @NTerm p, isprogram (mk_pi2 t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_spread_iff; simpl; split; intro i; repnd; auto.
dands; auto.
rw subvars_cons_l; sp.
Qed.
Lemma isprogram_eta_pair {p} :
forall t : @NTerm p, isprogram (mk_eta_pair t) <=> isprogram t.
Proof.
introv.
rw <- @isprogram_pair_iff.
rw @isprogram_pi1.
rw @isprogram_pi2.
split; sp.
Qed.
Lemma iscvalue_mkc_tequality {p} :
forall t1 t2 : @CTerm p, iscvalue (mkc_tequality t1 t2).
Proof.
intro; destruct t1; destruct t2; unfold iscvalue; simpl.
apply isvalue_tequality; allrw @isprog_eq; auto.
apply isprogram_tequality; sp.
Qed.
Lemma isprog_pw_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
isprog (mk_pw P ap A bp ba B cp ca cb C q)
<=> (isprog P
# isprog_vars [ap] A
# isprog_vars [bp, ba] B
# isprog_vars [cp, ca, cb] C
# isprog q).
Proof.
introv; split; intro isp.
rw @isprog_eq in isp.
inversion isp as [ cl wf ].
inversion wf as [|?| o lnt j e ]; subst.
generalize (j (nobnd P))
(j (bterm [ap] A))
(j (bterm [bp,ba] B))
(j (bterm [cp,ca,cb] C))
(j (nobnd q)); clear j;
intros i1 i2 i3 i4 i5; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
repeat (dest_imp i3 hyp).
repeat (dest_imp i4 hyp).
repeat (dest_imp i5 hyp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst.
unfold closed in cl; simpl in cl; allrw remove_nvars_nil_l; allrw app_nil_r.
rw <- null_iff_nil in cl.
allrw null_app; repnd.
allrw null_remove_nvars_subvars.
allrw null_iff_nil.
dands.
rw @isprog_eq; constructor; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_eq; constructor; sp.
apply isprog_pw; sp.
Qed.
Lemma isprog_pm_iff {p} :
forall (P : @NTerm p) ap A bp ba B cp ca cb C q,
isprog (mk_pm P ap A bp ba B cp ca cb C q)
<=> (isprog P
# isprog_vars [ap] A
# isprog_vars [bp, ba] B
# isprog_vars [cp, ca, cb] C
# isprog q).
Proof.
introv; split; intro isp.
rw @isprog_eq in isp.
inversion isp as [ cl wf ].
inversion wf as [|?| o lnt j e ]; subst.
generalize (j (nobnd P))
(j (bterm [ap] A))
(j (bterm [bp,ba] B))
(j (bterm [cp,ca,cb] C))
(j (nobnd q)); clear j;
intros i1 i2 i3 i4 i5; allsimpl.
repeat (dest_imp i1 hyp).
repeat (dest_imp i2 hyp).
repeat (dest_imp i3 hyp).
repeat (dest_imp i4 hyp).
repeat (dest_imp i5 hyp).
inversion i1; inversion i2; inversion i3; inversion i4; inversion i5; subst.
unfold closed in cl; simpl in cl; allrw remove_nvars_nil_l; allrw app_nil_r.
rw <- null_iff_nil in cl.
allrw null_app; repnd.
allrw null_remove_nvars_subvars.
allrw null_iff_nil.
dands.
rw @isprog_eq; constructor; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_vars_eq; sp.
rw @isprog_eq; constructor; sp.
apply isprog_pm; sp.
Qed.
Lemma isprogram_exception_implies {p} :
forall (bterms : list (@BTerm p)),
isprogram (oterm Exc bterms)
-> {a : NTerm
$ {t : NTerm
$ bterms = [bterm [] a, bterm [] t]
# isprogram a
# isprogram t}}.
Proof.
introv isp.
inversion isp as [c w].
inversion w as [|?|o lnt bw m]; subst; allsimpl.
repeat (destruct bterms; ginv).
allsimpl; ginv.
destruct b as [l1 t1]; destruct b0 as [l2 t2].
destruct l1; destruct l2; ginv.
allunfold @num_bvars; allsimpl; GC.
unfold closed in c; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw app_eq_nil_iff.
pose proof (bw (bterm [] t1)) as w1.
pose proof (bw (bterm [] t2)) as w2.
repeat (autodimp w1 hyp); repeat (autodimp w2 hyp).
inversion w1; inversion w2; subst.
exists t1 t2; dands; auto; constructor; sp.
Qed.
Lemma iscan_implies {p} :
forall t : @NTerm p,
iscan t
-> {c : CanonicalOp
& {bterms : list BTerm
& t = oterm (Can c) bterms}}
[+] {f : ntseq & t = sterm f}.
Proof.
introv isc.
destruct t as [v|f|op bs]; try (complete (inversion isc)).
- right.
eexists; eauto.
- destruct op; try (complete (inversion isc)).
left; exists c bs; sp.
Qed.
Lemma isexc_implies {p} :
forall t : @NTerm p,
isexc t
-> isprogram t
-> {a : NTerm & {e : NTerm & t = mk_exception a e}}.
Proof.
introv isc isp.
destruct t; try (complete (inversion isc)).
destruct o; try (complete (inversion isc)).
apply isprogram_exception_implies in isp; sp; subst.
eexists; eexists; reflexivity.
Qed.
Lemma isexc_implies2 {p} :
forall t : @NTerm p,
isexc t
-> {l : list BTerm & t = oterm Exc l}.
Proof.
introv isc.
destruct t; try (complete (inversion isc)).
destruct o; try (complete (inversion isc)).
eexists; eexists; sp.
Qed.
Lemma isprogram_trycatch_implies {p} :
forall (bterms : list (@BTerm p)),
isprogram (oterm (NCan NTryCatch) bterms)
-> {t : NTerm
$ {a : NTerm
$ {v : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [] a, bterm [v] b]
# isprogram t
# isprogram a
# isprogram_bt (bterm [v] b)}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b as [l1 t1]; allsimpl; cpx.
destruct b0 as [l2 t2]; allsimpl; cpx.
destruct b1 as [l3 t3]; allsimpl; cpx.
destruct l1; allsimpl; cpx.
destruct l2; allsimpl; cpx.
repeat (destruct l3; allsimpl; cpx).
generalize (isp (bterm [] t1)) (isp (bterm [] t2)) (isp (bterm [n] t3)); intros isp1 isp2 isp3.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists t1 t2 n t3; sp.
Qed.
Lemma isprogram_fresh_implies {p} :
forall (bterms : list (@BTerm p)),
isprogram (oterm (NCan NFresh) bterms)
-> {v : NVar
$ {b : NTerm
$ bterms = [bterm [v] b]
# isprogram_bt (bterm [v] b)}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [n0] n)); intros isp1.
repeat (autodimp isp1 hyp).
exists n0 n; sp.
Qed.
Lemma isprogram_cbv_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NCbv) bterms)
-> {t : NTerm
$ {v : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [v] b]
# isprogram t
# isprogram_bt (bterm [v] b)}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n0; sp.
Qed.
Lemma isprogram_apply_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NApply) bterms)
-> {f : NTerm
$ {a : NTerm
$ bterms = [bterm [] f, bterm [] a]
# isprogram f
# isprogram a}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_eapply_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NEApply) bterms)
-> {f : NTerm
$ {a : NTerm
$ bterms = [bterm [] f, bterm [] a]
# isprogram f
# isprogram a}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
(*
Lemma isprogram_apseq_implies {p} :
forall f (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NApseq f)) bterms)
-> {a : NTerm
$ bterms = [bterm [] a]
# isprogram a}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
*)
Lemma isprogram_parallel_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NParallel) bterms)
-> {a : NTerm
$ {b : NTerm
$ bterms = [bterm [] a, bterm [] b]
# isprogram a
# isprogram b}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_fix_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NFix) bterms)
-> {f : NTerm
$ bterms = [bterm [] f]
# isprogram f}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_sleep_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NSleep) bterms)
-> {t : NTerm
$ bterms = [bterm [] t]
# isprogram t}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_tuni_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NTUni) bterms)
-> {t : NTerm
$ bterms = [bterm [] t]
# isprogram t}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_minus_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NMinus) bterms)
-> {t : NTerm
$ bterms = [bterm [] t]
# isprogram t}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize (isp (bterm [] n)); intros isp1.
repeat (autodimp isp1 hyp).
apply isprogram_bt_nobnd in isp1.
exists n; sp.
Qed.
Lemma isprogram_spread_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NSpread) bterms)
-> {t : NTerm
$ {v1 : NVar
$ {v2 : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [v1,v2] b]
# isprogram t
# isprogram_bt (bterm [v1,v2] b)}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1,n2] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n2 n0; sp.
Qed.
Lemma isprogram_dsup_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NDsup) bterms)
-> {t : NTerm
$ {v1 : NVar
$ {v2 : NVar
$ {b : NTerm
$ bterms = [bterm [] t, bterm [v1,v2] b]
# isprogram t
# isprogram_bt (bterm [v1,v2] b)}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1,n2] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n2 n0; sp.
Qed.
Lemma isprogram_decide_implies {p} :
forall bterms : list (@BTerm p),
isprogram (oterm (NCan NDecide) bterms)
-> {t : NTerm
$ {v1 : NVar
$ {b1 : NTerm
$ {v2 : NVar
$ {b2 : NTerm
$ bterms = [bterm [] t, bterm [v1] b1, bterm [v2] b2]
# isprogram t
# isprogram_bt (bterm [v1] b1)
# isprogram_bt (bterm [v2] b2)}}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
destruct b1; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [n1] n0)) (isp (bterm [n3] n2));
intros isp1 isp2 isp3.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
apply isprogram_bt_nobnd in isp1.
exists n n1 n0 n3 n2; sp.
Qed.
Lemma isprogram_arithop_implies {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NArithOp o)) bterms)
-> {a : NTerm
$ {b : NTerm
$ bterms = [bterm [] a, bterm [] b]
# isprogram a
# isprogram b}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
repeat (destruct l; allsimpl; cpx).
generalize (isp (bterm [] n)) (isp (bterm [] n0)); intros isp1 isp2.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
apply isprogram_bt_nobnd in isp1.
apply isprogram_bt_nobnd in isp2.
exists n n0; sp.
Qed.
Lemma isprogram_arithop_iff {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NArithOp o)) bterms)
<=> {a : NTerm
$ {b : NTerm
$ bterms = [bterm [] a, bterm [] b]
# isprogram a
# isprogram b}}.
Proof.
introv; split; intro k.
apply isprogram_arithop_implies in k; auto.
exrepnd; subst.
apply isprogram_ot_iff; simpl.
unfold num_bvars; simpl; dands; sp; subst;
apply implies_isprogram_bt0; auto.
Qed.
Lemma isprogram_compop_implies {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCompOp o)) bterms)
-> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ {d : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c, bterm [] d]
# isprogram a
# isprogram b
# isprogram c
# isprogram d}}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
destruct b1; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct l0; allsimpl; cpx.
destruct b2; allsimpl; cpx.
destruct l; allsimpl; cpx.
generalize
(isp (bterm [] n))
(isp (bterm [] n0))
(isp (bterm [] n1))
(isp (bterm [] n2));
intros isp1 isp2 isp3 isp4.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
repeat (autodimp isp4 hyp).
allapply @isprogram_bt_nobnd.
exists n n0 n1 n2; sp.
Qed.
Lemma isprogram_compop_iff {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCompOp o)) bterms)
<=> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ {d : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c, bterm [] d]
# isprogram a
# isprogram b
# isprogram c
# isprogram d}}}}.
Proof.
introv; split; intro k.
apply isprogram_compop_implies in k; auto.
exrepnd; subst.
apply isprogram_ot_iff; unfold num_bvars; simpl; sp; subst;
apply implies_isprogram_bt0; auto.
Qed.
Lemma isprogram_cantest_implies {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCanTest o)) bterms)
-> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c]
# isprogram a
# isprogram b
# isprogram c}}}.
Proof.
introv isp.
apply isprogram_ot_iff in isp; simpl in isp; repnd.
repeat (destruct bterms; allsimpl; cpx).
allunfold @num_bvars.
destruct b; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct b0; allsimpl; cpx.
destruct b1; allsimpl; cpx.
destruct l; allsimpl; cpx.
destruct l0; allsimpl; cpx.
generalize
(isp (bterm [] n))
(isp (bterm [] n0))
(isp (bterm [] n1));
intros isp1 isp2 isp3.
repeat (autodimp isp1 hyp).
repeat (autodimp isp2 hyp).
repeat (autodimp isp3 hyp).
allapply @isprogram_bt_nobnd.
exists n n0 n1; sp.
Qed.
Lemma isprogram_cantest_iff {p} :
forall o (bterms : list (@BTerm p)),
isprogram (oterm (NCan (NCanTest o)) bterms)
<=> {a : NTerm
$ {b : NTerm
$ {c : NTerm
$ bterms = [bterm [] a, bterm [] b, bterm [] c]
# isprogram a
# isprogram b
# isprogram c}}}.
Proof.
introv; split; intro k.
apply isprogram_cantest_implies in k; auto.
exrepnd; subst.
apply isprogram_ot_iff; unfold num_bvars; simpl; sp; subst;
apply implies_isprogram_bt0; auto.
Qed.
Lemma isprog_vars_btrue {o} :
forall vs, @isprog_vars o vs mk_btrue.
Proof.
introv.
rw @isprog_vars_eq; simpl; dands; auto.
constructor; simpl; tcsp.
introv i; repndors; subst; tcsp.
constructor; eauto with slow.
Qed.
Lemma isprog_vars_bfalse {o} :
forall vs, @isprog_vars o vs mk_bfalse.
Proof.
introv.
rw @isprog_vars_eq; simpl; dands; auto.
constructor; simpl; tcsp.
introv i; repndors; subst; tcsp.
constructor; eauto with slow.
Qed.
Lemma isprog_vars_le_implies {o} :
forall (a b : @NTerm o) vs,
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_le a b).
Proof.
introv u v.
apply isprog_vars_le; sp.
Qed.
Lemma isprog_vars_less_than {o} :
forall (a b : @NTerm o) vs,
isprog_vars vs (mk_less_than a b) <=> (isprog_vars vs a # isprog_vars vs b).
Proof.
introv; unfold mk_less_than.
rw @isprog_vars_less; split; sp.
apply isprog_vars_true_iff; sp.
Qed.
Lemma isprog_implies_isprog_vars_nil {o} :
forall t, @isprog o t -> isprog_vars [] t.
Proof.
introv isp.
apply isprog_eq in isp.
apply isprog_vars_eq.
rw subvars_nil_r; auto.
Qed.
Lemma isprog_vars_nil_implies_isprog {o} :
forall t, isprog_vars [] t -> @isprog o t.
Proof.
introv isp.
apply isprog_eq.
apply isprog_vars_eq in isp; repnd.
apply subvars_nil_r in isp0.
unfold isprogram; auto.
Qed.
Lemma isprog_vars_nil_iff_isprog {o} :
forall t, @isprog o t <=> isprog_vars [] t.
Proof.
introv; split; intro k.
apply isprog_implies_isprog_vars_nil; auto.
apply isprog_vars_nil_implies_isprog; auto.
Qed.
Lemma isprog_less_than {o} :
forall a b : @NTerm o,
isprog (mk_less_than a b) <=> (isprog a # isprog b).
Proof.
introv.
allrw @isprog_vars_nil_iff_isprog.
apply isprog_vars_less_than.
Qed.
Lemma isprog_less_than_implies {o} :
forall a b : @NTerm o,
isprog a
-> isprog b
-> isprog (mk_less_than a b).
Proof.
introv x y.
apply isprog_less_than; sp.
Qed.
Lemma isprog_vars_prod_implies {p} :
forall vs (a b : @NTerm p),
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_prod a b).
Proof.
introv ispa ispb.
apply isprog_vars_prod; sp.
Qed.
Lemma isprog_vars_less_than_implies {o} :
forall (a b : @NTerm o) vs,
isprog_vars vs a
-> isprog_vars vs b
-> isprog_vars vs (mk_less_than a b).
Proof.
introv u v.
apply isprog_vars_less_than; sp.
Qed.
Lemma isprog_ot_iff {p} :
forall (o : @Opid p) (bts : list BTerm),
isprog (oterm o bts)
<=>
map num_bvars bts = OpBindings o
# (forall bt : BTerm, LIn bt bts -> isprog_bt bt).
Proof.
introv.
rw @isprog_eq.
rw @isprogram_ot_iff; split; intro k; repnd; dands; auto;
introv i; apply isprogram_bt_eq; auto.
Qed.
Lemma isprog_decide_iff {o} :
forall (a : @NTerm o) (v1 : NVar) (a1 : NTerm) (v2 : NVar) (a2 : NTerm),
isprog (mk_decide a v1 a1 v2 a2)
<=> (isprog a # isprog_vars [v1] a1 # isprog_vars [v2] a2).
Proof.
introv.
split; intro k; repnd; try (apply isprog_decide; auto).
unfold mk_decide in k.
rw @isprog_ot_iff in k; repnd; allsimpl; clear k0.
pose proof (k (nobnd a)) as h1; autodimp h1 hyp.
pose proof (k (bterm [v1] a1)) as h2; autodimp h2 hyp.
pose proof (k (bterm [v2] a2)) as h3; autodimp h3 hyp.
Qed.
Lemma isprog_vars_not {o} :
forall vs (t : @NTerm o),
isprog_vars vs (mk_not t) <=> isprog_vars vs t.
Proof.
introv.
unfold mk_not.
rw <- @isprog_vars_fun.
rw @isprog_vars_void_iff.
split; sp.
Qed.
Lemma implies_isprog_vars_not {o} :
forall vs (t : @NTerm o),
isprog_vars vs t -> isprog_vars vs (mk_not t).
Proof.
introv isp.
apply isprog_vars_not; auto.
Qed.
Lemma isprog_vars_disjoint_implies_isprog {o} :
forall vs (t : @NTerm o),
isprog_vars vs t
-> disjoint vs (free_vars t)
-> isprog t.
Proof.
introv isp disj.
allrw @isprog_vars_eq; repnd.
rw @isprog_eq.
constructor; auto.
unfold closed.
apply null_iff_nil.
introv i.
rw subvars_prop in isp0.
applydup isp0 in i.
apply disj in i0; sp.
Qed.
(* end hide *)
(**
We say that a term [t] is covered by a list of variables [vs] if the
free variables of [t] are all in [vs].
*)
Definition covered {p} (t : @NTerm p) (vs : list NVar) :=
subvars (free_vars t) vs.
(* begin hide *)
Lemma covered_proof_irrelevance {p} :
forall t vs,
forall x y : @covered p t vs,
x = y.
Proof.
intros.
apply UIP_dec.
apply bool_dec.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : covered ?t ?vs , H2 : covered ?t ?vs |- _ ] =>
pose proof (covered_proof_irrelevance t vs H2 H1) as h; subst
end : pi.
Lemma isprog_vars_implies_covered {o} :
forall (t : @NTerm o) vs,
isprog_vars vs t -> covered t vs.
Proof.
introv isp.
unfold covered.
allrw @isprog_vars_eq; sp.
Qed.
Hint Resolve isprog_vars_implies_covered : slow.
(* --- isprog hints --- *)
Hint Resolve isprog_lam : isprog.
Hint Resolve isprog_vars_lam : isprog.
Hint Resolve isprog_vars_isect : isprog.
Hint Resolve isprog_vars_base : isprog.
Hint Resolve isprog_vars_equality : isprog.
Hint Resolve isprog_vars_var_if : isprog.
Hint Resolve isprog_vars_if_isprog : isprog.
Hint Extern 100 (LIn _ _) => complete (simpl; sp) : isprog.
Hint Resolve isprog_implies : isprog.
Hint Resolve isprog_vars_btrue : slow.
Hint Resolve isprog_vars_bfalse : slow.
Hint Resolve isprog_vars_le_implies : slow.
Hint Resolve isprog_vars_less_than_implies : slow.
Hint Resolve isprog_vars_prod_implies : slow.
Hint Resolve wf_function : slow.
Hint Resolve wf_product : slow.
Lemma ispexc_exception {p} :
forall a e : @NTerm p,
isprogram a -> isprogram e -> ispexc (mk_exception a e).
Proof.
introv isp1 isp2.
split.
constructor.
apply isprogram_exception; auto.
Qed.
Hint Resolve ispexc_exception.
Lemma isp_can_or_exc_exception {p} :
forall a e : @NTerm p,
isprogram a
-> isprogram e
-> isp_can_or_exc (mk_exception a e).
Proof.
introv isp1 isp2.
split; auto.
apply isprogram_exception; auto.
right; sp.
Qed.
Hint Resolve isp_can_or_exc_exception.
Lemma free_vars_list_nil {p} :
forall ts : list (@NTerm p),
(forall t, LIn t ts -> isprog t)
-> free_vars_list ts = [].
Proof.
induction ts; introv h; allsimpl; auto.
allrw IHts; sp.
pose proof (h a) as k; autodimp k hyp.
apply isprog_eq in k.
inversion k.
allunfold @closed.
allrw; sp.
Qed.
Lemma newvarlst_prog {p} :
forall ts : list (@NTerm p),
(forall t, LIn t ts -> isprog t)
-> newvarlst ts = nvarx.
Proof.
introv h.
unfold newvarlst.
rw @free_vars_list_nil; auto.
Qed.
Lemma nt_wf_oterm_iff {p} :
forall o (bts : list (@BTerm p)),
nt_wf (oterm o bts)
<=> map num_bvars bts = OpBindings o
# forall b, LIn b bts -> bt_wf b.
Proof.
introv. sp_iff Case; introv h; repnd.
- Case "->".
inverts h as Hbf Hmap. split; auto.
- Case "<-".
constructor; auto.
Qed.
Lemma isprog_vars_ot_iff {p} :
forall (vs : list NVar) (o : @Opid p) (bts : list BTerm),
isprog_vars vs (oterm o bts)
<=>
map num_bvars bts = OpBindings o
# (forall l t, LIn (bterm l t) bts -> isprog_vars (vs ++ l) t).
Proof.
introv.
rw @isprog_vars_eq; simpl.
rw @nt_wf_oterm_iff.
rw subvars_flat_map.
split; intro k; repnd; dands; auto; introv i.
- apply isprog_vars_eq; dands.
apply k0 in i; simpl in i.
rw subvars_remove_nvars in i; auto.
apply k in i; inversion i; subst; auto.
- destruct x; simpl.
rw subvars_remove_nvars.
apply k in i.
apply isprog_vars_eq in i; repnd; auto.
- destruct b.
apply k in i.
apply isprog_vars_eq in i; repnd; auto.
Qed.
Lemma nt_wf_bottom {o} : nt_wf (@mk_bottom o).
Proof.
repeat constructor; simpl; introv i; dorn i; cpx; subst.
repeat constructor; simpl; introv i; dorn i; cpx; subst.
repeat constructor; simpl; introv i; dorn i; cpx; subst.
Qed.
Lemma closed_if_program {o} :
forall t : @NTerm o, isprogram t -> closed t.
Proof.
introv isp; destruct isp; auto.
Qed.
Hint Resolve closed_if_program : slow.
Definition mk_compop {p} x (a b c d : @NTerm p) :=
oterm (NCan (NCompOp x)) [nobnd a, nobnd b, nobnd c, nobnd d].
Lemma wf_compop {p} :
forall x (a b c d : @NTerm p),
wf_term a -> wf_term b -> wf_term c -> wf_term d
-> wf_term (mk_compop x a b c d).
Proof.
introv wa wb wc wd; allrw <- @nt_wf_eq.
constructor; simpl; tcsp.
introv k; repndors; subst; tcsp; constructor; auto.
Qed.
Lemma wf_compop_iff {p} :
forall x (a b c d : @NTerm p),
wf_term (mk_compop x a b c d) <=> (wf_term a # wf_term b # wf_term c # wf_term d).
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i e]; subst; allsimpl.
pose proof (i (nobnd a)) as ha.
pose proof (i (nobnd b)) as hb.
pose proof (i (nobnd c)) as hc.
pose proof (i (nobnd d)) as hd.
repeat (autodimp ha hyp).
repeat (autodimp hb hyp).
repeat (autodimp hc hyp).
repeat (autodimp hd hyp).
inversion ha; subst.
inversion hb; subst.
inversion hc; subst.
inversion hd; subst; sp.
- apply wf_compop; sp.
Qed.
Definition mk_arithop {p} x (a b : @NTerm p) :=
oterm (NCan (NArithOp x)) [nobnd a, nobnd b].
Lemma wf_arithop {p} :
forall x (a b : @NTerm p),
wf_term a -> wf_term b
-> wf_term (mk_arithop x a b).
Proof.
introv wa wb; allrw <- @nt_wf_eq.
constructor; simpl; tcsp.
introv k; repndors; subst; tcsp; constructor; auto.
Qed.
Lemma wf_arithop_iff {p} :
forall x (a b : @NTerm p),
wf_term (mk_arithop x a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i e]; subst; allsimpl.
pose proof (i (nobnd a)) as ha.
pose proof (i (nobnd b)) as hb.
repeat (autodimp ha hyp).
repeat (autodimp hb hyp).
inversion ha; subst.
inversion hb; subst; sp.
- apply wf_arithop; sp.
Qed.
Lemma isprog_arithop {p} :
forall (op: ArithOp) (a b : @NTerm p), isprog a -> isprog b -> isprog (mk_arithop op a b).
Proof.
sp; allrw @isprog_eq; intros; apply isprogram_arithop_iff; sp.
exists a b; auto.
Qed.
Definition mkc_arithop {p} (op: ArithOp) (t1 t2 : @CTerm p) : CTerm :=
let (a,x) := t1 in
let (b,y) := t2 in
exist isprog (mk_arithop op a b) (isprog_arithop op a b x y).
Lemma wf_can_test {p} :
forall x (a b c : @NTerm p),
wf_term a -> wf_term b -> wf_term c
-> wf_term (mk_can_test x a b c).
Proof.
introv wa wb wc; allrw <- @nt_wf_eq.
constructor; simpl; tcsp.
introv k; repndors; subst; tcsp; constructor; auto.
Qed.
Lemma wf_can_test_iff {p} :
forall x (a b c : @NTerm p),
wf_term (mk_can_test x a b c) <=> (wf_term a # wf_term b # wf_term c).
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i e]; subst; allsimpl.
pose proof (i (nobnd a)) as ha.
pose proof (i (nobnd b)) as hb.
pose proof (i (nobnd c)) as hc.
repeat (autodimp ha hyp).
repeat (autodimp hb hyp).
repeat (autodimp hc hyp).
inversion ha; subst.
inversion hb; subst.
inversion hc; subst; sp.
- apply wf_can_test; sp.
Qed.
Lemma wf_dsup {p} :
forall (a : @NTerm p) v1 v2 b,
wf_term (mk_dsup a v1 v2 b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1,v2] b)); clear bwf; intros bwf1 bwf2.
autodimp bwf1 hyp; autodimp bwf2 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; sp.
allsimpl; sp; subst; constructor; allrw @nt_wf_eq; sp.
Qed.
Lemma wf_sup_iff {p} :
forall a b : @NTerm p, wf_term (mk_sup a b) <=> (wf_term a # wf_term b).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)) (bw (nobnd b)); simpl; intros bw1 bw2.
autodimp bw1 hyp.
autodimp bw2 hyp.
inversion bw1; subst.
inversion bw2; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_refl_iff {p} :
forall a : @NTerm p, wf_term (mk_refl a) <=> wf_term a.
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)); simpl; intros bw1.
autodimp bw1 hyp.
inversion bw1; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_inl {p} :
forall a : @NTerm p, wf_term (mk_inl a) <=> wf_term a.
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)); simpl; intros bw1.
autodimp bw1 hyp.
inversion bw1; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_inr {p} :
forall a : @NTerm p, wf_term (mk_inr a) <=> wf_term a.
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bw e]; subst.
generalize (bw (nobnd a)); simpl; intros bw1.
autodimp bw1 hyp.
inversion bw1; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; simpl; sp; subst; constructor; rw @nt_wf_eq; sp.
Qed.
Lemma wf_decide {p} :
forall (a : @NTerm p) v1 b1 v2 b2,
wf_term (mk_decide a v1 b1 v2 b2) <=> (wf_term a # wf_term b1 # wf_term b2).
Proof.
introv; split; intro w; repnd.
rw @wf_term_eq in w.
inversion w as [|?| o l bwf e ]; subst.
generalize (bwf (nobnd a)) (bwf (bterm [v1] b1)) (bwf (bterm [v2] b2));
clear bwf; intros bwf1 bwf2 bwf3.
autodimp bwf1 hyp; autodimp bwf2 hyp; autodimp bwf3 hyp; try (complete (simpl; sp)).
inversion bwf1; subst.
inversion bwf2; subst.
inversion bwf3; subst.
allrw @nt_wf_eq; sp.
apply nt_wf_eq.
constructor; sp.
allsimpl; sp; subst; constructor; allrw @nt_wf_eq; sp.
Qed.
Lemma wf_fix_iff {p} :
forall t : @NTerm p,
wf_term (mk_fix t) <=> wf_term t.
Proof.
introv; split; intro k.
- allrw @wf_term_eq.
inversion k as [|?|? ? i]; allsimpl; subst; ginv.
pose proof (i (bterm [] t)) as h; autodimp h hyp.
inversion h; subst; auto.
- apply wf_fix; auto.
Qed.
Lemma closed_bt_bterm {o} :
forall vs (t : @NTerm o),
closed_bt (bterm vs t)
<=> subvars (free_vars t) vs.
Proof.
introv.
unfold closed_bt; simpl.
rw nil_remove_nvars_iff.
rw subvars_prop; sp.
Qed.
Lemma wf_fresh {p} :
forall v (b : @NTerm p), wf_term b -> wf_term (mk_fresh v b).
Proof.
intros v b; repeat (rw <- @nt_wf_eq).
intros ntb; inversion ntb; subst; constructor; allsimpl; sp; subst; constructor; sp.
Qed.
Lemma wf_fresh_iff {p} :
forall v (b : @NTerm p), wf_term (mk_fresh v b) <=> wf_term b.
Proof.
introv; split; intro i; try (apply wf_fresh; sp).
allrw @wf_term_eq.
inversion i as [|?| o lnt k e ]; subst; allsimpl.
generalize (k (bterm [v] b)); intros j.
dest_imp j hyp; sp.
inversion j; subst; sp.
Qed.
Lemma isprog_vars_subvars {o} :
forall (t : @NTerm o) vs1 vs2,
subvars vs1 vs2
-> isprog_vars vs1 t
-> isprog_vars vs2 t.
Proof.
introv sv isp.
allrw @isprog_vars_eq; repnd; dands; auto.
eapply subvars_trans; eauto.
Qed.
Hint Resolve isprog_vars_subvars : slow.
Lemma nt_wf_eapply_iff {p} :
forall (bs : list (@BTerm p)),
nt_wf (oterm (NCan NEApply) bs)
<=> {a : NTerm
$ {b : NTerm
$ bs = [bterm [] a, bterm [] b]
# nt_wf a
# nt_wf b}}.
Proof.
introv; split; intro k.
- inversion k as [|?|? ? imp e]; clear k; subst.
allsimpl.
repeat (destruct bs; allsimpl; ginv).
destruct b as [l1 t1].
destruct b0 as [l2 t2].
allunfold @num_bvars; allsimpl.
destruct l1; ginv.
destruct l2; ginv.
pose proof (imp (bterm [] t1)) as h1.
autodimp h1 hyp.
pose proof (imp (bterm [] t2)) as h2.
autodimp h2 hyp.
allrw @bt_wf_iff.
exists t1 t2; dands; auto.
- exrepnd; subst.
repeat constructor.
introv i; allsimpl; repndors; subst; tcsp.
Qed.
(* end hide *)
|
module top;
reg a, pass;
wire x, y, ab;
assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1;
assign y = a;
// We need this since Icarus currently has a bug when forcing from
// an expression (it only uses the value when the force ran).
assign ab = ~a;
tran (x, y);
initial begin
// $monitor ($realtime,, x,y,,a);
pass = 1'b1;
// Check matching values.
#1 if ( x !== 1'bx || y !== 1'bx) begin
$display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y);
pass = 1'b0;
end
#1 a = 1'b0;
#1 if ( x !== 1'b0 || y !== 1'b0) begin
$display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y);
pass = 1'b0;
end
#1 a = 1'b1;
#1 if ( x !== 1'b1 || y !== 1'b1) begin
$display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y);
pass = 1'b0;
end
// Now force and release the driving signal.
#1 force a = 1'bx;
#1 if ( x !== 1'bx || y !== 1'bx) begin
$display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y);
pass = 1'b0;
end
#1 release a;
a = 1'b0;
#1 if ( x !== 1'b0 || y !== 1'b0) begin
$display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y);
pass = 1'b0;
end
// Check that the other driver works.
#1 a = 1'bz;
#1 if ( x !== 1'b1 || y !== 1'b1) begin
$display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 08:42:14 AM
// Design Name:
// Module Name: ROM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ROM_test #(parameter W=32, parameter N=0)
(
input wire [9:0] address,
output reg [W-1:0] data
);
localparam ROM_FILE32_A ="/media/francis/Acer/Proyecto de graduacion/Link to GitHub/Proyecto_De_Graduacion/TXTVerification/Hexadecimal_A.txt";
localparam ROM_FILE64_A="/media/francis/Acer/Proyecto de graduacion/Link to GitHub/Proyecto_De_Graduacion/TXTVerification/Hexadecimal_A.txt";
localparam ROM_FILE32_B= "/media/francis/Acer/Proyecto de graduacion/Link to GitHub/Proyecto_De_Graduacion/TXTVerification/Hexadecimal_B.txt";
localparam ROM_FILE64_B= "/media/francis/Acer/Proyecto de graduacion/Link to GitHub/Proyecto_De_Graduacion/TXTVerification/Hexadecimal_B.txt";
//(* rom_style="{distributed | block}" *)
reg [W-1:0] rom_test [1023:0];
generate
if(W==32)
initial
begin
if(N==0)
$readmemh(ROM_FILE32_A, rom_test, 0, 1023);
else
$readmemh(ROM_FILE32_B, rom_test, 0, 1023);
end
else
initial
begin
if(N==0)
$readmemh(ROM_FILE64_A, rom_test, 0, 1023);
else
$readmemh(ROM_FILE64_B, rom_test, 0, 1023);
end
endgenerate
always @*
begin
data = rom_test[address];
end
endmodule
|
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
reg `control_w flit1c;
reg `data_w flit1d;
reg `control_w flit2c;
reg `data_w flit2d;
reg `control_w flit3c;
reg `data_w flit3d;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(flit2c), .port2_co(port2_co),
.port3_ci(flit3c), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(flit1d), .port1_do(port1_do),
.port2_di(flit2d), .port2_do(port2_do),
.port3_di(flit3d), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
flit0c = 22'h200001;
flit0d = 128'h0123456789abcdef0123456789abcdef;
flit1c = 22'h200802;
flit1d = 128'h0123456789abcdef0123456789abcdef;
flit2c = 22'h200c03;
flit2d = 128'h0123456789abcdef0123456789abcdef;
flit3c = 22'h201804;
flit3d = 128'h0123456789abcdef0123456789abcdef;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 22'h0;
flit0d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:20:29 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26,
n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40,
n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82,
n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96,
n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119,
n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152,
n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163,
n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313;
NAND2X1TS U47 ( .A(n37), .B(n196), .Y(n197) );
NAND2X1TS U48 ( .A(n163), .B(n35), .Y(n160) );
NAND2X1TS U49 ( .A(n211), .B(n210), .Y(n212) );
NAND2X1TS U50 ( .A(n225), .B(n224), .Y(n226) );
NAND2X1TS U51 ( .A(n177), .B(n176), .Y(n178) );
NAND2X1TS U52 ( .A(n218), .B(n217), .Y(n219) );
NAND2X1TS U53 ( .A(n36), .B(n186), .Y(n187) );
INVX4TS U54 ( .A(n204), .Y(n231) );
INVX1TS U55 ( .A(n223), .Y(n225) );
INVX1TS U56 ( .A(n209), .Y(n211) );
NOR2X1TS U57 ( .A(n298), .B(in2[5]), .Y(n308) );
NOR2X2TS U58 ( .A(n191), .B(n150), .Y(n152) );
NAND2X1TS U59 ( .A(n295), .B(n294), .Y(n298) );
NAND2X2TS U60 ( .A(n36), .B(n41), .Y(n150) );
INVX2TS U61 ( .A(n253), .Y(n30) );
XNOR2X1TS U62 ( .A(n169), .B(in2[31]), .Y(n170) );
MX2X1TS U63 ( .A(in2[29]), .B(n155), .S0(n17), .Y(n156) );
NOR2X1TS U64 ( .A(n168), .B(in2[30]), .Y(n169) );
INVX2TS U65 ( .A(n199), .Y(n145) );
NOR2X6TS U66 ( .A(n120), .B(in1[22]), .Y(n223) );
NAND2X2TS U67 ( .A(n120), .B(in1[22]), .Y(n224) );
NOR2X4TS U68 ( .A(n121), .B(in1[23]), .Y(n216) );
NOR2X2TS U69 ( .A(n119), .B(in1[21]), .Y(n221) );
NAND2X2TS U70 ( .A(n143), .B(in1[26]), .Y(n196) );
MXI2X4TS U71 ( .A(n109), .B(n108), .S0(n139), .Y(n121) );
NOR2X6TS U72 ( .A(n90), .B(in1[18]), .Y(n244) );
NAND2X6TS U73 ( .A(n82), .B(n38), .Y(n31) );
NAND2X2TS U74 ( .A(n90), .B(in1[18]), .Y(n245) );
XNOR2X1TS U75 ( .A(n115), .B(in2[20]), .Y(n96) );
OR2X6TS U76 ( .A(n87), .B(in1[17]), .Y(n38) );
INVX6TS U77 ( .A(n251), .Y(n82) );
OR2X4TS U78 ( .A(n81), .B(in1[16]), .Y(n39) );
NAND2X1TS U79 ( .A(n134), .B(n133), .Y(n137) );
NAND2X4TS U80 ( .A(n81), .B(in1[16]), .Y(n251) );
NOR2X2TS U81 ( .A(in2[25]), .B(in2[24]), .Y(n134) );
AND2X2TS U82 ( .A(n95), .B(n94), .Y(n103) );
XNOR2X1TS U83 ( .A(n73), .B(in2[12]), .Y(n60) );
INVX2TS U84 ( .A(add_sub), .Y(n139) );
NAND2BX1TS U85 ( .AN(n49), .B(n48), .Y(n50) );
INVX4TS U86 ( .A(in2[9]), .Y(n303) );
INVX2TS U87 ( .A(in2[8]), .Y(n43) );
NOR2XLTS U88 ( .A(in2[19]), .B(in2[18]), .Y(n94) );
INVX6TS U89 ( .A(in2[7]), .Y(n33) );
CLKMX2X2TS U90 ( .A(n75), .B(in2[15]), .S0(n300), .Y(n76) );
CLKMX2X2TS U91 ( .A(in2[30]), .B(n158), .S0(n17), .Y(n159) );
INVX12TS U92 ( .A(in2[6]), .Y(n307) );
INVX2TS U93 ( .A(n244), .Y(n13) );
NOR2XLTS U94 ( .A(n26), .B(n25), .Y(n246) );
INVX6TS U95 ( .A(n189), .Y(n202) );
OAI21XLTS U96 ( .A0(n301), .A1(n300), .B0(n299), .Y(res[6]) );
NAND2X2TS U97 ( .A(n87), .B(in1[17]), .Y(n248) );
INVX2TS U98 ( .A(add_sub), .Y(n312) );
INVX4TS U99 ( .A(n139), .Y(n17) );
NAND2X2TS U100 ( .A(n34), .B(n173), .Y(n172) );
INVX2TS U101 ( .A(n196), .Y(n144) );
NAND2BX2TS U102 ( .AN(in2[29]), .B(n157), .Y(n168) );
NAND2X2TS U103 ( .A(n111), .B(n110), .Y(n112) );
MX2X2TS U104 ( .A(n60), .B(in2[12]), .S0(n310), .Y(n61) );
BUFX6TS U105 ( .A(n312), .Y(n310) );
BUFX6TS U106 ( .A(n312), .Y(n300) );
NOR2X4TS U107 ( .A(in2[21]), .B(in2[20]), .Y(n110) );
NAND2X2TS U108 ( .A(n35), .B(n177), .Y(n167) );
OR2X4TS U109 ( .A(n159), .B(in1[30]), .Y(n35) );
INVX2TS U110 ( .A(n216), .Y(n218) );
NAND2X4TS U111 ( .A(n119), .B(in1[21]), .Y(n228) );
MXI2X4TS U112 ( .A(n89), .B(n88), .S0(add_sub), .Y(n90) );
XOR2X2TS U113 ( .A(n116), .B(in2[21]), .Y(n117) );
NOR2X4TS U114 ( .A(n115), .B(in2[20]), .Y(n116) );
NOR2X4TS U115 ( .A(n76), .B(in1[15]), .Y(n255) );
NOR2X2TS U116 ( .A(in2[23]), .B(in2[22]), .Y(n102) );
XOR2X1TS U117 ( .A(n213), .B(n212), .Y(res[24]) );
XNOR2X2TS U118 ( .A(n188), .B(n187), .Y(res[28]) );
XOR2X1TS U119 ( .A(n243), .B(n242), .Y(res[19]) );
XOR2X1TS U120 ( .A(n247), .B(n246), .Y(res[18]) );
NAND2X1TS U121 ( .A(n14), .B(n39), .Y(n28) );
AOI21X2TS U122 ( .A0(n35), .A1(n165), .B0(n164), .Y(n166) );
OR2X2TS U123 ( .A(n171), .B(in1[31]), .Y(n34) );
INVX2TS U124 ( .A(n30), .Y(n14) );
NOR2X4TS U125 ( .A(n29), .B(n244), .Y(n24) );
NAND2X2TS U126 ( .A(n171), .B(in1[31]), .Y(n173) );
NAND2X6TS U127 ( .A(n37), .B(n200), .Y(n191) );
NOR2X2TS U128 ( .A(n239), .B(n234), .Y(n101) );
INVX2TS U129 ( .A(n176), .Y(n165) );
NAND2X2TS U130 ( .A(n159), .B(in1[30]), .Y(n163) );
NAND2X6TS U131 ( .A(n39), .B(n38), .Y(n29) );
MX2X2TS U132 ( .A(in2[31]), .B(n170), .S0(n17), .Y(n171) );
NAND2X4TS U133 ( .A(n146), .B(in1[27]), .Y(n192) );
XOR2X1TS U134 ( .A(n269), .B(n268), .Y(res[13]) );
XNOR2X2TS U135 ( .A(n128), .B(in2[26]), .Y(n129) );
INVX2TS U136 ( .A(n259), .Y(n268) );
MXI2X4TS U137 ( .A(n141), .B(n140), .S0(n139), .Y(n146) );
NAND2X2TS U138 ( .A(n99), .B(in1[20]), .Y(n235) );
XOR2X2TS U139 ( .A(n130), .B(in2[25]), .Y(n131) );
INVX4TS U140 ( .A(n154), .Y(n127) );
NOR2X6TS U141 ( .A(n83), .B(in2[16]), .Y(n84) );
NOR2X6TS U142 ( .A(n68), .B(in1[14]), .Y(n260) );
MXI2X4TS U143 ( .A(n66), .B(n71), .S0(n310), .Y(n68) );
OAI21X1TS U144 ( .A0(n313), .A1(n312), .B0(n311), .Y(res[7]) );
OAI21XLTS U145 ( .A0(n290), .A1(n300), .B0(n289), .Y(res[10]) );
OAI21XLTS U146 ( .A0(n306), .A1(n312), .B0(n305), .Y(res[9]) );
OAI21XLTS U147 ( .A0(n283), .A1(n312), .B0(n282), .Y(res[8]) );
OAI21XLTS U148 ( .A0(n297), .A1(n300), .B0(n296), .Y(res[5]) );
OAI21XLTS U149 ( .A0(n293), .A1(n300), .B0(n292), .Y(res[4]) );
OAI21XLTS U150 ( .A0(n287), .A1(n312), .B0(n286), .Y(res[3]) );
OAI21XLTS U151 ( .A0(n281), .A1(n300), .B0(n280), .Y(res[1]) );
OAI21XLTS U152 ( .A0(n279), .A1(n312), .B0(n278), .Y(res[2]) );
OR2X2TS U153 ( .A(n137), .B(in2[27]), .Y(n153) );
NOR2X2TS U154 ( .A(in2[17]), .B(in2[16]), .Y(n95) );
OR2X1TS U155 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X4TS U156 ( .A(n98), .B(in1[19]), .Y(n239) );
NOR2X4TS U157 ( .A(n99), .B(in1[20]), .Y(n234) );
NOR2X2TS U158 ( .A(n265), .B(n260), .Y(n70) );
XOR2X2TS U159 ( .A(n63), .B(in2[13]), .Y(n65) );
OAI21X4TS U160 ( .A0(n209), .A1(n217), .B0(n210), .Y(n123) );
NOR3BX2TS U161 ( .AN(n110), .B(n115), .C(in2[22]), .Y(n107) );
NAND2X4TS U162 ( .A(n121), .B(in1[23]), .Y(n217) );
NAND3X8TS U163 ( .A(n23), .B(n20), .C(n18), .Y(n232) );
NOR2X4TS U164 ( .A(n22), .B(n21), .Y(n20) );
NOR2X4TS U165 ( .A(n53), .B(n52), .Y(n54) );
NOR2X4TS U166 ( .A(n288), .B(in2[10]), .Y(n53) );
OR2X4TS U167 ( .A(n54), .B(in1[11]), .Y(n40) );
NAND2X4TS U168 ( .A(n54), .B(in1[11]), .Y(n275) );
XNOR2X2TS U169 ( .A(n161), .B(n160), .Y(res[30]) );
OAI21X2TS U170 ( .A0(n240), .A1(n234), .B0(n235), .Y(n100) );
NOR2X8TS U171 ( .A(n122), .B(in1[24]), .Y(n209) );
NAND2X4TS U172 ( .A(n122), .B(in1[24]), .Y(n210) );
AOI21X4TS U173 ( .A0(n124), .A1(n214), .B0(n123), .Y(n125) );
NOR2X6TS U174 ( .A(n209), .B(n216), .Y(n124) );
OR2X4TS U175 ( .A(n147), .B(in1[28]), .Y(n36) );
MX2X4TS U176 ( .A(in2[28]), .B(n136), .S0(n17), .Y(n147) );
XNOR2X1TS U177 ( .A(n179), .B(n178), .Y(res[29]) );
XNOR2X2TS U178 ( .A(in2[14]), .B(n77), .Y(n66) );
MXI2X4TS U179 ( .A(n106), .B(n105), .S0(n17), .Y(n122) );
OAI2BB1X4TS U180 ( .A0N(n17), .A1N(n65), .B0(n64), .Y(n67) );
INVX4TS U181 ( .A(n56), .Y(n57) );
MXI2X4TS U182 ( .A(n132), .B(n131), .S0(n17), .Y(n142) );
NOR2X4TS U183 ( .A(n154), .B(in2[24]), .Y(n130) );
CLKINVX12TS U184 ( .A(n59), .Y(n73) );
XNOR2X4TS U185 ( .A(n135), .B(in2[28]), .Y(n136) );
NOR2X4TS U186 ( .A(n154), .B(n153), .Y(n135) );
NOR3X4TS U187 ( .A(n154), .B(in2[28]), .C(n153), .Y(n157) );
NAND4X8TS U188 ( .A(n104), .B(n103), .C(n110), .D(n102), .Y(n154) );
NAND2X2TS U189 ( .A(n124), .B(n215), .Y(n126) );
NAND2X1TS U190 ( .A(n300), .B(in2[11]), .Y(n44) );
NAND2X2TS U191 ( .A(n76), .B(in1[15]), .Y(n256) );
INVX2TS U192 ( .A(n195), .Y(n200) );
OR2X4TS U193 ( .A(n143), .B(in1[26]), .Y(n37) );
OR2X4TS U194 ( .A(n146), .B(in1[27]), .Y(n41) );
NAND2X1TS U195 ( .A(n300), .B(in2[13]), .Y(n64) );
NAND2X1TS U196 ( .A(n73), .B(n62), .Y(n63) );
XOR2X1TS U197 ( .A(n104), .B(in2[16]), .Y(n79) );
MXI2X4TS U198 ( .A(n97), .B(n96), .S0(add_sub), .Y(n99) );
NAND2X4TS U199 ( .A(n19), .B(n13), .Y(n18) );
NAND2X4TS U200 ( .A(n253), .B(n24), .Y(n23) );
XNOR2X1TS U201 ( .A(n157), .B(in2[29]), .Y(n155) );
INVX2TS U202 ( .A(in2[2]), .Y(n284) );
INVX4TS U203 ( .A(n275), .Y(n55) );
NOR2X4TS U204 ( .A(n61), .B(in1[12]), .Y(n270) );
NAND2X2TS U205 ( .A(n61), .B(in1[12]), .Y(n271) );
NAND2X4TS U206 ( .A(n67), .B(in1[13]), .Y(n266) );
NOR2X4TS U207 ( .A(in1[13]), .B(n67), .Y(n265) );
NAND2X2TS U208 ( .A(n68), .B(in1[14]), .Y(n261) );
NOR2X1TS U209 ( .A(n30), .B(n29), .Y(n26) );
NAND2X1TS U210 ( .A(n31), .B(n248), .Y(n25) );
NAND2X2TS U211 ( .A(n142), .B(in1[25]), .Y(n199) );
NOR2X2TS U212 ( .A(n142), .B(in1[25]), .Y(n195) );
INVX2TS U213 ( .A(n162), .Y(n177) );
NOR2X2TS U214 ( .A(n156), .B(in1[29]), .Y(n162) );
NAND2X2TS U215 ( .A(n156), .B(in1[29]), .Y(n176) );
OAI21X2TS U216 ( .A0(n182), .A1(n150), .B0(n149), .Y(n151) );
NAND2X1TS U217 ( .A(in2[10]), .B(add_sub), .Y(n47) );
NAND2BX1TS U218 ( .AN(n47), .B(n56), .Y(n46) );
INVX2TS U219 ( .A(in2[10]), .Y(n58) );
NAND2X2TS U220 ( .A(n104), .B(n95), .Y(n91) );
INVX2TS U221 ( .A(n31), .Y(n19) );
NOR2X2TS U222 ( .A(n248), .B(n244), .Y(n22) );
INVX2TS U223 ( .A(n245), .Y(n21) );
INVX2TS U224 ( .A(n115), .Y(n111) );
NAND2X4TS U225 ( .A(n104), .B(n103), .Y(n115) );
XOR2X1TS U226 ( .A(n127), .B(in2[24]), .Y(n105) );
INVX2TS U227 ( .A(n192), .Y(n183) );
AOI21X1TS U228 ( .A0(n36), .A1(n183), .B0(n148), .Y(n149) );
INVX2TS U229 ( .A(n186), .Y(n148) );
INVX2TS U230 ( .A(n163), .Y(n164) );
NAND2X1TS U231 ( .A(n285), .B(n284), .Y(n291) );
INVX2TS U232 ( .A(in2[4]), .Y(n294) );
NAND2X2TS U233 ( .A(n49), .B(n57), .Y(n288) );
NAND2X2TS U234 ( .A(n98), .B(in1[19]), .Y(n240) );
INVX2TS U235 ( .A(n233), .Y(n243) );
CLKBUFX2TS U236 ( .A(n232), .Y(n233) );
INVX2TS U237 ( .A(n221), .Y(n229) );
INVX2TS U238 ( .A(n228), .Y(n222) );
NOR2X4TS U239 ( .A(n223), .B(n221), .Y(n215) );
OAI21X1TS U240 ( .A0(n206), .A1(n216), .B0(n217), .Y(n207) );
NOR2X1TS U241 ( .A(n205), .B(n216), .Y(n208) );
INVX2TS U242 ( .A(n215), .Y(n205) );
CLKBUFX2TS U243 ( .A(n203), .Y(n204) );
NAND2X2TS U244 ( .A(n147), .B(in1[28]), .Y(n186) );
INVX2TS U245 ( .A(n191), .Y(n181) );
AOI21X2TS U246 ( .A0(n184), .A1(n41), .B0(n183), .Y(n185) );
INVX2TS U247 ( .A(n190), .Y(n184) );
NOR2XLTS U248 ( .A(n302), .B(in2[8]), .Y(n304) );
NAND2X1TS U249 ( .A(n40), .B(n275), .Y(n276) );
NAND2X1TS U250 ( .A(n272), .B(n271), .Y(n274) );
INVX2TS U251 ( .A(n270), .Y(n272) );
NAND2X1TS U252 ( .A(n267), .B(n266), .Y(n269) );
INVX2TS U253 ( .A(n265), .Y(n267) );
NAND2X1TS U254 ( .A(n262), .B(n261), .Y(n263) );
INVX2TS U255 ( .A(n260), .Y(n262) );
NAND2X1TS U256 ( .A(n257), .B(n256), .Y(n258) );
INVX2TS U257 ( .A(n255), .Y(n257) );
NAND2X1TS U258 ( .A(n39), .B(n251), .Y(n252) );
NAND2X1TS U259 ( .A(n38), .B(n248), .Y(n249) );
NAND2X1TS U260 ( .A(n28), .B(n27), .Y(n250) );
INVX2TS U261 ( .A(n82), .Y(n27) );
NAND2X1TS U262 ( .A(n13), .B(n245), .Y(n247) );
NAND2X1TS U263 ( .A(n241), .B(n240), .Y(n242) );
INVX2TS U264 ( .A(n239), .Y(n241) );
XNOR2X1TS U265 ( .A(n238), .B(n237), .Y(res[20]) );
NAND2X1TS U266 ( .A(n236), .B(n235), .Y(n237) );
OAI21X1TS U267 ( .A0(n243), .A1(n239), .B0(n240), .Y(n238) );
INVX2TS U268 ( .A(n234), .Y(n236) );
XNOR2X1TS U269 ( .A(n231), .B(n230), .Y(res[21]) );
NAND2X1TS U270 ( .A(n229), .B(n228), .Y(n230) );
XOR2X1TS U271 ( .A(n202), .B(n201), .Y(res[25]) );
NAND2X1TS U272 ( .A(n200), .B(n199), .Y(n201) );
NAND2X1TS U273 ( .A(n41), .B(n192), .Y(n193) );
XNOR2X2TS U274 ( .A(n174), .B(n172), .Y(res[31]) );
AND2X2TS U275 ( .A(n181), .B(n41), .Y(n15) );
INVX2TS U276 ( .A(n302), .Y(n49) );
NAND2X2TS U277 ( .A(n43), .B(n303), .Y(n56) );
AND2X8TS U278 ( .A(n33), .B(n307), .Y(n16) );
XNOR2X1TS U279 ( .A(n264), .B(n263), .Y(res[14]) );
BUFX20TS U280 ( .A(n78), .Y(n104) );
MXI2X8TS U281 ( .A(n114), .B(n113), .S0(n17), .Y(n120) );
NOR2X2TS U282 ( .A(n154), .B(n137), .Y(n138) );
NOR2X8TS U283 ( .A(in2[0]), .B(in2[1]), .Y(n285) );
XNOR2X4TS U284 ( .A(n91), .B(in2[18]), .Y(n88) );
XNOR2X4TS U285 ( .A(n107), .B(n108), .Y(n109) );
XOR2X4TS U286 ( .A(n53), .B(in2[11]), .Y(n45) );
NAND2X8TS U287 ( .A(n42), .B(n32), .Y(n302) );
AND2X8TS U288 ( .A(n16), .B(n285), .Y(n32) );
XOR2X1TS U289 ( .A(n227), .B(n226), .Y(res[22]) );
XOR2X1TS U290 ( .A(n220), .B(n219), .Y(res[23]) );
XNOR2X1TS U291 ( .A(n250), .B(n249), .Y(res[17]) );
OAI21XLTS U292 ( .A0(n268), .A1(n265), .B0(n266), .Y(n264) );
XOR2X4TS U293 ( .A(n84), .B(in2[17]), .Y(n85) );
NOR4X8TS U294 ( .A(in2[5]), .B(in2[4]), .C(in2[3]), .D(in2[2]), .Y(n42) );
XOR2XLTS U295 ( .A(n274), .B(n273), .Y(res[12]) );
XNOR2X4TS U296 ( .A(n112), .B(in2[22]), .Y(n113) );
XNOR2X4TS U297 ( .A(n92), .B(in2[19]), .Y(n93) );
NOR2X4TS U298 ( .A(n91), .B(in2[18]), .Y(n92) );
XNOR2X1TS U299 ( .A(n277), .B(n276), .Y(res[11]) );
XNOR2X1TS U300 ( .A(n14), .B(n252), .Y(res[16]) );
XNOR2X4TS U301 ( .A(n138), .B(n140), .Y(n141) );
NAND2X2TS U302 ( .A(n127), .B(n134), .Y(n128) );
OAI21X4TS U303 ( .A0(n45), .A1(n300), .B0(n44), .Y(n277) );
OAI211X2TS U304 ( .A0(in2[10]), .A1(add_sub), .B0(n46), .C0(in1[10]), .Y(n51) );
INVX2TS U305 ( .A(n47), .Y(n48) );
NAND2BX4TS U306 ( .AN(n51), .B(n50), .Y(n52) );
AOI21X4TS U307 ( .A0(n277), .A1(n40), .B0(n55), .Y(n273) );
NAND4BBX4TS U308 ( .AN(n302), .BN(in2[11]), .C(n58), .D(n57), .Y(n59) );
OAI21X4TS U309 ( .A0(n273), .A1(n270), .B0(n271), .Y(n259) );
INVX2TS U310 ( .A(in2[12]), .Y(n62) );
NOR2X2TS U311 ( .A(in2[13]), .B(in2[12]), .Y(n72) );
NAND2X8TS U312 ( .A(n73), .B(n72), .Y(n77) );
INVX2TS U313 ( .A(in2[14]), .Y(n71) );
OAI21X4TS U314 ( .A0(n260), .A1(n266), .B0(n261), .Y(n69) );
AOI21X4TS U315 ( .A0(n259), .A1(n70), .B0(n69), .Y(n254) );
NAND3X1TS U316 ( .A(n73), .B(n72), .C(n71), .Y(n74) );
XOR2X1TS U317 ( .A(n74), .B(in2[15]), .Y(n75) );
OAI21X4TS U318 ( .A0(n254), .A1(n255), .B0(n256), .Y(n253) );
INVX2TS U319 ( .A(in2[16]), .Y(n80) );
NOR3X8TS U320 ( .A(n77), .B(in2[15]), .C(in2[14]), .Y(n78) );
MXI2X4TS U321 ( .A(n80), .B(n79), .S0(add_sub), .Y(n81) );
INVX2TS U322 ( .A(in2[17]), .Y(n86) );
INVX3TS U323 ( .A(n104), .Y(n83) );
MXI2X4TS U324 ( .A(n86), .B(n85), .S0(add_sub), .Y(n87) );
INVX2TS U325 ( .A(in2[18]), .Y(n89) );
MX2X4TS U326 ( .A(in2[19]), .B(n93), .S0(add_sub), .Y(n98) );
INVX2TS U327 ( .A(in2[20]), .Y(n97) );
AOI21X4TS U328 ( .A0(n232), .A1(n101), .B0(n100), .Y(n203) );
INVX2TS U329 ( .A(in2[24]), .Y(n106) );
INVX2TS U330 ( .A(in2[23]), .Y(n108) );
INVX2TS U331 ( .A(in2[22]), .Y(n114) );
INVX2TS U332 ( .A(in2[21]), .Y(n118) );
MXI2X4TS U333 ( .A(n118), .B(n117), .S0(add_sub), .Y(n119) );
OAI21X4TS U334 ( .A0(n223), .A1(n228), .B0(n224), .Y(n214) );
OAI21X4TS U335 ( .A0(n203), .A1(n126), .B0(n125), .Y(n180) );
INVX2TS U336 ( .A(in2[26]), .Y(n133) );
MXI2X4TS U337 ( .A(n133), .B(n129), .S0(n17), .Y(n143) );
INVX2TS U338 ( .A(in2[25]), .Y(n132) );
INVX2TS U339 ( .A(in2[27]), .Y(n140) );
AOI21X4TS U340 ( .A0(n37), .A1(n145), .B0(n144), .Y(n182) );
AOI21X4TS U341 ( .A0(n180), .A1(n152), .B0(n151), .Y(n175) );
OAI21X2TS U342 ( .A0(n175), .A1(n162), .B0(n176), .Y(n161) );
XOR2X1TS U343 ( .A(n168), .B(in2[30]), .Y(n158) );
OAI21X4TS U344 ( .A0(n167), .A1(n175), .B0(n166), .Y(n174) );
OAI2BB1X4TS U345 ( .A0N(n174), .A1N(n34), .B0(n173), .Y(res[32]) );
INVX2TS U346 ( .A(n175), .Y(n179) );
BUFX4TS U347 ( .A(n180), .Y(n189) );
BUFX4TS U348 ( .A(n182), .Y(n190) );
OAI2BB1X4TS U349 ( .A0N(n189), .A1N(n15), .B0(n185), .Y(n188) );
OAI21X4TS U350 ( .A0(n202), .A1(n191), .B0(n190), .Y(n194) );
XNOR2X2TS U351 ( .A(n194), .B(n193), .Y(res[27]) );
OAI21X4TS U352 ( .A0(n202), .A1(n195), .B0(n199), .Y(n198) );
XNOR2X2TS U353 ( .A(n198), .B(n197), .Y(res[26]) );
INVX2TS U354 ( .A(n214), .Y(n206) );
AOI21X4TS U355 ( .A0(n231), .A1(n208), .B0(n207), .Y(n213) );
AOI21X4TS U356 ( .A0(n231), .A1(n215), .B0(n214), .Y(n220) );
AOI21X4TS U357 ( .A0(n231), .A1(n229), .B0(n222), .Y(n227) );
XOR2XLTS U358 ( .A(n254), .B(n258), .Y(res[15]) );
XNOR2X1TS U359 ( .A(n285), .B(n284), .Y(n279) );
AOI21X1TS U360 ( .A0(n312), .A1(in2[2]), .B0(in1[2]), .Y(n278) );
XNOR2X1TS U361 ( .A(in2[0]), .B(in2[1]), .Y(n281) );
AOI21X1TS U362 ( .A0(n310), .A1(in2[1]), .B0(in1[1]), .Y(n280) );
XNOR2X1TS U363 ( .A(n302), .B(in2[8]), .Y(n283) );
AOI21X1TS U364 ( .A0(n310), .A1(in2[8]), .B0(in1[8]), .Y(n282) );
XNOR2X1TS U365 ( .A(n291), .B(in2[3]), .Y(n287) );
AOI21X1TS U366 ( .A0(n312), .A1(in2[3]), .B0(in1[3]), .Y(n286) );
XNOR2X1TS U367 ( .A(n288), .B(in2[10]), .Y(n290) );
AOI21X1TS U368 ( .A0(n310), .A1(in2[10]), .B0(in1[10]), .Y(n289) );
NOR2X1TS U369 ( .A(n291), .B(in2[3]), .Y(n295) );
XNOR2X1TS U370 ( .A(n295), .B(n294), .Y(n293) );
AOI21X1TS U371 ( .A0(n310), .A1(in2[4]), .B0(in1[4]), .Y(n292) );
XNOR2X1TS U372 ( .A(n298), .B(in2[5]), .Y(n297) );
AOI21X1TS U373 ( .A0(n310), .A1(in2[5]), .B0(in1[5]), .Y(n296) );
XNOR2X1TS U374 ( .A(n308), .B(n307), .Y(n301) );
AOI21X1TS U375 ( .A0(n310), .A1(in2[6]), .B0(in1[6]), .Y(n299) );
XNOR2X1TS U376 ( .A(n304), .B(n303), .Y(n306) );
AOI21X1TS U377 ( .A0(n310), .A1(in2[9]), .B0(in1[9]), .Y(n305) );
NAND2X1TS U378 ( .A(n308), .B(n307), .Y(n309) );
XNOR2X1TS U379 ( .A(n309), .B(in2[7]), .Y(n313) );
AOI21X1TS U380 ( .A0(n310), .A1(in2[7]), .B0(in1[7]), .Y(n311) );
initial $sdf_annotate("Approx_adder_LOALPL11_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_TB_V
`define SKY130_FD_SC_HS__O221AI_TB_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 B2 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 B2 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B2 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B2 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o221ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH
// Engineer: Tomasz Kryjak
//
// Create Date: 11:29:28 10/28/2013
// Design Name:
// Module Name: tb_filter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_hdmi(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
// proccessing
wire [7:0] Y;
wire [7:0] Cb;
wire [7:0] Cr;
wire conv_hsync;
wire conv_vsync;
wire conv_de;
rgb2ycbcr conversion
(
.clk(rx_pclk),
.ce(1'b1),
.R(rx_red),
.G(rx_green),
.B(rx_blue),
.in_hsync(rx_hsync),
.in_vsync(rx_vsync),
.in_de(rx_de),
.Y(Y),
.Cb(Cb),
.Cr(Cr),
.out_hsync(conv_hsync),
.out_vsync(conv_vsync),
.out_de(conv_de)
);
wire [7:0] binary;
ycbcr_thresholding thresholding
(
.Y(Y),
.Cb(Cb),
.Cr(Cr),
.Ta(8'd90),
.Tb(8'd140),
.Tc(8'd90),
.Td(8'd126),
.binary(binary)
);
wire [7:0] cross_r;
wire [7:0] cross_g;
wire [7:0] cross_b;
//wire [9:0] centr_x;
//wire [9:0] centr_y;
wire [9:0] curr_w;
wire [9:0] curr_h;
//centroid #
//(
// .IMG_W(64),
// .IMG_H(64)
//)
//centro
//(
// .clk(rx_pclk),
// .ce(1'b1),
// .rst(1'b0),
// .de(conv_de),
// .hsync(conv_hsync),
// .vsync(conv_vsync),
// .mask((binary == 8'hFF) ? 1'b0 : 1'b1),
// .x(centr_x),
// .y(centr_y),
//
// .c_h(curr_h),
// .c_w(curr_w)
//);
reg [9:0] centr_x = 10'd20;
reg [9:0] centr_y = 10'd30;
assign cross_r = ((curr_w[9:0] == centr_x || curr_h[9:0] == centr_y) ? 8'hff : binary);
assign cross_g = ((curr_w[9:0] == centr_x || curr_h[9:0] == centr_y) ? 8'h0 : binary);
assign cross_b = ((curr_w[9:0] == centr_x || curr_h[9:0] == centr_y) ? 8'h0 : binary);
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = conv_de;
assign tx_hsync = conv_hsync;
assign tx_vsync = conv_vsync;
assign tx_red = cross_r;
assign tx_green = cross_g;
assign tx_blue = cross_b;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_CS_X.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_BCH_CS_X
// File Name: d_BCH_CS_X.v
//
// Version: v1.0.0-256B_T14
//
// Description:
// - BCH decoder: Chien search (CS) array
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_BCH_CS_X
#
(
parameter Multi = 2,
parameter GF = 12
)
(
i_clk,
i_RESET,
i_exe_cs,
i_data_fowarding,
i_MUX_data_ready,
i_BRAM_read_data,
i_v_000,
i_v_001,
i_v_002,
i_v_003,
i_v_004,
i_v_005,
i_v_006,
i_v_007,
i_v_008,
i_v_009,
i_v_010,
i_v_011,
i_v_012,
i_v_013,
i_v_014,
o_cs_available,
o_cs_cmplt,
o_BRAM_read_enable,
o_BRAM_read_address,
o_c_message_valid,
o_c_message_output_cmplt,
o_c_message
);
input i_clk;
input i_RESET;
input i_exe_cs;
input [Multi - 1:0] i_data_fowarding;
input i_MUX_data_ready;
input [Multi*8 - 1:0] i_BRAM_read_data;
input [GF*Multi - 1:0] i_v_000;
input [GF*Multi - 1:0] i_v_001;
input [GF*Multi - 1:0] i_v_002;
input [GF*Multi - 1:0] i_v_003;
input [GF*Multi - 1:0] i_v_004;
input [GF*Multi - 1:0] i_v_005;
input [GF*Multi - 1:0] i_v_006;
input [GF*Multi - 1:0] i_v_007;
input [GF*Multi - 1:0] i_v_008;
input [GF*Multi - 1:0] i_v_009;
input [GF*Multi - 1:0] i_v_010;
input [GF*Multi - 1:0] i_v_011;
input [GF*Multi - 1:0] i_v_012;
input [GF*Multi - 1:0] i_v_013;
input [GF*Multi - 1:0] i_v_014;
output o_cs_available;
output [Multi - 1:0] o_cs_cmplt;
output [Multi - 1:0] o_BRAM_read_enable;
output [Multi*8 - 1:0] o_BRAM_read_address;
output [Multi - 1:0] o_c_message_valid;
output [Multi - 1:0] o_c_message_output_cmplt;
output [Multi*8 - 1:0] o_c_message;
wire [Multi - 1:0] w_cs_available;
wire [Multi - 1:0] w_cs_start;
wire [Multi - 1:0] w_cs_pause;
wire [Multi - 1:0] w_c_message_output_start;
genvar i;
generate
for (i = 0; i < Multi; i = i + 1)
begin
d_BCH_CS_top
d_clustered_CS
(
.i_clk (i_clk ),
.i_RESET (i_RESET ),
.i_stop_dec (1'b0 ),
.o_cs_available (w_cs_available[i] ),
.i_exe_cs (i_exe_cs ),
.i_data_fowarding (i_data_fowarding[i] ),
.i_MUX_data_ready (i_MUX_data_ready ),
.i_v_000 (i_v_000[GF * (i+1) - 1 : GF * i] ),
.i_v_001 (i_v_001[GF * (i+1) - 1 : GF * i] ),
.i_v_002 (i_v_002[GF * (i+1) - 1 : GF * i] ),
.i_v_003 (i_v_003[GF * (i+1) - 1 : GF * i] ),
.i_v_004 (i_v_004[GF * (i+1) - 1 : GF * i] ),
.i_v_005 (i_v_005[GF * (i+1) - 1 : GF * i] ),
.i_v_006 (i_v_006[GF * (i+1) - 1 : GF * i] ),
.i_v_007 (i_v_007[GF * (i+1) - 1 : GF * i] ),
.i_v_008 (i_v_008[GF * (i+1) - 1 : GF * i] ),
.i_v_009 (i_v_009[GF * (i+1) - 1 : GF * i] ),
.i_v_010 (i_v_010[GF * (i+1) - 1 : GF * i] ),
.i_v_011 (i_v_011[GF * (i+1) - 1 : GF * i] ),
.i_v_012 (i_v_012[GF * (i+1) - 1 : GF * i] ),
.i_v_013 (i_v_013[GF * (i+1) - 1 : GF * i] ),
.i_v_014 (i_v_014[GF * (i+1) - 1 : GF * i] ),
.o_cs_start ( ),
.o_cs_cmplt (o_cs_cmplt[i] ),
.o_cs_pause ( ),
.o_BRAM_read_enable (o_BRAM_read_enable[i] ),
.o_BRAM_read_address (o_BRAM_read_address[(i+1)*8 - 1:i*8] ),
.i_BRAM_read_data (i_BRAM_read_data[(i+1)*8 - 1:i*8] ),
.o_c_message_valid (o_c_message_valid[i] ),
.o_c_message_output_start ( ),
.o_c_message_output_cmplt (o_c_message_output_cmplt[i] ),
.o_c_message (o_c_message[(i+1)*8 - 1:i*8] )
);
end
endgenerate
assign o_cs_available = w_cs_available[0] ;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2016 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
sub #(.IDX(0), .CHK(10)) i0;
sub #(.IDX(2), .CHK(12)) i2;
sub #(.IDX(7), .CHK(17)) i7;
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub ();
function integer get_element;
input integer index;
input integer array_arg[7:0];
get_element = array_arg[index];
endfunction
parameter integer IDX = 5;
parameter integer CHK = 5;
localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17};
localparam element1 = array[IDX];
localparam elementf = get_element(IDX, array);
initial begin
`checkh (element1, CHK);
`checkh (elementf, CHK);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/14/2016 06:25:09 AM
// Design Name:
// Module Name: Exp_operation_m
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation_m
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//underflow
input wire load_b_i,//overflow
input wire load_c_i,//result
input wire [EW:0] Data_A_i,
input wire [EW:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
///////////////////////////////////////////////
wire [EW:0] Data_S;
wire Overflow_A;
wire Overflow_flag_A;
wire underflow_exp_reg;
wire [EW:0] U_Limit;
/////////////////////////////Exponent calculation///
add_sub_carry_out #(.W(EW+1)) exp_add_subt_m(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S ({Overflow_A,Data_S})
);
RegisterMult #(.W(EW+1)) exp_result_m(
.clk (clk),
.rst (rst),
.load (load_c_i),
.D (Data_S),
.Q (Data_Result_o)
);
//Overflow/////////////////////////////////
RegisterMult#(.W(1)) Oflow_A_m (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Overflow_A),
.Q(Overflow_flag_A)
);
assign Overflow_flag_o = Overflow_flag_A | Data_Result_o[EW];
//Underflow//////////////////////////////
Comparator_Less #(.W(EW+1)) Exp_unflow_Comparator_m (
.Data_A(Data_S),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) Underflow_m (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(underflow_exp_reg),
.Q(Underflow_flag_o)
);
generate
if (EW == 8)
assign U_Limit = 9'd127;
else
assign U_Limit = 12'd1023;
endgenerate
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_switch
*/
module test_axis_switch_4x4_64;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT+1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_switch_4x4_64.lxt");
$dumpvars(0, test_axis_switch_4x4_64);
end
axis_switch #(
.M_COUNT(M_COUNT),
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// or1200_fpu_post_norm_addsub ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// post-normalization entity for the addition/subtraction unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, [email protected] ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module or1200_fpu_post_norm_addsub
(
clk_i,
opa_i,
opb_i,
fract_28_i,
exp_i,
sign_i,
fpu_op_i,
rmode_i,
output_o,
ine_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk_i;
input [FP_WIDTH-1:0] opa_i;
input [FP_WIDTH-1:0] opb_i;
input [FRAC_WIDTH+4:0] fract_28_i;
input [EXP_WIDTH-1:0] exp_i;
input sign_i;
input fpu_op_i;
input [1:0] rmode_i;
output reg [FP_WIDTH-1:0] output_o;
output reg ine_o;
wire [FP_WIDTH-1:0] s_opa_i;
wire [FP_WIDTH-1:0] s_opb_i;
wire [FRAC_WIDTH+4:0] s_fract_28_i;
wire [EXP_WIDTH-1:0] s_exp_i;
wire s_sign_i;
wire s_fpu_op_i;
wire [1:0] s_rmode_i;
wire [FP_WIDTH-1:0] s_output_o;
wire s_ine_o;
wire s_overflow;
wire [5:0] s_zeros;
reg [5:0] s_shr1;
reg [5:0] s_shl1;
wire s_shr2, s_carry;
wire [9:0] s_exp10;
reg [EXP_WIDTH:0] s_expo9_1;
wire [EXP_WIDTH:0] s_expo9_2;
wire [EXP_WIDTH:0] s_expo9_3;
reg [FRAC_WIDTH+4:0] s_fracto28_1;
wire [FRAC_WIDTH+4:0] s_fracto28_2;
wire [FRAC_WIDTH+4:0] s_fracto28_rnd;
wire s_roundup;
wire s_sticky;
wire s_zero_fract;
wire s_lost;
wire s_infa, s_infb;
wire s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign;
assign s_opa_i = opa_i;
assign s_opb_i = opb_i;
assign s_fract_28_i = fract_28_i;
assign s_exp_i = exp_i;
assign s_sign_i = sign_i;
assign s_fpu_op_i = fpu_op_i;
assign s_rmode_i = rmode_i;
// Output Register
always @(posedge clk_i)
begin
output_o <= s_output_o;
ine_o <= s_ine_o;
end
//*** Stage 1 ****
// figure out the output exponent and how much the fraction has to be
// shiftd right/left
assign s_carry = s_fract_28_i[27];
reg [5:0] lzeroes;
always @(s_fract_28_i)
casez(s_fract_28_i[26:0]) // synopsys full_case parallel_case
27'b1??????????????????????????: lzeroes = 0;
27'b01?????????????????????????: lzeroes = 1;
27'b001????????????????????????: lzeroes = 2;
27'b0001???????????????????????: lzeroes = 3;
27'b00001??????????????????????: lzeroes = 4;
27'b000001?????????????????????: lzeroes = 5;
27'b0000001????????????????????: lzeroes = 6;
27'b00000001???????????????????: lzeroes = 7;
27'b000000001??????????????????: lzeroes = 8;
27'b0000000001?????????????????: lzeroes = 9;
27'b00000000001????????????????: lzeroes = 10;
27'b000000000001???????????????: lzeroes = 11;
27'b0000000000001??????????????: lzeroes = 12;
27'b00000000000001?????????????: lzeroes = 13;
27'b000000000000001????????????: lzeroes = 14;
27'b0000000000000001???????????: lzeroes = 15;
27'b00000000000000001??????????: lzeroes = 16;
27'b000000000000000001?????????: lzeroes = 17;
27'b0000000000000000001????????: lzeroes = 18;
27'b00000000000000000001???????: lzeroes = 19;
27'b000000000000000000001??????: lzeroes = 20;
27'b0000000000000000000001?????: lzeroes = 21;
27'b00000000000000000000001????: lzeroes = 22;
27'b000000000000000000000001???: lzeroes = 23;
27'b0000000000000000000000001??: lzeroes = 24;
27'b00000000000000000000000001?: lzeroes = 25;
27'b000000000000000000000000001: lzeroes = 26;
27'b000000000000000000000000000: lzeroes = 27;
endcase
assign s_zeros = s_fract_28_i[27] ? 0 : lzeroes;
// negative flag & large flag & exp
assign s_exp10 = {2'd0,s_exp_i} + {9'd0,s_carry} - {4'd0,s_zeros};
always @(posedge clk_i)
begin
if (s_exp10[9] | !(|s_exp10))
begin
s_shr1 <= 0;
s_expo9_1 <= 9'd1;
if (|s_exp_i)
s_shl1 <= s_exp_i[5:0] - 6'd1;
else
s_shl1 <= 0;
end
else if (s_exp10[8])
begin
s_shr1 <= 0;
s_shl1 <= 0;
s_expo9_1 <= 9'b011111111;
end
else
begin
s_shr1 <= {5'd0,s_carry};
s_shl1 <= s_zeros;
s_expo9_1 <= s_exp10[8:0];
end // else: !if(s_exp10[8])
end // always @ (posedge clk_i)
//-
// *** Stage 2 ***
// Shifting the fraction and rounding
always @(posedge clk_i)
if (|s_shr1)
s_fracto28_1 <= s_fract_28_i >> s_shr1;
else
s_fracto28_1 <= s_fract_28_i << s_shl1;
assign s_expo9_2 = (s_fracto28_1[27:26]==2'b00) ?
s_expo9_1 - 9'd1 : s_expo9_1;
// round
//check last bit, before and after right-shift
assign s_sticky = s_fracto28_1[0] | (s_fract_28_i[0] & s_fract_28_i[27]);
assign s_roundup = s_rmode_i==2'b00 ?
// round to nearset even
s_fracto28_1[2] & ((s_fracto28_1[1] | s_sticky) |
s_fracto28_1[3]) :
s_rmode_i==2'b10 ?
// round up
(s_fracto28_1[2] | s_fracto28_1[1] | s_sticky) & !s_sign_i:
s_rmode_i==2'b11 ?
// round down
(s_fracto28_1[2] | s_fracto28_1[1] | s_sticky) & s_sign_i :
// round to zero(truncate = no rounding)
0;
assign s_fracto28_rnd = s_roundup ?
s_fracto28_1+28'b0000_0000_0000_0000_0000_0000_1000 :
s_fracto28_1;
// ***Stage 3***
// right-shift after rounding (if necessary)
assign s_shr2 = s_fracto28_rnd[27];
assign s_expo9_3 = (s_shr2 & s_expo9_2!=9'b011111111) ?
s_expo9_2 + 9'b000000001 : s_expo9_2;
assign s_fracto28_2 = s_shr2 ? {1'b0,s_fracto28_rnd[27:1]} : s_fracto28_rnd;
////-
assign s_infa = &s_opa_i[30:23];
assign s_infb = &s_opb_i[30:23];
assign s_nan_a = s_infa & (|s_opa_i[22:0]);
assign s_nan_b = s_infb & (|s_opb_i[22:0]);
assign s_nan_in = s_nan_a | s_nan_b;
// inf-inf=Nan
assign s_nan_op = (s_infa & s_infb) &
(s_opa_i[31] ^ (s_fpu_op_i ^ s_opb_i[31]));
assign s_nan_sign = (s_nan_a & s_nan_b) ? s_sign_i :
s_nan_a ?
s_opa_i[31] : s_opb_i[31];
// check if result is inexact;
assign s_lost = (s_shr1[0] & s_fract_28_i[0]) |
(s_shr2 & s_fracto28_rnd[0]) | (|s_fracto28_2[2:0]);
assign s_ine_o = (s_lost | s_overflow) & !(s_infa | s_infb);
assign s_overflow = s_expo9_3==9'b011111111 & !(s_infa | s_infb);
// '1' if fraction result is zero
assign s_zero_fract = s_zeros==27 & !s_fract_28_i[27];
// Generate result
assign s_output_o = (s_nan_in | s_nan_op) ?
{s_nan_sign,QNAN} :
(s_infa | s_infb) | s_overflow ?
{s_sign_i,INF} :
s_zero_fract ?
{s_sign_i,ZERO_VECTOR} :
{s_sign_i,s_expo9_3[7:0],s_fracto28_2[25:3]};
endmodule // or1200_fpu_post_norm_addsub
|
`timescale 1 ns / 1 ps
module esaxi_v1_0 #
(
// Users to add parameters here
parameter [11:0] C_READ_TAG_ADDR = 12'h810,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_ID_WIDTH = 1,
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 30,
parameter integer C_S00_AXI_AWUSER_WIDTH = 0,
parameter integer C_S00_AXI_ARUSER_WIDTH = 0,
parameter integer C_S00_AXI_WUSER_WIDTH = 0,
parameter integer C_S00_AXI_RUSER_WIDTH = 0,
parameter integer C_S00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO write port, write requests
output wire [102:0] emwr_wr_data,
output wire emwr_wr_en,
input wire emwr_full,
input wire emwr_prog_full,
// FIFO write port, read requests
output wire [102:0] emrq_wr_data,
output wire emrq_wr_en,
input wire emrq_full,
input wire emrq_prog_full,
// FIFO read port, read responses
input wire [102:0] emrr_rd_data,
output wire emrr_rd_en,
input wire emrr_empty,
// Control bits from eConfig
input wire [3:0] ecfg_tx_ctrl_mode,
input wire [11:0] ecfg_coreid,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_awid,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [7 : 0] s00_axi_awlen,
input wire [2 : 0] s00_axi_awsize,
input wire [1 : 0] s00_axi_awburst,
input wire s00_axi_awlock,
input wire [3 : 0] s00_axi_awcache,
input wire [2 : 0] s00_axi_awprot,
input wire [3 : 0] s00_axi_awqos,
input wire [3 : 0] s00_axi_awregion,
input wire [C_S00_AXI_AWUSER_WIDTH-1 : 0] s00_axi_awuser,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wlast,
input wire [C_S00_AXI_WUSER_WIDTH-1 : 0] s00_axi_wuser,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_bid,
output wire [1 : 0] s00_axi_bresp,
output wire [C_S00_AXI_BUSER_WIDTH-1 : 0] s00_axi_buser,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_arid,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [7 : 0] s00_axi_arlen,
input wire [2 : 0] s00_axi_arsize,
input wire [1 : 0] s00_axi_arburst,
input wire s00_axi_arlock,
input wire [3 : 0] s00_axi_arcache,
input wire [2 : 0] s00_axi_arprot,
input wire [3 : 0] s00_axi_arqos,
input wire [3 : 0] s00_axi_arregion,
input wire [C_S00_AXI_ARUSER_WIDTH-1 : 0] s00_axi_aruser,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_rid,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rlast,
output wire [C_S00_AXI_RUSER_WIDTH-1 : 0] s00_axi_ruser,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
esaxi_v1_0_S00_AXI # (
.C_READ_TAG_ADDR(C_READ_TAG_ADDR),
.C_S_AXI_ID_WIDTH(C_S00_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.C_S_AXI_AWUSER_WIDTH(C_S00_AXI_AWUSER_WIDTH),
.C_S_AXI_ARUSER_WIDTH(C_S00_AXI_ARUSER_WIDTH),
.C_S_AXI_WUSER_WIDTH(C_S00_AXI_WUSER_WIDTH),
.C_S_AXI_RUSER_WIDTH(C_S00_AXI_RUSER_WIDTH),
.C_S_AXI_BUSER_WIDTH(C_S00_AXI_BUSER_WIDTH)
) esaxi_v1_0_S00_AXI_inst (
.emwr_wr_data (emwr_wr_data),
.emwr_wr_en (emwr_wr_en),
.emwr_full (emwr_full),
.emwr_prog_full (emwr_prog_full),
.emrq_wr_data (emrq_wr_data),
.emrq_wr_en (emrq_wr_en),
.emrq_full (emrq_full),
.emrq_prog_full (emrq_prog_full),
.emrr_rd_data (emrr_rd_data),
.emrr_rd_en (emrr_rd_en),
.emrr_empty (emrr_empty),
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode),
.ecfg_coreid (ecfg_coreid),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWID(s00_axi_awid),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWLEN(s00_axi_awlen),
.S_AXI_AWSIZE(s00_axi_awsize),
.S_AXI_AWBURST(s00_axi_awburst),
.S_AXI_AWLOCK(s00_axi_awlock),
.S_AXI_AWCACHE(s00_axi_awcache),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWQOS(s00_axi_awqos),
.S_AXI_AWREGION(s00_axi_awregion),
.S_AXI_AWUSER(s00_axi_awuser),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WLAST(s00_axi_wlast),
.S_AXI_WUSER(s00_axi_wuser),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BID(s00_axi_bid),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BUSER(s00_axi_buser),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARID(s00_axi_arid),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARLEN(s00_axi_arlen),
.S_AXI_ARSIZE(s00_axi_arsize),
.S_AXI_ARBURST(s00_axi_arburst),
.S_AXI_ARLOCK(s00_axi_arlock),
.S_AXI_ARCACHE(s00_axi_arcache),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARQOS(s00_axi_arqos),
.S_AXI_ARREGION(s00_axi_arregion),
.S_AXI_ARUSER(s00_axi_aruser),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RID(s00_axi_rid),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RLAST(s00_axi_rlast),
.S_AXI_RUSER(s00_axi_ruser),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
module ICAP_core
(
input fastclk,
input [4:0] design_num,
input reconfigure,
input powerup,
input [3:0] sw_in,
output [3:0] sw_out,
output [3:0] pwr_out,
output initialized,
output [7:0] test
);
reg [1:0] clk;
reg reconfigure_sync;
reg [15:0] icap_din;
reg icap_ce;
reg icap_wr;
wire [15:0] icap_dout_reversed;
reg [15:0] icap_dout;
reg [15:0] ff_icap_din_reversed;
reg ff_icap_ce;
reg ff_icap_wr;
reg [3:0] MBT_REBOOT = 4'b0000;
reg [7:0] soft_dip = 8'b00000000;
reg test_trig;
assign test = { 8'b0 };
assign sw_out = powerup ? sw_in : soft_dip[3:0];
assign pwr_out = powerup ? sw_in : soft_dip[7:4];
assign initialized = state == IDLE;
wire busy;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst
(
.BUSY (busy), // Busy output
.O (icap_dout_reversed), // 16-bit data output
.CE (ff_icap_ce), // Clock enable input
.CLK (clk[0]), // Clock input
.I (ff_icap_din_reversed), // 16-bit data input
.WRITE (ff_icap_wr) // Write input
);
// -------------------------------------------------
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
// -- sequence. --
// -------------------------------------------------
parameter
INIT = 0,
RD_DUMMY = 1,
RD_SYNC_H = 2,
RD_SYNC_L = 3,
RD_NOOP_1 = 4,
RD_NOOP_2 = 5,
RD_GEN5 = 6,
RD_NOOP_3 = 7,
RD_NOOP_4 = 8,
RD_NOOP_5 = 9,
RD_NOOP_6 = 10,
RD_AVOID_ABORT_1 = 11,
RD_AVOID_ABORT_2 = 12,
RD_LATCH_DATA = 13,
RD_AVOID_ABORT_3 = 14,
RD_AVOID_ABORT_4 = 15,
RD_DESYNC_H = 16,
RD_DESYNC_L = 17,
RD_NOOP_7 = 18,
IDLE = 19,
DUMMY_1 = 20,
DUMMY_2 = 21,
SYNC_H = 22,
SYNC_L = 23,
GEN1_H = 24,
GEN1_L = 25,
GEN2_H = 26,
GEN2_L = 27,
GEN5_H = 28,
GEN5_L = 29,
RBT_H = 30,
RBT_L = 31,
RBT_NOOP_0 = 32,
RBT_NOOP_1 = 33,
RBT_NOOP_2 = 34,
RBT_NOOP_3 = 35;
reg [5:0] state = INIT;
reg [5:0] next_state;
always @(MBT_REBOOT or state or design_num or reconfigure_sync or powerup or sw_in or busy or soft_dip)
begin: COMB
case (state)
//--------------------
INIT:
begin
next_state = RD_DUMMY;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hFFFF; // Null data
end
RD_DUMMY:
begin
next_state = RD_SYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hAA99; // Sync word part 1
end
RD_SYNC_H:
begin
next_state = RD_SYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h5566; // Sync word part 2
end
RD_SYNC_L:
begin
next_state = RD_NOOP_1;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_1:
begin
next_state = RD_NOOP_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_2:
begin
next_state = RD_GEN5;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2ae1; // Read General_5 register
end
RD_GEN5:
begin
next_state = RD_NOOP_3;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_3:
begin
next_state = RD_NOOP_4;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_4:
begin
next_state = RD_NOOP_5;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_5:
begin
next_state = RD_NOOP_6;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_6:
begin
next_state = RD_AVOID_ABORT_1;
icap_ce = 1;
icap_wr = 0;
icap_din = 16'hffff; // Dummy Data
end
RD_AVOID_ABORT_1:
begin
next_state = RD_AVOID_ABORT_2;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'hffff; // Dummy Data
end
RD_AVOID_ABORT_2:
begin
next_state = RD_LATCH_DATA;
icap_ce = 0;
icap_wr = 1;
icap_din = 16'hffff; // Dummy Data
end
RD_LATCH_DATA:
begin
if (busy) begin
next_state = RD_LATCH_DATA;
icap_ce = 0;
icap_wr = 1;
icap_din = 16'hffff; // Dummy Data
end else begin
next_state = RD_AVOID_ABORT_3;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'hffff; // Dummy Data
end
end
RD_AVOID_ABORT_3:
begin
next_state = RD_AVOID_ABORT_4;
icap_ce = 1;
icap_wr = 0;
icap_din = 16'hffff; // Dummy Data
end
RD_AVOID_ABORT_4:
begin
next_state = RD_DESYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30a1; // Write to CMD Register
end
RD_DESYNC_H:
begin
next_state = RD_DESYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h000d; // DESYNC command
end
RD_DESYNC_L:
begin
next_state = RD_NOOP_7;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
RD_NOOP_7:
begin
next_state = IDLE;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
IDLE:
begin
if (reconfigure_sync) begin
next_state = DUMMY_1;
end else begin
next_state = IDLE;
end
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hFFFF; // Null data
end
DUMMY_1:
begin
next_state = DUMMY_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hFFFF; // Null data
end
DUMMY_2:
begin
next_state = SYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hAA99; // Sync word part 1
end
SYNC_H:
begin
next_state = SYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h5566; // Sync word part 2
end
SYNC_L:
begin
next_state = GEN1_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3261; // Write to GENERAL_1 Register....
end
GEN1_H:
begin
next_state = GEN1_L;
icap_ce = 0;
icap_wr = 0;
case (design_num)
5'b10000: icap_din = 16'h0000;
5'b00000: icap_din = 16'h4000;
5'b00001: icap_din = 16'h4000;
5'b00010: icap_din = 16'h4000;
5'b00011: icap_din = 16'h4000;
5'b00100: icap_din = 16'h8000;
5'b00101: icap_din = 16'hC000;
5'b00110: icap_din = 16'hC000;
5'b00111: icap_din = 16'hC000;
5'b01000: icap_din = 16'h0000;
5'b01001: icap_din = 16'h4000;
5'b01010: icap_din = 16'h8000;
5'b01011: icap_din = 16'hC000;
5'b01100: icap_din = 16'h0000;
5'b01101: icap_din = 16'h4000;
5'b01110: icap_din = 16'h8000; // The Null Co Processor
5'b01111: icap_din = 16'hC000;
default: icap_din = 16'h8000; // The Null Co Processor
endcase
end
GEN1_L:
begin
next_state = GEN2_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3281; // Write to GENERAL_2 Register....
end
GEN2_H:
begin
next_state = GEN2_L;
icap_ce = 0;
icap_wr = 0;
case (design_num)
5'b10000: icap_din = 16'h0300;
5'b00000: icap_din = 16'h0305;
5'b00001: icap_din = 16'h0305;
5'b00010: icap_din = 16'h0305;
5'b00011: icap_din = 16'h0305;
5'b00100: icap_din = 16'h030a;
5'b00101: icap_din = 16'h030f;
5'b00110: icap_din = 16'h030f;
5'b00111: icap_din = 16'h030f;
5'b01000: icap_din = 16'h0315;
5'b01001: icap_din = 16'h031a;
5'b01010: icap_din = 16'h031f;
5'b01011: icap_din = 16'h0324;
5'b01100: icap_din = 16'h032a;
5'b01101: icap_din = 16'h032f;
5'b01110: icap_din = 16'h0334; // The Null/SPI Co Processor
5'b01111: icap_din = 16'h0339;
default: icap_din = 16'h0334; // The Null/SPI Co Processor
endcase
end
//--------------------
GEN2_L:
begin
next_state = GEN5_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h32e1; // Write to GENERAL_5 Register....
end
GEN5_H:
begin
next_state = GEN5_L;
icap_ce = 0;
icap_wr = 0;
icap_din[15:8] = 8'b0;
icap_din[7:4] = powerup ? sw_in : soft_dip[7:4];
icap_din[3:0] = powerup ? sw_in : design_num[3:0];
end
//--------------------
GEN5_L:
begin
next_state = RBT_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
RBT_H:
begin
next_state = RBT_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h000E; // REBOOT Command issued.... value = 0x000E
end
//--------------------
RBT_L:
begin
next_state = RBT_NOOP_0;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // RBT_NOOP
end
RBT_NOOP_0:
begin
next_state = RBT_NOOP_1;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // RBT_NOOP
end
RBT_NOOP_1:
begin
next_state = RBT_NOOP_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // RBT_NOOP
end
RBT_NOOP_2:
begin
next_state = RBT_NOOP_3;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // RBT_NOOP
end
//--------------------
RBT_NOOP_3:
begin
next_state = IDLE;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hffff; // NULL value
end
default:
begin
next_state = IDLE;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hffff; // 16'h1111"
end
endcase
end
// Clock ICAP_SPARTAN6 and the state machine with clocks that are 90deg phase apart.
//
// This is an attempt to cure some reconfiguration unreliability.
//
// The problem is that ICAP_SPARTAN2 isn't treated by the Xilinx tools as a synchronous
// component, so when clocked off the same clock there can be timing issues.
//
// The below clocking patten runs the clock at 8MHz (half what it was before).
//
// It ensures there is plenty of setup and hold time margin for signals passing
// between ICAP_SPARTAN6 and the state machine, regardless of which clk edge is used
// ICAP_SPARTAN6.
//
// See this link for some related discussion:
// https://forums.xilinx.com/t5/Spartan-Family-FPGAs/20Mhz-limitation-for-ICAP-SPARTAN6/td-p/238060
//
// NOTE: I'm hedging here, as this bug is quite difficult to reproduce, and changing almost anything
// (e.g. connecting state to the test pins) causes the problem to go away.
//
// At worst this change should be harmless!
//
// Dave Banks - 18/07/2017
always@(posedge fastclk) begin
if (clk == 2'b00)
clk <= 2'b10;
else if (clk == 2'b10)
clk <= 2'b11;
else if (clk == 2'b11)
clk <= 2'b01;
else
clk <= 2'b00;
end
// Give a bit of delay before starting the state machine
always @(posedge clk[1]) begin
reconfigure_sync <= reconfigure;
if (MBT_REBOOT == 4'b1111) begin
state <= next_state;
end else begin
MBT_REBOOT <= MBT_REBOOT + 4'b0001;
state <= INIT;
end
if (state == RD_LATCH_DATA) begin
test_trig <= 1'b1;
end else begin
test_trig <= 1'b0;
end
if (state == RD_LATCH_DATA && !busy) begin
soft_dip <= icap_dout[7:0];
end
end
always @(posedge clk[1]) begin: ICAP_FF
// need to reverse bits to ICAP module since D0 bit is read first
ff_icap_din_reversed[0] <= icap_din[7];
ff_icap_din_reversed[1] <= icap_din[6];
ff_icap_din_reversed[2] <= icap_din[5];
ff_icap_din_reversed[3] <= icap_din[4];
ff_icap_din_reversed[4] <= icap_din[3];
ff_icap_din_reversed[5] <= icap_din[2];
ff_icap_din_reversed[6] <= icap_din[1];
ff_icap_din_reversed[7] <= icap_din[0];
ff_icap_din_reversed[8] <= icap_din[15];
ff_icap_din_reversed[9] <= icap_din[14];
ff_icap_din_reversed[10] <= icap_din[13];
ff_icap_din_reversed[11] <= icap_din[12];
ff_icap_din_reversed[12] <= icap_din[11];
ff_icap_din_reversed[13] <= icap_din[10];
ff_icap_din_reversed[14] <= icap_din[9];
ff_icap_din_reversed[15] <= icap_din[8];
ff_icap_ce <= icap_ce;
ff_icap_wr <= icap_wr;
end
always @(icap_dout_reversed) begin
// need to reverse bits to ICAP module since D0 bit is read first
icap_dout[0] <= icap_dout_reversed[7];
icap_dout[1] <= icap_dout_reversed[6];
icap_dout[2] <= icap_dout_reversed[5];
icap_dout[3] <= icap_dout_reversed[4];
icap_dout[4] <= icap_dout_reversed[3];
icap_dout[5] <= icap_dout_reversed[2];
icap_dout[6] <= icap_dout_reversed[1];
icap_dout[7] <= icap_dout_reversed[0];
icap_dout[8] <= icap_dout_reversed[15];
icap_dout[9] <= icap_dout_reversed[14];
icap_dout[10] <= icap_dout_reversed[13];
icap_dout[11] <= icap_dout_reversed[12];
icap_dout[12] <= icap_dout_reversed[11];
icap_dout[13] <= icap_dout_reversed[10];
icap_dout[14] <= icap_dout_reversed[9];
icap_dout[15] <= icap_dout_reversed[8];
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The tx_engine module takes a formatted header, number of alignment
// blanks and a payloa and concatenates all three (in that order) to form a
// packet. These packets must meet max-request, max-payload, and payload
// termination requirements (see Read Completion Boundary). The tx_engine does
// not check these requirements during operation, but may do so during simulation.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_engine
#(parameter C_DATA_WIDTH = 128,
parameter C_DEPTH_PACKETS = 10,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_FORMATTER_DELAY = 1,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// Interface: TX_DATA
input TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
input TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
output TX_DATA_READY,
// Interface: TX_PKT
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID
);
localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
localparam C_ACTUAL_HDR_FIFO_DEPTH = clog2s(C_DEPTH_PACKETS);
localparam C_USE_COMPUTE_REG = 1;
localparam C_USE_READY_REG = 1;
localparam C_USE_FWFT_HDR_FIFO = 1;
localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT; // Aligner
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNoPayload;
wire wTxDataReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
tx_data_pipeline
#(
.C_MAX_PAYLOAD (C_MAX_PAYLOAD_DWORDS*32),
.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
tx_data_pipeline_inst
(
// Outputs
.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_READY (TX_DATA_READY),
// Inputs
.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA (TX_DATA),
.WR_TX_DATA_VALID (TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_hdr_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_ACTUAL_HDR_FIFO_DEPTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
txhf_inst
(
// Outputs
.WR_TX_HDR_READY (TX_HDR_READY),
.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.RD_TX_HDR_VALID (wTxHdrValid),
.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
.WR_TX_HDR_VALID (TX_HDR_VALID),
.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
.RD_TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_alignment_pipeline
#(
// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_DATA_INPUT (1),
.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
// Parameters
/*AUTOINSTPARAM*/
// Parameters
.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
.C_USE_READY_REG (C_USE_READY_REG),
.C_VENDOR (C_VENDOR))
tx_alignment_inst
(
// Outputs
.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.TX_HDR_READY (wTxHdrReady),
.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
.TX_PKT_VALID (TX_PKT_VALID),
.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
// Inputs
.TX_DATA_START_FLAG (wTxDataStartFlag),
.TX_DATA_END_FLAGS (wTxDataEndFlags),
.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_PKT_READY (TX_PKT_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_read # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
input m_axi_aclk,
input m_axi_aresetn,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_rresp_err,
output dev_tx_cmd_rd_en,
input [29:0] dev_tx_cmd_rd_data,
input dev_tx_cmd_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n
);
localparam LP_AR_DELAY = 7;
localparam S_IDLE = 8'b00000001;
localparam S_CMD_0 = 8'b00000010;
localparam S_CMD_1 = 8'b00000100;
localparam S_WAIT_FULL_N = 8'b00001000;
localparam S_AR_REQ = 8'b00010000;
localparam S_AR_WAIT = 8'b00100000;
localparam S_AR_DONE = 8'b01000000;
localparam S_AR_DELAY = 8'b10000000;
reg [7:0] cur_state;
reg [7:0] next_state;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_m_axi_arlen;
reg [4:0] r_ar_delay;
reg r_dev_tx_cmd_rd_en;
reg r_pcie_tx_fifo_alloc_en;
wire w_axi_ar_req_gnt;
reg [2:0] r_axi_ar_req_gnt;
reg r_axi_ar_req;
reg r_m_axi_arvalid;
reg [C_M_AXI_DATA_WIDTH-1 : 0] r_m_axi_rdata;
reg r_m_axi_rlast;
//reg r_m_axi_rlast_d1;
//wire w_m_axi_rlast;
reg r_m_axi_rvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_rid;
reg [1:0] r_m_axi_rresp;
reg r_m_axi_rresp_err;
reg r_m_axi_rresp_err_d1;
reg r_m_axi_rresp_err_d2;
assign m_axi_arid = 0;
assign m_axi_araddr = {r_dev_addr, 2'b0};
assign m_axi_arlen = {1'b0, r_m_axi_arlen[9:3]};
assign m_axi_arsize = `D_AXSIZE_008_BYTES;
assign m_axi_arburst = `D_AXBURST_INCR;
assign m_axi_arlock = `D_AXLOCK_NORMAL;
assign m_axi_arcache = `D_AXCACHE_NON_CACHE;
assign m_axi_arprot = `D_AXPROT_SECURE;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
assign m_axi_arvalid = r_m_axi_arvalid;
assign m_axi_rready = 1;
assign m_axi_rresp_err = r_m_axi_rresp_err_d2;
assign dev_tx_cmd_rd_en = r_dev_tx_cmd_rd_en;
assign pcie_tx_fifo_alloc_en = r_pcie_tx_fifo_alloc_en;
assign pcie_tx_fifo_alloc_len = r_dev_cur_len[9:4];
assign pcie_tx_fifo_wr_en = r_m_axi_rvalid;
assign pcie_tx_fifo_wr_data = r_m_axi_rdata;
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dev_tx_cmd_empty_n == 1)
next_state <= S_CMD_0;
else
next_state <= S_IDLE;
end
S_CMD_0: begin
next_state <= S_CMD_1;
end
S_CMD_1: begin
next_state <= S_WAIT_FULL_N;
end
S_WAIT_FULL_N: begin
if(pcie_tx_fifo_full_n == 1 && w_axi_ar_req_gnt == 1)
next_state <= S_AR_REQ;
else
next_state <= S_WAIT_FULL_N;
end
S_AR_REQ: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_WAIT: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_DONE: begin
if(r_dev_dma_len == 0)
next_state <= S_IDLE;
else
next_state <= S_AR_DELAY;
end
S_AR_DELAY: begin
if(r_ar_delay == 0)
next_state <= S_WAIT_FULL_N;
else
next_state <= S_AR_DELAY;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_0: begin
r_dev_dma_len <= {dev_tx_cmd_rd_data[10:2], 2'b0};
end
S_CMD_1: begin
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_tx_cmd_rd_data[29:2], 2'b0};
end
S_WAIT_FULL_N: begin
r_m_axi_arlen <= r_dev_cur_len - 2;
end
S_AR_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AR_WAIT: begin
end
S_AR_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_ar_delay <= LP_AR_DELAY;
end
S_AR_DELAY: begin
r_ar_delay <= r_ar_delay - 1;
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_0: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_1: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_WAIT_FULL_N: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_REQ: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 1;
r_axi_ar_req <= 1;
end
S_AR_WAIT: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DONE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DELAY: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
default: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
endcase
end
//assign w_m_axi_rlast = r_m_axi_rlast & ~r_m_axi_rlast_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_rid <= m_axi_rid;
r_m_axi_rdata <= m_axi_rdata;
r_m_axi_rlast <= m_axi_rlast & m_axi_rvalid;
//r_m_axi_rlast_d1 <= r_m_axi_rlast;
r_m_axi_rvalid <= m_axi_rvalid;
r_m_axi_rresp <= m_axi_rresp;
r_m_axi_rresp_err_d1 <= r_m_axi_rresp_err;
r_m_axi_rresp_err_d2 <= r_m_axi_rresp_err | r_m_axi_rresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_rvalid == 1 && (r_m_axi_rresp != `D_AXI_RESP_OKAY || r_m_axi_rid != 0))
r_m_axi_rresp_err <= 1;
else
r_m_axi_rresp_err <= 0;
end
assign w_axi_ar_req_gnt = r_axi_ar_req_gnt[2];
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_ar_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_rlast, r_axi_ar_req})
2'b01: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[1:0], r_axi_ar_req_gnt[2]};
end
2'b10: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[0], r_axi_ar_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
endmodule |
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = ~(a | b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
nor104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
module top;
parameter seeq1 = 6'sb111000 === 4'sb1000;
parameter seeqx = 6'sbxxx000 === 4'sbx000;
parameter seeqz = 6'sbzzz000 === 4'sbz000;
parameter seq1 = 6'sb111000 == 4'sb1000;
parameter seqx = 6'sbxxx000 == 4'sbx000;
parameter seqz = 6'sbzzz000 == 4'sbz000;
reg pass;
initial begin
pass = 1'b1;
if (seeq1 !== 1'b1) begin
$display("FAILED: signed === (1), got %b", seeq1);
pass = 1'b0;
end
if (seeqx !== 1'b1) begin
$display("FAILED: signed === (x), got %b", seeqx);
pass = 1'b0;
end
if (seeqz !== 1'b1) begin
$display("FAILED: signed === (z), got %b", seeqz);
pass = 1'b0;
end
if (seq1 !== 1'b1) begin
$display("FAILED: signed == (1), got %b", seq1);
pass = 1'b0;
end
if (seqx !== 1'bx) begin
$display("FAILED: signed == (x), got %b", seqx);
pass = 1'b0;
end
if (seqz !== 1'bx) begin
$display("FAILED: signed == (z), got %b", seqz);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
module resetter(
clk,
rst_in1_n,
rst_in2_n,
rst_out_n );
parameter RST_CNT_SIZE = 3;
input clk;
input rst_in1_n; // input of external asynchronous reset 1
input rst_in2_n; // input of external asynchronous reset 2
output reg rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
reg rst1_n,rst2_n;
wire resets_n;
assign resets_n = rst_in1_n & rst_in2_n;
always @(posedge clk, negedge resets_n)
if( !resets_n ) // external asynchronous reset
begin
rst_cnt <= 0;
rst1_n <= 1'b0;
rst2_n <= 1'b0; // sync in reset end
rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
end
else // clocking
begin
rst1_n <= 1'b1;
rst2_n <= rst1_n;
if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
begin
rst_cnt <= rst_cnt + 1;
end
rst_out_n <= rst_cnt[RST_CNT_SIZE];
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: audio_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module audio_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports.
//
//===----------------------------------------------------------------------===//
module acl_mlab_fifo (
clock,
resetn,
data_in,
data_out,
valid_in,
valid_out,
stall_in,
stall_out,
usedw,
empty,
full,
almost_full);
function integer my_local_log;
input [31:0] value;
for (my_local_log=0; value>0; my_local_log=my_local_log+1)
value = value>>1;
endfunction
parameter DATA_WIDTH = 32;
parameter DEPTH = 256;
parameter NUM_BITS_USED_WORDS = DEPTH == 1 ? 1 : my_local_log(DEPTH-1);
parameter ALMOST_FULL_VALUE = 0;
input clock, stall_in, valid_in, resetn;
output stall_out, valid_out;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output [NUM_BITS_USED_WORDS-1:0] usedw;
output empty, full, almost_full;
// add a register stage prior to the acl_fifo.
//reg [DATA_WIDTH-1:0] data_input /* synthesis preserve */;
//reg valid_input /* synthesis preserve */;
//always@(posedge clock or negedge resetn)
//begin
// if (~resetn)
// begin
// data_input <= {DATA_WIDTH{1'bx}};
// valid_input <= 1'b0;
// end
// else if (~valid_input | ~full)
// begin
// valid_input <= valid_in;
// data_input <= data_in;
// end
//end
scfifo scfifo_component (
.clock (clock),
.data (data_in),
.rdreq ((~stall_in) & (~empty)),
.sclr (),
.wrreq (valid_in & (~full)),
.empty (empty),
.full (full),
.q (data_out),
.aclr (~resetn),
.almost_empty (),
.almost_full (almost_full),
.usedw (usedw));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = DEPTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = NUM_BITS_USED_WORDS,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.almost_full_value = ALMOST_FULL_VALUE;
assign stall_out = full;
assign valid_out = ~empty;
endmodule
|
// lpddr2_cntrlr_s0_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_s0_mm_interconnect_0 (
input wire avl_clk_out_clk_clk, // avl_clk_out_clk.clk
input wire cpu_inst_reset_n_reset_bridge_in_reset_reset, // cpu_inst_reset_n_reset_bridge_in_reset.reset
input wire sequencer_trk_mgr_inst_avl_reset_reset_bridge_in_reset_reset, // sequencer_trk_mgr_inst_avl_reset_reset_bridge_in_reset.reset
input wire [19:0] cpu_inst_data_master_address, // cpu_inst_data_master.address
output wire cpu_inst_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_inst_data_master_byteenable, // .byteenable
input wire cpu_inst_data_master_read, // .read
output wire [31:0] cpu_inst_data_master_readdata, // .readdata
input wire cpu_inst_data_master_write, // .write
input wire [31:0] cpu_inst_data_master_writedata, // .writedata
input wire [16:0] cpu_inst_instruction_master_address, // cpu_inst_instruction_master.address
output wire cpu_inst_instruction_master_waitrequest, // .waitrequest
input wire cpu_inst_instruction_master_read, // .read
output wire [31:0] cpu_inst_instruction_master_readdata, // .readdata
input wire [19:0] sequencer_trk_mgr_inst_trkm_address, // sequencer_trk_mgr_inst_trkm.address
output wire sequencer_trk_mgr_inst_trkm_waitrequest, // .waitrequest
input wire sequencer_trk_mgr_inst_trkm_read, // .read
output wire [31:0] sequencer_trk_mgr_inst_trkm_readdata, // .readdata
input wire sequencer_trk_mgr_inst_trkm_write, // .write
input wire [31:0] sequencer_trk_mgr_inst_trkm_writedata, // .writedata
output wire [15:0] hphy_bridge_s0_address, // hphy_bridge_s0.address
output wire hphy_bridge_s0_write, // .write
output wire hphy_bridge_s0_read, // .read
input wire [31:0] hphy_bridge_s0_readdata, // .readdata
output wire [31:0] hphy_bridge_s0_writedata, // .writedata
input wire hphy_bridge_s0_waitrequest, // .waitrequest
output wire [11:0] sequencer_mem_s1_address, // sequencer_mem_s1.address
output wire sequencer_mem_s1_write, // .write
input wire [31:0] sequencer_mem_s1_readdata, // .readdata
output wire [31:0] sequencer_mem_s1_writedata, // .writedata
output wire [3:0] sequencer_mem_s1_byteenable, // .byteenable
output wire sequencer_mem_s1_chipselect, // .chipselect
output wire [5:0] sequencer_trk_mgr_inst_trks_address, // sequencer_trk_mgr_inst_trks.address
output wire sequencer_trk_mgr_inst_trks_write, // .write
output wire sequencer_trk_mgr_inst_trks_read, // .read
input wire [31:0] sequencer_trk_mgr_inst_trks_readdata, // .readdata
output wire [31:0] sequencer_trk_mgr_inst_trks_writedata, // .writedata
input wire sequencer_trk_mgr_inst_trks_waitrequest, // .waitrequest
output wire [15:0] trk_mm_bridge_s0_address, // trk_mm_bridge_s0.address
output wire trk_mm_bridge_s0_write, // .write
output wire trk_mm_bridge_s0_read, // .read
input wire [31:0] trk_mm_bridge_s0_readdata, // .readdata
output wire [31:0] trk_mm_bridge_s0_writedata, // .writedata
output wire [0:0] trk_mm_bridge_s0_burstcount, // .burstcount
output wire [3:0] trk_mm_bridge_s0_byteenable, // .byteenable
input wire trk_mm_bridge_s0_readdatavalid, // .readdatavalid
input wire trk_mm_bridge_s0_waitrequest, // .waitrequest
output wire trk_mm_bridge_s0_debugaccess // .debugaccess
);
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
wire [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
wire [93:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [3:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
wire sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_waitrequest; // sequencer_trk_mgr_inst_trkm_agent:av_waitrequest -> sequencer_trk_mgr_inst_trkm_translator:uav_waitrequest
wire [31:0] sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_readdata; // sequencer_trk_mgr_inst_trkm_agent:av_readdata -> sequencer_trk_mgr_inst_trkm_translator:uav_readdata
wire sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_debugaccess; // sequencer_trk_mgr_inst_trkm_translator:uav_debugaccess -> sequencer_trk_mgr_inst_trkm_agent:av_debugaccess
wire [19:0] sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_address; // sequencer_trk_mgr_inst_trkm_translator:uav_address -> sequencer_trk_mgr_inst_trkm_agent:av_address
wire sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_read; // sequencer_trk_mgr_inst_trkm_translator:uav_read -> sequencer_trk_mgr_inst_trkm_agent:av_read
wire [3:0] sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_byteenable; // sequencer_trk_mgr_inst_trkm_translator:uav_byteenable -> sequencer_trk_mgr_inst_trkm_agent:av_byteenable
wire sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_readdatavalid; // sequencer_trk_mgr_inst_trkm_agent:av_readdatavalid -> sequencer_trk_mgr_inst_trkm_translator:uav_readdatavalid
wire sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_lock; // sequencer_trk_mgr_inst_trkm_translator:uav_lock -> sequencer_trk_mgr_inst_trkm_agent:av_lock
wire sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_write; // sequencer_trk_mgr_inst_trkm_translator:uav_write -> sequencer_trk_mgr_inst_trkm_agent:av_write
wire [31:0] sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_writedata; // sequencer_trk_mgr_inst_trkm_translator:uav_writedata -> sequencer_trk_mgr_inst_trkm_agent:av_writedata
wire [2:0] sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_burstcount; // sequencer_trk_mgr_inst_trkm_translator:uav_burstcount -> sequencer_trk_mgr_inst_trkm_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> sequencer_trk_mgr_inst_trkm_agent:rp_valid
wire [93:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> sequencer_trk_mgr_inst_trkm_agent:rp_data
wire rsp_mux_001_src_ready; // sequencer_trk_mgr_inst_trkm_agent:rp_ready -> rsp_mux_001:src_ready
wire [3:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> sequencer_trk_mgr_inst_trkm_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> sequencer_trk_mgr_inst_trkm_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> sequencer_trk_mgr_inst_trkm_agent:rp_endofpacket
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_agent:av_debugaccess
wire [19:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_agent:av_read
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_agent:av_write
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_agent:av_writedata
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_agent:av_burstcount
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> cpu_inst_instruction_master_agent:rp_valid
wire [93:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> cpu_inst_instruction_master_agent:rp_data
wire rsp_mux_002_src_ready; // cpu_inst_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
wire [3:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> cpu_inst_instruction_master_agent:rp_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> cpu_inst_instruction_master_agent:rp_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> cpu_inst_instruction_master_agent:rp_endofpacket
wire [31:0] trk_mm_bridge_s0_agent_m0_readdata; // trk_mm_bridge_s0_translator:uav_readdata -> trk_mm_bridge_s0_agent:m0_readdata
wire trk_mm_bridge_s0_agent_m0_waitrequest; // trk_mm_bridge_s0_translator:uav_waitrequest -> trk_mm_bridge_s0_agent:m0_waitrequest
wire trk_mm_bridge_s0_agent_m0_debugaccess; // trk_mm_bridge_s0_agent:m0_debugaccess -> trk_mm_bridge_s0_translator:uav_debugaccess
wire [19:0] trk_mm_bridge_s0_agent_m0_address; // trk_mm_bridge_s0_agent:m0_address -> trk_mm_bridge_s0_translator:uav_address
wire [3:0] trk_mm_bridge_s0_agent_m0_byteenable; // trk_mm_bridge_s0_agent:m0_byteenable -> trk_mm_bridge_s0_translator:uav_byteenable
wire trk_mm_bridge_s0_agent_m0_read; // trk_mm_bridge_s0_agent:m0_read -> trk_mm_bridge_s0_translator:uav_read
wire trk_mm_bridge_s0_agent_m0_readdatavalid; // trk_mm_bridge_s0_translator:uav_readdatavalid -> trk_mm_bridge_s0_agent:m0_readdatavalid
wire trk_mm_bridge_s0_agent_m0_lock; // trk_mm_bridge_s0_agent:m0_lock -> trk_mm_bridge_s0_translator:uav_lock
wire [31:0] trk_mm_bridge_s0_agent_m0_writedata; // trk_mm_bridge_s0_agent:m0_writedata -> trk_mm_bridge_s0_translator:uav_writedata
wire trk_mm_bridge_s0_agent_m0_write; // trk_mm_bridge_s0_agent:m0_write -> trk_mm_bridge_s0_translator:uav_write
wire [2:0] trk_mm_bridge_s0_agent_m0_burstcount; // trk_mm_bridge_s0_agent:m0_burstcount -> trk_mm_bridge_s0_translator:uav_burstcount
wire trk_mm_bridge_s0_agent_rf_source_valid; // trk_mm_bridge_s0_agent:rf_source_valid -> trk_mm_bridge_s0_agent_rsp_fifo:in_valid
wire [94:0] trk_mm_bridge_s0_agent_rf_source_data; // trk_mm_bridge_s0_agent:rf_source_data -> trk_mm_bridge_s0_agent_rsp_fifo:in_data
wire trk_mm_bridge_s0_agent_rf_source_ready; // trk_mm_bridge_s0_agent_rsp_fifo:in_ready -> trk_mm_bridge_s0_agent:rf_source_ready
wire trk_mm_bridge_s0_agent_rf_source_startofpacket; // trk_mm_bridge_s0_agent:rf_source_startofpacket -> trk_mm_bridge_s0_agent_rsp_fifo:in_startofpacket
wire trk_mm_bridge_s0_agent_rf_source_endofpacket; // trk_mm_bridge_s0_agent:rf_source_endofpacket -> trk_mm_bridge_s0_agent_rsp_fifo:in_endofpacket
wire trk_mm_bridge_s0_agent_rsp_fifo_out_valid; // trk_mm_bridge_s0_agent_rsp_fifo:out_valid -> trk_mm_bridge_s0_agent:rf_sink_valid
wire [94:0] trk_mm_bridge_s0_agent_rsp_fifo_out_data; // trk_mm_bridge_s0_agent_rsp_fifo:out_data -> trk_mm_bridge_s0_agent:rf_sink_data
wire trk_mm_bridge_s0_agent_rsp_fifo_out_ready; // trk_mm_bridge_s0_agent:rf_sink_ready -> trk_mm_bridge_s0_agent_rsp_fifo:out_ready
wire trk_mm_bridge_s0_agent_rsp_fifo_out_startofpacket; // trk_mm_bridge_s0_agent_rsp_fifo:out_startofpacket -> trk_mm_bridge_s0_agent:rf_sink_startofpacket
wire trk_mm_bridge_s0_agent_rsp_fifo_out_endofpacket; // trk_mm_bridge_s0_agent_rsp_fifo:out_endofpacket -> trk_mm_bridge_s0_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> trk_mm_bridge_s0_agent:cp_valid
wire [93:0] cmd_mux_src_data; // cmd_mux:src_data -> trk_mm_bridge_s0_agent:cp_data
wire cmd_mux_src_ready; // trk_mm_bridge_s0_agent:cp_ready -> cmd_mux:src_ready
wire [3:0] cmd_mux_src_channel; // cmd_mux:src_channel -> trk_mm_bridge_s0_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> trk_mm_bridge_s0_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> trk_mm_bridge_s0_agent:cp_endofpacket
wire [31:0] hphy_bridge_s0_agent_m0_readdata; // hphy_bridge_s0_translator:uav_readdata -> hphy_bridge_s0_agent:m0_readdata
wire hphy_bridge_s0_agent_m0_waitrequest; // hphy_bridge_s0_translator:uav_waitrequest -> hphy_bridge_s0_agent:m0_waitrequest
wire hphy_bridge_s0_agent_m0_debugaccess; // hphy_bridge_s0_agent:m0_debugaccess -> hphy_bridge_s0_translator:uav_debugaccess
wire [19:0] hphy_bridge_s0_agent_m0_address; // hphy_bridge_s0_agent:m0_address -> hphy_bridge_s0_translator:uav_address
wire [3:0] hphy_bridge_s0_agent_m0_byteenable; // hphy_bridge_s0_agent:m0_byteenable -> hphy_bridge_s0_translator:uav_byteenable
wire hphy_bridge_s0_agent_m0_read; // hphy_bridge_s0_agent:m0_read -> hphy_bridge_s0_translator:uav_read
wire hphy_bridge_s0_agent_m0_readdatavalid; // hphy_bridge_s0_translator:uav_readdatavalid -> hphy_bridge_s0_agent:m0_readdatavalid
wire hphy_bridge_s0_agent_m0_lock; // hphy_bridge_s0_agent:m0_lock -> hphy_bridge_s0_translator:uav_lock
wire [31:0] hphy_bridge_s0_agent_m0_writedata; // hphy_bridge_s0_agent:m0_writedata -> hphy_bridge_s0_translator:uav_writedata
wire hphy_bridge_s0_agent_m0_write; // hphy_bridge_s0_agent:m0_write -> hphy_bridge_s0_translator:uav_write
wire [2:0] hphy_bridge_s0_agent_m0_burstcount; // hphy_bridge_s0_agent:m0_burstcount -> hphy_bridge_s0_translator:uav_burstcount
wire hphy_bridge_s0_agent_rf_source_valid; // hphy_bridge_s0_agent:rf_source_valid -> hphy_bridge_s0_agent_rsp_fifo:in_valid
wire [94:0] hphy_bridge_s0_agent_rf_source_data; // hphy_bridge_s0_agent:rf_source_data -> hphy_bridge_s0_agent_rsp_fifo:in_data
wire hphy_bridge_s0_agent_rf_source_ready; // hphy_bridge_s0_agent_rsp_fifo:in_ready -> hphy_bridge_s0_agent:rf_source_ready
wire hphy_bridge_s0_agent_rf_source_startofpacket; // hphy_bridge_s0_agent:rf_source_startofpacket -> hphy_bridge_s0_agent_rsp_fifo:in_startofpacket
wire hphy_bridge_s0_agent_rf_source_endofpacket; // hphy_bridge_s0_agent:rf_source_endofpacket -> hphy_bridge_s0_agent_rsp_fifo:in_endofpacket
wire hphy_bridge_s0_agent_rsp_fifo_out_valid; // hphy_bridge_s0_agent_rsp_fifo:out_valid -> hphy_bridge_s0_agent:rf_sink_valid
wire [94:0] hphy_bridge_s0_agent_rsp_fifo_out_data; // hphy_bridge_s0_agent_rsp_fifo:out_data -> hphy_bridge_s0_agent:rf_sink_data
wire hphy_bridge_s0_agent_rsp_fifo_out_ready; // hphy_bridge_s0_agent:rf_sink_ready -> hphy_bridge_s0_agent_rsp_fifo:out_ready
wire hphy_bridge_s0_agent_rsp_fifo_out_startofpacket; // hphy_bridge_s0_agent_rsp_fifo:out_startofpacket -> hphy_bridge_s0_agent:rf_sink_startofpacket
wire hphy_bridge_s0_agent_rsp_fifo_out_endofpacket; // hphy_bridge_s0_agent_rsp_fifo:out_endofpacket -> hphy_bridge_s0_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> hphy_bridge_s0_agent:cp_valid
wire [93:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> hphy_bridge_s0_agent:cp_data
wire cmd_mux_001_src_ready; // hphy_bridge_s0_agent:cp_ready -> cmd_mux_001:src_ready
wire [3:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> hphy_bridge_s0_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> hphy_bridge_s0_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> hphy_bridge_s0_agent:cp_endofpacket
wire [31:0] sequencer_mem_s1_agent_m0_readdata; // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_agent:m0_readdata
wire sequencer_mem_s1_agent_m0_waitrequest; // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_agent:m0_waitrequest
wire sequencer_mem_s1_agent_m0_debugaccess; // sequencer_mem_s1_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
wire [19:0] sequencer_mem_s1_agent_m0_address; // sequencer_mem_s1_agent:m0_address -> sequencer_mem_s1_translator:uav_address
wire [3:0] sequencer_mem_s1_agent_m0_byteenable; // sequencer_mem_s1_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
wire sequencer_mem_s1_agent_m0_read; // sequencer_mem_s1_agent:m0_read -> sequencer_mem_s1_translator:uav_read
wire sequencer_mem_s1_agent_m0_readdatavalid; // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_agent:m0_readdatavalid
wire sequencer_mem_s1_agent_m0_lock; // sequencer_mem_s1_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
wire [31:0] sequencer_mem_s1_agent_m0_writedata; // sequencer_mem_s1_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
wire sequencer_mem_s1_agent_m0_write; // sequencer_mem_s1_agent:m0_write -> sequencer_mem_s1_translator:uav_write
wire [2:0] sequencer_mem_s1_agent_m0_burstcount; // sequencer_mem_s1_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
wire sequencer_mem_s1_agent_rf_source_valid; // sequencer_mem_s1_agent:rf_source_valid -> sequencer_mem_s1_agent_rsp_fifo:in_valid
wire [94:0] sequencer_mem_s1_agent_rf_source_data; // sequencer_mem_s1_agent:rf_source_data -> sequencer_mem_s1_agent_rsp_fifo:in_data
wire sequencer_mem_s1_agent_rf_source_ready; // sequencer_mem_s1_agent_rsp_fifo:in_ready -> sequencer_mem_s1_agent:rf_source_ready
wire sequencer_mem_s1_agent_rf_source_startofpacket; // sequencer_mem_s1_agent:rf_source_startofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_startofpacket
wire sequencer_mem_s1_agent_rf_source_endofpacket; // sequencer_mem_s1_agent:rf_source_endofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_endofpacket
wire sequencer_mem_s1_agent_rsp_fifo_out_valid; // sequencer_mem_s1_agent_rsp_fifo:out_valid -> sequencer_mem_s1_agent:rf_sink_valid
wire [94:0] sequencer_mem_s1_agent_rsp_fifo_out_data; // sequencer_mem_s1_agent_rsp_fifo:out_data -> sequencer_mem_s1_agent:rf_sink_data
wire sequencer_mem_s1_agent_rsp_fifo_out_ready; // sequencer_mem_s1_agent:rf_sink_ready -> sequencer_mem_s1_agent_rsp_fifo:out_ready
wire sequencer_mem_s1_agent_rsp_fifo_out_startofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_agent:rf_sink_startofpacket
wire sequencer_mem_s1_agent_rsp_fifo_out_endofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sequencer_mem_s1_agent:cp_valid
wire [93:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sequencer_mem_s1_agent:cp_data
wire cmd_mux_002_src_ready; // sequencer_mem_s1_agent:cp_ready -> cmd_mux_002:src_ready
wire [3:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sequencer_mem_s1_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sequencer_mem_s1_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sequencer_mem_s1_agent:cp_endofpacket
wire [31:0] sequencer_trk_mgr_inst_trks_agent_m0_readdata; // sequencer_trk_mgr_inst_trks_translator:uav_readdata -> sequencer_trk_mgr_inst_trks_agent:m0_readdata
wire sequencer_trk_mgr_inst_trks_agent_m0_waitrequest; // sequencer_trk_mgr_inst_trks_translator:uav_waitrequest -> sequencer_trk_mgr_inst_trks_agent:m0_waitrequest
wire sequencer_trk_mgr_inst_trks_agent_m0_debugaccess; // sequencer_trk_mgr_inst_trks_agent:m0_debugaccess -> sequencer_trk_mgr_inst_trks_translator:uav_debugaccess
wire [19:0] sequencer_trk_mgr_inst_trks_agent_m0_address; // sequencer_trk_mgr_inst_trks_agent:m0_address -> sequencer_trk_mgr_inst_trks_translator:uav_address
wire [3:0] sequencer_trk_mgr_inst_trks_agent_m0_byteenable; // sequencer_trk_mgr_inst_trks_agent:m0_byteenable -> sequencer_trk_mgr_inst_trks_translator:uav_byteenable
wire sequencer_trk_mgr_inst_trks_agent_m0_read; // sequencer_trk_mgr_inst_trks_agent:m0_read -> sequencer_trk_mgr_inst_trks_translator:uav_read
wire sequencer_trk_mgr_inst_trks_agent_m0_readdatavalid; // sequencer_trk_mgr_inst_trks_translator:uav_readdatavalid -> sequencer_trk_mgr_inst_trks_agent:m0_readdatavalid
wire sequencer_trk_mgr_inst_trks_agent_m0_lock; // sequencer_trk_mgr_inst_trks_agent:m0_lock -> sequencer_trk_mgr_inst_trks_translator:uav_lock
wire [31:0] sequencer_trk_mgr_inst_trks_agent_m0_writedata; // sequencer_trk_mgr_inst_trks_agent:m0_writedata -> sequencer_trk_mgr_inst_trks_translator:uav_writedata
wire sequencer_trk_mgr_inst_trks_agent_m0_write; // sequencer_trk_mgr_inst_trks_agent:m0_write -> sequencer_trk_mgr_inst_trks_translator:uav_write
wire [2:0] sequencer_trk_mgr_inst_trks_agent_m0_burstcount; // sequencer_trk_mgr_inst_trks_agent:m0_burstcount -> sequencer_trk_mgr_inst_trks_translator:uav_burstcount
wire sequencer_trk_mgr_inst_trks_agent_rf_source_valid; // sequencer_trk_mgr_inst_trks_agent:rf_source_valid -> sequencer_trk_mgr_inst_trks_agent_rsp_fifo:in_valid
wire [94:0] sequencer_trk_mgr_inst_trks_agent_rf_source_data; // sequencer_trk_mgr_inst_trks_agent:rf_source_data -> sequencer_trk_mgr_inst_trks_agent_rsp_fifo:in_data
wire sequencer_trk_mgr_inst_trks_agent_rf_source_ready; // sequencer_trk_mgr_inst_trks_agent_rsp_fifo:in_ready -> sequencer_trk_mgr_inst_trks_agent:rf_source_ready
wire sequencer_trk_mgr_inst_trks_agent_rf_source_startofpacket; // sequencer_trk_mgr_inst_trks_agent:rf_source_startofpacket -> sequencer_trk_mgr_inst_trks_agent_rsp_fifo:in_startofpacket
wire sequencer_trk_mgr_inst_trks_agent_rf_source_endofpacket; // sequencer_trk_mgr_inst_trks_agent:rf_source_endofpacket -> sequencer_trk_mgr_inst_trks_agent_rsp_fifo:in_endofpacket
wire sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_valid; // sequencer_trk_mgr_inst_trks_agent_rsp_fifo:out_valid -> sequencer_trk_mgr_inst_trks_agent:rf_sink_valid
wire [94:0] sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_data; // sequencer_trk_mgr_inst_trks_agent_rsp_fifo:out_data -> sequencer_trk_mgr_inst_trks_agent:rf_sink_data
wire sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_ready; // sequencer_trk_mgr_inst_trks_agent:rf_sink_ready -> sequencer_trk_mgr_inst_trks_agent_rsp_fifo:out_ready
wire sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_startofpacket; // sequencer_trk_mgr_inst_trks_agent_rsp_fifo:out_startofpacket -> sequencer_trk_mgr_inst_trks_agent:rf_sink_startofpacket
wire sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_endofpacket; // sequencer_trk_mgr_inst_trks_agent_rsp_fifo:out_endofpacket -> sequencer_trk_mgr_inst_trks_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sequencer_trk_mgr_inst_trks_agent:cp_valid
wire [93:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sequencer_trk_mgr_inst_trks_agent:cp_data
wire cmd_mux_003_src_ready; // sequencer_trk_mgr_inst_trks_agent:cp_ready -> cmd_mux_003:src_ready
wire [3:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sequencer_trk_mgr_inst_trks_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sequencer_trk_mgr_inst_trks_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sequencer_trk_mgr_inst_trks_agent:cp_endofpacket
wire cpu_inst_data_master_agent_cp_valid; // cpu_inst_data_master_agent:cp_valid -> router:sink_valid
wire [93:0] cpu_inst_data_master_agent_cp_data; // cpu_inst_data_master_agent:cp_data -> router:sink_data
wire cpu_inst_data_master_agent_cp_ready; // router:sink_ready -> cpu_inst_data_master_agent:cp_ready
wire cpu_inst_data_master_agent_cp_startofpacket; // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_inst_data_master_agent_cp_endofpacket; // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [93:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [3:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire sequencer_trk_mgr_inst_trkm_agent_cp_valid; // sequencer_trk_mgr_inst_trkm_agent:cp_valid -> router_001:sink_valid
wire [93:0] sequencer_trk_mgr_inst_trkm_agent_cp_data; // sequencer_trk_mgr_inst_trkm_agent:cp_data -> router_001:sink_data
wire sequencer_trk_mgr_inst_trkm_agent_cp_ready; // router_001:sink_ready -> sequencer_trk_mgr_inst_trkm_agent:cp_ready
wire sequencer_trk_mgr_inst_trkm_agent_cp_startofpacket; // sequencer_trk_mgr_inst_trkm_agent:cp_startofpacket -> router_001:sink_startofpacket
wire sequencer_trk_mgr_inst_trkm_agent_cp_endofpacket; // sequencer_trk_mgr_inst_trkm_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [93:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [3:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire cpu_inst_instruction_master_agent_cp_valid; // cpu_inst_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [93:0] cpu_inst_instruction_master_agent_cp_data; // cpu_inst_instruction_master_agent:cp_data -> router_002:sink_data
wire cpu_inst_instruction_master_agent_cp_ready; // router_002:sink_ready -> cpu_inst_instruction_master_agent:cp_ready
wire cpu_inst_instruction_master_agent_cp_startofpacket; // cpu_inst_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire cpu_inst_instruction_master_agent_cp_endofpacket; // cpu_inst_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
wire [93:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
wire [3:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
wire trk_mm_bridge_s0_agent_rp_valid; // trk_mm_bridge_s0_agent:rp_valid -> router_003:sink_valid
wire [93:0] trk_mm_bridge_s0_agent_rp_data; // trk_mm_bridge_s0_agent:rp_data -> router_003:sink_data
wire trk_mm_bridge_s0_agent_rp_ready; // router_003:sink_ready -> trk_mm_bridge_s0_agent:rp_ready
wire trk_mm_bridge_s0_agent_rp_startofpacket; // trk_mm_bridge_s0_agent:rp_startofpacket -> router_003:sink_startofpacket
wire trk_mm_bridge_s0_agent_rp_endofpacket; // trk_mm_bridge_s0_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [93:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [3:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire hphy_bridge_s0_agent_rp_valid; // hphy_bridge_s0_agent:rp_valid -> router_004:sink_valid
wire [93:0] hphy_bridge_s0_agent_rp_data; // hphy_bridge_s0_agent:rp_data -> router_004:sink_data
wire hphy_bridge_s0_agent_rp_ready; // router_004:sink_ready -> hphy_bridge_s0_agent:rp_ready
wire hphy_bridge_s0_agent_rp_startofpacket; // hphy_bridge_s0_agent:rp_startofpacket -> router_004:sink_startofpacket
wire hphy_bridge_s0_agent_rp_endofpacket; // hphy_bridge_s0_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [93:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [3:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire sequencer_mem_s1_agent_rp_valid; // sequencer_mem_s1_agent:rp_valid -> router_005:sink_valid
wire [93:0] sequencer_mem_s1_agent_rp_data; // sequencer_mem_s1_agent:rp_data -> router_005:sink_data
wire sequencer_mem_s1_agent_rp_ready; // router_005:sink_ready -> sequencer_mem_s1_agent:rp_ready
wire sequencer_mem_s1_agent_rp_startofpacket; // sequencer_mem_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire sequencer_mem_s1_agent_rp_endofpacket; // sequencer_mem_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [93:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [3:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sequencer_trk_mgr_inst_trks_agent_rp_valid; // sequencer_trk_mgr_inst_trks_agent:rp_valid -> router_006:sink_valid
wire [93:0] sequencer_trk_mgr_inst_trks_agent_rp_data; // sequencer_trk_mgr_inst_trks_agent:rp_data -> router_006:sink_data
wire sequencer_trk_mgr_inst_trks_agent_rp_ready; // router_006:sink_ready -> sequencer_trk_mgr_inst_trks_agent:rp_ready
wire sequencer_trk_mgr_inst_trks_agent_rp_startofpacket; // sequencer_trk_mgr_inst_trks_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sequencer_trk_mgr_inst_trks_agent_rp_endofpacket; // sequencer_trk_mgr_inst_trks_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [93:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [3:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [93:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [3:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [93:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [3:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [93:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [3:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [93:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [3:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [93:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [3:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [93:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [3:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux_002:sink1_valid
wire [93:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux_002:sink1_data
wire cmd_demux_002_src0_ready; // cmd_mux_002:sink1_ready -> cmd_demux_002:src0_ready
wire [3:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [93:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [3:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [93:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [3:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [93:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [3:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [93:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [3:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [93:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [3:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_002:sink0_valid
wire [93:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_002:sink0_data
wire rsp_demux_002_src1_ready; // rsp_mux_002:sink0_ready -> rsp_demux_002:src1_ready
wire [3:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [93:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [3:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire trk_mm_bridge_s0_agent_rdata_fifo_src_valid; // trk_mm_bridge_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] trk_mm_bridge_s0_agent_rdata_fifo_src_data; // trk_mm_bridge_s0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire trk_mm_bridge_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> trk_mm_bridge_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> trk_mm_bridge_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> trk_mm_bridge_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // trk_mm_bridge_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> trk_mm_bridge_s0_agent:rdata_fifo_sink_error
wire hphy_bridge_s0_agent_rdata_fifo_src_valid; // hphy_bridge_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] hphy_bridge_s0_agent_rdata_fifo_src_data; // hphy_bridge_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire hphy_bridge_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> hphy_bridge_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> hphy_bridge_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> hphy_bridge_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // hphy_bridge_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> hphy_bridge_s0_agent:rdata_fifo_sink_error
wire sequencer_mem_s1_agent_rdata_fifo_src_valid; // sequencer_mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] sequencer_mem_s1_agent_rdata_fifo_src_data; // sequencer_mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire sequencer_mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> sequencer_mem_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> sequencer_mem_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> sequencer_mem_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // sequencer_mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> sequencer_mem_s1_agent:rdata_fifo_sink_error
wire sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_valid; // sequencer_trk_mgr_inst_trks_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_data; // sequencer_trk_mgr_inst_trks_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sequencer_trk_mgr_inst_trks_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sequencer_trk_mgr_inst_trks_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sequencer_trk_mgr_inst_trks_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sequencer_trk_mgr_inst_trks_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sequencer_trk_mgr_inst_trks_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sequencer_trk_mgr_inst_trkm_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_read), // .read
.uav_write (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sequencer_trk_mgr_inst_trkm_address), // avalon_anti_master_0.address
.av_waitrequest (sequencer_trk_mgr_inst_trkm_waitrequest), // .waitrequest
.av_read (sequencer_trk_mgr_inst_trkm_read), // .read
.av_readdata (sequencer_trk_mgr_inst_trkm_readdata), // .readdata
.av_write (sequencer_trk_mgr_inst_trkm_write), // .write
.av_writedata (sequencer_trk_mgr_inst_trkm_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) trk_mm_bridge_s0_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (trk_mm_bridge_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (trk_mm_bridge_s0_agent_m0_burstcount), // .burstcount
.uav_read (trk_mm_bridge_s0_agent_m0_read), // .read
.uav_write (trk_mm_bridge_s0_agent_m0_write), // .write
.uav_waitrequest (trk_mm_bridge_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (trk_mm_bridge_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (trk_mm_bridge_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (trk_mm_bridge_s0_agent_m0_readdata), // .readdata
.uav_writedata (trk_mm_bridge_s0_agent_m0_writedata), // .writedata
.uav_lock (trk_mm_bridge_s0_agent_m0_lock), // .lock
.uav_debugaccess (trk_mm_bridge_s0_agent_m0_debugaccess), // .debugaccess
.av_address (trk_mm_bridge_s0_address), // avalon_anti_slave_0.address
.av_write (trk_mm_bridge_s0_write), // .write
.av_read (trk_mm_bridge_s0_read), // .read
.av_readdata (trk_mm_bridge_s0_readdata), // .readdata
.av_writedata (trk_mm_bridge_s0_writedata), // .writedata
.av_burstcount (trk_mm_bridge_s0_burstcount), // .burstcount
.av_byteenable (trk_mm_bridge_s0_byteenable), // .byteenable
.av_readdatavalid (trk_mm_bridge_s0_readdatavalid), // .readdatavalid
.av_waitrequest (trk_mm_bridge_s0_waitrequest), // .waitrequest
.av_debugaccess (trk_mm_bridge_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hphy_bridge_s0_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hphy_bridge_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hphy_bridge_s0_agent_m0_burstcount), // .burstcount
.uav_read (hphy_bridge_s0_agent_m0_read), // .read
.uav_write (hphy_bridge_s0_agent_m0_write), // .write
.uav_waitrequest (hphy_bridge_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hphy_bridge_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hphy_bridge_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (hphy_bridge_s0_agent_m0_readdata), // .readdata
.uav_writedata (hphy_bridge_s0_agent_m0_writedata), // .writedata
.uav_lock (hphy_bridge_s0_agent_m0_lock), // .lock
.uav_debugaccess (hphy_bridge_s0_agent_m0_debugaccess), // .debugaccess
.av_address (hphy_bridge_s0_address), // avalon_anti_slave_0.address
.av_write (hphy_bridge_s0_write), // .write
.av_read (hphy_bridge_s0_read), // .read
.av_readdata (hphy_bridge_s0_readdata), // .readdata
.av_writedata (hphy_bridge_s0_writedata), // .writedata
.av_waitrequest (hphy_bridge_s0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_mem_s1_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_mem_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_mem_s1_agent_m0_read), // .read
.uav_write (sequencer_mem_s1_agent_m0_write), // .write
.uav_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata
.uav_lock (sequencer_mem_s1_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_mem_s1_address), // avalon_anti_slave_0.address
.av_write (sequencer_mem_s1_write), // .write
.av_readdata (sequencer_mem_s1_readdata), // .readdata
.av_writedata (sequencer_mem_s1_writedata), // .writedata
.av_byteenable (sequencer_mem_s1_byteenable), // .byteenable
.av_chipselect (sequencer_mem_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (6),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_trk_mgr_inst_trks_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_trk_mgr_inst_trks_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_trk_mgr_inst_trks_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_trk_mgr_inst_trks_agent_m0_read), // .read
.uav_write (sequencer_trk_mgr_inst_trks_agent_m0_write), // .write
.uav_waitrequest (sequencer_trk_mgr_inst_trks_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_trk_mgr_inst_trks_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_trk_mgr_inst_trks_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_trk_mgr_inst_trks_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_trk_mgr_inst_trks_agent_m0_writedata), // .writedata
.uav_lock (sequencer_trk_mgr_inst_trks_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_trk_mgr_inst_trks_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_trk_mgr_inst_trks_address), // avalon_anti_slave_0.address
.av_write (sequencer_trk_mgr_inst_trks_write), // .write
.av_read (sequencer_trk_mgr_inst_trks_read), // .read
.av_readdata (sequencer_trk_mgr_inst_trks_readdata), // .readdata
.av_writedata (sequencer_trk_mgr_inst_trks_writedata), // .writedata
.av_waitrequest (sequencer_trk_mgr_inst_trks_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_CACHE_H (88),
.PKT_CACHE_L (85),
.PKT_THREAD_ID_H (81),
.PKT_THREAD_ID_L (81),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.ST_DATA_W (94),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_inst_data_master_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_CACHE_H (88),
.PKT_CACHE_L (85),
.PKT_THREAD_ID_H (81),
.PKT_THREAD_ID_L (81),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.ST_DATA_W (94),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sequencer_trk_mgr_inst_trkm_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_address), // av.address
.av_write (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_write), // .write
.av_read (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_read), // .read
.av_writedata (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sequencer_trk_mgr_inst_trkm_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sequencer_trk_mgr_inst_trkm_agent_cp_valid), // cp.valid
.cp_data (sequencer_trk_mgr_inst_trkm_agent_cp_data), // .data
.cp_startofpacket (sequencer_trk_mgr_inst_trkm_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sequencer_trk_mgr_inst_trkm_agent_cp_endofpacket), // .endofpacket
.cp_ready (sequencer_trk_mgr_inst_trkm_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_CACHE_H (88),
.PKT_CACHE_L (85),
.PKT_THREAD_ID_H (81),
.PKT_THREAD_ID_L (81),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.ST_DATA_W (94),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_inst_instruction_master_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_002_src_valid), // rp.valid
.rp_data (rsp_mux_002_src_data), // .data
.rp_channel (rsp_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (94),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) trk_mm_bridge_s0_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (trk_mm_bridge_s0_agent_m0_address), // m0.address
.m0_burstcount (trk_mm_bridge_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (trk_mm_bridge_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (trk_mm_bridge_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (trk_mm_bridge_s0_agent_m0_lock), // .lock
.m0_readdata (trk_mm_bridge_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (trk_mm_bridge_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (trk_mm_bridge_s0_agent_m0_read), // .read
.m0_waitrequest (trk_mm_bridge_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (trk_mm_bridge_s0_agent_m0_writedata), // .writedata
.m0_write (trk_mm_bridge_s0_agent_m0_write), // .write
.rp_endofpacket (trk_mm_bridge_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (trk_mm_bridge_s0_agent_rp_ready), // .ready
.rp_valid (trk_mm_bridge_s0_agent_rp_valid), // .valid
.rp_data (trk_mm_bridge_s0_agent_rp_data), // .data
.rp_startofpacket (trk_mm_bridge_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (trk_mm_bridge_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (trk_mm_bridge_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (trk_mm_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (trk_mm_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (trk_mm_bridge_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (trk_mm_bridge_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (trk_mm_bridge_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (trk_mm_bridge_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (trk_mm_bridge_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (trk_mm_bridge_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (trk_mm_bridge_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (trk_mm_bridge_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (trk_mm_bridge_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (95),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) trk_mm_bridge_s0_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (trk_mm_bridge_s0_agent_rf_source_data), // in.data
.in_valid (trk_mm_bridge_s0_agent_rf_source_valid), // .valid
.in_ready (trk_mm_bridge_s0_agent_rf_source_ready), // .ready
.in_startofpacket (trk_mm_bridge_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (trk_mm_bridge_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (trk_mm_bridge_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (trk_mm_bridge_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (trk_mm_bridge_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (trk_mm_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (trk_mm_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (94),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hphy_bridge_s0_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hphy_bridge_s0_agent_m0_address), // m0.address
.m0_burstcount (hphy_bridge_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (hphy_bridge_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hphy_bridge_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (hphy_bridge_s0_agent_m0_lock), // .lock
.m0_readdata (hphy_bridge_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (hphy_bridge_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hphy_bridge_s0_agent_m0_read), // .read
.m0_waitrequest (hphy_bridge_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hphy_bridge_s0_agent_m0_writedata), // .writedata
.m0_write (hphy_bridge_s0_agent_m0_write), // .write
.rp_endofpacket (hphy_bridge_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hphy_bridge_s0_agent_rp_ready), // .ready
.rp_valid (hphy_bridge_s0_agent_rp_valid), // .valid
.rp_data (hphy_bridge_s0_agent_rp_data), // .data
.rp_startofpacket (hphy_bridge_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (hphy_bridge_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hphy_bridge_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hphy_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hphy_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hphy_bridge_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hphy_bridge_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hphy_bridge_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hphy_bridge_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hphy_bridge_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hphy_bridge_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (hphy_bridge_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hphy_bridge_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hphy_bridge_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (95),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hphy_bridge_s0_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hphy_bridge_s0_agent_rf_source_data), // in.data
.in_valid (hphy_bridge_s0_agent_rf_source_valid), // .valid
.in_ready (hphy_bridge_s0_agent_rf_source_ready), // .ready
.in_startofpacket (hphy_bridge_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hphy_bridge_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (hphy_bridge_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (hphy_bridge_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (hphy_bridge_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hphy_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hphy_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (94),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_mem_s1_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_mem_s1_agent_m0_address), // m0.address
.m0_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_mem_s1_agent_m0_lock), // .lock
.m0_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_mem_s1_agent_m0_read), // .read
.m0_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata
.m0_write (sequencer_mem_s1_agent_m0_write), // .write
.rp_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_mem_s1_agent_rp_ready), // .ready
.rp_valid (sequencer_mem_s1_agent_rp_valid), // .valid
.rp_data (sequencer_mem_s1_agent_rp_data), // .data
.rp_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_mem_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_mem_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (95),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_mem_s1_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_mem_s1_agent_rf_source_data), // in.data
.in_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid
.in_ready (sequencer_mem_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (93),
.PKT_ORI_BURST_SIZE_L (91),
.PKT_RESPONSE_STATUS_H (90),
.PKT_RESPONSE_STATUS_L (89),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_TRANS_LOCK (60),
.PKT_BEGIN_BURST (75),
.PKT_PROTECTION_H (84),
.PKT_PROTECTION_L (82),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (80),
.PKT_DEST_ID_L (79),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (94),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_trk_mgr_inst_trks_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_trk_mgr_inst_trks_agent_m0_address), // m0.address
.m0_burstcount (sequencer_trk_mgr_inst_trks_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_trk_mgr_inst_trks_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_trk_mgr_inst_trks_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_trk_mgr_inst_trks_agent_m0_lock), // .lock
.m0_readdata (sequencer_trk_mgr_inst_trks_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_trk_mgr_inst_trks_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_trk_mgr_inst_trks_agent_m0_read), // .read
.m0_waitrequest (sequencer_trk_mgr_inst_trks_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_trk_mgr_inst_trks_agent_m0_writedata), // .writedata
.m0_write (sequencer_trk_mgr_inst_trks_agent_m0_write), // .write
.rp_endofpacket (sequencer_trk_mgr_inst_trks_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_trk_mgr_inst_trks_agent_rp_ready), // .ready
.rp_valid (sequencer_trk_mgr_inst_trks_agent_rp_valid), // .valid
.rp_data (sequencer_trk_mgr_inst_trks_agent_rp_data), // .data
.rp_startofpacket (sequencer_trk_mgr_inst_trks_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_trk_mgr_inst_trks_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_trk_mgr_inst_trks_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_trk_mgr_inst_trks_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_trk_mgr_inst_trks_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_trk_mgr_inst_trks_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (95),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_trk_mgr_inst_trks_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_trk_mgr_inst_trks_agent_rf_source_data), // in.data
.in_valid (sequencer_trk_mgr_inst_trks_agent_rf_source_valid), // .valid
.in_ready (sequencer_trk_mgr_inst_trks_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_trk_mgr_inst_trks_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_trk_mgr_inst_trks_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_trk_mgr_inst_trks_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
lpddr2_cntrlr_s0_mm_interconnect_0_router router (
.sink_ready (cpu_inst_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_router_001 router_001 (
.sink_ready (sequencer_trk_mgr_inst_trkm_agent_cp_ready), // sink.ready
.sink_valid (sequencer_trk_mgr_inst_trkm_agent_cp_valid), // .valid
.sink_data (sequencer_trk_mgr_inst_trkm_agent_cp_data), // .data
.sink_startofpacket (sequencer_trk_mgr_inst_trkm_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_trk_mgr_inst_trkm_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_router_002 router_002 (
.sink_ready (cpu_inst_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_router_003 router_003 (
.sink_ready (trk_mm_bridge_s0_agent_rp_ready), // sink.ready
.sink_valid (trk_mm_bridge_s0_agent_rp_valid), // .valid
.sink_data (trk_mm_bridge_s0_agent_rp_data), // .data
.sink_startofpacket (trk_mm_bridge_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (trk_mm_bridge_s0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_router_003 router_004 (
.sink_ready (hphy_bridge_s0_agent_rp_ready), // sink.ready
.sink_valid (hphy_bridge_s0_agent_rp_valid), // .valid
.sink_data (hphy_bridge_s0_agent_rp_data), // .data
.sink_startofpacket (hphy_bridge_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hphy_bridge_s0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_router_005 router_005 (
.sink_ready (sequencer_mem_s1_agent_rp_ready), // sink.ready
.sink_valid (sequencer_mem_s1_agent_rp_valid), // .valid
.sink_data (sequencer_mem_s1_agent_rp_data), // .data
.sink_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_router_006 router_006 (
.sink_ready (sequencer_trk_mgr_inst_trks_agent_rp_ready), // sink.ready
.sink_valid (sequencer_trk_mgr_inst_trks_agent_rp_valid), // .valid
.sink_data (sequencer_trk_mgr_inst_trks_agent_rp_data), // .data
.sink_startofpacket (sequencer_trk_mgr_inst_trks_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_trk_mgr_inst_trks_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux cmd_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_mux cmd_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src0_valid), // .valid
.sink1_channel (cmd_demux_002_src0_channel), // .channel
.sink1_data (cmd_demux_002_src0_data), // .data
.sink1_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux_001 rsp_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_cmd_demux_002 rsp_demux_003 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_rsp_mux rsp_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_002_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_002_src1_valid), // .valid
.sink0_channel (rsp_demux_002_src1_channel), // .channel
.sink0_data (rsp_demux_002_src1_data), // .data
.sink0_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (trk_mm_bridge_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (trk_mm_bridge_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (trk_mm_bridge_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hphy_bridge_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hphy_bridge_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hphy_bridge_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_trk_mgr_inst_trks_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v2_0_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_1_V
`define SKY130_FD_SC_LP__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_1_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
wire [31:0] outb0c0;
wire [31:0] outb0c1;
wire [31:0] outb1c0;
wire [31:0] outb1c1;
reg [7:0] lclmem [7:0];
ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
.outb1c0(outb1c0), .outb1c1(outb1c1)
);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`endif
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;
if (outb0c0 != 32'h00) $stop;
if (outb0c1 != 32'h01) $stop;
if (outb1c0 != 32'h10) $stop;
if (outb1c1 != 32'h11) $stop;
end
if (cyc==3) begin
// Can we scope down and read and write vars?
ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100;
ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100;
ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100;
ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
end
if (cyc==4) begin
// Can we do dotted's inside array sels?
ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
if (outb0c0 != 32'h100) $stop;
if (outb0c1 != 32'h101) $stop;
if (outb1c0 != 32'h110) $stop;
if (outb1c1 != 32'h111) $stop;
end
if (cyc==5) begin
if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
if (outb0c0 != 32'h1100) $stop;
if (outb0c1 != 32'h2101) $stop;
if (outb1c0 != 32'h2110) $stop;
if (outb1c1 != 32'h3111) $stop;
end
if (cyc==6) begin
if (outb0c0 != 32'h31100) $stop;
if (outb0c1 != 32'h02101) $stop;
if (outb1c0 != 32'h42110) $stop;
if (outb1c1 != 32'h03111) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
endmodule
module ma (
output wire [31:0] outb0c0,
output wire [31:0] outb0c1,
output wire [31:0] outb1c0,
output wire [31:0] outb1c1
);
`INLINE_MODULE
reg [7:0] rmtmem [7:0];
mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
endmodule
module mb (
output wire [31:0] outc0,
output wire [31:0] outc1
);
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 (.out(outc0));
mc #(P2,1) mc1 (.out(outc1));
global_mod #(32'hf33d) global_cell2 ();
wire reach_up_clk = t.clk;
always @(reach_up_clk) begin
if (P2==0) begin // Only for mb0
if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances
if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances
if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances
if (outc0 !== mc0.out) $stop; // Lower instances
if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances
if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances
if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances
if (outc1 !== mc1.out) $stop; // Lower instances
end
end
endmodule
module mc (output reg [31:0] out);
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
initial begin
out = {24'h0,P2[3:0],P3[3:0]};
//$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out);
end
// Can we look from the top module name down?
wire [31:0] reach_up_cyc = t.cyc;
always @ (posedge t.clk) begin
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
if (reach_up_cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf33d) $stop;
end
if (reach_up_cyc==4) begin
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
end
if (reach_up_cyc==5) begin
// Can we set another instance?
if (P3==1) begin // Without this, there are two possible correct answers...
mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2};
$display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2);
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_0_V
`define SKY130_FD_SC_LP__A32O_0_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_0 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_0_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] a = crc[7:0];
wire [7:0] b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[63:0]),
// Inputs
.clk (clk),
.a (a[7:0]),
.b (b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, a, b
);
input clk;
input [7:0] a;
input [7:0] b;
output reg [63:0] out;
and u0[7:0] (out[7:0], a[7:0], b[7:0]);
and u1[7:0] (out[15:8], a[0], b[7:0]);
and u2[7:0] (out[23:16], a[0], b[0]);
nand u3[7:0] (out[31:24], a[0], b[7:0]);
or u4[7:0] (out[39:32], a[0], b[7:0]);
nor u5[7:0] (out[47:40], a[0], b[7:0]);
xor u6[7:0] (out[55:48], a[0], b[7:0]);
xnor u7[7:0] (out[63:56], a[0], b[7:0]);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:33:48 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Initial/Initial_stub.v
// Design : Initial
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *)
module Initial(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[1599:0]" */;
input clka;
input [9:0]addra;
output [1599:0]douta;
endmodule
|
module mux_4to1_19bit(S, i1, i2, i3, i4, Q);
input[18:0] i1, i2, i3, i4;
input[1:0] S;
output[18:0] Q;
Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);
Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);
Mux_4_to_1 mux2(S, i1[2], i2[2], i3[2], i4[2], Q[2]);
Mux_4_to_1 mux3(S, i1[3], i2[3], i3[3], i4[3], Q[3]);
Mux_4_to_1 mux4(S, i1[4], i2[4], i3[4], i4[4], Q[4]);
Mux_4_to_1 mux5(S, i1[5], i2[5], i3[5], i4[5], Q[5]);
Mux_4_to_1 mux6(S, i1[6], i2[6], i3[6], i4[6], Q[6]);
Mux_4_to_1 mux7(S, i1[7], i2[7], i3[7], i4[7], Q[7]);
Mux_4_to_1 mux8(S, i1[8], i2[8], i3[8], i4[8], Q[8]);
Mux_4_to_1 mux9(S, i1[9], i2[9], i3[9], i4[9], Q[9]);
Mux_4_to_1 mux10(S, i1[10], i2[10], i3[10], i4[10], Q[10]);
Mux_4_to_1 mux11(S, i1[11], i2[11], i3[11], i4[11], Q[11]);
Mux_4_to_1 mux12(S, i1[12], i2[12], i3[12], i4[12], Q[12]);
Mux_4_to_1 mux13(S, i1[13], i2[13], i3[13], i4[13], Q[13]);
Mux_4_to_1 mux14(S, i1[14], i2[14], i3[14], i4[14], Q[14]);
Mux_4_to_1 mux15(S, i1[15], i2[15], i3[15], i4[15], Q[15]);
Mux_4_to_1 mux16(S, i1[16], i2[16], i3[16], i4[16], Q[16]);
Mux_4_to_1 mux17(S, i1[17], i2[17], i3[17], i4[17], Q[17]);
Mux_4_to_1 mux18(S, i1[18], i2[18], i3[18], i4[18], Q[18]);
endmodule |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_async_fifo
*
*/
`default_nettype none
module openhmc_async_fifo #(
parameter DWIDTH = 8,
parameter ENTRIES = 2,
parameter DISABLE_FULL_ASSERT = 0,
parameter DISABLE_EMPTY_ASSERT = 0,
parameter DISABLE_SHIFT_OUT_ASSERT = 0,
parameter DISABLE_SHIFT_IN_ASSERT = 0,
parameter DISABLE_SO_DATA_KNOWN_ASSERT = 0
) (
// interface for shift_in side
input wire si_clk,
input wire si_res_n,
input wire shift_in,
input wire [DWIDTH-1:0] d_in,
output reg full,
output reg almost_full,
// interface for shift_out side
input wire so_clk,
input wire so_res_n,
input wire shift_out,
output reg [DWIDTH-1:0] d_out,
output reg empty,
output reg almost_empty
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
// the FIFO currently can only have up to 2048 entries
localparam LG_ENTRIES = (ENTRIES <= 2) ? 1 :
(ENTRIES <= 4) ? 2 :
(ENTRIES <= 8) ? 3 :
(ENTRIES <= 16) ? 4 :
(ENTRIES <= 32) ? 5 :
(ENTRIES <= 64) ? 6 :
(ENTRIES <= 128) ? 7 :
(ENTRIES <= 256) ? 8 :
(ENTRIES <= 512) ? 9 :
(ENTRIES <= 1024) ? 10 : 11;
reg [DWIDTH-1:0] entry [0:ENTRIES-1];
reg [LG_ENTRIES-1:0] wp;
reg [LG_ENTRIES-1:0] rp;
// asynchronous thermo wp
reg [ENTRIES-1:0] thermo_wp_w;
reg [ENTRIES-1:0] thermo_rp_w;
reg [ENTRIES-1:0] thermo_wp;
reg [ENTRIES-1:0] thermo_rp;
reg [ENTRIES-1:0] thermo_wp_synced_0;
reg [ENTRIES-1:0] thermo_wp_synced_1;
reg [ENTRIES-1:0] thermo_rp_synced_0;
reg [ENTRIES-1:0] thermo_rp_synced_1;
wire [LG_ENTRIES-1:0] next_rp;
wire [LG_ENTRIES-1:0] next_rp_p1;
wire set_empty_w;
wire set_a_empty_0_w;
wire set_a_empty_1_w;
wire set_a_empty_2_w;
wire set_full_w;
wire set_a_full_0_w;
wire set_a_full_1_w;
wire set_a_full_2_w;
wire [LG_ENTRIES-1:0] upper_bound;
assign next_rp = (rp == upper_bound) ? {LG_ENTRIES {1'b0}} : rp + 1'b1;
assign next_rp_p1 = (next_rp == upper_bound) ? {LG_ENTRIES {1'b0}} : next_rp + 1'b1;
assign set_empty_w = (thermo_rp == thermo_wp_synced_1);
assign set_a_empty_0_w = (thermo_rp == {~thermo_wp_synced_1[0], thermo_wp_synced_1[ENTRIES-1:1]});
assign set_a_empty_1_w = (thermo_rp == {~thermo_wp_synced_1[1:0], thermo_wp_synced_1[ENTRIES-1:2]});
assign set_a_empty_2_w = (thermo_rp == {~thermo_wp_synced_1[2:0], thermo_wp_synced_1[ENTRIES-1:3]});
assign set_full_w = &(thermo_wp ^ thermo_rp_synced_1);
assign set_a_full_0_w = &(thermo_wp ^ {~thermo_rp_synced_1[0], thermo_rp_synced_1[ENTRIES-1:1]});
assign set_a_full_1_w = &(thermo_wp ^ {~thermo_rp_synced_1[1:0], thermo_rp_synced_1[ENTRIES-1:2]});
assign set_a_full_2_w = &(thermo_wp ^ {~thermo_rp_synced_1[2:0], thermo_rp_synced_1[ENTRIES-1:3]});
assign upper_bound = ENTRIES[LG_ENTRIES-1:0] - {{LG_ENTRIES-1 {1'b0}}, 1'b1};
always @ (*)
begin
if (shift_in && !full)
thermo_wp_w = {thermo_wp[ENTRIES-2:0], !thermo_wp[ENTRIES-1]};
else
thermo_wp_w = thermo_wp;
end
always @ (*)
begin
if (shift_out && !empty)
thermo_rp_w = {thermo_rp[ENTRIES-2:0], !thermo_rp[ENTRIES-1]};
else
thermo_rp_w = thermo_rp;
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
// shift_in side:
`ifdef ASYNC_RES
always @(posedge si_clk or negedge si_res_n) `else
always @(posedge si_clk) `endif
begin
if (!si_res_n)
begin
wp <= {LG_ENTRIES {1'b0}};
thermo_wp <= {ENTRIES {1'b0}};
full <= 1'b0;
almost_full <= 1'b0;
end
else
begin
full <= set_full_w || (set_a_full_0_w && shift_in) ;
almost_full <= set_full_w || (set_a_full_0_w) || (set_a_full_1_w && shift_in) ;
thermo_wp <= thermo_wp_w;
if (shift_in && !full)
begin
entry[wp] <= d_in;
if (wp == upper_bound)
wp <= {LG_ENTRIES {1'b0}};
else
wp <= wp + 1'b1;
end
end
end
// shift_out side
`ifdef ASYNC_RES
always @(posedge so_clk or negedge so_res_n) `else
always @(posedge so_clk) `endif
begin
if (!so_res_n)
begin
rp <= {LG_ENTRIES {1'b0}};
thermo_rp <= {ENTRIES {1'b0}};
empty <= 1'b1;
almost_empty <= 1'b1;
end
else
begin
empty <= (set_empty_w || (set_a_empty_0_w && shift_out && !empty));
almost_empty <= empty || set_empty_w || set_a_empty_0_w || (set_a_empty_1_w && shift_out && !empty);
thermo_rp <= thermo_rp_w;
// shift out and not empty or empty but a new word just finished synchronizing (like almost empty)
if (shift_out && !empty)
begin
rp <= next_rp;
d_out <= entry[next_rp];
end
else
begin
d_out <= entry[rp];
end
end
end
// syncing thermp_rp to shift_in domain
`ifdef ASYNC_RES
always @(posedge si_clk or negedge si_res_n) `else
always @(posedge si_clk) `endif
begin
if (!si_res_n)
begin
thermo_rp_synced_0 <= {ENTRIES {1'b0}};
thermo_rp_synced_1 <= {ENTRIES {1'b0}};
end
else
begin
thermo_rp_synced_0 <= thermo_rp;
thermo_rp_synced_1 <= thermo_rp_synced_0;
end
end
// syncing write pointer to shift_out domain
`ifdef ASYNC_RES
always @(posedge so_clk or negedge so_res_n) `else
always @(posedge so_clk) `endif
begin
if (!so_res_n)
begin
thermo_wp_synced_0 <= {ENTRIES {1'b0}};
thermo_wp_synced_1 <= {ENTRIES {1'b0}};
end
else
begin
thermo_wp_synced_0 <= thermo_wp;
thermo_wp_synced_1 <= thermo_wp_synced_0;
end
end
`ifdef CAG_ASSERTIONS
shift_in_and_full: assert property (@(posedge si_clk) disable iff(!si_res_n) (shift_in |-> !full));
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge so_clk) disable iff(!so_res_n) (shift_out |-> !empty));
if (DISABLE_SO_DATA_KNOWN_ASSERT == 0) begin
dout_known: assert property (@(posedge so_clk) disable iff(!so_res_n) (!empty |-> !$isunknown(d_out)));
end
final
begin
if (DISABLE_FULL_ASSERT == 0)
begin
full_set_assert: assert (!full);
end
if (DISABLE_EMPTY_ASSERT == 0)
begin
almost_empty_not_set_assert: assert (almost_empty);
empty_not_set_assert: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
`default_nettype wire
|
// -- (c) Copyright 2016 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
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// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
`timescale 1ps/1ps
module tuser_design_1_axis_broadcaster_0_0 #
(
parameter C_S_AXIS_TUSER_WIDTH = 8,
parameter C_M_AXIS_TUSER_WIDTH = 8
)
(
input wire [C_S_AXIS_TUSER_WIDTH-1:0] tuser,
output wire [C_M_AXIS_TUSER_WIDTH-1:0] tuser_out
);
assign tuser_out = {1'b0,1'b0};
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_log CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=21 WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources = reg 33
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altbarrel_shift_kud
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [31:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
wire [159:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 32'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[159:128];
assign
dir_w = {dir_pipe[0], dir_w[3:0], direction_w},
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {sbit_piper1d, smux_w[127:0], data},
sel_w = {distance[4:0]},
smux_w = {((({32{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128])), ((({32{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), ((({32{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64])), ((({32{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0]))};
endmodule //acl_fp_log_s5_altbarrel_shift_kud
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" SHIFTDIR="LEFT" WIDTH=64 WIDTHDIST=6 data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altbarrel_shift_sbb
(
data,
distance,
result) ;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
assign
dir_w = {dir_w[5:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {smux_w[383:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_s5_altbarrel_shift_sbb
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="RIGHT" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources = reg 33
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altbarrel_shift_72e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [31:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
wire [159:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 32'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[159:128];
assign
dir_w = {dir_pipe[0], dir_w[3:0], direction_w},
direction_w = 1'b1,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {sbit_piper1d, smux_w[127:0], data},
sel_w = {distance[4:0]},
smux_w = {((({32{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128])), ((({32{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), ((({32{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64])), ((({32{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0]))};
endmodule //acl_fp_log_s5_altbarrel_shift_72e
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="AND" PIPELINE=3 WIDTH=8 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_and_or_h9b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [7:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [7:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [7:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [7:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[7], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[6] & connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] & connection_r0_w[5]), (operation_r1_w[3] & connection_r0_w[4]), (operation_r1_w[2] & connection_r0_w[3]), (operation_r1_w[1] & connection_r0_w[2]), (operation_r1_w[0] & connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] & connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_altfp_log_and_or_h9b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=8 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_and_or_v6b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [7:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [7:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [7:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [7:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[7], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_altfp_log_and_or_v6b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=23 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_and_or_c8b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [22:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [22:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [3:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [22:0] connection_r0_w;
wire [3:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [22:0] operation_r1_w;
wire [3:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 4'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[22], operation_r1_w[17], operation_r1_w[11], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[3]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[21] | connection_r0_w[22]), (operation_r1_w[20] | connection_r0_w[21]), (operation_r1_w[19] | connection_r0_w[20]), (operation_r1_w[18] | connection_r0_w[19]), connection_r0_w[18], (operation_r1_w[16] | connection_r0_w[17]), (operation_r1_w[15] | connection_r0_w[16]), (operation_r1_w[14] | connection_r0_w[15]), (operation_r1_w[13] | connection_r0_w[14]), (operation_r1_w[12] | connection_r0_w[13]), connection_r0_w[12], (operation_r1_w[10] | connection_r0_w[11]), (operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[2] | connection_r1_w[3]), (operation_r2_w[1] | connection_r1_w[2]), (operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_altfp_log_and_or_c8b
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=39 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_s0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [38:0] dataa;
input [38:0] datab;
output [38:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [38:0] dataa;
tri0 [38:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [19:0] wire_csa_lower_result;
wire [18:0] wire_csa_upper0_result;
wire [18:0] wire_csa_upper1_result;
wire [38:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[19:0]),
.datab(datab[19:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 20,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[38:20]),
.datab(datab[38:20]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 19,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[38:20]),
.datab(datab[38:20]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 19,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({19{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({19{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_s0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=31 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_k0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [30:0] dataa;
input [30:0] datab;
output [30:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [30:0] dataa;
tri0 [30:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [15:0] wire_csa_lower_result;
wire [14:0] wire_csa_upper0_result;
wire [14:0] wire_csa_upper1_result;
wire [30:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[15:0]),
.datab(datab[15:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 16,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 15,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 15,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({15{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({15{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_k0e
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_0nc
(
dataa,
datab,
result) ;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] dataa;
tri0 [7:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] wire_add_sub1_result;
wire [7:0] result_w;
lpm_add_sub add_sub1
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "UNSIGNED",
add_sub1.lpm_width = 8,
add_sub1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub1_result;
endmodule //acl_fp_log_s5_altfp_log_csa_0nc
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=12 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_d4b
(
dataa,
datab,
result) ;
input [11:0] dataa;
input [11:0] datab;
output [11:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [11:0] dataa;
tri0 [11:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] wire_add_sub2_result;
wire [11:0] result_w;
lpm_add_sub add_sub2
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "UNSIGNED",
add_sub2.lpm_width = 12,
add_sub2.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub2_result;
endmodule //acl_fp_log_s5_altfp_log_csa_d4b
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=6 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_umc
(
dataa,
datab,
result) ;
input [5:0] dataa;
input [5:0] datab;
output [5:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [5:0] dataa;
tri0 [5:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] wire_add_sub3_result;
wire [5:0] result_w;
lpm_add_sub add_sub3
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_representation = "UNSIGNED",
add_sub3.lpm_width = 6,
add_sub3.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub3_result;
endmodule //acl_fp_log_s5_altfp_log_csa_umc
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_nlf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [25:0] wire_add_sub4_result;
wire [25:0] result_w;
lpm_add_sub add_sub4
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "SUB",
add_sub4.lpm_pipeline = 1,
add_sub4.lpm_representation = "UNSIGNED",
add_sub4.lpm_width = 26,
add_sub4.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub4_result;
endmodule //acl_fp_log_s5_altfp_log_csa_nlf
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_8kf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [7:0] dataa;
tri0 [7:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] wire_add_sub5_result;
wire [7:0] result_w;
lpm_add_sub add_sub5
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "SUB",
add_sub5.lpm_pipeline = 2,
add_sub5.lpm_representation = "UNSIGNED",
add_sub5.lpm_width = 8,
add_sub5.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub5_result;
endmodule //acl_fp_log_s5_altfp_log_csa_8kf
//altfp_log_rr_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" WIDTH_ALMOSTLOG=39 WIDTH_Y0=25 WIDTH_Z=26 a0_in aclr almostlog clk_en clock y0_in z
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=29 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_r0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [28:0] dataa;
input [28:0] datab;
output [28:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [28:0] dataa;
tri0 [28:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [14:0] wire_csa_lower_result;
wire [13:0] wire_csa_upper0_result;
wire [13:0] wire_csa_upper1_result;
wire [28:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[14:0]),
.datab(datab[14:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 15,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 14,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 14,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({14{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({14{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_r0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_o0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_o0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=31 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_l1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [30:0] dataa;
input [30:0] datab;
output [30:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [30:0] dataa;
tri0 [30:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [15:0] wire_csa_lower_result;
wire [14:0] wire_csa_upper0_result;
wire [14:0] wire_csa_upper1_result;
wire [30:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[15:0]),
.datab(datab[15:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 16,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 15,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 15,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({15{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({15{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_l1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=29 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_s1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [28:0] dataa;
input [28:0] datab;
output [28:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [28:0] dataa;
tri0 [28:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [14:0] wire_csa_lower_result;
wire [13:0] wire_csa_upper0_result;
wire [13:0] wire_csa_upper1_result;
wire [28:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[14:0]),
.datab(datab[14:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 15,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 14,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 14,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({14{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({14{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_s1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_csa_p1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_altfp_log_csa_p1e
//synthesis_resources = lpm_add_sub 27 lpm_mult 4 lpm_mux 5 reg 531
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_range_reduction_0sd
(
a0_in,
aclr,
almostlog,
clk_en,
clock,
y0_in,
z) ;
input [4:0] a0_in;
input aclr;
output [38:0] almostlog;
input clk_en;
input clock;
input [24:0] y0_in;
output [25:0] z;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [38:0] wire_add0_1_result;
wire [38:0] wire_add0_2_result;
wire [38:0] wire_add0_3_result;
wire [30:0] wire_add1_1_result;
wire [28:0] wire_add1_2_result;
wire [25:0] wire_add1_3_result;
wire [30:0] wire_sub1_1_result;
wire [28:0] wire_sub1_2_result;
wire [25:0] wire_sub1_3_result;
reg [4:0] A_pipe0_reg0;
reg [4:0] A_pipe0_reg1;
reg [4:0] A_pipe0_reg2;
reg [3:0] A_wire1_reg0;
reg [3:0] A_wire2_reg0;
reg [3:0] A_wire3_reg0;
reg [20:0] B_wire1_reg0;
reg [26:0] B_wire2_reg0;
reg [24:0] B_wire3_reg0;
reg [30:0] P_pipe0_reg0;
reg [28:0] P_pipe1_reg0;
reg [28:0] P_pipe2_reg0;
reg [22:0] P_pipe3_reg0;
reg [38:0] S_pipe22_reg0;
reg [38:0] S_pipe23_reg0;
reg [38:0] S_pipe24_reg0;
reg [38:0] S_wire1_reg0;
reg [38:0] S_wire2_reg0;
reg [38:0] S_wire3_reg0;
reg [24:0] Z_wire1_reg0;
reg [30:0] Z_wire2_reg0;
reg [28:0] Z_wire3_reg0;
wire [30:0] wire_mult0_result;
wire [28:0] wire_mult1_result;
wire [28:0] wire_mult2_result;
wire [22:0] wire_mult3_result;
wire [5:0] wire_InvTable0_result;
wire [38:0] wire_LogTable0_result;
wire [34:0] wire_LogTable1_result;
wire [31:0] wire_LogTable2_result;
wire [28:0] wire_LogTable3_result;
wire [3:0] A1_is_all_zero;
wire [3:0] A1_is_not_zero;
wire [3:0] A_all_zero2;
wire [3:0] A_all_zero3;
wire [4:0] A_pipe0;
wire [3:0] A_pipe11;
wire [3:0] A_pipe12;
wire [3:0] A_pipe13;
wire [4:0] A_wire0;
wire [3:0] A_wire1;
wire [3:0] A_wire2;
wire [3:0] A_wire3;
wire [30:0] B_pad_wire1;
wire [28:0] B_pad_wire2;
wire [25:0] B_pad_wire3;
wire [20:0] B_pipe1;
wire [26:0] B_pipe2;
wire [24:0] B_pipe3;
wire [20:0] B_wire1;
wire [26:0] B_wire2;
wire [24:0] B_wire3;
wire [30:0] epsZ_pad_wire1;
wire [28:0] epsZ_pad_wire2;
wire [25:0] epsZ_pad_wire3;
wire [30:0] epsZ_wire1;
wire [39:0] epsZ_wire2;
wire [40:0] epsZ_wire3;
wire [5:0] InvA0;
wire [38:0] L_wire0;
wire [34:0] L_wire1;
wire [31:0] L_wire2;
wire [28:0] L_wire3;
wire [30:0] mux0_data0;
wire [30:0] mux0_data1;
wire [30:0] P_pad_wire1;
wire [28:0] P_pad_wire2;
wire [25:0] P_pad_wire3;
wire [30:0] P_pipe0;
wire [28:0] P_pipe1;
wire [28:0] P_pipe2;
wire [22:0] P_pipe3;
wire [30:0] P_wire0;
wire [28:0] P_wire1;
wire [28:0] P_wire2;
wire [22:0] P_wire3;
wire [38:0] S_pipe11;
wire [38:0] S_pipe12;
wire [38:0] S_pipe13;
wire [38:0] S_pipe22;
wire [38:0] S_pipe23;
wire [38:0] S_pipe24;
wire [38:0] S_wire1;
wire [38:0] S_wire2;
wire [38:0] S_wire3;
wire [38:0] S_wire4;
wire [24:0] Z_pipe1;
wire [30:0] Z_pipe2;
wire [28:0] Z_pipe3;
wire [24:0] Z_wire1;
wire [30:0] Z_wire2;
wire [28:0] Z_wire3;
wire [25:0] Z_wire4;
wire [24:0] ZM_wire1;
wire [24:0] ZM_wire2;
wire [18:0] ZM_wire3;
acl_fp_log_s5_altfp_log_csa_s0e add0_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe11),
.datab({{4{1'b0}}, L_wire1}),
.result(wire_add0_1_result));
acl_fp_log_s5_altfp_log_csa_s0e add0_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe12),
.datab({{7{1'b0}}, L_wire2}),
.result(wire_add0_2_result));
acl_fp_log_s5_altfp_log_csa_s0e add0_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe13),
.datab({{10{1'b0}}, L_wire3}),
.result(wire_add0_3_result));
acl_fp_log_s5_altfp_log_csa_k0e add1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire1),
.datab(epsZ_pad_wire1),
.result(wire_add1_1_result));
acl_fp_log_s5_altfp_log_csa_r0e add1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire2),
.datab(epsZ_pad_wire2),
.result(wire_add1_2_result));
acl_fp_log_s5_altfp_log_csa_o0e add1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire3),
.datab(epsZ_pad_wire3),
.result(wire_add1_3_result));
acl_fp_log_s5_altfp_log_csa_l1e sub1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_1_result),
.datab(P_pad_wire1),
.result(wire_sub1_1_result));
acl_fp_log_s5_altfp_log_csa_s1e sub1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_2_result),
.datab(P_pad_wire2),
.result(wire_sub1_2_result));
acl_fp_log_s5_altfp_log_csa_p1e sub1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_3_result),
.datab(P_pad_wire3),
.result(wire_sub1_3_result));
// synopsys translate_off
initial
A_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg0 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg0 <= A_pipe0;
// synopsys translate_off
initial
A_pipe0_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg1 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg1 <= A_pipe0_reg0;
// synopsys translate_off
initial
A_pipe0_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg2 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg2 <= A_pipe0_reg1;
// synopsys translate_off
initial
A_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire1_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire1_reg0 <= A_wire1;
// synopsys translate_off
initial
A_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire2_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire2_reg0 <= A_wire2;
// synopsys translate_off
initial
A_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire3_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire3_reg0 <= A_wire3;
// synopsys translate_off
initial
B_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire1_reg0 <= 21'b0;
else if (clk_en == 1'b1) B_wire1_reg0 <= B_wire1;
// synopsys translate_off
initial
B_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire2_reg0 <= 27'b0;
else if (clk_en == 1'b1) B_wire2_reg0 <= B_wire2;
// synopsys translate_off
initial
B_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire3_reg0 <= 25'b0;
else if (clk_en == 1'b1) B_wire3_reg0 <= B_wire3;
// synopsys translate_off
initial
P_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe0_reg0 <= 31'b0;
else if (clk_en == 1'b1) P_pipe0_reg0 <= P_pipe0;
// synopsys translate_off
initial
P_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe1_reg0 <= 29'b0;
else if (clk_en == 1'b1) P_pipe1_reg0 <= P_pipe1;
// synopsys translate_off
initial
P_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe2_reg0 <= 29'b0;
else if (clk_en == 1'b1) P_pipe2_reg0 <= P_pipe2;
// synopsys translate_off
initial
P_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe3_reg0 <= 23'b0;
else if (clk_en == 1'b1) P_pipe3_reg0 <= P_pipe3;
// synopsys translate_off
initial
S_pipe22_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe22_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_pipe22_reg0 <= S_pipe22;
// synopsys translate_off
initial
S_pipe23_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe23_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_pipe23_reg0 <= S_pipe23;
// synopsys translate_off
initial
S_pipe24_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe24_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_pipe24_reg0 <= S_pipe24;
// synopsys translate_off
initial
S_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire1_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_wire1_reg0 <= S_wire1;
// synopsys translate_off
initial
S_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire2_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_wire2_reg0 <= S_wire2;
// synopsys translate_off
initial
S_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire3_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_wire3_reg0 <= S_wire3;
// synopsys translate_off
initial
Z_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire1_reg0 <= 25'b0;
else if (clk_en == 1'b1) Z_wire1_reg0 <= Z_wire1;
// synopsys translate_off
initial
Z_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire2_reg0 <= 31'b0;
else if (clk_en == 1'b1) Z_wire2_reg0 <= Z_wire2;
// synopsys translate_off
initial
Z_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire3_reg0 <= 29'b0;
else if (clk_en == 1'b1) Z_wire3_reg0 <= Z_wire3;
lpm_mult mult0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(InvA0),
.datab(y0_in),
.result(wire_mult0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult0.lpm_pipeline = 2,
mult0.lpm_representation = "UNSIGNED",
mult0.lpm_widtha = 6,
mult0.lpm_widthb = 25,
mult0.lpm_widthp = 31,
mult0.lpm_type = "lpm_mult";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire1),
.datab(ZM_wire1),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 1,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 4,
mult1.lpm_widthb = 25,
mult1.lpm_widthp = 29,
mult1.lpm_type = "lpm_mult";
lpm_mult mult2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire2),
.datab(ZM_wire2),
.result(wire_mult2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult2.lpm_pipeline = 1,
mult2.lpm_representation = "UNSIGNED",
mult2.lpm_widtha = 4,
mult2.lpm_widthb = 25,
mult2.lpm_widthp = 29,
mult2.lpm_type = "lpm_mult";
lpm_mult mult3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire3),
.datab(ZM_wire3),
.result(wire_mult3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult3.lpm_pipeline = 1,
mult3.lpm_representation = "UNSIGNED",
mult3.lpm_widtha = 4,
mult3.lpm_widthb = 19,
mult3.lpm_widthp = 23,
mult3.lpm_type = "lpm_mult";
lpm_mux InvTable0
(
.data({6'b100001, {2{6'b100010}}, {2{6'b100011}}, {2{6'b100100}}, 6'b100101, {2{6'b100110}}, 6'b100111, 6'b101000, {2{6'b101001}}, 6'b101010, 6'b101011, 6'b010110, {2{6'b010111}}, {2{6'b011000}}, {2{6'b011001}}, 6'b011010, {2{6'b011011}}, 6'b011100, 6'b011101, 6'b011110, 6'b011111, {2{6'b100000}}}),
.result(wire_InvTable0_result),
.sel(a0_in)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
InvTable0.lpm_size = 32,
InvTable0.lpm_width = 6,
InvTable0.lpm_widths = 5,
InvTable0.lpm_type = "lpm_mux";
lpm_mux LogTable0
(
.data({39'b111110000001111101011001001111000110001, {2{39'b111100000111101011100111100111111111100}}, {2{39'b111010010000111100101101011101010001110}}, {2{39'b111000011101100011111000100100011101011}}, 39'b110110101101010101011010000011111100001, {2{39'b110101000000000110011111000111101011001}}, 39'b110011010101101101001010110001100001100, 39'b110001101110000000010000011100001100110, {2{39'b110000001000110111001111001001010100010}}, 39'b101110100110001010001101010100010101001, 39'b101101000101110001110101000101000111110, 39'b010111111110101111101000111011110110000, {2{39'b010101001000101010111000000111001110001}}, {2{39'b010010011010010110001000010001001101001}}, {2{39'b001111110011001000111000110110010110011}}, 39'b001101010010011111011010011110010001010, {2{39'b001010110111111010000000110101101010100}}, 39'b001000100010111100011101000001000100111, 39'b000110010011001101011110010111010101100, 39'b000100001000010110011000101101011001111, 39'b000010000010000010101110110001001111001, {2{{39{1'b0}}}}}),
.result(wire_LogTable0_result),
.sel(A_wire0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable0.lpm_size = 32,
LogTable0.lpm_width = 39,
LogTable0.lpm_widths = 5,
LogTable0.lpm_type = "lpm_mux";
lpm_mux LogTable1
(
.data({35'b11100110010110111001111001101110111, 35'b11010101011101111001011010000111110, 35'b11000100101001010101000010100100111, 35'b10110011111001001010011110010110101, 35'b10100011001101010111011010100001011, 35'b10010010100101111001100101111100011, 35'b10000010000010101110110001001111001, 35'b01110001100011110100101110110000010, 35'b01101001010101111101010100100011000, 35'b01011000111101011000010111100001101, 35'b01001000101000111110110001111111101, 35'b00111000011000101110011100001001100, 35'b00101000001100100101001111110010110, 35'b00011000000100100001001000010100010, 35'b00001000000000100000000010101010111, {35{1'b0}}}),
.result(wire_LogTable1_result),
.sel(A_pipe11)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable1.lpm_size = 16,
LogTable1.lpm_width = 35,
LogTable1.lpm_widths = 4,
LogTable1.lpm_type = "lpm_mux";
lpm_mux LogTable2
(
.data({32'b11101000110100110011111101101000, 32'b11011000101101110000111000001100, 32'b11001000100111001110001110000010, 32'b10111000100001001011111101000110, 32'b10101000011011101010000011010111, 32'b10011000010110101000011110110010, 32'b10001000010010000111001101010110, 32'b01111000001110000110001101000000, 32'b01101000001010100101011011110000, 32'b01011000000111100100110111100100, 32'b01001000000101000100011110011011, 32'b00111000000011000100001110010011, 32'b00101000000001100100000101001101, 32'b00011000000000100100000001001000, 32'b00001000000000000100000000000010, {32{1'b0}}}),
.result(wire_LogTable2_result),
.sel(A_pipe12)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable2.lpm_size = 16,
LogTable2.lpm_width = 32,
LogTable2.lpm_widths = 4,
LogTable2.lpm_type = "lpm_mux";
lpm_mux LogTable3
(
.data({29'b11101000000110100100101111111, 29'b11011000000101101100101100110, 29'b11001000000100111000101010001, 29'b10111000000100001000100111111, 29'b10101000000011011100100110000, 29'b10011000000010110100100100011, 29'b10001000000010010000100011001, 29'b01111000000001110000100010001, 29'b01101000000001010100100001011, 29'b01011000000000111100100000110, 29'b01001000000000101000100000011, 29'b00111000000000011000100000001, 29'b00101000000000001100100000000, 29'b00011000000000000100100000000, 29'b00001000000000000000100000000, {29{1'b0}}}),
.result(wire_LogTable3_result),
.sel(A_pipe13)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable3.lpm_size = 16,
LogTable3.lpm_width = 29,
LogTable3.lpm_widths = 4,
LogTable3.lpm_type = "lpm_mux";
assign
A1_is_all_zero = {(A_pipe11[3] | A1_is_all_zero[2]), (A_pipe11[2] | A1_is_all_zero[1]), (A_pipe11[1] | A1_is_all_zero[0]), A_pipe11[0]},
A1_is_not_zero = {((~ A_pipe11[3]) & A1_is_not_zero[2]), (A_pipe11[2] | A1_is_not_zero[1]), (A_pipe11[1] | A1_is_not_zero[0]), A_pipe11[0]},
A_all_zero2 = {((~ A_pipe12[3]) & A_all_zero2[2]), ((~ A_pipe12[2]) & A_all_zero2[1]), ((~ A_pipe12[1]) & A_all_zero2[0]), (~ A_pipe12[0])},
A_all_zero3 = {((~ A_pipe13[3]) & A_all_zero3[2]), ((~ A_pipe13[2]) & A_all_zero3[1]), ((~ A_pipe13[1]) & A_all_zero3[0]), (~ A_pipe13[0])},
A_pipe0 = a0_in,
A_pipe11 = A_wire1_reg0,
A_pipe12 = A_wire2_reg0,
A_pipe13 = A_wire3_reg0,
A_wire0 = A_pipe0_reg2,
A_wire1 = Z_wire1[24:21],
A_wire2 = Z_wire2[30:27],
A_wire3 = Z_wire3[28:25],
almostlog = S_wire4,
B_pad_wire1 = {1'b0, B_pipe1, {9{1'b0}}},
B_pad_wire2 = {1'b0, B_pipe2, 1'b0},
B_pad_wire3 = {1'b0, B_pipe3},
B_pipe1 = B_wire1_reg0,
B_pipe2 = B_wire2_reg0,
B_pipe3 = B_wire3_reg0,
B_wire1 = Z_wire1[20:0],
B_wire2 = Z_wire2[26:0],
B_wire3 = Z_wire3[24:0],
epsZ_pad_wire1 = epsZ_wire1[30:0],
epsZ_pad_wire2 = epsZ_wire2[39:11],
epsZ_pad_wire3 = epsZ_wire3[40:15],
epsZ_wire1 = ({31{A1_is_all_zero[3]}} & (({31{(~ A1_is_not_zero[3])}} & mux0_data0) | ({31{A1_is_not_zero[3]}} & mux0_data1))),
epsZ_wire2 = {1'b0, (~ A_all_zero2[3]), {7{1'b0}}, ({31{(~ A_all_zero2[3])}} & Z_pipe2)},
epsZ_wire3 = {1'b0, (~ A_all_zero3[3]), {10{1'b0}}, ({29{(~ A_all_zero3[3])}} & Z_pipe3)},
InvA0 = wire_InvTable0_result,
L_wire0 = wire_LogTable0_result,
L_wire1 = wire_LogTable1_result,
L_wire2 = wire_LogTable2_result,
L_wire3 = wire_LogTable3_result,
mux0_data0 = {1'b1, {4{1'b0}}, Z_pipe1, 1'b0},
mux0_data1 = {1'b0, 1'b1, {4{1'b0}}, Z_pipe1},
P_pad_wire1 = {1'b0, P_wire1, 1'b0},
P_pad_wire2 = {{4{1'b0}}, P_wire2[28:4]},
P_pad_wire3 = {{7{1'b0}}, P_wire3[22:4]},
P_pipe0 = wire_mult0_result,
P_pipe1 = wire_mult1_result,
P_pipe2 = wire_mult2_result,
P_pipe3 = wire_mult3_result,
P_wire0 = P_pipe0_reg0,
P_wire1 = P_pipe1_reg0,
P_wire2 = P_pipe2_reg0,
P_wire3 = P_pipe3_reg0,
S_pipe11 = S_wire1_reg0,
S_pipe12 = S_wire2_reg0,
S_pipe13 = S_wire3_reg0,
S_pipe22 = wire_add0_1_result,
S_pipe23 = wire_add0_2_result,
S_pipe24 = wire_add0_3_result,
S_wire1 = L_wire0,
S_wire2 = S_pipe22_reg0,
S_wire3 = S_pipe23_reg0,
S_wire4 = S_pipe24_reg0,
z = Z_wire4,
Z_pipe1 = Z_wire1_reg0,
Z_pipe2 = Z_wire2_reg0,
Z_pipe3 = Z_wire3_reg0,
Z_wire1 = P_wire0[24:0],
Z_wire2 = wire_sub1_1_result,
Z_wire3 = wire_sub1_2_result,
Z_wire4 = wire_sub1_3_result,
ZM_wire1 = Z_wire1,
ZM_wire2 = Z_wire2[30:6],
ZM_wire3 = Z_wire3[28:10];
endmodule //acl_fp_log_s5_range_reduction_0sd
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=1 WIDTH=64 WIDTHAD=6 aclr clk_en clock data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_log_s5_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_log_s5_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder14_q;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
acl_fp_log_s5_altpriority_encoder_3v7 altpriority_encoder14
(
.data(data[1:0]),
.q(wire_altpriority_encoder14_q));
acl_fp_log_s5_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[3:2]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), ((wire_altpriority_encoder15_zero & wire_altpriority_encoder14_q) | ((~ wire_altpriority_encoder15_zero) & wire_altpriority_encoder15_q))};
endmodule //acl_fp_log_s5_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
wire [0:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
acl_fp_log_s5_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[1:0]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
acl_fp_log_s5_altpriority_encoder_3e8 altpriority_encoder17
(
.data(data[3:2]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
assign
q = {(~ wire_altpriority_encoder17_zero), ((wire_altpriority_encoder17_zero & wire_altpriority_encoder16_q) | ((~ wire_altpriority_encoder17_zero) & wire_altpriority_encoder17_q))},
zero = (wire_altpriority_encoder16_zero & wire_altpriority_encoder17_zero);
endmodule //acl_fp_log_s5_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder12_q;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
acl_fp_log_s5_altpriority_encoder_6v7 altpriority_encoder12
(
.data(data[3:0]),
.q(wire_altpriority_encoder12_q));
acl_fp_log_s5_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[7:4]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), (({2{wire_altpriority_encoder13_zero}} & wire_altpriority_encoder12_q) | ({2{(~ wire_altpriority_encoder13_zero)}} & wire_altpriority_encoder13_q))};
endmodule //acl_fp_log_s5_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
wire [1:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
acl_fp_log_s5_altpriority_encoder_6e8 altpriority_encoder18
(
.data(data[3:0]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
acl_fp_log_s5_altpriority_encoder_6e8 altpriority_encoder19
(
.data(data[7:4]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
assign
q = {(~ wire_altpriority_encoder19_zero), (({2{wire_altpriority_encoder19_zero}} & wire_altpriority_encoder18_q) | ({2{(~ wire_altpriority_encoder19_zero)}} & wire_altpriority_encoder19_q))},
zero = (wire_altpriority_encoder18_zero & wire_altpriority_encoder19_zero);
endmodule //acl_fp_log_s5_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
acl_fp_log_s5_altpriority_encoder_bv7 altpriority_encoder10
(
.data(data[7:0]),
.q(wire_altpriority_encoder10_q));
acl_fp_log_s5_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[15:8]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), (({3{wire_altpriority_encoder11_zero}} & wire_altpriority_encoder10_q) | ({3{(~ wire_altpriority_encoder11_zero)}} & wire_altpriority_encoder11_q))};
endmodule //acl_fp_log_s5_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
wire [2:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
acl_fp_log_s5_altpriority_encoder_be8 altpriority_encoder20
(
.data(data[7:0]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
acl_fp_log_s5_altpriority_encoder_be8 altpriority_encoder21
(
.data(data[15:8]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero));
assign
q = {(~ wire_altpriority_encoder21_zero), (({3{wire_altpriority_encoder21_zero}} & wire_altpriority_encoder20_q) | ({3{(~ wire_altpriority_encoder21_zero)}} & wire_altpriority_encoder21_q))},
zero = (wire_altpriority_encoder20_zero & wire_altpriority_encoder21_zero);
endmodule //acl_fp_log_s5_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_tv8
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder8_q;
wire [3:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
acl_fp_log_s5_altpriority_encoder_r08 altpriority_encoder8
(
.data(data[15:0]),
.q(wire_altpriority_encoder8_q));
acl_fp_log_s5_altpriority_encoder_rf8 altpriority_encoder9
(
.data(data[31:16]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({4{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({4{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //acl_fp_log_s5_altpriority_encoder_tv8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_te9
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
acl_fp_log_s5_altpriority_encoder_rf8 altpriority_encoder22
(
.data(data[15:0]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
acl_fp_log_s5_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[31:16]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
assign
q = {(~ wire_altpriority_encoder23_zero), (({4{wire_altpriority_encoder23_zero}} & wire_altpriority_encoder22_q) | ({4{(~ wire_altpriority_encoder23_zero)}} & wire_altpriority_encoder23_q))},
zero = (wire_altpriority_encoder22_zero & wire_altpriority_encoder23_zero);
endmodule //acl_fp_log_s5_altpriority_encoder_te9
//synthesis_resources = reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_uja
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
output [5:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_altpriority_encoder6_q;
wire [4:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
reg [5:0] pipeline_q_dffe;
wire [5:0] tmp_q_wire;
acl_fp_log_s5_altpriority_encoder_tv8 altpriority_encoder6
(
.data(data[31:0]),
.q(wire_altpriority_encoder6_q));
acl_fp_log_s5_altpriority_encoder_te9 altpriority_encoder7
(
.data(data[63:32]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 6'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= tmp_q_wire;
assign
q = pipeline_q_dffe,
tmp_q_wire = {(~ wire_altpriority_encoder7_zero), (({5{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({5{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //acl_fp_log_s5_altpriority_encoder_uja
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder24_q;
wire [3:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
acl_fp_log_s5_altpriority_encoder_r08 altpriority_encoder24
(
.data(data[15:0]),
.q(wire_altpriority_encoder24_q));
acl_fp_log_s5_altpriority_encoder_rf8 altpriority_encoder25
(
.data(data[31:16]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
assign
q = {(~ wire_altpriority_encoder25_zero), (({4{wire_altpriority_encoder25_zero}} & wire_altpriority_encoder24_q) | ({4{(~ wire_altpriority_encoder25_zero)}} & wire_altpriority_encoder25_q))};
endmodule //acl_fp_log_s5_altpriority_encoder_q08
//synthesis_resources = altsquare 1 lpm_add_sub 42 lpm_mult 5 lpm_mux 5 mux21 31 reg 1563
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_altfp_log_82b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [31:0] data;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_Lshiftsmall_result;
wire [63:0] wire_lzc_norm_L_result;
wire [31:0] wire_Rshiftsmall_result;
wire wire_exp_nan_result;
wire wire_exp_zero_result;
wire wire_man_inf_result;
wire wire_man_nan_result;
wire [38:0] wire_add1_result;
wire [30:0] wire_add2_result;
wire [7:0] wire_exp_biase_sub_result;
wire [11:0] wire_sub1_result;
wire [7:0] wire_sub2_result;
wire [5:0] wire_sub3_result;
wire [25:0] wire_sub4_result;
wire [7:0] wire_sub5_result;
wire [7:0] wire_sub6_result;
wire [38:0] wire_range_reduction_almostlog;
wire [25:0] wire_range_reduction_z;
wire [5:0] wire_lzc_norm_E_q;
wire [4:0] wire_lzoc_q;
wire [13:0] wire_squarer_result;
reg [34:0] absELog2_pipe_reg0;
reg [34:0] absELog2_pipe_reg1;
reg [34:0] absELog2_pipe_reg2;
reg [11:0] absZ0_pipe_reg0;
reg [11:0] absZ0_pipe_reg1;
reg [11:0] absZ0_pipe_reg2;
reg [11:0] absZ0_pipe_reg3;
reg [11:0] absZ0_pipe_reg4;
reg [11:0] absZ0_pipe_reg5;
reg [11:0] absZ0_pipe_reg6;
reg [11:0] absZ0_pipe_reg7;
reg [11:0] absZ0_pipe_reg8;
reg [11:0] absZ0_pipe_reg9;
reg [11:0] absZ0s_pipe1_reg0;
reg [11:0] absZ0s_pipe1_reg1;
reg [11:0] absZ0s_pipe1_reg2;
reg [11:0] absZ0s_pipe1_reg3;
reg [11:0] absZ0s_reg0;
reg [38:0] almostLog_pipe_reg0;
reg [38:0] almostLog_pipe_reg1;
reg [38:0] almostLog_pipe_reg2;
reg [0:0] doRR_reg0;
reg [0:0] doRR_reg1;
reg [7:0] E0_pipe_reg0;
reg [7:0] E0_pipe_reg1;
reg [7:0] E0_pipe_reg2;
reg [7:0] E0_pipe_reg3;
reg [7:0] E0_pipe_reg4;
reg [7:0] E0_pipe_reg5;
reg [7:0] E0_pipe_reg6;
reg [7:0] E0_pipe_reg7;
reg [7:0] E0_pipe_reg8;
reg [7:0] E0_pipe_reg9;
reg [4:0] E_normal_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg1;
reg [0:0] exp_is_ebiase_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg0;
reg [0:0] input_is_infinity_pipe_reg1;
reg [0:0] input_is_infinity_pipe_reg10;
reg [0:0] input_is_infinity_pipe_reg11;
reg [0:0] input_is_infinity_pipe_reg12;
reg [0:0] input_is_infinity_pipe_reg13;
reg [0:0] input_is_infinity_pipe_reg14;
reg [0:0] input_is_infinity_pipe_reg15;
reg [0:0] input_is_infinity_pipe_reg16;
reg [0:0] input_is_infinity_pipe_reg17;
reg [0:0] input_is_infinity_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg3;
reg [0:0] input_is_infinity_pipe_reg4;
reg [0:0] input_is_infinity_pipe_reg5;
reg [0:0] input_is_infinity_pipe_reg6;
reg [0:0] input_is_infinity_pipe_reg7;
reg [0:0] input_is_infinity_pipe_reg8;
reg [0:0] input_is_infinity_pipe_reg9;
reg [0:0] input_is_nan_pipe_reg0;
reg [0:0] input_is_nan_pipe_reg1;
reg [0:0] input_is_nan_pipe_reg10;
reg [0:0] input_is_nan_pipe_reg11;
reg [0:0] input_is_nan_pipe_reg12;
reg [0:0] input_is_nan_pipe_reg13;
reg [0:0] input_is_nan_pipe_reg14;
reg [0:0] input_is_nan_pipe_reg15;
reg [0:0] input_is_nan_pipe_reg16;
reg [0:0] input_is_nan_pipe_reg17;
reg [0:0] input_is_nan_pipe_reg2;
reg [0:0] input_is_nan_pipe_reg3;
reg [0:0] input_is_nan_pipe_reg4;
reg [0:0] input_is_nan_pipe_reg5;
reg [0:0] input_is_nan_pipe_reg6;
reg [0:0] input_is_nan_pipe_reg7;
reg [0:0] input_is_nan_pipe_reg8;
reg [0:0] input_is_nan_pipe_reg9;
reg [0:0] input_is_one_pipe_reg0;
reg [0:0] input_is_one_pipe_reg1;
reg [0:0] input_is_one_pipe_reg10;
reg [0:0] input_is_one_pipe_reg11;
reg [0:0] input_is_one_pipe_reg12;
reg [0:0] input_is_one_pipe_reg13;
reg [0:0] input_is_one_pipe_reg14;
reg [0:0] input_is_one_pipe_reg15;
reg [0:0] input_is_one_pipe_reg16;
reg [0:0] input_is_one_pipe_reg17;
reg [0:0] input_is_one_pipe_reg2;
reg [0:0] input_is_one_pipe_reg3;
reg [0:0] input_is_one_pipe_reg4;
reg [0:0] input_is_one_pipe_reg5;
reg [0:0] input_is_one_pipe_reg6;
reg [0:0] input_is_one_pipe_reg7;
reg [0:0] input_is_one_pipe_reg8;
reg [0:0] input_is_one_pipe_reg9;
reg [0:0] input_is_zero_pipe_reg0;
reg [0:0] input_is_zero_pipe_reg1;
reg [0:0] input_is_zero_pipe_reg10;
reg [0:0] input_is_zero_pipe_reg11;
reg [0:0] input_is_zero_pipe_reg12;
reg [0:0] input_is_zero_pipe_reg13;
reg [0:0] input_is_zero_pipe_reg14;
reg [0:0] input_is_zero_pipe_reg15;
reg [0:0] input_is_zero_pipe_reg16;
reg [0:0] input_is_zero_pipe_reg17;
reg [0:0] input_is_zero_pipe_reg2;
reg [0:0] input_is_zero_pipe_reg3;
reg [0:0] input_is_zero_pipe_reg4;
reg [0:0] input_is_zero_pipe_reg5;
reg [0:0] input_is_zero_pipe_reg6;
reg [0:0] input_is_zero_pipe_reg7;
reg [0:0] input_is_zero_pipe_reg8;
reg [0:0] input_is_zero_pipe_reg9;
reg [46:0] Log_normal_normd_pipe_reg0;
reg [46:0] Log_normal_reg0;
reg [26:0] Log_small_normd_pipe_reg0;
reg [26:0] Log_small_normd_pipe_reg1;
reg [5:0] Lshiftval_reg0;
reg [5:0] Lshiftval_reg1;
reg [5:0] Lshiftval_reg2;
reg [5:0] Lshiftval_reg3;
reg [4:0] lzo_pipe1_reg0;
reg [4:0] lzo_pipe1_reg1;
reg [4:0] lzo_pipe1_reg2;
reg [4:0] lzo_pipe1_reg3;
reg [4:0] lzo_pipe1_reg4;
reg [4:0] lzo_pipe1_reg5;
reg [4:0] lzo_pipe1_reg6;
reg [4:0] lzo_pipe1_reg7;
reg [4:0] lzo_pipe1_reg8;
reg [4:0] lzo_pipe1_reg9;
reg [4:0] lzo_reg0;
reg [4:0] lzo_reg1;
reg [4:0] lzo_reg2;
reg [4:0] lzo_reg3;
reg [4:0] lzo_reg4;
reg [4:0] lzo_reg5;
reg [4:0] lzo_reg6;
reg [4:0] lzo_reg7;
reg [0:0] sign_data_reg0;
reg [0:0] sign_data_reg1;
reg [0:0] sign_data_reg2;
reg [0:0] small_flag_pipe_reg0;
reg [0:0] small_flag_pipe_reg1;
reg [0:0] small_flag_pipe_reg2;
reg [0:0] small_flag_pipe_reg3;
reg [0:0] small_flag_pipe_reg4;
reg [0:0] small_flag_pipe_reg5;
reg [0:0] small_flag_pipe_reg6;
reg [0:0] small_flag_pipe_reg7;
reg [0:0] small_flag_pipe_reg8;
reg [0:0] small_flag_pipe_reg9;
reg [0:0] sR_pipe1_reg0;
reg [0:0] sR_pipe1_reg1;
reg [0:0] sR_pipe1_reg2;
reg [0:0] sR_pipe1_reg3;
reg [0:0] sR_pipe1_reg4;
reg [0:0] sR_pipe1_reg5;
reg [0:0] sR_pipe1_reg6;
reg [0:0] sR_pipe1_reg7;
reg [0:0] sR_pipe1_reg8;
reg [0:0] sR_pipe1_reg9;
reg [0:0] sR_pipe2_reg0;
reg [0:0] sR_pipe2_reg1;
reg [0:0] sR_pipe2_reg2;
reg [0:0] sR_pipe2_reg3;
reg [0:0] sR_pipe2_reg4;
reg [0:0] sR_pipe2_reg5;
reg [0:0] sR_pipe3_reg0;
reg [0:0] sR_pipe3_reg1;
reg [0:0] sR_pipe3_reg2;
reg [0:0] sR_pipe3_reg3;
reg [0:0] sR_pipe3_reg4;
reg [13:0] Z2o2_pipe_reg0;
reg [13:0] Z2o2_small_s_pipe_reg0;
reg [25:0] Zfinal_reg0;
reg [25:0] Zfinal_reg1;
wire [28:0] wire_addsub1_result;
wire [46:0] wire_addsub2_result;
wire [34:0] wire_mult1_result;
wire [30:0]wire_mux_result0a_dataout;
wire [7:0] absE;
wire [34:0] absELog2;
wire [46:0] absELog2_pad;
wire [34:0] absELog2_pipe;
wire [11:0] absZ0;
wire [11:0] absZ0_pipe;
wire [11:0] absZ0s;
wire [11:0] absZ0s_pipe1;
wire [11:0] absZ0s_pipe2;
wire aclr;
wire [38:0] almostLog;
wire [38:0] almostLog_pipe;
wire [7:0] data_exp_is_ebiase;
wire doRR;
wire doRR_pipe;
wire [7:0] E0;
wire [7:0] E0_is_zero;
wire [7:0] E0_pipe;
wire [1:0] E0_sub;
wire [7:0] E0offset;
wire [4:0] E_normal;
wire [4:0] E_normal_pipe;
wire [7:0] E_small;
wire [30:0] EFR;
wire [7:0] ER;
wire exp_all_one;
wire exp_all_zero;
wire [7:0] exp_biase;
wire [7:0] exp_data;
wire exp_is_ebiase;
wire exp_is_ebiase_pipe;
wire First_bit;
wire input_is_infinity;
wire input_is_infinity_pipe;
wire input_is_nan;
wire input_is_nan_pipe;
wire input_is_one;
wire input_is_one_pipe;
wire input_is_zero;
wire input_is_zero_pipe;
wire [25:0] Log1p_normal;
wire [26:0] Log2;
wire [26:0] Log_g;
wire [46:0] Log_normal;
wire [46:0] Log_normal_normd;
wire [46:0] Log_normal_normd_pipe;
wire [46:0] Log_normal_pipe;
wire [28:0] Log_small;
wire [26:0] Log_small1;
wire [26:0] Log_small2;
wire [26:0] Log_small_normd;
wire [26:0] Log_small_normd_pipe;
wire [38:0] LogF_normal;
wire [46:0] LogF_normal_pad;
wire [5:0] Lshiftval;
wire [4:0] lzo;
wire [4:0] lzo_pipe1;
wire [4:0] lzo_pipe2;
wire [24:0] man_above_half;
wire man_all_zero;
wire [24:0] man_below_half;
wire [22:0] man_data;
wire man_not_zero;
wire [4:0] pfinal_s;
wire round;
wire [5:0] Rshiftval;
wire sign_data;
wire sign_data_pipe;
wire small_flag;
wire small_flag_pipe;
wire [12:0] squarerIn;
wire [12:0] squarerIn0;
wire [12:0] squarerIn1;
wire sR;
wire sR_pipe1;
wire sR_pipe2;
wire sR_pipe3;
wire [2:0] sticky;
wire [24:0] Y0;
wire [13:0] Z2o2;
wire [13:0] Z2o2_pipe;
wire [28:0] Z2o2_small;
wire [13:0] Z2o2_small_s;
wire [13:0] Z2o2_small_s_pipe;
wire [28:0] Z_small;
wire [25:0] Zfinal;
wire [25:0] Zfinal_pipe;
acl_fp_log_s5_altbarrel_shift_kud Lshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({absZ0, {20{1'b0}}}),
.distance(Lshiftval[4:0]),
.result(wire_Lshiftsmall_result));
acl_fp_log_s5_altbarrel_shift_sbb lzc_norm_L
(
.data({Log_normal_pipe, {17{1'b0}}}),
.distance((~ wire_lzc_norm_E_q)),
.result(wire_lzc_norm_L_result));
acl_fp_log_s5_altbarrel_shift_72e Rshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Z2o2, {18{1'b0}}}),
.distance(Rshiftval[4:0]),
.result(wire_Rshiftsmall_result));
acl_fp_log_s5_altfp_log_and_or_h9b exp_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_nan_result));
acl_fp_log_s5_altfp_log_and_or_v6b exp_zero
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_zero_result));
acl_fp_log_s5_altfp_log_and_or_c8b man_inf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_inf_result));
acl_fp_log_s5_altfp_log_and_or_c8b man_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_nan_result));
acl_fp_log_s5_altfp_log_csa_s0e add1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({{13{1'b0}}, Log1p_normal}),
.datab(almostLog),
.result(wire_add1_result));
acl_fp_log_s5_altfp_log_csa_k0e add2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({ER, Log_g[26:4]}),
.datab({{30{1'b0}}, round}),
.result(wire_add2_result));
acl_fp_log_s5_altfp_log_csa_0nc exp_biase_sub
(
.dataa(exp_data),
.datab(exp_biase),
.result(wire_exp_biase_sub_result));
acl_fp_log_s5_altfp_log_csa_d4b sub1
(
.dataa({12{1'b0}}),
.datab(Y0[11:0]),
.result(wire_sub1_result));
acl_fp_log_s5_altfp_log_csa_0nc sub2
(
.dataa({8{1'b0}}),
.datab(E0),
.result(wire_sub2_result));
acl_fp_log_s5_altfp_log_csa_umc sub3
(
.dataa({1'b0, lzo}),
.datab({1'b0, pfinal_s}),
.result(wire_sub3_result));
acl_fp_log_s5_altfp_log_csa_nlf sub4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(Zfinal_pipe),
.datab({{14{1'b0}}, Z2o2[13:2]}),
.result(wire_sub4_result));
acl_fp_log_s5_altfp_log_csa_8kf sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b0, {5{1'b1}}, E0_sub}),
.datab({{3{1'b0}}, lzo_pipe2}),
.result(wire_sub5_result));
acl_fp_log_s5_altfp_log_csa_0nc sub6
(
.dataa(E0offset),
.datab({{3{1'b0}}, (~ E_normal)}),
.result(wire_sub6_result));
acl_fp_log_s5_range_reduction_0sd range_reduction
(
.a0_in(man_data[22:18]),
.aclr(aclr),
.almostlog(wire_range_reduction_almostlog),
.clk_en(clk_en),
.clock(clock),
.y0_in(Y0),
.z(wire_range_reduction_z));
acl_fp_log_s5_altpriority_encoder_uja lzc_norm_E
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Log_normal, 17'b00000000000000001}),
.q(wire_lzc_norm_E_q));
acl_fp_log_s5_altpriority_encoder_q08 lzoc
(
.data({({23{First_bit}} ^ Y0[23:1]), 9'b000000001}),
.q(wire_lzoc_q));
altsquare squarer
(
.aclr(aclr),
.clock(clock),
.data(squarerIn),
.ena(clk_en),
.result(wire_squarer_result));
defparam
squarer.data_width = 13,
squarer.pipeline = 1,
squarer.representation = "UNSIGNED",
squarer.result_alignment = "MSB",
squarer.result_width = 14,
squarer.lpm_type = "altsquare";
// synopsys translate_off
initial
absELog2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg0 <= 35'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg0 <= absELog2_pipe;
// synopsys translate_off
initial
absELog2_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg1 <= 35'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg1 <= absELog2_pipe_reg0;
// synopsys translate_off
initial
absELog2_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg2 <= 35'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg2 <= absELog2_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg0 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg0 <= absZ0_pipe;
// synopsys translate_off
initial
absZ0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg1 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg1 <= absZ0_pipe_reg0;
// synopsys translate_off
initial
absZ0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg2 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg2 <= absZ0_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg3 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg3 <= absZ0_pipe_reg2;
// synopsys translate_off
initial
absZ0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg4 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg4 <= absZ0_pipe_reg3;
// synopsys translate_off
initial
absZ0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg5 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg5 <= absZ0_pipe_reg4;
// synopsys translate_off
initial
absZ0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg6 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg6 <= absZ0_pipe_reg5;
// synopsys translate_off
initial
absZ0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg7 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg7 <= absZ0_pipe_reg6;
// synopsys translate_off
initial
absZ0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg8 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg8 <= absZ0_pipe_reg7;
// synopsys translate_off
initial
absZ0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg9 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg9 <= absZ0_pipe_reg8;
// synopsys translate_off
initial
absZ0s_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg0 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg0 <= absZ0s_pipe1;
// synopsys translate_off
initial
absZ0s_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg1 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg1 <= absZ0s_pipe1_reg0;
// synopsys translate_off
initial
absZ0s_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg2 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg2 <= absZ0s_pipe1_reg1;
// synopsys translate_off
initial
absZ0s_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg3 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg3 <= absZ0s_pipe1_reg2;
// synopsys translate_off
initial
absZ0s_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_reg0 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_reg0 <= absZ0s;
// synopsys translate_off
initial
almostLog_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg0 <= 39'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg0 <= almostLog_pipe;
// synopsys translate_off
initial
almostLog_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg1 <= 39'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg1 <= almostLog_pipe_reg0;
// synopsys translate_off
initial
almostLog_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg2 <= 39'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg2 <= almostLog_pipe_reg1;
// synopsys translate_off
initial
doRR_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg0 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg0 <= doRR;
// synopsys translate_off
initial
doRR_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg1 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg1 <= doRR_reg0;
// synopsys translate_off
initial
E0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg0 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg0 <= E0_pipe;
// synopsys translate_off
initial
E0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg1 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg1 <= E0_pipe_reg0;
// synopsys translate_off
initial
E0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg2 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg2 <= E0_pipe_reg1;
// synopsys translate_off
initial
E0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg3 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg3 <= E0_pipe_reg2;
// synopsys translate_off
initial
E0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg4 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg4 <= E0_pipe_reg3;
// synopsys translate_off
initial
E0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg5 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg5 <= E0_pipe_reg4;
// synopsys translate_off
initial
E0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg6 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg6 <= E0_pipe_reg5;
// synopsys translate_off
initial
E0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg7 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg7 <= E0_pipe_reg6;
// synopsys translate_off
initial
E0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg8 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg8 <= E0_pipe_reg7;
// synopsys translate_off
initial
E0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg9 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg9 <= E0_pipe_reg8;
// synopsys translate_off
initial
E_normal_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E_normal_pipe_reg0 <= 5'b0;
else if (clk_en == 1'b1) E_normal_pipe_reg0 <= E_normal_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg0 <= exp_is_ebiase_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg1 <= exp_is_ebiase_pipe_reg0;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg2 <= exp_is_ebiase_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg0 <= input_is_infinity_pipe;
// synopsys translate_off
initial
input_is_infinity_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg1 <= input_is_infinity_pipe_reg0;
// synopsys translate_off
initial
input_is_infinity_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg10 <= input_is_infinity_pipe_reg9;
// synopsys translate_off
initial
input_is_infinity_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg11 <= input_is_infinity_pipe_reg10;
// synopsys translate_off
initial
input_is_infinity_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg12 <= input_is_infinity_pipe_reg11;
// synopsys translate_off
initial
input_is_infinity_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg13 <= input_is_infinity_pipe_reg12;
// synopsys translate_off
initial
input_is_infinity_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg14 <= input_is_infinity_pipe_reg13;
// synopsys translate_off
initial
input_is_infinity_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg15 <= input_is_infinity_pipe_reg14;
// synopsys translate_off
initial
input_is_infinity_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg16 <= input_is_infinity_pipe_reg15;
// synopsys translate_off
initial
input_is_infinity_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg17 <= input_is_infinity_pipe_reg16;
// synopsys translate_off
initial
input_is_infinity_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg2 <= input_is_infinity_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg3 <= input_is_infinity_pipe_reg2;
// synopsys translate_off
initial
input_is_infinity_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg4 <= input_is_infinity_pipe_reg3;
// synopsys translate_off
initial
input_is_infinity_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg5 <= input_is_infinity_pipe_reg4;
// synopsys translate_off
initial
input_is_infinity_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg6 <= input_is_infinity_pipe_reg5;
// synopsys translate_off
initial
input_is_infinity_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg7 <= input_is_infinity_pipe_reg6;
// synopsys translate_off
initial
input_is_infinity_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg8 <= input_is_infinity_pipe_reg7;
// synopsys translate_off
initial
input_is_infinity_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg9 <= input_is_infinity_pipe_reg8;
// synopsys translate_off
initial
input_is_nan_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg0 <= input_is_nan_pipe;
// synopsys translate_off
initial
input_is_nan_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg1 <= input_is_nan_pipe_reg0;
// synopsys translate_off
initial
input_is_nan_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg10 <= input_is_nan_pipe_reg9;
// synopsys translate_off
initial
input_is_nan_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg11 <= input_is_nan_pipe_reg10;
// synopsys translate_off
initial
input_is_nan_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg12 <= input_is_nan_pipe_reg11;
// synopsys translate_off
initial
input_is_nan_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg13 <= input_is_nan_pipe_reg12;
// synopsys translate_off
initial
input_is_nan_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg14 <= input_is_nan_pipe_reg13;
// synopsys translate_off
initial
input_is_nan_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg15 <= input_is_nan_pipe_reg14;
// synopsys translate_off
initial
input_is_nan_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg16 <= input_is_nan_pipe_reg15;
// synopsys translate_off
initial
input_is_nan_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg17 <= input_is_nan_pipe_reg16;
// synopsys translate_off
initial
input_is_nan_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg2 <= input_is_nan_pipe_reg1;
// synopsys translate_off
initial
input_is_nan_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg3 <= input_is_nan_pipe_reg2;
// synopsys translate_off
initial
input_is_nan_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg4 <= input_is_nan_pipe_reg3;
// synopsys translate_off
initial
input_is_nan_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg5 <= input_is_nan_pipe_reg4;
// synopsys translate_off
initial
input_is_nan_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg6 <= input_is_nan_pipe_reg5;
// synopsys translate_off
initial
input_is_nan_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg7 <= input_is_nan_pipe_reg6;
// synopsys translate_off
initial
input_is_nan_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg8 <= input_is_nan_pipe_reg7;
// synopsys translate_off
initial
input_is_nan_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg9 <= input_is_nan_pipe_reg8;
// synopsys translate_off
initial
input_is_one_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg0 <= input_is_one_pipe;
// synopsys translate_off
initial
input_is_one_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg1 <= input_is_one_pipe_reg0;
// synopsys translate_off
initial
input_is_one_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg10 <= input_is_one_pipe_reg9;
// synopsys translate_off
initial
input_is_one_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg11 <= input_is_one_pipe_reg10;
// synopsys translate_off
initial
input_is_one_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg12 <= input_is_one_pipe_reg11;
// synopsys translate_off
initial
input_is_one_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg13 <= input_is_one_pipe_reg12;
// synopsys translate_off
initial
input_is_one_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg14 <= input_is_one_pipe_reg13;
// synopsys translate_off
initial
input_is_one_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg15 <= input_is_one_pipe_reg14;
// synopsys translate_off
initial
input_is_one_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg16 <= input_is_one_pipe_reg15;
// synopsys translate_off
initial
input_is_one_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg17 <= input_is_one_pipe_reg16;
// synopsys translate_off
initial
input_is_one_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg2 <= input_is_one_pipe_reg1;
// synopsys translate_off
initial
input_is_one_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg3 <= input_is_one_pipe_reg2;
// synopsys translate_off
initial
input_is_one_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg4 <= input_is_one_pipe_reg3;
// synopsys translate_off
initial
input_is_one_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg5 <= input_is_one_pipe_reg4;
// synopsys translate_off
initial
input_is_one_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg6 <= input_is_one_pipe_reg5;
// synopsys translate_off
initial
input_is_one_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg7 <= input_is_one_pipe_reg6;
// synopsys translate_off
initial
input_is_one_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg8 <= input_is_one_pipe_reg7;
// synopsys translate_off
initial
input_is_one_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg9 <= input_is_one_pipe_reg8;
// synopsys translate_off
initial
input_is_zero_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg0 <= input_is_zero_pipe;
// synopsys translate_off
initial
input_is_zero_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg1 <= input_is_zero_pipe_reg0;
// synopsys translate_off
initial
input_is_zero_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg10 <= input_is_zero_pipe_reg9;
// synopsys translate_off
initial
input_is_zero_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg11 <= input_is_zero_pipe_reg10;
// synopsys translate_off
initial
input_is_zero_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg12 <= input_is_zero_pipe_reg11;
// synopsys translate_off
initial
input_is_zero_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg13 <= input_is_zero_pipe_reg12;
// synopsys translate_off
initial
input_is_zero_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg14 <= input_is_zero_pipe_reg13;
// synopsys translate_off
initial
input_is_zero_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg15 <= input_is_zero_pipe_reg14;
// synopsys translate_off
initial
input_is_zero_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg16 <= input_is_zero_pipe_reg15;
// synopsys translate_off
initial
input_is_zero_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg17 <= input_is_zero_pipe_reg16;
// synopsys translate_off
initial
input_is_zero_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg2 <= input_is_zero_pipe_reg1;
// synopsys translate_off
initial
input_is_zero_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg3 <= input_is_zero_pipe_reg2;
// synopsys translate_off
initial
input_is_zero_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg4 <= input_is_zero_pipe_reg3;
// synopsys translate_off
initial
input_is_zero_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg5 <= input_is_zero_pipe_reg4;
// synopsys translate_off
initial
input_is_zero_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg6 <= input_is_zero_pipe_reg5;
// synopsys translate_off
initial
input_is_zero_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg7 <= input_is_zero_pipe_reg6;
// synopsys translate_off
initial
input_is_zero_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg8 <= input_is_zero_pipe_reg7;
// synopsys translate_off
initial
input_is_zero_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg9 <= input_is_zero_pipe_reg8;
// synopsys translate_off
initial
Log_normal_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_normd_pipe_reg0 <= 47'b0;
else if (clk_en == 1'b1) Log_normal_normd_pipe_reg0 <= Log_normal_normd_pipe;
// synopsys translate_off
initial
Log_normal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_reg0 <= 47'b0;
else if (clk_en == 1'b1) Log_normal_reg0 <= Log_normal;
// synopsys translate_off
initial
Log_small_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg0 <= 27'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg0 <= Log_small_normd_pipe;
// synopsys translate_off
initial
Log_small_normd_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg1 <= 27'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg1 <= Log_small_normd_pipe_reg0;
// synopsys translate_off
initial
Lshiftval_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg0 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg0 <= Lshiftval;
// synopsys translate_off
initial
Lshiftval_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg1 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg1 <= Lshiftval_reg0;
// synopsys translate_off
initial
Lshiftval_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg2 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg2 <= Lshiftval_reg1;
// synopsys translate_off
initial
Lshiftval_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg3 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg3 <= Lshiftval_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg0 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg0 <= lzo_pipe1;
// synopsys translate_off
initial
lzo_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg1 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg1 <= lzo_pipe1_reg0;
// synopsys translate_off
initial
lzo_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg2 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg2 <= lzo_pipe1_reg1;
// synopsys translate_off
initial
lzo_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg3 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg3 <= lzo_pipe1_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg4 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg4 <= lzo_pipe1_reg3;
// synopsys translate_off
initial
lzo_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg5 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg5 <= lzo_pipe1_reg4;
// synopsys translate_off
initial
lzo_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg6 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg6 <= lzo_pipe1_reg5;
// synopsys translate_off
initial
lzo_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg7 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg7 <= lzo_pipe1_reg6;
// synopsys translate_off
initial
lzo_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg8 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg8 <= lzo_pipe1_reg7;
// synopsys translate_off
initial
lzo_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg9 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg9 <= lzo_pipe1_reg8;
// synopsys translate_off
initial
lzo_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg0 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg0 <= lzo;
// synopsys translate_off
initial
lzo_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg1 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg1 <= lzo_reg0;
// synopsys translate_off
initial
lzo_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg2 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg2 <= lzo_reg1;
// synopsys translate_off
initial
lzo_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg3 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg3 <= lzo_reg2;
// synopsys translate_off
initial
lzo_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg4 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg4 <= lzo_reg3;
// synopsys translate_off
initial
lzo_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg5 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg5 <= lzo_reg4;
// synopsys translate_off
initial
lzo_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg6 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg6 <= lzo_reg5;
// synopsys translate_off
initial
lzo_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg7 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg7 <= lzo_reg6;
// synopsys translate_off
initial
sign_data_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg0 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg0 <= sign_data;
// synopsys translate_off
initial
sign_data_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg1 <= sign_data_reg0;
// synopsys translate_off
initial
sign_data_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg2 <= sign_data_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg0 <= small_flag_pipe;
// synopsys translate_off
initial
small_flag_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg1 <= small_flag_pipe_reg0;
// synopsys translate_off
initial
small_flag_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg2 <= small_flag_pipe_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg3 <= small_flag_pipe_reg2;
// synopsys translate_off
initial
small_flag_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg4 <= small_flag_pipe_reg3;
// synopsys translate_off
initial
small_flag_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg5 <= small_flag_pipe_reg4;
// synopsys translate_off
initial
small_flag_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg6 <= small_flag_pipe_reg5;
// synopsys translate_off
initial
small_flag_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg7 <= small_flag_pipe_reg6;
// synopsys translate_off
initial
small_flag_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg8 <= small_flag_pipe_reg7;
// synopsys translate_off
initial
small_flag_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg9 <= small_flag_pipe_reg8;
// synopsys translate_off
initial
sR_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg0 <= sR_pipe1;
// synopsys translate_off
initial
sR_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg1 <= sR_pipe1_reg0;
// synopsys translate_off
initial
sR_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg2 <= sR_pipe1_reg1;
// synopsys translate_off
initial
sR_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg3 <= sR_pipe1_reg2;
// synopsys translate_off
initial
sR_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg4 <= sR_pipe1_reg3;
// synopsys translate_off
initial
sR_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg5 <= sR_pipe1_reg4;
// synopsys translate_off
initial
sR_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg6 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg6 <= sR_pipe1_reg5;
// synopsys translate_off
initial
sR_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg7 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg7 <= sR_pipe1_reg6;
// synopsys translate_off
initial
sR_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg8 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg8 <= sR_pipe1_reg7;
// synopsys translate_off
initial
sR_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg9 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg9 <= sR_pipe1_reg8;
// synopsys translate_off
initial
sR_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg0 <= sR_pipe2;
// synopsys translate_off
initial
sR_pipe2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg1 <= sR_pipe2_reg0;
// synopsys translate_off
initial
sR_pipe2_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg2 <= sR_pipe2_reg1;
// synopsys translate_off
initial
sR_pipe2_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg3 <= sR_pipe2_reg2;
// synopsys translate_off
initial
sR_pipe2_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg4 <= sR_pipe2_reg3;
// synopsys translate_off
initial
sR_pipe2_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg5 <= sR_pipe2_reg4;
// synopsys translate_off
initial
sR_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg0 <= sR_pipe3;
// synopsys translate_off
initial
sR_pipe3_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg1 <= sR_pipe3_reg0;
// synopsys translate_off
initial
sR_pipe3_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg2 <= sR_pipe3_reg1;
// synopsys translate_off
initial
sR_pipe3_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg3 <= sR_pipe3_reg2;
// synopsys translate_off
initial
sR_pipe3_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg4 <= sR_pipe3_reg3;
// synopsys translate_off
initial
Z2o2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_pipe_reg0 <= 14'b0;
else if (clk_en == 1'b1) Z2o2_pipe_reg0 <= Z2o2_pipe;
// synopsys translate_off
initial
Z2o2_small_s_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_small_s_pipe_reg0 <= 14'b0;
else if (clk_en == 1'b1) Z2o2_small_s_pipe_reg0 <= Z2o2_small_s_pipe;
// synopsys translate_off
initial
Zfinal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg0 <= 26'b0;
else if (clk_en == 1'b1) Zfinal_reg0 <= Zfinal;
// synopsys translate_off
initial
Zfinal_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg1 <= 26'b0;
else if (clk_en == 1'b1) Zfinal_reg1 <= Zfinal_reg0;
lpm_add_sub addsub1
(
.add_sub(sR_pipe3),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(Z_small),
.datab(Z2o2_small),
.overflow(),
.result(wire_addsub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub1.lpm_pipeline = 2,
addsub1.lpm_representation = "UNSIGNED",
addsub1.lpm_width = 29,
addsub1.lpm_type = "lpm_add_sub";
lpm_add_sub addsub2
(
.add_sub((~ sR_pipe3)),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(absELog2_pad),
.datab(LogF_normal_pad),
.overflow(),
.result(wire_addsub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub2.lpm_pipeline = 2,
addsub2.lpm_representation = "UNSIGNED",
addsub2.lpm_width = 47,
addsub2.lpm_type = "lpm_add_sub";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(absE),
.datab(Log2),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 3,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 8,
mult1.lpm_widthb = 27,
mult1.lpm_widthp = 35,
mult1.lpm_type = "lpm_mult";
assign wire_mux_result0a_dataout = ((((input_is_zero | input_is_infinity) | input_is_nan) | input_is_one) === 1'b1) ? {{8{((~ input_is_one) | input_is_nan)}}, input_is_nan, {22{1'b0}}} : EFR;
assign
absE = (({8{(~ sR_pipe2)}} & E0) | ({8{sR_pipe2}} & wire_sub2_result)),
absELog2 = absELog2_pipe_reg2,
absELog2_pad = {absELog2, {12{1'b0}}},
absELog2_pipe = wire_mult1_result,
absZ0 = absZ0_pipe_reg9,
absZ0_pipe = (({12{(~ sR_pipe1)}} & Y0[11:0]) | ({12{sR_pipe1}} & wire_sub1_result)),
absZ0s = wire_Lshiftsmall_result[31:20],
absZ0s_pipe1 = absZ0s_reg0,
absZ0s_pipe2 = absZ0s_pipe1_reg3,
aclr = 1'b0,
almostLog = almostLog_pipe_reg2,
almostLog_pipe = wire_range_reduction_almostlog,
data_exp_is_ebiase = {((~ exp_data[7]) & data_exp_is_ebiase[6]), (exp_data[6] & data_exp_is_ebiase[5]), (exp_data[5] & data_exp_is_ebiase[4]), (exp_data[4] & data_exp_is_ebiase[3]), (exp_data[3] & data_exp_is_ebiase[2]), (exp_data[2] & data_exp_is_ebiase[1]), (exp_data[1] & data_exp_is_ebiase[0]), exp_data[0]},
doRR = Lshiftval[5],
doRR_pipe = doRR_reg1,
E0 = E0_pipe_reg9,
E0_is_zero = {((~ E0[7]) & E0_is_zero[6]), ((~ E0[6]) & E0_is_zero[5]), ((~ E0[5]) & E0_is_zero[4]), ((~ E0[4]) & E0_is_zero[3]), ((~ E0[3]) & E0_is_zero[2]), ((~ E0[2]) & E0_is_zero[1]), ((~ E0[1]) & E0_is_zero[0]), (~ E0[0])},
E0_pipe = wire_exp_biase_sub_result,
E0_sub = {(Log_small[28] | Log_small[27]), (Log_small[28] | (~ Log_small[27]))},
E0offset = 8'b10000110,
E_normal = E_normal_pipe_reg0,
E_normal_pipe = wire_lzc_norm_E_q[4:0],
E_small = wire_sub5_result,
EFR = wire_add2_result,
ER = (({8{(~ small_flag)}} & wire_sub6_result) | ({8{small_flag}} & E_small)),
exp_all_one = wire_exp_nan_result,
exp_all_zero = wire_exp_zero_result,
exp_biase = {7'b0111111, (~ First_bit)},
exp_data = data[30:23],
exp_is_ebiase = exp_is_ebiase_pipe_reg2,
exp_is_ebiase_pipe = data_exp_is_ebiase[7],
First_bit = man_data[22],
input_is_infinity = input_is_infinity_pipe_reg17,
input_is_infinity_pipe = (exp_all_one & (~ man_all_zero)),
input_is_nan = input_is_nan_pipe_reg17,
input_is_nan_pipe = ((exp_all_one & man_not_zero) | sign_data_pipe),
input_is_one = input_is_one_pipe_reg17,
input_is_one_pipe = (exp_is_ebiase & (~ man_all_zero)),
input_is_zero = input_is_zero_pipe_reg17,
input_is_zero_pipe = (~ exp_all_zero),
Log1p_normal = wire_sub4_result,
Log2 = 27'b101100010111001000011000000,
Log_g = (({27{(~ small_flag)}} & Log_normal_normd[45:19]) | ({27{small_flag}} & {Log_small_normd[25:0], 1'b0})),
Log_normal = wire_addsub2_result,
Log_normal_normd = Log_normal_normd_pipe_reg0,
Log_normal_normd_pipe = wire_lzc_norm_L_result[63:17],
Log_normal_pipe = Log_normal_reg0,
Log_small = wire_addsub1_result,
Log_small1 = (({27{(~ Log_small[27])}} & Log_small[26:0]) | ({27{Log_small[27]}} & Log_small[27:1])),
Log_small2 = (({27{(~ Log_small[28])}} & Log_small1) | ({27{Log_small[28]}} & Log_small[28:2])),
Log_small_normd = Log_small_normd_pipe_reg1,
Log_small_normd_pipe = Log_small2,
LogF_normal = wire_add1_result,
LogF_normal_pad = {{8{LogF_normal[38]}}, LogF_normal},
Lshiftval = wire_sub3_result,
lzo = lzo_pipe1_reg9,
lzo_pipe1 = (~ wire_lzoc_q),
lzo_pipe2 = lzo_reg7,
man_above_half = {1'b0, 1'b1, man_data},
man_all_zero = wire_man_inf_result,
man_below_half = {1'b1, man_data, 1'b0},
man_data = data[22:0],
man_not_zero = wire_man_nan_result,
pfinal_s = 5'b01101,
result = {(((sR | input_is_zero) | input_is_nan) & (~ input_is_one)), wire_mux_result0a_dataout},
round = (Log_g[3] & (Log_g[4] | sticky[2])),
Rshiftval = Lshiftval_reg3,
sign_data = data[31],
sign_data_pipe = sign_data_reg2,
small_flag = small_flag_pipe_reg9,
small_flag_pipe = ((~ doRR) & E0_is_zero[7]),
squarerIn = (({13{(~ doRR_pipe)}} & squarerIn0) | ({13{doRR_pipe}} & squarerIn1)),
squarerIn0 = {absZ0s_pipe1, 1'b0},
squarerIn1 = Zfinal[25:13],
sR = sR_pipe3_reg4,
sR_pipe1 = (~ (data_exp_is_ebiase[7] | exp_data[7])),
sR_pipe2 = sR_pipe1_reg9,
sR_pipe3 = sR_pipe2_reg5,
sticky = {(Log_g[2] | sticky[1]), (Log_g[1] | sticky[0]), Log_g[0]},
Y0 = (({25{(~ First_bit)}} & man_below_half) | ({25{First_bit}} & man_above_half)),
Z2o2 = Z2o2_pipe_reg0,
Z2o2_pipe = wire_squarer_result,
Z2o2_small = {{13{1'b0}}, Z2o2_small_s, {2{1'b0}}},
Z2o2_small_s = Z2o2_small_s_pipe_reg0,
Z2o2_small_s_pipe = wire_Rshiftsmall_result[31:18],
Z_small = {absZ0s_pipe2, {17{1'b0}}},
Zfinal = wire_range_reduction_z,
Zfinal_pipe = Zfinal_reg1;
endmodule //acl_fp_log_s5_altfp_log_82b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_log_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_log_s5_altfp_log_82b acl_fp_log_s5_altfp_log_82b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_log"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "21"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_gtx_es_wr (
// synchronous to the processor clock
up_rstn,
up_clk,
up_startaddr,
up_hsize,
up_hmin,
up_hmax,
// es interface, data is 64bits with valid as the qualifier
es_valid,
es_sos,
es_eos,
es_data,
// master interface and status signals
mb_req,
mb_ack,
mb_addr,
mb_data,
mb_done,
mb_error,
mb_readyn,
mb_ovf,
mb_unf,
mb_state,
mb_status,
// master debug data (for chipscope)
mb_dbg_data,
mb_dbg_trigger);
// synchronous to the processor clock
input up_rstn;
input up_clk;
input [31:0] up_startaddr;
input [15:0] up_hsize;
input [15:0] up_hmin;
input [15:0] up_hmax;
// es interface, data is 64bits with valid as the qualifier
input es_valid;
input es_sos;
input es_eos;
input [31:0] es_data;
// master interface and status signals
output mb_req;
input mb_ack;
output [31: 0] mb_addr;
output [31: 0] mb_data;
input mb_done;
input mb_error;
input mb_readyn;
output mb_ovf;
output mb_unf;
output mb_state;
output [ 1:0] mb_status;
// master debug data (for chipscope)
output [83:0] mb_dbg_data;
output [ 7:0] mb_dbg_trigger;
reg [ 5:0] mb_addr_diff = 'd0;
reg mb_almost_full = 'd0;
reg mb_almost_empty = 'd0;
reg mb_ovf = 'd0;
reg mb_unf = 'd0;
reg [ 5:0] mb_raddr = 'd0;
reg mb_rd = 'd0;
reg mb_rvalid = 'd0;
reg [31:0] mb_rdata = 'd0;
reg mb_state = 'd0;
reg [15:0] mb_hoffset = 'd0;
reg [31:0] mb_voffset = 'd0;
reg [15:0] mb_hmin = 'd0;
reg [15:0] mb_hmax = 'd0;
reg [15:0] mb_hsize = 'd0;
reg mb_req = 'd0;
reg [31:0] mb_addr = 'd0;
reg [31:0] mb_data = 'd0;
reg [ 1:0] mb_status = 'd0;
reg mb_wr = 'd0;
reg [ 5:0] mb_waddr = 'd0;
reg [31:0] mb_wdata = 'd0;
wire [ 6:0] mb_addr_diff_s;
wire [31:0] mb_addr_s;
wire mb_rd_s;
wire [31:0] mb_rdata_s;
// debug signals (for chipscope)
assign mb_dbg_trigger[7] = mb_unf;
assign mb_dbg_trigger[6] = mb_ovf;
assign mb_dbg_trigger[5] = mb_state;
assign mb_dbg_trigger[4] = mb_rvalid;
assign mb_dbg_trigger[3] = mb_req;
assign mb_dbg_trigger[2] = mb_ack;
assign mb_dbg_trigger[1] = mb_done;
assign mb_dbg_trigger[0] = mb_error;
assign mb_dbg_data[ 83: 83] = es_valid;
assign mb_dbg_data[ 82: 82] = es_sos;
assign mb_dbg_data[ 81: 81] = es_eos;
assign mb_dbg_data[ 80: 80] = mb_req;
assign mb_dbg_data[ 79: 79] = mb_ack;
assign mb_dbg_data[ 78: 78] = mb_done;
assign mb_dbg_data[ 77: 77] = mb_error;
assign mb_dbg_data[ 76: 76] = mb_readyn;
assign mb_dbg_data[ 75: 70] = mb_addr_diff;
assign mb_dbg_data[ 69: 69] = mb_almost_full;
assign mb_dbg_data[ 68: 68] = mb_almost_empty;
assign mb_dbg_data[ 67: 67] = mb_ovf;
assign mb_dbg_data[ 66: 66] = mb_unf;
assign mb_dbg_data[ 65: 60] = mb_raddr;
assign mb_dbg_data[ 59: 59] = mb_rd;
assign mb_dbg_data[ 58: 58] = mb_rvalid;
assign mb_dbg_data[ 57: 57] = mb_state;
assign mb_dbg_data[ 56: 41] = mb_hoffset;
assign mb_dbg_data[ 40: 9] = mb_voffset;
assign mb_dbg_data[ 8: 7] = mb_status;
assign mb_dbg_data[ 6: 6] = mb_wr;
assign mb_dbg_data[ 5: 0] = mb_waddr;
// standard book keeping stuff (memory management, overflow or underflow status)
assign mb_addr_diff_s = {1'b1, mb_waddr} - mb_raddr;
assign mb_addr_s = mb_voffset + {mb_hoffset, 2'd0};
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
mb_addr_diff <= 'd0;
mb_almost_full <= 'd0;
mb_almost_empty <= 'd0;
mb_ovf <= 'd0;
mb_unf <= 'd0;
end else begin
mb_addr_diff <= mb_addr_diff_s[5:0];
mb_almost_full <= (mb_addr_diff > 60) ? 1'b1 : 1'b0;
mb_almost_empty <= (mb_addr_diff < 3) ? 1'b1 : 1'b0;
mb_ovf <= (mb_addr_diff < 3) ? mb_almost_full : 1'b0;
mb_unf <= (mb_addr_diff > 60) ? mb_almost_empty : 1'b0;
end
end
// master read and pipe line delays (memory latency)
assign mb_rd_s = (mb_waddr == mb_raddr) ? 1'b0 : ~mb_state;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
mb_raddr <= 'd0;
mb_rd <= 'd0;
mb_rvalid <= 'd0;
mb_rdata <= 'd0;
end else begin
if (mb_rd_s == 1'b1) begin
mb_raddr <= mb_raddr + 1'b1;
end
mb_rd <= mb_rd_s;
mb_rvalid <= mb_rd;
mb_rdata <= mb_rdata_s;
end
end
// master command state and address update
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
mb_state <= 'd0;
mb_hoffset <= 'd0;
mb_voffset <= 'd0;
mb_hmin <= 'd0;
mb_hmax <= 'd0;
mb_hsize <= 'd0;
end else begin
if (mb_done == 1'b1) begin
mb_state <= 1'b0;
end else if (mb_rd_s == 1'b1) begin
mb_state <= 1'b1;
end
if (mb_done == 1'b1) begin
if (mb_hoffset >= mb_hmax) begin
mb_hoffset <= mb_hmin;
end else begin
mb_hoffset <= mb_hoffset + 1'b1;
end
end else if (es_sos == 1'b1) begin
mb_hoffset <= up_hmin;
end
if ((mb_done == 1'b1) && (mb_hoffset >= mb_hmax)) begin
mb_voffset <= mb_voffset + {mb_hsize, 2'd0};
end else if (es_sos == 1'b1) begin
mb_voffset <= up_startaddr;
end
if ((es_sos == 1'b1) || (es_eos == 1'b1)) begin
mb_hmin <= up_hmin;
mb_hmax <= up_hmax;
mb_hsize <= up_hsize;
end
end
end
// master bus write
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
mb_req <= 'd0;
mb_addr <= 'd0;
mb_data <= 'd0;
mb_status <= 'd0;
end else begin
if (mb_ack == 1'b1) begin
mb_req <= 1'b0;
end else if (mb_rvalid == 1'b1) begin
mb_req <= 1'b1;
end
if (mb_rvalid == 1'b1) begin
mb_addr <= mb_addr_s;
mb_data <= mb_rdata;
end
if (mb_done == 1'b1) begin
mb_status <= {mb_error, ~mb_readyn};
end else if (mb_rvalid == 1'b1) begin
mb_status <= 2'd0;
end
end
end
// es data write
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
mb_wr <= 'd0;
mb_waddr <= 'd0;
mb_wdata <= 'd0;
end else begin
mb_wr <= es_valid;
if (mb_wr == 1'b1) begin
mb_waddr <= mb_waddr + 1'b1;
end
mb_wdata <= es_data;
end
end
// a small buffer is used to hold the eye scan data
cf_mem #(.DW(32), .AW(6)) i_mem (
.clka (up_clk),
.wea (mb_wr),
.addra (mb_waddr),
.dina (mb_wdata),
.clkb (up_clk),
.addrb (mb_raddr),
.doutb (mb_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module compare (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
db_index,
contacts_index,
contacts_address0,
contacts_ce0,
contacts_q0,
contacts_address1,
contacts_ce1,
contacts_q1,
database_address0,
database_ce0,
database_q0,
database_address1,
database_ce1,
database_q1,
ap_return
);
parameter ap_ST_fsm_state1 = 33'd1;
parameter ap_ST_fsm_state2 = 33'd2;
parameter ap_ST_fsm_state3 = 33'd4;
parameter ap_ST_fsm_state4 = 33'd8;
parameter ap_ST_fsm_state5 = 33'd16;
parameter ap_ST_fsm_state6 = 33'd32;
parameter ap_ST_fsm_state7 = 33'd64;
parameter ap_ST_fsm_state8 = 33'd128;
parameter ap_ST_fsm_state9 = 33'd256;
parameter ap_ST_fsm_state10 = 33'd512;
parameter ap_ST_fsm_state11 = 33'd1024;
parameter ap_ST_fsm_state12 = 33'd2048;
parameter ap_ST_fsm_state13 = 33'd4096;
parameter ap_ST_fsm_state14 = 33'd8192;
parameter ap_ST_fsm_state15 = 33'd16384;
parameter ap_ST_fsm_state16 = 33'd32768;
parameter ap_ST_fsm_state17 = 33'd65536;
parameter ap_ST_fsm_state18 = 33'd131072;
parameter ap_ST_fsm_state19 = 33'd262144;
parameter ap_ST_fsm_state20 = 33'd524288;
parameter ap_ST_fsm_state21 = 33'd1048576;
parameter ap_ST_fsm_state22 = 33'd2097152;
parameter ap_ST_fsm_state23 = 33'd4194304;
parameter ap_ST_fsm_state24 = 33'd8388608;
parameter ap_ST_fsm_state25 = 33'd16777216;
parameter ap_ST_fsm_state26 = 33'd33554432;
parameter ap_ST_fsm_state27 = 33'd67108864;
parameter ap_ST_fsm_state28 = 33'd134217728;
parameter ap_ST_fsm_state29 = 33'd268435456;
parameter ap_ST_fsm_state30 = 33'd536870912;
parameter ap_ST_fsm_state31 = 33'd1073741824;
parameter ap_ST_fsm_state32 = 33'd2147483648;
parameter ap_ST_fsm_state33 = 33'd4294967296;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [30:0] db_index;
input [7:0] contacts_index;
output [12:0] contacts_address0;
output contacts_ce0;
input [7:0] contacts_q0;
output [12:0] contacts_address1;
output contacts_ce1;
input [7:0] contacts_q1;
output [14:0] database_address0;
output database_ce0;
input [7:0] database_q0;
output [14:0] database_address1;
output database_ce1;
input [7:0] database_q1;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[12:0] contacts_address0;
reg contacts_ce0;
reg[12:0] contacts_address1;
reg contacts_ce1;
reg[14:0] database_address0;
reg database_ce0;
reg[14:0] database_address1;
reg database_ce1;
reg[0:0] ap_return;
(* fsm_encoding = "none" *) reg [32:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [12:0] tmp_fu_1352_p3;
reg [12:0] tmp_reg_2975;
wire [31:0] tmp_s_fu_1364_p3;
reg [31:0] tmp_s_reg_3041;
wire [0:0] grp_fu_1336_p2;
reg [0:0] tmp_15_reg_3127;
wire ap_CS_fsm_state2;
wire [0:0] grp_fu_1342_p2;
reg [0:0] tmp_15_1_reg_3132;
wire ap_CS_fsm_state3;
wire [0:0] tmp4_fu_1494_p2;
reg [0:0] tmp4_reg_3177;
reg [0:0] tmp_15_4_reg_3182;
wire ap_CS_fsm_state4;
reg [0:0] tmp_15_5_reg_3187;
wire ap_CS_fsm_state5;
wire [0:0] tmp3_fu_1596_p2;
reg [0:0] tmp3_reg_3232;
reg [0:0] tmp_15_8_reg_3237;
wire ap_CS_fsm_state6;
reg [0:0] tmp_15_9_reg_3242;
wire ap_CS_fsm_state7;
wire [0:0] tmp11_fu_1691_p2;
reg [0:0] tmp11_reg_3287;
reg [0:0] tmp_15_11_reg_3292;
wire ap_CS_fsm_state8;
reg [0:0] tmp_15_12_reg_3297;
wire ap_CS_fsm_state9;
wire [0:0] tmp2_fu_1798_p2;
reg [0:0] tmp2_reg_3342;
reg [0:0] tmp_15_15_reg_3347;
wire ap_CS_fsm_state10;
reg [0:0] tmp_15_16_reg_3352;
wire ap_CS_fsm_state11;
wire [0:0] tmp19_fu_1893_p2;
reg [0:0] tmp19_reg_3397;
reg [0:0] tmp_15_19_reg_3402;
wire ap_CS_fsm_state12;
reg [0:0] tmp_15_20_reg_3407;
wire ap_CS_fsm_state13;
wire [0:0] tmp18_fu_1995_p2;
reg [0:0] tmp18_reg_3452;
reg [0:0] tmp_15_23_reg_3457;
wire ap_CS_fsm_state14;
reg [0:0] tmp_15_24_reg_3462;
wire ap_CS_fsm_state15;
wire [0:0] tmp26_fu_2090_p2;
reg [0:0] tmp26_reg_3507;
reg [0:0] tmp_15_27_reg_3512;
wire ap_CS_fsm_state16;
reg [0:0] tmp_15_28_reg_3517;
wire ap_CS_fsm_state17;
wire [0:0] tmp17_fu_2197_p2;
reg [0:0] tmp17_reg_3562;
reg [0:0] tmp_15_31_reg_3567;
wire ap_CS_fsm_state18;
reg [0:0] tmp_15_32_reg_3572;
wire ap_CS_fsm_state19;
wire [0:0] tmp35_fu_2292_p2;
reg [0:0] tmp35_reg_3617;
reg [0:0] tmp_15_35_reg_3622;
wire ap_CS_fsm_state20;
reg [0:0] tmp_15_36_reg_3627;
wire ap_CS_fsm_state21;
wire [0:0] tmp34_fu_2394_p2;
reg [0:0] tmp34_reg_3672;
reg [0:0] tmp_15_39_reg_3677;
wire ap_CS_fsm_state22;
reg [0:0] tmp_15_40_reg_3682;
wire ap_CS_fsm_state23;
wire [0:0] tmp42_fu_2489_p2;
reg [0:0] tmp42_reg_3727;
reg [0:0] tmp_15_43_reg_3732;
wire ap_CS_fsm_state24;
reg [0:0] tmp_15_44_reg_3737;
wire ap_CS_fsm_state25;
wire [0:0] tmp33_fu_2596_p2;
reg [0:0] tmp33_reg_3782;
reg [0:0] tmp_15_47_reg_3787;
wire ap_CS_fsm_state26;
reg [0:0] tmp_15_48_reg_3792;
wire ap_CS_fsm_state27;
wire [0:0] tmp50_fu_2691_p2;
reg [0:0] tmp50_reg_3837;
reg [0:0] tmp_15_51_reg_3842;
wire ap_CS_fsm_state28;
reg [0:0] tmp_15_52_reg_3847;
wire ap_CS_fsm_state29;
wire [0:0] tmp49_fu_2793_p2;
reg [0:0] tmp49_reg_3892;
reg [0:0] tmp_15_55_reg_3897;
wire ap_CS_fsm_state30;
reg [0:0] tmp_15_56_reg_3902;
wire ap_CS_fsm_state31;
wire [0:0] tmp57_fu_2888_p2;
reg [0:0] tmp57_reg_3947;
reg [0:0] tmp_15_59_reg_3952;
wire ap_CS_fsm_state32;
reg [0:0] tmp_15_60_reg_3957;
wire [63:0] tmp_12_fu_1372_p1;
wire signed [63:0] tmp_14_fu_1377_p1;
wire [63:0] tmp_12_1_fu_1388_p1;
wire signed [63:0] tmp_14_1_fu_1399_p1;
wire [63:0] tmp_12_2_fu_1409_p1;
wire signed [63:0] tmp_14_2_fu_1419_p1;
wire [63:0] tmp_12_3_fu_1429_p1;
wire signed [63:0] tmp_14_3_fu_1439_p1;
wire [63:0] tmp_12_4_fu_1449_p1;
wire signed [63:0] tmp_14_4_fu_1459_p1;
wire [63:0] tmp_12_5_fu_1469_p1;
wire signed [63:0] tmp_14_5_fu_1479_p1;
wire [63:0] tmp_12_6_fu_1505_p1;
wire signed [63:0] tmp_14_6_fu_1515_p1;
wire [63:0] tmp_12_7_fu_1525_p1;
wire signed [63:0] tmp_14_7_fu_1535_p1;
wire [63:0] tmp_12_8_fu_1545_p1;
wire signed [63:0] tmp_14_8_fu_1555_p1;
wire [63:0] tmp_12_9_fu_1565_p1;
wire signed [63:0] tmp_14_9_fu_1575_p1;
wire [63:0] tmp_12_s_fu_1606_p1;
wire signed [63:0] tmp_14_s_fu_1616_p1;
wire [63:0] tmp_12_10_fu_1626_p1;
wire signed [63:0] tmp_14_10_fu_1636_p1;
wire [63:0] tmp_12_11_fu_1646_p1;
wire signed [63:0] tmp_14_11_fu_1656_p1;
wire [63:0] tmp_12_12_fu_1666_p1;
wire signed [63:0] tmp_14_12_fu_1676_p1;
wire [63:0] tmp_12_13_fu_1702_p1;
wire signed [63:0] tmp_14_13_fu_1712_p1;
wire [63:0] tmp_12_14_fu_1722_p1;
wire signed [63:0] tmp_14_14_fu_1732_p1;
wire [63:0] tmp_12_15_fu_1742_p1;
wire signed [63:0] tmp_14_15_fu_1752_p1;
wire [63:0] tmp_12_16_fu_1762_p1;
wire signed [63:0] tmp_14_16_fu_1772_p1;
wire [63:0] tmp_12_17_fu_1808_p1;
wire signed [63:0] tmp_14_17_fu_1818_p1;
wire [63:0] tmp_12_18_fu_1828_p1;
wire signed [63:0] tmp_14_18_fu_1838_p1;
wire [63:0] tmp_12_19_fu_1848_p1;
wire signed [63:0] tmp_14_19_fu_1858_p1;
wire [63:0] tmp_12_20_fu_1868_p1;
wire signed [63:0] tmp_14_20_fu_1878_p1;
wire [63:0] tmp_12_21_fu_1904_p1;
wire signed [63:0] tmp_14_21_fu_1914_p1;
wire [63:0] tmp_12_22_fu_1924_p1;
wire signed [63:0] tmp_14_22_fu_1934_p1;
wire [63:0] tmp_12_23_fu_1944_p1;
wire signed [63:0] tmp_14_23_fu_1954_p1;
wire [63:0] tmp_12_24_fu_1964_p1;
wire signed [63:0] tmp_14_24_fu_1974_p1;
wire [63:0] tmp_12_25_fu_2005_p1;
wire signed [63:0] tmp_14_25_fu_2015_p1;
wire [63:0] tmp_12_26_fu_2025_p1;
wire signed [63:0] tmp_14_26_fu_2035_p1;
wire [63:0] tmp_12_27_fu_2045_p1;
wire signed [63:0] tmp_14_27_fu_2055_p1;
wire [63:0] tmp_12_28_fu_2065_p1;
wire signed [63:0] tmp_14_28_fu_2075_p1;
wire [63:0] tmp_12_29_fu_2101_p1;
wire signed [63:0] tmp_14_29_fu_2111_p1;
wire [63:0] tmp_12_30_fu_2121_p1;
wire signed [63:0] tmp_14_30_fu_2131_p1;
wire [63:0] tmp_12_31_fu_2141_p1;
wire signed [63:0] tmp_14_31_fu_2151_p1;
wire [63:0] tmp_12_32_fu_2161_p1;
wire signed [63:0] tmp_14_32_fu_2171_p1;
wire [63:0] tmp_12_33_fu_2207_p1;
wire signed [63:0] tmp_14_33_fu_2217_p1;
wire [63:0] tmp_12_34_fu_2227_p1;
wire signed [63:0] tmp_14_34_fu_2237_p1;
wire [63:0] tmp_12_35_fu_2247_p1;
wire signed [63:0] tmp_14_35_fu_2257_p1;
wire [63:0] tmp_12_36_fu_2267_p1;
wire signed [63:0] tmp_14_36_fu_2277_p1;
wire [63:0] tmp_12_37_fu_2303_p1;
wire signed [63:0] tmp_14_37_fu_2313_p1;
wire [63:0] tmp_12_38_fu_2323_p1;
wire signed [63:0] tmp_14_38_fu_2333_p1;
wire [63:0] tmp_12_39_fu_2343_p1;
wire signed [63:0] tmp_14_39_fu_2353_p1;
wire [63:0] tmp_12_40_fu_2363_p1;
wire signed [63:0] tmp_14_40_fu_2373_p1;
wire [63:0] tmp_12_41_fu_2404_p1;
wire signed [63:0] tmp_14_41_fu_2414_p1;
wire [63:0] tmp_12_42_fu_2424_p1;
wire signed [63:0] tmp_14_42_fu_2434_p1;
wire [63:0] tmp_12_43_fu_2444_p1;
wire signed [63:0] tmp_14_43_fu_2454_p1;
wire [63:0] tmp_12_44_fu_2464_p1;
wire signed [63:0] tmp_14_44_fu_2474_p1;
wire [63:0] tmp_12_45_fu_2500_p1;
wire signed [63:0] tmp_14_45_fu_2510_p1;
wire [63:0] tmp_12_46_fu_2520_p1;
wire signed [63:0] tmp_14_46_fu_2530_p1;
wire [63:0] tmp_12_47_fu_2540_p1;
wire signed [63:0] tmp_14_47_fu_2550_p1;
wire [63:0] tmp_12_48_fu_2560_p1;
wire signed [63:0] tmp_14_48_fu_2570_p1;
wire [63:0] tmp_12_49_fu_2606_p1;
wire signed [63:0] tmp_14_49_fu_2616_p1;
wire [63:0] tmp_12_50_fu_2626_p1;
wire signed [63:0] tmp_14_50_fu_2636_p1;
wire [63:0] tmp_12_51_fu_2646_p1;
wire signed [63:0] tmp_14_51_fu_2656_p1;
wire [63:0] tmp_12_52_fu_2666_p1;
wire signed [63:0] tmp_14_52_fu_2676_p1;
wire [63:0] tmp_12_53_fu_2702_p1;
wire signed [63:0] tmp_14_53_fu_2712_p1;
wire [63:0] tmp_12_54_fu_2722_p1;
wire signed [63:0] tmp_14_54_fu_2732_p1;
wire [63:0] tmp_12_55_fu_2742_p1;
wire signed [63:0] tmp_14_55_fu_2752_p1;
wire [63:0] tmp_12_56_fu_2762_p1;
wire signed [63:0] tmp_14_56_fu_2772_p1;
wire [63:0] tmp_12_57_fu_2803_p1;
wire signed [63:0] tmp_14_57_fu_2813_p1;
wire [63:0] tmp_12_58_fu_2823_p1;
wire signed [63:0] tmp_14_58_fu_2833_p1;
wire [63:0] tmp_12_59_fu_2843_p1;
wire signed [63:0] tmp_14_59_fu_2853_p1;
wire [63:0] tmp_12_60_fu_2863_p1;
wire signed [63:0] tmp_14_60_fu_2873_p1;
wire [63:0] tmp_12_61_fu_2899_p1;
wire signed [63:0] tmp_14_61_fu_2909_p1;
wire [63:0] tmp_12_62_fu_2919_p1;
wire signed [63:0] tmp_14_62_fu_2929_p1;
wire ap_CS_fsm_state33;
wire [6:0] tmp_127_fu_1348_p1;
wire [25:0] tmp_128_fu_1360_p1;
wire [12:0] tmp_11_s_fu_1382_p2;
wire [31:0] tmp_13_s_fu_1393_p2;
wire [12:0] tmp_11_1_fu_1404_p2;
wire [31:0] tmp_13_1_fu_1414_p2;
wire [12:0] tmp_11_2_fu_1424_p2;
wire [31:0] tmp_13_2_fu_1434_p2;
wire [12:0] tmp_11_3_fu_1444_p2;
wire [31:0] tmp_13_3_fu_1454_p2;
wire [12:0] tmp_11_4_fu_1464_p2;
wire [31:0] tmp_13_4_fu_1474_p2;
wire [0:0] tmp6_fu_1488_p2;
wire [0:0] tmp5_fu_1484_p2;
wire [12:0] tmp_11_5_fu_1500_p2;
wire [31:0] tmp_13_5_fu_1510_p2;
wire [12:0] tmp_11_6_fu_1520_p2;
wire [31:0] tmp_13_6_fu_1530_p2;
wire [12:0] tmp_11_7_fu_1540_p2;
wire [31:0] tmp_13_7_fu_1550_p2;
wire [12:0] tmp_11_8_fu_1560_p2;
wire [31:0] tmp_13_8_fu_1570_p2;
wire [0:0] tmp9_fu_1584_p2;
wire [0:0] tmp8_fu_1580_p2;
wire [0:0] tmp7_fu_1590_p2;
wire [12:0] tmp_11_9_fu_1601_p2;
wire [31:0] tmp_13_9_fu_1611_p2;
wire [12:0] tmp_11_10_fu_1621_p2;
wire [31:0] tmp_13_10_fu_1631_p2;
wire [12:0] tmp_11_11_fu_1641_p2;
wire [31:0] tmp_13_11_fu_1651_p2;
wire [12:0] tmp_11_12_fu_1661_p2;
wire [31:0] tmp_13_12_fu_1671_p2;
wire [0:0] tmp13_fu_1685_p2;
wire [0:0] tmp12_fu_1681_p2;
wire [12:0] tmp_11_13_fu_1697_p2;
wire [31:0] tmp_13_13_fu_1707_p2;
wire [12:0] tmp_11_14_fu_1717_p2;
wire [31:0] tmp_13_14_fu_1727_p2;
wire [12:0] tmp_11_15_fu_1737_p2;
wire [31:0] tmp_13_15_fu_1747_p2;
wire [12:0] tmp_11_16_fu_1757_p2;
wire [31:0] tmp_13_16_fu_1767_p2;
wire [0:0] tmp16_fu_1781_p2;
wire [0:0] tmp15_fu_1777_p2;
wire [0:0] tmp14_fu_1787_p2;
wire [0:0] tmp10_fu_1793_p2;
wire [12:0] tmp_11_17_fu_1803_p2;
wire [31:0] tmp_13_17_fu_1813_p2;
wire [12:0] tmp_11_18_fu_1823_p2;
wire [31:0] tmp_13_18_fu_1833_p2;
wire [12:0] tmp_11_19_fu_1843_p2;
wire [31:0] tmp_13_19_fu_1853_p2;
wire [12:0] tmp_11_20_fu_1863_p2;
wire [31:0] tmp_13_20_fu_1873_p2;
wire [0:0] tmp21_fu_1887_p2;
wire [0:0] tmp20_fu_1883_p2;
wire [12:0] tmp_11_21_fu_1899_p2;
wire [31:0] tmp_13_21_fu_1909_p2;
wire [12:0] tmp_11_22_fu_1919_p2;
wire [31:0] tmp_13_22_fu_1929_p2;
wire [12:0] tmp_11_23_fu_1939_p2;
wire [31:0] tmp_13_23_fu_1949_p2;
wire [12:0] tmp_11_24_fu_1959_p2;
wire [31:0] tmp_13_24_fu_1969_p2;
wire [0:0] tmp24_fu_1983_p2;
wire [0:0] tmp23_fu_1979_p2;
wire [0:0] tmp22_fu_1989_p2;
wire [12:0] tmp_11_25_fu_2000_p2;
wire [31:0] tmp_13_25_fu_2010_p2;
wire [12:0] tmp_11_26_fu_2020_p2;
wire [31:0] tmp_13_26_fu_2030_p2;
wire [12:0] tmp_11_27_fu_2040_p2;
wire [31:0] tmp_13_27_fu_2050_p2;
wire [12:0] tmp_11_28_fu_2060_p2;
wire [31:0] tmp_13_28_fu_2070_p2;
wire [0:0] tmp28_fu_2084_p2;
wire [0:0] tmp27_fu_2080_p2;
wire [12:0] tmp_11_29_fu_2096_p2;
wire [31:0] tmp_13_29_fu_2106_p2;
wire [12:0] tmp_11_30_fu_2116_p2;
wire [31:0] tmp_13_30_fu_2126_p2;
wire [12:0] tmp_11_31_fu_2136_p2;
wire [31:0] tmp_13_31_fu_2146_p2;
wire [12:0] tmp_11_32_fu_2156_p2;
wire [31:0] tmp_13_32_fu_2166_p2;
wire [0:0] tmp31_fu_2180_p2;
wire [0:0] tmp30_fu_2176_p2;
wire [0:0] tmp29_fu_2186_p2;
wire [0:0] tmp25_fu_2192_p2;
wire [12:0] tmp_11_33_fu_2202_p2;
wire [31:0] tmp_13_33_fu_2212_p2;
wire [12:0] tmp_11_34_fu_2222_p2;
wire [31:0] tmp_13_34_fu_2232_p2;
wire [12:0] tmp_11_35_fu_2242_p2;
wire [31:0] tmp_13_35_fu_2252_p2;
wire [12:0] tmp_11_36_fu_2262_p2;
wire [31:0] tmp_13_36_fu_2272_p2;
wire [0:0] tmp37_fu_2286_p2;
wire [0:0] tmp36_fu_2282_p2;
wire [12:0] tmp_11_37_fu_2298_p2;
wire [31:0] tmp_13_37_fu_2308_p2;
wire [12:0] tmp_11_38_fu_2318_p2;
wire [31:0] tmp_13_38_fu_2328_p2;
wire [12:0] tmp_11_39_fu_2338_p2;
wire [31:0] tmp_13_39_fu_2348_p2;
wire [12:0] tmp_11_40_fu_2358_p2;
wire [31:0] tmp_13_40_fu_2368_p2;
wire [0:0] tmp40_fu_2382_p2;
wire [0:0] tmp39_fu_2378_p2;
wire [0:0] tmp38_fu_2388_p2;
wire [12:0] tmp_11_41_fu_2399_p2;
wire [31:0] tmp_13_41_fu_2409_p2;
wire [12:0] tmp_11_42_fu_2419_p2;
wire [31:0] tmp_13_42_fu_2429_p2;
wire [12:0] tmp_11_43_fu_2439_p2;
wire [31:0] tmp_13_43_fu_2449_p2;
wire [12:0] tmp_11_44_fu_2459_p2;
wire [31:0] tmp_13_44_fu_2469_p2;
wire [0:0] tmp44_fu_2483_p2;
wire [0:0] tmp43_fu_2479_p2;
wire [12:0] tmp_11_45_fu_2495_p2;
wire [31:0] tmp_13_45_fu_2505_p2;
wire [12:0] tmp_11_46_fu_2515_p2;
wire [31:0] tmp_13_46_fu_2525_p2;
wire [12:0] tmp_11_47_fu_2535_p2;
wire [31:0] tmp_13_47_fu_2545_p2;
wire [12:0] tmp_11_48_fu_2555_p2;
wire [31:0] tmp_13_48_fu_2565_p2;
wire [0:0] tmp47_fu_2579_p2;
wire [0:0] tmp46_fu_2575_p2;
wire [0:0] tmp45_fu_2585_p2;
wire [0:0] tmp41_fu_2591_p2;
wire [12:0] tmp_11_49_fu_2601_p2;
wire [31:0] tmp_13_49_fu_2611_p2;
wire [12:0] tmp_11_50_fu_2621_p2;
wire [31:0] tmp_13_50_fu_2631_p2;
wire [12:0] tmp_11_51_fu_2641_p2;
wire [31:0] tmp_13_51_fu_2651_p2;
wire [12:0] tmp_11_52_fu_2661_p2;
wire [31:0] tmp_13_52_fu_2671_p2;
wire [0:0] tmp52_fu_2685_p2;
wire [0:0] tmp51_fu_2681_p2;
wire [12:0] tmp_11_53_fu_2697_p2;
wire [31:0] tmp_13_53_fu_2707_p2;
wire [12:0] tmp_11_54_fu_2717_p2;
wire [31:0] tmp_13_54_fu_2727_p2;
wire [12:0] tmp_11_55_fu_2737_p2;
wire [31:0] tmp_13_55_fu_2747_p2;
wire [12:0] tmp_11_56_fu_2757_p2;
wire [31:0] tmp_13_56_fu_2767_p2;
wire [0:0] tmp55_fu_2781_p2;
wire [0:0] tmp54_fu_2777_p2;
wire [0:0] tmp53_fu_2787_p2;
wire [12:0] tmp_11_57_fu_2798_p2;
wire [31:0] tmp_13_57_fu_2808_p2;
wire [12:0] tmp_11_58_fu_2818_p2;
wire [31:0] tmp_13_58_fu_2828_p2;
wire [12:0] tmp_11_59_fu_2838_p2;
wire [31:0] tmp_13_59_fu_2848_p2;
wire [12:0] tmp_11_60_fu_2858_p2;
wire [31:0] tmp_13_60_fu_2868_p2;
wire [0:0] tmp59_fu_2882_p2;
wire [0:0] tmp58_fu_2878_p2;
wire [12:0] tmp_11_61_fu_2894_p2;
wire [31:0] tmp_13_61_fu_2904_p2;
wire [12:0] tmp_11_62_fu_2914_p2;
wire [31:0] tmp_13_62_fu_2924_p2;
wire [0:0] tmp62_fu_2942_p2;
wire [0:0] tmp61_fu_2938_p2;
wire [0:0] tmp60_fu_2948_p2;
wire [0:0] tmp56_fu_2954_p2;
wire [0:0] tmp48_fu_2959_p2;
wire [0:0] tmp32_fu_2964_p2;
wire [0:0] tmp1_fu_2934_p2;
wire [0:0] found_1_s_fu_2969_p2;
reg [0:0] ap_return_preg;
reg [32:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 33'd1;
#0 ap_return_preg = 1'd0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 1'd0;
end else begin
if ((1'b1 == ap_CS_fsm_state33)) begin
ap_return_preg <= found_1_s_fu_2969_p2;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
tmp11_reg_3287 <= tmp11_fu_1691_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state17)) begin
tmp17_reg_3562 <= tmp17_fu_2197_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state13)) begin
tmp18_reg_3452 <= tmp18_fu_1995_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state11)) begin
tmp19_reg_3397 <= tmp19_fu_1893_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state15)) begin
tmp26_reg_3507 <= tmp26_fu_2090_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state9)) begin
tmp2_reg_3342 <= tmp2_fu_1798_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state25)) begin
tmp33_reg_3782 <= tmp33_fu_2596_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state21)) begin
tmp34_reg_3672 <= tmp34_fu_2394_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state19)) begin
tmp35_reg_3617 <= tmp35_fu_2292_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state5)) begin
tmp3_reg_3232 <= tmp3_fu_1596_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state23)) begin
tmp42_reg_3727 <= tmp42_fu_2489_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state29)) begin
tmp49_reg_3892 <= tmp49_fu_2793_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
tmp4_reg_3177 <= tmp4_fu_1494_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state27)) begin
tmp50_reg_3837 <= tmp50_fu_2691_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state31)) begin
tmp57_reg_3947 <= tmp57_fu_2888_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state8)) begin
tmp_15_11_reg_3292 <= grp_fu_1336_p2;
tmp_15_12_reg_3297 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state10)) begin
tmp_15_15_reg_3347 <= grp_fu_1336_p2;
tmp_15_16_reg_3352 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state12)) begin
tmp_15_19_reg_3402 <= grp_fu_1336_p2;
tmp_15_20_reg_3407 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
tmp_15_1_reg_3132 <= grp_fu_1342_p2;
tmp_15_reg_3127 <= grp_fu_1336_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state14)) begin
tmp_15_23_reg_3457 <= grp_fu_1336_p2;
tmp_15_24_reg_3462 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state16)) begin
tmp_15_27_reg_3512 <= grp_fu_1336_p2;
tmp_15_28_reg_3517 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state18)) begin
tmp_15_31_reg_3567 <= grp_fu_1336_p2;
tmp_15_32_reg_3572 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state20)) begin
tmp_15_35_reg_3622 <= grp_fu_1336_p2;
tmp_15_36_reg_3627 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state22)) begin
tmp_15_39_reg_3677 <= grp_fu_1336_p2;
tmp_15_40_reg_3682 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state24)) begin
tmp_15_43_reg_3732 <= grp_fu_1336_p2;
tmp_15_44_reg_3737 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state26)) begin
tmp_15_47_reg_3787 <= grp_fu_1336_p2;
tmp_15_48_reg_3792 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state4)) begin
tmp_15_4_reg_3182 <= grp_fu_1336_p2;
tmp_15_5_reg_3187 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state28)) begin
tmp_15_51_reg_3842 <= grp_fu_1336_p2;
tmp_15_52_reg_3847 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state30)) begin
tmp_15_55_reg_3897 <= grp_fu_1336_p2;
tmp_15_56_reg_3902 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state32)) begin
tmp_15_59_reg_3952 <= grp_fu_1336_p2;
tmp_15_60_reg_3957 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state6)) begin
tmp_15_8_reg_3237 <= grp_fu_1336_p2;
tmp_15_9_reg_3242 <= grp_fu_1342_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
tmp_reg_2975[12 : 6] <= tmp_fu_1352_p3[12 : 6];
tmp_s_reg_3041[31 : 6] <= tmp_s_fu_1364_p3[31 : 6];
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)) | (1'b1 == ap_CS_fsm_state33))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state33)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state33)) begin
ap_return = found_1_s_fu_2969_p2;
end else begin
ap_return = ap_return_preg;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state32)) begin
contacts_address0 = tmp_12_61_fu_2899_p1;
end else if ((1'b1 == ap_CS_fsm_state31)) begin
contacts_address0 = tmp_12_59_fu_2843_p1;
end else if ((1'b1 == ap_CS_fsm_state30)) begin
contacts_address0 = tmp_12_57_fu_2803_p1;
end else if ((1'b1 == ap_CS_fsm_state29)) begin
contacts_address0 = tmp_12_55_fu_2742_p1;
end else if ((1'b1 == ap_CS_fsm_state28)) begin
contacts_address0 = tmp_12_53_fu_2702_p1;
end else if ((1'b1 == ap_CS_fsm_state27)) begin
contacts_address0 = tmp_12_51_fu_2646_p1;
end else if ((1'b1 == ap_CS_fsm_state26)) begin
contacts_address0 = tmp_12_49_fu_2606_p1;
end else if ((1'b1 == ap_CS_fsm_state25)) begin
contacts_address0 = tmp_12_47_fu_2540_p1;
end else if ((1'b1 == ap_CS_fsm_state24)) begin
contacts_address0 = tmp_12_45_fu_2500_p1;
end else if ((1'b1 == ap_CS_fsm_state23)) begin
contacts_address0 = tmp_12_43_fu_2444_p1;
end else if ((1'b1 == ap_CS_fsm_state22)) begin
contacts_address0 = tmp_12_41_fu_2404_p1;
end else if ((1'b1 == ap_CS_fsm_state21)) begin
contacts_address0 = tmp_12_39_fu_2343_p1;
end else if ((1'b1 == ap_CS_fsm_state20)) begin
contacts_address0 = tmp_12_37_fu_2303_p1;
end else if ((1'b1 == ap_CS_fsm_state19)) begin
contacts_address0 = tmp_12_35_fu_2247_p1;
end else if ((1'b1 == ap_CS_fsm_state18)) begin
contacts_address0 = tmp_12_33_fu_2207_p1;
end else if ((1'b1 == ap_CS_fsm_state17)) begin
contacts_address0 = tmp_12_31_fu_2141_p1;
end else if ((1'b1 == ap_CS_fsm_state16)) begin
contacts_address0 = tmp_12_29_fu_2101_p1;
end else if ((1'b1 == ap_CS_fsm_state15)) begin
contacts_address0 = tmp_12_27_fu_2045_p1;
end else if ((1'b1 == ap_CS_fsm_state14)) begin
contacts_address0 = tmp_12_25_fu_2005_p1;
end else if ((1'b1 == ap_CS_fsm_state13)) begin
contacts_address0 = tmp_12_23_fu_1944_p1;
end else if ((1'b1 == ap_CS_fsm_state12)) begin
contacts_address0 = tmp_12_21_fu_1904_p1;
end else if ((1'b1 == ap_CS_fsm_state11)) begin
contacts_address0 = tmp_12_19_fu_1848_p1;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
contacts_address0 = tmp_12_17_fu_1808_p1;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
contacts_address0 = tmp_12_15_fu_1742_p1;
end else if ((1'b1 == ap_CS_fsm_state8)) begin
contacts_address0 = tmp_12_13_fu_1702_p1;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
contacts_address0 = tmp_12_11_fu_1646_p1;
end else if ((1'b1 == ap_CS_fsm_state6)) begin
contacts_address0 = tmp_12_s_fu_1606_p1;
end else if ((1'b1 == ap_CS_fsm_state5)) begin
contacts_address0 = tmp_12_8_fu_1545_p1;
end else if ((1'b1 == ap_CS_fsm_state4)) begin
contacts_address0 = tmp_12_6_fu_1505_p1;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
contacts_address0 = tmp_12_4_fu_1449_p1;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
contacts_address0 = tmp_12_2_fu_1409_p1;
end else if ((1'b1 == ap_CS_fsm_state1)) begin
contacts_address0 = tmp_12_fu_1372_p1;
end else begin
contacts_address0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state32)) begin
contacts_address1 = tmp_12_62_fu_2919_p1;
end else if ((1'b1 == ap_CS_fsm_state31)) begin
contacts_address1 = tmp_12_60_fu_2863_p1;
end else if ((1'b1 == ap_CS_fsm_state30)) begin
contacts_address1 = tmp_12_58_fu_2823_p1;
end else if ((1'b1 == ap_CS_fsm_state29)) begin
contacts_address1 = tmp_12_56_fu_2762_p1;
end else if ((1'b1 == ap_CS_fsm_state28)) begin
contacts_address1 = tmp_12_54_fu_2722_p1;
end else if ((1'b1 == ap_CS_fsm_state27)) begin
contacts_address1 = tmp_12_52_fu_2666_p1;
end else if ((1'b1 == ap_CS_fsm_state26)) begin
contacts_address1 = tmp_12_50_fu_2626_p1;
end else if ((1'b1 == ap_CS_fsm_state25)) begin
contacts_address1 = tmp_12_48_fu_2560_p1;
end else if ((1'b1 == ap_CS_fsm_state24)) begin
contacts_address1 = tmp_12_46_fu_2520_p1;
end else if ((1'b1 == ap_CS_fsm_state23)) begin
contacts_address1 = tmp_12_44_fu_2464_p1;
end else if ((1'b1 == ap_CS_fsm_state22)) begin
contacts_address1 = tmp_12_42_fu_2424_p1;
end else if ((1'b1 == ap_CS_fsm_state21)) begin
contacts_address1 = tmp_12_40_fu_2363_p1;
end else if ((1'b1 == ap_CS_fsm_state20)) begin
contacts_address1 = tmp_12_38_fu_2323_p1;
end else if ((1'b1 == ap_CS_fsm_state19)) begin
contacts_address1 = tmp_12_36_fu_2267_p1;
end else if ((1'b1 == ap_CS_fsm_state18)) begin
contacts_address1 = tmp_12_34_fu_2227_p1;
end else if ((1'b1 == ap_CS_fsm_state17)) begin
contacts_address1 = tmp_12_32_fu_2161_p1;
end else if ((1'b1 == ap_CS_fsm_state16)) begin
contacts_address1 = tmp_12_30_fu_2121_p1;
end else if ((1'b1 == ap_CS_fsm_state15)) begin
contacts_address1 = tmp_12_28_fu_2065_p1;
end else if ((1'b1 == ap_CS_fsm_state14)) begin
contacts_address1 = tmp_12_26_fu_2025_p1;
end else if ((1'b1 == ap_CS_fsm_state13)) begin
contacts_address1 = tmp_12_24_fu_1964_p1;
end else if ((1'b1 == ap_CS_fsm_state12)) begin
contacts_address1 = tmp_12_22_fu_1924_p1;
end else if ((1'b1 == ap_CS_fsm_state11)) begin
contacts_address1 = tmp_12_20_fu_1868_p1;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
contacts_address1 = tmp_12_18_fu_1828_p1;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
contacts_address1 = tmp_12_16_fu_1762_p1;
end else if ((1'b1 == ap_CS_fsm_state8)) begin
contacts_address1 = tmp_12_14_fu_1722_p1;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
contacts_address1 = tmp_12_12_fu_1666_p1;
end else if ((1'b1 == ap_CS_fsm_state6)) begin
contacts_address1 = tmp_12_10_fu_1626_p1;
end else if ((1'b1 == ap_CS_fsm_state5)) begin
contacts_address1 = tmp_12_9_fu_1565_p1;
end else if ((1'b1 == ap_CS_fsm_state4)) begin
contacts_address1 = tmp_12_7_fu_1525_p1;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
contacts_address1 = tmp_12_5_fu_1469_p1;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
contacts_address1 = tmp_12_3_fu_1429_p1;
end else if ((1'b1 == ap_CS_fsm_state1)) begin
contacts_address1 = tmp_12_1_fu_1388_p1;
end else begin
contacts_address1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state5) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state10) | (1'b1 == ap_CS_fsm_state11) | (1'b1 == ap_CS_fsm_state12) | (1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state14) | (1'b1 == ap_CS_fsm_state15) | (1'b1 == ap_CS_fsm_state16) | (1'b1 == ap_CS_fsm_state17) | (1'b1 == ap_CS_fsm_state18) | (1'b1 == ap_CS_fsm_state19) | (1'b1 == ap_CS_fsm_state20) | (1'b1 == ap_CS_fsm_state21) | (1'b1 == ap_CS_fsm_state22) | (1'b1 == ap_CS_fsm_state23) | (1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state28) | (1'b1 == ap_CS_fsm_state29) | (1'b1 == ap_CS_fsm_state30) | (1'b1 == ap_CS_fsm_state31) | (1'b1 == ap_CS_fsm_state32))) begin
contacts_ce0 = 1'b1;
end else begin
contacts_ce0 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state5) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state10) | (1'b1 == ap_CS_fsm_state11) | (1'b1 == ap_CS_fsm_state12) | (1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state14) | (1'b1 == ap_CS_fsm_state15) | (1'b1 == ap_CS_fsm_state16) | (1'b1 == ap_CS_fsm_state17) | (1'b1 == ap_CS_fsm_state18) | (1'b1 == ap_CS_fsm_state19) | (1'b1 == ap_CS_fsm_state20) | (1'b1 == ap_CS_fsm_state21) | (1'b1 == ap_CS_fsm_state22) | (1'b1 == ap_CS_fsm_state23) | (1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state28) | (1'b1 == ap_CS_fsm_state29) | (1'b1 == ap_CS_fsm_state30) | (1'b1 == ap_CS_fsm_state31) | (1'b1 == ap_CS_fsm_state32))) begin
contacts_ce1 = 1'b1;
end else begin
contacts_ce1 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state32)) begin
database_address0 = tmp_14_61_fu_2909_p1;
end else if ((1'b1 == ap_CS_fsm_state31)) begin
database_address0 = tmp_14_59_fu_2853_p1;
end else if ((1'b1 == ap_CS_fsm_state30)) begin
database_address0 = tmp_14_57_fu_2813_p1;
end else if ((1'b1 == ap_CS_fsm_state29)) begin
database_address0 = tmp_14_55_fu_2752_p1;
end else if ((1'b1 == ap_CS_fsm_state28)) begin
database_address0 = tmp_14_53_fu_2712_p1;
end else if ((1'b1 == ap_CS_fsm_state27)) begin
database_address0 = tmp_14_51_fu_2656_p1;
end else if ((1'b1 == ap_CS_fsm_state26)) begin
database_address0 = tmp_14_49_fu_2616_p1;
end else if ((1'b1 == ap_CS_fsm_state25)) begin
database_address0 = tmp_14_47_fu_2550_p1;
end else if ((1'b1 == ap_CS_fsm_state24)) begin
database_address0 = tmp_14_45_fu_2510_p1;
end else if ((1'b1 == ap_CS_fsm_state23)) begin
database_address0 = tmp_14_43_fu_2454_p1;
end else if ((1'b1 == ap_CS_fsm_state22)) begin
database_address0 = tmp_14_41_fu_2414_p1;
end else if ((1'b1 == ap_CS_fsm_state21)) begin
database_address0 = tmp_14_39_fu_2353_p1;
end else if ((1'b1 == ap_CS_fsm_state20)) begin
database_address0 = tmp_14_37_fu_2313_p1;
end else if ((1'b1 == ap_CS_fsm_state19)) begin
database_address0 = tmp_14_35_fu_2257_p1;
end else if ((1'b1 == ap_CS_fsm_state18)) begin
database_address0 = tmp_14_33_fu_2217_p1;
end else if ((1'b1 == ap_CS_fsm_state17)) begin
database_address0 = tmp_14_31_fu_2151_p1;
end else if ((1'b1 == ap_CS_fsm_state16)) begin
database_address0 = tmp_14_29_fu_2111_p1;
end else if ((1'b1 == ap_CS_fsm_state15)) begin
database_address0 = tmp_14_27_fu_2055_p1;
end else if ((1'b1 == ap_CS_fsm_state14)) begin
database_address0 = tmp_14_25_fu_2015_p1;
end else if ((1'b1 == ap_CS_fsm_state13)) begin
database_address0 = tmp_14_23_fu_1954_p1;
end else if ((1'b1 == ap_CS_fsm_state12)) begin
database_address0 = tmp_14_21_fu_1914_p1;
end else if ((1'b1 == ap_CS_fsm_state11)) begin
database_address0 = tmp_14_19_fu_1858_p1;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
database_address0 = tmp_14_17_fu_1818_p1;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
database_address0 = tmp_14_15_fu_1752_p1;
end else if ((1'b1 == ap_CS_fsm_state8)) begin
database_address0 = tmp_14_13_fu_1712_p1;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
database_address0 = tmp_14_11_fu_1656_p1;
end else if ((1'b1 == ap_CS_fsm_state6)) begin
database_address0 = tmp_14_s_fu_1616_p1;
end else if ((1'b1 == ap_CS_fsm_state5)) begin
database_address0 = tmp_14_8_fu_1555_p1;
end else if ((1'b1 == ap_CS_fsm_state4)) begin
database_address0 = tmp_14_6_fu_1515_p1;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
database_address0 = tmp_14_4_fu_1459_p1;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
database_address0 = tmp_14_2_fu_1419_p1;
end else if ((1'b1 == ap_CS_fsm_state1)) begin
database_address0 = tmp_14_fu_1377_p1;
end else begin
database_address0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state32)) begin
database_address1 = tmp_14_62_fu_2929_p1;
end else if ((1'b1 == ap_CS_fsm_state31)) begin
database_address1 = tmp_14_60_fu_2873_p1;
end else if ((1'b1 == ap_CS_fsm_state30)) begin
database_address1 = tmp_14_58_fu_2833_p1;
end else if ((1'b1 == ap_CS_fsm_state29)) begin
database_address1 = tmp_14_56_fu_2772_p1;
end else if ((1'b1 == ap_CS_fsm_state28)) begin
database_address1 = tmp_14_54_fu_2732_p1;
end else if ((1'b1 == ap_CS_fsm_state27)) begin
database_address1 = tmp_14_52_fu_2676_p1;
end else if ((1'b1 == ap_CS_fsm_state26)) begin
database_address1 = tmp_14_50_fu_2636_p1;
end else if ((1'b1 == ap_CS_fsm_state25)) begin
database_address1 = tmp_14_48_fu_2570_p1;
end else if ((1'b1 == ap_CS_fsm_state24)) begin
database_address1 = tmp_14_46_fu_2530_p1;
end else if ((1'b1 == ap_CS_fsm_state23)) begin
database_address1 = tmp_14_44_fu_2474_p1;
end else if ((1'b1 == ap_CS_fsm_state22)) begin
database_address1 = tmp_14_42_fu_2434_p1;
end else if ((1'b1 == ap_CS_fsm_state21)) begin
database_address1 = tmp_14_40_fu_2373_p1;
end else if ((1'b1 == ap_CS_fsm_state20)) begin
database_address1 = tmp_14_38_fu_2333_p1;
end else if ((1'b1 == ap_CS_fsm_state19)) begin
database_address1 = tmp_14_36_fu_2277_p1;
end else if ((1'b1 == ap_CS_fsm_state18)) begin
database_address1 = tmp_14_34_fu_2237_p1;
end else if ((1'b1 == ap_CS_fsm_state17)) begin
database_address1 = tmp_14_32_fu_2171_p1;
end else if ((1'b1 == ap_CS_fsm_state16)) begin
database_address1 = tmp_14_30_fu_2131_p1;
end else if ((1'b1 == ap_CS_fsm_state15)) begin
database_address1 = tmp_14_28_fu_2075_p1;
end else if ((1'b1 == ap_CS_fsm_state14)) begin
database_address1 = tmp_14_26_fu_2035_p1;
end else if ((1'b1 == ap_CS_fsm_state13)) begin
database_address1 = tmp_14_24_fu_1974_p1;
end else if ((1'b1 == ap_CS_fsm_state12)) begin
database_address1 = tmp_14_22_fu_1934_p1;
end else if ((1'b1 == ap_CS_fsm_state11)) begin
database_address1 = tmp_14_20_fu_1878_p1;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
database_address1 = tmp_14_18_fu_1838_p1;
end else if ((1'b1 == ap_CS_fsm_state9)) begin
database_address1 = tmp_14_16_fu_1772_p1;
end else if ((1'b1 == ap_CS_fsm_state8)) begin
database_address1 = tmp_14_14_fu_1732_p1;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
database_address1 = tmp_14_12_fu_1676_p1;
end else if ((1'b1 == ap_CS_fsm_state6)) begin
database_address1 = tmp_14_10_fu_1636_p1;
end else if ((1'b1 == ap_CS_fsm_state5)) begin
database_address1 = tmp_14_9_fu_1575_p1;
end else if ((1'b1 == ap_CS_fsm_state4)) begin
database_address1 = tmp_14_7_fu_1535_p1;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
database_address1 = tmp_14_5_fu_1479_p1;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
database_address1 = tmp_14_3_fu_1439_p1;
end else if ((1'b1 == ap_CS_fsm_state1)) begin
database_address1 = tmp_14_1_fu_1399_p1;
end else begin
database_address1 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state5) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state10) | (1'b1 == ap_CS_fsm_state11) | (1'b1 == ap_CS_fsm_state12) | (1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state14) | (1'b1 == ap_CS_fsm_state15) | (1'b1 == ap_CS_fsm_state16) | (1'b1 == ap_CS_fsm_state17) | (1'b1 == ap_CS_fsm_state18) | (1'b1 == ap_CS_fsm_state19) | (1'b1 == ap_CS_fsm_state20) | (1'b1 == ap_CS_fsm_state21) | (1'b1 == ap_CS_fsm_state22) | (1'b1 == ap_CS_fsm_state23) | (1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state28) | (1'b1 == ap_CS_fsm_state29) | (1'b1 == ap_CS_fsm_state30) | (1'b1 == ap_CS_fsm_state31) | (1'b1 == ap_CS_fsm_state32))) begin
database_ce0 = 1'b1;
end else begin
database_ce0 = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)) | (1'b1 == ap_CS_fsm_state2) | (1'b1 == ap_CS_fsm_state3) | (1'b1 == ap_CS_fsm_state4) | (1'b1 == ap_CS_fsm_state5) | (1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state7) | (1'b1 == ap_CS_fsm_state8) | (1'b1 == ap_CS_fsm_state9) | (1'b1 == ap_CS_fsm_state10) | (1'b1 == ap_CS_fsm_state11) | (1'b1 == ap_CS_fsm_state12) | (1'b1 == ap_CS_fsm_state13) | (1'b1 == ap_CS_fsm_state14) | (1'b1 == ap_CS_fsm_state15) | (1'b1 == ap_CS_fsm_state16) | (1'b1 == ap_CS_fsm_state17) | (1'b1 == ap_CS_fsm_state18) | (1'b1 == ap_CS_fsm_state19) | (1'b1 == ap_CS_fsm_state20) | (1'b1 == ap_CS_fsm_state21) | (1'b1 == ap_CS_fsm_state22) | (1'b1 == ap_CS_fsm_state23) | (1'b1 == ap_CS_fsm_state24) | (1'b1 == ap_CS_fsm_state25) | (1'b1 == ap_CS_fsm_state26) | (1'b1 == ap_CS_fsm_state27) | (1'b1 == ap_CS_fsm_state28) | (1'b1 == ap_CS_fsm_state29) | (1'b1 == ap_CS_fsm_state30) | (1'b1 == ap_CS_fsm_state31) | (1'b1 == ap_CS_fsm_state32))) begin
database_ce1 = 1'b1;
end else begin
database_ce1 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
ap_NS_fsm = ap_ST_fsm_state5;
end
ap_ST_fsm_state5 : begin
ap_NS_fsm = ap_ST_fsm_state6;
end
ap_ST_fsm_state6 : begin
ap_NS_fsm = ap_ST_fsm_state7;
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_state8;
end
ap_ST_fsm_state8 : begin
ap_NS_fsm = ap_ST_fsm_state9;
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state10;
end
ap_ST_fsm_state10 : begin
ap_NS_fsm = ap_ST_fsm_state11;
end
ap_ST_fsm_state11 : begin
ap_NS_fsm = ap_ST_fsm_state12;
end
ap_ST_fsm_state12 : begin
ap_NS_fsm = ap_ST_fsm_state13;
end
ap_ST_fsm_state13 : begin
ap_NS_fsm = ap_ST_fsm_state14;
end
ap_ST_fsm_state14 : begin
ap_NS_fsm = ap_ST_fsm_state15;
end
ap_ST_fsm_state15 : begin
ap_NS_fsm = ap_ST_fsm_state16;
end
ap_ST_fsm_state16 : begin
ap_NS_fsm = ap_ST_fsm_state17;
end
ap_ST_fsm_state17 : begin
ap_NS_fsm = ap_ST_fsm_state18;
end
ap_ST_fsm_state18 : begin
ap_NS_fsm = ap_ST_fsm_state19;
end
ap_ST_fsm_state19 : begin
ap_NS_fsm = ap_ST_fsm_state20;
end
ap_ST_fsm_state20 : begin
ap_NS_fsm = ap_ST_fsm_state21;
end
ap_ST_fsm_state21 : begin
ap_NS_fsm = ap_ST_fsm_state22;
end
ap_ST_fsm_state22 : begin
ap_NS_fsm = ap_ST_fsm_state23;
end
ap_ST_fsm_state23 : begin
ap_NS_fsm = ap_ST_fsm_state24;
end
ap_ST_fsm_state24 : begin
ap_NS_fsm = ap_ST_fsm_state25;
end
ap_ST_fsm_state25 : begin
ap_NS_fsm = ap_ST_fsm_state26;
end
ap_ST_fsm_state26 : begin
ap_NS_fsm = ap_ST_fsm_state27;
end
ap_ST_fsm_state27 : begin
ap_NS_fsm = ap_ST_fsm_state28;
end
ap_ST_fsm_state28 : begin
ap_NS_fsm = ap_ST_fsm_state29;
end
ap_ST_fsm_state29 : begin
ap_NS_fsm = ap_ST_fsm_state30;
end
ap_ST_fsm_state30 : begin
ap_NS_fsm = ap_ST_fsm_state31;
end
ap_ST_fsm_state31 : begin
ap_NS_fsm = ap_ST_fsm_state32;
end
ap_ST_fsm_state32 : begin
ap_NS_fsm = ap_ST_fsm_state33;
end
ap_ST_fsm_state33 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state10 = ap_CS_fsm[32'd9];
assign ap_CS_fsm_state11 = ap_CS_fsm[32'd10];
assign ap_CS_fsm_state12 = ap_CS_fsm[32'd11];
assign ap_CS_fsm_state13 = ap_CS_fsm[32'd12];
assign ap_CS_fsm_state14 = ap_CS_fsm[32'd13];
assign ap_CS_fsm_state15 = ap_CS_fsm[32'd14];
assign ap_CS_fsm_state16 = ap_CS_fsm[32'd15];
assign ap_CS_fsm_state17 = ap_CS_fsm[32'd16];
assign ap_CS_fsm_state18 = ap_CS_fsm[32'd17];
assign ap_CS_fsm_state19 = ap_CS_fsm[32'd18];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state20 = ap_CS_fsm[32'd19];
assign ap_CS_fsm_state21 = ap_CS_fsm[32'd20];
assign ap_CS_fsm_state22 = ap_CS_fsm[32'd21];
assign ap_CS_fsm_state23 = ap_CS_fsm[32'd22];
assign ap_CS_fsm_state24 = ap_CS_fsm[32'd23];
assign ap_CS_fsm_state25 = ap_CS_fsm[32'd24];
assign ap_CS_fsm_state26 = ap_CS_fsm[32'd25];
assign ap_CS_fsm_state27 = ap_CS_fsm[32'd26];
assign ap_CS_fsm_state28 = ap_CS_fsm[32'd27];
assign ap_CS_fsm_state29 = ap_CS_fsm[32'd28];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state30 = ap_CS_fsm[32'd29];
assign ap_CS_fsm_state31 = ap_CS_fsm[32'd30];
assign ap_CS_fsm_state32 = ap_CS_fsm[32'd31];
assign ap_CS_fsm_state33 = ap_CS_fsm[32'd32];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5];
assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd8];
assign found_1_s_fu_2969_p2 = (tmp32_fu_2964_p2 & tmp1_fu_2934_p2);
assign grp_fu_1336_p2 = ((contacts_q0 == database_q0) ? 1'b1 : 1'b0);
assign grp_fu_1342_p2 = ((contacts_q1 == database_q1) ? 1'b1 : 1'b0);
assign tmp10_fu_1793_p2 = (tmp14_fu_1787_p2 & tmp11_reg_3287);
assign tmp11_fu_1691_p2 = (tmp13_fu_1685_p2 & tmp12_fu_1681_p2);
assign tmp12_fu_1681_p2 = (tmp_15_8_reg_3237 & tmp_15_9_reg_3242);
assign tmp13_fu_1685_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp14_fu_1787_p2 = (tmp16_fu_1781_p2 & tmp15_fu_1777_p2);
assign tmp15_fu_1777_p2 = (tmp_15_11_reg_3292 & tmp_15_12_reg_3297);
assign tmp16_fu_1781_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp17_fu_2197_p2 = (tmp25_fu_2192_p2 & tmp18_reg_3452);
assign tmp18_fu_1995_p2 = (tmp22_fu_1989_p2 & tmp19_reg_3397);
assign tmp19_fu_1893_p2 = (tmp21_fu_1887_p2 & tmp20_fu_1883_p2);
assign tmp1_fu_2934_p2 = (tmp17_reg_3562 & tmp2_reg_3342);
assign tmp20_fu_1883_p2 = (tmp_15_15_reg_3347 & tmp_15_16_reg_3352);
assign tmp21_fu_1887_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp22_fu_1989_p2 = (tmp24_fu_1983_p2 & tmp23_fu_1979_p2);
assign tmp23_fu_1979_p2 = (tmp_15_19_reg_3402 & tmp_15_20_reg_3407);
assign tmp24_fu_1983_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp25_fu_2192_p2 = (tmp29_fu_2186_p2 & tmp26_reg_3507);
assign tmp26_fu_2090_p2 = (tmp28_fu_2084_p2 & tmp27_fu_2080_p2);
assign tmp27_fu_2080_p2 = (tmp_15_23_reg_3457 & tmp_15_24_reg_3462);
assign tmp28_fu_2084_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp29_fu_2186_p2 = (tmp31_fu_2180_p2 & tmp30_fu_2176_p2);
assign tmp2_fu_1798_p2 = (tmp10_fu_1793_p2 & tmp3_reg_3232);
assign tmp30_fu_2176_p2 = (tmp_15_27_reg_3512 & tmp_15_28_reg_3517);
assign tmp31_fu_2180_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp32_fu_2964_p2 = (tmp48_fu_2959_p2 & tmp33_reg_3782);
assign tmp33_fu_2596_p2 = (tmp41_fu_2591_p2 & tmp34_reg_3672);
assign tmp34_fu_2394_p2 = (tmp38_fu_2388_p2 & tmp35_reg_3617);
assign tmp35_fu_2292_p2 = (tmp37_fu_2286_p2 & tmp36_fu_2282_p2);
assign tmp36_fu_2282_p2 = (tmp_15_31_reg_3567 & tmp_15_32_reg_3572);
assign tmp37_fu_2286_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp38_fu_2388_p2 = (tmp40_fu_2382_p2 & tmp39_fu_2378_p2);
assign tmp39_fu_2378_p2 = (tmp_15_35_reg_3622 & tmp_15_36_reg_3627);
assign tmp3_fu_1596_p2 = (tmp7_fu_1590_p2 & tmp4_reg_3177);
assign tmp40_fu_2382_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp41_fu_2591_p2 = (tmp45_fu_2585_p2 & tmp42_reg_3727);
assign tmp42_fu_2489_p2 = (tmp44_fu_2483_p2 & tmp43_fu_2479_p2);
assign tmp43_fu_2479_p2 = (tmp_15_39_reg_3677 & tmp_15_40_reg_3682);
assign tmp44_fu_2483_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp45_fu_2585_p2 = (tmp47_fu_2579_p2 & tmp46_fu_2575_p2);
assign tmp46_fu_2575_p2 = (tmp_15_43_reg_3732 & tmp_15_44_reg_3737);
assign tmp47_fu_2579_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp48_fu_2959_p2 = (tmp56_fu_2954_p2 & tmp49_reg_3892);
assign tmp49_fu_2793_p2 = (tmp53_fu_2787_p2 & tmp50_reg_3837);
assign tmp4_fu_1494_p2 = (tmp6_fu_1488_p2 & tmp5_fu_1484_p2);
assign tmp50_fu_2691_p2 = (tmp52_fu_2685_p2 & tmp51_fu_2681_p2);
assign tmp51_fu_2681_p2 = (tmp_15_47_reg_3787 & tmp_15_48_reg_3792);
assign tmp52_fu_2685_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp53_fu_2787_p2 = (tmp55_fu_2781_p2 & tmp54_fu_2777_p2);
assign tmp54_fu_2777_p2 = (tmp_15_51_reg_3842 & tmp_15_52_reg_3847);
assign tmp55_fu_2781_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp56_fu_2954_p2 = (tmp60_fu_2948_p2 & tmp57_reg_3947);
assign tmp57_fu_2888_p2 = (tmp59_fu_2882_p2 & tmp58_fu_2878_p2);
assign tmp58_fu_2878_p2 = (tmp_15_55_reg_3897 & tmp_15_56_reg_3902);
assign tmp59_fu_2882_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp5_fu_1484_p2 = (tmp_15_reg_3127 & tmp_15_1_reg_3132);
assign tmp60_fu_2948_p2 = (tmp62_fu_2942_p2 & tmp61_fu_2938_p2);
assign tmp61_fu_2938_p2 = (tmp_15_59_reg_3952 & tmp_15_60_reg_3957);
assign tmp62_fu_2942_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp6_fu_1488_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp7_fu_1590_p2 = (tmp9_fu_1584_p2 & tmp8_fu_1580_p2);
assign tmp8_fu_1580_p2 = (tmp_15_4_reg_3182 & tmp_15_5_reg_3187);
assign tmp9_fu_1584_p2 = (grp_fu_1336_p2 & grp_fu_1342_p2);
assign tmp_11_10_fu_1621_p2 = (tmp_reg_2975 | 13'd11);
assign tmp_11_11_fu_1641_p2 = (tmp_reg_2975 | 13'd12);
assign tmp_11_12_fu_1661_p2 = (tmp_reg_2975 | 13'd13);
assign tmp_11_13_fu_1697_p2 = (tmp_reg_2975 | 13'd14);
assign tmp_11_14_fu_1717_p2 = (tmp_reg_2975 | 13'd15);
assign tmp_11_15_fu_1737_p2 = (tmp_reg_2975 | 13'd16);
assign tmp_11_16_fu_1757_p2 = (tmp_reg_2975 | 13'd17);
assign tmp_11_17_fu_1803_p2 = (tmp_reg_2975 | 13'd18);
assign tmp_11_18_fu_1823_p2 = (tmp_reg_2975 | 13'd19);
assign tmp_11_19_fu_1843_p2 = (tmp_reg_2975 | 13'd20);
assign tmp_11_1_fu_1404_p2 = (tmp_reg_2975 | 13'd2);
assign tmp_11_20_fu_1863_p2 = (tmp_reg_2975 | 13'd21);
assign tmp_11_21_fu_1899_p2 = (tmp_reg_2975 | 13'd22);
assign tmp_11_22_fu_1919_p2 = (tmp_reg_2975 | 13'd23);
assign tmp_11_23_fu_1939_p2 = (tmp_reg_2975 | 13'd24);
assign tmp_11_24_fu_1959_p2 = (tmp_reg_2975 | 13'd25);
assign tmp_11_25_fu_2000_p2 = (tmp_reg_2975 | 13'd26);
assign tmp_11_26_fu_2020_p2 = (tmp_reg_2975 | 13'd27);
assign tmp_11_27_fu_2040_p2 = (tmp_reg_2975 | 13'd28);
assign tmp_11_28_fu_2060_p2 = (tmp_reg_2975 | 13'd29);
assign tmp_11_29_fu_2096_p2 = (tmp_reg_2975 | 13'd30);
assign tmp_11_2_fu_1424_p2 = (tmp_reg_2975 | 13'd3);
assign tmp_11_30_fu_2116_p2 = (tmp_reg_2975 | 13'd31);
assign tmp_11_31_fu_2136_p2 = (tmp_reg_2975 | 13'd32);
assign tmp_11_32_fu_2156_p2 = (tmp_reg_2975 | 13'd33);
assign tmp_11_33_fu_2202_p2 = (tmp_reg_2975 | 13'd34);
assign tmp_11_34_fu_2222_p2 = (tmp_reg_2975 | 13'd35);
assign tmp_11_35_fu_2242_p2 = (tmp_reg_2975 | 13'd36);
assign tmp_11_36_fu_2262_p2 = (tmp_reg_2975 | 13'd37);
assign tmp_11_37_fu_2298_p2 = (tmp_reg_2975 | 13'd38);
assign tmp_11_38_fu_2318_p2 = (tmp_reg_2975 | 13'd39);
assign tmp_11_39_fu_2338_p2 = (tmp_reg_2975 | 13'd40);
assign tmp_11_3_fu_1444_p2 = (tmp_reg_2975 | 13'd4);
assign tmp_11_40_fu_2358_p2 = (tmp_reg_2975 | 13'd41);
assign tmp_11_41_fu_2399_p2 = (tmp_reg_2975 | 13'd42);
assign tmp_11_42_fu_2419_p2 = (tmp_reg_2975 | 13'd43);
assign tmp_11_43_fu_2439_p2 = (tmp_reg_2975 | 13'd44);
assign tmp_11_44_fu_2459_p2 = (tmp_reg_2975 | 13'd45);
assign tmp_11_45_fu_2495_p2 = (tmp_reg_2975 | 13'd46);
assign tmp_11_46_fu_2515_p2 = (tmp_reg_2975 | 13'd47);
assign tmp_11_47_fu_2535_p2 = (tmp_reg_2975 | 13'd48);
assign tmp_11_48_fu_2555_p2 = (tmp_reg_2975 | 13'd49);
assign tmp_11_49_fu_2601_p2 = (tmp_reg_2975 | 13'd50);
assign tmp_11_4_fu_1464_p2 = (tmp_reg_2975 | 13'd5);
assign tmp_11_50_fu_2621_p2 = (tmp_reg_2975 | 13'd51);
assign tmp_11_51_fu_2641_p2 = (tmp_reg_2975 | 13'd52);
assign tmp_11_52_fu_2661_p2 = (tmp_reg_2975 | 13'd53);
assign tmp_11_53_fu_2697_p2 = (tmp_reg_2975 | 13'd54);
assign tmp_11_54_fu_2717_p2 = (tmp_reg_2975 | 13'd55);
assign tmp_11_55_fu_2737_p2 = (tmp_reg_2975 | 13'd56);
assign tmp_11_56_fu_2757_p2 = (tmp_reg_2975 | 13'd57);
assign tmp_11_57_fu_2798_p2 = (tmp_reg_2975 | 13'd58);
assign tmp_11_58_fu_2818_p2 = (tmp_reg_2975 | 13'd59);
assign tmp_11_59_fu_2838_p2 = (tmp_reg_2975 | 13'd60);
assign tmp_11_5_fu_1500_p2 = (tmp_reg_2975 | 13'd6);
assign tmp_11_60_fu_2858_p2 = (tmp_reg_2975 | 13'd61);
assign tmp_11_61_fu_2894_p2 = (tmp_reg_2975 | 13'd62);
assign tmp_11_62_fu_2914_p2 = (tmp_reg_2975 | 13'd63);
assign tmp_11_6_fu_1520_p2 = (tmp_reg_2975 | 13'd7);
assign tmp_11_7_fu_1540_p2 = (tmp_reg_2975 | 13'd8);
assign tmp_11_8_fu_1560_p2 = (tmp_reg_2975 | 13'd9);
assign tmp_11_9_fu_1601_p2 = (tmp_reg_2975 | 13'd10);
assign tmp_11_s_fu_1382_p2 = (tmp_fu_1352_p3 | 13'd1);
assign tmp_127_fu_1348_p1 = contacts_index[6:0];
assign tmp_128_fu_1360_p1 = db_index[25:0];
assign tmp_12_10_fu_1626_p1 = tmp_11_10_fu_1621_p2;
assign tmp_12_11_fu_1646_p1 = tmp_11_11_fu_1641_p2;
assign tmp_12_12_fu_1666_p1 = tmp_11_12_fu_1661_p2;
assign tmp_12_13_fu_1702_p1 = tmp_11_13_fu_1697_p2;
assign tmp_12_14_fu_1722_p1 = tmp_11_14_fu_1717_p2;
assign tmp_12_15_fu_1742_p1 = tmp_11_15_fu_1737_p2;
assign tmp_12_16_fu_1762_p1 = tmp_11_16_fu_1757_p2;
assign tmp_12_17_fu_1808_p1 = tmp_11_17_fu_1803_p2;
assign tmp_12_18_fu_1828_p1 = tmp_11_18_fu_1823_p2;
assign tmp_12_19_fu_1848_p1 = tmp_11_19_fu_1843_p2;
assign tmp_12_1_fu_1388_p1 = tmp_11_s_fu_1382_p2;
assign tmp_12_20_fu_1868_p1 = tmp_11_20_fu_1863_p2;
assign tmp_12_21_fu_1904_p1 = tmp_11_21_fu_1899_p2;
assign tmp_12_22_fu_1924_p1 = tmp_11_22_fu_1919_p2;
assign tmp_12_23_fu_1944_p1 = tmp_11_23_fu_1939_p2;
assign tmp_12_24_fu_1964_p1 = tmp_11_24_fu_1959_p2;
assign tmp_12_25_fu_2005_p1 = tmp_11_25_fu_2000_p2;
assign tmp_12_26_fu_2025_p1 = tmp_11_26_fu_2020_p2;
assign tmp_12_27_fu_2045_p1 = tmp_11_27_fu_2040_p2;
assign tmp_12_28_fu_2065_p1 = tmp_11_28_fu_2060_p2;
assign tmp_12_29_fu_2101_p1 = tmp_11_29_fu_2096_p2;
assign tmp_12_2_fu_1409_p1 = tmp_11_1_fu_1404_p2;
assign tmp_12_30_fu_2121_p1 = tmp_11_30_fu_2116_p2;
assign tmp_12_31_fu_2141_p1 = tmp_11_31_fu_2136_p2;
assign tmp_12_32_fu_2161_p1 = tmp_11_32_fu_2156_p2;
assign tmp_12_33_fu_2207_p1 = tmp_11_33_fu_2202_p2;
assign tmp_12_34_fu_2227_p1 = tmp_11_34_fu_2222_p2;
assign tmp_12_35_fu_2247_p1 = tmp_11_35_fu_2242_p2;
assign tmp_12_36_fu_2267_p1 = tmp_11_36_fu_2262_p2;
assign tmp_12_37_fu_2303_p1 = tmp_11_37_fu_2298_p2;
assign tmp_12_38_fu_2323_p1 = tmp_11_38_fu_2318_p2;
assign tmp_12_39_fu_2343_p1 = tmp_11_39_fu_2338_p2;
assign tmp_12_3_fu_1429_p1 = tmp_11_2_fu_1424_p2;
assign tmp_12_40_fu_2363_p1 = tmp_11_40_fu_2358_p2;
assign tmp_12_41_fu_2404_p1 = tmp_11_41_fu_2399_p2;
assign tmp_12_42_fu_2424_p1 = tmp_11_42_fu_2419_p2;
assign tmp_12_43_fu_2444_p1 = tmp_11_43_fu_2439_p2;
assign tmp_12_44_fu_2464_p1 = tmp_11_44_fu_2459_p2;
assign tmp_12_45_fu_2500_p1 = tmp_11_45_fu_2495_p2;
assign tmp_12_46_fu_2520_p1 = tmp_11_46_fu_2515_p2;
assign tmp_12_47_fu_2540_p1 = tmp_11_47_fu_2535_p2;
assign tmp_12_48_fu_2560_p1 = tmp_11_48_fu_2555_p2;
assign tmp_12_49_fu_2606_p1 = tmp_11_49_fu_2601_p2;
assign tmp_12_4_fu_1449_p1 = tmp_11_3_fu_1444_p2;
assign tmp_12_50_fu_2626_p1 = tmp_11_50_fu_2621_p2;
assign tmp_12_51_fu_2646_p1 = tmp_11_51_fu_2641_p2;
assign tmp_12_52_fu_2666_p1 = tmp_11_52_fu_2661_p2;
assign tmp_12_53_fu_2702_p1 = tmp_11_53_fu_2697_p2;
assign tmp_12_54_fu_2722_p1 = tmp_11_54_fu_2717_p2;
assign tmp_12_55_fu_2742_p1 = tmp_11_55_fu_2737_p2;
assign tmp_12_56_fu_2762_p1 = tmp_11_56_fu_2757_p2;
assign tmp_12_57_fu_2803_p1 = tmp_11_57_fu_2798_p2;
assign tmp_12_58_fu_2823_p1 = tmp_11_58_fu_2818_p2;
assign tmp_12_59_fu_2843_p1 = tmp_11_59_fu_2838_p2;
assign tmp_12_5_fu_1469_p1 = tmp_11_4_fu_1464_p2;
assign tmp_12_60_fu_2863_p1 = tmp_11_60_fu_2858_p2;
assign tmp_12_61_fu_2899_p1 = tmp_11_61_fu_2894_p2;
assign tmp_12_62_fu_2919_p1 = tmp_11_62_fu_2914_p2;
assign tmp_12_6_fu_1505_p1 = tmp_11_5_fu_1500_p2;
assign tmp_12_7_fu_1525_p1 = tmp_11_6_fu_1520_p2;
assign tmp_12_8_fu_1545_p1 = tmp_11_7_fu_1540_p2;
assign tmp_12_9_fu_1565_p1 = tmp_11_8_fu_1560_p2;
assign tmp_12_fu_1372_p1 = tmp_fu_1352_p3;
assign tmp_12_s_fu_1606_p1 = tmp_11_9_fu_1601_p2;
assign tmp_13_10_fu_1631_p2 = (tmp_s_reg_3041 | 32'd11);
assign tmp_13_11_fu_1651_p2 = (tmp_s_reg_3041 | 32'd12);
assign tmp_13_12_fu_1671_p2 = (tmp_s_reg_3041 | 32'd13);
assign tmp_13_13_fu_1707_p2 = (tmp_s_reg_3041 | 32'd14);
assign tmp_13_14_fu_1727_p2 = (tmp_s_reg_3041 | 32'd15);
assign tmp_13_15_fu_1747_p2 = (tmp_s_reg_3041 | 32'd16);
assign tmp_13_16_fu_1767_p2 = (tmp_s_reg_3041 | 32'd17);
assign tmp_13_17_fu_1813_p2 = (tmp_s_reg_3041 | 32'd18);
assign tmp_13_18_fu_1833_p2 = (tmp_s_reg_3041 | 32'd19);
assign tmp_13_19_fu_1853_p2 = (tmp_s_reg_3041 | 32'd20);
assign tmp_13_1_fu_1414_p2 = (tmp_s_reg_3041 | 32'd2);
assign tmp_13_20_fu_1873_p2 = (tmp_s_reg_3041 | 32'd21);
assign tmp_13_21_fu_1909_p2 = (tmp_s_reg_3041 | 32'd22);
assign tmp_13_22_fu_1929_p2 = (tmp_s_reg_3041 | 32'd23);
assign tmp_13_23_fu_1949_p2 = (tmp_s_reg_3041 | 32'd24);
assign tmp_13_24_fu_1969_p2 = (tmp_s_reg_3041 | 32'd25);
assign tmp_13_25_fu_2010_p2 = (tmp_s_reg_3041 | 32'd26);
assign tmp_13_26_fu_2030_p2 = (tmp_s_reg_3041 | 32'd27);
assign tmp_13_27_fu_2050_p2 = (tmp_s_reg_3041 | 32'd28);
assign tmp_13_28_fu_2070_p2 = (tmp_s_reg_3041 | 32'd29);
assign tmp_13_29_fu_2106_p2 = (tmp_s_reg_3041 | 32'd30);
assign tmp_13_2_fu_1434_p2 = (tmp_s_reg_3041 | 32'd3);
assign tmp_13_30_fu_2126_p2 = (tmp_s_reg_3041 | 32'd31);
assign tmp_13_31_fu_2146_p2 = (tmp_s_reg_3041 | 32'd32);
assign tmp_13_32_fu_2166_p2 = (tmp_s_reg_3041 | 32'd33);
assign tmp_13_33_fu_2212_p2 = (tmp_s_reg_3041 | 32'd34);
assign tmp_13_34_fu_2232_p2 = (tmp_s_reg_3041 | 32'd35);
assign tmp_13_35_fu_2252_p2 = (tmp_s_reg_3041 | 32'd36);
assign tmp_13_36_fu_2272_p2 = (tmp_s_reg_3041 | 32'd37);
assign tmp_13_37_fu_2308_p2 = (tmp_s_reg_3041 | 32'd38);
assign tmp_13_38_fu_2328_p2 = (tmp_s_reg_3041 | 32'd39);
assign tmp_13_39_fu_2348_p2 = (tmp_s_reg_3041 | 32'd40);
assign tmp_13_3_fu_1454_p2 = (tmp_s_reg_3041 | 32'd4);
assign tmp_13_40_fu_2368_p2 = (tmp_s_reg_3041 | 32'd41);
assign tmp_13_41_fu_2409_p2 = (tmp_s_reg_3041 | 32'd42);
assign tmp_13_42_fu_2429_p2 = (tmp_s_reg_3041 | 32'd43);
assign tmp_13_43_fu_2449_p2 = (tmp_s_reg_3041 | 32'd44);
assign tmp_13_44_fu_2469_p2 = (tmp_s_reg_3041 | 32'd45);
assign tmp_13_45_fu_2505_p2 = (tmp_s_reg_3041 | 32'd46);
assign tmp_13_46_fu_2525_p2 = (tmp_s_reg_3041 | 32'd47);
assign tmp_13_47_fu_2545_p2 = (tmp_s_reg_3041 | 32'd48);
assign tmp_13_48_fu_2565_p2 = (tmp_s_reg_3041 | 32'd49);
assign tmp_13_49_fu_2611_p2 = (tmp_s_reg_3041 | 32'd50);
assign tmp_13_4_fu_1474_p2 = (tmp_s_reg_3041 | 32'd5);
assign tmp_13_50_fu_2631_p2 = (tmp_s_reg_3041 | 32'd51);
assign tmp_13_51_fu_2651_p2 = (tmp_s_reg_3041 | 32'd52);
assign tmp_13_52_fu_2671_p2 = (tmp_s_reg_3041 | 32'd53);
assign tmp_13_53_fu_2707_p2 = (tmp_s_reg_3041 | 32'd54);
assign tmp_13_54_fu_2727_p2 = (tmp_s_reg_3041 | 32'd55);
assign tmp_13_55_fu_2747_p2 = (tmp_s_reg_3041 | 32'd56);
assign tmp_13_56_fu_2767_p2 = (tmp_s_reg_3041 | 32'd57);
assign tmp_13_57_fu_2808_p2 = (tmp_s_reg_3041 | 32'd58);
assign tmp_13_58_fu_2828_p2 = (tmp_s_reg_3041 | 32'd59);
assign tmp_13_59_fu_2848_p2 = (tmp_s_reg_3041 | 32'd60);
assign tmp_13_5_fu_1510_p2 = (tmp_s_reg_3041 | 32'd6);
assign tmp_13_60_fu_2868_p2 = (tmp_s_reg_3041 | 32'd61);
assign tmp_13_61_fu_2904_p2 = (tmp_s_reg_3041 | 32'd62);
assign tmp_13_62_fu_2924_p2 = (tmp_s_reg_3041 | 32'd63);
assign tmp_13_6_fu_1530_p2 = (tmp_s_reg_3041 | 32'd7);
assign tmp_13_7_fu_1550_p2 = (tmp_s_reg_3041 | 32'd8);
assign tmp_13_8_fu_1570_p2 = (tmp_s_reg_3041 | 32'd9);
assign tmp_13_9_fu_1611_p2 = (tmp_s_reg_3041 | 32'd10);
assign tmp_13_s_fu_1393_p2 = (tmp_s_fu_1364_p3 | 32'd1);
assign tmp_14_10_fu_1636_p1 = $signed(tmp_13_10_fu_1631_p2);
assign tmp_14_11_fu_1656_p1 = $signed(tmp_13_11_fu_1651_p2);
assign tmp_14_12_fu_1676_p1 = $signed(tmp_13_12_fu_1671_p2);
assign tmp_14_13_fu_1712_p1 = $signed(tmp_13_13_fu_1707_p2);
assign tmp_14_14_fu_1732_p1 = $signed(tmp_13_14_fu_1727_p2);
assign tmp_14_15_fu_1752_p1 = $signed(tmp_13_15_fu_1747_p2);
assign tmp_14_16_fu_1772_p1 = $signed(tmp_13_16_fu_1767_p2);
assign tmp_14_17_fu_1818_p1 = $signed(tmp_13_17_fu_1813_p2);
assign tmp_14_18_fu_1838_p1 = $signed(tmp_13_18_fu_1833_p2);
assign tmp_14_19_fu_1858_p1 = $signed(tmp_13_19_fu_1853_p2);
assign tmp_14_1_fu_1399_p1 = $signed(tmp_13_s_fu_1393_p2);
assign tmp_14_20_fu_1878_p1 = $signed(tmp_13_20_fu_1873_p2);
assign tmp_14_21_fu_1914_p1 = $signed(tmp_13_21_fu_1909_p2);
assign tmp_14_22_fu_1934_p1 = $signed(tmp_13_22_fu_1929_p2);
assign tmp_14_23_fu_1954_p1 = $signed(tmp_13_23_fu_1949_p2);
assign tmp_14_24_fu_1974_p1 = $signed(tmp_13_24_fu_1969_p2);
assign tmp_14_25_fu_2015_p1 = $signed(tmp_13_25_fu_2010_p2);
assign tmp_14_26_fu_2035_p1 = $signed(tmp_13_26_fu_2030_p2);
assign tmp_14_27_fu_2055_p1 = $signed(tmp_13_27_fu_2050_p2);
assign tmp_14_28_fu_2075_p1 = $signed(tmp_13_28_fu_2070_p2);
assign tmp_14_29_fu_2111_p1 = $signed(tmp_13_29_fu_2106_p2);
assign tmp_14_2_fu_1419_p1 = $signed(tmp_13_1_fu_1414_p2);
assign tmp_14_30_fu_2131_p1 = $signed(tmp_13_30_fu_2126_p2);
assign tmp_14_31_fu_2151_p1 = $signed(tmp_13_31_fu_2146_p2);
assign tmp_14_32_fu_2171_p1 = $signed(tmp_13_32_fu_2166_p2);
assign tmp_14_33_fu_2217_p1 = $signed(tmp_13_33_fu_2212_p2);
assign tmp_14_34_fu_2237_p1 = $signed(tmp_13_34_fu_2232_p2);
assign tmp_14_35_fu_2257_p1 = $signed(tmp_13_35_fu_2252_p2);
assign tmp_14_36_fu_2277_p1 = $signed(tmp_13_36_fu_2272_p2);
assign tmp_14_37_fu_2313_p1 = $signed(tmp_13_37_fu_2308_p2);
assign tmp_14_38_fu_2333_p1 = $signed(tmp_13_38_fu_2328_p2);
assign tmp_14_39_fu_2353_p1 = $signed(tmp_13_39_fu_2348_p2);
assign tmp_14_3_fu_1439_p1 = $signed(tmp_13_2_fu_1434_p2);
assign tmp_14_40_fu_2373_p1 = $signed(tmp_13_40_fu_2368_p2);
assign tmp_14_41_fu_2414_p1 = $signed(tmp_13_41_fu_2409_p2);
assign tmp_14_42_fu_2434_p1 = $signed(tmp_13_42_fu_2429_p2);
assign tmp_14_43_fu_2454_p1 = $signed(tmp_13_43_fu_2449_p2);
assign tmp_14_44_fu_2474_p1 = $signed(tmp_13_44_fu_2469_p2);
assign tmp_14_45_fu_2510_p1 = $signed(tmp_13_45_fu_2505_p2);
assign tmp_14_46_fu_2530_p1 = $signed(tmp_13_46_fu_2525_p2);
assign tmp_14_47_fu_2550_p1 = $signed(tmp_13_47_fu_2545_p2);
assign tmp_14_48_fu_2570_p1 = $signed(tmp_13_48_fu_2565_p2);
assign tmp_14_49_fu_2616_p1 = $signed(tmp_13_49_fu_2611_p2);
assign tmp_14_4_fu_1459_p1 = $signed(tmp_13_3_fu_1454_p2);
assign tmp_14_50_fu_2636_p1 = $signed(tmp_13_50_fu_2631_p2);
assign tmp_14_51_fu_2656_p1 = $signed(tmp_13_51_fu_2651_p2);
assign tmp_14_52_fu_2676_p1 = $signed(tmp_13_52_fu_2671_p2);
assign tmp_14_53_fu_2712_p1 = $signed(tmp_13_53_fu_2707_p2);
assign tmp_14_54_fu_2732_p1 = $signed(tmp_13_54_fu_2727_p2);
assign tmp_14_55_fu_2752_p1 = $signed(tmp_13_55_fu_2747_p2);
assign tmp_14_56_fu_2772_p1 = $signed(tmp_13_56_fu_2767_p2);
assign tmp_14_57_fu_2813_p1 = $signed(tmp_13_57_fu_2808_p2);
assign tmp_14_58_fu_2833_p1 = $signed(tmp_13_58_fu_2828_p2);
assign tmp_14_59_fu_2853_p1 = $signed(tmp_13_59_fu_2848_p2);
assign tmp_14_5_fu_1479_p1 = $signed(tmp_13_4_fu_1474_p2);
assign tmp_14_60_fu_2873_p1 = $signed(tmp_13_60_fu_2868_p2);
assign tmp_14_61_fu_2909_p1 = $signed(tmp_13_61_fu_2904_p2);
assign tmp_14_62_fu_2929_p1 = $signed(tmp_13_62_fu_2924_p2);
assign tmp_14_6_fu_1515_p1 = $signed(tmp_13_5_fu_1510_p2);
assign tmp_14_7_fu_1535_p1 = $signed(tmp_13_6_fu_1530_p2);
assign tmp_14_8_fu_1555_p1 = $signed(tmp_13_7_fu_1550_p2);
assign tmp_14_9_fu_1575_p1 = $signed(tmp_13_8_fu_1570_p2);
assign tmp_14_fu_1377_p1 = $signed(tmp_s_fu_1364_p3);
assign tmp_14_s_fu_1616_p1 = $signed(tmp_13_9_fu_1611_p2);
assign tmp_fu_1352_p3 = {{tmp_127_fu_1348_p1}, {6'd0}};
assign tmp_s_fu_1364_p3 = {{tmp_128_fu_1360_p1}, {6'd0}};
always @ (posedge ap_clk) begin
tmp_reg_2975[5:0] <= 6'b000000;
tmp_s_reg_3041[5:0] <= 6'b000000;
end
endmodule //compare
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Dec 20 2013
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_phy_tempmon #
(
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100)
parameter TEMP_HYST = 1,
parameter TEMP_MIN_LIMIT = 12'h8ac,
parameter TEMP_MAX_LIMIT = 12'hca4
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;
// Temperature sampler FSM encoding
localparam IDLE = 11'b000_0000_0001;
localparam INIT = 11'b000_0000_0010;
localparam FOUR_INC = 11'b000_0000_0100;
localparam THREE_INC = 11'b000_0000_1000;
localparam TWO_INC = 11'b000_0001_0000;
localparam ONE_INC = 11'b000_0010_0000;
localparam NEUTRAL = 11'b000_0100_0000;
localparam ONE_DEC = 11'b000_1000_0000;
localparam TWO_DEC = 11'b001_0000_0000;
localparam THREE_DEC = 11'b010_0000_0000;
localparam FOUR_DEC = 11'b100_0000_0000;
//===========================================================================
// Reg declarations
//===========================================================================
// Output port flops. Inc and dec are mutex.
reg pi_f_dec; // Flop output
reg pi_f_inc; // Flop output
reg pi_f_dec_nxt; // FSM output
reg pi_f_inc_nxt; // FSM output
// FSM state
reg [10:0] tempmon_state;
reg [10:0] tempmon_state_nxt;
// FSM output used to capture the initial device termperature
reg tempmon_state_init;
// Flag to indicate the initial device temperature is captured and normal operation can begin
reg tempmon_init_complete;
// Temperature band/state boundaries
reg [11:0] four_inc_max_limit;
reg [11:0] three_inc_max_limit;
reg [11:0] two_inc_max_limit;
reg [11:0] one_inc_max_limit;
reg [11:0] neutral_max_limit;
reg [11:0] one_dec_max_limit;
reg [11:0] two_dec_max_limit;
reg [11:0] three_dec_max_limit;
reg [11:0] three_inc_min_limit;
reg [11:0] two_inc_min_limit;
reg [11:0] one_inc_min_limit;
reg [11:0] neutral_min_limit;
reg [11:0] one_dec_min_limit;
reg [11:0] two_dec_min_limit;
reg [11:0] three_dec_min_limit;
reg [11:0] four_dec_min_limit;
reg [11:0] device_temp_init;
// Flops for capturing and storing the current device temperature
reg tempmon_sample_en_101;
reg tempmon_sample_en_102;
reg [11:0] device_temp_101;
reg [11:0] device_temp_capture_102;
reg update_temp_102;
// Flops for comparing temperature to max limits
reg temp_cmp_four_inc_max_102;
reg temp_cmp_three_inc_max_102;
reg temp_cmp_two_inc_max_102;
reg temp_cmp_one_inc_max_102;
reg temp_cmp_neutral_max_102;
reg temp_cmp_one_dec_max_102;
reg temp_cmp_two_dec_max_102;
reg temp_cmp_three_dec_max_102;
// Flops for comparing temperature to min limits
reg temp_cmp_three_inc_min_102;
reg temp_cmp_two_inc_min_102;
reg temp_cmp_one_inc_min_102;
reg temp_cmp_neutral_min_102;
reg temp_cmp_one_dec_min_102;
reg temp_cmp_two_dec_min_102;
reg temp_cmp_three_dec_min_102;
reg temp_cmp_four_dec_min_102;
//===========================================================================
// Overview and temperature band limits
//===========================================================================
// The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM
// has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or
// decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are
// offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state
// and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when
// the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above
// 125C will never be entered.
// Temperature lowest highest
// <------------------------------------------------------------------------------------------------------------------------------------------------>
//
// Temp four three two one neutral one two three four
// band/state inc inc inc inc dec dec dec dec
//
// Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|
// Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |
// | | | | | | |
// | | | | | | |
// three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |
// | device_temp_init |
// four_inc_max_limit three_dec_max_limit
// Boundaries for moving from lower temp bands to higher temp bands.
// Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,
// and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.
wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band
wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;
wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;
wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET;
wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band
wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;
wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;
wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band
wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];
// Boundaries for moving from higher temp bands to lower temp bands
wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band
wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;
wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;
wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band
wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;
wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;
wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;
wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band
//===========================================================================
// Capture device temperature
//===========================================================================
// There is a three stage pipeline used to capture temperature, calculate the next state
// of the FSM, and update the tempmon outputs.
//
// Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.
// Input device_temp is compared to ADC codes for 0C and 125C and limited
// at the flop input if needed.
//
// Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries
// to determine if a state change is needed. State changes are only enabled on the
// rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser
// increment or decrement signal is generated and flopped.
//
// Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.
// Limit device_temp to 0C to 125C and assign it to flop input device_temp_100
// temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15
wire device_temp_high = device_temp > TEMP_MAX_LIMIT;
wire device_temp_low = device_temp < TEMP_MIN_LIMIT;
wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )
| ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )
| ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp );
// Capture/hold the initial temperature used in setting temperature bands and set init complete flag
// to enable normal sample operation.
wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;
wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;
// Capture/hold the current temperature on the sample enable signal rising edge after init is complete.
// The captured current temp is not used functionaly. It is just useful for debug and waveform review.
wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;
wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;
//===========================================================================
// Generate FSM arc signals
//===========================================================================
// Temperature comparisons for increasing temperature.
wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;
wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;
wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;
wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;
wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;
wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;
wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;
wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;
// Temperature comparisons for decreasing temperature.
wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;
wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;
wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;
wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;
wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;
wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;
wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;
wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;
// FSM arcs for increasing temperature.
wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;
wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;
wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;
wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;
wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;
wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;
wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;
wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;
// FSM arcs for decreasing temperature.
wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;
wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;
wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;
wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;
wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;
wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;
wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;
wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;
//===========================================================================
// Implement FSM
//===========================================================================
// In addition to the nine temperature states, there are also IDLE and INIT states.
// The INIT state triggers the calculation of the temperature boundaries between the
// other states. After INIT, the FSM will always go to the NEUTRAL state. There is
// no timing restriction required between calib_complete and tempmon_sample_en.
always @(*) begin
tempmon_state_nxt = tempmon_state;
tempmon_state_init = 1'b0;
pi_f_inc_nxt = 1'b0;
pi_f_dec_nxt = 1'b0;
casez (tempmon_state)
IDLE: begin
if (calib_complete) tempmon_state_nxt = INIT;
end
INIT: begin
tempmon_state_nxt = NEUTRAL;
tempmon_state_init = 1'b1;
end
FOUR_INC: begin
if (temp_gte_four_inc_max) begin
tempmon_state_nxt = THREE_INC;
pi_f_dec_nxt = 1'b1;
end
end
THREE_INC: begin
if (temp_gte_three_inc_max) begin
tempmon_state_nxt = TWO_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_inc_min) begin
tempmon_state_nxt = FOUR_INC;
pi_f_inc_nxt = 1'b1;
end
end
TWO_INC: begin
if (temp_gte_two_inc_max) begin
tempmon_state_nxt = ONE_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_inc_min) begin
tempmon_state_nxt = THREE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_INC: begin
if (temp_gte_one_inc_max) begin
tempmon_state_nxt = NEUTRAL;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_inc_min) begin
tempmon_state_nxt = TWO_INC;
pi_f_inc_nxt = 1'b1;
end
end
NEUTRAL: begin
if (temp_gte_neutral_max) begin
tempmon_state_nxt = ONE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_neutral_min) begin
tempmon_state_nxt = ONE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_DEC: begin
if (temp_gte_one_dec_max) begin
tempmon_state_nxt = TWO_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_dec_min) begin
tempmon_state_nxt = NEUTRAL;
pi_f_inc_nxt = 1'b1;
end
end
TWO_DEC: begin
if (temp_gte_two_dec_max) begin
tempmon_state_nxt = THREE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_dec_min) begin
tempmon_state_nxt = ONE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
THREE_DEC: begin
if (temp_gte_three_dec_max) begin
tempmon_state_nxt = FOUR_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_dec_min) begin
tempmon_state_nxt = TWO_DEC;
pi_f_inc_nxt = 1'b1;
end
end
FOUR_DEC: begin
if (temp_lte_four_dec_min) begin
tempmon_state_nxt = THREE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
default: begin
tempmon_state_nxt = IDLE;
end
endcase
end //always
//synopsys translate_off
reg [71:0] tempmon_state_name;
always @(*) casez (tempmon_state)
IDLE : tempmon_state_name = "IDLE";
INIT : tempmon_state_name = "INIT";
FOUR_INC : tempmon_state_name = "FOUR_INC";
THREE_INC : tempmon_state_name = "THREE_INC";
TWO_INC : tempmon_state_name = "TWO_INC";
ONE_INC : tempmon_state_name = "ONE_INC";
NEUTRAL : tempmon_state_name = "NEUTRAL";
ONE_DEC : tempmon_state_name = "ONE_DEC";
TWO_DEC : tempmon_state_name = "TWO_DEC";
THREE_DEC : tempmon_state_name = "THREE_DEC";
FOUR_DEC : tempmon_state_name = "FOUR_DEC";
default : tempmon_state_name = "BAD_STATE";
endcase
//synopsys translate_on
//===========================================================================
// Generate final output and implement flops
//===========================================================================
// Generate output
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;
// Implement reset flops
always @(posedge clk) begin
if(rst) begin
tempmon_state <= #TCQ 11'b000_0000_0001;
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
four_inc_max_limit <= #TCQ 12'b0;
three_inc_max_limit <= #TCQ 12'b0;
two_inc_max_limit <= #TCQ 12'b0;
one_inc_max_limit <= #TCQ 12'b0;
neutral_max_limit <= #TCQ 12'b0;
one_dec_max_limit <= #TCQ 12'b0;
two_dec_max_limit <= #TCQ 12'b0;
three_dec_max_limit <= #TCQ 12'b0;
three_inc_min_limit <= #TCQ 12'b0;
two_inc_min_limit <= #TCQ 12'b0;
one_inc_min_limit <= #TCQ 12'b0;
neutral_min_limit <= #TCQ 12'b0;
one_dec_min_limit <= #TCQ 12'b0;
two_dec_min_limit <= #TCQ 12'b0;
three_dec_min_limit <= #TCQ 12'b0;
four_dec_min_limit <= #TCQ 12'b0;
device_temp_init <= #TCQ 12'b0;
tempmon_init_complete <= #TCQ 1'b0;
tempmon_sample_en_101 <= #TCQ 1'b0;
tempmon_sample_en_102 <= #TCQ 1'b0;
device_temp_101 <= #TCQ 12'b0;
device_temp_capture_102 <= #TCQ 12'b0;
end
else begin
tempmon_state <= #TCQ tempmon_state_nxt;
pi_f_inc <= #TCQ pi_f_inc_nxt;
pi_f_dec <= #TCQ pi_f_dec_nxt;
four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;
three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;
two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;
one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;
neutral_max_limit <= #TCQ neutral_max_limit_nxt;
one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;
two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;
three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;
three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;
two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;
one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;
neutral_min_limit <= #TCQ neutral_min_limit_nxt;
one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;
two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;
three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;
four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;
device_temp_init <= #TCQ device_temp_init_nxt;
tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;
tempmon_sample_en_101 <= #TCQ tempmon_sample_en;
tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;
device_temp_101 <= #TCQ device_temp_100;
device_temp_capture_102 <= #TCQ device_temp_capture_101;
end
end
// Implement non-reset flops
always @(posedge clk) begin
temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;
temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;
temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;
temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;
temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;
temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;
temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;
temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;
temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;
temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;
temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;
temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;
temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;
temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;
temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;
temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;
update_temp_102 <= #TCQ update_temp_101;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_intfloat_conv ////
//// Floating Point Post Normalisation Unit ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// Modified by Julius Baxter, July, 2010 ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module fpu_post_norm_intfloat_conv
(
clk, rst, fpu_op, opas, sign, rmode, fract_in,
exp_in, opa_dn, opa_nan, opa_inf, opb_dn, out,
ine, inv, overflow, underflow, f2i_out_sign
);
input clk;
input rst;
input [2:0] fpu_op;
input opas;
input sign;
input [1:0] rmode;
input [47:0] fract_in;
input [7:0] exp_in;
input opa_dn, opb_dn;
input opa_nan, opa_inf;
output [30:0] out;
output ine, inv;
output overflow, underflow;
output f2i_out_sign;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
/*wire*/ reg [22:0] fract_out;
/*wire*/reg [7:0] exp_out;
wire [30:0] out;
wire exp_out1_co, overflow, underflow;
wire [22:0] fract_out_final;
reg [22:0] fract_out_rnd;
wire [8:0] exp_next_mi;
wire dn;
wire exp_rnd_adj;
wire [7:0] exp_out_final;
reg [7:0] exp_out_rnd;
wire op_dn = opa_dn | opb_dn;
wire op_mul = fpu_op[2:0]==3'b010;
wire op_div = fpu_op[2:0]==3'b011;
wire op_i2f = fpu_op[2:0]==3'b100;
wire op_f2i = fpu_op[2:0]==3'b101;
reg [5:0] fi_ldz;
wire g, r, s;
wire round, round2, round2a, round2_fasu, round2_fmul;
wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a;
wire [22:0] fract_out_rnd0, fract_out_rnd1, fract_out_rnd2,
fract_out_rnd2a;
wire exp_rnd_adj0, exp_rnd_adj2a;
wire r_sign;
wire ovf0, ovf1;
wire [23:0] fract_out_pl1;
wire [7:0] exp_out_pl1, exp_out_mi1;
wire exp_out_00, exp_out_fe, exp_out_ff, exp_in_00,
exp_in_ff;
wire exp_out_final_ff, fract_out_7fffff;
/*wire*/reg [24:0] fract_trunc;
wire [7:0] exp_out1;
wire grs_sel;
wire fract_out_00;
reg fract_in_00;
wire shft_co;
wire [8:0] exp_in_pl1, exp_in_mi1;
wire [47:0] fract_in_shftr;
wire [47:0] fract_in_shftl;
wire [7:0] shft2;
wire [7:0] exp_out1_mi1;
wire [6:0] fi_ldz_2a;
wire [7:0] fi_ldz_2;
wire left_right;
wire [7:0] shift_right;
wire [7:0] shift_left;
wire [7:0] fasu_shift;
wire [5:0] fi_ldz_mi1;
wire [5:0] fi_ldz_mi22;
wire [6:0] ldz_all;
wire [7:0] f2i_shft;
wire [55:0] exp_f2i_1;
wire f2i_zero, f2i_max;
wire [7:0] f2i_emin;
wire f2i_exp_gt_max ,f2i_exp_lt_min;
wire [7:0] conv_shft;
wire [7:0] exp_i2f, exp_f2i, conv_exp;
wire round2_f2i;
////////////////////////////////////////////////////////////////////////
//
// Normalize and Round Logic
//
// ---------------------------------------------------------------------
// Count Leading zeros in fraction
always @(/*fract_in*/ posedge clk or posedge rst)
if (rst)
fi_ldz <= 0;
else
casez(fract_in) // synopsys full_case parallel_case
48'b1???????????????????????????????????????????????: fi_ldz <= 1;
48'b01??????????????????????????????????????????????: fi_ldz <= 2;
48'b001?????????????????????????????????????????????: fi_ldz <= 3;
48'b0001????????????????????????????????????????????: fi_ldz <= 4;
48'b00001???????????????????????????????????????????: fi_ldz <= 5;
48'b000001??????????????????????????????????????????: fi_ldz <= 6;
48'b0000001?????????????????????????????????????????: fi_ldz <= 7;
48'b00000001????????????????????????????????????????: fi_ldz <= 8;
48'b000000001???????????????????????????????????????: fi_ldz <= 9;
48'b0000000001??????????????????????????????????????: fi_ldz <= 10;
48'b00000000001?????????????????????????????????????: fi_ldz <= 11;
48'b000000000001????????????????????????????????????: fi_ldz <= 12;
48'b0000000000001???????????????????????????????????: fi_ldz <= 13;
48'b00000000000001??????????????????????????????????: fi_ldz <= 14;
48'b000000000000001?????????????????????????????????: fi_ldz <= 15;
48'b0000000000000001????????????????????????????????: fi_ldz <= 16;
48'b00000000000000001???????????????????????????????: fi_ldz <= 17;
48'b000000000000000001??????????????????????????????: fi_ldz <= 18;
48'b0000000000000000001?????????????????????????????: fi_ldz <= 19;
48'b00000000000000000001????????????????????????????: fi_ldz <= 20;
48'b000000000000000000001???????????????????????????: fi_ldz <= 21;
48'b0000000000000000000001??????????????????????????: fi_ldz <= 22;
48'b00000000000000000000001?????????????????????????: fi_ldz <= 23;
48'b000000000000000000000001????????????????????????: fi_ldz <= 24;
48'b0000000000000000000000001???????????????????????: fi_ldz <= 25;
48'b00000000000000000000000001??????????????????????: fi_ldz <= 26;
48'b000000000000000000000000001?????????????????????: fi_ldz <= 27;
48'b0000000000000000000000000001????????????????????: fi_ldz <= 28;
48'b00000000000000000000000000001???????????????????: fi_ldz <= 29;
48'b000000000000000000000000000001??????????????????: fi_ldz <= 30;
48'b0000000000000000000000000000001?????????????????: fi_ldz <= 31;
48'b00000000000000000000000000000001????????????????: fi_ldz <= 32;
48'b000000000000000000000000000000001???????????????: fi_ldz <= 33;
48'b0000000000000000000000000000000001??????????????: fi_ldz <= 34;
48'b00000000000000000000000000000000001?????????????: fi_ldz <= 35;
48'b000000000000000000000000000000000001????????????: fi_ldz <= 36;
48'b0000000000000000000000000000000000001???????????: fi_ldz <= 37;
48'b00000000000000000000000000000000000001??????????: fi_ldz <= 38;
48'b000000000000000000000000000000000000001?????????: fi_ldz <= 39;
48'b0000000000000000000000000000000000000001????????: fi_ldz <= 40;
48'b00000000000000000000000000000000000000001???????: fi_ldz <= 41;
48'b000000000000000000000000000000000000000001??????: fi_ldz <= 42;
48'b0000000000000000000000000000000000000000001?????: fi_ldz <= 43;
48'b00000000000000000000000000000000000000000001????: fi_ldz <= 44;
48'b000000000000000000000000000000000000000000001???: fi_ldz <= 45;
48'b0000000000000000000000000000000000000000000001??: fi_ldz <= 46;
48'b00000000000000000000000000000000000000000000001?: fi_ldz <= 47;
48'b00000000000000000000000000000000000000000000000?: fi_ldz <= 48;
endcase
// ---------------------------------------------------------------------
// Normalize
wire exp_in_80;
wire rmode_00, rmode_01, rmode_10, rmode_11;
// Misc common signals
assign exp_in_ff = &exp_in;
assign exp_in_00 = !(|exp_in);
assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]);
assign exp_out_ff = &exp_out;
assign exp_out_00 = !(|exp_out);
assign exp_out_fe = &exp_out[7:1] & !exp_out[0];
assign exp_out_final_ff = &exp_out_final;
assign fract_out_7fffff = &fract_out;
assign fract_out_00 = !(|fract_out);
//assign fract_in_00 = !(|fract_in);
always @(posedge clk or posedge rst)
if (rst)
fract_in_00 <= 1'b0;
else
fract_in_00 <= !(|fract_in);
assign rmode_00 = (rmode==2'b00);
assign rmode_01 = (rmode==2'b01);
assign rmode_10 = (rmode==2'b10);
assign rmode_11 = (rmode==2'b11);
// Fasu Output will be denormalized ...
assign dn = !op_mul & !op_div &
(exp_in_00 | (exp_next_mi[8] & !fract_in[47]) );
// ---------------------------------------------------------------------
// Fraction Normalization
parameter f2i_emax = 8'h9d;
// Special Signals for f2i
assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f;
assign f2i_exp_gt_max = (exp_in > f2i_emax);
assign f2i_exp_lt_min = (exp_in < f2i_emin);
// Incremented fraction for rounding
assign fract_out_pl1 = fract_out + 24'd1;
/*
assign f2i_zero = (!opas & (exp_in<f2i_emin)) |
(opas & (exp_in>f2i_emax)) |
(opas & (exp_in<f2i_emin) & (fract_in_00 | !rmode_11));
assign f2i_max = (!opas & (exp_in>f2i_emax)) |
(opas & (exp_in<f2i_emin) & !fract_in_00 & rmode_11);
*/
// Zero when :
// a) too small exp. and positive sign - result will be 0
// b) too big exp. and negative sign - result will be largest possible -int
// c) -infinity: largest possible -int
// d) -0.0: give positive 0
assign f2i_zero = (
( (f2i_exp_lt_min & (opas & (!rmode_11 | fract_in_00))) |
(f2i_exp_lt_min & !opas) |
(f2i_exp_gt_max & opas) )
& !(&exp_in)
) |
// -inf case
(opa_inf & opas) |
// -0.0 case
(fract_in_00 & exp_in_00);
// Maximum :
// a) too big exp and positive sign - result will be maximum int.
// b) rounding negative down and less than minimum expon. for int = -1
// c) +/- NaN or +inf - result will be maximum int
// d) disabled when the -0.0 case comes up
assign f2i_max = (
( ((!opas & f2i_exp_gt_max) |
(f2i_exp_lt_min & !fract_in_00 & rmode_11 & opas))
& !(&exp_in)) |
// Either +/- NaN, or +inf
(opa_nan | (opa_inf & !opas))) &
// .. and NOT -0.0( 0x80000000)
!(opas & fract_in_00 & exp_in_00);
// Claculate various shifting options
assign f2i_shft = exp_in-8'h7d;
assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz};
assign fract_in_shftl = (|conv_shft[7:6] | (f2i_zero & op_f2i)) ?
0 : fract_in<<conv_shft[5:0];
// Final fraction output
always @(posedge clk or posedge rst)
if (rst)
begin
fract_out <= 1'b0;
fract_trunc <= 'd0;
end
else
{fract_out,fract_trunc} <= fract_in_shftl;
// ---------------------------------------------------------------------
// Exponent Normalization
assign fi_ldz_mi1 = fi_ldz - 6'd1;
assign fi_ldz_mi22 = fi_ldz - 6'd22;
assign exp_out_pl1 = exp_out + 8'd1;
assign exp_out_mi1 = exp_out - 8'd1;
assign exp_in_pl1 = exp_in + 9'd1; // 9 bits - includes carry out
assign exp_in_mi1 = exp_in - 9'd1; // 9 bits - includes carry out
assign exp_out1_mi1 = exp_out1 - 8'd1;
assign exp_next_mi = exp_in_pl1 -
{3'd0,fi_ldz_mi1}; // 9 bits - includes carry out
assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
// Only ever force positive if:
// i) It's a NaN
// ii) It's zero and not -inf
// iii) We've rounded to 0 (both fract and exp out are 0 and not forced)
// Force to 1 (negative) when have negative sign with too big exponent
assign f2i_out_sign = (opas & (exp_in>f2i_emax) & f2i_zero) ?
1'b1 : opa_nan | (f2i_zero & !f2i_max & !(opa_inf & opas))
| (!(|out) & !f2i_zero)
?
1'b0 :opas;
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 1'b0) : (8'h9e-{2'd0,fi_ldz});
assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
assign exp_f2i = f2i_zero ? 1'b0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
//assign exp_out = conv_exp;
always @(posedge clk or posedge rst)
if (rst)
exp_out <= 'd0;
else
exp_out <= conv_exp;
assign ldz_all = {1'b0,fi_ldz};
assign fi_ldz_2a = 6'd23 - fi_ldz;
assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
// ---------------------------------------------------------------------
// Round
// Extract rounding (GRS) bits
assign g = fract_out[0];
assign r = fract_trunc[24];
assign s = |fract_trunc[23:0];
// Round to nearest even
assign round = (g & r) | (r & s) ;
assign {exp_rnd_adj0, fract_out_rnd0} = round ?
fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out;
assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i;
// round to zero
// Added detection of sign and rounding up in case of negative ftoi! - JPB
assign fract_out_rnd1 = (exp_out_ff & !dn & !op_f2i) ?
23'h7fffff :
(op_f2i & (|fract_trunc) & opas) ?
fract_out_pl1[22:0] : fract_out ;
assign exp_out_rnd1 = (g & r & s & exp_in_ff) ?
exp_next_mi[7:0] : (exp_out_ff & !op_f2i) ?
exp_in :
(op_f2i & opas & (|fract_trunc) & fract_out_pl1[23]) ?
exp_out_pl1: exp_out;
assign ovf1 = exp_out_ff & !dn;
// round to +inf (UP) and -inf (DOWN)
assign r_sign = sign;
assign round2a = !exp_out_fe | !fract_out_7fffff |
(exp_out_fe & fract_out_7fffff);
assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] |
(exp_out[7] & round2a));
assign round2_f2i = rmode_10 &
(( |fract_in[23:0] & !opas & (exp_in<8'h80 )) |
(|fract_trunc));
assign round2 = op_f2i ? round2_f2i : round2_fasu;
assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 :
{1'b0, fract_out};
assign exp_out_rnd2a = exp_rnd_adj2a ? exp_out_pl1 : exp_out;
assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ?
23'h7fffff : fract_out_rnd2a;
assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ?
8'hfe : exp_out_rnd2a;
// Choose rounding mode
always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2)
case(rmode) // synopsys full_case parallel_case
0: exp_out_rnd = exp_out_rnd0;
1: exp_out_rnd = exp_out_rnd1;
2,3: exp_out_rnd = exp_out_rnd2;
endcase
always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2)
case(rmode) // synopsys full_case parallel_case
0: fract_out_rnd = fract_out_rnd0;
1: fract_out_rnd = fract_out_rnd1;
2,3: fract_out_rnd = fract_out_rnd2;
endcase
// ---------------------------------------------------------------------
// Final Output Mux
// Fix Output for denormalized and special numbers
assign fract_out_final = ovf0 ? 23'h0 :
(f2i_max & op_f2i) ? 23'h7fffff :
fract_out_rnd;
assign exp_out_final = (f2i_max & op_f2i) ? 8'hff : exp_out_rnd;
// ---------------------------------------------------------------------
// Pack Result
assign out = {exp_out_final, fract_out_final};
// ---------------------------------------------------------------------
// Exceptions
assign underflow = (!fract_in[47] & exp_out1_co) & !dn;
assign overflow = ovf0 | ovf1;
wire f2i_ine;
wire exp_in_lt_half = (exp_in<8'h80);
assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) |
(|fract_trunc) |
(f2i_zero & exp_in_lt_half & opas & !fract_in_00) |
(f2i_max & rmode_11 & (exp_in<8'h80));
assign ine = op_f2i ? f2i_ine :
op_i2f ? (|fract_trunc) :
((r & !dn) | (s & !dn) );
assign inv = op_f2i & (exp_in > f2i_emax);
endmodule // fpu_post_norm_intfloat_conv
|
/*
* Verilog-A math library test code for Icarus Verilog.
* http://www.icarus.com/eda/verilog/
*
* Copyright (C) 2007-2009 Cary R. ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/*
* As of Dec. 2009 some systems have started returning the sign of
* a NaN, because of this we can for some conditions get -nan. This
* will cause mismatches with the gold file. Alan M. Feldstein
* suggested on the iverilog-devel mailing list that we use fabs
* (abs()) since C99 speifies that it will remove the sign of the
* NaN. This appears to work, so I wrapped all functions that we
* expect to return NaN with a call to abs().
*/
// Get the Verilog-A constants.
`include "constants.vams"
module top;
real zero, mzero, pinf, minf, nan;
initial begin
// Define a few constants.
zero = 0.0;
mzero = -1.0 * zero;
pinf = 1/0.0;
minf = ln(0);
nan = abs(sqrt(-1.0));
$display("Using +0 = %f, -0 = %f, nan = %f, inf = %f and -inf = %f.\n",
zero, mzero, nan, pinf, minf);
// Check that the comparisons used to detection a NaN work correctly.
if (nan != nan) $display("NaN != comparison works correctly.");
else $display("NaN != comparison failed.");
if (nan == nan) $display("NaN == comparison failed.\n");
else $display("NaN == comparison works correctly.\n");
check_sqrt;
$display("");
check_ln;
$display("");
check_log;
$display("");
check_exp;
$display("");
check_abs;
$display("");
check_ceil;
$display("");
check_floor;
$display("");
check_sin;
$display("");
check_cos;
$display("");
check_tan;
$display("");
check_asin;
$display("");
check_acos;
$display("");
check_atan;
$display("");
check_sinh;
$display("");
check_cosh;
$display("");
check_tanh;
$display("");
check_asinh;
$display("");
check_acosh;
$display("");
check_atanh;
$display("");
check_min;
$display("");
check_max;
$display("");
check_pow;
$display("");
check_atan2;
$display("");
check_hypot;
$display("");
check_constants;
end
// Task to check the square root function.
task check_sqrt;
begin
$display("--- Checking the sqrt function ---");
$display("The square root of 2.0 is %f.", sqrt(2.0));
$display("The square root of 1.0 is %f.", sqrt(1.0));
$display("The square root of 0.0 is %f.", sqrt(zero));
$display("The square root of -0.0 is %f.", sqrt(mzero));
$display("The square root of -1.0 is %f.", abs(sqrt(-1.0)));
$display("The square root of inf is %f.", sqrt(pinf));
$display("The square root of -inf is %f.", abs(sqrt(minf)));
$display("The square root of nan is %f.", abs(sqrt(nan)));
end
endtask
// Task to check the natural log function.
task check_ln;
begin
$display("--- Checking the ln function ---");
$display("The natural log of 10.0 is %f.", ln(10.0));
$display("The natural log of 1.0 is %f.", ln(1.0));
$display("The natural log of 0.5 is %f.", ln(0.5));
$display("The natural log of 0.0 is %f.", ln(zero));
$display("The natural log of -0.0 is %f.", ln(mzero));
$display("The natural log of -1.0 is %f.", abs(ln(-1.0)));
$display("The natural log of inf is %f.", ln(pinf));
$display("The natural log of -inf is %f.", abs(ln(minf)));
$display("The natural log of nan is %f.", abs(ln(nan)));
end
endtask
// Task to check the log base 10 function.
task check_log;
begin
$display("--- Checking the log function ---");
$display("The log base 10 of 10.0 is %f.", log(10.0));
$display("The log base 10 of 1.0 is %f.", log(1.0));
$display("The log base 10 of 0.5 is %f.", log(0.5));
$display("The log base 10 of 0.0 is %f.", log(zero));
$display("The log base 10 of -0.0 is %f.", log(mzero));
$display("The log base 10 of -1.0 is %f.", abs(log(-1.0)));
$display("The log base 10 of inf is %f.", log(pinf));
$display("The log base 10 of -inf is %f.", abs(log(minf)));
$display("The log base 10 of nan is %f.", abs(log(nan)));
end
endtask
// Task to check the exponential function.
task check_exp;
begin
$display("--- Checking the exp function ---");
$display("The exponential of 1.0 is %f.", exp(1.0));
$display("The exponential of 0.0 is %f.", exp(zero));
$display("The exponential of -0.0 is %f.", exp(mzero));
$display("The exponential of -1.0 is %f.", exp(-1.0));
$display("The exponential of inf is %f.", exp(pinf));
$display("The exponential of -inf is %f.", exp(minf));
$display("The exponential of nan is %f.", abs(exp(nan)));
end
endtask
// Task to check the absolute value function.
task check_abs;
begin
$display("--- Checking the abs function ---");
$display("The absolute value of 1.0 is %f.", abs(1.0));
$display("The absolute value of 0.0 is %f.", abs(zero));
$display("The absolute value of -0.0 is %f.", abs(mzero));
$display("The absolute value of -1.0 is %f.", abs(-1.0));
$display("The absolute value of inf is %f.", abs(pinf));
$display("The absolute value of -inf is %f.", abs(minf));
$display("The absolute value of nan is %f.", abs(nan));
end
endtask
// Task to check the ceiling function.
task check_ceil;
begin
$display("--- Checking the ceil function ---");
$display("The ceiling of 2.1 is %f.", ceil(2.1));
$display("The ceiling of 0.5 is %f.", ceil(0.5));
$display("The ceiling of -0.5 is %f.", ceil(-0.5) + 0.0);
$display("The ceiling of -1.1 is %f.", ceil(-1.1));
$display("The ceiling of inf is %f.", ceil(pinf));
$display("The ceiling of -inf is %f.", ceil(minf));
$display("The ceiling of nan is %f.", abs(ceil(nan)));
end
endtask
// Task to check the floor function.
task check_floor;
begin
$display("--- Checking the floor function ---");
$display("The floor of 2.1 is %f.", floor(2.1));
$display("The floor of 0.5 is %f.", floor(0.5));
$display("The floor of -0.5 is %f.", floor(-0.5));
$display("The floor of -1.1 is %f.", floor(-1.1));
$display("The floor of inf is %f.", floor(pinf));
$display("The floor of -inf is %f.", floor(minf));
$display("The floor of nan is %f.", abs(floor(nan)));
end
endtask
// Task to check the sin function.
task check_sin;
begin
$display("--- Checking the sin function ---");
$display("The sin of 4.0 is %f.", sin(4.0));
$display("The sin of 1.0 is %f.", sin(1.0));
$display("The sin of 0.0 is %f.", sin(zero));
$display("The sin of -0.0 is %f.", sin(mzero));
$display("The sin of -1.0 is %f.", sin(-1.0));
$display("The sin of -4.0 is %f.", sin(-4.0));
$display("The sin of inf is %f.", abs(sin(pinf)));
$display("The sin of -inf is %f.", abs(sin(minf)));
$display("The sin of nan is %f.", abs(sin(nan)));
end
endtask
// Task to check the cos function.
task check_cos;
begin
$display("--- Checking the cos function ---");
$display("The cos of 4.0 is %f.", cos(4.0));
$display("The cos of 1.0 is %f.", cos(1.0));
$display("The cos of 0.0 is %f.", cos(zero));
$display("The cos of -0.0 is %f.", cos(mzero));
$display("The cos of -1.0 is %f.", cos(-1.0));
$display("The cos of -4.0 is %f.", cos(-4.0));
$display("The cos of inf is %f.", abs(cos(pinf)));
$display("The cos of -inf is %f.", abs(cos(minf)));
$display("The cos of nan is %f.", abs(cos(nan)));
end
endtask
// Task to check the tan function.
task check_tan;
begin
$display("--- Checking the tan function ---");
$display("The tan of 4.0 is %f.", tan(4.0));
$display("The tan of 1.0 is %f.", tan(1.0));
$display("The tan of 0.0 is %f.", tan(zero));
$display("The tan of -0.0 is %f.", tan(mzero));
$display("The tan of -1.0 is %f.", tan(-1.0));
$display("The tan of -4.0 is %f.", tan(-4.0));
// The underlying math libraries can give different results for
// this corner case, so we can only use four significant digits
// for these two tests.
$display("The tan of pi/2 is %.4g.", tan(asin(1.0)));
$display("The tan of -pi/2 is %.4g.", tan(asin(-1.0)));
$display("The tan of inf is %f.", abs(tan(pinf)));
$display("The tan of -inf is %f.", abs(tan(minf)));
$display("The tan of nan is %f.", abs(tan(nan)));
end
endtask
// Task to check the asin function.
task check_asin;
begin
$display("--- Checking the asin function ---");
$display("The asin of 1.1 is %f.", abs(asin(1.1)));
$display("The asin of 1.0 is %f.", asin(1.0));
$display("The asin of 0.5 is %f.", asin(0.5));
$display("The asin of 0.0 is %f.", asin(zero));
$display("The asin of -0.0 is %f.", asin(mzero));
$display("The asin of -0.5 is %f.", asin(-0.5));
$display("The asin of -1.0 is %f.", asin(-1.0));
$display("The asin of -1.1 is %f.", abs(asin(-1.1)));
$display("The asin of inf is %f.", abs(asin(pinf)));
$display("The asin of -inf is %f.", abs(asin(minf)));
$display("The asin of nan is %f.", abs(asin(nan)));
end
endtask
// Task to check the acos function.
task check_acos;
begin
$display("--- Checking the acos function ---");
$display("The acos of 1.1 is %f.", abs(acos(1.1)));
$display("The acos of 1.0 is %f.", acos(1.0));
$display("The acos of 0.5 is %f.", acos(0.5));
$display("The acos of 0.0 is %f.", acos(zero));
$display("The acos of -0.0 is %f.", acos(mzero));
$display("The acos of -0.5 is %f.", acos(-0.5));
$display("The acos of -1.0 is %f.", acos(-1.0));
$display("The acos of -1.1 is %f.", abs(acos(-1.1)));
$display("The acos of inf is %f.", abs(acos(pinf)));
$display("The acos of -inf is %f.", abs(acos(minf)));
$display("The acos of nan is %f.", abs(acos(nan)));
end
endtask
// Task to check the atan function.
task check_atan;
begin
$display("--- Checking the atan function ---");
$display("The atan of 2.0 is %f.", atan(2.0));
$display("The atan of 0.5 is %f.", atan(0.5));
$display("The atan of 0.0 is %f.", atan(zero));
$display("The atan of -0.0 is %f.", atan(mzero));
$display("The atan of -0.5 is %f.", atan(-0.5));
$display("The atan of -2.0 is %f.", atan(-2.0));
$display("The atan of inf is %f.", atan(pinf));
$display("The atan of -inf is %f.", atan(minf));
$display("The atan of nan is %f.", abs(atan(nan)));
end
endtask
// Task to check the sinh function.
task check_sinh;
begin
$display("--- Checking the sinh function ---");
$display("The sinh of 2.0 is %f.", sinh(2.0));
$display("The sinh of 1.0 is %f.", sinh(1.0));
$display("The sinh of 0.5 is %f.", sinh(0.5));
$display("The sinh of 0.0 is %f.", sinh(zero));
$display("The sinh of -0.0 is %f.", sinh(mzero));
$display("The sinh of -0.5 is %f.", sinh(-0.5));
$display("The sinh of -1.0 is %f.", sinh(-1.0));
$display("The sinh of -2.0 is %f.", sinh(-2.0));
$display("The sinh of inf is %f.", sinh(pinf));
$display("The sinh of -inf is %f.", sinh(minf));
$display("The sinh of nan is %f.", abs(sinh(nan)));
end
endtask
// Task to check the cosh function.
task check_cosh;
begin
$display("--- Checking the cosh function ---");
$display("The cosh of 2.0 is %f.", cosh(2.0));
$display("The cosh of 1.0 is %f.", cosh(1.0));
$display("The cosh of 0.5 is %f.", cosh(0.5));
$display("The cosh of 0.0 is %f.", cosh(zero));
$display("The cosh of -0.0 is %f.", cosh(mzero));
$display("The cosh of -0.5 is %f.", cosh(-0.5));
$display("The cosh of -1.0 is %f.", cosh(-1.0));
$display("The cosh of -2.0 is %f.", cosh(-2.0));
$display("The cosh of inf is %f.", cosh(pinf));
$display("The cosh of -inf is %f.", cosh(minf));
$display("The cosh of nan is %f.", abs(cosh(nan)));
end
endtask
// Task to check the tanh function.
task check_tanh;
begin
$display("--- Checking the tanh function ---");
$display("The tanh of 2.0 is %f.", tanh(2.0));
$display("The tanh of 1.0 is %f.", tanh(1.0));
$display("The tanh of 0.5 is %f.", tanh(0.5));
$display("The tanh of 0.0 is %f.", tanh(zero));
$display("The tanh of -0.0 is %f.", tanh(mzero));
$display("The tanh of -0.5 is %f.", tanh(-0.5));
$display("The tanh of -1.0 is %f.", tanh(-1.0));
$display("The tanh of -2.0 is %f.", tanh(-2.0));
$display("The tanh of inf is %f.", tanh(pinf));
$display("The tanh of -inf is %f.", tanh(minf));
$display("The tanh of nan is %f.", abs(tanh(nan)));
end
endtask
// Task to check the asinh function.
task check_asinh;
begin
$display("--- Checking the asinh function ---");
$display("The asinh of 2.0 is %f.", asinh(2.0));
$display("The asinh of 1.0 is %f.", asinh(1.0));
$display("The asinh of 0.5 is %f.", asinh(0.5));
$display("The asinh of 0.0 is %f.", asinh(zero));
$display("The asinh of -0.0 is %f.", asinh(mzero));
$display("The asinh of -0.5 is %f.", asinh(-0.5));
$display("The asinh of -1.0 is %f.", asinh(-1.0));
$display("The asinh of -2.0 is %f.", asinh(-2.0));
$display("The asinh of inf is %f.", asinh(pinf));
$display("The asinh of -inf is %f.", asinh(minf));
$display("The asinh of nan is %f.", abs(asinh(nan)));
end
endtask
// Task to check the acosh function.
task check_acosh;
begin
$display("--- Checking the acosh function ---");
$display("The acosh of 2.0 is %f.", acosh(2.0));
$display("The acosh of 1.0 is %f.", acosh(1.0));
$display("The acosh of 0.5 is %f.", abs(acosh(0.5)));
$display("The acosh of 0 is %f.", abs(acosh(zero)));
$display("The acosh of -0 is %f.", abs(acosh(mzero)));
$display("The acosh of -0.5 is %f.", abs(acosh(-0.5)));
$display("The acosh of -1.0 is %f.", abs(acosh(-1.0)));
$display("The acosh of -2.0 is %f.", abs(acosh(-2.0)));
$display("The acosh of inf is %f.", acosh(pinf));
$display("The acosh of -inf is %f.", abs(acosh(minf)));
$display("The acosh of nan is %f.", abs(acosh(nan)));
end
endtask
// Task to check the atanh function.
task check_atanh;
begin
$display("--- Checking the atanh function ---");
$display("The atanh of 2.0 is %f.", abs(atanh(2.0)));
$display("The atanh of 1.0 is %f.", atanh(1.0));
$display("The atanh of 0.5 is %f.", atanh(0.5));
$display("The atanh of 0.0 is %f.", atanh(zero));
$display("The atanh of -0.0 is %f.", atanh(mzero));
$display("The atanh of -0.5 is %f.", atanh(-0.5));
$display("The atanh of -1.0 is %f.", atanh(-1.0));
$display("The atanh of -2.0 is %f.", abs(atanh(-2.0)));
$display("The atanh of inf is %f.", abs(atanh(pinf)));
$display("The atanh of -inf is %f.", abs(atanh(minf)));
$display("The atanh of nan is %f.", abs(atanh(nan)));
end
endtask
// Task to check the min function.
task check_min;
begin
$display("--- Checking the min function ---");
$display("The minimum of 1.0 and 2.0 is %f.", min(1.0, 2.0));
$display("The minimum of 2.0 and 1.0 is %f.", min(2.0, 1.0));
$display("The minimum of 1.0 and -1.0 is %f.", min(1.0, -1.0));
$display("The minimum of -1.0 and -2.0 is %f.", min(-1.0, -2.0));
$display("The minimum of 2.0 and inf is %f.", min(2.0, pinf));
$display("The minimum of inf and 2.0 is %f.", min(pinf, 2.0));
$display("The minimum of 2.0 and -inf is %f.", min(2.0, minf));
$display("The minimum of -inf and 2.0 is %f.", min(minf, 2.0));
$display("The minimum of 2.0 and nan is %f.", min(2.0, nan));
$display("The minimum of nan and 2.0 is %f.", min(nan, 2.0));
end
endtask
// Task to check the max function.
task check_max;
begin
$display("--- Checking the max function ---");
$display("The maximum of 1.0 and 2.0 is %f.", max(1.0, 2.0));
$display("The maximum of 2.0 and 1.0 is %f.", max(2.0, 1.0));
$display("The maximum of 1.0 and -1.0 is %f.", max(1.0, -1.0));
$display("The maximum of -1.0 and -2.0 is %f.", max(-1.0, -2.0));
$display("The maximum of 2.0 and inf is %f.", max(2.0, pinf));
$display("The maximum of inf and 2.0 is %f.", max(pinf, 2.0));
$display("The maximum of 2.0 and -inf is %f.", max(2.0, minf));
$display("The maximum of -inf and 2.0 is %f.", max(minf, 2.0));
$display("The maximum of 2.0 and nan is %f.", max(2.0, nan));
$display("The maximum of nan and 2.0 is %f.", max(nan, 2.0));
end
endtask
// Task to check the power function.
task check_pow;
begin
$display("--- Checking the pow function ---");
$display(" 0.0 to the power of 0.0 is %f.", pow(zero, zero));
$display(" 1.0 to the power of 0.0 is %f.", pow(1.0, zero));
$display("-1.0 to the power of 0.0 is %f.", pow(-1.0, zero));
$display(" 0.0 to the power of 1.0 is %f.", pow(zero, 1.0));
$display(" 1.0 to the power of 1.0 is %f.", pow(1.0, 1.0));
$display("-1.0 to the power of 1.0 is %f.", pow(-1.0, 1.0));
$display(" 8.0 to the power of 1/3 is %f.", pow(8.0, 1.0/3.0));
$display(" 8.0 to the power of -1/3 is %f.", pow(8.0, -1.0/3.0));
$display(" 2.0 to the power of 3.0 is %f.", pow(2.0, 3.0));
$display(" 2.0 to the power of 5000 is %f.", pow(2.0, 5000));
$display("-2.0 to the power of 5001 is %f.", pow(-2.0, 5001));
$display(" 2.0 to the power of -5000 is %f.", pow(2.0, -5000));
$display(" inf to the power of 0.0 is %f.", pow(pinf, zero));
$display("-inf to the power of 0.0 is %f.", pow(minf, zero));
$display(" inf to the power of 1.0 is %f.", pow(pinf, 1.0));
$display("-inf to the power of 1.0 is %f.", pow(minf, 1.0));
$display(" inf to the power of 2.0 is %f.", pow(pinf, 2.0));
$display("-inf to the power of 2.0 is %f.", pow(minf, 2.0));
$display(" 1.0 to the power of inf is %f.", pow(1.0, pinf));
$display("-1.0 to the power of inf is %f.", pow(-1.0, pinf));
$display(" 0.5 to the power of inf is %f.", pow(0.5, pinf));
$display(" 2.0 to the power of inf is %f.", pow(2.0, pinf));
$display(" 1.0 to the power of -inf is %f.", pow(1.0, minf));
$display("-1.0 to the power of -inf is %f.", pow(-1.0, minf));
$display(" 0.5 to the power of -inf is %f.", pow(0.5, minf));
$display(" 2.0 to the power of -inf is %f.", pow(2.0, minf));
$display("-1.0 to the power of -1/3 is %f.", abs(pow(-1.0, -1.0/3.0)));
$display(" 1.0 to the power of nan is %f.", pow(1.0, nan));
$display(" nan to the power of 1.0 is %f.", abs(pow(nan, 1.0)));
$display(" nan to the power of 0.0 is %f.", pow(nan, zero));
$display(" nan to the power of nan is %f.", abs(pow(nan, nan)));
end
endtask
// Task to check the atan of x/y function.
task check_atan2;
begin
$display("--- Checking the atan2 function ---");
$display("The atan of 0.0/ 0.0 is %f.", atan2(zero, zero));
$display("The atan of -0.0/ 0.0 is %f.", atan2(mzero, zero));
$display("The atan of 0.0/-0.0 is %f.", atan2(zero, mzero));
$display("The atan of -0.0/-0.0 is %f.", atan2(mzero, mzero));
$display("The atan of 0.0/ 1.0 is %f.", atan2(zero, 1.0));
$display("The atan of 1.0/ 0.0 is %f.", atan2(1.0, zero));
$display("The atan of 1.0/ 1.0 is %f.", atan2(1.0, 1.0));
$display("The atan of 0.0/-1.0 is %f.", atan2(zero, -1.0));
$display("The atan of -1.0/ 0.0 is %f.", atan2(-1.0, zero));
$display("The atan of -1.0/-1.0 is %f.", atan2(-1.0, -1.0));
$display("The atan of inf/ 0.0 is %f.", atan2(pinf, zero));
$display("The atan of 0.0/ inf is %f.", atan2(zero, pinf));
$display("The atan of inf/ inf is %f.", atan2(pinf, pinf));
$display("The atan of -inf/ 0.0 is %f.", atan2(minf, zero));
$display("The atan of 0.0/-inf is %f.", atan2(zero, minf));
$display("The atan of -inf/-inf is %f.", atan2(minf, minf));
$display("The atan of nan/ 0.0 is %f.", abs(atan2(nan, zero)));
$display("The atan of nan/ 1.0 is %f.", abs(atan2(nan, 1.0)));
$display("The atan of 1.0/ nan is %f.", abs(atan2(1.0, nan)));
end
endtask
// Task to check the distance from origin function.
task check_hypot;
begin
$display("--- Checking the hypot function ---");
$display("The distance to ( 0.0, 0.0) is %f.", hypot(zero, zero));
$display("The distance to ( 2.0, 0.0) is %f.", hypot(2.0, zero));
$display("The distance to ( -2.0, 0.0) is %f.", hypot(-2.0, zero));
$display("The distance to ( 0.0, 2.0) is %f.", hypot(zero, 2.0));
$display("The distance to ( 0.0, -2.0) is %f.", hypot(zero, -2.0));
$display("The distance to ( inf, 0.0) is %f.", hypot(pinf, zero));
$display("The distance to ( 0.0, inf) is %f.", hypot(zero, pinf));
$display("The distance to ( -inf, 0.0) is %f.", hypot(minf, zero));
$display("The distance to ( nan, 0.0) is %f.", abs(hypot(nan, zero)));
$display("The distance to ( 0.0, nan) is %f.", abs(hypot(zero, nan)));
end
endtask
// Task to check the mathematical constants.
task check_constants;
begin
$display("--- Checking the mathematical constants ---");
$display(" Pi is %.16f.", `M_PI);
$display(" 2*Pi is %.16f.", `M_TWO_PI);
$display(" Pi/2 is %.16f.", `M_PI_2);
$display(" Pi/4 is %.16f.", `M_PI_4);
$display(" 1/Pi is %.16f.", `M_1_PI);
$display(" 2/Pi is %.16f.", `M_2_PI);
$display("2/sqrt(Pi) is %.16f.", `M_2_SQRTPI);
$display(" e is %.16f.", `M_E);
$display(" log2(e) is %.16f.", `M_LOG2E);
$display(" log10(e) is %.16f.", `M_LOG10E);
$display(" loge(2) is %.16f.", `M_LN2);
$display(" loge(10) is %.16f.", `M_LN10);
$display(" sqrt(2) is %.16f.", `M_SQRT2);
$display(" 1/sqrt(2) is %.16f.", `M_SQRT1_2);
end
endtask
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: one_hot_mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A mux module, where the output select is a one-hot bus
// Author: Dustin Richmond
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module one_hot_mux
#(parameter C_DATA_WIDTH = 1,
parameter C_SELECT_WIDTH = 2,
parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
)
(
input [C_SELECT_WIDTH-1:0] ONE_HOT_SELECT,
input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
output [C_DATA_WIDTH-1:0] ONE_HOT_OUTPUT);
`include "functions.vh"
genvar i;
wire [C_DATA_WIDTH-1:0] wOneHotInputs[(1<<C_SELECT_WIDTH):1];
reg [C_DATA_WIDTH-1:0] _rOneHotOutput;
assign ONE_HOT_OUTPUT = _rOneHotOutput;
generate
for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
end
if(C_SELECT_WIDTH == 1) begin
always @(*) begin
_rOneHotOutput = wOneHotInputs[1];
end
end else if(C_SELECT_WIDTH == 2) begin
always @(*) begin
case(ONE_HOT_SELECT)
2'b01: _rOneHotOutput = wOneHotInputs[1];
2'b10: _rOneHotOutput = wOneHotInputs[2];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 4) begin
always @(*) begin
case(ONE_HOT_SELECT)
4'b0001: _rOneHotOutput = wOneHotInputs[1];
4'b0010: _rOneHotOutput = wOneHotInputs[2];
4'b0100: _rOneHotOutput = wOneHotInputs[4];
4'b1000: _rOneHotOutput = wOneHotInputs[8];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 8) begin
always @(*) begin
case(ONE_HOT_SELECT)
8'b00000001: _rOneHotOutput = wOneHotInputs[1];
8'b00000010: _rOneHotOutput = wOneHotInputs[2];
8'b00000100: _rOneHotOutput = wOneHotInputs[4];
8'b00001000: _rOneHotOutput = wOneHotInputs[8];
8'b00010000: _rOneHotOutput = wOneHotInputs[16];
8'b00100000: _rOneHotOutput = wOneHotInputs[32];
8'b01000000: _rOneHotOutput = wOneHotInputs[64];
8'b10000000: _rOneHotOutput = wOneHotInputs[128];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end
endgenerate
endmodule
|
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
/*
Implements a butterfly module for a FFT.
Takes complex numbers W, XA, XB and returns
YA = XA + W*XB
YB = XA - W*XB
It can take input no more frequently than once every
two steps. This is so, hopefully, less multiply
blocks can be used.
*/
module butterfly
#(
// The width of m_in.
parameter M_WDTH = 0,
// The width of the input, output and twiddle factors.
parameter X_WDTH = 0
)
(
input wire clk,
input wire rst_n,
// m_in contains data that passes through this block with no change.
// It is delayed for 3 counts like x_nd->y_nd.
input wire [M_WDTH-1:0] m_in,
// The twiddle factor.
input wire signed [2*X_WDTH-1:0] w,
// XA
input wire signed [2*X_WDTH-1:0] xa,
// XB
input wire signed [2*X_WDTH-1:0] xb,
// Set to 1 when new data is present on inputs.
// Cannot be set to 1 for two consecutive steps.
input wire x_nd,
// delayed version of m_in.
output reg [M_WDTH-1:0] m_out,
// YA = XA + W*XB
// YB = XA - W*XB
// When y_nd=1 y_re and y_im are outputing YA.
// The step after they are outputting YB.
output wire signed [2*X_WDTH-1:0] y,
output reg y_nd
);
// Set wire to the real and imag parts for convenience.
wire signed [X_WDTH-1:0] w_re;
wire signed [X_WDTH-1:0] w_im;
assign w_re = w[2*X_WDTH-1:X_WDTH];
assign w_im = w[X_WDTH-1:0];
wire signed [X_WDTH-1:0] xa_re;
wire signed [X_WDTH-1:0] xa_im;
assign xa_re = xa[2*X_WDTH-1:X_WDTH];
assign xa_im = xa[X_WDTH-1:0];
wire signed [X_WDTH-1:0] xb_re;
wire signed [X_WDTH-1:0] xb_im;
assign xb_re = xb[2*X_WDTH-1:X_WDTH];
assign xb_im = xb[X_WDTH-1:0];
reg signed [X_WDTH-1: 0] y_re;
reg signed [X_WDTH-1: 0] y_im;
assign y = {y_re, y_im};
// Delayed m_in.
reg signed [M_WDTH-1:0] m[1:0];
// Delayed XA
reg signed [X_WDTH-1:0] za_re[1:0];
reg signed [X_WDTH-1:0] za_im[1:0];
// Delayed XB
reg signed [X_WDTH-1:0] zb_re;
reg signed [X_WDTH-1:0] zb_im;
// Delayed W
reg signed [X_WDTH-1:0] ww_re;
reg signed [X_WDTH-1:0] ww_im;
// Delayed x_nd
reg signed x_nd_old[2:0];
// Storage for output of multipliers
reg signed [2*X_WDTH-1:0] zbw_m1;
reg signed [2*X_WDTH-1:0] zbw_m2;
// W * XB
reg signed [X_WDTH-1:0] zbw_re;
wire signed [X_WDTH-1:0] zbw_im;
assign zbw_im = (zbw_m1 >>> (X_WDTH-2)) + (zbw_m2 >>> (X_WDTH-2));
reg signed [X_WDTH-1:0] zbw_im_old;
// Wire of longer length for adding or substracting W*XB to XA.
// If we don't create longer wires for them then we can lose the
// high bit. The contents of these wires are downshifted into a
// normal size for use.
wire signed [X_WDTH:0] z1_re_big;
wire signed [X_WDTH:0] z1_im_big;
assign z1_re_big = za_re[0] + zbw_re;
assign z1_im_big = za_im[0] + zbw_im;
wire signed [X_WDTH:0] z2_re_big;
wire signed [X_WDTH:0] z2_im_big;
assign z2_re_big = za_re[1] - zbw_re;
assign z2_im_big = za_im[1] - zbw_im_old;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
y_nd <= 1'b0;
end
else
begin
// Set delay for x_nd_old and m.
x_nd_old[0] <= x_nd;
x_nd_old[1] <= x_nd_old[0];
x_nd_old[2] <= x_nd_old[1];
m[0] <= m_in;
m[1] <= m[0];
m_out <= m[1];
// STAGE 1
if (x_nd)
begin
za_re[0] <= xa_re;
za_im[0] <= xa_im;
ww_re <= w_re;
ww_im <= w_im;
zb_re <= xb_re;
zb_im <= xb_im;
// We perform two multiplications for calculate the real part
// of W*XB.
zbw_m1 <= xb_re*w_re;
zbw_m2 <= xb_im*w_im;
if (x_nd_old[0])
$display("ERROR: BF got new data two steps in a row.");
end
if (x_nd_old[0])
// STAGE 2
begin
// Now start the multiplications for the imag part of W*WB.
zbw_m1 <= zb_re*ww_im;
zbw_m2 <= zb_im*ww_re;
// Downshift the multiplied results into normal width and
// substract them.
// Overflow is not possible upon substraction since we
// know that W and XB both have magnitude less than 1
// so their multiple must also.
zbw_re <= (zbw_m1 >>> (X_WDTH-2)) - (zbw_m2 >>> (X_WDTH-2));
end
// STAGE 3
if (x_nd_old[1])
begin
// We only need to shift the required delayed data
// with XA every two steps since new input cannot
// arrive more frequently than that.
// XA is needed by a wire calculating z2_re_big and ze_im_big
// next step.
za_re[1] <= za_re[0];
za_im[1] <= za_im[0];
// Output YA.
y_nd <= 1'b1;
y_re <= z1_re_big >>> 1;
y_im <= z1_im_big >>> 1;
zbw_im_old <= zbw_im;
end
// STAGE 4
if (x_nd_old[2])
begin
// Output YB.
y_nd <= 1'b0;
y_re <= z2_re_big >>> 1;
y_im <= z2_im_big >>> 1;
end
end
end
endmodule |
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus master interface.
*
* rcn bus vector definition =
* {valid, pending, wr, id[5:0], mask[3:0], addr[23:2], seq[1:0], data[31:0]}
*
* data = [31:0]
* seq = [33:32]
* addr = [55:34]
* mask = [59:56]
* id = [65:60]
* wr = [66]
* pending = [67]
* valid = [68]
*
*/
module rcn_master
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [1:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [1:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data
);
parameter MASTER_ID = 0;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [5:0] my_id = MASTER_ID;
wire my_resp = rin[68] && !rin[67] && (rin[65:60] == my_id);
wire req_valid;
wire [68:0] req;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rout <= 69'd0;
end
else
begin
rin <= rcn_in;
rout <= (req_valid) ? req : (my_resp) ? 69'd0 : rin;
end
assign busy = rin[68] && !my_resp;
assign req_valid = cs && !(rin[68] && !my_resp);
assign req = {1'b1, 1'b1, wr, my_id, mask, addr[23:2], seq, wdata};
assign rdone = my_resp && !rin[66];
assign wdone = my_resp && rin[66];
assign rsp_seq = rin[33:32];
assign rsp_mask = rin[59:56];
assign rsp_addr = {rin[55:34], 2'd0};
assign rsp_data = rin[31:0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`timescale 1ns/1ps
`define STRINGIFY(x) `"x`"
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk_a;
reg rce_a;
reg [`ADDR_WIDTH-1:0] ra_a;
wire [`DATA_WIDTH-1:0] rq_a;
reg wce_a;
reg [`ADDR_WIDTH-1:0] wa_a;
reg [`DATA_WIDTH-1:0] wd_a;
reg clk_b;
reg rce_b;
reg [`ADDR_WIDTH-1:0] ra_b;
wire [`DATA_WIDTH-1:0] rq_b;
reg wce_b;
reg [`ADDR_WIDTH-1:0] wa_b;
reg [`DATA_WIDTH-1:0] wd_b;
initial clk_a = 0;
initial clk_b = 0;
initial ra_a = 0;
initial ra_b = 0;
initial rce_a = 0;
initial rce_b = 0;
initial forever #(PERIOD / 2.0) clk_a = ~clk_a;
initial begin
#(PERIOD / 4.0);
forever #(PERIOD / 2.0) clk_b = ~clk_b;
end
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
integer b;
reg done_a;
reg done_b;
initial done_a = 1'b0;
initial done_b = 1'b0;
wire done_sim = done_a & done_b;
reg [`DATA_WIDTH-1:0] expected_a;
reg [`DATA_WIDTH-1:0] expected_b;
always @(posedge clk_a) begin
expected_a <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
end
always @(posedge clk_b) begin
expected_b <= (b | (b << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
end
wire error_a = a != 0 ? rq_a !== expected_a : 0;
wire error_b = b != (1<<`ADDR_WIDTH) / 2 ? rq_b !== expected_b : 0;
integer error_a_cnt = 0;
integer error_b_cnt = 0;
always @ (posedge clk_a)
begin
if (error_a)
error_a_cnt <= error_a_cnt + 1'b1;
end
always @ (posedge clk_b)
begin
if (error_b)
error_b_cnt <= error_b_cnt + 1'b1;
end
// PORT A
initial #(1) begin
// Write data
for (a = 0; a < (1<<`ADDR_WIDTH) / 2; a = a + ADDR_INCR) begin
@(negedge clk_a) begin
wa_a = a;
wd_a = a | (a << 20) | 20'h55000;
wce_a = 1;
end
@(posedge clk_a) begin
#(PERIOD/10) wce_a = 0;
end
end
// Read data
for (a = 0; a < (1<<`ADDR_WIDTH) / 2; a = a + ADDR_INCR) begin
@(negedge clk_a) begin
ra_a = a;
rce_a = 1;
end
@(posedge clk_a) begin
#(PERIOD/10) rce_a = 0;
if ( rq_a !== expected_a) begin
$display("%d: PORT A: FAIL: mismatch act=%x exp=%x at %x", $time, rq_a, expected_a, a);
end else begin
$display("%d: PORT A: OK: act=%x exp=%x at %x", $time, rq_a, expected_a, a);
end
end
end
done_a = 1'b1;
end
// PORT B
initial #(1) begin
// Write data
for (b = (1<<`ADDR_WIDTH) / 2; b < (1<<`ADDR_WIDTH); b = b + ADDR_INCR) begin
@(negedge clk_b) begin
wa_b = b;
wd_b = b | (b << 20) | 20'h55000;
wce_b = 1;
end
@(posedge clk_b) begin
#(PERIOD/10) wce_b = 0;
end
end
// Read data
for (b = (1<<`ADDR_WIDTH) / 2; b < (1<<`ADDR_WIDTH); b = b + ADDR_INCR) begin
@(negedge clk_b) begin
ra_b = b;
rce_b = 1;
end
@(posedge clk_b) begin
#(PERIOD/10) rce_b = 0;
if ( rq_b !== expected_b) begin
$display("%d: PORT B: FAIL: mismatch act=%x exp=%x at %x", $time, rq_b, expected_b, b);
end else begin
$display("%d: PORT B: OK: act=%x exp=%x at %x", $time, rq_b, expected_b, b);
end
end
end
done_b = 1'b1;
end
// Scan for simulation finish
always @(posedge clk_a, posedge clk_b) begin
if (done_sim)
$finish_and_return( (error_a_cnt == 0 & error_b_cnt == 0) ? 0 : -1 );
end
case (`STRINGIFY(`TOP))
"BRAM_TDP_32x512": begin
BRAM_TDP_32x512 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
"BRAM_TDP_16x1024": begin
BRAM_TDP_16x1024 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
"BRAM_TDP_8x2048": begin
BRAM_TDP_8x2048 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
"BRAM_TDP_4x4096": begin
BRAM_TDP_4x4096 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
endcase
endmodule
|
/*******************************************************************************
Vendor: Xilinx
Associated Filename: realfft_rtl_tb.v
Purpose: Part of a Vivado HLS tutorial example
Device: All
Revision History: March 31, 2013 - initial release
*******************************************************************************
Copyright (C) 2013 XILINX, Inc.
This file contains confidential and proprietary information of Xilinx, Inc. and
is protected under U.S. and international copyright and other intellectual
property laws.
DISCLAIMER
This disclaimer is not a license and does not grant any rights to the materials
distributed herewith. Except as otherwise provided in a valid license issued to
you by Xilinx, and to the maximum extent permitted by applicable law:
(1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX
HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature related to, arising under
or in connection with these materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage (including loss of data,
profits, goodwill, or any type of loss or damage suffered as a result of any
action brought by a third party) even if such damage or loss was reasonably
foreseeable or Xilinx had been advised of the possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-safe, or for use in any
application requiring fail-safe performance, such as life-support or safety
devices or systems, Class III medical devices, nuclear facilities, applications
related to the deployment of airbags, or any other applications that could lead
to death, personal injury, or severe property or environmental damage
(individually and collectively, "Critical Applications"). Customer asresultes the
sole risk and liability of any use of Xilinx products in Critical Applications,
subject only to applicable laws and regulations governing limitations on product
liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT
ALL TIMES.
*******************************************************************************/
`timescale 1 ns / 1 ps
`define EOF 32'hFFFF_FFFF
`define NULL 0
`define MAX_LINE_LENGTH 1000
module realfft_rtl_tb ();
reg aclk = 1'b0;
reg aresetn = 1'b1;
reg [15:0]real2xfft_din_tdata;
wire real2xfft_din_tready;
reg real2xfft_din_tvalid;
wire [31:0]xfft2real_dout_tdata;
reg xfft2real_dout_tready;
wire xfft2real_dout_tvalid;
//RealFFT_wrapper dut0 (
RealFFT_wrapper dut0 (
.aclk(aclk),
.aresetn(aresetn),
.real2xfft_din_tdata(real2xfft_din_tdata),
.real2xfft_din_tready(real2xfft_din_tready),
.real2xfft_din_tvalid(real2xfft_din_tvalid),
.xfft2real_dout_tdata(xfft2real_dout_tdata),
.xfft2real_dout_tready(xfft2real_dout_tready),
.xfft2real_dout_tvalid(xfft2real_dout_tvalid)
);
// Clock generator
always #5 aclk = ~aclk;
// Reset generator
initial begin
#10
@(posedge aclk)
aresetn = 1'b0;
#100
@(posedge aclk)
aresetn = 1'b1;
end
// real2fft stimulus process
initial begin : tvin_block
integer tvin_fd, c, r, i;
reg [8*`MAX_LINE_LENGTH:0] line; /* Line of text read from file */
reg [31:0] num_sent;
tvin_fd = $fopen("../../../../verilog_tb/realfft_fe_tvin.dat", "r");
if (tvin_fd == `NULL) begin// If error opening file
$display("Could not open input test vector file. Bailing out...");
disable tvin_block; // Just quit
end
// Wait for areset to assert and de-assert
wait(aresetn == 1'b0) @(posedge aclk);
num_sent = 0;
real2xfft_din_tdata = 32'hDEADBEEF;
real2xfft_din_tvalid = 1'b0;
wait(aresetn == 1'b1) @(posedge aclk);
#20
@(negedge aclk)
// Read entire input TV file
c = $fgetc(tvin_fd);
while (c != `EOF) begin
/* Check the first character for comment */
if (c == "/")
r = $fgets(line, tvin_fd);
else begin
// Push the character back to the tvin_fd then read the next TV
r = $ungetc(c, tvin_fd);
r = $fscanf(tvin_fd," %h\n", real2xfft_din_tdata);
real2xfft_din_tvalid = 1'b1;
// Hold AXIS output signals until TREADY is asserted
wait(real2xfft_din_tready == 1'b1) @(negedge aclk)
num_sent = num_sent + 1;
end // if c else
c = $fgetc(tvin_fd);
end // while not EOF
// Flush the FFT pipeline
for (i = 0; i < 1024; i = i + 1) begin
real2xfft_din_tdata = 32'h0000_0000;
real2xfft_din_tvalid = 1'b1;
// Hold AXIS output signals until TREADY is asserted
wait(real2xfft_din_tready == 1'b1) @(negedge aclk)
num_sent = num_sent + 1;
end
real2xfft_din_tdata = 32'hCAFEDECA;
real2xfft_din_tvalid = 1'b0;
$fclose(tvin_fd);
end // initial
// xfft2real response process
initial begin : tvout_block
integer tvout_fd, c, r;
reg [8*`MAX_LINE_LENGTH:0] line; /* Line of text read from file */
reg [31:0] tvout_expected;
reg [31:0] num_rx;
integer err_cnt;
tvout_fd = $fopen("../../../../verilog_tb/realfft_be_tvout.dat", "r");
if (tvout_fd == `NULL) begin // If error opening file
$display("Could not open output test vector file. Bailing out...");
disable tvout_block; // Just quit
end
// Wait for areset to assert and de-assert
wait(aresetn == 1'b0) @(posedge aclk);
err_cnt = 0;
num_rx = 0;
xfft2real_dout_tready = 1'b0;
wait(aresetn == 1'b1) @(posedge aclk);
#20
@(negedge aclk)
// Set TREADY - never de-asserted until all responses received
xfft2real_dout_tready = 1'b1;
// Read entire output TV file and compare against golden data
c = $fgetc(tvout_fd);
while (c != `EOF) begin
/* Check the first character for comment */
if (c == "/")
r = $fgets(line, tvout_fd);
else begin
// Push the character back to the tvout_fd then read the next TV
r = $ungetc(c, tvout_fd);
r = $fscanf(tvout_fd," %h\n", tvout_expected);
@(negedge aclk)
// Wait for TVALID
while(xfft2real_dout_tvalid == 1'b0) begin
@(negedge aclk);
end
// TODO: Check tvout_val against expected data accounting for
// precision losses...
$display("%d - Expected: 0x%8h; Got: 0x%8h", num_rx[8:0], tvout_expected, xfft2real_dout_tdata);
$display("Expect differences of less than 2-3 bits due to rounding");
num_rx = num_rx + 1;
end // if c else
c = $fgetc(tvout_fd);
end // while not EOF
//xfft2real_dout_tready = 1'b0;
#200
$fclose(tvout_fd);
$finish;
end // initial
endmodule
|
// ghrd_10as066n2_axi_bridge_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_axi_bridge_0 #(
parameter USE_PIPELINE = 1,
parameter USE_M0_AWID = 1,
parameter USE_M0_AWREGION = 1,
parameter USE_M0_AWLEN = 1,
parameter USE_M0_AWSIZE = 1,
parameter USE_M0_AWBURST = 1,
parameter USE_M0_AWLOCK = 1,
parameter USE_M0_AWCACHE = 1,
parameter USE_M0_AWQOS = 1,
parameter USE_S0_AWREGION = 1,
parameter USE_S0_AWLOCK = 1,
parameter USE_S0_AWCACHE = 1,
parameter USE_S0_AWQOS = 1,
parameter USE_S0_AWPROT = 1,
parameter USE_M0_WSTRB = 1,
parameter USE_S0_WLAST = 1,
parameter USE_M0_BID = 1,
parameter USE_M0_BRESP = 1,
parameter USE_S0_BRESP = 1,
parameter USE_M0_ARID = 1,
parameter USE_M0_ARREGION = 1,
parameter USE_M0_ARLEN = 1,
parameter USE_M0_ARSIZE = 1,
parameter USE_M0_ARBURST = 1,
parameter USE_M0_ARLOCK = 1,
parameter USE_M0_ARCACHE = 1,
parameter USE_M0_ARQOS = 1,
parameter USE_S0_ARREGION = 1,
parameter USE_S0_ARLOCK = 1,
parameter USE_S0_ARCACHE = 1,
parameter USE_S0_ARQOS = 1,
parameter USE_S0_ARPROT = 1,
parameter USE_M0_RID = 1,
parameter USE_M0_RRESP = 1,
parameter USE_M0_RLAST = 1,
parameter USE_S0_RRESP = 1,
parameter M0_ID_WIDTH = 3,
parameter S0_ID_WIDTH = 6,
parameter DATA_WIDTH = 512,
parameter WRITE_ADDR_USER_WIDTH = 32,
parameter READ_ADDR_USER_WIDTH = 32,
parameter WRITE_DATA_USER_WIDTH = 32,
parameter WRITE_RESP_USER_WIDTH = 32,
parameter READ_DATA_USER_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter USE_S0_AWUSER = 0,
parameter USE_S0_ARUSER = 0,
parameter USE_S0_WUSER = 0,
parameter USE_S0_RUSER = 0,
parameter USE_S0_BUSER = 0,
parameter USE_M0_AWUSER = 0,
parameter USE_M0_ARUSER = 0,
parameter USE_M0_WUSER = 0,
parameter USE_M0_RUSER = 0,
parameter USE_M0_BUSER = 0,
parameter AXI_VERSION = "AXI4"
) (
input wire aclk, // clk.clk
input wire aresetn, // clk_reset.reset_n
output wire [2:0] m0_awid, // m0.awid
output wire [31:0] m0_awaddr, // .awaddr
output wire [7:0] m0_awlen, // .awlen
output wire [2:0] m0_awsize, // .awsize
output wire [1:0] m0_awburst, // .awburst
output wire [0:0] m0_awlock, // .awlock
output wire [3:0] m0_awcache, // .awcache
output wire [2:0] m0_awprot, // .awprot
output wire [3:0] m0_awqos, // .awqos
output wire [3:0] m0_awregion, // .awregion
output wire m0_awvalid, // .awvalid
input wire m0_awready, // .awready
output wire [511:0] m0_wdata, // .wdata
output wire [63:0] m0_wstrb, // .wstrb
output wire m0_wlast, // .wlast
output wire m0_wvalid, // .wvalid
input wire m0_wready, // .wready
input wire [2:0] m0_bid, // .bid
input wire [1:0] m0_bresp, // .bresp
input wire m0_bvalid, // .bvalid
output wire m0_bready, // .bready
output wire [2:0] m0_arid, // .arid
output wire [31:0] m0_araddr, // .araddr
output wire [7:0] m0_arlen, // .arlen
output wire [2:0] m0_arsize, // .arsize
output wire [1:0] m0_arburst, // .arburst
output wire [0:0] m0_arlock, // .arlock
output wire [3:0] m0_arcache, // .arcache
output wire [2:0] m0_arprot, // .arprot
output wire [3:0] m0_arqos, // .arqos
output wire [3:0] m0_arregion, // .arregion
output wire m0_arvalid, // .arvalid
input wire m0_arready, // .arready
input wire [2:0] m0_rid, // .rid
input wire [511:0] m0_rdata, // .rdata
input wire [1:0] m0_rresp, // .rresp
input wire m0_rlast, // .rlast
input wire m0_rvalid, // .rvalid
output wire m0_rready, // .rready
input wire [5:0] s0_awid, // s0.awid
input wire [31:0] s0_awaddr, // .awaddr
input wire [7:0] s0_awlen, // .awlen
input wire [2:0] s0_awsize, // .awsize
input wire [1:0] s0_awburst, // .awburst
input wire [0:0] s0_awlock, // .awlock
input wire [3:0] s0_awcache, // .awcache
input wire [2:0] s0_awprot, // .awprot
input wire [3:0] s0_awqos, // .awqos
input wire [3:0] s0_awregion, // .awregion
input wire s0_awvalid, // .awvalid
output wire s0_awready, // .awready
input wire [511:0] s0_wdata, // .wdata
input wire [63:0] s0_wstrb, // .wstrb
input wire s0_wlast, // .wlast
input wire s0_wvalid, // .wvalid
output wire s0_wready, // .wready
output wire [5:0] s0_bid, // .bid
output wire [1:0] s0_bresp, // .bresp
output wire s0_bvalid, // .bvalid
input wire s0_bready, // .bready
input wire [5:0] s0_arid, // .arid
input wire [31:0] s0_araddr, // .araddr
input wire [7:0] s0_arlen, // .arlen
input wire [2:0] s0_arsize, // .arsize
input wire [1:0] s0_arburst, // .arburst
input wire [0:0] s0_arlock, // .arlock
input wire [3:0] s0_arcache, // .arcache
input wire [2:0] s0_arprot, // .arprot
input wire [3:0] s0_arqos, // .arqos
input wire [3:0] s0_arregion, // .arregion
input wire s0_arvalid, // .arvalid
output wire s0_arready, // .arready
output wire [5:0] s0_rid, // .rid
output wire [511:0] s0_rdata, // .rdata
output wire [1:0] s0_rresp, // .rresp
output wire s0_rlast, // .rlast
output wire s0_rvalid, // .rvalid
input wire s0_rready // .rready
);
altera_axi_bridge #(
.USE_PIPELINE (USE_PIPELINE),
.USE_M0_AWID (USE_M0_AWID),
.USE_M0_AWREGION (USE_M0_AWREGION),
.USE_M0_AWLEN (USE_M0_AWLEN),
.USE_M0_AWSIZE (USE_M0_AWSIZE),
.USE_M0_AWBURST (USE_M0_AWBURST),
.USE_M0_AWLOCK (USE_M0_AWLOCK),
.USE_M0_AWCACHE (USE_M0_AWCACHE),
.USE_M0_AWQOS (USE_M0_AWQOS),
.USE_S0_AWREGION (USE_S0_AWREGION),
.USE_S0_AWLOCK (USE_S0_AWLOCK),
.USE_S0_AWCACHE (USE_S0_AWCACHE),
.USE_S0_AWQOS (USE_S0_AWQOS),
.USE_S0_AWPROT (USE_S0_AWPROT),
.USE_M0_WSTRB (USE_M0_WSTRB),
.USE_S0_WLAST (USE_S0_WLAST),
.USE_M0_BID (USE_M0_BID),
.USE_M0_BRESP (USE_M0_BRESP),
.USE_S0_BRESP (USE_S0_BRESP),
.USE_M0_ARID (USE_M0_ARID),
.USE_M0_ARREGION (USE_M0_ARREGION),
.USE_M0_ARLEN (USE_M0_ARLEN),
.USE_M0_ARSIZE (USE_M0_ARSIZE),
.USE_M0_ARBURST (USE_M0_ARBURST),
.USE_M0_ARLOCK (USE_M0_ARLOCK),
.USE_M0_ARCACHE (USE_M0_ARCACHE),
.USE_M0_ARQOS (USE_M0_ARQOS),
.USE_S0_ARREGION (USE_S0_ARREGION),
.USE_S0_ARLOCK (USE_S0_ARLOCK),
.USE_S0_ARCACHE (USE_S0_ARCACHE),
.USE_S0_ARQOS (USE_S0_ARQOS),
.USE_S0_ARPROT (USE_S0_ARPROT),
.USE_M0_RID (USE_M0_RID),
.USE_M0_RRESP (USE_M0_RRESP),
.USE_M0_RLAST (USE_M0_RLAST),
.USE_S0_RRESP (USE_S0_RRESP),
.M0_ID_WIDTH (M0_ID_WIDTH),
.S0_ID_WIDTH (S0_ID_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.WRITE_ADDR_USER_WIDTH (WRITE_ADDR_USER_WIDTH),
.READ_ADDR_USER_WIDTH (READ_ADDR_USER_WIDTH),
.WRITE_DATA_USER_WIDTH (WRITE_DATA_USER_WIDTH),
.WRITE_RESP_USER_WIDTH (WRITE_RESP_USER_WIDTH),
.READ_DATA_USER_WIDTH (READ_DATA_USER_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.USE_S0_AWUSER (USE_S0_AWUSER),
.USE_S0_ARUSER (USE_S0_ARUSER),
.USE_S0_WUSER (USE_S0_WUSER),
.USE_S0_RUSER (USE_S0_RUSER),
.USE_S0_BUSER (USE_S0_BUSER),
.USE_M0_AWUSER (USE_M0_AWUSER),
.USE_M0_ARUSER (USE_M0_ARUSER),
.USE_M0_WUSER (USE_M0_WUSER),
.USE_M0_RUSER (USE_M0_RUSER),
.USE_M0_BUSER (USE_M0_BUSER),
.AXI_VERSION (AXI_VERSION),
.BURST_LENGTH_WIDTH (8),
.LOCK_WIDTH (1)
) axi_bridge_0 (
.aclk (aclk), // input, width = 1, clk.clk
.aresetn (aresetn), // input, width = 1, clk_reset.reset_n
.s0_awid (s0_awid), // input, width = 6, s0.awid
.s0_awaddr (s0_awaddr), // input, width = 32, .awaddr
.s0_awlen (s0_awlen), // input, width = 8, .awlen
.s0_awsize (s0_awsize), // input, width = 3, .awsize
.s0_awburst (s0_awburst), // input, width = 2, .awburst
.s0_awlock (s0_awlock), // input, width = 1, .awlock
.s0_awcache (s0_awcache), // input, width = 4, .awcache
.s0_awprot (s0_awprot), // input, width = 3, .awprot
.s0_awqos (s0_awqos), // input, width = 4, .awqos
.s0_awregion (s0_awregion), // input, width = 4, .awregion
.s0_awvalid (s0_awvalid), // input, width = 1, .awvalid
.s0_awready (s0_awready), // output, width = 1, .awready
.s0_wdata (s0_wdata), // input, width = 512, .wdata
.s0_wstrb (s0_wstrb), // input, width = 64, .wstrb
.s0_wlast (s0_wlast), // input, width = 1, .wlast
.s0_wvalid (s0_wvalid), // input, width = 1, .wvalid
.s0_wready (s0_wready), // output, width = 1, .wready
.s0_bid (s0_bid), // output, width = 6, .bid
.s0_bresp (s0_bresp), // output, width = 2, .bresp
.s0_bvalid (s0_bvalid), // output, width = 1, .bvalid
.s0_bready (s0_bready), // input, width = 1, .bready
.s0_arid (s0_arid), // input, width = 6, .arid
.s0_araddr (s0_araddr), // input, width = 32, .araddr
.s0_arlen (s0_arlen), // input, width = 8, .arlen
.s0_arsize (s0_arsize), // input, width = 3, .arsize
.s0_arburst (s0_arburst), // input, width = 2, .arburst
.s0_arlock (s0_arlock), // input, width = 1, .arlock
.s0_arcache (s0_arcache), // input, width = 4, .arcache
.s0_arprot (s0_arprot), // input, width = 3, .arprot
.s0_arqos (s0_arqos), // input, width = 4, .arqos
.s0_arregion (s0_arregion), // input, width = 4, .arregion
.s0_arvalid (s0_arvalid), // input, width = 1, .arvalid
.s0_arready (s0_arready), // output, width = 1, .arready
.s0_rid (s0_rid), // output, width = 6, .rid
.s0_rdata (s0_rdata), // output, width = 512, .rdata
.s0_rresp (s0_rresp), // output, width = 2, .rresp
.s0_rlast (s0_rlast), // output, width = 1, .rlast
.s0_rvalid (s0_rvalid), // output, width = 1, .rvalid
.s0_rready (s0_rready), // input, width = 1, .rready
.m0_awid (m0_awid), // output, width = 3, m0.awid
.m0_awaddr (m0_awaddr), // output, width = 32, .awaddr
.m0_awlen (m0_awlen), // output, width = 8, .awlen
.m0_awsize (m0_awsize), // output, width = 3, .awsize
.m0_awburst (m0_awburst), // output, width = 2, .awburst
.m0_awlock (m0_awlock), // output, width = 1, .awlock
.m0_awcache (m0_awcache), // output, width = 4, .awcache
.m0_awprot (m0_awprot), // output, width = 3, .awprot
.m0_awqos (m0_awqos), // output, width = 4, .awqos
.m0_awregion (m0_awregion), // output, width = 4, .awregion
.m0_awvalid (m0_awvalid), // output, width = 1, .awvalid
.m0_awready (m0_awready), // input, width = 1, .awready
.m0_wdata (m0_wdata), // output, width = 512, .wdata
.m0_wstrb (m0_wstrb), // output, width = 64, .wstrb
.m0_wlast (m0_wlast), // output, width = 1, .wlast
.m0_wvalid (m0_wvalid), // output, width = 1, .wvalid
.m0_wready (m0_wready), // input, width = 1, .wready
.m0_bid (m0_bid), // input, width = 3, .bid
.m0_bresp (m0_bresp), // input, width = 2, .bresp
.m0_bvalid (m0_bvalid), // input, width = 1, .bvalid
.m0_bready (m0_bready), // output, width = 1, .bready
.m0_arid (m0_arid), // output, width = 3, .arid
.m0_araddr (m0_araddr), // output, width = 32, .araddr
.m0_arlen (m0_arlen), // output, width = 8, .arlen
.m0_arsize (m0_arsize), // output, width = 3, .arsize
.m0_arburst (m0_arburst), // output, width = 2, .arburst
.m0_arlock (m0_arlock), // output, width = 1, .arlock
.m0_arcache (m0_arcache), // output, width = 4, .arcache
.m0_arprot (m0_arprot), // output, width = 3, .arprot
.m0_arqos (m0_arqos), // output, width = 4, .arqos
.m0_arregion (m0_arregion), // output, width = 4, .arregion
.m0_arvalid (m0_arvalid), // output, width = 1, .arvalid
.m0_arready (m0_arready), // input, width = 1, .arready
.m0_rid (m0_rid), // input, width = 3, .rid
.m0_rdata (m0_rdata), // input, width = 512, .rdata
.m0_rresp (m0_rresp), // input, width = 2, .rresp
.m0_rlast (m0_rlast), // input, width = 1, .rlast
.m0_rvalid (m0_rvalid), // input, width = 1, .rvalid
.m0_rready (m0_rready), // output, width = 1, .rready
.s0_awuser (32'b00000000000000000000000000000000), // (terminated),
.s0_wuser (32'b00000000000000000000000000000000), // (terminated),
.s0_buser (), // (terminated),
.s0_aruser (32'b00000000000000000000000000000000), // (terminated),
.s0_ruser (), // (terminated),
.m0_awuser (), // (terminated),
.m0_wuser (), // (terminated),
.m0_buser (32'b00000000000000000000000000000000), // (terminated),
.m0_aruser (), // (terminated),
.m0_ruser (32'b00000000000000000000000000000000), // (terminated),
.m0_wid (), // (terminated),
.s0_wid (6'b000000) // (terminated),
);
endmodule
|
// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
`define USEAND 0 // No available documentation provides for macros without values so we use 0
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule
`ifndef USEAND
`include "ifndef_else_module_a_and.v"
`else
`include "ifndef_else_module_a_or.v"
`endif
`include "ifndef_else_module_b.v"
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_rptr_groups.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module fpu_rptr_groups (
inq_in1,
inq_in2,
inq_id,
inq_op,
inq_rnd_mode,
inq_in1_50_0_neq_0,
inq_in1_53_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_50_0_neq_0,
inq_in2_53_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
ctu_tst_macrotest,
ctu_tst_pre_grst_l,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_short_chain,
global_shift_enable,
grst_l,
cluster_cken,
se,
arst_l,
fpu_grst_l,
fmul_clken_l,
fdiv_clken_l,
scan_manual_6,
si,
so_unbuf,
pcx_fpio_data_px2,
pcx_fpio_data_rdy_px2,
fp_cpx_req_cq,
fp_cpx_data_ca,
inq_sram_din_unbuf,
inq_in1_add_buf1,
inq_in1_mul_buf1,
inq_in1_div_buf1,
inq_in2_add_buf1,
inq_in2_mul_buf1,
inq_in2_div_buf1,
inq_id_add_buf1,
inq_id_mul_buf1,
inq_id_div_buf1,
inq_op_add_buf1,
inq_op_div_buf1,
inq_op_mul_buf1,
inq_rnd_mode_add_buf1,
inq_rnd_mode_div_buf1,
inq_rnd_mode_mul_buf1,
inq_in1_50_0_neq_0_add_buf1,
inq_in1_50_0_neq_0_mul_buf1,
inq_in1_50_0_neq_0_div_buf1,
inq_in1_53_0_neq_0_add_buf1,
inq_in1_53_0_neq_0_mul_buf1,
inq_in1_53_0_neq_0_div_buf1,
inq_in1_53_32_neq_0_add_buf1,
inq_in1_53_32_neq_0_mul_buf1,
inq_in1_53_32_neq_0_div_buf1,
inq_in1_exp_eq_0_add_buf1,
inq_in1_exp_eq_0_mul_buf1,
inq_in1_exp_eq_0_div_buf1,
inq_in1_exp_neq_ffs_add_buf1,
inq_in1_exp_neq_ffs_mul_buf1,
inq_in1_exp_neq_ffs_div_buf1,
inq_in2_50_0_neq_0_add_buf1,
inq_in2_50_0_neq_0_mul_buf1,
inq_in2_50_0_neq_0_div_buf1,
inq_in2_53_0_neq_0_add_buf1,
inq_in2_53_0_neq_0_mul_buf1,
inq_in2_53_0_neq_0_div_buf1,
inq_in2_53_32_neq_0_add_buf1,
inq_in2_53_32_neq_0_mul_buf1,
inq_in2_53_32_neq_0_div_buf1,
inq_in2_exp_eq_0_add_buf1,
inq_in2_exp_eq_0_mul_buf1,
inq_in2_exp_eq_0_div_buf1,
inq_in2_exp_neq_ffs_add_buf1,
inq_in2_exp_neq_ffs_mul_buf1,
inq_in2_exp_neq_ffs_div_buf1,
ctu_tst_macrotest_buf1,
ctu_tst_pre_grst_l_buf1,
ctu_tst_scan_disable_buf1,
ctu_tst_scanmode_buf1,
ctu_tst_short_chain_buf1,
global_shift_enable_buf1,
grst_l_buf1,
cluster_cken_buf1,
se_add_exp_buf2,
se_add_frac_buf2,
se_out_buf2,
se_mul64_buf2,
se_cluster_header_buf2,
se_in_buf3,
se_mul_buf4,
se_div_buf5,
arst_l_div_buf2,
arst_l_mul_buf2,
arst_l_cluster_header_buf2,
arst_l_in_buf3,
arst_l_out_buf3,
arst_l_add_buf4,
fpu_grst_l_mul_buf1,
fpu_grst_l_in_buf2,
fpu_grst_l_add_buf3,
fmul_clken_l_buf1,
fdiv_clken_l_div_exp_buf1,
fdiv_clken_l_div_frac_buf1,
scan_manual_6_buf1,
si_buf1,
so,
pcx_fpio_data_px2_buf1,
pcx_fpio_data_rdy_px2_buf1,
fp_cpx_req_cq_buf1,
fp_cpx_data_ca_buf1,
inq_sram_din_buf1
);
input [63:0] inq_in1;
input [63:0] inq_in2;
input [4:0] inq_id;
input [7:0] inq_op;
input [1:0] inq_rnd_mode;
input inq_in1_50_0_neq_0;
input inq_in1_53_0_neq_0;
input inq_in1_53_32_neq_0;
input inq_in1_exp_eq_0;
input inq_in1_exp_neq_ffs;
input inq_in2_50_0_neq_0;
input inq_in2_53_0_neq_0;
input inq_in2_53_32_neq_0;
input inq_in2_exp_eq_0;
input inq_in2_exp_neq_ffs;
input ctu_tst_macrotest;
input ctu_tst_pre_grst_l;
input ctu_tst_scan_disable;
input ctu_tst_scanmode;
input ctu_tst_short_chain;
input global_shift_enable;
input grst_l;
input cluster_cken;
input se;
input arst_l;
input fpu_grst_l;
input fmul_clken_l;
input fdiv_clken_l;
input scan_manual_6;
input si;
input so_unbuf;
input [123:0] pcx_fpio_data_px2;
input pcx_fpio_data_rdy_px2;
input [7:0] fp_cpx_req_cq;
input [144:0] fp_cpx_data_ca;
input [155:0] inq_sram_din_unbuf;
output [63:0] inq_in1_add_buf1;
output [63:0] inq_in1_mul_buf1;
output [63:0] inq_in1_div_buf1;
output [63:0] inq_in2_add_buf1;
output [63:0] inq_in2_mul_buf1;
output [63:0] inq_in2_div_buf1;
output [4:0] inq_id_add_buf1;
output [4:0] inq_id_mul_buf1;
output [4:0] inq_id_div_buf1;
output [7:0] inq_op_add_buf1;
output [7:0] inq_op_mul_buf1;
output [7:0] inq_op_div_buf1;
output [1:0] inq_rnd_mode_add_buf1;
output [1:0] inq_rnd_mode_mul_buf1;
output [1:0] inq_rnd_mode_div_buf1;
output inq_in1_50_0_neq_0_add_buf1;
output inq_in1_50_0_neq_0_mul_buf1;
output inq_in1_50_0_neq_0_div_buf1;
output inq_in1_53_0_neq_0_add_buf1;
output inq_in1_53_0_neq_0_mul_buf1;
output inq_in1_53_0_neq_0_div_buf1;
output inq_in1_53_32_neq_0_add_buf1;
output inq_in1_53_32_neq_0_mul_buf1;
output inq_in1_53_32_neq_0_div_buf1;
output inq_in1_exp_eq_0_add_buf1;
output inq_in1_exp_eq_0_mul_buf1;
output inq_in1_exp_eq_0_div_buf1;
output inq_in1_exp_neq_ffs_add_buf1;
output inq_in1_exp_neq_ffs_mul_buf1;
output inq_in1_exp_neq_ffs_div_buf1;
output inq_in2_50_0_neq_0_add_buf1;
output inq_in2_50_0_neq_0_mul_buf1;
output inq_in2_50_0_neq_0_div_buf1;
output inq_in2_53_0_neq_0_add_buf1;
output inq_in2_53_0_neq_0_mul_buf1;
output inq_in2_53_0_neq_0_div_buf1;
output inq_in2_53_32_neq_0_add_buf1;
output inq_in2_53_32_neq_0_mul_buf1;
output inq_in2_53_32_neq_0_div_buf1;
output inq_in2_exp_eq_0_add_buf1;
output inq_in2_exp_eq_0_mul_buf1;
output inq_in2_exp_eq_0_div_buf1;
output inq_in2_exp_neq_ffs_add_buf1;
output inq_in2_exp_neq_ffs_mul_buf1;
output inq_in2_exp_neq_ffs_div_buf1;
output ctu_tst_macrotest_buf1;
output ctu_tst_pre_grst_l_buf1;
output ctu_tst_scan_disable_buf1;
output ctu_tst_scanmode_buf1;
output ctu_tst_short_chain_buf1;
output global_shift_enable_buf1;
output grst_l_buf1;
output cluster_cken_buf1;
output se_add_exp_buf2;
output se_add_frac_buf2;
output se_out_buf2;
output se_mul64_buf2;
output se_cluster_header_buf2;
output se_in_buf3;
output se_mul_buf4;
output se_div_buf5;
output arst_l_div_buf2;
output arst_l_mul_buf2;
output arst_l_cluster_header_buf2;
output arst_l_in_buf3;
output arst_l_out_buf3;
output arst_l_add_buf4;
output fpu_grst_l_mul_buf1;
output fpu_grst_l_in_buf2;
output fpu_grst_l_add_buf3;
output fmul_clken_l_buf1;
output fdiv_clken_l_div_exp_buf1;
output fdiv_clken_l_div_frac_buf1;
output scan_manual_6_buf1;
output si_buf1;
output so;
output [123:0] pcx_fpio_data_px2_buf1;
output pcx_fpio_data_rdy_px2_buf1;
output [7:0] fp_cpx_req_cq_buf1;
output [144:0] fp_cpx_data_ca_buf1;
output [155:0] inq_sram_din_buf1;
wire [3:0] inq_id_add_buf1_unused;
wire [2:0] inq_id_mul_buf1_unused;
wire [4:0] inq_id_div_buf1_unused;
wire [1:0] ctu_tst_buf1_lo_unused;
wire [1:0] cluster_cken_buf1_unused;
wire [1:0] se_mul64_buf2_unused;
wire [2:0] arst_l_buf1_unused;
wire [1:0] fdiv_clken_l_buf1_unused;
wire [2:0] so_cluster_header_buf1_unused;
wire [2:0] si_buf1_unused;
wire [2:0] pcx_fpio_data_px2_buf1_unused;
wire [5:0] fp_cpx_buf1_9_unused;
// inq_in1
fpu_bufrpt_grp32 i_inq_in1_add_buf1_hi (
.in (inq_in1[63:32]),
.out (inq_in1_add_buf1[63:32])
);
fpu_bufrpt_grp32 i_inq_in1_add_buf1_lo (
.in (inq_in1[31:0]),
.out (inq_in1_add_buf1[31:0])
);
fpu_bufrpt_grp32 i_inq_in1_mul_buf1_hi (
.in (inq_in1[63:32]),
.out (inq_in1_mul_buf1[63:32])
);
fpu_bufrpt_grp32 i_inq_in1_mul_buf1_lo (
.in (inq_in1[31:0]),
.out (inq_in1_mul_buf1[31:0])
);
fpu_bufrpt_grp64 i_inq_in1_div_buf1 (
.in (inq_in1[63:0]),
.out (inq_in1_div_buf1[63:0])
);
// inq_in2
fpu_bufrpt_grp32 i_inq_in2_add_buf1_hi (
.in (inq_in2[63:32]),
.out (inq_in2_add_buf1[63:32])
);
fpu_bufrpt_grp32 i_inq_in2_add_buf1_lo (
.in (inq_in2[31:0]),
.out (inq_in2_add_buf1[31:0])
);
fpu_bufrpt_grp32 i_inq_in2_mul_buf1_hi (
.in (inq_in2[63:32]),
.out (inq_in2_mul_buf1[63:32])
);
fpu_bufrpt_grp32 i_inq_in2_mul_buf1_lo (
.in (inq_in2[31:0]),
.out (inq_in2_mul_buf1[31:0])
);
fpu_bufrpt_grp64 i_inq_in2_div_buf1 (
.in (inq_in2[63:0]),
.out (inq_in2_div_buf1[63:0])
);
// group inq_*eq_*
fpu_bufrpt_grp32 i_inq_id_add_buf1 (
.in ({4'h0,
se_out_buf2,
arst_l_out_buf3,
fpu_grst_l_in_buf2,
inq_id[4:0],
inq_op[7:0],
inq_rnd_mode[1:0],
inq_in1_50_0_neq_0,
inq_in1_53_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_50_0_neq_0,
inq_in2_53_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs}),
.out ({inq_id_add_buf1_unused[3:0],
se_in_buf3,
arst_l_add_buf4,
fpu_grst_l_add_buf3,
inq_id_add_buf1[4:0],
inq_op_add_buf1[7:0],
inq_rnd_mode_add_buf1[1:0],
inq_in1_50_0_neq_0_add_buf1,
inq_in1_53_0_neq_0_add_buf1,
inq_in1_53_32_neq_0_add_buf1,
inq_in1_exp_eq_0_add_buf1,
inq_in1_exp_neq_ffs_add_buf1,
inq_in2_50_0_neq_0_add_buf1,
inq_in2_53_0_neq_0_add_buf1,
inq_in2_53_32_neq_0_add_buf1,
inq_in2_exp_eq_0_add_buf1,
inq_in2_exp_neq_ffs_add_buf1})
);
fpu_bufrpt_grp32 i_inq_id_mul_buf1 (
.in ({3'h0,
se_in_buf3,
arst_l_mul_buf2,
fpu_grst_l_mul_buf1,
fmul_clken_l,
inq_id[4:0],
inq_op[7:0],
inq_rnd_mode[1:0],
inq_in1_50_0_neq_0,
inq_in1_53_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_50_0_neq_0,
inq_in2_53_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs}),
.out ({inq_id_mul_buf1_unused[2:0],
se_mul_buf4,
arst_l_out_buf3,
fpu_grst_l_in_buf2,
fmul_clken_l_buf1,
inq_id_mul_buf1[4:0],
inq_op_mul_buf1[7:0],
inq_rnd_mode_mul_buf1[1:0],
inq_in1_50_0_neq_0_mul_buf1,
inq_in1_53_0_neq_0_mul_buf1,
inq_in1_53_32_neq_0_mul_buf1,
inq_in1_exp_eq_0_mul_buf1,
inq_in1_exp_neq_ffs_mul_buf1,
inq_in2_50_0_neq_0_mul_buf1,
inq_in2_53_0_neq_0_mul_buf1,
inq_in2_53_32_neq_0_mul_buf1,
inq_in2_exp_eq_0_mul_buf1,
inq_in2_exp_neq_ffs_mul_buf1})
);
fpu_bufrpt_grp32 i_inq_id_div_buf1 (
.in ({5'h00,
se_mul_buf4,
arst_l_mul_buf2,
inq_id[4:0],
inq_op[7:0],
inq_rnd_mode[1:0],
inq_in1_50_0_neq_0,
inq_in1_53_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_50_0_neq_0,
inq_in2_53_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs}),
.out ({inq_id_div_buf1_unused[4:0],
se_div_buf5,
arst_l_in_buf3,
inq_id_div_buf1[4:0],
inq_op_div_buf1[7:0],
inq_rnd_mode_div_buf1[1:0],
inq_in1_50_0_neq_0_div_buf1,
inq_in1_53_0_neq_0_div_buf1,
inq_in1_53_32_neq_0_div_buf1,
inq_in1_exp_eq_0_div_buf1,
inq_in1_exp_neq_ffs_div_buf1,
inq_in2_50_0_neq_0_div_buf1,
inq_in2_53_0_neq_0_div_buf1,
inq_in2_53_32_neq_0_div_buf1,
inq_in2_exp_eq_0_div_buf1,
inq_in2_exp_neq_ffs_div_buf1})
);
// buffer ctu_tst signals
fpu_bufrpt_grp4 i_ctu_tst_buf1_hi (
.in ({ctu_tst_short_chain,
ctu_tst_macrotest,
ctu_tst_scan_disable,
ctu_tst_pre_grst_l}),
.out ({ctu_tst_short_chain_buf1,
ctu_tst_macrotest_buf1,
ctu_tst_scan_disable_buf1,
ctu_tst_pre_grst_l_buf1})
);
fpu_bufrpt_grp4 i_ctu_tst_buf1_lo (
.in ({ctu_tst_scanmode,
global_shift_enable,
2'b00}),
.out ({ctu_tst_scanmode_buf1,
global_shift_enable_buf1,
ctu_tst_buf1_lo_unused[1:0]})
);
// buffer cluster_header inputs
fpu_bufrpt_grp4 i_cluster_cken_buf1 (
.in ({cluster_cken,
grst_l,
2'b00}),
.out ({cluster_cken_buf1,
grst_l_buf1,
cluster_cken_buf1_unused[1:0]})
);
// buffers for se (scan enable driven from test_stub_scan)
fpu_bufrpt_grp4 i_se_buf1 (
.in ({se,
se,
so_unbuf,
1'b0}),
.out ({se_add_buf1,
se_mul64_buf1,
so_buf1,
se_buf1_unused})
);
fpu_bufrpt_grp4 i_se_add_buf2 (
.in ({se_add_buf1,
se_add_buf1,
se_add_buf1,
1'b0}),
.out ({se_add_exp_buf2,
se_add_frac_buf2,
se_out_buf2,
se_add_buf2_unused})
);
fpu_bufrpt_grp4 i_se_mul64_buf2 (
.in ({se_mul64_buf1,
se_mul64_buf1,
2'b00}),
.out ({se_mul64_buf2,
se_cluster_header_buf2,
se_mul64_buf2_unused[1:0]})
);
// buffers for arst_l, also use to buffer fpu_grst_l
fpu_bufrpt_grp4 i_arst_l_buf1 (
.in ({arst_l,
3'b000}),
.out ({arst_l_buf1,
arst_l_buf1_unused[2:0]})
);
fpu_bufrpt_grp4 i_arst_l_buf2 (
.in ({arst_l_buf1,
arst_l_buf1,
arst_l_buf1,
fpu_grst_l}),
.out ({arst_l_mul_buf2,
arst_l_cluster_header_buf2,
arst_l_div_buf2,
fpu_grst_l_mul_buf1})
);
// buffers for fdiv_clken_l
fpu_bufrpt_grp4 i_fdiv_clken_l_buf1 (
.in ({fdiv_clken_l,
fdiv_clken_l,
2'b00}),
.out ({fdiv_clken_l_div_exp_buf1,
fdiv_clken_l_div_frac_buf1,
fdiv_clken_l_buf1_unused[1:0]})
);
// buffer scan_out from cluster_header (internal driver 2X) to test_stub (long_chain_so_0)
fpu_bufrpt_grp4 i_so_cluster_header_buf1 (
.in ({scan_manual_6,
3'b000}),
.out ({scan_manual_6_buf1,
so_cluster_header_buf1_unused[2:0]})
);
// buffer si at FPU cluster right edge
fpu_bufrpt_grp4 i_si_buf1 (
.in ({si,
3'b000}),
.out ({si_buf1,
si_buf1_unused[2:0]})
);
// pcx_fpio* signals buffered for mintiming
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_0 (
.in ({pcx_fpio_data_px2[108],
pcx_fpio_data_px2[109],
pcx_fpio_data_px2[110],
pcx_fpio_data_px2[111],
pcx_fpio_data_px2[112],
pcx_fpio_data_px2[113],
pcx_fpio_data_px2[114],
pcx_fpio_data_px2[115],
pcx_fpio_data_px2[116],
pcx_fpio_data_px2[117],
pcx_fpio_data_px2[118],
pcx_fpio_data_px2[119],
pcx_fpio_data_px2[120],
pcx_fpio_data_px2[121],
pcx_fpio_data_px2[122],
pcx_fpio_data_px2[123]}),
.out ({pcx_fpio_data_px2_buf1[108],
pcx_fpio_data_px2_buf1[109],
pcx_fpio_data_px2_buf1[110],
pcx_fpio_data_px2_buf1[111],
pcx_fpio_data_px2_buf1[112],
pcx_fpio_data_px2_buf1[113],
pcx_fpio_data_px2_buf1[114],
pcx_fpio_data_px2_buf1[115],
pcx_fpio_data_px2_buf1[116],
pcx_fpio_data_px2_buf1[117],
pcx_fpio_data_px2_buf1[118],
pcx_fpio_data_px2_buf1[119],
pcx_fpio_data_px2_buf1[120],
pcx_fpio_data_px2_buf1[121],
pcx_fpio_data_px2_buf1[122],
pcx_fpio_data_px2_buf1[123]})
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_1 (
.in ({pcx_fpio_data_px2[92],
pcx_fpio_data_px2[93],
pcx_fpio_data_px2[94],
pcx_fpio_data_px2[95],
pcx_fpio_data_px2[96],
pcx_fpio_data_px2[97],
pcx_fpio_data_px2[98],
pcx_fpio_data_px2[99],
pcx_fpio_data_px2[100],
pcx_fpio_data_px2[101],
pcx_fpio_data_px2[102],
pcx_fpio_data_px2[103],
pcx_fpio_data_px2[104],
pcx_fpio_data_px2[105],
pcx_fpio_data_px2[106],
pcx_fpio_data_px2[107]}),
.out ({pcx_fpio_data_px2_buf1[92],
pcx_fpio_data_px2_buf1[93],
pcx_fpio_data_px2_buf1[94],
pcx_fpio_data_px2_buf1[95],
pcx_fpio_data_px2_buf1[96],
pcx_fpio_data_px2_buf1[97],
pcx_fpio_data_px2_buf1[98],
pcx_fpio_data_px2_buf1[99],
pcx_fpio_data_px2_buf1[100],
pcx_fpio_data_px2_buf1[101],
pcx_fpio_data_px2_buf1[102],
pcx_fpio_data_px2_buf1[103],
pcx_fpio_data_px2_buf1[104],
pcx_fpio_data_px2_buf1[105],
pcx_fpio_data_px2_buf1[106],
pcx_fpio_data_px2_buf1[107]})
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_2 (
.in ({pcx_fpio_data_px2[76],
pcx_fpio_data_px2[77],
pcx_fpio_data_px2[78],
pcx_fpio_data_px2[79],
pcx_fpio_data_px2[80],
pcx_fpio_data_px2[81],
pcx_fpio_data_px2[82],
pcx_fpio_data_px2[83],
pcx_fpio_data_px2[84],
pcx_fpio_data_px2[85],
pcx_fpio_data_px2[86],
pcx_fpio_data_px2[87],
pcx_fpio_data_px2[88],
pcx_fpio_data_px2[89],
pcx_fpio_data_px2[90],
pcx_fpio_data_px2[91]}),
.out ({pcx_fpio_data_px2_buf1[76],
pcx_fpio_data_px2_buf1[77],
pcx_fpio_data_px2_buf1[78],
pcx_fpio_data_px2_buf1[79],
pcx_fpio_data_px2_buf1[80],
pcx_fpio_data_px2_buf1[81],
pcx_fpio_data_px2_buf1[82],
pcx_fpio_data_px2_buf1[83],
pcx_fpio_data_px2_buf1[84],
pcx_fpio_data_px2_buf1[85],
pcx_fpio_data_px2_buf1[86],
pcx_fpio_data_px2_buf1[87],
pcx_fpio_data_px2_buf1[88],
pcx_fpio_data_px2_buf1[89],
pcx_fpio_data_px2_buf1[90],
pcx_fpio_data_px2_buf1[91]})
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_3 (
.in ({pcx_fpio_data_px2[3:0],
pcx_fpio_data_px2[64],
pcx_fpio_data_px2[65],
pcx_fpio_data_px2[66],
pcx_fpio_data_px2[67],
pcx_fpio_data_px2[68],
pcx_fpio_data_px2[69],
pcx_fpio_data_px2[70],
pcx_fpio_data_px2[71],
pcx_fpio_data_px2[72],
pcx_fpio_data_px2[73],
pcx_fpio_data_px2[74],
pcx_fpio_data_px2[75]}),
.out ({pcx_fpio_data_px2_buf1[3:0],
pcx_fpio_data_px2_buf1[64],
pcx_fpio_data_px2_buf1[65],
pcx_fpio_data_px2_buf1[66],
pcx_fpio_data_px2_buf1[67],
pcx_fpio_data_px2_buf1[68],
pcx_fpio_data_px2_buf1[69],
pcx_fpio_data_px2_buf1[70],
pcx_fpio_data_px2_buf1[71],
pcx_fpio_data_px2_buf1[72],
pcx_fpio_data_px2_buf1[73],
pcx_fpio_data_px2_buf1[74],
pcx_fpio_data_px2_buf1[75]})
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_4 (
.in (pcx_fpio_data_px2[19:4]),
.out (pcx_fpio_data_px2_buf1[19:4])
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_5 (
.in (pcx_fpio_data_px2[35:20]),
.out (pcx_fpio_data_px2_buf1[35:20])
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_6 (
.in ({pcx_fpio_data_rdy_px2,
pcx_fpio_data_px2[50:36]}),
.out ({pcx_fpio_data_rdy_px2_buf1,
pcx_fpio_data_px2_buf1[50:36]})
);
fpu_rptr_pcx_fpio_grp16 i_pcx_fpio_buf1_7 (
.in ({3'b000,
pcx_fpio_data_px2[63:51]}),
.out ({pcx_fpio_data_px2_buf1_unused[2:0],
pcx_fpio_data_px2_buf1[63:51]})
);
// buffer fp_cpx_* signals for mintiming
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_0 (
.in ({
fp_cpx_data_ca[142],
fp_cpx_data_ca[140],
fp_cpx_data_ca[138],
fp_cpx_data_ca[136],
fp_cpx_data_ca[134],
fp_cpx_data_ca[132],
fp_cpx_data_ca[130],
fp_cpx_data_ca[128],
fp_cpx_req_cq[6],
fp_cpx_req_cq[7],
fp_cpx_req_cq[3],
fp_cpx_req_cq[2],
fp_cpx_req_cq[5],
fp_cpx_req_cq[1],
fp_cpx_req_cq[0],
fp_cpx_req_cq[4]}),
.out ({
fp_cpx_data_ca_buf1[142],
fp_cpx_data_ca_buf1[140],
fp_cpx_data_ca_buf1[138],
fp_cpx_data_ca_buf1[136],
fp_cpx_data_ca_buf1[134],
fp_cpx_data_ca_buf1[132],
fp_cpx_data_ca_buf1[130],
fp_cpx_data_ca_buf1[128],
fp_cpx_req_cq_buf1[6],
fp_cpx_req_cq_buf1[7],
fp_cpx_req_cq_buf1[3],
fp_cpx_req_cq_buf1[2],
fp_cpx_req_cq_buf1[5],
fp_cpx_req_cq_buf1[1],
fp_cpx_req_cq_buf1[0],
fp_cpx_req_cq_buf1[4]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_1 (
.in ({
fp_cpx_data_ca[34],
fp_cpx_data_ca[36],
fp_cpx_data_ca[38],
fp_cpx_data_ca[40],
fp_cpx_data_ca[42],
fp_cpx_data_ca[44],
fp_cpx_data_ca[46],
fp_cpx_data_ca[48],
fp_cpx_data_ca[50],
fp_cpx_data_ca[52],
fp_cpx_data_ca[54],
fp_cpx_data_ca[56],
fp_cpx_data_ca[58],
fp_cpx_data_ca[60],
fp_cpx_data_ca[62],
fp_cpx_data_ca[144]}),
.out ({
fp_cpx_data_ca_buf1[34],
fp_cpx_data_ca_buf1[36],
fp_cpx_data_ca_buf1[38],
fp_cpx_data_ca_buf1[40],
fp_cpx_data_ca_buf1[42],
fp_cpx_data_ca_buf1[44],
fp_cpx_data_ca_buf1[46],
fp_cpx_data_ca_buf1[48],
fp_cpx_data_ca_buf1[50],
fp_cpx_data_ca_buf1[52],
fp_cpx_data_ca_buf1[54],
fp_cpx_data_ca_buf1[56],
fp_cpx_data_ca_buf1[58],
fp_cpx_data_ca_buf1[60],
fp_cpx_data_ca_buf1[62],
fp_cpx_data_ca_buf1[144]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_2 (
.in ({
fp_cpx_data_ca[2],
fp_cpx_data_ca[4],
fp_cpx_data_ca[6],
fp_cpx_data_ca[8],
fp_cpx_data_ca[10],
fp_cpx_data_ca[12],
fp_cpx_data_ca[14],
fp_cpx_data_ca[16],
fp_cpx_data_ca[18],
fp_cpx_data_ca[20],
fp_cpx_data_ca[22],
fp_cpx_data_ca[24],
fp_cpx_data_ca[26],
fp_cpx_data_ca[28],
fp_cpx_data_ca[30],
fp_cpx_data_ca[32]}),
.out ({
fp_cpx_data_ca_buf1[2],
fp_cpx_data_ca_buf1[4],
fp_cpx_data_ca_buf1[6],
fp_cpx_data_ca_buf1[8],
fp_cpx_data_ca_buf1[10],
fp_cpx_data_ca_buf1[12],
fp_cpx_data_ca_buf1[14],
fp_cpx_data_ca_buf1[16],
fp_cpx_data_ca_buf1[18],
fp_cpx_data_ca_buf1[20],
fp_cpx_data_ca_buf1[22],
fp_cpx_data_ca_buf1[24],
fp_cpx_data_ca_buf1[26],
fp_cpx_data_ca_buf1[28],
fp_cpx_data_ca_buf1[30],
fp_cpx_data_ca_buf1[32]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_3 (
.in ({
fp_cpx_data_ca[31],
fp_cpx_data_ca[27],
fp_cpx_data_ca[23],
fp_cpx_data_ca[25],
fp_cpx_data_ca[21],
fp_cpx_data_ca[17],
fp_cpx_data_ca[19],
fp_cpx_data_ca[15],
fp_cpx_data_ca[11],
fp_cpx_data_ca[13],
fp_cpx_data_ca[9],
fp_cpx_data_ca[5],
fp_cpx_data_ca[7],
fp_cpx_data_ca[3],
fp_cpx_data_ca[0],
fp_cpx_data_ca[1]}),
.out ({
fp_cpx_data_ca_buf1[31],
fp_cpx_data_ca_buf1[27],
fp_cpx_data_ca_buf1[23],
fp_cpx_data_ca_buf1[25],
fp_cpx_data_ca_buf1[21],
fp_cpx_data_ca_buf1[17],
fp_cpx_data_ca_buf1[19],
fp_cpx_data_ca_buf1[15],
fp_cpx_data_ca_buf1[11],
fp_cpx_data_ca_buf1[13],
fp_cpx_data_ca_buf1[9],
fp_cpx_data_ca_buf1[5],
fp_cpx_data_ca_buf1[7],
fp_cpx_data_ca_buf1[3],
fp_cpx_data_ca_buf1[0],
fp_cpx_data_ca_buf1[1]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_4 (
.in ({
fp_cpx_data_ca[59],
fp_cpx_data_ca[61],
fp_cpx_data_ca[57],
fp_cpx_data_ca[53],
fp_cpx_data_ca[55],
fp_cpx_data_ca[51],
fp_cpx_data_ca[47],
fp_cpx_data_ca[49],
fp_cpx_data_ca[45],
fp_cpx_data_ca[41],
fp_cpx_data_ca[43],
fp_cpx_data_ca[39],
fp_cpx_data_ca[35],
fp_cpx_data_ca[37],
fp_cpx_data_ca[33],
fp_cpx_data_ca[29]}),
.out ({
fp_cpx_data_ca_buf1[59],
fp_cpx_data_ca_buf1[61],
fp_cpx_data_ca_buf1[57],
fp_cpx_data_ca_buf1[53],
fp_cpx_data_ca_buf1[55],
fp_cpx_data_ca_buf1[51],
fp_cpx_data_ca_buf1[47],
fp_cpx_data_ca_buf1[49],
fp_cpx_data_ca_buf1[45],
fp_cpx_data_ca_buf1[41],
fp_cpx_data_ca_buf1[43],
fp_cpx_data_ca_buf1[39],
fp_cpx_data_ca_buf1[35],
fp_cpx_data_ca_buf1[37],
fp_cpx_data_ca_buf1[33],
fp_cpx_data_ca_buf1[29]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_5 (
.in ({
fp_cpx_data_ca[113],
fp_cpx_data_ca[117],
fp_cpx_data_ca[121],
fp_cpx_data_ca[119],
fp_cpx_data_ca[123],
fp_cpx_data_ca[127],
fp_cpx_data_ca[125],
fp_cpx_data_ca[129],
fp_cpx_data_ca[133],
fp_cpx_data_ca[131],
fp_cpx_data_ca[135],
fp_cpx_data_ca[139],
fp_cpx_data_ca[137],
fp_cpx_data_ca[141],
fp_cpx_data_ca[143],
fp_cpx_data_ca[63]}),
.out ({
fp_cpx_data_ca_buf1[113],
fp_cpx_data_ca_buf1[117],
fp_cpx_data_ca_buf1[121],
fp_cpx_data_ca_buf1[119],
fp_cpx_data_ca_buf1[123],
fp_cpx_data_ca_buf1[127],
fp_cpx_data_ca_buf1[125],
fp_cpx_data_ca_buf1[129],
fp_cpx_data_ca_buf1[133],
fp_cpx_data_ca_buf1[131],
fp_cpx_data_ca_buf1[135],
fp_cpx_data_ca_buf1[139],
fp_cpx_data_ca_buf1[137],
fp_cpx_data_ca_buf1[141],
fp_cpx_data_ca_buf1[143],
fp_cpx_data_ca_buf1[63]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_6 (
.in ({
fp_cpx_data_ca[85],
fp_cpx_data_ca[83],
fp_cpx_data_ca[87],
fp_cpx_data_ca[91],
fp_cpx_data_ca[89],
fp_cpx_data_ca[93],
fp_cpx_data_ca[97],
fp_cpx_data_ca[95],
fp_cpx_data_ca[99],
fp_cpx_data_ca[103],
fp_cpx_data_ca[101],
fp_cpx_data_ca[105],
fp_cpx_data_ca[109],
fp_cpx_data_ca[107],
fp_cpx_data_ca[111],
fp_cpx_data_ca[115]}),
.out ({
fp_cpx_data_ca_buf1[85],
fp_cpx_data_ca_buf1[83],
fp_cpx_data_ca_buf1[87],
fp_cpx_data_ca_buf1[91],
fp_cpx_data_ca_buf1[89],
fp_cpx_data_ca_buf1[93],
fp_cpx_data_ca_buf1[97],
fp_cpx_data_ca_buf1[95],
fp_cpx_data_ca_buf1[99],
fp_cpx_data_ca_buf1[103],
fp_cpx_data_ca_buf1[101],
fp_cpx_data_ca_buf1[105],
fp_cpx_data_ca_buf1[109],
fp_cpx_data_ca_buf1[107],
fp_cpx_data_ca_buf1[111],
fp_cpx_data_ca_buf1[115]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_7 (
.in ({
fp_cpx_data_ca[114],
fp_cpx_data_ca[116],
fp_cpx_data_ca[118],
fp_cpx_data_ca[120],
fp_cpx_data_ca[122],
fp_cpx_data_ca[124],
fp_cpx_data_ca[126],
fp_cpx_data_ca[65],
fp_cpx_data_ca[67],
fp_cpx_data_ca[69],
fp_cpx_data_ca[73],
fp_cpx_data_ca[71],
fp_cpx_data_ca[75],
fp_cpx_data_ca[79],
fp_cpx_data_ca[77],
fp_cpx_data_ca[81]}),
.out ({
fp_cpx_data_ca_buf1[114],
fp_cpx_data_ca_buf1[116],
fp_cpx_data_ca_buf1[118],
fp_cpx_data_ca_buf1[120],
fp_cpx_data_ca_buf1[122],
fp_cpx_data_ca_buf1[124],
fp_cpx_data_ca_buf1[126],
fp_cpx_data_ca_buf1[65],
fp_cpx_data_ca_buf1[67],
fp_cpx_data_ca_buf1[69],
fp_cpx_data_ca_buf1[73],
fp_cpx_data_ca_buf1[71],
fp_cpx_data_ca_buf1[75],
fp_cpx_data_ca_buf1[79],
fp_cpx_data_ca_buf1[77],
fp_cpx_data_ca_buf1[81]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_8 (
.in ({
fp_cpx_data_ca[82],
fp_cpx_data_ca[84],
fp_cpx_data_ca[86],
fp_cpx_data_ca[88],
fp_cpx_data_ca[90],
fp_cpx_data_ca[92],
fp_cpx_data_ca[94],
fp_cpx_data_ca[96],
fp_cpx_data_ca[98],
fp_cpx_data_ca[100],
fp_cpx_data_ca[102],
fp_cpx_data_ca[104],
fp_cpx_data_ca[106],
fp_cpx_data_ca[108],
fp_cpx_data_ca[110],
fp_cpx_data_ca[112]}),
.out ({
fp_cpx_data_ca_buf1[82],
fp_cpx_data_ca_buf1[84],
fp_cpx_data_ca_buf1[86],
fp_cpx_data_ca_buf1[88],
fp_cpx_data_ca_buf1[90],
fp_cpx_data_ca_buf1[92],
fp_cpx_data_ca_buf1[94],
fp_cpx_data_ca_buf1[96],
fp_cpx_data_ca_buf1[98],
fp_cpx_data_ca_buf1[100],
fp_cpx_data_ca_buf1[102],
fp_cpx_data_ca_buf1[104],
fp_cpx_data_ca_buf1[106],
fp_cpx_data_ca_buf1[108],
fp_cpx_data_ca_buf1[110],
fp_cpx_data_ca_buf1[112]})
);
fpu_rptr_fp_cpx_grp16 i_fp_cpx_buf1_9 (
.in ({
6'b000000,
so_buf1,
fp_cpx_data_ca[64],
fp_cpx_data_ca[66],
fp_cpx_data_ca[68],
fp_cpx_data_ca[70],
fp_cpx_data_ca[72],
fp_cpx_data_ca[74],
fp_cpx_data_ca[76],
fp_cpx_data_ca[78],
fp_cpx_data_ca[80]}),
.out ({
fp_cpx_buf1_9_unused[5:0],
so,
fp_cpx_data_ca_buf1[64],
fp_cpx_data_ca_buf1[66],
fp_cpx_data_ca_buf1[68],
fp_cpx_data_ca_buf1[70],
fp_cpx_data_ca_buf1[72],
fp_cpx_data_ca_buf1[74],
fp_cpx_data_ca_buf1[76],
fp_cpx_data_ca_buf1[78],
fp_cpx_data_ca_buf1[80]})
);
// buffer fpu_in_dp outputs (sram din inputs) for mintiming
fpu_rptr_inq i_inq_sram_din_buf1 (
.in (inq_sram_din_unbuf[155:0]),
.out (inq_sram_din_buf1[155:0])
);
endmodule
|
module top(input CLOCK_50, input [1:0] KEY, output [7:0] LED,
output Tx, input Rx, output [3:0] Snd, input [3:0] SW,
//DRAM signals
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CAS_N,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output [1:0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N
);
wire [31:0] data1; // From arbiter of bus_arbiter.v
wire [31:0] data_out2; // From arbiter of bus_arbiter.v
wire data_valid1; // From arbiter of bus_arbiter.v
wire data_valid2; // From arbiter of bus_arbiter.v
wire write_complete2; // From arbiter of bus_arbiter.v
wire v_sync; // From gen of ntsc_gen.v
wire clk;
wire snd;
wire ntsc_clk;
wire [3:0] snd_signals;
reg [2:0] rst_n = 3'b000;
reg [23:0] counter = 0;
//DRAM wires
wire [23:0] dram_addr;
wire dram_req_read, dram_req_write, dram_data_valid;
wire [31:0] dram_data_out, dram_data_in;
wire [31:0] data_in2;
wire [23:0] addr2, addr1;
wire req_read2, req_write2, req_read1, dram_write_complete;
//assign Snd = {3'b0,snd};
//assign Snd = snd_signals;
assign clk = CLOCK_50;
ntsc_gen #(.DATA_BITS(4)) gen(
// Outputs
.v_data (Snd),
.v_sync (v_sync),
// Inputs
.clk (ntsc_clk));
pll1 pll(
.inclk0(CLOCK_50),
.c0(ntsc_clk));
core core(
// Outputs
.LED (LED[7:0]),
.tx (Tx),
.snd_out (snd),
.snd_signals (snd_signals),
// Inputs
.clk (clk),
.rst_n (rst_n[2]),
.rx (Rx),
.switches (SW[3:0]),
.dram_data_out (data_in2),
.dram_addr (addr2),
.dram_req_read (req_read2),
.dram_req_write (req_write2),
.dram_data_in (data_out2),
.dram_data_valid (data_valid2),
.dram_write_complete (write_complete2)
);
wire CLOCK_100, CLOCK_100_del_3ns;
sdram_clk_gen clk_gen(
.inclk0(CLOCK_50),
.c0(CLOCK_100_del_3ns),
.c1(CLOCK_100));
sdram_controller3 controller(
.data_out (dram_data_out[31:0]),
.data_valid (dram_data_valid),
// Outputs
.write_complete (dram_write_complete),
.DRAM_ADDR (DRAM_ADDR[12:0]),
.DRAM_BA (DRAM_BA[1:0]),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQM (DRAM_DQM[1:0]),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N),
// Inouts
.DRAM_DQ (DRAM_DQ[15:0]),
// Inputs
.CLOCK_50 (CLOCK_50),
.CLOCK_100 (CLOCK_100),
.CLOCK_100_del_3ns(CLOCK_100_del_3ns),
.rst (rst),
.address (dram_addr[23:0]),
.req_read (dram_req_read),
.req_write (dram_req_write),
.data_in (dram_data_in[31:0])
/*AUTOINST*/);
bus_arbiter arbiter(
// Outputs
.data1 (data1[31:0]),
.data_valid1 (data_valid1),
.data_out2 (data_out2[31:0]),
.data_valid2 (data_valid2),
.write_complete2 (write_complete2),
.dram_addr (dram_addr[23:0]),
.dram_data_in (dram_data_in[31:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.addr1 (addr1[23:0]),
.req_read1 (req_read1),
.addr2 (addr2[23:0]),
.data_in2 (data_in2[31:0]),
.req_read2 (req_read2),
.req_write2 (req_write2),
.dram_data_out (dram_data_out[31:0]),
.dram_data_out_valid(dram_data_valid),
.dram_write_complete(dram_write_complete));
//assign LED[7] = Tx;
always @(posedge CLOCK_50)begin
rst_n <= {rst_n[1:0],KEY[0]};
counter <= counter + 1;
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sounder_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,mask_i,tx_i_o,tx_q_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [13:0] ampl_i;
input [15:0] mask_i;
output [13:0] tx_i_o;
output [13:0] tx_q_o;
wire pn;
wire [13:0] min_value = (~ampl_i)+14'b1;
lfsr pn_code
( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),.mask_i(mask_i),.pn_o(pn) );
assign tx_i_o = ena_i ? (pn ? ampl_i : min_value) : 14'b0; // Bipolar
assign tx_q_o = 14'b0;
endmodule // sounder_tx
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_addr_cmd_pads(
/*
config_data_in,
config_clock_in,
config_io_ena,
config_update,
*/
reset_n,
reset_n_afi_clk,
pll_hr_clk,
pll_avl_phy_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
/*
input config_data_in;
input config_clock_in;
input config_io_ena;
input config_update;
*/
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_hr_clk;
input pll_avl_phy_clk;
input pll_mem_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
/* ********* *
* A/C Logic *
* ********* */
localparam CMD_WIDTH =
MEM_CHIP_SELECT_WIDTH +
MEM_CLK_EN_WIDTH +
MEM_ODT_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH;
localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
wire [AC_CLK_WIDTH-1:0] ac_clk;
generate
genvar i;
for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
begin: address_gen
wire addr_cmd_clk;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ac_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(ac_clk[i])
);
end
endgenerate
hps_sdram_p0_generic_ddio uaddress_pad(
.datain(phy_ddio_address),
.halfratebypass(1'b1),
.dataout(phy_mem_address),
.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
);
defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
hps_sdram_p0_generic_ddio ubank_pad(
.datain(phy_ddio_bank),
.halfratebypass(1'b1),
.dataout(phy_mem_bank),
.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
);
defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
hps_sdram_p0_generic_ddio ucmd_pad(
.datain({
phy_ddio_we_n,
phy_ddio_cas_n,
phy_ddio_ras_n,
phy_ddio_odt,
phy_ddio_cke,
phy_ddio_cs_n
}),
.halfratebypass(1'b1),
.dataout({
phy_mem_we_n,
phy_mem_cas_n,
phy_mem_ras_n,
phy_mem_odt,
phy_mem_cke,
phy_mem_cs_n
}),
.clk_hr({CMD_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
);
defparam ucmd_pad.WIDTH = CMD_WIDTH;
hps_sdram_p0_generic_ddio ureset_n_pad(
.datain(phy_ddio_reset_n),
.halfratebypass(1'b1),
.dataout(phy_mem_reset_n),
.clk_hr(pll_hr_clk),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
);
defparam ureset_n_pad.WIDTH = 1;
/* ************ *
* Config Logic *
* ************ */
wire [4:0] outputdelaysetting;
wire [4:0] outputenabledelaysetting;
wire outputhalfratebypass;
wire [4:0] inputdelaysetting;
wire [1:0] rfifo_clock_select;
wire [2:0] rfifo_mode;
/*
cyclonev_io_config ioconfig (
.datain(config_data_in),
.clk(config_clock_in),
.ena(config_io_ena),
.update(config_update),
.outputregdelaysetting(outputdelaysetting),
.outputenabledelaysetting(outputenabledelaysetting),
.outputhalfratebypass(outputhalfratebypass),
.readfiforeadclockselect(rfifo_clock_select),
.readfifomode(rfifo_mode),
.padtoinputregisterdelaysetting(inputdelaysetting),
.dataout()
);
*/
/* *************** *
* Mem Clock Logic *
* *************** */
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
if (IS_HHP_HPS == "true") begin
assign phy_clk_out = phy_clk_in;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
end
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin (leveled_dqs_clocks[0]),
`else
.clkin (leveled_dqs_clocks),
`endif
.clkout (mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
wire mem_ck_hi;
wire mem_ck_lo;
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
assign mem_ck_hi = 1'b0;
assign mem_ck_lo = 1'b1;
end
else
begin
assign mem_ck_hi = phy_ddio_ck[0];
assign mem_ck_lo = phy_ddio_ck[1];
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (mem_ck_hi),
.datain_l (mem_ck_lo),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
hps_sdram_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_0_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration meta controller.
//
// Compute center of the window set up with with the ktap_left,
// ktap_right dance (hereafter "the window"). Also compute center of the
// edge (hereafter "the edge") to be aligned in the center
// of this window.
//
// Following the ktap_left/right dance, the to be centered edge is
// always left at the right edge of the window
// if SCANFROMRIGHT == 1, and the left edge otherwise.
//
// An assumption is the rise(0) case has a window wider than the noise on the
// edge. The noise case with the possibly narrow window
// will always be shifted by 90. And the fall(180) case is shifted by
// 90 twice. Hence when we start, we can assume the center of the
// edge is to the right/left of the the window center.
//
// The actual hardware does not necessarily monotonically appear to
// move the window centers. Because of noise, it is possible for the
// centered edge to move opposite the expected direction with a tap increment.
//
// This problem is solved by computing the absolute difference between
// the centers and the circular distance between the centers. These will
// be the same until the difference transits through zero. Then the circular
// difference will jump to almost the value of TAPSPERKCLK.
//
// The window center computation is done at 1/2 tap increments to maintain
// resolution through the divide by 2 for centering.
//
// There is a corner case of when the shift is greater than 180 degress. In
// this case the absolute difference and the circular difference will be
// unequal at the beginning of the alignment. This is solved by latching
// if they are equal at the end of each cycle. The completion must see
// that they were equal in the previous cycle, but are not equal in this cycle.
//
// Since the phaser out steps are of unknown size, it is possible to overshoot
// the center. The previous difference is recorded and if its less than the current
// difference, poc_backup is driven high.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_0_poc_meta #
(parameter SCANFROMRIGHT = 0,
parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
run_ends, mmcm_edge_detect_done, edge_center, left, right,
window_center, diff, poc_backup, mmcm_lbclk_edge_aligned,
// Inputs
rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end,
run_polarity, rise_lead_right, rise_trail_left, rise_lead_center,
rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,
use_noise_window, ktap_at_right_edge, ktap_at_left_edge
);
localparam NINETY = TAPSPERKCLK/4;
function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a,
input [1:0] b,
input integer base);
integer offset_ii;
begin
offset_ii = (a + b * NINETY) < base
? (a + b * NINETY)
: (a + b * NINETY - base);
offset = offset_ii[TAPCNTRWIDTH-1:0];
end
endfunction // offset
function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base-b;
end
endfunction // mod_sub
function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left,
input [TAPCNTRWIDTH-1:0] diff,
input integer base);
integer center_ii;
begin
center_ii = ({left, 1'b0} + diff < base * 2)
? {left, 1'b0} + diff + 32'h0
: {left, 1'b0} + diff - base * 2;
center = center_ii[TAPCNTRWIDTH:0];
end
endfunction // center
input rst;
input clk;
input mmcm_edge_detect_rdy;
reg [1:0] run_ends_r;
input run_too_small;
reg run_too_small_r1, run_too_small_r2, run_too_small_r3;
always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1;
always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1;
always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2;
wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ;
// This input used only for the SVA.
input [TAPCNTRWIDTH-1:0] run;
input run_end;
reg run_end_r, run_end_r1, run_end_r2, run_end_r3;
always @(posedge clk) run_end_r <= #TCQ run_end;
always @(posedge clk) run_end_r1 <= #TCQ run_end_r;
always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;
always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;
input run_polarity;
reg run_polarity_held_ns, run_polarity_held_r;
always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;
always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;
reg [1:0] run_ends_ns;
always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;
always @(*) begin
run_ends_ns = run_ends_r;
if (reset_run_ends) run_ends_ns = 2'b0;
else case (run_ends_r)
2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};
2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};
endcase // case (run_ends_r)
end // always @ begin
output [1:0] run_ends;
assign run_ends = run_ends_r;
reg done_r;
wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;
always @(posedge clk) done_r <= #TCQ done_ns;
output mmcm_edge_detect_done;
assign mmcm_edge_detect_done = done_r;
input [TAPCNTRWIDTH-1:0] rise_lead_right;
input [TAPCNTRWIDTH-1:0] rise_trail_left;
input [TAPCNTRWIDTH-1:0] rise_lead_center;
input [TAPCNTRWIDTH-1:0] rise_trail_center;
input [TAPCNTRWIDTH-1:0] rise_trail_right;
input [TAPCNTRWIDTH-1:0] rise_lead_left;
input [1:0] ninety_offsets;
wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;
wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);
wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;
always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;
always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;
wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] edge_diff_r;
always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;
wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] edge_center_r;
always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;
output [TAPCNTRWIDTH:0] edge_center;
assign edge_center = edge_center_r;
input use_noise_window;
output [TAPCNTRWIDTH-1:0] left, right;
assign left = use_noise_window ? rise_lead_left : rise_trail_left;
assign right = use_noise_window ? rise_trail_right : rise_lead_right;
wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] center_diff_r;
always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;
wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] window_center_r;
always @(posedge clk) window_center_r <= #TCQ window_center_ns;
output [TAPCNTRWIDTH:0] window_center;
assign window_center = window_center_r;
localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;
wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};
wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};
wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center
? right_center - left_center
: right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;
reg [TAPCNTRWIDTH+1:0] diff_r;
always @(posedge clk) diff_r <= #TCQ diff_ns;
output [TAPCNTRWIDTH+1:0] diff;
assign diff = diff_r;
wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2
? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r
: diff_r;
reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;
always @(posedge clk) prev_r <= #TCQ prev_ns;
always @(*) prev_ns = done_ns ? diff_r : prev_r;
input ktap_at_right_edge;
input ktap_at_left_edge;
wire centering = !(ktap_at_right_edge || ktap_at_left_edge);
wire diffs_eq = abs_diff == diff_r;
reg diffs_eq_ns, diffs_eq_r;
always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);
always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;
reg edge_aligned_r;
reg prev_valid_ns, prev_valid_r;
always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;
always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;
wire indicate_alignment = ~rst && centering && done_ns;
wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);
always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;
reg poc_backup_r;
wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
output poc_backup;
assign poc_backup = poc_backup_r;
output mmcm_lbclk_edge_aligned;
assign mmcm_lbclk_edge_aligned = edge_aligned_r;
endmodule // mig_7series_v4_0_poc_meta
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
`include "defines.v"
module connectRouter_nobuffer
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_in,
input `control_w inj,
input bfull,
input clk,
input rst,
output `control_w port_out,
output accept,
output `control_w eject,
output push
);
wire `control_w port_0;
assign port_0 = (rst) ? `control_n'd0 : port_in;
wire bfull;
wire productive;
wire push;
wire pop;
wire `control_w bout;
wire [2:0] bsize;
/************* STAGE 1 *************/
reg `control_w port_r_0, port_r_1;
wire `control_w port_1, port_2;
always @(posedge clk) begin
port_r_0 <= port_0;
end
assign productive = (port_r_0[`dest_f] < 4 || port_r_0[`dest_f] > 11)? 0 : 1;
assign push = productive && ~bfull;
assign eject = port_r_0;
assign port_1 = push ? 0 : port_r_0;
assign accept = (~port_1[`valid_f] & inj[`valid_f]);
assign port_2 = accept ? inj : port_1;
/*********** STAGE 2 ***************/
always @ (posedge clk) begin
port_r_1 <= port_2;
end
assign port_out = port_r_1;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
c_worked <= $c("my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
vluint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Unary minus operator test
module vhdl_unary_minus_test;
logic signed [7:0] data_in;
logic signed [7:0] data_out;
logic clk = 1'b0;
vhdl_unary_minus dut(data_in, clk, data_out);
always #10 clk = ~clk;
initial begin
#5;
data_in = -12;
#20;
if(data_out !== 12) begin
$display("FAILED 1");
$finish();
end
data_in = 33;
#20;
if(data_out !== -33) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
$finish();
end
endmodule
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: This is a generic n-deep SRL instantiation
// Verilog-standard: Verilog 2001
// $Revision:
// $Date:
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "none", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam P_SRLASIZE = 5;
localparam P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
endgenerate
// Instantiate MUX
generate
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
endgenerate
endmodule
`default_nettype wire
|
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
// AVR Serial Signals
output tx,
input rx,
// ADC Interface Signals
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(8'hff),
.dout(spi_dout)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
// Output declarations
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
if (spi_ss) begin // device is not selected
byte_ct_d = 1'b0;
end
if (spi_done) begin // sent/received data from SPI
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample
sample_channel_d = spi_dout[7:4]; // and the channel that was sampled
byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
sample_channel_q <= sample_channel_d;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:29:52 2016
/////////////////////////////////////////////////////////////
module Priority_Codec_32 ( Data_Dec_i, Data_Bin_o );
input [25:0] Data_Dec_i;
output [4:0] Data_Bin_o;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50;
NOR3BX1TS U3 ( .AN(n25), .B(Data_Dec_i[18]), .C(n6), .Y(n31) );
NOR3BX1TS U4 ( .AN(n39), .B(Data_Dec_i[10]), .C(Data_Dec_i[11]), .Y(
Data_Bin_o[4]) );
INVX2TS U5 ( .A(n31), .Y(n5) );
AOI31X1TS U6 ( .A0(n7), .A1(n1), .A2(n40), .B0(n41), .Y(n34) );
INVX2TS U7 ( .A(Data_Bin_o[4]), .Y(n4) );
INVX2TS U8 ( .A(n42), .Y(n6) );
INVX2TS U9 ( .A(n16), .Y(n3) );
NOR2X1TS U10 ( .A(n22), .B(n23), .Y(n21) );
NOR4BX1TS U11 ( .AN(n13), .B(n5), .C(Data_Dec_i[13]), .D(Data_Dec_i[14]),
.Y(n50) );
NOR3X1TS U12 ( .A(Data_Dec_i[24]), .B(Data_Dec_i[25]), .C(n40), .Y(n42) );
NOR4BX1TS U13 ( .AN(n24), .B(n4), .C(Data_Dec_i[5]), .D(Data_Dec_i[6]), .Y(
n49) );
NOR2BX1TS U14 ( .AN(n50), .B(Data_Dec_i[12]), .Y(n39) );
NAND2BX1TS U15 ( .AN(Data_Dec_i[3]), .B(n38), .Y(n16) );
NAND4X1TS U16 ( .A(n32), .B(n33), .C(n34), .D(n35), .Y(Data_Bin_o[1]) );
NAND4BX1TS U17 ( .AN(Data_Dec_i[21]), .B(Data_Dec_i[19]), .C(n42), .D(n9),
.Y(n32) );
NAND4BX1TS U18 ( .AN(Data_Dec_i[17]), .B(Data_Dec_i[15]), .C(n31), .D(n10),
.Y(n33) );
NOR2BX1TS U19 ( .AN(n49), .B(Data_Dec_i[4]), .Y(n38) );
NAND2BX1TS U20 ( .AN(Data_Dec_i[23]), .B(n8), .Y(n40) );
NAND2X1TS U21 ( .A(Data_Dec_i[2]), .B(n3), .Y(n20) );
NAND4X1TS U22 ( .A(n26), .B(n28), .C(n48), .D(n17), .Y(n41) );
AOI31X1TS U23 ( .A0(Data_Bin_o[4]), .A1(n24), .A2(Data_Dec_i[6]), .B0(n2),
.Y(n48) );
INVX2TS U24 ( .A(n20), .Y(n2) );
INVX2TS U25 ( .A(Data_Dec_i[22]), .Y(n8) );
NOR4BX1TS U26 ( .AN(n29), .B(n36), .C(n23), .D(n37), .Y(n35) );
NOR4BX1TS U27 ( .AN(Data_Dec_i[7]), .B(Data_Dec_i[9]), .C(Data_Dec_i[8]),
.D(n4), .Y(n37) );
NOR3X1TS U28 ( .A(n16), .B(Data_Dec_i[1]), .C(Data_Dec_i[0]), .Y(n36) );
NOR3X1TS U29 ( .A(Data_Dec_i[16]), .B(Data_Dec_i[17]), .C(Data_Dec_i[15]),
.Y(n13) );
NOR3X1TS U30 ( .A(Data_Dec_i[20]), .B(Data_Dec_i[21]), .C(Data_Dec_i[19]),
.Y(n25) );
NAND3BX1TS U31 ( .AN(n43), .B(n44), .C(n45), .Y(Data_Bin_o[0]) );
OAI31X1TS U32 ( .A0(n4), .A1(Data_Dec_i[9]), .A2(n11), .B0(n30), .Y(n43) );
AOI31X1TS U33 ( .A0(n3), .A1(n12), .A2(Data_Dec_i[0]), .B0(n22), .Y(n44) );
NAND4BX1TS U34 ( .AN(n18), .B(n19), .C(n20), .D(n21), .Y(Data_Bin_o[2]) );
NAND4BX1TS U35 ( .AN(Data_Dec_i[6]), .B(Data_Dec_i[5]), .C(Data_Bin_o[4]),
.D(n24), .Y(n19) );
OAI211X1TS U36 ( .A0(n6), .A1(n25), .B0(n14), .C0(n26), .Y(n18) );
OAI211X1TS U37 ( .A0(n13), .A1(n5), .B0(n14), .C0(n15), .Y(Data_Bin_o[3]) );
OA21XLTS U38 ( .A0(n16), .A1(Data_Dec_i[2]), .B0(n17), .Y(n15) );
AND2X2TS U39 ( .A(Data_Dec_i[3]), .B(n38), .Y(n23) );
AND2X2TS U40 ( .A(Data_Dec_i[4]), .B(n49), .Y(n22) );
AOI211X1TS U41 ( .A0(n46), .A1(n1), .B0(n47), .C0(n41), .Y(n45) );
OAI21X1TS U42 ( .A0(Data_Dec_i[23]), .A1(n8), .B0(n7), .Y(n46) );
OAI33XLTS U43 ( .A0(n9), .A1(Data_Dec_i[21]), .A2(n6), .B0(n10), .B1(
Data_Dec_i[17]), .B2(n5), .Y(n47) );
NAND3BX1TS U44 ( .AN(Data_Dec_i[11]), .B(n39), .C(Data_Dec_i[10]), .Y(n28)
);
NAND2X1TS U45 ( .A(Data_Dec_i[12]), .B(n50), .Y(n30) );
NAND2X1TS U46 ( .A(Data_Dec_i[11]), .B(n39), .Y(n29) );
AND4X1TS U47 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n14) );
NAND4BX1TS U48 ( .AN(Data_Dec_i[14]), .B(Data_Dec_i[13]), .C(n31), .D(n13),
.Y(n27) );
NAND3X1TS U49 ( .A(n31), .B(n13), .C(Data_Dec_i[14]), .Y(n17) );
NOR3X1TS U50 ( .A(Data_Dec_i[8]), .B(Data_Dec_i[9]), .C(Data_Dec_i[7]), .Y(
n24) );
NAND3X1TS U51 ( .A(n42), .B(n25), .C(Data_Dec_i[18]), .Y(n26) );
INVX2TS U52 ( .A(Data_Dec_i[20]), .Y(n9) );
INVX2TS U53 ( .A(Data_Dec_i[16]), .Y(n10) );
INVX2TS U54 ( .A(Data_Dec_i[24]), .Y(n7) );
INVX2TS U55 ( .A(Data_Dec_i[25]), .Y(n1) );
INVX2TS U56 ( .A(Data_Dec_i[8]), .Y(n11) );
INVX2TS U57 ( .A(Data_Dec_i[1]), .Y(n12) );
endmodule
module RegisterAdd_W5 ( clk, rst, load, D, Q );
input [4:0] D;
output [4:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11;
OAI2BB2XLTS U2 ( .B0(n1), .B1(load), .A0N(load), .A1N(D[0]), .Y(n6) );
OAI2BB2XLTS U3 ( .B0(n2), .B1(load), .A0N(D[1]), .A1N(load), .Y(n7) );
OAI2BB2XLTS U4 ( .B0(n3), .B1(load), .A0N(D[2]), .A1N(load), .Y(n8) );
OAI2BB2XLTS U5 ( .B0(n4), .B1(load), .A0N(D[3]), .A1N(load), .Y(n9) );
CLKINVX1TS U6 ( .A(rst), .Y(n10) );
OAI2BB2XLTS U7 ( .B0(n5), .B1(load), .A0N(D[4]), .A1N(load), .Y(n11) );
DFFRX2TS \Q_reg[4] ( .D(n11), .CK(clk), .RN(n10), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n9), .CK(clk), .RN(n10), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n8), .CK(clk), .RN(n10), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n7), .CK(clk), .RN(n10), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n6), .CK(clk), .RN(n10), .Q(Q[0]), .QN(n1) );
endmodule
module LZD ( clk, rst, load_i, Add_subt_result_i, Shift_Value_o );
input [25:0] Add_subt_result_i;
output [4:0] Shift_Value_o;
input clk, rst, load_i;
wire [4:0] Codec_to_Reg;
Priority_Codec_32 \LZD_SINGLEBLK.Codec_32 ( .Data_Dec_i(Add_subt_result_i),
.Data_Bin_o(Codec_to_Reg) );
RegisterAdd_W5 Output_Reg ( .clk(clk), .rst(rst), .load(load_i), .D(
Codec_to_Reg), .Q(Shift_Value_o) );
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bram_1024_0 (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [9 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [19 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [19 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bram_1024_0.mif"),
.C_INIT_FILE("bram_1024_0.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(20),
.C_READ_WIDTH_A(20),
.C_WRITE_DEPTH_A(1024),
.C_READ_DEPTH_A(1024),
.C_ADDRA_WIDTH(10),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(20),
.C_READ_WIDTH_B(20),
.C_WRITE_DEPTH_B(1024),
.C_READ_DEPTH_B(1024),
.C_ADDRB_WIDTH(10),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.74095 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(10'B0),
.dinb(20'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(20'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 512 words x 128 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module xs6_sram_1024x128_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
parameter SRAM4_INIT_0 = 256'h0,
parameter SRAM4_INIT_1 = 256'h0,
parameter SRAM4_INIT_2 = 256'h0,
parameter SRAM4_INIT_3 = 256'h0,
parameter SRAM4_INIT_4 = 256'h0,
parameter SRAM4_INIT_5 = 256'h0,
parameter SRAM4_INIT_6 = 256'h0,
parameter SRAM4_INIT_7 = 256'h0,
parameter SRAM4_INIT_8 = 256'h0,
parameter SRAM4_INIT_9 = 256'h0,
parameter SRAM4_INIT_10 = 256'h0,
parameter SRAM4_INIT_11 = 256'h0,
parameter SRAM4_INIT_12 = 256'h0,
parameter SRAM4_INIT_13 = 256'h0,
parameter SRAM4_INIT_14 = 256'h0,
parameter SRAM4_INIT_15 = 256'h0,
parameter SRAM4_INIT_16 = 256'h0,
parameter SRAM4_INIT_17 = 256'h0,
parameter SRAM4_INIT_18 = 256'h0,
parameter SRAM4_INIT_19 = 256'h0,
parameter SRAM4_INIT_20 = 256'h0,
parameter SRAM4_INIT_21 = 256'h0,
parameter SRAM4_INIT_22 = 256'h0,
parameter SRAM4_INIT_23 = 256'h0,
parameter SRAM4_INIT_24 = 256'h0,
parameter SRAM4_INIT_25 = 256'h0,
parameter SRAM4_INIT_26 = 256'h0,
parameter SRAM4_INIT_27 = 256'h0,
parameter SRAM4_INIT_28 = 256'h0,
parameter SRAM4_INIT_29 = 256'h0,
parameter SRAM4_INIT_30 = 256'h0,
parameter SRAM4_INIT_31 = 256'h0,
parameter SRAM4_INIT_32 = 256'h0,
parameter SRAM4_INIT_33 = 256'h0,
parameter SRAM4_INIT_34 = 256'h0,
parameter SRAM4_INIT_35 = 256'h0,
parameter SRAM4_INIT_36 = 256'h0,
parameter SRAM4_INIT_37 = 256'h0,
parameter SRAM4_INIT_38 = 256'h0,
parameter SRAM4_INIT_39 = 256'h0,
parameter SRAM4_INIT_40 = 256'h0,
parameter SRAM4_INIT_41 = 256'h0,
parameter SRAM4_INIT_42 = 256'h0,
parameter SRAM4_INIT_43 = 256'h0,
parameter SRAM4_INIT_44 = 256'h0,
parameter SRAM4_INIT_45 = 256'h0,
parameter SRAM4_INIT_46 = 256'h0,
parameter SRAM4_INIT_47 = 256'h0,
parameter SRAM4_INIT_48 = 256'h0,
parameter SRAM4_INIT_49 = 256'h0,
parameter SRAM4_INIT_50 = 256'h0,
parameter SRAM4_INIT_51 = 256'h0,
parameter SRAM4_INIT_52 = 256'h0,
parameter SRAM4_INIT_53 = 256'h0,
parameter SRAM4_INIT_54 = 256'h0,
parameter SRAM4_INIT_55 = 256'h0,
parameter SRAM4_INIT_56 = 256'h0,
parameter SRAM4_INIT_57 = 256'h0,
parameter SRAM4_INIT_58 = 256'h0,
parameter SRAM4_INIT_59 = 256'h0,
parameter SRAM4_INIT_60 = 256'h0,
parameter SRAM4_INIT_61 = 256'h0,
parameter SRAM4_INIT_62 = 256'h0,
parameter SRAM4_INIT_63 = 256'h0,
parameter SRAM5_INIT_0 = 256'h0,
parameter SRAM5_INIT_1 = 256'h0,
parameter SRAM5_INIT_2 = 256'h0,
parameter SRAM5_INIT_3 = 256'h0,
parameter SRAM5_INIT_4 = 256'h0,
parameter SRAM5_INIT_5 = 256'h0,
parameter SRAM5_INIT_6 = 256'h0,
parameter SRAM5_INIT_7 = 256'h0,
parameter SRAM5_INIT_8 = 256'h0,
parameter SRAM5_INIT_9 = 256'h0,
parameter SRAM5_INIT_10 = 256'h0,
parameter SRAM5_INIT_11 = 256'h0,
parameter SRAM5_INIT_12 = 256'h0,
parameter SRAM5_INIT_13 = 256'h0,
parameter SRAM5_INIT_14 = 256'h0,
parameter SRAM5_INIT_15 = 256'h0,
parameter SRAM5_INIT_16 = 256'h0,
parameter SRAM5_INIT_17 = 256'h0,
parameter SRAM5_INIT_18 = 256'h0,
parameter SRAM5_INIT_19 = 256'h0,
parameter SRAM5_INIT_20 = 256'h0,
parameter SRAM5_INIT_21 = 256'h0,
parameter SRAM5_INIT_22 = 256'h0,
parameter SRAM5_INIT_23 = 256'h0,
parameter SRAM5_INIT_24 = 256'h0,
parameter SRAM5_INIT_25 = 256'h0,
parameter SRAM5_INIT_26 = 256'h0,
parameter SRAM5_INIT_27 = 256'h0,
parameter SRAM5_INIT_28 = 256'h0,
parameter SRAM5_INIT_29 = 256'h0,
parameter SRAM5_INIT_30 = 256'h0,
parameter SRAM5_INIT_31 = 256'h0,
parameter SRAM5_INIT_32 = 256'h0,
parameter SRAM5_INIT_33 = 256'h0,
parameter SRAM5_INIT_34 = 256'h0,
parameter SRAM5_INIT_35 = 256'h0,
parameter SRAM5_INIT_36 = 256'h0,
parameter SRAM5_INIT_37 = 256'h0,
parameter SRAM5_INIT_38 = 256'h0,
parameter SRAM5_INIT_39 = 256'h0,
parameter SRAM5_INIT_40 = 256'h0,
parameter SRAM5_INIT_41 = 256'h0,
parameter SRAM5_INIT_42 = 256'h0,
parameter SRAM5_INIT_43 = 256'h0,
parameter SRAM5_INIT_44 = 256'h0,
parameter SRAM5_INIT_45 = 256'h0,
parameter SRAM5_INIT_46 = 256'h0,
parameter SRAM5_INIT_47 = 256'h0,
parameter SRAM5_INIT_48 = 256'h0,
parameter SRAM5_INIT_49 = 256'h0,
parameter SRAM5_INIT_50 = 256'h0,
parameter SRAM5_INIT_51 = 256'h0,
parameter SRAM5_INIT_52 = 256'h0,
parameter SRAM5_INIT_53 = 256'h0,
parameter SRAM5_INIT_54 = 256'h0,
parameter SRAM5_INIT_55 = 256'h0,
parameter SRAM5_INIT_56 = 256'h0,
parameter SRAM5_INIT_57 = 256'h0,
parameter SRAM5_INIT_58 = 256'h0,
parameter SRAM5_INIT_59 = 256'h0,
parameter SRAM5_INIT_60 = 256'h0,
parameter SRAM5_INIT_61 = 256'h0,
parameter SRAM5_INIT_62 = 256'h0,
parameter SRAM5_INIT_63 = 256'h0,
parameter SRAM6_INIT_0 = 256'h0,
parameter SRAM6_INIT_1 = 256'h0,
parameter SRAM6_INIT_2 = 256'h0,
parameter SRAM6_INIT_3 = 256'h0,
parameter SRAM6_INIT_4 = 256'h0,
parameter SRAM6_INIT_5 = 256'h0,
parameter SRAM6_INIT_6 = 256'h0,
parameter SRAM6_INIT_7 = 256'h0,
parameter SRAM6_INIT_8 = 256'h0,
parameter SRAM6_INIT_9 = 256'h0,
parameter SRAM6_INIT_10 = 256'h0,
parameter SRAM6_INIT_11 = 256'h0,
parameter SRAM6_INIT_12 = 256'h0,
parameter SRAM6_INIT_13 = 256'h0,
parameter SRAM6_INIT_14 = 256'h0,
parameter SRAM6_INIT_15 = 256'h0,
parameter SRAM6_INIT_16 = 256'h0,
parameter SRAM6_INIT_17 = 256'h0,
parameter SRAM6_INIT_18 = 256'h0,
parameter SRAM6_INIT_19 = 256'h0,
parameter SRAM6_INIT_20 = 256'h0,
parameter SRAM6_INIT_21 = 256'h0,
parameter SRAM6_INIT_22 = 256'h0,
parameter SRAM6_INIT_23 = 256'h0,
parameter SRAM6_INIT_24 = 256'h0,
parameter SRAM6_INIT_25 = 256'h0,
parameter SRAM6_INIT_26 = 256'h0,
parameter SRAM6_INIT_27 = 256'h0,
parameter SRAM6_INIT_28 = 256'h0,
parameter SRAM6_INIT_29 = 256'h0,
parameter SRAM6_INIT_30 = 256'h0,
parameter SRAM6_INIT_31 = 256'h0,
parameter SRAM6_INIT_32 = 256'h0,
parameter SRAM6_INIT_33 = 256'h0,
parameter SRAM6_INIT_34 = 256'h0,
parameter SRAM6_INIT_35 = 256'h0,
parameter SRAM6_INIT_36 = 256'h0,
parameter SRAM6_INIT_37 = 256'h0,
parameter SRAM6_INIT_38 = 256'h0,
parameter SRAM6_INIT_39 = 256'h0,
parameter SRAM6_INIT_40 = 256'h0,
parameter SRAM6_INIT_41 = 256'h0,
parameter SRAM6_INIT_42 = 256'h0,
parameter SRAM6_INIT_43 = 256'h0,
parameter SRAM6_INIT_44 = 256'h0,
parameter SRAM6_INIT_45 = 256'h0,
parameter SRAM6_INIT_46 = 256'h0,
parameter SRAM6_INIT_47 = 256'h0,
parameter SRAM6_INIT_48 = 256'h0,
parameter SRAM6_INIT_49 = 256'h0,
parameter SRAM6_INIT_50 = 256'h0,
parameter SRAM6_INIT_51 = 256'h0,
parameter SRAM6_INIT_52 = 256'h0,
parameter SRAM6_INIT_53 = 256'h0,
parameter SRAM6_INIT_54 = 256'h0,
parameter SRAM6_INIT_55 = 256'h0,
parameter SRAM6_INIT_56 = 256'h0,
parameter SRAM6_INIT_57 = 256'h0,
parameter SRAM6_INIT_58 = 256'h0,
parameter SRAM6_INIT_59 = 256'h0,
parameter SRAM6_INIT_60 = 256'h0,
parameter SRAM6_INIT_61 = 256'h0,
parameter SRAM6_INIT_62 = 256'h0,
parameter SRAM6_INIT_63 = 256'h0,
parameter SRAM7_INIT_0 = 256'h0,
parameter SRAM7_INIT_1 = 256'h0,
parameter SRAM7_INIT_2 = 256'h0,
parameter SRAM7_INIT_3 = 256'h0,
parameter SRAM7_INIT_4 = 256'h0,
parameter SRAM7_INIT_5 = 256'h0,
parameter SRAM7_INIT_6 = 256'h0,
parameter SRAM7_INIT_7 = 256'h0,
parameter SRAM7_INIT_8 = 256'h0,
parameter SRAM7_INIT_9 = 256'h0,
parameter SRAM7_INIT_10 = 256'h0,
parameter SRAM7_INIT_11 = 256'h0,
parameter SRAM7_INIT_12 = 256'h0,
parameter SRAM7_INIT_13 = 256'h0,
parameter SRAM7_INIT_14 = 256'h0,
parameter SRAM7_INIT_15 = 256'h0,
parameter SRAM7_INIT_16 = 256'h0,
parameter SRAM7_INIT_17 = 256'h0,
parameter SRAM7_INIT_18 = 256'h0,
parameter SRAM7_INIT_19 = 256'h0,
parameter SRAM7_INIT_20 = 256'h0,
parameter SRAM7_INIT_21 = 256'h0,
parameter SRAM7_INIT_22 = 256'h0,
parameter SRAM7_INIT_23 = 256'h0,
parameter SRAM7_INIT_24 = 256'h0,
parameter SRAM7_INIT_25 = 256'h0,
parameter SRAM7_INIT_26 = 256'h0,
parameter SRAM7_INIT_27 = 256'h0,
parameter SRAM7_INIT_28 = 256'h0,
parameter SRAM7_INIT_29 = 256'h0,
parameter SRAM7_INIT_30 = 256'h0,
parameter SRAM7_INIT_31 = 256'h0,
parameter SRAM7_INIT_32 = 256'h0,
parameter SRAM7_INIT_33 = 256'h0,
parameter SRAM7_INIT_34 = 256'h0,
parameter SRAM7_INIT_35 = 256'h0,
parameter SRAM7_INIT_36 = 256'h0,
parameter SRAM7_INIT_37 = 256'h0,
parameter SRAM7_INIT_38 = 256'h0,
parameter SRAM7_INIT_39 = 256'h0,
parameter SRAM7_INIT_40 = 256'h0,
parameter SRAM7_INIT_41 = 256'h0,
parameter SRAM7_INIT_42 = 256'h0,
parameter SRAM7_INIT_43 = 256'h0,
parameter SRAM7_INIT_44 = 256'h0,
parameter SRAM7_INIT_45 = 256'h0,
parameter SRAM7_INIT_46 = 256'h0,
parameter SRAM7_INIT_47 = 256'h0,
parameter SRAM7_INIT_48 = 256'h0,
parameter SRAM7_INIT_49 = 256'h0,
parameter SRAM7_INIT_50 = 256'h0,
parameter SRAM7_INIT_51 = 256'h0,
parameter SRAM7_INIT_52 = 256'h0,
parameter SRAM7_INIT_53 = 256'h0,
parameter SRAM7_INIT_54 = 256'h0,
parameter SRAM7_INIT_55 = 256'h0,
parameter SRAM7_INIT_56 = 256'h0,
parameter SRAM7_INIT_57 = 256'h0,
parameter SRAM7_INIT_58 = 256'h0,
parameter SRAM7_INIT_59 = 256'h0,
parameter SRAM7_INIT_60 = 256'h0,
parameter SRAM7_INIT_61 = 256'h0,
parameter SRAM7_INIT_62 = 256'h0,
parameter SRAM7_INIT_63 = 256'h0,
parameter UNUSED = 1'd1
)
(
input i_clk,
input [127:0] i_write_data,
input i_write_enable,
input [9:0] i_address,
input [15:0] i_byte_enable,
output [127:0] o_read_data
);
wire [23:0] nc24_00, nc24_01, nc24_02, nc24_03;
wire [15:0] wea_b0;
wire [15:0] wea_b1;
wire [127:0] read_data_b0;
wire [127:0] read_data_b1;
reg address_9_r;
always @(posedge i_clk)
address_9_r <= i_address[9];
assign wea_b0 = {16{i_write_enable & ~i_address[9]}} & i_byte_enable;
assign wea_b1 = {16{i_write_enable & i_address[9]}} & i_byte_enable;
assign o_read_data = address_9_r ? read_data_b1 : read_data_b0;
// -----------------------------------------
// Bank 0 - first 8kb block
// -----------------------------------------
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[3:0] ),
.DOA ( read_data_b0[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram1 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[7:4] ),
.DOA ( read_data_b0[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[11:8] ),
.DOA ( read_data_b0[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[15:12] ),
.DOA ( read_data_b0[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
// -----------------------------------------
// Bank 1 - second 8kb block
// -----------------------------------------
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM4_INIT_0 ),
.INIT_01 ( SRAM4_INIT_1 ),
.INIT_02 ( SRAM4_INIT_2 ),
.INIT_03 ( SRAM4_INIT_3 ),
.INIT_04 ( SRAM4_INIT_4 ),
.INIT_05 ( SRAM4_INIT_5 ),
.INIT_06 ( SRAM4_INIT_6 ),
.INIT_07 ( SRAM4_INIT_7 ),
.INIT_08 ( SRAM4_INIT_8 ),
.INIT_09 ( SRAM4_INIT_9 ),
.INIT_0A ( SRAM4_INIT_10 ),
.INIT_0B ( SRAM4_INIT_11 ),
.INIT_0C ( SRAM4_INIT_12 ),
.INIT_0D ( SRAM4_INIT_13 ),
.INIT_0E ( SRAM4_INIT_14 ),
.INIT_0F ( SRAM4_INIT_15 ),
.INIT_10 ( SRAM4_INIT_16 ),
.INIT_11 ( SRAM4_INIT_17 ),
.INIT_12 ( SRAM4_INIT_18 ),
.INIT_13 ( SRAM4_INIT_19 ),
.INIT_14 ( SRAM4_INIT_20 ),
.INIT_15 ( SRAM4_INIT_21 ),
.INIT_16 ( SRAM4_INIT_22 ),
.INIT_17 ( SRAM4_INIT_23 ),
.INIT_18 ( SRAM4_INIT_24 ),
.INIT_19 ( SRAM4_INIT_25 ),
.INIT_1A ( SRAM4_INIT_26 ),
.INIT_1B ( SRAM4_INIT_27 ),
.INIT_1C ( SRAM4_INIT_28 ),
.INIT_1D ( SRAM4_INIT_29 ),
.INIT_1E ( SRAM4_INIT_30 ),
.INIT_1F ( SRAM4_INIT_31 ),
.INIT_20 ( SRAM4_INIT_32 ),
.INIT_21 ( SRAM4_INIT_33 ),
.INIT_22 ( SRAM4_INIT_34 ),
.INIT_23 ( SRAM4_INIT_35 ),
.INIT_24 ( SRAM4_INIT_36 ),
.INIT_25 ( SRAM4_INIT_37 ),
.INIT_26 ( SRAM4_INIT_38 ),
.INIT_27 ( SRAM4_INIT_39 ),
.INIT_28 ( SRAM4_INIT_40 ),
.INIT_29 ( SRAM4_INIT_41 ),
.INIT_2A ( SRAM4_INIT_42 ),
.INIT_2B ( SRAM4_INIT_43 ),
.INIT_2C ( SRAM4_INIT_44 ),
.INIT_2D ( SRAM4_INIT_45 ),
.INIT_2E ( SRAM4_INIT_46 ),
.INIT_2F ( SRAM4_INIT_47 ),
.INIT_30 ( SRAM4_INIT_48 ),
.INIT_31 ( SRAM4_INIT_49 ),
.INIT_32 ( SRAM4_INIT_50 ),
.INIT_33 ( SRAM4_INIT_51 ),
.INIT_34 ( SRAM4_INIT_52 ),
.INIT_35 ( SRAM4_INIT_53 ),
.INIT_36 ( SRAM4_INIT_54 ),
.INIT_37 ( SRAM4_INIT_55 ),
.INIT_38 ( SRAM4_INIT_56 ),
.INIT_39 ( SRAM4_INIT_57 ),
.INIT_3A ( SRAM4_INIT_58 ),
.INIT_3B ( SRAM4_INIT_59 ),
.INIT_3C ( SRAM4_INIT_60 ),
.INIT_3D ( SRAM4_INIT_61 ),
.INIT_3E ( SRAM4_INIT_62 ),
.INIT_3F ( SRAM4_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram4 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[3:0] ),
.DOA ( read_data_b1[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM5_INIT_0 ),
.INIT_01 ( SRAM5_INIT_1 ),
.INIT_02 ( SRAM5_INIT_2 ),
.INIT_03 ( SRAM5_INIT_3 ),
.INIT_04 ( SRAM5_INIT_4 ),
.INIT_05 ( SRAM5_INIT_5 ),
.INIT_06 ( SRAM5_INIT_6 ),
.INIT_07 ( SRAM5_INIT_7 ),
.INIT_08 ( SRAM5_INIT_8 ),
.INIT_09 ( SRAM5_INIT_9 ),
.INIT_0A ( SRAM5_INIT_10 ),
.INIT_0B ( SRAM5_INIT_11 ),
.INIT_0C ( SRAM5_INIT_12 ),
.INIT_0D ( SRAM5_INIT_13 ),
.INIT_0E ( SRAM5_INIT_14 ),
.INIT_0F ( SRAM5_INIT_15 ),
.INIT_10 ( SRAM5_INIT_16 ),
.INIT_11 ( SRAM5_INIT_17 ),
.INIT_12 ( SRAM5_INIT_18 ),
.INIT_13 ( SRAM5_INIT_19 ),
.INIT_14 ( SRAM5_INIT_20 ),
.INIT_15 ( SRAM5_INIT_21 ),
.INIT_16 ( SRAM5_INIT_22 ),
.INIT_17 ( SRAM5_INIT_23 ),
.INIT_18 ( SRAM5_INIT_24 ),
.INIT_19 ( SRAM5_INIT_25 ),
.INIT_1A ( SRAM5_INIT_26 ),
.INIT_1B ( SRAM5_INIT_27 ),
.INIT_1C ( SRAM5_INIT_28 ),
.INIT_1D ( SRAM5_INIT_29 ),
.INIT_1E ( SRAM5_INIT_30 ),
.INIT_1F ( SRAM5_INIT_31 ),
.INIT_20 ( SRAM5_INIT_32 ),
.INIT_21 ( SRAM5_INIT_33 ),
.INIT_22 ( SRAM5_INIT_34 ),
.INIT_23 ( SRAM5_INIT_35 ),
.INIT_24 ( SRAM5_INIT_36 ),
.INIT_25 ( SRAM5_INIT_37 ),
.INIT_26 ( SRAM5_INIT_38 ),
.INIT_27 ( SRAM5_INIT_39 ),
.INIT_28 ( SRAM5_INIT_40 ),
.INIT_29 ( SRAM5_INIT_41 ),
.INIT_2A ( SRAM5_INIT_42 ),
.INIT_2B ( SRAM5_INIT_43 ),
.INIT_2C ( SRAM5_INIT_44 ),
.INIT_2D ( SRAM5_INIT_45 ),
.INIT_2E ( SRAM5_INIT_46 ),
.INIT_2F ( SRAM5_INIT_47 ),
.INIT_30 ( SRAM5_INIT_48 ),
.INIT_31 ( SRAM5_INIT_49 ),
.INIT_32 ( SRAM5_INIT_50 ),
.INIT_33 ( SRAM5_INIT_51 ),
.INIT_34 ( SRAM5_INIT_52 ),
.INIT_35 ( SRAM5_INIT_53 ),
.INIT_36 ( SRAM5_INIT_54 ),
.INIT_37 ( SRAM5_INIT_55 ),
.INIT_38 ( SRAM5_INIT_56 ),
.INIT_39 ( SRAM5_INIT_57 ),
.INIT_3A ( SRAM5_INIT_58 ),
.INIT_3B ( SRAM5_INIT_59 ),
.INIT_3C ( SRAM5_INIT_60 ),
.INIT_3D ( SRAM5_INIT_61 ),
.INIT_3E ( SRAM5_INIT_62 ),
.INIT_3F ( SRAM5_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram5 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[7:4] ),
.DOA ( read_data_b1[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM6_INIT_0 ),
.INIT_01 ( SRAM6_INIT_1 ),
.INIT_02 ( SRAM6_INIT_2 ),
.INIT_03 ( SRAM6_INIT_3 ),
.INIT_04 ( SRAM6_INIT_4 ),
.INIT_05 ( SRAM6_INIT_5 ),
.INIT_06 ( SRAM6_INIT_6 ),
.INIT_07 ( SRAM6_INIT_7 ),
.INIT_08 ( SRAM6_INIT_8 ),
.INIT_09 ( SRAM6_INIT_9 ),
.INIT_0A ( SRAM6_INIT_10 ),
.INIT_0B ( SRAM6_INIT_11 ),
.INIT_0C ( SRAM6_INIT_12 ),
.INIT_0D ( SRAM6_INIT_13 ),
.INIT_0E ( SRAM6_INIT_14 ),
.INIT_0F ( SRAM6_INIT_15 ),
.INIT_10 ( SRAM6_INIT_16 ),
.INIT_11 ( SRAM6_INIT_17 ),
.INIT_12 ( SRAM6_INIT_18 ),
.INIT_13 ( SRAM6_INIT_19 ),
.INIT_14 ( SRAM6_INIT_20 ),
.INIT_15 ( SRAM6_INIT_21 ),
.INIT_16 ( SRAM6_INIT_22 ),
.INIT_17 ( SRAM6_INIT_23 ),
.INIT_18 ( SRAM6_INIT_24 ),
.INIT_19 ( SRAM6_INIT_25 ),
.INIT_1A ( SRAM6_INIT_26 ),
.INIT_1B ( SRAM6_INIT_27 ),
.INIT_1C ( SRAM6_INIT_28 ),
.INIT_1D ( SRAM6_INIT_29 ),
.INIT_1E ( SRAM6_INIT_30 ),
.INIT_1F ( SRAM6_INIT_31 ),
.INIT_20 ( SRAM6_INIT_32 ),
.INIT_21 ( SRAM6_INIT_33 ),
.INIT_22 ( SRAM6_INIT_34 ),
.INIT_23 ( SRAM6_INIT_35 ),
.INIT_24 ( SRAM6_INIT_36 ),
.INIT_25 ( SRAM6_INIT_37 ),
.INIT_26 ( SRAM6_INIT_38 ),
.INIT_27 ( SRAM6_INIT_39 ),
.INIT_28 ( SRAM6_INIT_40 ),
.INIT_29 ( SRAM6_INIT_41 ),
.INIT_2A ( SRAM6_INIT_42 ),
.INIT_2B ( SRAM6_INIT_43 ),
.INIT_2C ( SRAM6_INIT_44 ),
.INIT_2D ( SRAM6_INIT_45 ),
.INIT_2E ( SRAM6_INIT_46 ),
.INIT_2F ( SRAM6_INIT_47 ),
.INIT_30 ( SRAM6_INIT_48 ),
.INIT_31 ( SRAM6_INIT_49 ),
.INIT_32 ( SRAM6_INIT_50 ),
.INIT_33 ( SRAM6_INIT_51 ),
.INIT_34 ( SRAM6_INIT_52 ),
.INIT_35 ( SRAM6_INIT_53 ),
.INIT_36 ( SRAM6_INIT_54 ),
.INIT_37 ( SRAM6_INIT_55 ),
.INIT_38 ( SRAM6_INIT_56 ),
.INIT_39 ( SRAM6_INIT_57 ),
.INIT_3A ( SRAM6_INIT_58 ),
.INIT_3B ( SRAM6_INIT_59 ),
.INIT_3C ( SRAM6_INIT_60 ),
.INIT_3D ( SRAM6_INIT_61 ),
.INIT_3E ( SRAM6_INIT_62 ),
.INIT_3F ( SRAM6_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram6 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[11:8] ),
.DOA ( read_data_b1[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
.INIT_00 ( SRAM7_INIT_0 ),
.INIT_01 ( SRAM7_INIT_1 ),
.INIT_02 ( SRAM7_INIT_2 ),
.INIT_03 ( SRAM7_INIT_3 ),
.INIT_04 ( SRAM7_INIT_4 ),
.INIT_05 ( SRAM7_INIT_5 ),
.INIT_06 ( SRAM7_INIT_6 ),
.INIT_07 ( SRAM7_INIT_7 ),
.INIT_08 ( SRAM7_INIT_8 ),
.INIT_09 ( SRAM7_INIT_9 ),
.INIT_0A ( SRAM7_INIT_10 ),
.INIT_0B ( SRAM7_INIT_11 ),
.INIT_0C ( SRAM7_INIT_12 ),
.INIT_0D ( SRAM7_INIT_13 ),
.INIT_0E ( SRAM7_INIT_14 ),
.INIT_0F ( SRAM7_INIT_15 ),
.INIT_10 ( SRAM7_INIT_16 ),
.INIT_11 ( SRAM7_INIT_17 ),
.INIT_12 ( SRAM7_INIT_18 ),
.INIT_13 ( SRAM7_INIT_19 ),
.INIT_14 ( SRAM7_INIT_20 ),
.INIT_15 ( SRAM7_INIT_21 ),
.INIT_16 ( SRAM7_INIT_22 ),
.INIT_17 ( SRAM7_INIT_23 ),
.INIT_18 ( SRAM7_INIT_24 ),
.INIT_19 ( SRAM7_INIT_25 ),
.INIT_1A ( SRAM7_INIT_26 ),
.INIT_1B ( SRAM7_INIT_27 ),
.INIT_1C ( SRAM7_INIT_28 ),
.INIT_1D ( SRAM7_INIT_29 ),
.INIT_1E ( SRAM7_INIT_30 ),
.INIT_1F ( SRAM7_INIT_31 ),
.INIT_20 ( SRAM7_INIT_32 ),
.INIT_21 ( SRAM7_INIT_33 ),
.INIT_22 ( SRAM7_INIT_34 ),
.INIT_23 ( SRAM7_INIT_35 ),
.INIT_24 ( SRAM7_INIT_36 ),
.INIT_25 ( SRAM7_INIT_37 ),
.INIT_26 ( SRAM7_INIT_38 ),
.INIT_27 ( SRAM7_INIT_39 ),
.INIT_28 ( SRAM7_INIT_40 ),
.INIT_29 ( SRAM7_INIT_41 ),
.INIT_2A ( SRAM7_INIT_42 ),
.INIT_2B ( SRAM7_INIT_43 ),
.INIT_2C ( SRAM7_INIT_44 ),
.INIT_2D ( SRAM7_INIT_45 ),
.INIT_2E ( SRAM7_INIT_46 ),
.INIT_2F ( SRAM7_INIT_47 ),
.INIT_30 ( SRAM7_INIT_48 ),
.INIT_31 ( SRAM7_INIT_49 ),
.INIT_32 ( SRAM7_INIT_50 ),
.INIT_33 ( SRAM7_INIT_51 ),
.INIT_34 ( SRAM7_INIT_52 ),
.INIT_35 ( SRAM7_INIT_53 ),
.INIT_36 ( SRAM7_INIT_54 ),
.INIT_37 ( SRAM7_INIT_55 ),
.INIT_38 ( SRAM7_INIT_56 ),
.INIT_39 ( SRAM7_INIT_57 ),
.INIT_3A ( SRAM7_INIT_58 ),
.INIT_3B ( SRAM7_INIT_59 ),
.INIT_3C ( SRAM7_INIT_60 ),
.INIT_3D ( SRAM7_INIT_61 ),
.INIT_3E ( SRAM7_INIT_62 ),
.INIT_3F ( SRAM7_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram7 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[15:12] ),
.DOA ( read_data_b1[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_PP_SYMBOL_V
|
/***********************************************************************
Incorrect direction non-detection test case
Copyright (C) 2001 Eric LaForest, [email protected]
Licenced under GPL
***********************************************************************/
module CPU (data, address, rw, clock, reset);
inout [15:0] data;
output [15:0] address;
// This should be an output really....
input rw;
input clock, reset;
reg [15:0] data, address; // XXX error on data
reg rw; // error on rw
// I presume these should not be allowed to occur....
always @(posedge clock) begin
rw <= 1'b1;
end
always @(negedge clock) begin
rw <= 1'b0;
end
endmodule
module BENCH ();
reg [15:0] address, data;
reg rw, clock, reset;
CPU fm (address, data, rw, clock, reset);
initial begin
clock <= 0;
reset <= 1;
#1000;
$finish;
end
always begin
# 10 clock <= ~clock;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V |
// AJ, Beck, and Ray
// subtract testbench
// 5/4/15
`include "adder_subtractor.v"
`include "flag.v"
`include "mux2_1.sv"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "subtract.v"
module subtracttest();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
wire zADD, oADD, cADD, nADD;
// declare an instance of the module
subtract subtract (busADD, busA, busB, zADD, oADD, cADD, nADD);
// Running the GUI part of simulation
subtracttester tester (busADD, busA, busB, zADD, oADD, cADD, nADD);
// file for gtkwave
initial
begin
$dumpfile("subtracttest.vcd");
$dumpvars(1, subtract);
end
endmodule
module subtracttester (busADD, busA, busB, zADD, oADD, cADD, nADD);
input [31:0] busADD;
output reg [31:0] busA, busB;
input zADD, oADD, cADD, nADD;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t zADD \t oADD \t cADD \t nADD \t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b", busADD, busA, busB, zADD, oADD, cADD, nADD, $time);
// positive - positive
busA = 32'h01010101; busB = 32'h01010101; // should have carryOut
#d;
busA = 32'h7FFFFFF0; busB = 32'h7FFFFFFF;
#d;
// positive - negative
busA = 32'h00000001; busB = 32'hFFFFFFFF; // 1 - -1
#d;
busA = 32'h70000000; busB = 32'hF0000000; // should overflow
#d;
// negative - positive
busA = 32'hFFFFFFFF; busB = 32'h00000001;
#d;
busA = 32'h90000000; busB = 32'h70000000; // should overflow
#d;
// negative - negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF;
#d;
busA = 32'hF0000000; busB = 32'hF0000000;
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x14.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 14;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [1:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [1:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x14_bist artisan_ssp(
`else
art_hssp_64x14 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x14_bist vs_ssp(
`else
vs_hdsp_64x14 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({2'b00, di[13:0]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
RAMB16_S18 ramb16_s18(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({2'b00, di[13:0]}),
.DIP(2'b00),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverydEe_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 1;
parameter AWIDTH = 9;
parameter MEM_SIZE = 300;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverydEe(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd300;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
contact_discoverydEe_ram contact_discoverydEe_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pipe_eq.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_eq.v
// Description : PIPE Equalization Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Equalization Module ------------------------------------------
module PCIEBus_pipe_eq #
(
parameter PCIE_SIM_MODE = "FALSE",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_RXEQ_MODE_GEN3 = 1
)
(
//---------- Input -------------------------------------
input EQ_CLK,
input EQ_RST_N,
input EQ_GEN3,
input [ 1:0] EQ_TXEQ_CONTROL,
input [ 3:0] EQ_TXEQ_PRESET,
input [ 3:0] EQ_TXEQ_PRESET_DEFAULT,
input [ 5:0] EQ_TXEQ_DEEMPH_IN,
input [ 1:0] EQ_RXEQ_CONTROL,
input [ 2:0] EQ_RXEQ_PRESET,
input [ 5:0] EQ_RXEQ_LFFS,
input [ 3:0] EQ_RXEQ_TXPRESET,
input EQ_RXEQ_USER_EN,
input [17:0] EQ_RXEQ_USER_TXCOEFF,
input EQ_RXEQ_USER_MODE,
//---------- Output ------------------------------------
output EQ_TXEQ_DEEMPH,
output [ 4:0] EQ_TXEQ_PRECURSOR,
output [ 6:0] EQ_TXEQ_MAINCURSOR,
output [ 4:0] EQ_TXEQ_POSTCURSOR,
output [17:0] EQ_TXEQ_DEEMPH_OUT,
output EQ_TXEQ_DONE,
output [ 5:0] EQ_TXEQ_FSM,
output [17:0] EQ_RXEQ_NEW_TXCOEFF,
output EQ_RXEQ_LFFS_SEL,
output EQ_RXEQ_ADAPT_DONE,
output EQ_RXEQ_DONE,
output [ 5:0] EQ_RXEQ_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
//---------- Internal Signals --------------------------
reg [18:0] txeq_preset = 19'd0;
reg txeq_preset_done = 1'd0;
reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
reg [ 2:0] rxeq_preset = 3'd0;
reg rxeq_preset_valid = 1'd0;
reg [ 3:0] rxeq_txpreset = 4'd0;
reg [17:0] rxeq_txcoeff = 18'd0;
reg [ 2:0] rxeq_cnt = 3'd0;
reg [ 5:0] rxeq_fs = 6'd0;
reg [ 5:0] rxeq_lf = 6'd0;
reg rxeq_new_txcoeff_req = 1'd0;
//---------- Output Registers --------------------------
reg [18:0] txeq_txcoeff = 19'd0;
reg txeq_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg [17:0] rxeq_new_txcoeff = 18'd0;
reg rxeq_lffs_sel = 1'd0;
reg rxeq_adapt_done_reg = 1'd0;
reg rxeq_adapt_done = 1'd0;
reg rxeq_done = 1'd0;
reg [ 5:0] fsm_rx = 6'd0;
//---------- RXEQ Eye Scan Module Output ---------------
wire rxeqscan_lffs_sel;
wire rxeqscan_preset_done;
wire [17:0] rxeqscan_new_txcoeff;
wire rxeqscan_new_txcoeff_done;
wire rxeqscan_adapt_done;
//---------- FSM ---------------------------------------
localparam FSM_TXEQ_IDLE = 6'b000001;
localparam FSM_TXEQ_PRESET = 6'b000010;
localparam FSM_TXEQ_TXCOEFF = 6'b000100;
localparam FSM_TXEQ_REMAP = 6'b001000;
localparam FSM_TXEQ_QUERY = 6'b010000;
localparam FSM_TXEQ_DONE = 6'b100000;
localparam FSM_RXEQ_IDLE = 6'b000001;
localparam FSM_RXEQ_PRESET = 6'b000010;
localparam FSM_RXEQ_TXCOEFF = 6'b000100;
localparam FSM_RXEQ_LF = 6'b001000;
localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;
localparam FSM_RXEQ_DONE = 6'b100000;
//---------- TXEQ Presets Look-up Table ----------------
// TXPRECURSOR = Coefficient range between 0 and 20 units
// TXMAINCURSOR = Coefficient range between 29 and 80 units
// TXPOSTCURSOR = Coefficient range between 0 and 31 units
//------------------------------------------------------
// Actual Full Swing (FS) = 80
// Actual Low Frequency (LF) = 29
// Advertise Full Swing (FS) = 40
// Advertise Low Frequency (LF) = 15
//------------------------------------------------------
// Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
// Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
// De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis
//------------------------------------------------------
// Note: TXMAINCURSOR calculated internally in GT
//------------------------------------------------------
localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_00 = 7'd60;
localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB
localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB
localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_02 = 7'd64;
localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB
localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_03 = 7'd70;
localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB
localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_04 = 7'd80;
localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB
localparam TXMAINCURSOR_05 = 7'd72;
localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB
localparam TXMAINCURSOR_06 = 7'd70;
localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_07 = 7'd56;
localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB
localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_08 = 7'd60;
localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal
localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules
//---------- Input FF ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
txeq_control_reg1 <= 2'd0;
txeq_preset_reg1 <= 4'd0;
txeq_deemph_reg1 <= 6'd1;
rxeq_control_reg1 <= 2'd0;
rxeq_preset_reg1 <= 3'd0;
rxeq_lffs_reg1 <= 6'd0;
rxeq_txpreset_reg1 <= 4'd0;
rxeq_user_en_reg1 <= 1'd0;
rxeq_user_txcoeff_reg1 <= 18'd0;
rxeq_user_mode_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
txeq_control_reg2 <= 2'd0;
txeq_preset_reg2 <= 4'd0;
txeq_deemph_reg2 <= 6'd1;
rxeq_control_reg2 <= 2'd0;
rxeq_preset_reg2 <= 3'd0;
rxeq_lffs_reg2 <= 6'd0;
rxeq_txpreset_reg2 <= 4'd0;
rxeq_user_en_reg2 <= 1'd0;
rxeq_user_txcoeff_reg2 <= 18'd0;
rxeq_user_mode_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= EQ_GEN3;
txeq_control_reg1 <= EQ_TXEQ_CONTROL;
txeq_preset_reg1 <= EQ_TXEQ_PRESET;
txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN;
rxeq_control_reg1 <= EQ_RXEQ_CONTROL;
rxeq_preset_reg1 <= EQ_RXEQ_PRESET;
rxeq_lffs_reg1 <= EQ_RXEQ_LFFS;
rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET;
rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN;
rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
txeq_control_reg2 <= txeq_control_reg1;
txeq_preset_reg2 <= txeq_preset_reg1;
txeq_deemph_reg2 <= txeq_deemph_reg1;
rxeq_control_reg2 <= rxeq_control_reg1;
rxeq_preset_reg2 <= rxeq_preset_reg1;
rxeq_lffs_reg2 <= rxeq_lffs_reg1;
rxeq_txpreset_reg2 <= rxeq_txpreset_reg1;
rxeq_user_en_reg2 <= rxeq_user_en_reg1;
rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
rxeq_user_mode_reg2 <= rxeq_user_mode_reg1;
end
end
//---------- TXEQ Preset -------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- Select TXEQ Preset ----------------
case (EQ_TXEQ_PRESET_DEFAULT)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd0;
end
else
begin
if (fsm_tx == FSM_TXEQ_PRESET)
begin
//---------- Select TXEQ Preset ----------------
case (txeq_preset_reg2)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd1;
end
else
begin
txeq_preset <= txeq_preset;
txeq_preset_done <= 1'd0;
end
end
end
//---------- TXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ----------------------------
FSM_TXEQ_IDLE :
begin
case (txeq_control_reg2)
//---------- Idle ------------------------------
2'd0 :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Process TXEQ Preset ---------------
2'd1 :
begin
fsm_tx <= FSM_TXEQ_PRESET;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Coefficient -----------------------
2'd2 :
begin
fsm_tx <= FSM_TXEQ_TXCOEFF;
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= 2'd1;
txeq_done <= 1'd0;
end
//---------- Query -----------------------------
2'd3 :
begin
fsm_tx <= FSM_TXEQ_QUERY;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
//---------- Process TXEQ Preset -------------------
FSM_TXEQ_PRESET :
begin
fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
txeq_txcoeff <= txeq_preset;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Latch Link Partner TX Coefficient -----
FSM_TXEQ_TXCOEFF :
begin
fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
//---------- Shift in extra bit for TXMAINCURSOR
if (txeq_txcoeff_cnt == 2'd1)
txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
else
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
txeq_done <= 1'd0;
end
//---------- Remap to GT TX Coefficient ------------
FSM_TXEQ_REMAP :
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Query TXEQ Coefficient ----------------
FSM_TXEQ_QUERY:
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Done ----------------------------------
FSM_TXEQ_DONE :
begin
fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ----------------------------
FSM_RXEQ_IDLE :
begin
case (rxeq_control_reg2)
//---------- Process RXEQ Preset ---------------
2'd1 :
begin
fsm_rx <= FSM_RXEQ_PRESET;
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient --------
2'd2 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
2'd3 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
//---------- Process RXEQ Preset -------------------
FSM_RXEQ_PRESET :
begin
fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd1;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Shift-in Link Partner TX Coefficient and Preset
FSM_RXEQ_TXCOEFF :
begin
fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Read Low Frequency (LF) Value ---------
FSM_RXEQ_LF :
begin
fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient ------------
FSM_RXEQ_NEW_TXCOEFF_REQ :
begin
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
if (rxeqscan_new_txcoeff_done)
begin
fsm_rx <= FSM_RXEQ_DONE;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
rxeq_lffs_sel <= rxeqscan_lffs_sel;
rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ;
rxeq_new_txcoeff_req <= 1'd1;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
end
//---------- RXEQ Done -----------------------------
FSM_RXEQ_DONE :
begin
fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= rxeq_lffs_sel;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeq_adapt_done;
rxeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Module ----------------------------------------------
PCIEBus_rxeq_scan #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE),
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3)
)
rxeq_scan_i
(
//---------- Input -------------------------------------
.RXEQSCAN_CLK (EQ_CLK),
.RXEQSCAN_RST_N (EQ_RST_N),
.RXEQSCAN_CONTROL (rxeq_control_reg2),
.RXEQSCAN_FS (rxeq_fs),
.RXEQSCAN_LF (rxeq_lf),
.RXEQSCAN_PRESET (rxeq_preset),
.RXEQSCAN_PRESET_VALID (rxeq_preset_valid),
.RXEQSCAN_TXPRESET (rxeq_txpreset),
.RXEQSCAN_TXCOEFF (rxeq_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req),
//---------- Output ------------------------------------
.RXEQSCAN_PRESET_DONE (rxeqscan_preset_done),
.RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done),
.RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel),
.RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done)
);
//---------- PIPE EQ Output ----------------------------------------------------
assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0];
assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00;
assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
assign EQ_TXEQ_DONE = txeq_done;
assign EQ_TXEQ_FSM = fsm_tx;
assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel;
assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done;
assign EQ_RXEQ_DONE = rxeq_done;
assign EQ_RXEQ_FSM = fsm_rx;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
wire ignore_new_start = (action_on_new_start == `OVL_IGNORE_NEW_START);
wire reset_on_new_start = (action_on_new_start == `OVL_RESET_ON_NEW_START);
wire error_on_new_start = (action_on_new_start == `OVL_ERROR_ON_NEW_START);
`ifdef OVL_SHARED_CODE
reg window = 0;
integer i = 0;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (!window && start_event == 1'b1) begin
window <= 1'b1;
i <= num_cks;
end
else if (window) begin
if (i == 1 && ((!reset_on_new_start) || (!start_event)) )
window <= 1'b0;
if (reset_on_new_start && start_event)
i <= num_cks;
else if (i != 1)
i <= i - 1;
end // if (window)
end
else begin
window <= 1'b0;
i <= 0;
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_time_assert #(
.num_cks(num_cks))
assert_time_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.test_expr(test_expr),
.window(window),
.ignore_new_start(ignore_new_start),
.reset_on_new_start(reset_on_new_start),
.error_on_new_start(error_on_new_start),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_time_assume #(
.num_cks(num_cks))
assert_time_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.test_expr(test_expr),
.window(window),
.ignore_new_start(ignore_new_start),
.reset_on_new_start(reset_on_new_start),
.error_on_new_start(error_on_new_start),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_time_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_time_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_event(start_event),
.window(window),
.reset_on_new_start(reset_on_new_start),
.window_close(i == 1)); // i == 1 means window is closing
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_time.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_time_assert (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start, xzcheck_enable);
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start;
input test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_time_assume (clk, reset_n, start_event, test_expr, window,
ignore_new_start, reset_on_new_start, error_on_new_start, xzcheck_enable);
parameter num_cks = 2;
input clk, reset_n, start_event, window, ignore_new_start, reset_on_new_start, error_on_new_start;
input test_expr, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_time_cover (clk, reset_n, start_event, window, reset_on_new_start, window_close);
parameter OVL_COVER_BASIC_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, start_event, window, reset_on_new_start, window_close;
//wire window_close;//This is for passing the condition while a window is closing
endmodule
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 28325 $
// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule // BRAM2
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__FAHCON_PP_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_top.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input [3:0] reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [8-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [17:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [4:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[9];
assign tx_negedge = reg_ctrl[10];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[6:0];
assign lsb = reg_ctrl[11];
assign ie = reg_ctrl[12];
assign ass = reg_ctrl[13];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {8{tip & ass}}) | (reg_ss & {8{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[5-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
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