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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_2048x8(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/17.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2017/08/13 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// Code ok to distribute
module autoasciienum_auto();
reg [2:0] /* auto enum sm_psm */ sm_psm;
reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
localparam [2:0] // auto enum sm_psm
PSM_IDL = 0,
PSM_RST = 6,
PSM_ZOT = 7;
localparam [2:0] // auto enum sm_ps2
PS2_IDL = 0,
PS2_FOO = 1;
/*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_psm__ascii; // Decode of sm_psm
always @(sm_psm) begin
case ({sm_psm})
PSM_IDL: _sm_psm__ascii = "psmidl";
PSM_RST: _sm_psm__ascii = "psmrst";
PSM_ZOT: _sm_psm__ascii = "psmzot";
default: _sm_psm__ascii = "%Error";
endcase
end
// End of automatics
/*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_ps2__ascii; // Decode of sm_ps2
always @(sm_ps2) begin
case ({sm_ps2})
PS2_IDL: _sm_ps2__ascii = "ps2idl";
PS2_FOO: _sm_ps2__ascii = "ps2foo";
default: _sm_ps2__ascii = "%Error";
endcase
end
// End of automatics
endmodule : autoasciienum_auto
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tg_status.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
(** #<style> .doc { font-family: monospace; white-space: pre; } </style># **)
Require Import Bool. (* For bool_scope delimiter 'bool'. *)
Require Import ssrmatching.
Declare ML Module "ssreflect_plugin".
(**
This file is the Gallina part of the ssreflect plugin implementation.
Files that use the ssreflect plugin should always Require ssreflect and
either Import ssreflect or Import ssreflect.SsrSyntax.
Part of the contents of this file is technical and will only interest
advanced developers; in addition the following are defined:
#[#the str of v by f#]# == the Canonical s : str such that f s = v.
#[#the str of v#]# == the Canonical s : str that coerces to v.
argumentType c == the T such that c : forall x : T, P x.
returnType c == the R such that c : T -> R.
{type of c for s} == P s where c : forall x : T, P x.
nonPropType == an interface for non-Prop Types: a nonPropType coerces
to a Type, and only types that do _not_ have sort
Prop are canonical nonPropType instances. This is
useful for applied views (see mid-file comment).
notProp T == the nonPropType instance for type T.
phantom T v == singleton type with inhabitant Phantom T v.
phant T == singleton type with inhabitant Phant v.
=^~ r == the converse of rewriting rule r (e.g., in a
rewrite multirule).
unkeyed t == t, but treated as an unkeyed matching pattern by
the ssreflect matching algorithm.
nosimpl t == t, but on the right-hand side of Definition C :=
nosimpl disables expansion of C by /=.
locked t == t, but locked t is not convertible to t.
locked_with k t == t, but not convertible to t or locked_with k' t
unless k = k' (with k : unit). Coq type-checking
will be much more efficient if locked_with with a
bespoke k is used for sealed definitions.
unlockable v == interface for sealed constant definitions of v.
Unlockable def == the unlockable that registers def : C = v.
#[#unlockable of C#]# == a clone for C of the canonical unlockable for the
definition of C (e.g., if it uses locked_with).
#[#unlockable fun C#]# == #[#unlockable of C#]# with the expansion forced to be
an explicit lambda expression.
-> The usage pattern for ADT operations is:
Definition foo_def x1 .. xn := big_foo_expression.
Fact foo_key : unit. Proof. by #[# #]#. Qed.
Definition foo := locked_with foo_key foo_def.
Canonical foo_unlockable := #[#unlockable fun foo#]#.
This minimizes the comparison overhead for foo, while still allowing
rewrite unlock to expose big_foo_expression.
Additionally we provide default intro pattern ltac views:
- top of the stack actions:
=> /[apply] := => hyp {}/hyp
=> /[swap] := => x y; move: y x
(also swap and perserves let bindings)
=> /[dup] := => x; have copy := x; move: copy x
(also copies and preserves let bindings)
More information about these definitions and their use can be found in the
ssreflect manual, and in specific comments below. **)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Module SsrSyntax.
(**
Declare Ssr keywords: 'is' 'of' '//' '/=' and '//='. We also declare the
parsing level 8, as a workaround for a notation grammar factoring problem.
Arguments of application-style notations (at level 10) should be declared
at level 8 rather than 9 or the camlp5 grammar will not factor properly. **)
Reserved Notation "(* x 'is' y 'of' z 'isn't' // /= //= *)" (at level 8).
Reserved Notation "(* 69 *)" (at level 69).
(** Non ambiguous keyword to check if the SsrSyntax module is imported **)
Reserved Notation "(* Use to test if 'SsrSyntax_is_Imported' *)" (at level 8).
Reserved Notation "<hidden n >" (at level 0, n at level 0,
format "<hidden n >").
Reserved Notation "T (* n *)" (at level 200, format "T (* n *)").
End SsrSyntax.
Export SsrMatchingSyntax.
Export SsrSyntax.
(** Save primitive notation that will be overloaded. **)
Local Notation CoqGenericIf c vT vF := (if c then vT else vF) (only parsing).
Local Notation CoqGenericDependentIf c x R vT vF :=
(if c as x return R then vT else vF) (only parsing).
Local Notation CoqCast x T := (x : T) (only parsing).
(** Reserve notation that introduced in this file. **)
Reserved Notation "'if' c 'then' vT 'else' vF" (at level 200,
c, vT, vF at level 200).
Reserved Notation "'if' c 'return' R 'then' vT 'else' vF" (at level 200,
c, R, vT, vF at level 200).
Reserved Notation "'if' c 'as' x 'return' R 'then' vT 'else' vF" (at level 200,
c, R, vT, vF at level 200, x name).
Reserved Notation "x : T" (at level 100, right associativity,
format "'[hv' x '/ ' : T ']'").
Reserved Notation "T : 'Type'" (at level 100, format "T : 'Type'").
Reserved Notation "P : 'Prop'" (at level 100, format "P : 'Prop'").
Reserved Notation "[ 'the' sT 'of' v 'by' f ]" (at level 0,
format "[ 'the' sT 'of' v 'by' f ]").
Reserved Notation "[ 'the' sT 'of' v ]" (at level 0,
format "[ 'the' sT 'of' v ]").
Reserved Notation "{ 'type' 'of' c 'for' s }" (at level 0,
format "{ 'type' 'of' c 'for' s }").
Reserved Notation "=^~ r" (at level 100, format "=^~ r").
Reserved Notation "[ 'unlockable' 'of' C ]" (at level 0,
format "[ 'unlockable' 'of' C ]").
Reserved Notation "[ 'unlockable' 'fun' C ]" (at level 0,
format "[ 'unlockable' 'fun' C ]").
(**
To define notations for tactic in intro patterns.
When "=> /t" is parsed, "t:%ssripat" is actually interpreted. **)
Declare Scope ssripat_scope.
Delimit Scope ssripat_scope with ssripat.
(**
Make the general "if" into a notation, so that we can override it below.
The notations are "only parsing" because the Coq decompiler will not
recognize the expansion of the boolean if; using the default printer
avoids a spurious trailing %%GEN_IF. **)
Declare Scope general_if_scope.
Delimit Scope general_if_scope with GEN_IF.
Notation "'if' c 'then' vT 'else' vF" :=
(CoqGenericIf c vT vF) (only parsing) : general_if_scope.
Notation "'if' c 'return' R 'then' vT 'else' vF" :=
(CoqGenericDependentIf c c R vT vF) (only parsing) : general_if_scope.
Notation "'if' c 'as' x 'return' R 'then' vT 'else' vF" :=
(CoqGenericDependentIf c x R vT vF) (only parsing) : general_if_scope.
(** Force boolean interpretation of simple if expressions. **)
Declare Scope boolean_if_scope.
Delimit Scope boolean_if_scope with BOOL_IF.
Notation "'if' c 'return' R 'then' vT 'else' vF" :=
(if c is true as c in bool return R then vT else vF) : boolean_if_scope.
Notation "'if' c 'then' vT 'else' vF" :=
(if c%bool is true as _ in bool return _ then vT else vF) : boolean_if_scope.
Notation "'if' c 'as' x 'return' R 'then' vT 'else' vF" :=
(if c%bool is true as x in bool return R then vT else vF) : boolean_if_scope.
Open Scope boolean_if_scope.
(**
To allow a wider variety of notations without reserving a large number of
of identifiers, the ssreflect library systematically uses "forms" to
enclose complex mixfix syntax. A "form" is simply a mixfix expression
enclosed in square brackets and introduced by a keyword:
#[#keyword ... #]#
Because the keyword follows a bracket it does not need to be reserved.
Non-ssreflect libraries that do not respect the form syntax (e.g., the Coq
Lists library) should be loaded before ssreflect so that their notations
do not mask all ssreflect forms. **)
Declare Scope form_scope.
Delimit Scope form_scope with FORM.
Open Scope form_scope.
(**
Allow overloading of the cast (x : T) syntax, put whitespace around the
":" symbol to avoid lexical clashes (and for consistency with the parsing
precedence of the notation, which binds less tightly than application),
and put printing boxes that print the type of a long definition on a
separate line rather than force-fit it at the right margin. **)
Notation "x : T" := (CoqCast x T) : core_scope.
(**
Allow the casual use of notations like nat * nat for explicit Type
declarations. Note that (nat * nat : Type) is NOT equivalent to
(nat * nat)%%type, whose inferred type is legacy type "Set". **)
Notation "T : 'Type'" := (CoqCast T%type Type) (only parsing) : core_scope.
(** Allow similarly Prop annotation for, e.g., rewrite multirules. **)
Notation "P : 'Prop'" := (CoqCast P%type Prop) (only parsing) : core_scope.
(** Constants for abstract: and #[#: name #]# intro pattern **)
Definition abstract_lock := unit.
Definition abstract_key := tt.
Definition abstract (statement : Type) (id : nat) (lock : abstract_lock) :=
let: tt := lock in statement.
Declare Scope ssr_scope.
Notation "<hidden n >" := (abstract _ n _) : ssr_scope.
Notation "T (* n *)" := (abstract T n abstract_key) : ssr_scope.
Open Scope ssr_scope.
Register abstract_lock as plugins.ssreflect.abstract_lock.
Register abstract_key as plugins.ssreflect.abstract_key.
Register abstract as plugins.ssreflect.abstract.
(** Constants for tactic-views **)
Inductive external_view : Type := tactic_view of Type.
(**
Syntax for referring to canonical structures:
#[#the struct_type of proj_val by proj_fun#]#
This form denotes the Canonical instance s of the Structure type
struct_type whose proj_fun projection is proj_val, i.e., such that
proj_fun s = proj_val.
Typically proj_fun will be A record field accessors of struct_type, but
this need not be the case; it can be, for instance, a field of a record
type to which struct_type coerces; proj_val will likewise be coerced to
the return type of proj_fun. In all but the simplest cases, proj_fun
should be eta-expanded to allow for the insertion of implicit arguments.
In the common case where proj_fun itself is a coercion, the "by" part
can be omitted entirely; in this case it is inferred by casting s to the
inferred type of proj_val. Obviously the latter can be fixed by using an
explicit cast on proj_val, and it is highly recommended to do so when the
return type intended for proj_fun is "Type", as the type inferred for
proj_val may vary because of sort polymorphism (it could be Set or Prop).
Note when using the #[#the _ of _ #]# form to generate a substructure from a
telescopes-style canonical hierarchy (implementing inheritance with
coercions), one should always project or coerce the value to the BASE
structure, because Coq will only find a Canonical derived structure for
the Canonical base structure -- not for a base structure that is specific
to proj_value. **)
Module TheCanonical.
#[universes(template)]
Variant put vT sT (v1 v2 : vT) (s : sT) := Put.
Definition get vT sT v s (p : @put vT sT v v s) := let: Put _ _ _ := p in s.
Definition get_by vT sT of sT -> vT := @get vT sT.
End TheCanonical.
Import TheCanonical. (* Note: no export. *)
Local Arguments get_by _%type_scope _%type_scope _ _ _ _.
Notation "[ 'the' sT 'of' v 'by' f ]" :=
(@get_by _ sT f _ _ ((fun v' (s : sT) => Put v' (f s) s) v _))
(only parsing) : form_scope.
Notation "[ 'the' sT 'of' v ]" := (get ((fun s : sT => Put v (*coerce*) s s) _))
(only parsing) : form_scope.
(**
The following are "format only" versions of the above notations.
We need to do this to prevent the formatter from being be thrown off by
application collapsing, coercion insertion and beta reduction in the right
hand side of the notations above. **)
Notation "[ 'the' sT 'of' v 'by' f ]" := (@get_by _ sT f v _ _)
(only printing) : form_scope.
Notation "[ 'the' sT 'of' v ]" := (@get _ sT v _ _)
(only printing) : form_scope.
(**
We would like to recognize
Notation " #[# 'the' sT 'of' v : 'Type' #]#" := (@get Type sT v _ _)
(at level 0, format " #[# 'the' sT 'of' v : 'Type' #]#") : form_scope.
**)
(**
Helper notation for canonical structure inheritance support.
This is a workaround for the poor interaction between delta reduction and
canonical projections in Coq's unification algorithm, by which transparent
definitions hide canonical instances, i.e., in
Canonical a_type_struct := @Struct a_type ...
Definition my_type := a_type.
my_type doesn't effectively inherit the struct structure from a_type. Our
solution is to redeclare the instance as follows
Canonical my_type_struct := Eval hnf in #[#struct of my_type#]#.
The special notation #[#str of _ #]# must be defined for each Strucure "str"
with constructor "Str", typically as follows
Definition clone_str s :=
let: Str _ x y ... z := s return {type of Str for s} -> str in
fun k => k _ x y ... z.
Notation " #[# 'str' 'of' T 'for' s #]#" := (@clone_str s (@Str T))
(at level 0, format " #[# 'str' 'of' T 'for' s #]#") : form_scope.
Notation " #[# 'str' 'of' T #]#" := (repack_str (fun x => @Str T x))
(at level 0, format " #[# 'str' 'of' T #]#") : form_scope.
The notation for the match return predicate is defined below; the eta
expansion in the second form serves both to distinguish it from the first
and to avoid the delta reduction problem.
There are several variations on the notation and the definition of the
the "clone" function, for telescopes, mixin classes, and join (multiple
inheritance) classes. We describe a different idiom for clones in ssrfun;
it uses phantom types (see below) and static unification; see fintype and
ssralg for examples. **)
Definition argumentType T P & forall x : T, P x := T.
Definition dependentReturnType T P & forall x : T, P x := P.
Definition returnType aT rT & aT -> rT := rT.
Notation "{ 'type' 'of' c 'for' s }" := (dependentReturnType c s) : type_scope.
(**
A generic "phantom" type (actually, a unit type with a phantom parameter).
This type can be used for type definitions that require some Structure
on one of their parameters, to allow Coq to infer said structure so it
does not have to be supplied explicitly or via the " #[#the _ of _ #]#" notation
(the latter interacts poorly with other Notation).
The definition of a (co)inductive type with a parameter p : p_type, that
needs to use the operations of a structure
Structure p_str : Type := p_Str {p_repr :> p_type; p_op : p_repr -> ...}
should be given as
Inductive indt_type (p : p_str) := Indt ... .
Definition indt_of (p : p_str) & phantom p_type p := indt_type p.
Notation "{ 'indt' p }" := (indt_of (Phantom p)).
Definition indt p x y ... z : {indt p} := @Indt p x y ... z.
Notation " #[# 'indt' x y ... z #]#" := (indt x y ... z).
That is, the concrete type and its constructor should be shadowed by
definitions that use a phantom argument to infer and display the true
value of p (in practice, the "indt" constructor often performs additional
functions, like "locking" the representation -- see below).
We also define a simpler version ("phant" / "Phant") of phantom for the
common case where p_type is Type. **)
#[universes(template)]
Variant phantom T (p : T) := Phantom.
Arguments phantom : clear implicits.
Arguments Phantom : clear implicits.
#[universes(template)]
Variant phant (p : Type) := Phant.
(** Internal tagging used by the implementation of the ssreflect elim. **)
Definition protect_term (A : Type) (x : A) : A := x.
Register protect_term as plugins.ssreflect.protect_term.
(**
The ssreflect idiom for a non-keyed pattern:
- unkeyed t will match any subterm that unifies with t, regardless of
whether it displays the same head symbol as t.
- unkeyed t a b will match any application of a term f unifying with t,
to two arguments unifying with with a and b, respectively, regardless of
apparent head symbols.
- unkeyed x where x is a variable will match any subterm with the same
type as x (when x would raise the 'indeterminate pattern' error). **)
Notation unkeyed x := (let flex := x in flex).
(** Ssreflect converse rewrite rule rule idiom. **)
Definition ssr_converse R (r : R) := (Logic.I, r).
Notation "=^~ r" := (ssr_converse r) : form_scope.
(**
Term tagging (user-level).
The ssreflect library uses four strengths of term tagging to restrict
convertibility during type checking:
nosimpl t simplifies to t EXCEPT in a definition; more precisely, given
Definition foo := nosimpl bar, foo (or foo t') will NOT be expanded by
the /= and //= switches unless it is in a forcing context (e.g., in
match foo t' with ... end, foo t' will be reduced if this allows the
match to be reduced). Note that nosimpl bar is simply notation for a
a term that beta-iota reduces to bar; hence rewrite /foo will replace
foo by bar, and rewrite -/foo will replace bar by foo.
CAVEAT: nosimpl should not be used inside a Section, because the end of
section "cooking" removes the iota redex.
locked t is provably equal to t, but is not convertible to t; 'locked'
provides support for selective rewriting, via the lock t : t = locked t
Lemma, and the ssreflect unlock tactic.
locked_with k t is equal but not convertible to t, much like locked t,
but supports explicit tagging with a value k : unit. This is used to
mitigate a flaw in the term comparison heuristic of the Coq kernel,
which treats all terms of the form locked t as equal and compares their
arguments recursively, leading to an exponential blowup of comparison.
For this reason locked_with should be used rather than locked when
defining ADT operations. The unlock tactic does not support locked_with
but the unlock rewrite rule does, via the unlockable interface.
we also use Module Type ascription to create truly opaque constants,
because simple expansion of constants to reveal an unreducible term
doubles the time complexity of a negative comparison. Such opaque
constants can be expanded generically with the unlock rewrite rule.
See the definition of card and subset in fintype for examples of this. **)
Notation nosimpl t := (let: tt := tt in t).
Lemma master_key : unit. Proof. exact tt. Qed.
Definition locked A := let: tt := master_key in fun x : A => x.
Register master_key as plugins.ssreflect.master_key.
Register locked as plugins.ssreflect.locked.
Lemma lock A x : x = locked x :> A. Proof. unlock; reflexivity. Qed.
(** Needed for locked predicates, in particular for eqType's. **)
Lemma not_locked_false_eq_true : locked false <> true.
Proof. unlock; discriminate. Qed.
(** The basic closing tactic "done". **)
Ltac done :=
trivial; hnf; intros; solve
[ do ![solve [trivial | apply: sym_equal; trivial]
| discriminate | contradiction | split]
| case not_locked_false_eq_true; assumption
| match goal with H : ~ _ |- _ => solve [case H; trivial] end ].
(** Quicker done tactic not including split, syntax: /0/ **)
Ltac ssrdone0 :=
trivial; hnf; intros; solve
[ do ![solve [trivial | apply: sym_equal; trivial]
| discriminate | contradiction ]
| case not_locked_false_eq_true; assumption
| match goal with H : ~ _ |- _ => solve [case H; trivial] end ].
(** To unlock opaque constants. **)
#[universes(template)]
Structure unlockable T v := Unlockable {unlocked : T; _ : unlocked = v}.
Lemma unlock T x C : @unlocked T x C = x. Proof. by case: C. Qed.
Notation "[ 'unlockable' 'of' C ]" :=
(@Unlockable _ _ C (unlock _)) : form_scope.
Notation "[ 'unlockable' 'fun' C ]" :=
(@Unlockable _ (fun _ => _) C (unlock _)) : form_scope.
(** Generic keyed constant locking. **)
(** The argument order ensures that k is always compared before T. **)
Definition locked_with k := let: tt := k in fun T x => x : T.
(**
This can be used as a cheap alternative to cloning the unlockable instance
below, but with caution as unkeyed matching can be expensive. **)
Lemma locked_withE T k x : unkeyed (locked_with k x) = x :> T.
Proof. by case: k. Qed.
(** Intensionaly, this instance will not apply to locked u. **)
Canonical locked_with_unlockable T k x :=
@Unlockable T x (locked_with k x) (locked_withE k x).
(** More accurate variant of unlock, and safer alternative to locked_withE. **)
Lemma unlock_with T k x : unlocked (locked_with_unlockable k x) = x :> T.
Proof. exact: unlock. Qed.
(** The internal lemmas for the have tactics. **)
Definition ssr_have Plemma Pgoal (step : Plemma) rest : Pgoal := rest step.
Arguments ssr_have Plemma [Pgoal].
Definition ssr_have_let Pgoal Plemma step
(rest : let x : Plemma := step in Pgoal) : Pgoal := rest.
Arguments ssr_have_let [Pgoal].
Register ssr_have as plugins.ssreflect.ssr_have.
Register ssr_have_let as plugins.ssreflect.ssr_have_let.
Definition ssr_suff Plemma Pgoal step (rest : Plemma) : Pgoal := step rest.
Arguments ssr_suff Plemma [Pgoal].
Definition ssr_wlog := ssr_suff.
Arguments ssr_wlog Plemma [Pgoal].
Register ssr_suff as plugins.ssreflect.ssr_suff.
Register ssr_wlog as plugins.ssreflect.ssr_wlog.
(** Internal N-ary congruence lemmas for the congr tactic. **)
Fixpoint nary_congruence_statement (n : nat)
: (forall B, (B -> B -> Prop) -> Prop) -> Prop :=
match n with
| O => fun k => forall B, k B (fun x1 x2 : B => x1 = x2)
| S n' =>
let k' A B e (f1 f2 : A -> B) :=
forall x1 x2, x1 = x2 -> (e (f1 x1) (f2 x2) : Prop) in
fun k => forall A, nary_congruence_statement n' (fun B e => k _ (k' A B e))
end.
Lemma nary_congruence n (k := fun B e => forall y : B, (e y y : Prop)) :
nary_congruence_statement n k.
Proof.
have: k _ _ := _; rewrite {1}/k.
elim: n k => [|n IHn] k k_P /= A; first exact: k_P.
by apply: IHn => B e He; apply: k_P => f x1 x2 <-.
Qed.
Lemma ssr_congr_arrow Plemma Pgoal : Plemma = Pgoal -> Plemma -> Pgoal.
Proof. by move->. Qed.
Arguments ssr_congr_arrow : clear implicits.
Register nary_congruence as plugins.ssreflect.nary_congruence.
Register ssr_congr_arrow as plugins.ssreflect.ssr_congr_arrow.
(** View lemmas that don't use reflection. **)
Section ApplyIff.
Variables P Q : Prop.
Hypothesis eqPQ : P <-> Q.
Lemma iffLR : P -> Q. Proof. by case: eqPQ. Qed.
Lemma iffRL : Q -> P. Proof. by case: eqPQ. Qed.
Lemma iffLRn : ~P -> ~Q. Proof. by move=> nP tQ; case: nP; case: eqPQ tQ. Qed.
Lemma iffRLn : ~Q -> ~P. Proof. by move=> nQ tP; case: nQ; case: eqPQ tP. Qed.
End ApplyIff.
Hint View for move/ iffLRn|2 iffRLn|2 iffLR|2 iffRL|2.
Hint View for apply/ iffRLn|2 iffLRn|2 iffRL|2 iffLR|2.
(**
To focus non-ssreflect tactics on a subterm, eg vm_compute.
Usage:
elim/abstract_context: (pattern) => G defG.
vm_compute; rewrite {}defG {G}.
Note that vm_cast are not stored in the proof term
for reductions occurring in the context, hence
set here := pattern; vm_compute in (value of here)
blows up at Qed time. **)
Lemma abstract_context T (P : T -> Type) x :
(forall Q, Q = P -> Q x) -> P x.
Proof. by move=> /(_ P); apply. Qed.
(*****************************************************************************)
(* Material for under/over (to rewrite under binders using "context lemmas") *)
Require Export ssrunder.
#[global]
Hint Extern 0 (@Under_rel.Over_rel _ _ _ _) =>
solve [ apply: Under_rel.over_rel_done ] : core.
#[global]
Hint Resolve Under_rel.over_rel_done : core.
Register Under_rel.Under_rel as plugins.ssreflect.Under_rel.
Register Under_rel.Under_rel_from_rel as plugins.ssreflect.Under_rel_from_rel.
(** Closing rewrite rule *)
Definition over := over_rel.
(** Closing tactic *)
Ltac over :=
by [ apply: Under_rel.under_rel_done
| rewrite over
].
(** Convenience rewrite rule to unprotect evars, e.g., to instantiate
them in another way than with reflexivity. *)
Definition UnderE := Under_relE.
(*****************************************************************************)
(** An interface for non-Prop types; used to avoid improper instantiation
of polymorphic lemmas with on-demand implicits when they are used as views.
For example: Some_inj {T} : forall x y : T, Some x = Some y -> x = y.
Using move/Some_inj on a goal of the form Some n = Some 0 will fail:
SSReflect will interpret the view as @Some_inj ?T _top_assumption_
since this is the well-typed application of the view with the minimal
number of inserted evars (taking ?T := Some n = Some 0), and then will
later complain that it cannot erase _top_assumption_ after having
abstracted the viewed assumption. Making x and y maximal implicits
would avoid this and force the intended @Some_inj nat x y _top_assumption_
interpretation, but is undesirable as it makes it harder to use Some_inj
with the many SSReflect and MathComp lemmas that have an injectivity
premise. Specifying {T : nonPropType} solves this more elegantly, as then
(?T : Type) no longer unifies with (Some n = Some 0), which has sort Prop.
**)
Module NonPropType.
(** Implementation notes:
We rely on three interface Structures:
- test_of r, the middle structure, performs the actual check: it has two
canonical instances whose 'condition' projection are maybeProj (?P : Prop)
and tt, and which set r := true and r := false, respectively. Unifying
condition (?t : test_of ?r) with maybeProj T will thus set ?r to true if
T is in Prop as the test_Prop T instance will apply, and otherwise simplify
maybeProp T to tt and use the test_negative instance and set ?r to false.
- call_of c r sets up a call to test_of on condition c with expected result r.
It has a default instance for its 'callee' projection to Type, which
sets c := maybeProj T and r := false when unifying with a type T.
- type is a telescope on call_of c r, which checks that unifying test_of ?r1
with c indeed sets ?r1 := r; the type structure bundles the 'test' instance
and its 'result' value along with its call_of c r projection. The default
instance essentially provides eta-expansion for 'type'. This is only
essential for the first 'result' projection to bool; using the instance
for other projection merely avoids spurious delta expansions that would
spoil the notProp T notation.
In detail, unifying T =~= ?S with ?S : nonPropType, i.e.,
(1) T =~= @callee (@condition (result ?S) (test ?S)) (result ?S) (frame ?S)
first uses the default call instance with ?T := T to reduce (1) to
(2a) @condition (result ?S) (test ?S) =~= maybeProp T
(3) result ?S =~= false
(4) frame ?S =~= call T
along with some trivial universe-related checks which are irrelevant here.
Then the unification tries to use the test_Prop instance to reduce (2a) to
(6a) result ?S =~= true
(7a) ?P =~= T with ?P : Prop
(8a) test ?S =~= test_Prop ?P
Now the default 'check' instance with ?result := true resolves (6a) as
(9a) ?S := @check true ?test ?frame
Then (7a) can be solved precisely if T has sort at most (hence exactly) Prop,
and then (8a) is solved by the check instance, yielding ?test := test_Prop T,
and completing the solution of (2a), and _committing_ to it. But now (3) is
inconsistent with (9a), and this makes the entire problem (1) fails.
If on the othe hand T does not have sort Prop then (7a) fails and the
unification resorts to delta expanding (2a), which gives
(2b) @condition (result ?S) (test ?S) =~= tt
which is then reduced, using the test_negative instance, to
(6b) result ?S =~= false
(8b) test ?S =~= test_negative
Both are solved using the check default instance, as in the (2a) branch, giving
(9b) ?S := @check false test_negative ?frame
Then (3) and (4) are similarly soved using check, giving the final assignment
(9) ?S := notProp T
Observe that we _must_ perform the actual test unification on the arguments
of the initial canonical instance, and not on the instance itself as we do
in mathcomp/matrix and mathcomp/vector, because we want the unification to
fail when T has sort Prop. If both the test_of _and_ the result check
unifications were done as part of the structure telescope then the latter
would be a sub-problem of the former, and thus failing the check would merely
make the test_of unification backtrack and delta-expand and we would not get
failure.
**)
Structure call_of (condition : unit) (result : bool) := Call {callee : Type}.
Definition maybeProp (T : Type) := tt.
Definition call T := Call (maybeProp T) false T.
Structure test_of (result : bool) := Test {condition :> unit}.
Definition test_Prop (P : Prop) := Test true (maybeProp P).
Definition test_negative := Test false tt.
Structure type :=
Check {result : bool; test : test_of result; frame : call_of test result}.
Definition check result test frame := @Check result test frame.
Module Exports.
Canonical call.
Canonical test_Prop.
Canonical test_negative.
Canonical check.
Notation nonPropType := type.
Coercion callee : call_of >-> Sortclass.
Coercion frame : type >-> call_of.
Notation notProp T := (@check false test_negative (call T)).
End Exports.
End NonPropType.
Export NonPropType.Exports.
Module Export ipat.
Notation "'[' 'apply' ']'" := (ltac:(let f := fresh "_top_" in move=> f {}/f))
(at level 0, only parsing) : ssripat_scope.
(* we try to preserve the naming by matching the names from the goal *)
(* we do move to perform a hnf before trying to match *)
Notation "'[' 'swap' ']'" := (ltac:(move;
let x := lazymatch goal with
| |- forall (x : _), _ => fresh x | |- let x := _ in _ => fresh x | _ => fresh "_top_"
end in intro x; move;
let y := lazymatch goal with
| |- forall (y : _), _ => fresh y | |- let y := _ in _ => fresh y | _ => fresh "_top_"
end in intro y; revert x; revert y))
(at level 0, only parsing) : ssripat_scope.
(* we try to preserve the naming by matching the names from the goal *)
(* we do move to perform a hnf before trying to match *)
Notation "'[' 'dup' ']'" := (ltac:(move;
lazymatch goal with
| |- forall (x : _), _ =>
let x := fresh x in intro x;
let copy := fresh x in have copy := x; revert x; revert copy
| |- let x := _ in _ =>
let x := fresh x in intro x;
let copy := fresh x in pose copy := x;
do [unfold x in (value of copy)]; revert x; revert copy
| |- _ =>
let x := fresh "_top_" in move=> x;
let copy := fresh "_top" in have copy := x; revert x; revert copy
end))
(at level 0, only parsing) : ssripat_scope.
End ipat.
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
pc // Program counter
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] pc; // Program counter
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_dcdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: LSU Data Cache Data Path
// - Final Way-Select Mux.
// - Alignment, Sign-Extension, Endianness.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module lsu_dcdp ( /*AUTOARG*/
// Outputs
so, dcache_rdata_wb_buf, mbist_dcache_data_in,
lsu_exu_dfill_data_w2, lsu_ffu_ld_data, stb_rdata_ramc_buf,
// Inputs
rclk, si, se, rst_tri_en, dcache_rdata_wb, dcache_rparity_wb,
dcache_rdata_msb_w0_m, dcache_rdata_msb_w1_m,
dcache_rdata_msb_w2_m, dcache_rdata_msb_w3_m, lsu_bist_rsel_way_e,
dcache_alt_mx_sel_e, cache_way_hit_buf2, morphed_addr_m,
signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m,
merge7_sel_byte0_m, merge7_sel_byte7_m, merge6_sel_byte1_m,
merge6_sel_byte6_m, merge5_sel_byte2_m, merge5_sel_byte5_m,
merge4_sel_byte3_m, merge4_sel_byte4_m, merge3_sel_byte0_m,
merge3_sel_byte3_m, merge3_sel_byte4_m,
merge3_sel_byte7_default_m, merge3_sel_byte_m, merge2_sel_byte1_m,
merge2_sel_byte2_m, merge2_sel_byte5_m,
merge2_sel_byte6_default_m, merge2_sel_byte_m, merge0_sel_byte0_m,
merge0_sel_byte1_m, merge0_sel_byte2_m,
merge0_sel_byte3_default_m, merge0_sel_byte4_m,
merge0_sel_byte5_m, merge0_sel_byte6_m,
merge0_sel_byte7_default_m, merge1_sel_byte0_m,
merge1_sel_byte1_m, merge1_sel_byte2_m,
merge1_sel_byte3_default_m, merge1_sel_byte4_m,
merge1_sel_byte5_m, merge1_sel_byte6_m,
merge1_sel_byte7_default_m, merge0_sel_byte_1h_m,
merge1_sel_byte_1h_m, merge1_sel_byte_2h_m, stb_rdata_ramc
) ;
input rclk;
input si;
input se;
output so;
input rst_tri_en;
input [63:0] dcache_rdata_wb;
output [63:0] dcache_rdata_wb_buf;
input [7:0] dcache_rparity_wb;
output [71:0] mbist_dcache_data_in;
output [63:0] lsu_exu_dfill_data_w2; // bypass data - d$ fill or hit
output [63:0] lsu_ffu_ld_data ; // ld data to frf
//=========================================
//dc_fill CP
//=========================================
input [7:0] dcache_rdata_msb_w0_m; //from D$
input [7:0] dcache_rdata_msb_w1_m; //from D$
input [7:0] dcache_rdata_msb_w2_m; //from D$
input [7:0] dcache_rdata_msb_w3_m; //from D$
input [3:0] lsu_bist_rsel_way_e; //from qdp2
input dcache_alt_mx_sel_e;
input [3:0] cache_way_hit_buf2; //from dtlb
input [7:0] morphed_addr_m; //from dctl
input signed_ldst_byte_m; //from dctl
// input unsigned_ldst_byte_m; //from dctl
input signed_ldst_hw_m; //from dctl
// input unsigned_ldst_hw_m; //from dctl
input signed_ldst_w_m; //from dctl
// input unsigned_ldst_w_m; //from dctl
input merge7_sel_byte0_m;
input merge7_sel_byte7_m;
input merge6_sel_byte1_m;
input merge6_sel_byte6_m;
input merge5_sel_byte2_m;
input merge5_sel_byte5_m;
input merge4_sel_byte3_m;
input merge4_sel_byte4_m;
input merge3_sel_byte0_m;
input merge3_sel_byte3_m;
input merge3_sel_byte4_m;
input merge3_sel_byte7_default_m;
input merge3_sel_byte_m ;
input merge2_sel_byte1_m;
input merge2_sel_byte2_m;
input merge2_sel_byte5_m;
input merge2_sel_byte6_default_m;
input merge2_sel_byte_m ;
input merge0_sel_byte0_m, merge0_sel_byte1_m;
input merge0_sel_byte2_m, merge0_sel_byte3_default_m;
input merge0_sel_byte4_m, merge0_sel_byte5_m;
input merge0_sel_byte6_m, merge0_sel_byte7_default_m;
input merge1_sel_byte0_m, merge1_sel_byte1_m;
input merge1_sel_byte2_m, merge1_sel_byte3_default_m;
input merge1_sel_byte4_m, merge1_sel_byte5_m;
input merge1_sel_byte6_m, merge1_sel_byte7_default_m;
input merge0_sel_byte_1h_m ;
input merge1_sel_byte_1h_m, merge1_sel_byte_2h_m ;
input [14:9] stb_rdata_ramc;
output [14:9] stb_rdata_ramc_buf;
//wire [3:1] lsu_byp_byte_zero_extend ; // zero-extend for bypass bytes 7-1
wire [7:1] lsu_byp_byte_sign_extend ; // sign-extend by 1 for byp bytes 7-1
wire [7:0] byte0,byte1,byte2,byte3;
wire [7:0] byte4,byte5,byte6,byte7;
//wire [3:1] zero_extend_g;
wire [7:1] sign_extend_g;
wire [7:0] align_byte3 ;
wire [7:0] align_byte2 ;
wire [7:0] align_byte1_1h,align_byte1_2h;
wire [7:0] align_byte0_1h,align_byte0_2h ;
wire [63:0] align_byte ;
wire merge7_sel_byte0;
wire merge7_sel_byte7;
wire merge6_sel_byte1;
wire merge6_sel_byte6;
wire merge5_sel_byte2;
wire merge5_sel_byte5;
wire merge4_sel_byte3;
wire merge4_sel_byte4;
wire merge3_sel_byte0;
wire merge3_sel_byte3;
wire merge3_sel_byte4;
wire merge3_sel_byte7;
wire merge3_sel_byte ;
wire merge2_sel_byte1;
wire merge2_sel_byte2;
wire merge2_sel_byte5;
wire merge2_sel_byte6;
wire merge2_sel_byte ;
wire merge0_sel_byte0, merge0_sel_byte1;
wire merge0_sel_byte2, merge0_sel_byte3;
wire merge0_sel_byte4, merge0_sel_byte5;
wire merge0_sel_byte6, merge0_sel_byte7;
wire merge1_sel_byte0, merge1_sel_byte1;
wire merge1_sel_byte2, merge1_sel_byte3;
wire merge1_sel_byte4, merge1_sel_byte5;
wire merge1_sel_byte6, merge1_sel_byte7;
wire merge0_sel_byte_1h ;
wire merge1_sel_byte_1h, merge1_sel_byte_2h ;
wire clk;
assign clk = rclk;
assign stb_rdata_ramc_buf[14:9] = stb_rdata_ramc[14:9];
//=========================================================================================
// Alignment of Fill Data
//=========================================================================================
// Alignment needs to be done for following reasons :
// - Write of data to irf on ld hit in l1.
// - Write of data to irf on ld fill to l1 after miss in l1.
// - Store of irf data to memory.
// - Data must be aligned before write to stb.
// - If data is bypassed from stb by ld then it will
// need realignment thru dfq i.e., it looks like a fill.
// This applies to data either read from the dcache (hit) or dfq(fill on miss).
assign byte7[7:0] = dcache_rdata_wb[63:56];
assign byte6[7:0] = dcache_rdata_wb[55:48];
assign byte5[7:0] = dcache_rdata_wb[47:40];
assign byte4[7:0] = dcache_rdata_wb[39:32];
assign byte3[7:0] = dcache_rdata_wb[31:24];
assign byte2[7:0] = dcache_rdata_wb[23:16];
assign byte1[7:0] = dcache_rdata_wb[15:8];
assign byte0[7:0] = dcache_rdata_wb[7:0];
//assign zero_extend_g[3:1] = lsu_byp_byte_zero_extend[3:1] ;
assign sign_extend_g[7:1] = lsu_byp_byte_sign_extend[7:1] ;
//buffer
assign dcache_rdata_wb_buf[63:0] = dcache_rdata_wb[63:0];
assign mbist_dcache_data_in[71:0] = {dcache_rdata_wb_buf[63:0], dcache_rparity_wb[7:0]};
// Final endian/justified/sign-extend Byte 0.
//assign align_byte0_1h[7:0]
// = merge0_sel_byte0 ? byte0[7:0] :
// merge0_sel_byte1 ? byte1[7:0] :
// merge0_sel_byte2 ? byte2[7:0] :
// merge0_sel_byte3 ? byte3[7:0] :
// 8'hxx ;
wire merge0_sel_byte0_mxsel0, merge0_sel_byte1_mxsel1, merge0_sel_byte2_mxsel2, merge0_sel_byte3_mxsel3;
assign merge0_sel_byte0_mxsel0 = merge0_sel_byte0 & ~rst_tri_en;
assign merge0_sel_byte1_mxsel1 = merge0_sel_byte1 & ~rst_tri_en;
assign merge0_sel_byte2_mxsel2 = merge0_sel_byte2 & ~rst_tri_en;
assign merge0_sel_byte3_mxsel3 = merge0_sel_byte3 | rst_tri_en;
mux4ds #(8) align_byte0_1h_mx (
.in0 (byte0[7:0]),
.in1 (byte1[7:0]),
.in2 (byte2[7:0]),
.in3 (byte3[7:0]),
.sel0(merge0_sel_byte0_mxsel0),
.sel1(merge0_sel_byte1_mxsel1),
.sel2(merge0_sel_byte2_mxsel2),
.sel3(merge0_sel_byte3_mxsel3),
.dout(align_byte0_1h[7:0])
);
//assign align_byte0_2h[7:0]
// = merge0_sel_byte4 ? byte4[7:0] :
// merge0_sel_byte5 ? byte5[7:0] :
// merge0_sel_byte6 ? byte6[7:0] :
// merge0_sel_byte7 ? byte7[7:0] :
// 8'hxx ;
wire merge0_sel_byte4_mxsel0, merge0_sel_byte5_mxsel1, merge0_sel_byte6_mxsel2, merge0_sel_byte7_mxsel3;
assign merge0_sel_byte4_mxsel0 = merge0_sel_byte4 & ~rst_tri_en;
assign merge0_sel_byte5_mxsel1 = merge0_sel_byte5 & ~rst_tri_en;
assign merge0_sel_byte6_mxsel2 = merge0_sel_byte6 & ~rst_tri_en;
assign merge0_sel_byte7_mxsel3 = merge0_sel_byte7 | rst_tri_en;
mux4ds #(8) align_byte0_2h_mx (
.in0 (byte4[7:0]),
.in1 (byte5[7:0]),
.in2 (byte6[7:0]),
.in3 (byte7[7:0]),
.sel0(merge0_sel_byte4_mxsel0),
.sel1(merge0_sel_byte5_mxsel1),
.sel2(merge0_sel_byte6_mxsel2),
.sel3(merge0_sel_byte7_mxsel3),
.dout(align_byte0_2h[7:0])
);
// No sign-extension or zero-extension for byte0
//assign align_byte[7:0]
// = merge0_sel_byte_1h ? align_byte0_1h[7:0] :
// align_byte0_2h[7:0] ;
assign align_byte[7:0] = merge0_sel_byte_1h ? align_byte0_1h[7:0] :
align_byte0_2h[7:0];
// Final endian/justified/sign-extend Byte 1.
// *** The path thru byte1 is the most critical ***
//assign align_byte1_1h[7:0]
// = merge1_sel_byte0 ? byte0[7:0] :
// merge1_sel_byte1 ? byte1[7:0] :
// merge1_sel_byte2 ? byte2[7:0] :
// merge1_sel_byte3 ? byte3[7:0] :
// 8'hxx ;
wire merge1_sel_byte0_mxsel0, merge1_sel_byte1_mxsel1, merge1_sel_byte2_mxsel2, merge1_sel_byte3_mxsel3;
assign merge1_sel_byte0_mxsel0 = merge1_sel_byte0 & ~rst_tri_en;
assign merge1_sel_byte1_mxsel1 = merge1_sel_byte1 & ~rst_tri_en;
assign merge1_sel_byte2_mxsel2 = merge1_sel_byte2 & ~rst_tri_en;
assign merge1_sel_byte3_mxsel3 = merge1_sel_byte3 | rst_tri_en;
mux4ds #(8) align_byte1_1h_mx (
.in0 (byte0[7:0]),
.in1 (byte1[7:0]),
.in2 (byte2[7:0]),
.in3 (byte3[7:0]),
.sel0(merge1_sel_byte0_mxsel0),
.sel1(merge1_sel_byte1_mxsel1),
.sel2(merge1_sel_byte2_mxsel2),
.sel3(merge1_sel_byte3_mxsel3),
.dout(align_byte1_1h[7:0])
);
//assign align_byte1_2h[7:0]
// = merge1_sel_byte4 ? byte4[7:0] :
// merge1_sel_byte5 ? byte5[7:0] :
// merge1_sel_byte6 ? byte6[7:0] :
// merge1_sel_byte7 ? byte7[7:0] :
// 8'hxx ;
wire merge1_sel_byte4_mxsel0, merge1_sel_byte5_mxsel1, merge1_sel_byte6_mxsel2, merge1_sel_byte7_mxsel3;
assign merge1_sel_byte4_mxsel0 = merge1_sel_byte4 & ~rst_tri_en;
assign merge1_sel_byte5_mxsel1 = merge1_sel_byte5 & ~rst_tri_en;
assign merge1_sel_byte6_mxsel2 = merge1_sel_byte6 & ~rst_tri_en;
assign merge1_sel_byte7_mxsel3 = merge1_sel_byte7 | rst_tri_en;
mux4ds #(8) align_byte1_2h_mx (
.in0 (byte4[7:0]),
.in1 (byte5[7:0]),
.in2 (byte6[7:0]),
.in3 (byte7[7:0]),
.sel0(merge1_sel_byte4_mxsel0),
.sel1(merge1_sel_byte5_mxsel1),
.sel2(merge1_sel_byte6_mxsel2),
.sel3(merge1_sel_byte7_mxsel3),
.dout(align_byte1_2h[7:0])
);
//assign align_byte[15:8] =
// zero_extend_g[1] ? 8'h00 :
// sign_extend_g[1] ? 8'hff :
// merge1_sel_byte_1h ? align_byte1_1h[7:0] :
// merge1_sel_byte_2h ? align_byte1_2h[7:0] :
// 8'hxx ;
//mux4ds #(8) align_byte1_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (align_byte1_1h[7:0]),
// .in3 (align_byte1_2h[7:0]),
// .sel0(zero_extend_g[1]),
// .sel1(sign_extend_g[1]),
// .sel2(merge1_sel_byte_1h),
// .sel3(merge1_sel_byte_2h),
// .dout(align_byte[15:8])
//);
//change to aoi from pass gate
//don't need zero_extend
assign align_byte[15:8] =
(sign_extend_g[1] ? 8'hff : 8'h00) |
(merge1_sel_byte_1h ? align_byte1_1h[7:0] : 8'h00) |
(merge1_sel_byte_2h ? align_byte1_2h[7:0] : 8'h00);
// Final endian/justified/sign-extend Byte 2.
//assign align_byte2[7:0]
// = merge2_sel_byte1 ? byte1[7:0] :
// merge2_sel_byte2 ? byte2[7:0] :
// merge2_sel_byte5 ? byte5[7:0] :
// merge2_sel_byte6 ? byte6[7:0] :
// 8'hxx ;
wire merge2_sel_byte1_mxsel0, merge2_sel_byte2_mxsel1, merge2_sel_byte5_mxsel2, merge2_sel_byte6_mxsel3;
assign merge2_sel_byte1_mxsel0 = merge2_sel_byte1 & ~rst_tri_en;
assign merge2_sel_byte2_mxsel1 = merge2_sel_byte2 & ~rst_tri_en;
assign merge2_sel_byte5_mxsel2 = merge2_sel_byte5 & ~rst_tri_en;
assign merge2_sel_byte6_mxsel3 = merge2_sel_byte6 | rst_tri_en;
mux4ds #(8) align_byte2_1st_mx (
.in0 (byte1[7:0]),
.in1 (byte2[7:0]),
.in2 (byte5[7:0]),
.in3 (byte6[7:0]),
.sel0(merge2_sel_byte1_mxsel0),
.sel1(merge2_sel_byte2_mxsel1),
.sel2(merge2_sel_byte5_mxsel2),
.sel3(merge2_sel_byte6_mxsel3),
.dout(align_byte2[7:0])
);
//assign align_byte[23:16] =
// zero_extend_g[2] ? 8'h00 :
// sign_extend_g[2] ? 8'hff :
// merge2_sel_byte ? align_byte2[7:0] :
// 8'hxx ;
//mux3ds #(8) align_byte2_2nd_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (align_byte2[7:0]),
// .sel0(zero_extend_g[2]),
// .sel1(sign_extend_g[2]),
// .sel2(merge2_sel_byte),
// .dout(align_byte[23:16])
// );
assign align_byte[23:16] =
( sign_extend_g[2] ? 8'hff : 8'h00) |
( merge2_sel_byte ? align_byte2[7:0] : 8'h00);
// Final endian/justified/sign-extend Byte 3.
//assign align_byte3[7:0]
// = merge3_sel_byte0 ? byte0[7:0] :
// merge3_sel_byte3 ? byte3[7:0] :
// merge3_sel_byte4 ? byte4[7:0] :
// merge3_sel_byte7 ? byte7[7:0] :
// 8'hxx ;
wire merge3_sel_byte0_mxsel0, merge3_sel_byte3_mxsel1, merge3_sel_byte4_mxsel2, merge3_sel_byte7_mxsel3;
assign merge3_sel_byte0_mxsel0 = merge3_sel_byte0 & ~rst_tri_en;
assign merge3_sel_byte3_mxsel1 = merge3_sel_byte3 & ~rst_tri_en;
assign merge3_sel_byte4_mxsel2 = merge3_sel_byte4 & ~rst_tri_en;
assign merge3_sel_byte7_mxsel3 = merge3_sel_byte7 | rst_tri_en;
mux4ds #(8) align_byte3_1st_mx (
.in0 (byte0[7:0]),
.in1 (byte3[7:0]),
.in2 (byte4[7:0]),
.in3 (byte7[7:0]),
.sel0(merge3_sel_byte0_mxsel0),
.sel1(merge3_sel_byte3_mxsel1),
.sel2(merge3_sel_byte4_mxsel2),
.sel3(merge3_sel_byte7_mxsel3),
.dout(align_byte3[7:0])
);
//assign align_byte[31:24] =
// zero_extend_g[3] ? 8'h00 :
// sign_extend_g[3] ? 8'hff :
// merge3_sel_byte ? align_byte3[7:0] :
// 8'hxx ;
//mux3ds #(8) align_byte3_2nd_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (align_byte3[7:0]),
// .sel0(zero_extend_g[3]),
// .sel1(sign_extend_g[3]),
// .sel2(merge3_sel_byte),
// .dout(align_byte[31:24])
// );
assign align_byte[31:24] =
(sign_extend_g[3] ? 8'hff : 8'h00 ) |
(merge3_sel_byte ? align_byte3[7:0] : 8'h00);
// Final endian/justified/sign-extend Byte 4.
//assign align_byte[39:32]
// = zero_extend_g[4] ? 8'h00 :
// sign_extend_g[4] ? 8'hff :
// merge4_sel_byte3 ? byte3[7:0] :
// merge4_sel_byte4 ? byte4[7:0] :
// 8'hxx;
//mux4ds #(8) align_byte4_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (byte3[7:0]),
// .in3 (byte4[7:0]),
// .sel0(zero_extend_g[4]),
// .sel1(sign_extend_g[4]),
// .sel2(merge4_sel_byte3),
// .sel3(merge4_sel_byte4),
// .dout(align_byte[39:32])
// );
assign align_byte[39:32] =
(sign_extend_g[4] ? 8'hff : 8'h00) |
(merge4_sel_byte3 ? byte3[7:0] : 8'h00) |
(merge4_sel_byte4 ? byte4[7:0] : 8'h00);
// Final endian/justified/sign-extend Byte 5.
//assign align_byte[47:40]
// = zero_extend_g[5] ? 8'h00 :
// sign_extend_g[5] ? 8'hff :
// merge5_sel_byte2 ? byte2[7:0] :
// merge5_sel_byte5 ? byte5[7:0] :
// 8'hxx ;
//mux4ds #(8) align_byte5_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (byte2[7:0]),
// .in3 (byte5[7:0]),
// .sel0(zero_extend_g[5]),
// .sel1(sign_extend_g[5]),
// .sel2(merge5_sel_byte2),
// .sel3(merge5_sel_byte5),
// .dout(align_byte[47:40])
// );
assign align_byte[47:40] =
(sign_extend_g[5] ? 8'hff : 8'h00) |
(merge5_sel_byte2 ? byte2[7:0] : 8'h00) |
(merge5_sel_byte5 ? byte5[7:0] : 8'h00);
// Final endian/justified/sign-extend Byte 6.
//assign align_byte[55:48]
// = zero_extend_g[6] ? 8'h00 :
// sign_extend_g[6] ? 8'hff :
// merge6_sel_byte1 ? byte1[7:0] :
// merge6_sel_byte6 ? byte6[7:0] :
// 8'hxx ;
//mux4ds #(8) align_byte6_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (byte1[7:0]),
// .in3 (byte6[7:0]),
// .sel0(zero_extend_g[6]),
// .sel1(sign_extend_g[6]),
// .sel2(merge6_sel_byte1),
// .sel3(merge6_sel_byte6),
// .dout(align_byte[55:48])
// );
assign align_byte[55:48] =
(sign_extend_g[6] ? 8'hff : 8'h00) |
(merge6_sel_byte1 ? byte1[7:0] : 8'h00) |
(merge6_sel_byte6 ? byte6[7:0] : 8'h00);
// Final endian/justified/sign-extend Byte 7.
//assign align_byte[63:56] =
// zero_extend_g[7] ? 8'h00 :
// sign_extend_g[7] ? 8'hff :
// merge7_sel_byte0 ? byte0[7:0] :
// merge7_sel_byte7 ? byte7[7:0] :
// 8'hxx ;
//mux4ds #(8) align_byte7_mx (
// .in0 (8'h00),
// .in1 (8'hff),
// .in2 (byte0[7:0]),
// .in3 (byte7[7:0]),
// .sel0(zero_extend_g[7]),
// .sel1(sign_extend_g[7]),
// .sel2(merge7_sel_byte0),
// .sel3(merge7_sel_byte7),
// .dout(align_byte[63:56])
// );
assign align_byte[63:56] =
(sign_extend_g[7] ? 8'hff : 8'h00 ) |
(merge7_sel_byte0 ? byte0[7:0] : 8'h00) |
(merge7_sel_byte7 ? byte7[7:0] : 8'h00);
//====================================================
//dc_fill CP sign/zero control signals
//====================================================
wire [7:0] ld_data_msb_w0_m;
wire [7:0] ld_data_msb_w1_m;
wire [7:0] ld_data_msb_w2_m;
wire [7:0] ld_data_msb_w3_m;
wire [7:0] ld_data_msb_w0_g;
wire [7:0] ld_data_msb_w1_g;
wire [7:0] ld_data_msb_w2_g;
wire [7:0] ld_data_msb_w3_g;
assign ld_data_msb_w0_m[7:0] = dcache_rdata_msb_w0_m[7:0];
assign ld_data_msb_w1_m[7:0] = dcache_rdata_msb_w1_m[7:0];
assign ld_data_msb_w2_m[7:0] = dcache_rdata_msb_w2_m[7:0];
assign ld_data_msb_w3_m[7:0] = dcache_rdata_msb_w3_m[7:0];
dff_s #(32) ld_data_msb_stgg (
.din ({ld_data_msb_w0_m[7:0], ld_data_msb_w1_m[7:0], ld_data_msb_w2_m[7:0], ld_data_msb_w3_m[7:0]}),
.q ({ld_data_msb_w0_g[7:0], ld_data_msb_w1_g[7:0], ld_data_msb_w2_g[7:0], ld_data_msb_w3_g[7:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [3:0] dcache_alt_rsel_way_m;
wire dcache_alt_mx_sel_m;
dff_s #(5) dcache_alt_stgm (
.din ({lsu_bist_rsel_way_e[3:0], dcache_alt_mx_sel_e}),
.q ({dcache_alt_rsel_way_m[3:0], dcache_alt_mx_sel_m}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [3:0] dcache_alt_rsel_way_g;
wire dcache_alt_mx_sel_g;
dff_s #(5) dcache_alt_stgg (
.din ({dcache_alt_rsel_way_m[3:0], dcache_alt_mx_sel_m}),
.q ({dcache_alt_rsel_way_g[3:0], dcache_alt_mx_sel_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [3:0] cache_way_mx_sel;
assign cache_way_mx_sel [3:0] = dcache_alt_mx_sel_g ? dcache_alt_rsel_way_g[3:0] : cache_way_hit_buf2[3:0];
// wire [7:0] align_bytes_msb;
//mux4ds #(8) align_bytes_msb_mux (
// .in0 (ld_data_msb_w0_g[7:0]),
// .in1 (ld_data_msb_w1_g[7:0]),
// .in2 (ld_data_msb_w2_g[7:0]),
// .in3 (ld_data_msb_w3_g[7:0]),
// .sel0 (cache_way_mx_sel[0]),
// .sel1 (cache_way_mx_sel[1]),
// .sel2 (cache_way_mx_sel[2]),
// .sel3 (cache_way_mx_sel[3]),
// .dout (align_bytes_msb[7:0])
//);
wire signed_ldst_byte_g;
wire signed_ldst_hw_g;
wire signed_ldst_w_g;
dff_s #(3) ldst_size_stgg(
.din ({signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m}),
.q ({signed_ldst_byte_g, signed_ldst_hw_g, signed_ldst_w_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [7:0] morphed_addr_g;
dff_s #(8) stgg_morphadd(
.din (morphed_addr_m[7:0]),
.q (morphed_addr_g[7:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire sign_bit_w0_g, sign_bit_w1_g, sign_bit_w2_g, sign_bit_w3_g;
assign sign_bit_w0_g =
(morphed_addr_g[0] & ld_data_msb_w0_g[7]) |
(morphed_addr_g[1] & ld_data_msb_w0_g[6]) |
(morphed_addr_g[2] & ld_data_msb_w0_g[5]) |
(morphed_addr_g[3] & ld_data_msb_w0_g[4]) |
(morphed_addr_g[4] & ld_data_msb_w0_g[3]) |
(morphed_addr_g[5] & ld_data_msb_w0_g[2]) |
(morphed_addr_g[6] & ld_data_msb_w0_g[1]) |
(morphed_addr_g[7] & ld_data_msb_w0_g[0]) ;
assign sign_bit_w1_g =
(morphed_addr_g[0] & ld_data_msb_w1_g[7]) |
(morphed_addr_g[1] & ld_data_msb_w1_g[6]) |
(morphed_addr_g[2] & ld_data_msb_w1_g[5]) |
(morphed_addr_g[3] & ld_data_msb_w1_g[4]) |
(morphed_addr_g[4] & ld_data_msb_w1_g[3]) |
(morphed_addr_g[5] & ld_data_msb_w1_g[2]) |
(morphed_addr_g[6] & ld_data_msb_w1_g[1]) |
(morphed_addr_g[7] & ld_data_msb_w1_g[0]) ;
assign sign_bit_w2_g =
(morphed_addr_g[0] & ld_data_msb_w2_g[7]) |
(morphed_addr_g[1] & ld_data_msb_w2_g[6]) |
(morphed_addr_g[2] & ld_data_msb_w2_g[5]) |
(morphed_addr_g[3] & ld_data_msb_w2_g[4]) |
(morphed_addr_g[4] & ld_data_msb_w2_g[3]) |
(morphed_addr_g[5] & ld_data_msb_w2_g[2]) |
(morphed_addr_g[6] & ld_data_msb_w2_g[1]) |
(morphed_addr_g[7] & ld_data_msb_w2_g[0]) ;
assign sign_bit_w3_g =
(morphed_addr_g[0] & ld_data_msb_w3_g[7]) |
(morphed_addr_g[1] & ld_data_msb_w3_g[6]) |
(morphed_addr_g[2] & ld_data_msb_w3_g[5]) |
(morphed_addr_g[3] & ld_data_msb_w3_g[4]) |
(morphed_addr_g[4] & ld_data_msb_w3_g[3]) |
(morphed_addr_g[5] & ld_data_msb_w3_g[2]) |
(morphed_addr_g[6] & ld_data_msb_w3_g[1]) |
(morphed_addr_g[7] & ld_data_msb_w3_g[0]) ;
//assign sign_bit_g =
// (morphed_addr_g[0] & align_bytes_msb[7]) |
// (morphed_addr_g[1] & align_bytes_msb[6]) |
// (morphed_addr_g[2] & align_bytes_msb[5]) |
// (morphed_addr_g[3] & align_bytes_msb[4]) |
// (morphed_addr_g[4] & align_bytes_msb[3]) |
// (morphed_addr_g[5] & align_bytes_msb[2]) |
// (morphed_addr_g[6] & align_bytes_msb[1]) |
// (morphed_addr_g[7] & align_bytes_msb[0]) ;
//dff #(4) ssign_bit_stgg (
// .din ({sign_bit_w0_m, sign_bit_w1_m, sign_bit_w2_m, sign_bit_w3_m}),
// .q ({sign_bit_w0_g, sign_bit_w1_g, sign_bit_w2_g, sign_bit_w3_g}),
// .clk (clk),
// .se (se), .si (), .so ()
// );
// byte0 never requires sign or zero extension.
//w0
// wire [3:1] lsu_byp_byte_zero_extend_w0;
wire [7:1] lsu_byp_byte_sign_extend_w0;
//assign lsu_byp_byte_zero_extend_w0[1] =
// unsigned_ldst_byte_g | (signed_ldst_byte_g & ~sign_bit_w0_g);
assign lsu_byp_byte_sign_extend_w0[1] =
signed_ldst_byte_g & sign_bit_w0_g;
//assign lsu_byp_byte_zero_extend_w0[2] =
// unsigned_ldst_hw_g | (signed_ldst_hw_g & ~sign_bit_w0_g);
assign lsu_byp_byte_sign_extend_w0[2] =
signed_ldst_hw_g & sign_bit_w0_g;
//assign lsu_byp_byte_zero_extend_w0[3] =
// lsu_byp_byte_zero_extend_w0[2] ;
assign lsu_byp_byte_sign_extend_w0[3] =
lsu_byp_byte_sign_extend_w0[2] ;
//assign lsu_byp_byte_zero_extend_w0[4] =
// unsigned_ldst_w_g | (signed_ldst_w_g & ~sign_bit_w0_g);
assign lsu_byp_byte_sign_extend_w0[4] =
signed_ldst_w_g & sign_bit_w0_g;
//assign lsu_byp_byte_zero_extend_w0[5] =
// lsu_byp_byte_zero_extend_w0[4] ;
assign lsu_byp_byte_sign_extend_w0[5] =
lsu_byp_byte_sign_extend_w0[4] ;
//assign lsu_byp_byte_zero_extend_w0[6] =
// lsu_byp_byte_zero_extend_w0[4] ;
assign lsu_byp_byte_sign_extend_w0[6] =
lsu_byp_byte_sign_extend_w0[4] ;
//assign lsu_byp_byte_zero_extend_w0[7] =
// lsu_byp_byte_zero_extend_w0[4] ;
assign lsu_byp_byte_sign_extend_w0[7] =
lsu_byp_byte_sign_extend_w0[4] ;
//w1
// wire [3:1] lsu_byp_byte_zero_extend_w1;
wire [7:1] lsu_byp_byte_sign_extend_w1;
//assign lsu_byp_byte_zero_extend_w1[1] =
// unsigned_ldst_byte_g | (signed_ldst_byte_g & ~sign_bit_w1_g);
assign lsu_byp_byte_sign_extend_w1[1] =
signed_ldst_byte_g & sign_bit_w1_g;
//assign lsu_byp_byte_zero_extend_w1[2] =
// unsigned_ldst_hw_g | (signed_ldst_hw_g & ~sign_bit_w1_g);
assign lsu_byp_byte_sign_extend_w1[2] =
signed_ldst_hw_g & sign_bit_w1_g;
//assign lsu_byp_byte_zero_extend_w1[3] =
// lsu_byp_byte_zero_extend_w1[2] ;
assign lsu_byp_byte_sign_extend_w1[3] =
lsu_byp_byte_sign_extend_w1[2] ;
//assign lsu_byp_byte_zero_extend_w1[4] =
// unsigned_ldst_w_g | (signed_ldst_w_g & ~sign_bit_w1_g);
assign lsu_byp_byte_sign_extend_w1[4] =
signed_ldst_w_g & sign_bit_w1_g;
//assign lsu_byp_byte_zero_extend_w1[5] =
// lsu_byp_byte_zero_extend_w1[4] ;
assign lsu_byp_byte_sign_extend_w1[5] =
lsu_byp_byte_sign_extend_w1[4] ;
//assign lsu_byp_byte_zero_extend_w1[6] =
// lsu_byp_byte_zero_extend_w1[4] ;
assign lsu_byp_byte_sign_extend_w1[6] =
lsu_byp_byte_sign_extend_w1[4] ;
//assign lsu_byp_byte_zero_extend_w1[7] =
// lsu_byp_byte_zero_extend_w1[4] ;
assign lsu_byp_byte_sign_extend_w1[7] =
lsu_byp_byte_sign_extend_w1[4] ;
//w2
// wire [3:1] lsu_byp_byte_zero_extend_w2;
wire [7:1] lsu_byp_byte_sign_extend_w2;
//assign lsu_byp_byte_zero_extend_w2[1] =
// unsigned_ldst_byte_g | (signed_ldst_byte_g & ~sign_bit_w2_g);
assign lsu_byp_byte_sign_extend_w2[1] =
signed_ldst_byte_g & sign_bit_w2_g;
//assign lsu_byp_byte_zero_extend_w2[2] =
// unsigned_ldst_hw_g | (signed_ldst_hw_g & ~sign_bit_w2_g);
assign lsu_byp_byte_sign_extend_w2[2] =
signed_ldst_hw_g & sign_bit_w2_g;
//assign lsu_byp_byte_zero_extend_w2[3] =
// lsu_byp_byte_zero_extend_w2[2] ;
assign lsu_byp_byte_sign_extend_w2[3] =
lsu_byp_byte_sign_extend_w2[2] ;
//assign lsu_byp_byte_zero_extend_w2[4] =
// unsigned_ldst_w_g | (signed_ldst_w_g & ~sign_bit_w2_g);
assign lsu_byp_byte_sign_extend_w2[4] =
signed_ldst_w_g & sign_bit_w2_g;
//assign lsu_byp_byte_zero_extend_w2[5] =
// lsu_byp_byte_zero_extend_w2[4] ;
assign lsu_byp_byte_sign_extend_w2[5] =
lsu_byp_byte_sign_extend_w2[4] ;
//assign lsu_byp_byte_zero_extend_w2[6] =
// lsu_byp_byte_zero_extend_w2[4] ;
assign lsu_byp_byte_sign_extend_w2[6] =
lsu_byp_byte_sign_extend_w2[4] ;
//assign lsu_byp_byte_zero_extend_w2[7] =
// lsu_byp_byte_zero_extend_w2[4] ;
assign lsu_byp_byte_sign_extend_w2[7] =
lsu_byp_byte_sign_extend_w2[4] ;
//w3
// wire [3:1] lsu_byp_byte_zero_extend_w3;
wire [7:1] lsu_byp_byte_sign_extend_w3;
//assign lsu_byp_byte_zero_extend_w3[1] =
// unsigned_ldst_byte_g | (signed_ldst_byte_g & ~sign_bit_w3_g);
assign lsu_byp_byte_sign_extend_w3[1] =
signed_ldst_byte_g & sign_bit_w3_g;
//assign lsu_byp_byte_zero_extend_w3[2] =
// unsigned_ldst_hw_g | (signed_ldst_hw_g & ~sign_bit_w3_g);
assign lsu_byp_byte_sign_extend_w3[2] =
signed_ldst_hw_g & sign_bit_w3_g;
//assign lsu_byp_byte_zero_extend_w3[3] =
// lsu_byp_byte_zero_extend_w3[2] ;
assign lsu_byp_byte_sign_extend_w3[3] =
lsu_byp_byte_sign_extend_w3[2] ;
//assign lsu_byp_byte_zero_extend_w3[4] =
// unsigned_ldst_w_g | (signed_ldst_w_g & ~sign_bit_w3_g);
assign lsu_byp_byte_sign_extend_w3[4] =
signed_ldst_w_g & sign_bit_w3_g;
//assign lsu_byp_byte_zero_extend_w3[5] =
// lsu_byp_byte_zero_extend_w3[4] ;
assign lsu_byp_byte_sign_extend_w3[5] =
lsu_byp_byte_sign_extend_w3[4] ;
//assign lsu_byp_byte_zero_extend_w3[6] =
// lsu_byp_byte_zero_extend_w3[4] ;
assign lsu_byp_byte_sign_extend_w3[6] =
lsu_byp_byte_sign_extend_w3[4] ;
//assign lsu_byp_byte_zero_extend_w3[7] =
// lsu_byp_byte_zero_extend_w3[4] ;
assign lsu_byp_byte_sign_extend_w3[7] =
lsu_byp_byte_sign_extend_w3[4] ;
//mux4ds #(14) zero_sign_sel_mux (
// .in0 ({lsu_byp_byte_zero_extend_w0[7:1],lsu_byp_byte_sign_extend_w0[7:1]}),
// .in1 ({lsu_byp_byte_zero_extend_w1[7:1],lsu_byp_byte_sign_extend_w1[7:1]}),
// .in2 ({lsu_byp_byte_zero_extend_w2[7:1],lsu_byp_byte_sign_extend_w2[7:1]}),
// .in3 ({lsu_byp_byte_zero_extend_w3[7:1],lsu_byp_byte_sign_extend_w3[7:1]}),
// .sel0 (cache_way_mx_sel[0]),
// .sel1 (cache_way_mx_sel[1]),
// .sel2 (cache_way_mx_sel[2]),
// .sel3 (cache_way_mx_sel[3]),
// .dout ({lsu_byp_byte_zero_extend[7:1],lsu_byp_byte_sign_extend[7:1]})
//);
//assign lsu_byp_byte_zero_extend[3:1] =
// (cache_way_mx_sel[0] ? lsu_byp_byte_zero_extend_w0[3:1] : 3'b0 ) |
// (cache_way_mx_sel[1] ? lsu_byp_byte_zero_extend_w1[3:1] : 3'b0 ) |
// (cache_way_mx_sel[2] ? lsu_byp_byte_zero_extend_w2[3:1] : 3'b0 ) |
// (cache_way_mx_sel[3] ? lsu_byp_byte_zero_extend_w3[3:1] : 3'b0 ) ;
assign lsu_byp_byte_sign_extend[7:1] =
(cache_way_mx_sel[0] ? lsu_byp_byte_sign_extend_w0[7:1] : 7'b0) |
(cache_way_mx_sel[1] ? lsu_byp_byte_sign_extend_w1[7:1] : 7'b0) |
(cache_way_mx_sel[2] ? lsu_byp_byte_sign_extend_w2[7:1] : 7'b0) |
(cache_way_mx_sel[3] ? lsu_byp_byte_sign_extend_w3[7:1] : 7'b0) ;
dff_s #(37) stgg_mergesel(
.din ({
merge7_sel_byte0_m, merge7_sel_byte7_m,
merge6_sel_byte1_m, merge6_sel_byte6_m,
merge5_sel_byte2_m, merge5_sel_byte5_m,
merge4_sel_byte3_m, merge4_sel_byte4_m,
merge3_sel_byte0_m, merge3_sel_byte3_m,
merge3_sel_byte4_m, merge3_sel_byte7_default_m, merge3_sel_byte_m,
merge2_sel_byte1_m, merge2_sel_byte2_m, merge2_sel_byte5_m,
merge2_sel_byte6_default_m, merge2_sel_byte_m,
merge0_sel_byte0_m, merge0_sel_byte1_m,
merge0_sel_byte2_m, merge0_sel_byte3_default_m,
merge0_sel_byte4_m, merge0_sel_byte5_m,
merge0_sel_byte6_m, merge0_sel_byte7_default_m,
merge1_sel_byte0_m, merge1_sel_byte1_m,
merge1_sel_byte2_m, merge1_sel_byte3_default_m,
merge1_sel_byte4_m, merge1_sel_byte5_m,
merge1_sel_byte6_m, merge1_sel_byte7_default_m,
merge0_sel_byte_1h_m,merge1_sel_byte_1h_m, merge1_sel_byte_2h_m
}),
.q ({
merge7_sel_byte0, merge7_sel_byte7,
merge6_sel_byte1, merge6_sel_byte6,
merge5_sel_byte2, merge5_sel_byte5,
merge4_sel_byte3, merge4_sel_byte4,
merge3_sel_byte0, merge3_sel_byte3,
merge3_sel_byte4, merge3_sel_byte7,merge3_sel_byte,
merge2_sel_byte1, merge2_sel_byte2, merge2_sel_byte5,
merge2_sel_byte6, merge2_sel_byte,
merge0_sel_byte0, merge0_sel_byte1,
merge0_sel_byte2, merge0_sel_byte3,
merge0_sel_byte4, merge0_sel_byte5,
merge0_sel_byte6, merge0_sel_byte7,
merge1_sel_byte0, merge1_sel_byte1,
merge1_sel_byte2, merge1_sel_byte3,
merge1_sel_byte4, merge1_sel_byte5,
merge1_sel_byte6, merge1_sel_byte7,
merge0_sel_byte_1h,merge1_sel_byte_1h, merge1_sel_byte_2h
}),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_exu_dfill_data_w2[63:0] = align_byte[63:0] ;
assign lsu_ffu_ld_data[63:0] = align_byte[63:0] ;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History: 1.2 11/8/2010 Removed unused signals.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
wire COutb,COutd;
reg COuta,COutc;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
{COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
{COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// calculate how many buf still available
//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr;
assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// bug823
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [6:0] in = crc[6:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mask; // From test of Test.v
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
.mask (mask[3:0]),
// Inputs
.clk (clk),
.in (in[6:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out & mask};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e9d3a74e9d3f656
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, mask,
// Inputs
clk, in
);
input clk;
input [6:0] in; // Note much wider than any index
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);
mask[1] <= ((15 + in - 5) < 14);
mask[0] <= ((15 + in - 5) < 15);
end
endmodule
|
// Check assignment operations in constant functions.
module constfunc7();
function real i_to_r(input signed [3:0] value);
i_to_r = value + 0.5;
endfunction
function signed [3:0] r_to_i(input real value);
r_to_i = value;
endfunction
function real u_to_r(input [3:0] value);
u_to_r = value + 0.5;
endfunction
function [3:0] r_to_u(input real value);
r_to_u = value;
endfunction
function [3:0] i_to_u(input signed [3:0] value);
i_to_u = value;
endfunction
function signed [3:0] u_to_i(input [3:0] value);
u_to_i = value;
endfunction
function [5:0] si_to_lu(input signed [3:0] value);
si_to_lu = value;
endfunction
function signed [5:0] su_to_li(input [3:0] value);
su_to_li = value;
endfunction
function [3:0] li_to_su(input signed [5:0] value);
li_to_su = value;
endfunction
function signed [3:0] lu_to_si(input [5:0] value);
lu_to_si = value;
endfunction
localparam i_to_r_res1 = i_to_r(-9);
localparam i_to_r_res2 = i_to_r(-8);
localparam i_to_r_res3 = i_to_r( 7);
localparam i_to_r_res4 = i_to_r( 8);
localparam r_to_i_res1 = r_to_i(-8.5);
localparam r_to_i_res2 = r_to_i(-7.5);
localparam r_to_i_res3 = r_to_i( 6.5);
localparam r_to_i_res4 = r_to_i( 7.5);
localparam u_to_r_res1 = u_to_r(-1);
localparam u_to_r_res2 = u_to_r( 1);
localparam u_to_r_res3 = u_to_r(15);
localparam u_to_r_res4 = u_to_r(17);
localparam r_to_u_res1 = r_to_u(-0.5);
localparam r_to_u_res2 = r_to_u( 0.5);
localparam r_to_u_res3 = r_to_u(14.5);
localparam r_to_u_res4 = r_to_u(16.5);
localparam i_to_u_res1 = i_to_u(-9);
localparam i_to_u_res2 = i_to_u(-8);
localparam i_to_u_res3 = i_to_u( 7);
localparam i_to_u_res4 = i_to_u( 8);
localparam u_to_i_res1 = u_to_i(-1);
localparam u_to_i_res2 = u_to_i( 1);
localparam u_to_i_res3 = u_to_i(15);
localparam u_to_i_res4 = u_to_i(17);
localparam si_to_lu_res1 = si_to_lu(-9);
localparam si_to_lu_res2 = si_to_lu(-8);
localparam si_to_lu_res3 = si_to_lu( 7);
localparam si_to_lu_res4 = si_to_lu( 8);
localparam su_to_li_res1 = su_to_li(-1);
localparam su_to_li_res2 = su_to_li( 1);
localparam su_to_li_res3 = su_to_li(15);
localparam su_to_li_res4 = su_to_li(17);
localparam li_to_su_res1 = li_to_su(-9);
localparam li_to_su_res2 = li_to_su(-8);
localparam li_to_su_res3 = li_to_su( 7);
localparam li_to_su_res4 = li_to_su( 8);
localparam lu_to_si_res1 = lu_to_si(-1);
localparam lu_to_si_res2 = lu_to_si( 1);
localparam lu_to_si_res3 = lu_to_si(15);
localparam lu_to_si_res4 = lu_to_si(17);
reg failed;
initial begin
failed = 0;
$display("%0g", i_to_r_res1); if (i_to_r_res1 != 7.5) failed = 1;
$display("%0g", i_to_r_res2); if (i_to_r_res2 != -7.5) failed = 1;
$display("%0g", i_to_r_res3); if (i_to_r_res3 != 7.5) failed = 1;
$display("%0g", i_to_r_res4); if (i_to_r_res4 != -7.5) failed = 1;
$display("");
$display("%0d", r_to_i_res1); if (r_to_i_res1 !== 7) failed = 1;
$display("%0d", r_to_i_res2); if (r_to_i_res2 !== -8) failed = 1;
$display("%0d", r_to_i_res3); if (r_to_i_res3 !== 7) failed = 1;
$display("%0d", r_to_i_res4); if (r_to_i_res4 !== -8) failed = 1;
$display("");
$display("%0g", u_to_r_res1); if (u_to_r_res1 != 15.5) failed = 1;
$display("%0g", u_to_r_res2); if (u_to_r_res2 != 1.5) failed = 1;
$display("%0g", u_to_r_res3); if (u_to_r_res3 != 15.5) failed = 1;
$display("%0g", u_to_r_res4); if (u_to_r_res4 != 1.5) failed = 1;
$display("");
$display("%0d", r_to_u_res1); if (r_to_u_res1 !== 15) failed = 1;
$display("%0d", r_to_u_res2); if (r_to_u_res2 !== 1) failed = 1;
$display("%0d", r_to_u_res3); if (r_to_u_res3 !== 15) failed = 1;
$display("%0d", r_to_u_res4); if (r_to_u_res4 !== 1) failed = 1;
$display("");
$display("%0d", i_to_u_res1); if (i_to_u_res1 !== 7) failed = 1;
$display("%0d", i_to_u_res2); if (i_to_u_res2 !== 8) failed = 1;
$display("%0d", i_to_u_res3); if (i_to_u_res3 !== 7) failed = 1;
$display("%0d", i_to_u_res4); if (i_to_u_res4 !== 8) failed = 1;
$display("");
$display("%0d", u_to_i_res1); if (u_to_i_res1 !== -1) failed = 1;
$display("%0d", u_to_i_res2); if (u_to_i_res2 !== 1) failed = 1;
$display("%0d", u_to_i_res3); if (u_to_i_res3 !== -1) failed = 1;
$display("%0d", u_to_i_res4); if (u_to_i_res4 !== 1) failed = 1;
$display("");
$display("%0d", si_to_lu_res1); if (si_to_lu_res1 !== 7) failed = 1;
$display("%0d", si_to_lu_res2); if (si_to_lu_res2 !== 56) failed = 1;
$display("%0d", si_to_lu_res3); if (si_to_lu_res3 !== 7) failed = 1;
$display("%0d", si_to_lu_res4); if (si_to_lu_res4 !== 56) failed = 1;
$display("");
$display("%0d", su_to_li_res1); if (su_to_li_res1 !== 15) failed = 1;
$display("%0d", su_to_li_res2); if (su_to_li_res2 !== 1) failed = 1;
$display("%0d", su_to_li_res3); if (su_to_li_res3 !== 15) failed = 1;
$display("%0d", su_to_li_res4); if (su_to_li_res4 !== 1) failed = 1;
$display("");
$display("%0d", li_to_su_res1); if (li_to_su_res1 !== 7) failed = 1;
$display("%0d", li_to_su_res2); if (li_to_su_res2 !== 8) failed = 1;
$display("%0d", li_to_su_res3); if (li_to_su_res3 !== 7) failed = 1;
$display("%0d", li_to_su_res4); if (li_to_su_res4 !== 8) failed = 1;
$display("");
$display("%0d", lu_to_si_res1); if (lu_to_si_res1 !== -1) failed = 1;
$display("%0d", lu_to_si_res2); if (lu_to_si_res2 !== 1) failed = 1;
$display("%0d", lu_to_si_res3); if (lu_to_si_res3 !== -1) failed = 1;
$display("%0d", lu_to_si_res4); if (lu_to_si_res4 !== 1) failed = 1;
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_decoder.v
// Title : Instruction decoder
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Support for static branch prediction. Information about
// : branch type is generated and passed on to the predictor.
// Version : 3.2
// : No change
// Version : 3.3
// : Renamed port names that conflict with keywords reserved
// : in System-Verilog.
// =============================================================================
`include "lm32_include.v"
// Index of opcode field in an instruction
`define LM32_OPCODE_RNG 31:26
`define LM32_OP_RNG 30:26
// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
`define LM32_OPCODE_ADD 5'b01101
`define LM32_OPCODE_AND 5'b01000
`define LM32_OPCODE_ANDHI 6'b011000
`define LM32_OPCODE_B 6'b110000
`define LM32_OPCODE_BI 6'b111000
`define LM32_OPCODE_BE 6'b010001
`define LM32_OPCODE_BG 6'b010010
`define LM32_OPCODE_BGE 6'b010011
`define LM32_OPCODE_BGEU 6'b010100
`define LM32_OPCODE_BGU 6'b010101
`define LM32_OPCODE_BNE 6'b010111
`define LM32_OPCODE_CALL 6'b110110
`define LM32_OPCODE_CALLI 6'b111110
`define LM32_OPCODE_CMPE 5'b11001
`define LM32_OPCODE_CMPG 5'b11010
`define LM32_OPCODE_CMPGE 5'b11011
`define LM32_OPCODE_CMPGEU 5'b11100
`define LM32_OPCODE_CMPGU 5'b11101
`define LM32_OPCODE_CMPNE 5'b11111
`define LM32_OPCODE_DIVU 6'b100011
`define LM32_OPCODE_LB 6'b000100
`define LM32_OPCODE_LBU 6'b010000
`define LM32_OPCODE_LH 6'b000111
`define LM32_OPCODE_LHU 6'b001011
`define LM32_OPCODE_LW 6'b001010
`define LM32_OPCODE_MODU 6'b110001
`define LM32_OPCODE_MUL 5'b00010
`define LM32_OPCODE_NOR 5'b00001
`define LM32_OPCODE_OR 5'b01110
`define LM32_OPCODE_ORHI 6'b011110
`define LM32_OPCODE_RAISE 6'b101011
`define LM32_OPCODE_RCSR 6'b100100
`define LM32_OPCODE_SB 6'b001100
`define LM32_OPCODE_SEXTB 6'b101100
`define LM32_OPCODE_SEXTH 6'b110111
`define LM32_OPCODE_SH 6'b000011
`define LM32_OPCODE_SL 5'b01111
`define LM32_OPCODE_SR 5'b00101
`define LM32_OPCODE_SRU 5'b00000
`define LM32_OPCODE_SUB 6'b110010
`define LM32_OPCODE_SW 6'b010110
`define LM32_OPCODE_USER 6'b110011
`define LM32_OPCODE_WCSR 6'b110100
`define LM32_OPCODE_XNOR 5'b01001
`define LM32_OPCODE_XOR 5'b00110
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_decoder (
// ----- Inputs -------
instruction,
// ----- Outputs -------
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith,
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift,
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext,
`endif
x_result_sel_logic,
`ifdef CFG_USER_ENABLED
x_result_sel_user,
`endif
x_result_sel_add,
m_result_sel_compare,
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift,
`endif
w_result_sel_load,
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul,
`endif
x_bypass_enable,
m_bypass_enable,
read_enable_0,
read_idx_0,
read_enable_1,
read_idx_1,
write_enable,
write_idx,
immediate,
branch_offset,
load,
store,
size,
sign_extend,
adder_op,
logic_op,
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction,
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
shift_left,
shift_right,
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
multiply,
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
divide,
modulus,
`endif
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
`ifdef CFG_DEBUG_ENABLED
break_opcode,
`endif
scall,
eret,
`ifdef CFG_DEBUG_ENABLED
bret,
`endif
`ifdef CFG_USER_ENABLED
user_opcode,
`endif
csr_write_enable
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
`ifdef LM32_MC_ARITHMETIC_ENABLED
output x_result_sel_mc_arith;
reg x_result_sel_mc_arith;
`endif
`ifdef LM32_NO_BARREL_SHIFT
output x_result_sel_shift;
reg x_result_sel_shift;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
output x_result_sel_sext;
reg x_result_sel_sext;
`endif
output x_result_sel_logic;
reg x_result_sel_logic;
`ifdef CFG_USER_ENABLED
output x_result_sel_user;
reg x_result_sel_user;
`endif
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
output m_result_sel_shift;
reg m_result_sel_shift;
`endif
output w_result_sel_load;
reg w_result_sel_load;
`ifdef CFG_PL_MULTIPLY_ENABLED
output w_result_sel_mul;
reg w_result_sel_mul;
`endif
output x_bypass_enable;
wire x_bypass_enable;
output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
output [`LM32_REG_IDX_RNG] read_idx_0;
wire [`LM32_REG_IDX_RNG] read_idx_0;
output read_enable_1;
wire read_enable_1;
output [`LM32_REG_IDX_RNG] read_idx_1;
wire [`LM32_REG_IDX_RNG] read_idx_1;
output write_enable;
wire write_enable;
output [`LM32_REG_IDX_RNG] write_idx;
wire [`LM32_REG_IDX_RNG] write_idx;
output [`LM32_WORD_RNG] immediate;
wire [`LM32_WORD_RNG] immediate;
output [`LM32_PC_RNG] branch_offset;
wire [`LM32_PC_RNG] branch_offset;
output load;
wire load;
output store;
wire store;
output [`LM32_SIZE_RNG] size;
wire [`LM32_SIZE_RNG] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
output [`LM32_LOGIC_OP_RNG] logic_op;
wire [`LM32_LOGIC_OP_RNG] logic_op;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
output direction;
wire direction;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
output shift_left;
wire shift_left;
output shift_right;
wire shift_right;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
output multiply;
wire multiply;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
output divide;
wire divide;
output modulus;
wire modulus;
`endif
output branch;
wire branch;
output branch_reg;
wire branch_reg;
output [`LM32_CONDITION_RNG] condition;
wire [`LM32_CONDITION_RNG] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
`ifdef CFG_DEBUG_ENABLED
output break_opcode;
wire break_opcode;
`endif
output scall;
wire scall;
output eret;
wire eret;
`ifdef CFG_DEBUG_ENABLED
output bret;
wire bret;
`endif
`ifdef CFG_USER_ENABLED
output [`LM32_USER_OPCODE_RNG] user_opcode;
wire [`LM32_USER_OPCODE_RNG] user_opcode;
`endif
output csr_write_enable;
wire csr_write_enable;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits
wire [`LM32_WORD_RNG] call_immediate; // Call immediate
wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
wire select_high_immediate; // Whether to select the high immediate
wire select_call_immediate; // Whether to select the call immediate
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Determine opcode
assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
`ifdef CFG_MC_DIVIDE_ENABLED
assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
`endif
assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
`ifdef CFG_MC_DIVIDE_ENABLED
assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
`endif
`ifdef LM32_MULTIPLY_ENABLED
assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
`endif
assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
`ifdef CFG_SIGN_EXTEND_ENABLED
assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
`endif
assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
`ifdef LM32_BARREL_SHIFT_ENABLED
assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;
`endif
assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
// Group opcodes by function
assign arith = op_add | op_sub;
assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
`ifdef LM32_BARREL_SHIFT_ENABLED
assign shift = op_sl | op_sr | op_sru;
`endif
`ifdef LM32_NO_BARREL_SHIFT
assign shift = op_sr | op_sru;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
assign shift_left = op_sl;
assign shift_right = op_sr | op_sru;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
assign sext = op_sextb | op_sexth;
`endif
`ifdef LM32_MULTIPLY_ENABLED
assign multiply = op_mul;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
assign divide = op_divu;
assign modulus = op_modu;
`endif
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
// Select pipeline multiplexor controls
always @(*)
begin
// D stage
if (call)
d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
else
d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
if (call)
d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;
else if ((instruction[31] == 1'b0) && !bra)
d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
else
d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1;
// X stage
x_result_sel_csr = `FALSE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith = `FALSE;
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift = `FALSE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext = `FALSE;
`endif
x_result_sel_logic = `FALSE;
`ifdef CFG_USER_ENABLED
x_result_sel_user = `FALSE;
`endif
x_result_sel_add = `FALSE;
if (op_rcsr)
x_result_sel_csr = `TRUE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
else if (shift_left | shift_right)
x_result_sel_mc_arith = `TRUE;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
else if (divide | modulus)
x_result_sel_mc_arith = `TRUE;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
else if (multiply)
x_result_sel_mc_arith = `TRUE;
`endif
`endif
`ifdef LM32_NO_BARREL_SHIFT
else if (shift)
x_result_sel_shift = `TRUE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
else if (sext)
x_result_sel_sext = `TRUE;
`endif
else if (logical)
x_result_sel_logic = `TRUE;
`ifdef CFG_USER_ENABLED
else if (op_user)
x_result_sel_user = `TRUE;
`endif
else
x_result_sel_add = `TRUE;
// M stage
m_result_sel_compare = cmp;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift = shift;
`endif
// W stage
w_result_sel_load = load;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul = op_mul;
`endif
end
// Set if result is valid at end of X stage
assign x_bypass_enable = arith
| logical
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
| shift_left
| shift_right
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
| multiply
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
| divide
| modulus
`endif
`ifdef LM32_NO_BARREL_SHIFT
| shift
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
| sext
`endif
`ifdef CFG_USER_ENABLED
| op_user
`endif
| op_rcsr
;
// Set if result is valid at end of M stage
assign m_bypass_enable = x_bypass_enable
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
| shift
`endif
| cmp
;
// Register file read port 0
assign read_enable_0 = ~(op_bi | op_calli);
assign read_idx_0 = instruction[25:21];
// Register file read port 1
assign read_enable_1 = ~(op_bi | op_calli | load);
assign read_idx_1 = instruction[20:16];
// Register file write port
assign write_enable = ~(bra | op_raise | store | op_wcsr);
assign write_idx = call
? 5'd29
: instruction[31] == 1'b0
? instruction[20:16]
: instruction[15:11];
// Size of load/stores
assign size = instruction[27:26];
// Whether to sign or zero extend
assign sign_extend = instruction[28];
// Set adder_op to 1 to perform a subtraction
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
// Logic operation (and, or, etc)
assign logic_op = instruction[29:26];
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
// Shift direction
assign direction = instruction[29];
`endif
// Control flow microcodes
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
`ifdef CFG_DEBUG_ENABLED
assign break_opcode = op_raise & ~instruction[2];
`endif
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
`ifdef CFG_DEBUG_ENABLED
assign bret = op_b & (instruction[25:21] == 5'd31);
`endif
`ifdef CFG_USER_ENABLED
// Extract user opcode
assign user_opcode = instruction[10:0];
`endif
// CSR read/write
assign csr_write_enable = op_wcsr;
// Extract immediate from instruction
assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
assign select_high_immediate = op_andhi | op_orhi;
assign select_call_immediate = instruction[31];
assign high_immediate = {instruction[15:0], 16'h0000};
assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
assign immediate = select_high_immediate == `TRUE
? high_immediate
: extended_immediate;
assign branch_offset = select_call_immediate == `TRUE
? call_immediate
: branch_immediate;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Mat2AXIvideo (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n,
img_data_stream_0_V_read,
img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n,
img_data_stream_1_V_read,
img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n,
img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter ap_ST_st5_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv13_1FFF = 13'b1111111111111;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
input [7:0] img_data_stream_0_V_dout;
input img_data_stream_0_V_empty_n;
output img_data_stream_0_V_read;
input [7:0] img_data_stream_1_V_dout;
input img_data_stream_1_V_empty_n;
output img_data_stream_1_V_read;
input [7:0] img_data_stream_2_V_dout;
input img_data_stream_2_V_empty_n;
output img_data_stream_2_V_read;
output [31:0] OUTPUT_STREAM_TDATA;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [0:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [0:0] OUTPUT_STREAM_TID;
output [0:0] OUTPUT_STREAM_TDEST;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_data_stream_0_V_read;
reg img_data_stream_1_V_read;
reg img_data_stream_2_V_read;
reg OUTPUT_STREAM_TVALID;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm = 4'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_23;
reg [11:0] p_3_reg_170;
reg ap_sig_bdd_60;
wire [12:0] op2_assign_fu_186_p2;
reg [12:0] op2_assign_reg_267;
wire [0:0] exitcond3_fu_197_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_74;
wire [11:0] i_V_fu_202_p2;
reg [11:0] i_V_reg_276;
wire [0:0] exitcond4_fu_208_p2;
reg [0:0] exitcond4_reg_281;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_85;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_sig_bdd_99;
reg ap_sig_ioackin_OUTPUT_STREAM_TREADY;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
wire [11:0] j_V_fu_213_p2;
wire [0:0] axi_last_V_fu_223_p2;
reg [0:0] axi_last_V_reg_290;
reg [11:0] p_s_reg_159;
reg ap_sig_cseq_ST_st5_fsm_3;
reg ap_sig_bdd_130;
reg [0:0] tmp_user_V_fu_96;
reg ap_reg_ioackin_OUTPUT_STREAM_TREADY = 1'b0;
wire [12:0] tmp_cast_fu_182_p1;
wire [12:0] tmp_cast_38_fu_219_p1;
reg [3:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_OUTPUT_STREAM_TREADY
if (ap_rst == 1'b1) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_99 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_logic_1 == OUTPUT_STREAM_TREADY))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
p_3_reg_170 <= j_V_fu_213_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
p_3_reg_170 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_3)) begin
p_s_reg_159 <= i_V_reg_276;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
p_s_reg_159 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
tmp_user_V_fu_96 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
tmp_user_V_fu_96 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
axi_last_V_reg_290 <= axi_last_V_fu_223_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond4_reg_281 <= exitcond4_fu_208_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
i_V_reg_276 <= i_V_fu_202_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
op2_assign_reg_267 <= op2_assign_fu_186_p2;
end
end
/// OUTPUT_STREAM_TVALID assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_reg_ppiten_pp0_it1 or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_99 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY))) begin
OUTPUT_STREAM_TVALID = ap_const_logic_1;
end else begin
OUTPUT_STREAM_TVALID = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond3_fu_197_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond3_fu_197_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_3 assign process. ///
always @ (ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (OUTPUT_STREAM_TREADY or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY)) begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
end else begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = ap_const_logic_1;
end
end
/// img_data_stream_0_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_0_V_read = ap_const_logic_1;
end else begin
img_data_stream_0_V_read = ap_const_logic_0;
end
end
/// img_data_stream_1_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_1_V_read = ap_const_logic_1;
end else begin
img_data_stream_1_V_read = ap_const_logic_0;
end
end
/// img_data_stream_2_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_2_V_read = ap_const_logic_1;
end else begin
img_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_60 or exitcond3_fu_197_p2 or exitcond4_fu_208_p2 or exitcond4_reg_281 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_60) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(exitcond3_fu_197_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_st5_fsm_3 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign OUTPUT_STREAM_TDATA = {{{{{{ap_const_lv8_FF}, {img_data_stream_2_V_dout}}}, {img_data_stream_1_V_dout}}}, {img_data_stream_0_V_dout}};
assign OUTPUT_STREAM_TDEST = ap_const_lv1_0;
assign OUTPUT_STREAM_TID = ap_const_lv1_0;
assign OUTPUT_STREAM_TKEEP = ap_const_lv4_F;
assign OUTPUT_STREAM_TLAST = axi_last_V_reg_290;
assign OUTPUT_STREAM_TSTRB = ap_const_lv4_0;
assign OUTPUT_STREAM_TUSER = tmp_user_V_fu_96;
/// ap_sig_bdd_130 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_130 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_23 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_23 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_60 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_60 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_74 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_74 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_85 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_85 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_99 assign process. ///
always @ (img_data_stream_0_V_empty_n or img_data_stream_1_V_empty_n or img_data_stream_2_V_empty_n or exitcond4_reg_281)
begin
ap_sig_bdd_99 = (((img_data_stream_0_V_empty_n == ap_const_logic_0) & (exitcond4_reg_281 == ap_const_lv1_0)) | ((exitcond4_reg_281 == ap_const_lv1_0) & (img_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond4_reg_281 == ap_const_lv1_0) & (img_data_stream_2_V_empty_n == ap_const_logic_0)));
end
assign axi_last_V_fu_223_p2 = (tmp_cast_38_fu_219_p1 == op2_assign_reg_267? 1'b1: 1'b0);
assign exitcond3_fu_197_p2 = (p_s_reg_159 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond4_fu_208_p2 = (p_3_reg_170 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_202_p2 = (p_s_reg_159 + ap_const_lv12_1);
assign j_V_fu_213_p2 = (p_3_reg_170 + ap_const_lv12_1);
assign op2_assign_fu_186_p2 = ($signed(tmp_cast_fu_182_p1) + $signed(ap_const_lv13_1FFF));
assign tmp_cast_38_fu_219_p1 = p_3_reg_170;
assign tmp_cast_fu_182_p1 = img_cols_V_read;
endmodule //image_filter_Mat2AXIvideo
|
//----------------------------------------------------------------------------
module machine( inc_pc, load_acc, load_pc, rd,wr, load_ir,
datactl_ena, halt, clk1, zero, ena, opcode );
output inc_pc, load_acc, load_pc, rd, wr, load_ir;
output datactl_ena, halt;
input clk1, zero, ena;
input [2:0] opcode;
reg inc_pc, load_acc, load_pc, rd, wr, load_ir;
reg datactl_ena, halt;
reg [2:0] state;
parameter HLT = 3 'b000,
SKZ = 3 'b001,
ADD = 3 'b010,
ANDD = 3 'b011,
XORR = 3 'b100,
LDA = 3 'b101,
STO = 3 'b110,
JMP = 3 'b111;
always @( negedge clk1 )
begin
if ( !ena ) //???????RST???????
begin
state<=3'b000;
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
ctl_cycle;
end
//-----------------begin of task ctl_cycle---------
task ctl_cycle;
begin
casex(state)
3'b000: //load high 8bits in struction
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0001;
{wr,load_ir,datactl_ena,halt}<=4'b0100;
state<=3'b001;
end
3'b001: //pc increased by one then load low 8bits instruction
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1001;
{wr,load_ir,datactl_ena,halt}<=4'b0100;
state<=3'b010;
end
3'b010: //idle
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
state<=3'b011;
end
3'b011: //next instruction address setup ?????????
begin
if(opcode==HLT) //?????HLT
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0001;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b100;
end
3'b100: //fetch oprand
begin
if(opcode==JMP)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0010;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if( opcode==ADD || opcode==ANDD ||
opcode==XORR || opcode==LDA)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0001;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if(opcode==STO)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0010;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b101;
end
3'b101: //operation
begin
if ( opcode==ADD||opcode==ANDD||
opcode==XORR||opcode==LDA )
begin //?????????????????
{inc_pc,load_acc,load_pc,rd}<=4'b0101;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if( opcode==SKZ && zero==1)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if(opcode==JMP)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1010;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
if(opcode==STO)
begin
//???????wr?1????RAM?
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b1010;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b110;
end
3'b110: //idle
begin
if ( opcode==STO )
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0010;
end
else
if ( opcode==ADD||opcode==ANDD||
opcode==XORR||opcode==LDA)
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0001;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b111;
end
3'b111: //
begin
if( opcode==SKZ && zero==1 )
begin
{inc_pc,load_acc,load_pc,rd}<=4'b1000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
else
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
end
state<=3'b000;
end
default:
begin
{inc_pc,load_acc,load_pc,rd}<=4'b0000;
{wr,load_ir,datactl_ena,halt}<=4'b0000;
state<=3'b000;
end
endcase
end
endtask
//-----------------end of task ctl_cycle---------
endmodule
//------------------------------------------------------------------------------
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: timer.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $
*/
module timer(output wire rdy, input wire clk, input wire reset);
reg [4:0] count;
assign rdy = count[4];
always @(posedge clk or posedge reset)
if (reset)
count <= 5'h0f;
else
count <= count - 1;
endmodule // timer
|
//altera message_off 10230 10762 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_sideband
# (parameter
// parameters
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2, //2-FR,4-HR,8-QR
CFG_REG_GRANT = 1,
CFG_CTL_TBP_NUM = 4,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_BA_WIDTH = 3,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_MEM_IF_CLK_PAIR_COUNT = 2,
CFG_RANK_TIMER_OUTPUT_REG = 0,
T_PARAM_ARF_TO_VALID_WIDTH = 10,
T_PARAM_ARF_PERIOD_WIDTH = 13,
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 10,
T_PARAM_SRF_TO_VALID_WIDTH = 10,
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10,
T_PARAM_PDN_TO_VALID_WIDTH = 6,
T_PARAM_PDN_PERIOD_WIDTH = 16,
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6,
T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH = 4,
BANK_TIMER_COUNTER_OFFSET = 2 //used to be 4
)
(
ctl_clk,
ctl_reset_n,
// local interface
rfsh_req,
rfsh_chip,
rfsh_ack,
self_rfsh_req,
self_rfsh_chip,
self_rfsh_ack,
deep_powerdn_req,
deep_powerdn_chip,
deep_powerdn_ack,
power_down_ack,
// sideband output
stall_row_arbiter,
stall_col_arbiter,
stall_chip,
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
sb_tbp_precharge_all,
// PHY interface
ctl_mem_clk_disable,
ctl_cal_req,
ctl_init_req,
ctl_cal_success,
// tbp & cmd gen
cmd_gen_chipsel,
tbp_chipsel,
tbp_load,
// timing
t_param_arf_to_valid,
t_param_arf_period,
t_param_pch_all_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_pdn_to_valid,
t_param_pdn_period,
t_param_power_saving_exit,
t_param_mem_clk_entry_cycles,
// block status
tbp_empty,
tbp_bank_closed,
tbp_timer_ready,
row_grant,
col_grant,
// dqs tracking
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
// config ports
cfg_cs_addr_width,
cfg_enable_dqs_tracking,
cfg_user_rfsh,
cfg_type,
cfg_tcl,
cfg_regdimm_enable,
// ZQ Calibration
zqcal_req,
// to refresh controller
sideband_in_refresh
);
// states for "sideband_state" state machine
localparam IDLE_S1 = 3'b000;
localparam ARF = 3'b001;
localparam PDN = 3'b010;
localparam SRF = 3'b100;
// states for "disable_clk_state" state machine
localparam IDLE_S2 = 2'b00;
localparam DISABLECLK1 = 2'b01;
localparam DISABLECLK2 = 2'b10;
// states for "state" state machine
localparam IDLE_S3 = 9'b000000000;
localparam INIT = 9'b000000001;
localparam PCHALL = 9'b000000010;
localparam REFRESH = 9'b000000100;
localparam PDOWN = 9'b000001000;
localparam SELFRFSH = 9'b000010000;
localparam DEEPPDN = 9'b000100000;
localparam INITREQ = 9'b001000000;
localparam ZQCAL = 9'b010000000;
localparam DQSTRK = 9'b100000000;
localparam POWER_SAVING_COUNTER_WIDTH = T_PARAM_SRF_TO_VALID_WIDTH;
localparam POWER_SAVING_EXIT_COUNTER_WIDTH = T_PARAM_POWER_SAVING_EXIT_WIDTH;
localparam DISABLE_CLK_COUNTER_WIDTH = T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH;
localparam ARF_COUNTER_WIDTH = T_PARAM_ARF_PERIOD_WIDTH;
localparam PDN_COUNTER_WIDTH = T_PARAM_PDN_PERIOD_WIDTH;
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2 ** CFG_MEM_IF_BA_WIDTH;
localparam integer CFG_PORT_WIDTH_TCL_SQRD = 2 ** CFG_PORT_WIDTH_TCL;
localparam SAMPLE_EVERY_N_RFSH = 0; //Valid values are 0-7
input ctl_clk;
input ctl_reset_n;
input rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output rfsh_ack;
input self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
output self_rfsh_ack;
input deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output deep_powerdn_ack;
output power_down_ack;
output stall_row_arbiter;
output stall_col_arbiter;
output [CFG_MEM_IF_CHIP-1:0] stall_chip;
output [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
output [CFG_MEM_IF_CHIP-1:0] sb_do_refresh;
output [CFG_MEM_IF_CHIP-1:0] sb_do_self_refresh;
output [CFG_MEM_IF_CHIP-1:0] sb_do_power_down;
output [CFG_MEM_IF_CHIP-1:0] sb_do_deep_pdown;
output [CFG_MEM_IF_CHIP-1:0] sb_do_zq_cal;
output [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
output [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
output ctl_cal_req;
output ctl_init_req;
input ctl_cal_success;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [T_PARAM_ARF_TO_VALID_WIDTH-1:0] t_param_arf_to_valid;
input [T_PARAM_ARF_PERIOD_WIDTH-1:0] t_param_arf_period;
input [T_PARAM_PCH_ALL_TO_VALID_WIDTH-1:0] t_param_pch_all_to_valid;
input [T_PARAM_SRF_TO_VALID_WIDTH-1:0] t_param_srf_to_valid;
input [T_PARAM_SRF_TO_ZQ_CAL_WIDTH-1:0] t_param_srf_to_zq_cal;
input [T_PARAM_PDN_TO_VALID_WIDTH-1:0] t_param_pdn_to_valid;
input [T_PARAM_PDN_PERIOD_WIDTH-1:0] t_param_pdn_period;
input [T_PARAM_POWER_SAVING_EXIT_WIDTH-1:0] t_param_power_saving_exit;
input [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH-1:0] t_param_mem_clk_entry_cycles;
input tbp_empty;
input [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
input [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
input row_grant;
input col_grant;
output [CFG_MEM_IF_CHIP-1:0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP-1:0] afi_seq_busy;
output [CFG_MEM_IF_CHIP-1:0] afi_ctl_long_idle;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
input cfg_enable_dqs_tracking;
input cfg_user_rfsh;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input cfg_regdimm_enable;
input zqcal_req;
output [CFG_MEM_IF_CHIP-1:0] sideband_in_refresh;
// end of port declaration
wire self_rfsh_ack;
wire deep_powerdn_ack;
wire power_down_ack;
wire [CFG_MEM_IF_CLK_PAIR_COUNT-1:0] ctl_mem_clk_disable;
wire ctl_cal_req;
wire ctl_init_req;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_refresh;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_self_refresh;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] sb_do_zq_cal;
reg [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] do_refresh;
reg [CFG_MEM_IF_CHIP-1:0] do_power_down;
reg [CFG_MEM_IF_CHIP-1:0] do_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
reg [CFG_MEM_IF_CHIP-1:0] do_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] stall_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_stall_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_stall_chip_combi;
reg [CFG_MEM_IF_CHIP-1:0] stall_arbiter;
reg [CFG_MEM_IF_CHIP-1:0] afi_ctl_refresh_done;
wire [CFG_MEM_IF_CHIP-1:0] afi_ctl_long_idle;
reg [CFG_MEM_IF_CHIP-1:0] dqstrk_exit;
reg [CFG_MEM_IF_CHIP-1:0] doing_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] init_req;
reg [CFG_MEM_IF_CHIP-1:0] disable_clk;
reg [CFG_MEM_IF_CHIP-1:0] int_init_req;
reg [CFG_MEM_IF_CHIP-1:0] int_disable_clk;
reg refresh_req;
reg [CFG_MEM_IF_CHIP-1:0] refresh_chip_req;
reg [CFG_MEM_IF_CHIP-1:0] self_refresh_chip_req;
reg self_rfsh_req_r;
reg [CFG_MEM_IF_CHIP-1:0] deep_pdown_chip_req;
reg [CFG_MEM_IF_CHIP-1:0] power_down_chip_req;
wire [CFG_MEM_IF_CHIP-1:0] power_down_chip_req_combi;
wire [CFG_MEM_IF_CHIP-1:0] all_banks_closed;
wire [CFG_MEM_IF_CHIP-1:0] tcom_not_running;
reg [CFG_PORT_WIDTH_TCL_SQRD-1:0] tcom_not_running_pipe [CFG_MEM_IF_CHIP-1:0];
reg [CFG_MEM_IF_CHIP-1:0] can_refresh;
reg [CFG_MEM_IF_CHIP-1:0] can_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] can_deep_pdown;
reg [CFG_MEM_IF_CHIP-1:0] can_power_down;
reg [CFG_MEM_IF_CHIP-1:0] can_exit_power_saving_mode;
reg [CFG_MEM_IF_CHIP-1:0] cs_refresh_req;
wire grant;
wire [CFG_MEM_IF_CHIP-1:0] cs_zq_cal_req;
wire [CFG_MEM_IF_CHIP-1:0] power_saving_enter_ready;
wire [CFG_MEM_IF_CHIP-1:0] power_saving_exit_ready;
reg [PDN_COUNTER_WIDTH - 1 : 0] power_down_cnt;
reg no_command_r1;
reg [CFG_MEM_IF_CHIP-1:0] afi_seq_busy_r; // synchronizer
reg [CFG_MEM_IF_CHIP-1:0] afi_seq_busy_r2; // synchronizer
//new! to avoid contention
reg [CFG_MEM_IF_CHIP-1:0] do_refresh_req;
reg refresh_req_ack;
reg dummy_do_refresh;
reg dummy_do_refresh_r;
reg do_refresh_r;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_req;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_req_r1;
reg [CFG_MEM_IF_CHIP-1:0] do_self_rfsh_req_r2;
reg self_rfsh_req_ack;
reg dummy_do_self_rfsh;
reg [CFG_MEM_IF_CHIP-1:0] do_zqcal_req;
reg zqcal_req_ack;
reg dummy_do_zqcal;
reg [CFG_MEM_IF_CHIP-1:0] do_pch_all_req;
reg pch_all_req_ack;
reg dummy_do_pch_all;
reg do_refresh_to_all_chip;
reg do_refresh_to_all_chip_r;
reg do_self_refresh_to_all_chip;
reg do_self_refresh_to_all_chip_r;
reg do_zqcal_to_all_chip;
reg do_zqcal_to_all_chip_r;
reg [CFG_MEM_IF_CHIP-1:0] sideband_in_refresh;
reg [2:0] trk_rfsh_cntr [CFG_MEM_IF_CHIP-1:0];
integer i;
assign ctl_mem_clk_disable = {CFG_MEM_IF_CLK_PAIR_COUNT{&int_disable_clk}};
assign ctl_cal_req = &int_init_req;
assign ctl_init_req = 1'b0;
assign afi_ctl_long_idle = {CFG_MEM_IF_CHIP{1'b0}};
//generate *_chip_ok signals by checking can_*[chip], only when for_chip[chip] is 1
generate
genvar chip;
for (chip = 0; chip < CFG_MEM_IF_CHIP; chip = chip + 1)
begin : gen_chip_ok
// check can_* only for chips that we'd like to precharge_all to, ^~ is XNOR
assign tcom_not_running[chip] = tbp_timer_ready[chip];
assign all_banks_closed[chip] = tbp_bank_closed[chip];
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
tcom_not_running_pipe[chip] <= 0;
end
else
begin
if (!tcom_not_running[chip])
begin
tcom_not_running_pipe[chip] <= 0;
end
else
begin
tcom_not_running_pipe[chip] <= {tcom_not_running_pipe[chip][CFG_PORT_WIDTH_TCL_SQRD -2 :0],tcom_not_running[chip]};
end
end
end
// Generate per chip init_req and disable_clk
// to be used in MMR case where they actually use smaller CS than the actual design
// example: 2 CS design, but user only use 1 CS in MMR mode
always @ (*)
begin
if (chip < (2 ** cfg_cs_addr_width))
begin
int_init_req [chip] = init_req [chip];
int_disable_clk[chip] = disable_clk[chip];
end
else
begin
int_init_req [chip] = 1'b1;
int_disable_clk[chip] = 1'b1;
end
end
end
endgenerate
assign rfsh_ack = (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) ? |do_refresh : ((|do_refresh | do_refresh_r) & refresh_req_ack);
assign self_rfsh_ack = |do_self_rfsh;
assign deep_powerdn_ack = |do_deep_pdown;
assign power_down_ack = |do_power_down;
// Register sideband signals when CFG_REG_GRANT is '1'
// to prevent sideband request going out on the same cycle as tbp request
generate
begin
genvar j;
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_do_precharge_all <= 0;
sb_do_refresh <= 0;
sb_do_self_refresh <= 0;
sb_do_power_down <= 0;
sb_do_deep_pdown <= 0;
sb_do_zq_cal <= 0;
end
else
begin
sb_do_precharge_all <= do_precharge_all;
sb_do_refresh <= do_refresh;
sb_do_self_refresh <= do_self_rfsh;
sb_do_power_down <= do_power_down;
sb_do_deep_pdown <= do_deep_pdown;
sb_do_zq_cal <= do_zqcal;
end
end
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin : tbp_loop_1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sb_tbp_precharge_all [j] <= 1'b0;
end
else
begin
if (tbp_load[j])
begin
sb_tbp_precharge_all [j] <= do_precharge_all [cmd_gen_chipsel];
end
else
begin
sb_tbp_precharge_all [j] <= do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
end
end
end
end
end
else
begin
always @ (*)
begin
sb_do_precharge_all = do_precharge_all;
sb_do_refresh = do_refresh;
sb_do_self_refresh = do_self_rfsh;
sb_do_power_down = do_power_down;
sb_do_deep_pdown = do_deep_pdown;
sb_do_zq_cal = do_zqcal;
end
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin : tbp_loop_2
always @ (*)
begin
sb_tbp_precharge_all [j] = do_precharge_all [tbp_chipsel [(j + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j * CFG_MEM_IF_CS_WIDTH]];
end
end
end
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_req_ack <= 0;
zqcal_req_ack <= 0;
pch_all_req_ack <= 0;
self_rfsh_req_ack <= 0;
dummy_do_refresh_r <= dummy_do_refresh;
do_refresh_r <= 0;
end
else
begin
refresh_req_ack <= dummy_do_refresh;
zqcal_req_ack <= dummy_do_zqcal;
pch_all_req_ack <= dummy_do_pch_all;
self_rfsh_req_ack <= dummy_do_self_rfsh;
dummy_do_refresh_r <= dummy_do_refresh;
if (dummy_do_refresh && !dummy_do_refresh_r)
begin
do_refresh_r <= |do_refresh;
end
else
begin
do_refresh_r <= 0;
end
end
end
always @(*)
begin
i = 0;
dummy_do_refresh = 0;
dummy_do_pch_all = 0;
dummy_do_zqcal = 0;
if (|do_pch_all_req)
begin
do_refresh = 0;
do_zqcal = 0;
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
begin
do_precharge_all = do_pch_all_req;
end
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_precharge_all [i] = do_pch_all_req[i];
dummy_do_pch_all = |do_pch_all_req;
end
else if (i%2 == 1 && pch_all_req_ack)
begin
do_precharge_all [i] = do_pch_all_req[i];
end
else
begin
do_precharge_all [i] = 0;
end
end
end
end
else if (|do_refresh_req)
begin
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1)) // if not (regdimm and DDR3), normal refresh
begin
do_refresh = do_refresh_req;
end
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_refresh [i] = do_refresh_req [i];
if (&refresh_chip_req) // refresh to all chips in REGDIMM
begin
dummy_do_refresh = &do_refresh_req;
end
else
begin
dummy_do_refresh = |do_refresh_req;
end
end
else if (i%2 == 1 && refresh_req_ack)
begin
do_refresh [i] = do_refresh_req [i];
end
else
begin
do_refresh [i] = 0;
end
end
end
do_precharge_all = 0;
do_zqcal = 0;
end
else if (|do_zqcal_req)
begin
do_refresh = 0;
do_precharge_all = 0;
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
begin
do_zqcal = do_zqcal_req;
end
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_zqcal [i] = do_zqcal_req[i];
dummy_do_zqcal = |do_zqcal_req;
end
else if (i%2 == 1 && zqcal_req_ack)
begin
do_zqcal [i] = do_zqcal_req[i];
end
else
begin
do_zqcal [i] = 0;
end
end
end
end
else
begin
do_refresh = 0;
dummy_do_refresh = 0;
do_precharge_all = 0;
dummy_do_pch_all = 0;
do_zqcal = 0;
dummy_do_zqcal = 0;
end
end
always @(*)
begin
i = 0;
dummy_do_self_rfsh = 1'b0;
if (|do_refresh_req || |do_precharge_all || |do_zqcal_req)
begin
if (|do_self_rfsh_r)
begin
do_self_rfsh = do_self_rfsh_req;
dummy_do_self_rfsh = 1'b1;
end
else
begin
do_self_rfsh = 0;
end
end
else
begin
if (!(cfg_regdimm_enable && cfg_type == `MMR_TYPE_DDR3 && CFG_MEM_IF_CHIP != 1))
begin
do_self_rfsh = do_self_rfsh_req;
end
else
begin
for (i = 0;i < CFG_MEM_IF_CHIP;i = i + 1)
begin
if (i%2 == 0)
begin
do_self_rfsh [i] = do_self_rfsh_req[i];
dummy_do_self_rfsh = |do_self_rfsh_req;
end
else if (i%2 == 1 && self_rfsh_req_ack)
begin
do_self_rfsh [i] = do_self_rfsh_req[i];
end
else
begin
do_self_rfsh [i] = 0;
end
end
end
end
end
always @ (*)
begin
do_refresh_to_all_chip = &do_refresh_req;
do_self_refresh_to_all_chip = &do_self_rfsh_req;
do_zqcal_to_all_chip = &do_zqcal_req;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_self_rfsh_req_r1 <= 0;
do_self_rfsh_req_r2 <= 0;
do_refresh_to_all_chip_r <= 1'b0;
do_self_refresh_to_all_chip_r <= 1'b0;
do_zqcal_to_all_chip_r <= 1'b0;
end
else
begin
do_self_rfsh_req_r1 <= do_self_rfsh_req;
do_self_rfsh_req_r2 <= do_self_rfsh_req_r1;
do_refresh_to_all_chip_r <= do_refresh_to_all_chip;
do_self_refresh_to_all_chip_r <= do_self_refresh_to_all_chip;
do_zqcal_to_all_chip_r <= do_zqcal_to_all_chip;
end
end
assign stall_row_arbiter = |stall_arbiter;
assign stall_col_arbiter = |stall_arbiter;
assign grant = (CFG_REG_GRANT == 1) ? (row_grant | col_grant) : 1'b0;
//register self_rfsh_req and deep_powerdn_req
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
self_refresh_chip_req <= 0;
deep_pdown_chip_req <= 0;
self_rfsh_req_r <= 0;
do_self_rfsh_r <= 0;
end
else
begin
if (self_rfsh_req)
begin
self_refresh_chip_req <= self_rfsh_chip;
end
else
begin
self_refresh_chip_req <= 0;
end
self_rfsh_req_r <= self_rfsh_req & |self_rfsh_chip;
do_self_rfsh_r <= do_self_rfsh;
if (deep_powerdn_req)
begin
deep_pdown_chip_req <= deep_powerdn_chip;
end
else
begin
deep_pdown_chip_req <= 0;
end
end
end
//combi user refresh
always @(*)
begin
if (cfg_user_rfsh)
begin
if (rfsh_req)
begin
refresh_req = 1'b1;
refresh_chip_req = rfsh_chip;
end
else
begin
refresh_req = 1'b0;
refresh_chip_req = 0;
end
end
else
begin
refresh_req = |cs_refresh_req;
refresh_chip_req = cs_refresh_req;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_seq_busy_r <= 0;
afi_seq_busy_r2 <= 0;
end
else
begin
afi_seq_busy_r <= afi_seq_busy;
afi_seq_busy_r2 <= afi_seq_busy_r;
end
end
// cans
generate
genvar w_cs;
for (w_cs = 0;w_cs < CFG_MEM_IF_CHIP;w_cs = w_cs + 1)
begin : can_signal_per_chip
// Can refresh signal for each rank
always @ (*)
begin
can_refresh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & ~grant;
end
// Can self refresh signal for each rank
always @ (*)
begin
can_self_rfsh [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & tcom_not_running_pipe [w_cs][cfg_tcl] & ~grant;
end
always @ (*)
begin
can_deep_pdown [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & tcom_not_running_pipe [w_cs][cfg_tcl] & ~grant;
end
// Can power down signal for each rank
always @ (*)
begin
can_power_down [w_cs] = power_saving_enter_ready [w_cs] & all_banks_closed [w_cs] & tcom_not_running [w_cs] & tcom_not_running_pipe [w_cs][cfg_tcl] & ~grant;
end
// Can exit power saving mode signal for each rank
always @ (*)
begin
can_exit_power_saving_mode [w_cs] = power_saving_exit_ready [w_cs];
end
end
endgenerate
/*------------------------------------------------------------------------------
[START] Power Saving Rank Monitor
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Power Saving State Machine
------------------------------------------------------------------------------*/
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : power_saving_logic_per_chip
reg [POWER_SAVING_COUNTER_WIDTH - 1 : 0] power_saving_cnt;
reg [POWER_SAVING_EXIT_COUNTER_WIDTH - 1 : 0] power_saving_exit_cnt;
reg [8 : 0] state;
reg [2 : 0] sideband_state;
reg [1 : 0] disable_clk_state;
reg disable_clk_state_busy;
reg disable_clk_state_busy_r;
reg int_enter_power_saving_ready;
reg int_exit_power_saving_ready;
reg registered_reset;
reg int_zq_cal_req;
reg int_do_power_down;
reg int_do_power_down_r1;
reg int_do_deep_power_down;
reg int_do_deep_power_down_r1;
reg int_do_self_refresh;
reg int_do_self_refresh_r1;
reg [DISABLE_CLK_COUNTER_WIDTH - 1 : 0] disable_clk_cnt;
reg disable_clk_entry;
reg disable_clk_exit;
reg int_disable_clk;
reg int_disable_clk_r1;
reg in_refresh;
// assignment
assign power_saving_enter_ready [u_cs] = int_enter_power_saving_ready;
assign power_saving_exit_ready [u_cs] = int_exit_power_saving_ready & ~((int_do_power_down & ~int_do_power_down_r1) | (int_do_self_refresh & ~int_do_self_refresh_r1) | (int_do_deep_power_down & ~int_do_deep_power_down_r1));
assign cs_zq_cal_req [u_cs] = int_zq_cal_req;
// Counter for power saving state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_saving_cnt <= 0;
end
else
begin
if (do_precharge_all[u_cs] || do_refresh[u_cs] || do_self_rfsh[u_cs] || do_power_down[u_cs])
begin
power_saving_cnt <= BANK_TIMER_COUNTER_OFFSET;
end
else if (power_saving_cnt != {POWER_SAVING_COUNTER_WIDTH{1'b1}})
begin
power_saving_cnt <= power_saving_cnt + 1'b1;
end
end
end
// Counter for power saving exit cycles
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_saving_exit_cnt <= 0;
end
else
begin
if ((int_do_power_down & !int_do_power_down_r1) || (int_do_self_refresh & !int_do_self_refresh_r1) || (int_do_deep_power_down & !int_do_deep_power_down_r1))
begin
power_saving_exit_cnt <= BANK_TIMER_COUNTER_OFFSET;
end
else if (power_saving_exit_cnt != {POWER_SAVING_EXIT_COUNTER_WIDTH{1'b1}})
begin
power_saving_exit_cnt <= power_saving_exit_cnt + 1'b1;
end
end
end
// Disable clock counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
disable_clk_cnt <= 0;
end
else
begin
if ((int_do_self_refresh & !int_do_self_refresh_r1) || (int_do_deep_power_down & !int_do_deep_power_down_r1) || (!int_disable_clk & int_disable_clk_r1))
begin
disable_clk_cnt <= BANK_TIMER_COUNTER_OFFSET;
end
else if (disable_clk_cnt != {DISABLE_CLK_COUNTER_WIDTH{1'b1}})
begin
disable_clk_cnt <= disable_clk_cnt + 1'b1;
end
end
end
// Do power down, deep power down and self refresh register
always @ (*)
begin
int_do_power_down = do_power_down[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_power_down_r1 <= 1'b0;
end
else
begin
int_do_power_down_r1 <= int_do_power_down;
end
end
always @ (*)
begin
int_do_deep_power_down = do_deep_pdown[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_deep_power_down_r1 <= 1'b0;
end
else
begin
int_do_deep_power_down_r1 <= int_do_deep_power_down;
end
end
always @ (*)
begin
int_do_self_refresh = do_self_rfsh[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_self_refresh_r1 <= 1'b0;
end
else
begin
int_do_self_refresh_r1 <= int_do_self_refresh;
end
end
// Disable clock registers
always @ (*)
begin
int_disable_clk = disable_clk[u_cs];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_disable_clk_r1 <= 1'b0;
end
else
begin
int_disable_clk_r1 <= int_disable_clk;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
disable_clk_state_busy_r <= 1'b0;
end
else
begin
disable_clk_state_busy_r <= disable_clk_state_busy;
end
end
// Power saving mode exit ready information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_exit_power_saving_ready <= 1'b0;
end
else
begin
if ((int_do_power_down) && (!int_do_power_down_r1)) // positive edge detector but late by one clock cycle
begin
int_exit_power_saving_ready <= 1'b0;
end
else if ((int_do_self_refresh) && (!int_do_self_refresh_r1)) // positive edge detector
begin
int_exit_power_saving_ready <= 1'b0;
end
else if ((int_do_deep_power_down) && (!int_do_deep_power_down_r1)) // positive edge detector
begin
int_exit_power_saving_ready <= 1'b0;
end
else if (power_saving_exit_cnt >= t_param_power_saving_exit)
begin
int_exit_power_saving_ready <= 1'b1;
end
else
begin
int_exit_power_saving_ready <= 1'b0;
end
end
end
// Disable clock entry and exit logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
disable_clk_entry <= 1'b0;
disable_clk_exit <= 1'b0;
end
else
begin
if ((int_do_self_refresh) && (!int_do_self_refresh_r1)) // positive edge detector
begin
disable_clk_entry <= 1'b0;
disable_clk_exit <= 1'b0;
end
else if ((int_do_deep_power_down) && (!int_do_deep_power_down_r1)) // positive edge detector
begin
disable_clk_entry <= 1'b0;
disable_clk_exit <= 1'b0;
end
else if ((!int_disable_clk) && (int_disable_clk_r1)) // negative edge detector
begin
disable_clk_entry <= 1'b0;
disable_clk_exit <= 1'b0;
end
else if (disable_clk_cnt >= t_param_mem_clk_entry_cycles)
begin
disable_clk_entry <= 1'b1;
disable_clk_exit <= 1'b1;
end
else
begin
disable_clk_entry <= 1'b0;
disable_clk_exit <= 1'b0;
end
end
end
// stall_chip output signal
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
stall_chip[u_cs] = int_stall_chip[u_cs] | int_stall_chip_combi[u_cs];
end
else
begin
stall_chip[u_cs] = int_stall_chip[u_cs];
end
end
// int_stall_chip_combi signal, we need to issue stall chip one clock cycle earlier to rank timer
// because rank timer is using a register output
always @ (*)
begin
if (state == IDLE_S3)
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip_combi[u_cs] = 1'b1;
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
else
begin
int_stall_chip_combi[u_cs] = 1'b0;
end
end
// command issuing state machine
always @(posedge ctl_clk, negedge ctl_reset_n)
begin : FSM
if (!ctl_reset_n)
begin
state <= INIT;
int_stall_chip[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
do_power_down[u_cs] <= 1'b0;
do_deep_pdown[u_cs] <= 1'b0;
do_self_rfsh_req[u_cs] <= 1'b0;
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
do_pch_all_req[u_cs] <= 1'b0;
do_refresh_req[u_cs] <= 1'b0;
afi_ctl_refresh_done[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
init_req[u_cs] <= 1'b0;
trk_rfsh_cntr[u_cs] <= 0;
end
else
begin
case(state)
INIT :
begin
if (ctl_cal_success == 1'b1)
begin
state <= IDLE_S3;
int_stall_chip[u_cs] <= 1'b0;
end
else
begin
state <= INIT;
int_stall_chip[u_cs] <= 1'b1;
end
end
IDLE_S3 :
begin
do_pch_all_req[u_cs] <= 1'b0;
if (do_zqcal_req[u_cs])
begin
if (do_zqcal[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b0;
doing_zqcal[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
else if (refresh_chip_req[u_cs] && !do_refresh[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
begin
state <= REFRESH;
end
else
begin
state <= PCHALL;
end
end
else if (self_refresh_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
begin
state <= SELFRFSH;
end
else
begin
state <= PCHALL;
end
end
else if (deep_pdown_chip_req[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
begin
state <= DEEPPDN;
end
else
begin
state <= PCHALL;
end
end
else if (power_down_chip_req_combi[u_cs])
begin
int_stall_chip[u_cs] <= 1'b1;
if (all_banks_closed[u_cs])
begin
state <= PDOWN;
end
else
begin
state <= PCHALL;
end
end
else if (int_stall_chip[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
begin
int_stall_chip[u_cs] <= 1'b0;
end
end
PCHALL :
begin
if (refresh_chip_req[u_cs] | self_refresh_chip_req[u_cs] | power_down_chip_req_combi[u_cs] | deep_pdown_chip_req[u_cs])
begin
if (do_precharge_all[u_cs] || all_banks_closed[u_cs])
begin
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (refresh_chip_req[u_cs])
begin
state <= REFRESH;
end
else if (self_refresh_chip_req[u_cs])
begin
state <= SELFRFSH;
end
else if (deep_pdown_chip_req[u_cs])
begin
state <= DEEPPDN;
end
else
begin
state <= PDOWN;
end
end
else if (refresh_chip_req[u_cs])
begin
if ((~all_banks_closed & refresh_chip_req ) == (~all_banks_closed & tcom_not_running & refresh_chip_req ) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (self_refresh_chip_req[u_cs])
begin
if ((~all_banks_closed & self_refresh_chip_req) == (~all_banks_closed & tcom_not_running & self_refresh_chip_req) && !grant)
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else if (&tcom_not_running && !grant) // for power down and deep power down request, since these request must go to all chips
begin
do_pch_all_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
state <= IDLE_S3;
do_pch_all_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
end
REFRESH :
begin
if (do_refresh[u_cs])
begin
do_refresh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_enable_dqs_tracking && (do_refresh_to_all_chip | do_refresh_to_all_chip_r))
trk_rfsh_cntr[u_cs] <= trk_rfsh_cntr[u_cs] + 1'b1;
if (cfg_enable_dqs_tracking && (do_refresh_to_all_chip | do_refresh_to_all_chip_r) && trk_rfsh_cntr[u_cs] == SAMPLE_EVERY_N_RFSH)
begin
state <= DQSTRK;
trk_rfsh_cntr[u_cs] <= 0;
end
else if (power_down_chip_req_combi[u_cs])
begin
state <= PDOWN;
end
else if (zqcal_req)
begin
state <= ZQCAL;
doing_zqcal[u_cs] <= 1'b1;
end
else
begin
state <= IDLE_S3;
end
end
else if (refresh_chip_req[u_cs])
begin
if (!all_banks_closed[u_cs])
begin
state <= PCHALL;
end
else if (refresh_chip_req == (can_refresh & refresh_chip_req))
begin
do_refresh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
else
begin
if (zqcal_req)
begin
state <= ZQCAL;
doing_zqcal[u_cs] <= 1'b1;
end
else
begin
state <= IDLE_S3;
end
stall_arbiter[u_cs] <= 1'b0;
end
end
SELFRFSH :
begin
if (!all_banks_closed[u_cs])
begin
state <= PCHALL;
end
else if (!self_refresh_chip_req[u_cs] && can_exit_power_saving_mode[u_cs] && !disable_clk_state_busy)
begin
do_self_rfsh_req[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
if (cfg_type == `MMR_TYPE_DDR3) // DDR3
begin
state <= ZQCAL;
doing_zqcal[u_cs] <= 1'b1;
end
else
begin
state <= IDLE_S3;
end
end
else if (do_self_rfsh_req_r2[u_cs])
begin
stall_arbiter[u_cs] <= 1'b0; // only assert for three clock cycle for self refresh entry (thress instead of one to solve conflicting command issues in half/quarter rate and regdimm design)
end
else if (self_refresh_chip_req == (can_self_rfsh & self_refresh_chip_req) && !(|do_precharge_all))
begin
do_self_rfsh_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
PDOWN :
begin
if (refresh_chip_req[u_cs] && !do_refresh[u_cs] && can_exit_power_saving_mode[u_cs])
begin
state <= REFRESH;
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
end
else if (!power_down_chip_req_combi[u_cs] && can_exit_power_saving_mode[u_cs])
begin
do_power_down[u_cs] <= 1'b0;
stall_arbiter[u_cs] <= 1'b0;
state <= IDLE_S3;
end
else if (&can_power_down && !refresh_req)
begin
do_power_down[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
else
begin
state <= PDOWN;
end
end
DEEPPDN :
begin
if (!all_banks_closed[u_cs])
begin
state <= PCHALL;
end
else if (!deep_pdown_chip_req[u_cs] && can_exit_power_saving_mode[u_cs] && !disable_clk_state_busy)
begin
do_deep_pdown[u_cs] <= 1'b0;
state <= INITREQ;
end
else if (&can_deep_pdown && !(|do_precharge_all))
begin
do_deep_pdown[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
end
end
ZQCAL :
begin
if (cs_zq_cal_req[u_cs])
begin
do_zqcal_req[u_cs] <= 1'b1;
stall_arbiter[u_cs] <= 1'b1;
state <= IDLE_S3;
end
end
DQSTRK :
begin
if (!dqstrk_exit[u_cs] && !afi_ctl_refresh_done[u_cs] && !do_refresh[u_cs] && power_saving_enter_ready[u_cs])
begin
afi_ctl_refresh_done[u_cs] <= 1'b1;
end
else if (!dqstrk_exit[u_cs] && afi_ctl_refresh_done[u_cs] && afi_seq_busy_r2[u_cs]) // stall until seq_busy is deasserted
begin
dqstrk_exit[u_cs] <= 1'b1;
end
else if (dqstrk_exit[u_cs] && !afi_seq_busy_r2[u_cs])
begin
afi_ctl_refresh_done[u_cs] <= 1'b0;
dqstrk_exit[u_cs] <= 1'b0;
state <= IDLE_S3;
end
end
INITREQ :
begin
if (!init_req[u_cs])
begin
init_req[u_cs] <= 1'b1;
end
else if (!ctl_cal_success) // wait for cal_success to go low
begin
init_req[u_cs] <= 1'b0;
state <= INIT;
end
end
default :
begin
state <= IDLE_S3;
end
endcase
end
end
// Disable memory clock state
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
disable_clk_state <= IDLE_S2;
disable_clk_state_busy <= 1'b0;
disable_clk[u_cs] <= 1'b0;
end
else
begin
case (disable_clk_state)
IDLE_S2 :
begin
if (do_self_rfsh[u_cs] && !disable_clk_state_busy_r) // to prevent it from re-entering disable clock state
begin
disable_clk_state <= DISABLECLK1;
disable_clk_state_busy <= 1'b1;
end
else if (do_deep_pdown[u_cs] && !disable_clk_state_busy_r) // to prevent it from re-entering disable clock state
begin
disable_clk_state <= DISABLECLK1;
disable_clk_state_busy <= 1'b1;
end
else
begin
disable_clk_state <= IDLE_S2;
disable_clk_state_busy <= 1'b0;
disable_clk[u_cs] <= 1'b0;
end
end
DISABLECLK1 :
begin
if ((!deep_pdown_chip_req[u_cs] && !self_refresh_chip_req[u_cs]) && can_exit_power_saving_mode[u_cs]) // exit both power saving state
begin
disable_clk_state <= DISABLECLK2;
disable_clk[u_cs] <= 1'b0;
end
else if (disable_clk_entry) // can disable memory clock now
begin
disable_clk[u_cs] <= 1'b1;
end
end
DISABLECLK2 :
begin
if (!(!int_disable_clk && int_disable_clk_r1) && disable_clk_exit) // delay by N clock cycles before exting deep power down or self refresh
begin
disable_clk_state <= IDLE_S2;
disable_clk_state_busy <= 1'b0;
end
end
default :
begin
disable_clk_state <= IDLE_S2;
end
endcase
end
end
// sideband state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sideband_state <= IDLE_S1;
int_enter_power_saving_ready <= 1'b0;
int_zq_cal_req <= 1'b0;
sideband_in_refresh[u_cs] <= 1'b0;
end
else
begin
case (sideband_state)
IDLE_S1 :
begin
int_zq_cal_req <= 1'b0;
if (power_saving_cnt >= t_param_pch_all_to_valid)
begin
int_enter_power_saving_ready <= 1'b1;
end
else
begin
int_enter_power_saving_ready <= 1'b0;
end
if (do_precharge_all[u_cs])
begin
int_enter_power_saving_ready <= 1'b0;
end
if (do_refresh[u_cs])
begin
sideband_state <= ARF;
int_enter_power_saving_ready <= 1'b0;
end
if (do_self_rfsh[u_cs])
begin
sideband_state <= SRF;
int_enter_power_saving_ready <= 1'b0;
end
if (do_power_down[u_cs])
begin
sideband_state <= PDN;
int_enter_power_saving_ready <= 1'b0;
end
if (do_refresh[u_cs])
begin
sideband_in_refresh[u_cs] <= 1'b1;
end
else
begin
sideband_in_refresh[u_cs] <= 1'b0;
end
end
ARF :
begin
if (power_saving_cnt >= t_param_arf_to_valid)
begin
sideband_state <= IDLE_S1;
int_enter_power_saving_ready <= 1'b1;
sideband_in_refresh[u_cs] <= 1'b0;
int_zq_cal_req <= 1'b1;
end
else
begin
sideband_state <= ARF;
int_enter_power_saving_ready <= 1'b0;
sideband_in_refresh[u_cs] <= 1'b1;
int_zq_cal_req <= 1'b0;
end
end
SRF :
begin
sideband_in_refresh[u_cs] <= 1'b0;
// ZQ request to state machine
if (power_saving_cnt == t_param_srf_to_zq_cal) // only one cycle
begin
int_zq_cal_req <= 1'b1;
end
else
begin
int_zq_cal_req <= 1'b0;
end
if (!do_self_rfsh[u_cs] && power_saving_cnt >= t_param_srf_to_valid)
begin
sideband_state <= IDLE_S1;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= SRF;
int_enter_power_saving_ready <= 1'b0;
end
end
PDN :
begin
int_zq_cal_req <= 1'b0;
sideband_in_refresh[u_cs] <= 1'b0;
if (!do_power_down[u_cs] && power_saving_cnt >= t_param_pdn_to_valid)
begin
sideband_state <= IDLE_S1;
int_enter_power_saving_ready <= 1'b1;
end
else
begin
sideband_state <= PDN;
int_enter_power_saving_ready <= 1'b0;
end
end
default :
begin
sideband_state <= IDLE_S1;
sideband_in_refresh[u_cs] <= 1'b0;
end
endcase
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Refresh Request
------------------------------------------------------------------------------*/
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : auto_refresh_logic_per_chip
reg [ARF_COUNTER_WIDTH - 1 : 0] refresh_cnt;
// refresh counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
refresh_cnt <= 0;
end
else
begin
if (self_rfsh_req && !self_rfsh_req_r && |self_rfsh_chip)
begin
refresh_cnt <= {ARF_COUNTER_WIDTH{1'b1}};
end
else if (do_refresh[s_cs])
begin
refresh_cnt <= 3;
end
else if (refresh_cnt != {ARF_COUNTER_WIDTH{1'b1}})
begin
refresh_cnt <= refresh_cnt + 1'b1;
end
end
end
// refresh request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cs_refresh_req [s_cs] <= 1'b0;
end
else
begin
if (self_rfsh_req && !self_rfsh_req_r && |self_rfsh_chip)
begin
cs_refresh_req [s_cs] <= 1'b1;
end
else if (do_refresh[s_cs] || do_self_rfsh[s_cs])
begin
cs_refresh_req [s_cs] <= 1'b0;
end
else if (refresh_cnt >= t_param_arf_period)
begin
cs_refresh_req [s_cs] <= 1'b1;
end
else
begin
cs_refresh_req [s_cs] <= 1'b0;
end
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Power Down Request
------------------------------------------------------------------------------*/
// register no command signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
no_command_r1 <= 1'b0;
end
else
begin
no_command_r1 <= tbp_empty;
end
end
// power down counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_cnt <= 0;
end
else
begin
if ((!tbp_empty && no_command_r1) || self_rfsh_req) // negative edge detector
begin
power_down_cnt <= 3;
end
else if (tbp_empty && power_down_cnt != {PDN_COUNTER_WIDTH{1'b1}} && ctl_cal_success)
begin
power_down_cnt <= power_down_cnt + 1'b1;
end
end
end
// power down request logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_chip_req <= 0;
end
else
begin
if (t_param_pdn_period == 0) // when auto power down cycles is set to '0', auto power down mode will be disabled
begin
power_down_chip_req <= 0;
end
else
begin
if (!tbp_empty || self_rfsh_req) // we need to make sure power down request to go low as fast as possible to avoid unnecessary power down
begin
power_down_chip_req <= 0;
end
else if (power_down_chip_req == 0)
begin
if (power_down_cnt >= t_param_pdn_period && !(|doing_zqcal))
begin
power_down_chip_req <= {CFG_MEM_IF_CHIP{1'b1}};
end
else
begin
power_down_chip_req <= 0;
end
end
else if (!(power_down_cnt >= t_param_pdn_period))
begin
power_down_chip_req <= 0;
end
end
end
end
assign power_down_chip_req_combi = power_down_chip_req & {CFG_MEM_IF_CHIP{tbp_empty}} & {CFG_MEM_IF_CHIP{~refresh_req}};
/*------------------------------------------------------------------------------
[END] Power Saving Rank Monitor
------------------------------------------------------------------------------*/
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder4to16.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_decoder4to16();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [15:1] dout;
// Declare "reg" signals: inputs to the DUT
reg [3:0] din;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
decoder4to16 dec4to16 (
// instance_name(signal name),
// Signal name can be the same as the instance name
din,dout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
din = 15'd0;
#1;
din = 15'd1;
// @ t=0,
#1;
din = 15'd2;
#1;
din = 15'd3;
#1;
din = 15'd4;
#1;
din = 15'd5;
#1;
din = 15'd6;
#1;
din = 15'd7;
#1;
din = 15'd8;
#1;
din = 15'd9;
#1;
din = 15'd10;
#1;
din = 15'd11;
#1;
din = 15'd12;
#1;
din = 15'd13;
#1;
din = 15'd14;
#1;
din = 15'd15;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_ICFSM_IDLE 2'd0
`define OR1200_ICFSM_CFETCH 2'd1
`define OR1200_ICFSM_LREFILL3 2'd2
`define OR1200_ICFSM_IFETCH 2'd3
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // fetch in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
end
default:
state <= #1 `OR1200_ICFSM_IDLE;
endcase
end
endmodule
|
// soc_system_mm_interconnect_3.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.12.19.15:55:02
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_3 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire system_pll_outclk0_clk, // system_pll_outclk0.clk
input wire fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset, // fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset.reset
input wire hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
output wire [7:0] fifo_bridge_cpuM_cpus0_s1_address, // fifo_bridge_cpuM_cpus0_s1.address
output wire fifo_bridge_cpuM_cpus0_s1_write, // .write
output wire fifo_bridge_cpuM_cpus0_s1_read, // .read
input wire [31:0] fifo_bridge_cpuM_cpus0_s1_readdata, // .readdata
output wire [31:0] fifo_bridge_cpuM_cpus0_s1_writedata, // .writedata
output wire [7:0] fifo_bridge_cpuM_cpus1_s1_address, // fifo_bridge_cpuM_cpus1_s1.address
output wire fifo_bridge_cpuM_cpus1_s1_write, // .write
output wire fifo_bridge_cpuM_cpus1_s1_read, // .read
input wire [31:0] fifo_bridge_cpuM_cpus1_s1_readdata, // .readdata
output wire [31:0] fifo_bridge_cpuM_cpus1_s1_writedata // .writedata
);
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // fifo_bridge_cpuM_cpus0_s1_translator:uav_waitrequest -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> fifo_bridge_cpuM_cpus0_s1_translator:uav_burstcount
wire [31:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> fifo_bridge_cpuM_cpus0_s1_translator:uav_writedata
wire [20:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_address -> fifo_bridge_cpuM_cpus0_s1_translator:uav_address
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_write -> fifo_bridge_cpuM_cpus0_s1_translator:uav_write
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> fifo_bridge_cpuM_cpus0_s1_translator:uav_lock
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_read -> fifo_bridge_cpuM_cpus0_s1_translator:uav_read
wire [31:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // fifo_bridge_cpuM_cpus0_s1_translator:uav_readdata -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // fifo_bridge_cpuM_cpus0_s1_translator:uav_readdatavalid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fifo_bridge_cpuM_cpus0_s1_translator:uav_debugaccess
wire [3:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> fifo_bridge_cpuM_cpus0_s1_translator:uav_byteenable
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [112:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [112:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [33:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // fifo_bridge_cpuM_cpus1_s1_translator:uav_waitrequest -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> fifo_bridge_cpuM_cpus1_s1_translator:uav_burstcount
wire [31:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> fifo_bridge_cpuM_cpus1_s1_translator:uav_writedata
wire [20:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_address -> fifo_bridge_cpuM_cpus1_s1_translator:uav_address
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_write -> fifo_bridge_cpuM_cpus1_s1_translator:uav_write
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> fifo_bridge_cpuM_cpus1_s1_translator:uav_lock
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_read -> fifo_bridge_cpuM_cpus1_s1_translator:uav_read
wire [31:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // fifo_bridge_cpuM_cpus1_s1_translator:uav_readdata -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // fifo_bridge_cpuM_cpus1_s1_translator:uav_readdatavalid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fifo_bridge_cpuM_cpus1_s1_translator:uav_debugaccess
wire [3:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> fifo_bridge_cpuM_cpus1_s1_translator:uav_byteenable
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [112:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [112:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [33:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
wire [111:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
wire [111:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [111:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [111:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [1:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [111:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [111:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [1:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [111:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [1:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [111:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [1:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [111:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [1:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [111:0] limiter_rsp_src_data; // limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire [1:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [111:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [1:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [111:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [1:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [111:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [1:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [111:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire [1:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire limiter_001_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> limiter_001:rsp_src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> burst_adapter:sink0_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> burst_adapter:sink0_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> burst_adapter:sink0_startofpacket
wire [111:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> burst_adapter:sink0_data
wire [1:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_src_ready; // burst_adapter:sink0_ready -> cmd_xbar_mux:src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [111:0] burst_adapter_source0_data; // burst_adapter:source0_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [1:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> burst_adapter_001:sink0_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> burst_adapter_001:sink0_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> burst_adapter_001:sink0_startofpacket
wire [111:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> burst_adapter_001:sink0_data
wire [1:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> burst_adapter_001:sink0_channel
wire cmd_xbar_mux_001_src_ready; // burst_adapter_001:sink0_ready -> cmd_xbar_mux_001:src_ready
wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [111:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_001_source0_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
wire [1:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> crosser:in_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
wire [111:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> crosser:in_data
wire [1:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> crosser:in_channel
wire cmd_xbar_demux_src0_ready; // crosser:in_ready -> cmd_xbar_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_xbar_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [111:0] crosser_out_data; // crosser:out_data -> cmd_xbar_mux:sink0_data
wire [1:0] crosser_out_channel; // crosser:out_channel -> cmd_xbar_mux:sink0_channel
wire crosser_out_ready; // cmd_xbar_mux:sink0_ready -> crosser:out_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> crosser_001:in_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [111:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> crosser_001:in_data
wire [1:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> crosser_001:in_channel
wire cmd_xbar_demux_src1_ready; // crosser_001:in_ready -> cmd_xbar_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_xbar_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [111:0] crosser_001_out_data; // crosser_001:out_data -> cmd_xbar_mux_001:sink0_data
wire [1:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_xbar_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_xbar_mux_001:sink0_ready -> crosser_001:out_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> crosser_002:in_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> crosser_002:in_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> crosser_002:in_startofpacket
wire [111:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> crosser_002:in_data
wire [1:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> crosser_002:in_channel
wire cmd_xbar_demux_001_src0_ready; // crosser_002:in_ready -> cmd_xbar_demux_001:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> cmd_xbar_mux:sink1_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [111:0] crosser_002_out_data; // crosser_002:out_data -> cmd_xbar_mux:sink1_data
wire [1:0] crosser_002_out_channel; // crosser_002:out_channel -> cmd_xbar_mux:sink1_channel
wire crosser_002_out_ready; // cmd_xbar_mux:sink1_ready -> crosser_002:out_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> crosser_003:in_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> crosser_003:in_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> crosser_003:in_startofpacket
wire [111:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> crosser_003:in_data
wire [1:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> crosser_003:in_channel
wire cmd_xbar_demux_001_src1_ready; // crosser_003:in_ready -> cmd_xbar_demux_001:src1_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> cmd_xbar_mux_001:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [111:0] crosser_003_out_data; // crosser_003:out_data -> cmd_xbar_mux_001:sink1_data
wire [1:0] crosser_003_out_channel; // crosser_003:out_channel -> cmd_xbar_mux_001:sink1_channel
wire crosser_003_out_ready; // cmd_xbar_mux_001:sink1_ready -> crosser_003:out_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> crosser_004:in_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> crosser_004:in_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> crosser_004:in_startofpacket
wire [111:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> crosser_004:in_data
wire [1:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> crosser_004:in_channel
wire rsp_xbar_demux_src0_ready; // crosser_004:in_ready -> rsp_xbar_demux:src0_ready
wire crosser_004_out_endofpacket; // crosser_004:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire crosser_004_out_valid; // crosser_004:out_valid -> rsp_xbar_mux:sink0_valid
wire crosser_004_out_startofpacket; // crosser_004:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [111:0] crosser_004_out_data; // crosser_004:out_data -> rsp_xbar_mux:sink0_data
wire [1:0] crosser_004_out_channel; // crosser_004:out_channel -> rsp_xbar_mux:sink0_channel
wire crosser_004_out_ready; // rsp_xbar_mux:sink0_ready -> crosser_004:out_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> crosser_005:in_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> crosser_005:in_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> crosser_005:in_startofpacket
wire [111:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> crosser_005:in_data
wire [1:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> crosser_005:in_channel
wire rsp_xbar_demux_src1_ready; // crosser_005:in_ready -> rsp_xbar_demux:src1_ready
wire crosser_005_out_endofpacket; // crosser_005:out_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire crosser_005_out_valid; // crosser_005:out_valid -> rsp_xbar_mux_001:sink0_valid
wire crosser_005_out_startofpacket; // crosser_005:out_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [111:0] crosser_005_out_data; // crosser_005:out_data -> rsp_xbar_mux_001:sink0_data
wire [1:0] crosser_005_out_channel; // crosser_005:out_channel -> rsp_xbar_mux_001:sink0_channel
wire crosser_005_out_ready; // rsp_xbar_mux_001:sink0_ready -> crosser_005:out_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> crosser_006:in_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> crosser_006:in_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> crosser_006:in_startofpacket
wire [111:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> crosser_006:in_data
wire [1:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> crosser_006:in_channel
wire rsp_xbar_demux_001_src0_ready; // crosser_006:in_ready -> rsp_xbar_demux_001:src0_ready
wire crosser_006_out_endofpacket; // crosser_006:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire crosser_006_out_valid; // crosser_006:out_valid -> rsp_xbar_mux:sink1_valid
wire crosser_006_out_startofpacket; // crosser_006:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [111:0] crosser_006_out_data; // crosser_006:out_data -> rsp_xbar_mux:sink1_data
wire [1:0] crosser_006_out_channel; // crosser_006:out_channel -> rsp_xbar_mux:sink1_channel
wire crosser_006_out_ready; // rsp_xbar_mux:sink1_ready -> crosser_006:out_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> crosser_007:in_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> crosser_007:in_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> crosser_007:in_startofpacket
wire [111:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> crosser_007:in_data
wire [1:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> crosser_007:in_channel
wire rsp_xbar_demux_001_src1_ready; // crosser_007:in_ready -> rsp_xbar_demux_001:src1_ready
wire crosser_007_out_endofpacket; // crosser_007:out_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire crosser_007_out_valid; // crosser_007:out_valid -> rsp_xbar_mux_001:sink1_valid
wire crosser_007_out_startofpacket; // crosser_007:out_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [111:0] crosser_007_out_data; // crosser_007:out_data -> rsp_xbar_mux_001:sink1_data
wire [1:0] crosser_007_out_channel; // crosser_007:out_channel -> rsp_xbar_mux_001:sink1_channel
wire crosser_007_out_ready; // rsp_xbar_mux_001:sink1_ready -> crosser_007:out_ready
wire [1:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [1:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) fifo_bridge_cpum_cpus0_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (fifo_bridge_cpuM_cpus0_s1_address), // avalon_anti_slave_0.address
.av_write (fifo_bridge_cpuM_cpus0_s1_write), // .write
.av_read (fifo_bridge_cpuM_cpus0_s1_read), // .read
.av_readdata (fifo_bridge_cpuM_cpus0_s1_readdata), // .readdata
.av_writedata (fifo_bridge_cpuM_cpus0_s1_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) fifo_bridge_cpum_cpus1_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (fifo_bridge_cpuM_cpus1_s1_address), // avalon_anti_slave_0.address
.av_write (fifo_bridge_cpuM_cpus1_s1_write), // .write
.av_read (fifo_bridge_cpuM_cpus1_s1_read), // .read
.av_readdata (fifo_bridge_cpuM_cpus1_s1_readdata), // .readdata
.av_writedata (fifo_bridge_cpuM_cpus1_s1_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (106),
.PKT_CACHE_L (103),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (107),
.PKT_RESPONSE_STATUS_H (108),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (99),
.PKT_THREAD_ID_L (88),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.ID (0)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (limiter_rsp_src_data), // .data
.write_rp_channel (limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (limiter_001_rsp_src_valid), // read_rp.valid
.read_rp_data (limiter_001_rsp_src_data), // .data
.read_rp_channel (limiter_001_rsp_src_channel), // .channel
.read_rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (limiter_001_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (8'b00000000), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_RESPONSE_STATUS_H (108),
.PKT_RESPONSE_STATUS_L (107),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.ST_CHANNEL_W (2),
.ST_DATA_W (112),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (113),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_RESPONSE_STATUS_H (108),
.PKT_RESPONSE_STATUS_L (107),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.ST_CHANNEL_W (2),
.ST_DATA_W (112),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_001_source0_ready), // cp.ready
.cp_valid (burst_adapter_001_source0_valid), // .valid
.cp_data (burst_adapter_001_source0_data), // .data
.cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_001_source0_channel), // .channel
.rf_sink_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (113),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_system_mm_interconnect_3_addr_router addr_router (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_addr_router addr_router_001 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_id_router id_router (
.sink_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_id_router id_router_001 (
.sink_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_src_data), // .data
.sink0_channel (cmd_xbar_mux_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter_001 (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_001_src_data), // .data
.sink0_channel (cmd_xbar_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_001_src_ready), // .ready
.source0_valid (burst_adapter_001_source0_valid), // source0.valid
.source0_data (burst_adapter_001_source0_data), // .data
.source0_channel (burst_adapter_001_source0_channel), // .channel
.source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_001_source0_ready) // .ready
);
soc_system_mm_interconnect_3_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_cmd_xbar_demux cmd_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_cmd_xbar_mux cmd_xbar_mux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_002_out_ready), // sink1.ready
.sink1_valid (crosser_002_out_valid), // .valid
.sink1_channel (crosser_002_out_channel), // .channel
.sink1_data (crosser_002_out_data), // .data
.sink1_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_demux rsp_xbar_demux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_004_out_ready), // sink0.ready
.sink0_valid (crosser_004_out_valid), // .valid
.sink0_channel (crosser_004_out_channel), // .channel
.sink0_data (crosser_004_out_data), // .data
.sink0_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.sink1_ready (crosser_006_out_ready), // sink1.ready
.sink1_valid (crosser_006_out_valid), // .valid
.sink1_channel (crosser_006_out_channel), // .channel
.sink1_data (crosser_006_out_data), // .data
.sink1_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_006_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_mux rsp_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_005_out_ready), // sink0.ready
.sink0_valid (crosser_005_out_valid), // .valid
.sink0_channel (crosser_005_out_channel), // .channel
.sink0_data (crosser_005_out_data), // .data
.sink0_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.sink1_ready (crosser_007_out_ready), // sink1.ready
.sink1_valid (crosser_007_out_valid), // .valid
.sink1_channel (crosser_007_out_channel), // .channel
.sink1_data (crosser_007_out_data), // .data
.sink1_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_007_out_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_src0_ready), // in.ready
.in_valid (cmd_xbar_demux_src0_valid), // .valid
.in_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_src0_channel), // .channel
.in_data (cmd_xbar_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_src1_ready), // in.ready
.in_valid (cmd_xbar_demux_src1_valid), // .valid
.in_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_src1_channel), // .channel
.in_data (cmd_xbar_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_001_src0_ready), // in.ready
.in_valid (cmd_xbar_demux_001_src0_valid), // .valid
.in_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_001_src0_channel), // .channel
.in_data (cmd_xbar_demux_001_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_001_src1_ready), // in.ready
.in_valid (cmd_xbar_demux_001_src1_valid), // .valid
.in_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_001_src1_channel), // .channel
.in_data (cmd_xbar_demux_001_src1_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_004 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_src0_ready), // in.ready
.in_valid (rsp_xbar_demux_src0_valid), // .valid
.in_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_src0_channel), // .channel
.in_data (rsp_xbar_demux_src0_data), // .data
.out_ready (crosser_004_out_ready), // out.ready
.out_valid (crosser_004_out_valid), // .valid
.out_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.out_channel (crosser_004_out_channel), // .channel
.out_data (crosser_004_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_005 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_src1_ready), // in.ready
.in_valid (rsp_xbar_demux_src1_valid), // .valid
.in_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_src1_channel), // .channel
.in_data (rsp_xbar_demux_src1_data), // .data
.out_ready (crosser_005_out_ready), // out.ready
.out_valid (crosser_005_out_valid), // .valid
.out_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.out_channel (crosser_005_out_channel), // .channel
.out_data (crosser_005_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_006 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_001_src0_ready), // in.ready
.in_valid (rsp_xbar_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_001_src0_channel), // .channel
.in_data (rsp_xbar_demux_001_src0_data), // .data
.out_ready (crosser_006_out_ready), // out.ready
.out_valid (crosser_006_out_valid), // .valid
.out_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.out_channel (crosser_006_out_channel), // .channel
.out_data (crosser_006_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_007 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_001_src1_ready), // in.ready
.in_valid (rsp_xbar_demux_001_src1_valid), // .valid
.in_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_001_src1_channel), // .channel
.in_data (rsp_xbar_demux_001_src1_data), // .data
.out_ready (crosser_007_out_ready), // out.ready
.out_valid (crosser_007_out_valid), // .valid
.out_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.out_channel (crosser_007_out_channel), // .channel
.out_data (crosser_007_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2013 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.3
// \ \ Description : Xilinx Functional Simulation Library Component
// / / User Interface to Global Clock, Reset and 3-State Controls
// /___/ /\ Filename : STARTUPE3.v
// \ \ / \ Timestamp : Tue Jul 9 16:30:16 PDT 2013
// \___\/\___\
//
// Revision:
// 07/12/13 - Initial version.
// 02/06/14 - Fixed tristate of USRCCLKTS (CR 766066).
// 04/15/14 - Updated FCSBO, DO and DI to connect to glbl (CR 763244).
// 05/27/14 - New simulation library message format.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module STARTUPE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter PROG_USR = "FALSE",
parameter real SIM_CCLK_FREQ = 0.0
)(
output CFGCLK,
output CFGMCLK,
output [3:0] DI,
output EOS,
output PREQ,
input [3:0] DO,
input [3:0] DTS,
input FCSBO,
input FCSBTS,
input GSR,
input GTS,
input KEYCLEARB,
input PACK,
input USRCCLKO,
input USRCCLKTS,
input USRDONEO,
input USRDONETS
);
reg SIM_CCLK_FREQ_BINARY;
reg [2:0] PROG_USR_BINARY;
time CFGMCLK_PERIOD = 20000;
reg cfgmclk_out;
localparam MODULE_NAME = "STARTUPE3";
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
wire start_count;
integer edge_count = 0;
reg preq_deassert = 0;
reg PREQ_out = 0;
wire EOS_out;
// Counters and Flags
reg [2:0] edge_count_cclko = 0;
reg [2:0] cclko_wait_count = 3'b010;
reg start_glbl_cclko = 0;
initial begin
case (PROG_USR)
"FALSE" : PROG_USR_BINARY = 3'b000;
"TRUE" : PROG_USR_BINARY = 3'b111;
default : begin
$display("Error: [Unisim %s-101] PROG_USR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PROG_USR);
$finish;
end
endcase
if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0))
SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ;
else begin
$display("Error: [Unisim %s-102] SIM_CCLK_FREQ attribute is set to %f. Legal values for this attribute are 0.0 to 10.0. Instance: %m", MODULE_NAME, SIM_CCLK_FREQ);
$finish;
end
end
//-------------------------------------------------------------------------------
//----------------- Initial -----------------------------------------------------
//-------------------------------------------------------------------------------
initial begin
cfgmclk_out = 0;
forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out;
end
//-------------------------------------------------------------------------------
//-------------------- PREQ -----------------------------------------------------
//-------------------------------------------------------------------------------
assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0;
always @(posedge cfgmclk_out) begin
if(start_count)
edge_count = edge_count + 1;
else
edge_count = 0;
if(edge_count == 35)
preq_deassert <= 1'b1;
else
preq_deassert <= 1'b0;
end
always @(negedge glbl.PROGB_GLBL, posedge preq_deassert)
PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert;
//-------------------------------------------------------------------------------
//-------------------- ERROR MSG ------------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge PACK) begin
if(PREQ_out == 1'b0)
$display("Error: [Unisim %s-1] PACK received with no associate PREQ. Instance: %m", MODULE_NAME);
end
//-------------------------------------------------------------------------------
//--------------------- EOS -----------------------------------------------------
//-------------------------------------------------------------------------------
assign EOS_out = ~glbl.GSR;
//-------------------------------------------------------------------------------
//-------------------- glbl.CCLKO ---------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge USRCCLKO) begin
if(EOS_out) edge_count_cclko <= edge_count_cclko + 1;
end
always @(edge_count_cclko)
if (edge_count_cclko == cclko_wait_count)
start_glbl_cclko = 1;
//-------------------------------------------------------------------------------
//-------------------- OUTPUT ---------------------------------------------------
//-------------------------------------------------------------------------------
assign CFGMCLK = cfgmclk_out;
assign PREQ = PREQ_out;
assign EOS = EOS_out;
// assign glbl.CCLKO_GLBL = start_glbl_cclko ? ~USRCCLKTS? USRCCLKO : 1'b1 : 1'b1;
assign glbl.CCLKO_GLBL = start_glbl_cclko ? (~USRCCLKTS ? USRCCLKO : 1'bz) : 1'b1;
assign glbl.FCSBO_GLBL = ~FCSBTS ? FCSBO : 1'bz;
assign glbl.DO_GLBL[0] = ~DTS[0] ? DO[0] : 1'bz;
assign glbl.DO_GLBL[1] = ~DTS[1] ? DO[1] : 1'bz;
assign glbl.DO_GLBL[2] = ~DTS[2] ? DO[2] : 1'bz;
assign glbl.DO_GLBL[3] = ~DTS[3] ? DO[3] : 1'bz;
assign DI = glbl.DI_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: acl_int_sdiv64.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_div64s (
enable,
clock,
denom,
numer,
quotient,
remain);
input enable;
input clock;
input [63:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [63:0] remain;
wire [63:0] sub_wire0;
wire [63:0] sub_wire1;
wire [63:0] remain = sub_wire0[63:0];
wire [63:0] quotient = sub_wire1[63:0];
lpm_divide LPM_DIVIDE_component (
.clock (clock),
.clken (enable),
.denom (denom),
.numer (numer),
.remain (sub_wire0),
.quotient (sub_wire1),
.aclr (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 32,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 64,
LPM_DIVIDE_component.lpm_widthn = 64;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "FALSE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "64"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 64 0 INPUT NODEFVAL "denom[63..0]"
// Retrieval info: USED_PORT: numer 0 0 64 0 INPUT NODEFVAL "numer[63..0]"
// Retrieval info: USED_PORT: quotient 0 0 64 0 OUTPUT NODEFVAL "quotient[63..0]"
// Retrieval info: USED_PORT: remain 0 0 64 0 OUTPUT NODEFVAL "remain[63..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 64 0 denom 0 0 64 0
// Retrieval info: CONNECT: @numer 0 0 64 0 numer 0 0 64 0
// Retrieval info: CONNECT: quotient 0 0 64 0 @quotient 0 0 64 0
// Retrieval info: CONNECT: remain 0 0 64 0 @remain 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_sdiv64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_sdiv64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_sdiv64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_sdiv64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_sdiv64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_sdiv64_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [71:0] muxed; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {muxed[63:0]};
wire [5:0] width_check = cyc[5:0] + 1;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h20050a66e7b253d1
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
muxed,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [71:0] muxed;
wire [71:0] a = {in[7:0],~in[31:0],in[31:0]};
wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]};
/*AUTOWIRE*/
Muxer muxer (
.sa (0),
.sb (in[0]),
/*AUTOINST*/
// Outputs
.muxed (muxed[71:0]),
// Inputs
.a (a[71:0]),
.b (b[71:0]));
endmodule
module Muxer (/*AUTOARG*/
// Outputs
muxed,
// Inputs
sa, sb, a, b
);
input sa;
input sb;
output wire [71:0] muxed;
input [71:0] a;
input [71:0] b;
// Constification wasn't sizing with inlining and gave
// unsized error on below
// v
assign muxed = (({72{sa}} & a)
| ({72{sb}} & b));
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_wr_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Writes between AFI and DDRC/OCM
*
*****************************************************************************/
module processing_system7_bfm_v2_0_intr_wr_mem(
sw_clk,
rstn,
full,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_QOS,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
/* local parameters for interconnect wr fifo model */
input sw_clk, rstn;
output full;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg [axi_qos_width-1:0] WR_QOS;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1];
wire empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
task automatic write_mem;
input [wr_fifo_data_bits-1:0] data;
begin
wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
end
endtask
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr <= 0;
rd_ptr <= 0;
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
WR_QOS = 0;
state = SEND_DATA;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
if(!empty) begin
WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
rd_ptr <= rd_ptr+1;
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) rd_ptr[intr_cnt_width-2:0] = 0;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
endmodule
|
/******************************************************************************
* File Name : ec_alu.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : This file contains the module for ALU of the
* elliptic curve processor for the curve
* y^2 + xy = x^3 + a.x^2 + b
* where a = 1
******************************************************************************/
`timescale 1ns / 1ps
`ifndef __ECALU_V__
`define __ECALU_V__
//`include "ff/multiplier.v"
//`include "ff/sqr.v"
//`include "mux8.v"
//`include "mux4.v"
/*---------------------------------------------------------------------------
* Module Name : ec_alu
* Synopsis : Elliptic Curve ALU
* Finite field elements are instantiated over here
* 1. Multiplier
* 2. Squarers
*--------------------------------------------------------------------------*/
module ec_alu(cw, a0, a1, a2, a3, c0, c1);
input wire [232:0] a0, a1, a2, a3; /* the inputs to the alu */
input wire [9:0] cw; /* the control word */
output wire [232:0] c0, c1; /* the alu outputs */
/* Temporary results */
wire [232:0] a0sq, a0qu;
wire [232:0] a1sq, a1qu;
wire [232:0] a2sq, a2qu;
wire [232:0] sa2, sa4, sa5, sa7, sa8, sa8_1;
wire [232:0] sc1;
wire [232:0] sd2, sd2_1;
/* Multiplier inputs and output */
wire [232:0] minA, minB, mout;
multiplier mul(minA, minB, mout);
squarer sq1_p0(a0, a0sq);
squarer sq_p1(a1, a1sq);
squarer sq_p2(a2, a2sq);
squarer sq2_p2(a2sq, a2qu);
squarer sq2_p1(a1sq, a1qu);
squarer sq2_p3(a0sq, a0qu);
/* Choose the inputs to the Multiplier */
mux8 muxA(a0, a0sq, a2, sa7, sd2, a1, a1qu, 233'd0, cw[2:0], minA);
mux8 muxB(a1, a1sq, sa4, sa8, sd2_1, a3, a2qu,a1qu, cw[5:3], minB);
/* Choose the outputs of the ALU */
mux4 muxC(mout, sa2, a1sq, sc1, cw[7:6], c0);
mux4 muxD(sa8_1, sa5, a1qu, sd2, cw[9:8], c1);
assign sa2 = mout ^ a2;
assign sa4 = a1sq ^ a2;
assign sa5 = mout ^ a2sq ^ a0;
assign sa7 = a0 ^ a2;
assign sa8 = a1 ^ a3;
assign sa8_1 = mout ^ a0;
assign sc1 = mout ^ a3;
assign sd2 = a0qu ^ a1;
assign sd2_1 = a2sq ^ a3 ^ a1;
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_4_V
`define SKY130_FD_SC_LP__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2008 by Wilson Snyder.
module t (clk);
input clk;
integer cyc; initial cyc=1;
integer sum;
integer cpre;
always @ (posedge clk) begin
if (cyc!=0) begin
cpre = cyc;
cyc <= cyc + 1;
if (cyc==1) begin
if (mlog2(32'd0) != 32'd0) $stop;
if (mlog2(32'd1) != 32'd0) $stop;
if (mlog2(32'd3) != 32'd2) $stop;
sum <= 32'd0;
end
else if (cyc<90) begin
// (cyc) so if we trash the variable things will get upset.
sum <= mlog2(cyc) + sum * 32'd42;
if (cpre != cyc) $stop;
end
else if (cyc==90) begin
if (sum !== 32'h0f12bb51) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function integer mlog2;
input [31:0] value;
integer i;
begin
if(value < 32'd1) begin
mlog2 = 0;
end
else begin
value = value - 32'd1;
mlog2 = 0;
for(i=0;i<32;i=i+1) begin
if(value > 32'd0) begin
mlog2 = mlog2 + 1;
end
value = value >> 1;
end
end
end
endfunction
endmodule
|
`timescale 1ns / 1ps
/*
* Module: InstructionMemory
*
* Implements read-only instruction memory
* Memory contents are initialized from the file "ImemInit.v"
*/
module InstructionMemory(Data, Address);
parameter T_rd = 20;
parameter MemSize = 40;
output [31:0] Data;
input [31:0] Address;
reg [31:0] Data;
/*
* ECEN 350 Processor Test Functions
* Texas A&M University
*/
always @ (Address) begin
case(Address)
/*
* Test Program 1:
* Sums $a0 words starting at $a1. Stores the sum at the end of the array
* Tests add, addi, lw, sw, beq
*/
/*
main:
li $t0, 50 # Initialize the array to (50, 40, 30)
sw $t0, 0($0) # Store first value
li $t0, 40
sw $t0, 4($0) # Store Second Value
li $t0, 30
sw $t0, 8($0) # Store Third Value
li $a0, 0 # address of array
li $a1, 3 # 3 values to sum
TestProg1:
add $t0, $0, $0 # This is the sum
add $t1, $0, $a0 # This is our array pointer
add $t2, $0, $0 # This is our index counter
P1Loop: beq $t2, $a1, P1Done # Our loop
lw $t3, 0($t1) # Load Array[i]
add $t0, $t0, $t3 # Add it into the sum
add $t1, $t1, 4 # Next address
add $t2, $t2, 1 # Next index
j P1Loop # Jump to loop
P1Done: sw $t0, 0($t1) # Store the sum at end of array
lw $t0, 12($0) # Load Final Value
nop # Complete
*/
32'h00: Data = 32'h34080032;
32'h04: Data = 32'hac080000;
32'h08: Data = 32'h34080028;
32'h0C: Data = 32'hac080004;
32'h10: Data = 32'h3408001e;
32'h14: Data = 32'hac080008;
32'h18: Data = 32'h34040000;
32'h1C: Data = 32'h34050003;
32'h20: Data = 32'h00004020;
32'h24: Data = 32'h00044820;
32'h28: Data = 32'h00005020;
32'h2C: Data = 32'h11450005;
32'h30: Data = 32'h8d2b0000;
32'h34: Data = 32'h010b4020;
32'h38: Data = 32'h21290004;
32'h3C: Data = 32'h214a0001;
32'h40: Data = 32'h0800000b;
32'h44: Data = 32'had280000;
32'h48: Data = 32'h8c08000c;
32'h4C: Data = 32'h00000000;
/*
* Test Program 2:
* Does some arithmetic computations and stores result in memory
*/
/*
main2:
li $a0, 32 # Address of memory to store result
TestProg2:
add $2, $0, 1 # $2 = 1
sub $3, $0, $2 # $3 = -1
slt $5, $3, $0 # $5 = 1
add $6, $2, $5 # $6 = 2
or $7, $5, $6 # $7 = 3
sub $8, $5, $7 # $8 = -2
and $9, $8, $7 # $9 = 2
sw $9, 0($a0) # Store $9 in DMem[8]
lw $9, 32($0) # Load Final Value
nop # Complete
*/
32'h60: Data = 32'h34040020;
32'h64: Data = 32'h20020001;
32'h68: Data = 32'h00021822;
32'h6C: Data = 32'h0060282a;
32'h70: Data = 32'h00453020;
32'h74: Data = 32'h00a63825;
32'h78: Data = 32'h00a74022;
32'h7C: Data = 32'h01074824;
32'h80: Data = 32'hac890000;
32'h84: Data = 32'h8c090020;
32'h88: Data = 32'h00000000;
/*
* Test Program 3
* Test Immediate Function
*/
/*
TestProg3:
li $a0, 0xfeedbeef # $a0 = 0xfeedbeef
sw $a0, 36($0) # Store $a0 in DMem[9]
addi $a1, $a0, -2656 # $a1 = 0xfeedb48f
sw $a1, 40($0) # Store $a1 in DMem[10]
addiu $a1, $a0, -2656 # $a1 = 0xfeedb48f
sw $a1, 44($0) # Store $a1 in DMem[11]
andi $a1, $a0, 0xf5a0 # $a1 = 0xb4a0
sw $a1, 48($0) # Store $a1 in DMem[12]
sll $a1, $a0, 5 # $a1 = 0xddb7dde0
sw $a1, 52($0) # Store $a1 in DMem[13]
srl $a1, $a0, 5 # $a1 = 0x07f76df7
sw $a1, 56($0) # Store $a1 in DMem[14]
sra $a1, $a0, 5 # $a1 = 0xfff76df7
sw $a1, 60($0) # Store $a1 in DMem[15]
slti $a1, $a0, 1 # $a1 = 1
sw $a1, 64($0) # Store $a1 in DMem[16]
slti $a1, $a1, -1 # $a1 = 0
sw $a1, 68($0) # Store $a1 in DMem[17]
sltiu $a1, $a0, 1 # $a1 = 0
sw $a1, 72($0) # Store $a1 in DMem[18]
sltiu $a1, $a1, -1 # $a1 = 1
sw $a1, 76($0) # Store $a1 in DMem[19]
xori $a1, $a0, 0xf5a0 # $a1 = 0xfeed4b4f
sw $a1, 80($0) # Store $a1 in DMem[20]
lw $a0, 36($0) # Load Value to test
lw $a1, 40($0) # Load Value to test
lw $a1, 44($0) # Load Value to test
lw $a1, 48($0) # Load Value to test
lw $a1, 52($0) # Load Value to test
lw $a1, 56($0) # Load Value to test
lw $a1, 60($0) # Load Value to test
lw $a1, 64($0) # Load Value to test
lw $a1, 68($0) # Load Value to test
lw $a1, 72($0) # Load Value to test
lw $a1, 76($0) # Load Value to test
lw $a1, 80($0) # Load Value to test
nop # Complete
*/
32'hA0: Data = 32'h3c01feed;
32'hA4: Data = 32'h3424beef;
32'hA8: Data = 32'hac040024;
32'hAC: Data = 32'h2085f5a0;
32'hB0: Data = 32'hac050028;
32'hB4: Data = 32'h2485f5a0;
32'hB8: Data = 32'hac05002c;
32'hBC: Data = 32'h3085f5a0;
32'hC0: Data = 32'hac050030;
32'hC4: Data = 32'h00042940;
32'hC8: Data = 32'hac050034;
32'hCC: Data = 32'h00042942;
32'hD0: Data = 32'hac050038;
32'hD4: Data = 32'h00042943;
32'hD8: Data = 32'hac05003c;
32'hDC: Data = 32'h28850001;
32'hE0: Data = 32'hac050040;
32'hE4: Data = 32'h28a5ffff;
32'hE8: Data = 32'hac050044;
32'hEC: Data = 32'h2c850001;
32'hF0: Data = 32'hac050048;
32'hF4: Data = 32'h2ca5ffff;
32'hF8: Data = 32'hac05004c;
32'hFC: Data = 32'h3885f5a0;
32'h100: Data = 32'hac050050;
32'h104: Data = 32'h8c040024;
32'h108: Data = 32'h8c050028;
32'h10C: Data = 32'h8c05002c;
32'h110: Data = 32'h8c050030;
32'h114: Data = 32'h8c050034;
32'h118: Data = 32'h8c050038;
32'h11C: Data = 32'h8c05003c;
32'h120: Data = 32'h8c050040;
32'h124: Data = 32'h8c050044;
32'h128: Data = 32'h8c050048;
32'h12C: Data = 32'h8c05004c;
32'h130: Data = 32'h8c050050;
32'h134: Data = 32'h00000000;
/*
* Test Program 4
* Test jal and jr
*/
/*
TestProg4:
li $t1, 0xfeed # $t1 = 0xfeed
li $t0, 0x190 # Load address of P4jr
jr $t0 # Jump to P4jr
li $t1, 0 # Check for failure to jump
P4jr: sw $t1, 84($0) # $t1 should be 0xfeed if successful
li $t0, 0xcafe # $t1 = 0xcafe
jal P4Jal # Jump to P4Jal
li $t0, 0xbabe # Check for failure to jump
P4Jal: sw $t0, 88($0) # $t0 should be 0xcafe if successful
li $t2, 0xface # $t2 = 0xface
j P4Skip # Jump to P4Skip
li $t2, 0
P4Skip: sw $t2, 92($0) # $t2 should be 0xface if successful
sw $ra, 96($0) # Store $ra
lw $t0, 84($0) # Load value for check
lw $t1, 88($0) # Load value for check
lw $t2, 92($0) # Load value for check
lw $ra, 96($0) # Load value for check
*/
32'h180: Data = 32'h3409feed;
32'h184: Data = 32'h34080190;
32'h188: Data = 32'h01000008;
32'h18C: Data = 32'h34090000;
32'h190: Data = 32'hac090054;
32'h194: Data = 32'h3408cafe;
32'h198: Data = 32'h0c000068;
32'h19C: Data = 32'h3408babe;
32'h1A0: Data = 32'hac080058;
32'h1A4: Data = 32'h340aface;
32'h1A8: Data = 32'h0800006c;
32'h1AC: Data = 32'h340a0000;
32'h1B0: Data = 32'hac0a005c;
32'h1B4: Data = 32'hac1f0060;
32'h1B8: Data = 32'h8c080054;
32'h1BC: Data = 32'h8c090058;
32'h1C0: Data = 32'h8c0a005c;
32'h1C4: Data = 32'h8c1f0060;
32'h1C8: Data = 32'h00000000;
/*
* Test Program 5
* Tests mula using wavelet transform
*/
/*
TestProg5:
li $2, 1 # $1 = 1
li $3, 0 # $2 = -1
li $20, 0 # $20 = 0 (result)
li $4, 5 # Load wavelet part 1
li $5, 7 # Load wavelet part 2
li $6, 2 # Load wavelet part 3
li $7, 9 # Load wavelet part 4
mula $20, $4, $2 # Perform convolution
mula $20, $5, $2
mula $20, $6, $0
mula $20, $7, $0
sw $20, 104($0) # Save result
li $20, 0 # Reset result
mula $20, $4, $0 # Perform convolution
mula $20, $5, $0
mula $20, $6, $2
mula $20, $7, $2
sw $20, 108($0) # Save result
li $20, 0 # Reset result
mula $20, $4, $2 # Perform convolution
mula $20, $5, $0
mula $20, $6, $2
mula $20, $7, $0
sw $20, 112($0) # Save result
li $20, 0 # Reset result
mula $20, $4, $0 # Perform convolution
mula $20, $5, $2
mula $20, $6, $0
mula $20, $7, $2
sw $20, 116($0) # Save result
lw $t0, 104($0) # Load value for check
lw $t0, 108($0) # Load value for check
lw $t0, 112($0) # Load value for check
lw $t0, 116($0) # Load value for check
*/
32'h200: Data = 32'h34020001;
32'h204: Data = 32'h34030000;
32'h208: Data = 32'h34140000;
32'h20C: Data = 32'h34040005;
32'h210: Data = 32'h34050007;
32'h214: Data = 32'h34060002;
32'h218: Data = 32'h34070009;
32'h21C: Data = 32'h0082a038;
32'h220: Data = 32'h00a2a038;
32'h224: Data = 32'h00c0a038;
32'h228: Data = 32'h00e0a038;
32'h22C: Data = 32'hac140068;
32'h230: Data = 32'h34140000;
32'h234: Data = 32'h0080a038;
32'h238: Data = 32'h00a0a038;
32'h23C: Data = 32'h00c2a038;
32'h240: Data = 32'h00e2a038;
32'h244: Data = 32'hac14006c;
32'h248: Data = 32'h34140000;
32'h24C: Data = 32'h0082a038;
32'h250: Data = 32'h00a0a038;
32'h254: Data = 32'h00c2a038;
32'h258: Data = 32'h00e0a038;
32'h25C: Data = 32'hac140070;
32'h260: Data = 32'h34140000;
32'h264: Data = 32'h0080a038;
32'h268: Data = 32'h00a2a038;
32'h26C: Data = 32'h00c0a038;
32'h270: Data = 32'h00e2a038;
32'h274: Data = 32'hac140074;
32'h278: Data = 32'h8c080068;
32'h27C: Data = 32'h8c08006c;
32'h280: Data = 32'h8c080070;
32'h284: Data = 32'h8c080074;
/*
* Test Program 6
* Tests Overflow Exceptions
*/
/*
Test4-1:
li $t0, -2147450880
add $t0, $t0, $t0
lw $t0, 4($0)
Test4-2:
li $t0, 2147450879
add $t0, $t0, $t0
lw $t0, 4($0)
Test 4-3:
lw $t0, 4($0)
li $t0, -2147483648
li $t1, 1
sub $t0, $t0, $t1
lw $t0, 4($0)
Test 4-4:
li $t0, 2147483647
mula $t0, $t0, $t0
lw $t0, 4($0)
*/
32'h300: Data = 32'h3c018000;
32'h304: Data = 32'h34288000;
32'h308: Data = 32'h01084020;
32'h30C: Data = 32'h8c080004;
32'h310: Data = 32'h3c017fff;
32'h314: Data = 32'h34287fff;
32'h318: Data = 32'h01084020;
32'h31C: Data = 32'h8c080004;
32'h320: Data = 32'h8c080004;
32'h324: Data = 32'h3c088000;
32'h328: Data = 32'h34090001;
32'h32C: Data = 32'h01094022;
32'h330: Data = 32'h8c080004;
32'h334: Data = 32'h3c017FFF;
32'h338: Data = 32'h3428FFFF;
32'h33C: Data = 32'h01084038;
32'h340: Data = 32'h8c080004;
/*
* Overflow Exception
*/
/*
lw $t0, 0($0)
*/
32'hF0000000: Data = 32'h8c080000;
default: Data = 32'hXXXXXXXX;
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
pmod_spi_cs,
pmod_spi_miso,
pmod_spi_clk,
pmod_spi_convst,
pmod_gpio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
output pmod_spi_cs;
input pmod_spi_miso;
output pmod_spi_clk;
output pmod_spi_convst;
input pmod_gpio;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t),
.dio_i(gpio_o),
.dio_o(gpio_i),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.pmod_spi_cs (pmod_spi_cs),
.pmod_spi_miso (pmod_spi_miso),
.pmod_spi_clk (pmod_spi_clk),
.pmod_spi_convst (pmod_spi_convst),
.pmod_gpio (pmod_gpio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
//----------------------------------------------------------------------------
// VSYNC Generator - Sub-Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: v_sync.v
//
// Description:
// This is the VSYNC signal generator. It generates
// the appropriate VSYNC signal for the target TFT display. The core
// of this module is a state machine that controls 4 counters and the
// VSYNC and V_DE signals.
//
// Design Notes:
// -- Input clock is (~HSYNC)
// -- Input rst is vsync_rst signal generated from the h_sync.v module
// -- V_DE is and with H_DE to generate DE signal for the TFT display
// -- v_bp_cnt_tc is the terminal count of the back porch time counter. Used to
// -- generate get_line_start pulse.
// -- v_l_cnt_tc is the terminal count of the line time counter. Used to not
// -- generate get_line_start pulse.
//
//-----------------------------------------------------------------------------
// Structure:
// -- v_sync.v
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/ 100 ps
module v_sync(
clk, // I
clk_stb, // I
rst, // I
VSYNC, // O
V_DE, // O
v_bp_cnt_tc, // O
v_l_cnt_tc); // O
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input clk;
input clk_stb;
input rst;
output VSYNC;
output V_DE;
output v_bp_cnt_tc;
output v_l_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
reg V_DE;
reg VSYNC;
reg [0:1] v_p_cnt; // 2-bit counter (2 HSYNCs for pulse time)
reg [0:4] v_bp_cnt; // 5-bit counter (31 HSYNCs for back porch time)
reg [0:8] v_l_cnt; // 9-bit counter (480 HSYNCs for line time)
reg [0:3] v_fp_cnt; // 4-bit counter (12 HSYNCs for front porch time)
reg v_p_cnt_ce;
reg v_bp_cnt_ce;
reg v_l_cnt_ce;
reg v_fp_cnt_ce;
reg v_p_cnt_clr;
reg v_bp_cnt_clr;
reg v_l_cnt_clr;
reg v_fp_cnt_clr;
reg v_p_cnt_tc;
reg v_bp_cnt_tc;
reg v_l_cnt_tc;
reg v_fp_cnt_tc;
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - State Declaration
///////////////////////////////////////////////////////////////////////////////
parameter [0:4] SET_COUNTERS = 5'b00001;
parameter [0:4] PULSE = 5'b00010;
parameter [0:4] BACK_PORCH = 5'b00100;
parameter [0:4] LINE = 5'b01000;
parameter [0:4] FRONT_PORCH = 5'b10000;
reg [0:4] VSYNC_cs /*synthesis syn_encoding="onehot"*/;
reg [0:4] VSYNC_ns;
///////////////////////////////////////////////////////////////////////////////
// clock enable State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
reg clk_stb_d1;
reg clk_ce_neg;
reg clk_ce_pos;
always @ (posedge clk)
begin
clk_stb_d1 <= clk_stb;
clk_ce_pos <= clk_stb & ~clk_stb_d1;
clk_ce_neg <= ~clk_stb & clk_stb_d1;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Sequential Block
///////////////////////////////////////////////////////////////////////////////
always @ (posedge clk)
begin
if (rst) VSYNC_cs = SET_COUNTERS;
else if (clk_ce_pos) VSYNC_cs = VSYNC_ns;
end
///////////////////////////////////////////////////////////////////////////////
// VSYNC State Machine - Combinatorial Block
///////////////////////////////////////////////////////////////////////////////
always @ (VSYNC_cs or v_p_cnt_tc or v_bp_cnt_tc or v_l_cnt_tc or v_fp_cnt_tc)
begin
case (VSYNC_cs)
/////////////////////////////////////////////////////////////////////////
// SET COUNTERS STATE
// -- Clear and de-enable all counters on frame_start signal
/////////////////////////////////////////////////////////////////////////
SET_COUNTERS: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = PULSE;
end
/////////////////////////////////////////////////////////////////////////
// PULSE STATE
// -- Enable pulse counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
PULSE: begin
v_p_cnt_ce = 1;
v_p_cnt_clr = 0;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 0;
V_DE = 0;
if (v_p_cnt_tc == 0) VSYNC_ns = PULSE;
else VSYNC_ns = BACK_PORCH;
end
/////////////////////////////////////////////////////////////////////////
// BACK PORCH STATE
// -- Enable back porch counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
BACK_PORCH: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 1;
v_bp_cnt_clr = 0;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 0;
if (v_bp_cnt_tc == 0) VSYNC_ns = BACK_PORCH;
else VSYNC_ns = LINE;
end
/////////////////////////////////////////////////////////////////////////
// LINE STATE
// -- Enable line counter
// -- De-enable others
/////////////////////////////////////////////////////////////////////////
LINE: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 1;
v_l_cnt_clr = 0;
v_fp_cnt_ce = 0;
v_fp_cnt_clr = 1;
VSYNC = 1;
V_DE = 1;
if (v_l_cnt_tc == 0) VSYNC_ns = LINE;
else VSYNC_ns = FRONT_PORCH;
end
/////////////////////////////////////////////////////////////////////////
// FRONT PORCH STATE
// -- Enable front porch counter
// -- De-enable others
// -- Wraps to PULSE state
/////////////////////////////////////////////////////////////////////////
FRONT_PORCH: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
if (v_fp_cnt_tc == 0) VSYNC_ns = FRONT_PORCH;
else VSYNC_ns = PULSE;
end
/////////////////////////////////////////////////////////////////////////
// DEFAULT STATE
/////////////////////////////////////////////////////////////////////////
default: begin
v_p_cnt_ce = 0;
v_p_cnt_clr = 1;
v_bp_cnt_ce = 0;
v_bp_cnt_clr = 1;
v_l_cnt_ce = 0;
v_l_cnt_clr = 1;
v_fp_cnt_ce = 1;
v_fp_cnt_clr = 0;
VSYNC = 1;
V_DE = 0;
VSYNC_ns = SET_COUNTERS;
end
endcase
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Pulse Counter - Counts 2 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_p_cnt_clr) begin
v_p_cnt = 2'b0;
v_p_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_p_cnt_ce) begin
if (v_p_cnt == 1) begin
v_p_cnt = v_p_cnt + 1;
v_p_cnt_tc = 1;
end
else begin
v_p_cnt = v_p_cnt + 1;
v_p_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Back Porch Counter - Counts 31 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_bp_cnt_clr) begin
v_bp_cnt = 5'b0;
v_bp_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_bp_cnt_ce) begin
if (v_bp_cnt == 30) begin
v_bp_cnt = v_bp_cnt + 1;
v_bp_cnt_tc = 1;
end
else begin
v_bp_cnt = v_bp_cnt + 1;
v_bp_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Line Counter - Counts 480 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_l_cnt_clr) begin
v_l_cnt = 9'b0;
v_l_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_l_cnt_ce) begin
if (v_l_cnt == 479) begin
v_l_cnt = v_l_cnt + 1;
v_l_cnt_tc = 1;
end
else begin
v_l_cnt = v_l_cnt + 1;
v_l_cnt_tc = 0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// Vertical Front Porch Counter - Counts 12 clocks(~HSYNC) for pulse time
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if (v_fp_cnt_clr) begin
v_fp_cnt = 4'b0;
v_fp_cnt_tc = 0;
end
else if (clk_ce_neg) begin
if (v_fp_cnt_ce) begin
if (v_fp_cnt == 11) begin
v_fp_cnt = v_fp_cnt + 1;
v_fp_cnt_tc = 1;
end
else begin
v_fp_cnt = v_fp_cnt + 1;
v_fp_cnt_tc = 0;
end
end
end
end
endmodule
|
module finished_wf
(/*AUTOARG*/
// Outputs
fetchwave_wf_done_en, fetchwave_wf_done_wf_id,
max_instr_inflight_array,
// Inputs
clk, rst, f_decode_wfid, f_sgpr_alu_wr_done_wfid,
f_vgpr_alu_wr_done_wfid, alu_wfid, f_salu_branch_wfid, f_decode_valid,
f_decode_wf_halt, f_vgpr_alu_wr_done, f_sgpr_alu_wr_done, alu_valid,
f_salu_branch_en, mem_wait_arry
);
input clk,rst;
input [`WF_ID_LENGTH-1:0] f_decode_wfid, f_sgpr_alu_wr_done_wfid,
f_vgpr_alu_wr_done_wfid, alu_wfid,
f_salu_branch_wfid;
input f_decode_valid, f_decode_wf_halt, f_vgpr_alu_wr_done,
f_sgpr_alu_wr_done, alu_valid, f_salu_branch_en;
input [`WF_PER_CU-1:0] mem_wait_arry;
output fetchwave_wf_done_en;
output [`WF_ID_LENGTH-1:0] fetchwave_wf_done_wf_id;
output [`WF_PER_CU-1:0] max_instr_inflight_array;
wire decode_wf_halt_valid;
wire [`WF_PER_CU-1:0] decoded_retired_sgpr, decoded_retired_vgpr,
decoded_retired_branch;
wire [`WF_PER_CU-1:0] decoded_decode_wf_halt, decoded_decode_valid,
decoded_wf_done, decoded_no_inflight_instr;
wire [`WF_PER_CU-1:0] done_wf_array;
wire [`WF_PER_CU-1:0] halted_reg_out, halted_reg_in, halted_reg_wr_en;
wire [`WF_PER_CU-1:0] decoded_alu_valid;
// Decoder for the retired instructions
decoder_6b_40b_en decoder_retired_sgpr
(
.addr_in(f_sgpr_alu_wr_done_wfid),
.out(decoded_retired_sgpr),
.en(f_sgpr_alu_wr_done)
);
decoder_6b_40b_en decoder_retired_vgpr
(
.addr_in(f_vgpr_alu_wr_done_wfid),
.out(decoded_retired_vgpr),
.en(f_vgpr_alu_wr_done)
);
decoder_6b_40b_en decoder_retired_branch
(
.addr_in(f_salu_branch_wfid),
.out(decoded_retired_branch),
.en(f_salu_branch_en)
);
// Decoder for the issued instructions
decoder_6b_40b_en decoder_issued_inst
(
.addr_in(alu_wfid),
.out(decoded_alu_valid),
.en(alu_valid)
);
// Decoder for the halt signal
decoder_6b_40b_en decode_wf_halt_decoder
(
.addr_in(f_decode_wfid),
.out(decoded_decode_wf_halt),
.en(decode_wf_halt_valid)
);
decoder_6b_40b_en decode_wf_halt_decoder_valid
(
.addr_in(f_decode_wfid),
.out(decoded_decode_valid),
.en(f_decode_valid)
);
// Decoder for the done wf signal
decoder_6b_40b_en decode_finished_wf
(
.addr_in(fetchwave_wf_done_wf_id),
.out(decoded_wf_done),
.en(fetchwave_wf_done_en)
);
// Register to record witch registers had a halt signals
dff_en halted_reg[`WF_PER_CU-1:0]
(
.q(halted_reg_out),
.d(halted_reg_in),
.en(halted_reg_wr_en),
.clk(clk),
.rst(rst)
);
// Arbiter to chose witch finished wf signal will be issued
arbiter finished_arbiter
(
.issued_en(fetchwave_wf_done_en),
.issued_wf_id(fetchwave_wf_done_wf_id),
.input_arry(done_wf_array),
.choosen_valid(fetchwave_wf_done_en),
.choosen_wf_id(fetchwave_wf_done_wf_id),
.clk(clk),
.rst(rst)
);
// Counter for the inflight instructions
inflight_instr_counter inflight_instr_counters[`WF_PER_CU-1:0]
(
.clk(clk),
.rst(rst),
// Input from retired instructions
.retire_vgpr_1_en(decoded_retired_vgpr),
.retire_branch_en(decoded_retired_branch),
.retire_sgpr_en(decoded_retired_sgpr),
// Input from issued instructions
.issued_en(decoded_alu_valid),
// Output
.no_inflight_instr_flag(decoded_no_inflight_instr),
.max_inflight_instr_flag(max_instr_inflight_array)
);
assign decode_wf_halt_valid = f_decode_valid && f_decode_wf_halt;
assign done_wf_array = halted_reg_out & decoded_no_inflight_instr & ~mem_wait_arry;
assign halted_reg_in = decoded_decode_wf_halt | (~decoded_wf_done & halted_reg_out);
assign halted_reg_wr_en = decoded_decode_valid | decoded_wf_done;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFXBP_PP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_PP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx2mb_link_ctr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* pcx2mb_link_cnt.v: A counter to keep track of outstanding transactions
* to one of the five destinations of the PCX request. This
* counter will be instantiated 5 times.
*
* The core has a link credit of 2 transactions. However, it will
* speculatively send a third transaction, assuming that a grant
* will be received in time. If this block is not ready to grant
* the first transaction, then the third one must be dropped,
* because the core will re-send it.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: pcx2mb_link_ctr.v,v 1.1 2007/06/30 00:23:40 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_link_ctr (
// Outputs
request_mask_pa,
// Inputs
rclk,
reset_l,
pcx_req_pa,
pcx_req_px,
pcx_atom_px,
pcx_grant_px
);
output request_mask_pa;
input rclk;
input reset_l;
input pcx_req_pa;
input pcx_req_px;
input pcx_atom_px;
input pcx_grant_px;
reg [1:0] link_count_pa;
wire request_mask_pa;
wire count_inc;
wire count_dec;
assign count_inc = pcx_req_pa || (pcx_req_px && pcx_atom_px);
assign count_dec = pcx_grant_px;
always @(posedge rclk) begin
if (!reset_l) begin
link_count_pa <= 2'b00;
end
else if (count_inc && count_dec) begin
link_count_pa <= link_count_pa;
end
else if (count_inc && !link_count_pa[1]) begin
link_count_pa <= link_count_pa + 2'b01;
end
else if (count_dec) begin
link_count_pa <= link_count_pa - 2'b01;
end
else begin
link_count_pa <= link_count_pa;
end
end
assign request_mask_pa = link_count_pa[1];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_Mark2();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg begin_operation;
reg ack_operation;
reg [2:0] operation;
//Oper_Start_in signals
reg [W-1:0] Data_1;
reg [W-1:0] Data_2;
reg [1:0] region_flag;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
reg add_subt;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire operation_ready;
wire zero_flag;
wire NaN_flag;
wire [W-1:0] op_result;
wire busy;
// LOS CODIGOS PARA LAS OPERACIONES
localparam [2:0] FPADD = 3'b000,
FPSUB = 3'b001,
FPCOS = 3'b010,
FPSEN = 3'b011,
FPMULT = 3'b100;
// LAS REGIONES DEL ANGULO
localparam [1:0] IoIV1 = 2'b00,
II = 2'b01,
III = 2'b10,
IoIV2 = 2'b11;
localparam [1:0] ROUNDING_MODE_TRUNCT = 2'b00,
ROUNDING_MODE_NEG_INF = 2'b01,
ROUNDING_MODE_POS_INF = 2'b10;
`ifdef FPUv2_behav
FPU_Interface2 #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_FPU_Interface (
.clk (clk),
.rst (rst),
.begin_operation (begin_operation),
.ack_operation (ack_operation),
.operation (operation),
.region_flag (region_flag),
.Data_1 (Data_1),
.Data_2 (Data_2),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.NaN_flag (NaN_flag),
.operation_ready (operation_ready),
.op_result (op_result),
.busy (busy)
);
`endif
`ifdef DW1_SINGLE
integer PIPE=0;
FPU_Multiplication_Function_W32_EW8_SW23 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef DW1_DOUBLE
integer PIPE=0;
FPU_Multiplication_Function_W64_EW11_SW52 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef KOA2_SINGLE
integer PIPE=0;
FPU_Multiplication_Function_W32_EW8_SW23 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef KOA2_DOUBLE
integer PIPE=0;
FPU_Multiplication_Function_W64_EW11_SW52 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef KOA2_SINGLE
integer PIPE=0;
FPU_Multiplication_Function_W32_EW8_SW23 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef KOA2_DOUBLE
integer PIPE=0;
FPU_Multiplication_Function_W64_EW11_SW52 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef RKOA1_SINGLE
integer PIPE=0;
FPU_Multiplication_Function_W32_EW8_SW23 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef RKOA1_DOUBLE
integer PIPE=0;
FPU_Multiplication_Function_W64_EW11_SW52 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef RKOA2_SINGLE
integer PIPE=0;
FPU_Multiplication_Function_W32_EW8_SW23 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef RKOA2_DOUBLE
integer PIPE=0;
FPU_Multiplication_Function_W64_EW11_SW52 uut (
.clk (clk),
.rst (rst),
.beg_FSM (begin_operation),
.ack_FSM (ack_operation),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef FPADD1_SINGLE
integer PIPE=0;
FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 uut(
.clk(clk),
.rst(rst),
.beg_FSM(begin_operation),
.ack_FSM(ack_operation),
.Data_X(Data_1),
.Data_Y(Data_2),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(operation_ready),
.final_result_ieee(op_result)
);
`endif
`ifdef FPADD1_DOUBLE
integer PIPE=0;
FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 uut(
.clk(clk),
.rst(rst),
.beg_FSM(begin_operation),
.ack_FSM(ack_operation),
.Data_X(Data_1),
.Data_Y(Data_2),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(operation_ready),
.final_result_ieee(op_result)
);
`endif
`ifdef FPADD2_SINGLE
integer PIPE=1;
FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 inst_uut (
.clk (clk),
.rst (rst),
.beg_OP (begin_operation),
.Data_X (Data_1),
.Data_Y (Data_2),
.add_subt (add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef FPADD2_DOUBLE
integer PIPE=1;
FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 inst_uut (
.clk (clk),
.rst (rst),
.beg_OP (begin_operation),
.Data_X (Data_1),
.Data_Y (Data_2),
.add_subt (add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (operation_ready),
.final_result_ieee (op_result)
);
`endif
`ifdef CORDIC1_SINGLE
integer PIPE=0;
CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5 uut (
.clk (clk),
.rst (rst),
.beg_fsm_cordic (begin_operation),
.ack_cordic (ack_operation),
.operation (1'b1),
.data_in (Data_1),
.shift_region_flag (region_flag),
.r_mode (r_mode),
.ready_cordic (operation_ready),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.data_output (op_result)
);
`endif
`ifdef CORDIC1_DOUBLE
integer PIPE=0;
CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6 uut (
.clk (clk),
.rst (rst),
.beg_fsm_cordic (begin_operation),
.ack_cordic (ack_operation),
.operation (1'b1),
.data_in (Data_1),
.shift_region_flag (region_flag),
.r_mode (r_mode),
.ready_cordic (operation_ready),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.data_output (op_result)
);
`endif
`ifdef CORDIC2_SINGLE
CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 uut (
.clk (clk),
.rst (rst),
.beg_fsm_cordic (begin_operation),
.ack_cordic (ack_operation),
.operation (1'b1),
.data_in (Data_1),
.shift_region_flag (region_flag),
.ready_cordic (operation_ready),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.busy (busy),
.data_output (op_result)
);
`endif
`ifdef CORDIC2_DOUBLE
CORDIC_Arch3_W64_EW11_SW52_SWR55_EWR6 uut (
.clk (clk),
.rst (rst),
.beg_fsm_cordic (begin_operation),
.ack_cordic (ack_operation),
.operation (1'b1),
.data_in (Data_1),
.shift_region_flag (region_flag),
.ready_cordic (operation_ready),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.busy (busy),
.data_output (op_result)
);
`endif
reg [W-1:0] Array_IN_1 [0:(((2**PERIOD))-1)];
reg [W-1:0] Array_IN_2 [0:(((2**PERIOD))-1)];
integer contador;
integer FileSaveData;
integer FileSaveData_FLOAT;
initial begin
// Initialize Inputs
$vcdpluson;
clk = 0;
rst = 1;
r_mode=ROUNDING_MODE_TRUNCT;
begin_operation = 0;
ack_operation = 0;
Data_1 = 0;
Data_2 = 0;
region_flag = IoIV1;
add_subt =1'b0;
$display("------------------------OP--------------------------");
$display("------------------------ --------------------------");
$display("------------------------OP--------------------------");
#100;
rst = 0;
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
FileSaveData = $fopen("ResultadoXilinxFLMv2.txt","w");
FileSaveData_FLOAT = $fopen("ResultadoXilinxFLMv2F.txt","w");
if (PIPE) begin
run_PIPE(FileSaveData,FileSaveData_FLOAT,(2**PERIOD));
end else begin
run_Arch2(FileSaveData,FileSaveData_FLOAT,(2**PERIOD));
end
#100 rst = 0;
$finish;
$vcdplusclose;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #10 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer FData1;
input integer Vector_size;
begin
begin_operation = 0;
rst = 0;
#15 rst = 1;
#25 rst = 0;
// begin_operation = 0;
ack_operation = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
#(PERIOD/4) begin_operation = 1;
//Wait for the operation operation_ready
@(posedge operation_ready) begin
#(PERIOD+2);
ack_operation = 1;
#4;
$display("%h\n",op_result);
$fwrite(FDataO,"%h\n",op_result);
$display("%f\n",$bitstoshortreal(op_result));
`ifdef SINGLE
$fwrite(FData1,"%f\n",$bitstoshortreal(op_result));
`else
$fwrite(FData1,"%f\n",$bitstoreal(op_result));
`endif
end
@(negedge clk) begin
ack_operation = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
$fclose(FData1);
end
endtask
////////////////////////////TASK FOR THE PIPE ADDER/////////////////
////We need to read in a non-linear fashion, therefore
// we are going to write first the 3 first input operands,
// then, the normal running operation,
// and then the final procedure.
task run_PIPE;
input integer FData1;
input integer FData2;
input integer Vector_size2;
begin
begin_operation = 0;
rst = 0;
#15 rst = 1;
#25 rst = 0;
//begin_operation = 0;
contador = 0;
@(posedge clk)
begin_operation = 1;
@(posedge clk)
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
contador = contador + 1;
repeat(Vector_size2*2+6) @(posedge clk) begin
#(PERIOD/3);
if(~busy & ~rst) begin
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
contador = contador + 1;
end
if (operation_ready) begin
$fwrite(FData1,"%h\n",op_result);
`ifdef SINGLE
$fwrite(FData2,"%f\n",$bitstoshortreal(op_result));
`else
$fwrite(FData2,"%f\n",$bitstoreal(op_result));
`endif
end
end
begin_operation = 0;
$fclose(FData1);
$fclose(FData2);
end
endtask
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_misc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_misc(io_tdo_en ,bscan_hiz_l_in ,bscan_update_dr_in ,tdi ,
spare_misc_pad ,spare_misc_pad_to_core ,spare_misc_pindata ,
spare_misc_pin ,burnin ,io_burnin ,spare_misc_paddata ,
spare_misc_padoe ,vreg_selbg_l ,io_pmi ,tck2 ,pad_misc_bsi ,
pad_misc_se ,pad_misc_si ,pad_misc_so ,bscan_clock_dr_in ,ssi_miso
,ssi_mosi ,temp_trig ,jbus_arst_l ,jbus_adbginit_l ,ext_int_l ,
vdd_sense ,jbus_gdbginit_l ,bscan_shift_dr_out ,bscan_update_dr_out
,bscan_clock_dr_out ,bscan_mode_ctl_out ,pmi ,io_ext_int_l ,
pll_char_in ,jbus_grst_l ,jbus_gclk ,vss_sense ,clk_stretch ,
pwron_rst_l ,test_mode ,vddo ,io_trigin ,pmo ,pgrm_en ,io_test_mode
,clk_misc_cken ,hstl_vref ,tms ,pcm_misc_oe ,io_pwron_rst_l ,
io_tms ,io_pmo ,io_pgrm_en ,io_pll_char_in ,io_tdo ,jbi_io_ssi_sck
,jbi_io_ssi_mosi ,io_trst_l ,io_tck ,io_tdi ,io_temp_trig ,
spare_misc_pin_to_core ,io_jbi_ssi_miso ,tck ,tdo ,trst_l ,ssi_sck
,bscan_mode_ctl_in ,bscan_shift_dr_in ,bscan_hiz_l_out ,
pad_misc_bso ,io_tck2 ,spare_misc_pinoe ,io_vreg_selbg_l ,
io_clk_stretch ,trigin );
output [2:0] spare_misc_pad_to_core ;
input [2:0] spare_misc_paddata ;
input [2:0] spare_misc_padoe ;
inout [2:0] spare_misc_pad ;
output io_burnin ;
output io_pmi ;
output pad_misc_so ;
output bscan_shift_dr_out ;
output bscan_update_dr_out ;
output bscan_clock_dr_out ;
output bscan_mode_ctl_out ;
output io_ext_int_l ;
output io_trigin ;
output io_test_mode ;
output io_pwron_rst_l ;
output io_tms ;
output io_pgrm_en ;
output io_pll_char_in ;
output io_trst_l ;
output io_tck ;
output io_tdi ;
output io_temp_trig ;
output spare_misc_pin_to_core ;
output io_jbi_ssi_miso ;
output bscan_hiz_l_out ;
output pad_misc_bso ;
output io_tck2 ;
output io_vreg_selbg_l ;
output io_clk_stretch ;
input io_tdo_en ;
input bscan_hiz_l_in ;
input bscan_update_dr_in ;
input spare_misc_pindata ;
input pad_misc_bsi ;
input pad_misc_se ;
input pad_misc_si ;
input bscan_clock_dr_in ;
input jbus_arst_l ;
input jbus_adbginit_l ;
input jbus_gdbginit_l ;
input jbus_grst_l ;
input jbus_gclk ;
input vddo ;
input clk_misc_cken ;
input pcm_misc_oe ;
input io_pmo ;
input io_tdo ;
input jbi_io_ssi_sck ;
input jbi_io_ssi_mosi ;
input bscan_mode_ctl_in ;
input bscan_shift_dr_in ;
input spare_misc_pinoe ;
inout tdi ;
inout spare_misc_pin ;
inout burnin ;
inout vreg_selbg_l ;
inout tck2 ;
inout ssi_miso ;
inout ssi_mosi ;
inout temp_trig ;
inout ext_int_l ;
inout vdd_sense ;
inout pmi ;
inout pll_char_in ;
inout vss_sense ;
inout clk_stretch ;
inout pwron_rst_l ;
inout test_mode ;
inout pmo ;
inout pgrm_en ;
inout hstl_vref ;
inout tms ;
inout tck ;
inout tdo ;
inout trst_l ;
inout ssi_sck ;
inout trigin ;
supply1 vdd ;
supply0 vss ;
wire net282 ;
wire net300 ;
wire net283 ;
wire net301 ;
wire net284 ;
wire net302 ;
wire net285 ;
wire net286 ;
wire net287 ;
wire net288 ;
wire net305 ;
wire chunk1_so ;
wire chunk5_so ;
wire net296 ;
wire net297 ;
wire net412 ;
wire net298 ;
wire net413 ;
wire net299 ;
wire chunk2_bso ;
wire net0251 ;
wire chunk1_bso ;
wire net0254 ;
wire net324 ;
wire net0257 ;
wire net325 ;
wire net326 ;
wire net327 ;
wire net328 ;
wire net329 ;
wire reset_l ;
wire net330 ;
wire net338 ;
wire net339 ;
wire net340 ;
wire net341 ;
wire net342 ;
wire net343 ;
wire net344 ;
wire net346 ;
wire chunk3_bso ;
wire rclk ;
wire misc_si_1 ;
wire misc_si_2 ;
wire header_si ;
wire chunk2_so ;
wire net273 ;
bw_u1_minbuf_4x I141 (
.z (header_si ),
.a (misc_si_2 ) );
bw_clk_cl_misc_jbus pad_misc_header (
.arst_l (jbus_arst_l ),
.adbginit_l (jbus_adbginit_l ),
.se (pad_misc_se ),
.si (pad_misc_si ),
.cluster_grst_l (reset_l ),
.so (misc_si_1 ),
.dbginit_l (net273 ),
.rclk (rclk ),
.gclk (jbus_gclk ),
.cluster_cken (clk_misc_cken ),
.grst_l (jbus_grst_l ),
.gdbginit_l (jbus_gdbginit_l ) );
bw_u1_ckbuf_1p5x so_ckbuf (
.clk (net0251 ),
.rclk (rclk ) );
bw_u1_scanl_2x lockup_bso (
.so (net0254 ),
.sd (chunk1_bso ),
.ck (net341 ) );
bw_u1_minbuf_1x si_minbuf1 (
.z (misc_si_2 ),
.a (misc_si_1 ) );
bw_io_misc_rpt rpt0 (
.in2 (bscan_mode_ctl_in ),
.out2 (net343 ),
.out3 (net342 ),
.out4 (net341 ),
.out5 (net340 ),
.out6 (net339 ),
.out7 (net338 ),
.in3 (bscan_shift_dr_in ),
.in4 (bscan_clock_dr_in ),
.in5 (bscan_update_dr_in ),
.in6 (reset_l ),
.in7 (pad_misc_se ),
.in1 (bscan_hiz_l_in ),
.out1 (net344 ) );
bw_io_misc_rpt rpt1 (
.in2 (net343 ),
.out2 (net329 ),
.out3 (net328 ),
.out4 (net327 ),
.out5 (net326 ),
.out6 (net325 ),
.out7 (net324 ),
.in3 (net342 ),
.in4 (net341 ),
.in5 (net340 ),
.in6 (net339 ),
.in7 (net338 ),
.in1 (net344 ),
.out1 (net330 ) );
bw_io_misc_rpt rpt2 (
.in2 (net329 ),
.out2 (net287 ),
.out3 (net286 ),
.out4 (net285 ),
.out5 (net284 ),
.out6 (net283 ),
.out7 (net282 ),
.in3 (net328 ),
.in4 (net327 ),
.in5 (net326 ),
.in6 (net325 ),
.in7 (net324 ),
.in1 (net330 ),
.out1 (net288 ) );
bw_io_misc_rpt rpt3 (
.in2 (net287 ),
.out2 (net301 ),
.out3 (net300 ),
.out4 (net299 ),
.out5 (net298 ),
.out6 (net297 ),
.out7 (net296 ),
.in3 (net286 ),
.in4 (net285 ),
.in5 (net284 ),
.in6 (net283 ),
.in7 (net282 ),
.in1 (net288 ),
.out1 (net302 ) );
bw_io_misc_rpt rpt4 (
.in2 (net301 ),
.out2 (bscan_mode_ctl_out ),
.out3 (bscan_shift_dr_out ),
.out4 (bscan_clock_dr_out ),
.out5 (bscan_update_dr_out ),
.out6 (net346 ),
.out7 (net305 ),
.in3 (net300 ),
.in4 (net299 ),
.in5 (net298 ),
.in6 (vss ),
.in7 (vss ),
.in1 (net302 ),
.out1 (bscan_hiz_l_out ) );
bw_u1_buf_20x so_buf (
.z (pad_misc_so ),
.a (net0257 ) );
bw_u1_scanl_2x lockup_so (
.so (net0257 ),
.sd (chunk5_so ),
.ck (net0251 ) );
bw_io_hstl_drv hstl_vref_dummy (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.pad (hstl_vref ),
.sel_data_n (vss ),
.pad_up (vss ),
.pad_dn_l (vdd ),
.por (vss ),
.bsr_up (vss ),
.bsr_dn_l (vdd ),
.vddo (vddo ) );
bw_io_misc_chunk1 chunk1 (
.obsel ({vss ,vss } ),
.io_ext_int_l (io_ext_int_l ),
.spare_misc_pinoe (spare_misc_pinoe ),
.sel_bypass (vss ),
.vss_sense (vss_sense ),
.vdd_sense (vdd_sense ),
.test_mode (test_mode ),
.ext_int_l (ext_int_l ),
.temp_trig (temp_trig ),
.spare_misc_pindata (spare_misc_pindata ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.clk_stretch (clk_stretch ),
.hiz_l (net344 ),
.rst_val_dn (vdd ),
.rst_val_up (vdd ),
.reset_l (net339 ),
.mode_ctl (net343 ),
.update_dr (net340 ),
.io_test_mode (io_test_mode ),
.shift_dr (net342 ),
.clock_dr (net341 ),
.io_clk_stretch (io_clk_stretch ),
.por_l (vdd ),
.rst_io_l (vdd ),
.bsi (chunk2_bso ),
.se (net338 ),
.si (header_si ),
.so (chunk1_so ),
.bso (chunk1_bso ),
.clk (rclk ),
.io_pgrm_en (io_pgrm_en ),
.io_burnin (io_burnin ),
.burnin (burnin ),
.pgrm_en (pgrm_en ),
.io_temp_trig (io_temp_trig ),
.pwron_rst_l (pwron_rst_l ),
.io_pwron_rst_l (io_pwron_rst_l ),
.spare_misc_pin (spare_misc_pin ),
.spare_misc_pin_to_core (spare_misc_pin_to_core ) );
bw_io_misc_chunk2 chunk2 (
.obsel ({vss ,vss } ),
.io_pll_char_in (io_pll_char_in ),
.sel_bypass (vss ),
.tck2 (tck2 ),
.io_tck2 (io_tck2 ),
.pll_char_in (pll_char_in ),
.ssi_mosi (ssi_mosi ),
.jbi_io_ssi_mosi (jbi_io_ssi_mosi ),
.ssi_miso (ssi_miso ),
.io_jbi_ssi_miso (io_jbi_ssi_miso ),
.vddo (vddo ),
.vref (hstl_vref ),
.ckd (vss ),
.so (chunk2_so ),
.bso (chunk2_bso ),
.rst_val_up (vdd ),
.rst_val_dn (vdd ),
.reset_l (net325 ),
.si (chunk1_so ),
.se (net324 ),
.bsi (chunk3_bso ),
.rst_io_l (vdd ),
.hiz_l (net330 ),
.shift_dr (net328 ),
.update_dr (net326 ),
.clock_dr (net327 ),
.mode_ctl (net329 ),
.clk (rclk ),
.por_l (vdd ) );
bw_io_misc_chunk3 chunk3 (
.spare_misc_pad ({spare_misc_pad[0] } ),
.spare_misc_paddata ({spare_misc_paddata[0] } ),
.spare_misc_pad_to_core ({spare_misc_pad_to_core[0] } ),
.obsel ({vss ,vss } ),
.spare_misc_padoe ({spare_misc_padoe[0] } ),
.ssi_sck (ssi_sck ),
.jbi_io_ssi_sck (jbi_io_ssi_sck ),
.trigin (trigin ),
.io_trigin (io_trigin ),
.io_tms (io_tms ),
.io_vreg_selbg_l (io_vreg_selbg_l ),
.clk (rclk ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.rst_val_up (vdd ),
.tms (tms ),
.sel_bypass (vss ),
.mode_ctl (net287 ),
.rst_val_dn (vdd ),
.bsi (net412 ),
.clock_dr (net285 ),
.shift_dr (net286 ),
.hiz_l (net288 ),
.update_dr (net284 ),
.rst_io_l (vdd ),
.por_l (vdd ),
.se (net282 ),
.si (chunk2_so ),
.reset_l (net283 ),
.so (net413 ),
.bso (chunk3_bso ),
.hstl_vref (hstl_vref ),
.vreg_selbg_l (vreg_selbg_l ) );
bw_u1_buf_30x bso_buf (
.z (pad_misc_bso ),
.a (net0254 ) );
bw_io_misc_chunk5 chunk5 (
.spare_misc_pad ({spare_misc_pad[2:1] } ),
.spare_misc_paddata ({spare_misc_paddata[2:1] } ),
.obsel ({vss ,vss } ),
.spare_misc_padoe ({spare_misc_padoe[2:1] } ),
.spare_misc_pad_to_core ({spare_misc_pad_to_core[2:1] } ),
.clk (rclk ),
.sel_bypass (vss ),
.io_tdo_en (io_tdo_en ),
.ckd (vss ),
.vref (hstl_vref ),
.vddo (vddo ),
.io_tdo (io_tdo ),
.rst_val_up (vdd ),
.io_tdi (io_tdi ),
.mode_ctl (net301 ),
.rst_val_dn (vdd ),
.io_trst_l (io_trst_l ),
.bsi (pad_misc_bsi ),
.io_tck (io_tck ),
.clock_dr (net299 ),
.tck (tck ),
.shift_dr (net300 ),
.trst_l (trst_l ),
.hiz_l (net302 ),
.tdi (tdi ),
.update_dr (net298 ),
.rst_io_l (vdd ),
.por_l (vdd ),
.tdo (tdo ),
.se (net296 ),
.si (net413 ),
.reset_l (net297 ),
.so (chunk5_so ),
.bso (net412 ) );
bw_io_misc_chunk6 chunk6 (
.io_pmi (io_pmi ),
.pcm_misc_oe (pcm_misc_oe ),
.vddo (vddo ),
.pmo (pmo ),
.io_pmo (io_pmo ),
.por_l (vdd ),
.pmi (pmi ) );
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
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//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer with Packet FIFO
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_r_upsizer_pktfifo #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter C_CLK_CONV = 1'b0,
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1,
// Log2 of Up-Sizing ratio for data.
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Global Signals
input wire S_AXI_ACLK,
input wire M_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire M_AXI_ARESETN,
// Command Interface
input wire [C_AXI_ADDR_WIDTH-1:0] cmd_si_addr,
input wire [C_AXI_ID_WIDTH-1:0] cmd_si_id,
input wire [8-1:0] cmd_si_len,
input wire [3-1:0] cmd_si_size,
input wire [2-1:0] cmd_si_burst,
output wire cmd_ready,
// Slave Interface Write Address Port
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARREGION,
input wire [4-1:0] S_AXI_ARQOS,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [8-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [4-1:0] M_AXI_ARREGION,
output wire [4-1:0] M_AXI_ARQOS,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE
);
assign cmd_ready = 1'b1;
localparam integer P_SI_BYTES = C_S_AXI_DATA_WIDTH / 8;
localparam integer P_MI_BYTES = C_M_AXI_DATA_WIDTH / 8;
localparam integer P_MAX_BYTES = 1024 / 8;
localparam integer P_SI_SIZE = f_ceil_log2(P_SI_BYTES);
localparam integer P_MI_SIZE = f_ceil_log2(P_MI_BYTES);
localparam integer P_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer P_RATIO_LOG = f_ceil_log2(P_RATIO);
localparam integer P_NUM_BUF = (P_RATIO == 2) ? 4 : 8;
localparam integer P_BUF_LIMIT = P_NUM_BUF - 1;
localparam integer P_NUM_BUF_LOG = f_ceil_log2(P_NUM_BUF);
localparam integer P_M_RBUFFER_DEPTH = 512;
localparam integer P_M_RBUFFER_DEPTH_LOG = 9;
localparam integer P_S_RBUFFER_DEPTH = P_M_RBUFFER_DEPTH * P_RATIO;
localparam integer P_S_RBUFFER_DEPTH_LOG = f_ceil_log2(P_S_RBUFFER_DEPTH);
localparam integer P_M_RBUFFER_WORDS = P_M_RBUFFER_DEPTH / P_NUM_BUF;
localparam integer P_M_RBUFFER_WORDS_LOG = f_ceil_log2(P_M_RBUFFER_WORDS);
localparam integer P_S_RBUFFER_WORDS = P_M_RBUFFER_WORDS * P_RATIO;
localparam integer P_S_RBUFFER_WORDS_LOG = f_ceil_log2(P_S_RBUFFER_WORDS);
localparam integer P_M_RBUFFER_BYTES = P_M_RBUFFER_WORDS * P_MI_BYTES;
localparam integer P_M_RBUFFER_BYTES_LOG = f_ceil_log2(P_M_RBUFFER_BYTES);
localparam integer P_MAX_RBUFFER_BYTES_LOG = f_ceil_log2((P_M_RBUFFER_DEPTH / 4) * P_MAX_BYTES);
localparam [1:0] P_INCR = 2'b01, P_WRAP = 2'b10, P_FIXED = 2'b00;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NUM_RAMB = C_M_AXI_DATA_WIDTH / 32;
localparam integer P_S_RAMB_WIDTH = C_S_AXI_DATA_WIDTH / P_NUM_RAMB;
localparam integer P_S_RAMB_PWIDTH = (P_S_RAMB_WIDTH < 8) ? P_S_RAMB_WIDTH : ((P_SI_BYTES * 9) / P_NUM_RAMB);
localparam integer P_S_CMD_WIDTH = P_MI_SIZE+4 + C_AXI_ID_WIDTH + 4 + 3 + 8 + 3 + 2;
localparam integer P_M_CMD_WIDTH = P_MI_SIZE+4 + 8 + 3 + 2;
localparam integer P_ARFIFO_WIDTH = 29 + C_AXI_ADDR_WIDTH;
localparam integer P_COMMON_CLOCK = (C_CLK_CONV & C_AXI_IS_ACLK_ASYNC) ? 0 : 1;
genvar i;
genvar j;
reg S_AXI_ARREADY_i;
reg M_AXI_RREADY_i;
reg M_AXI_ARVALID_i;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR_i;
wire [7:0] M_AXI_ARLEN_i;
wire [2:0] M_AXI_ARSIZE_i;
wire [1:0] M_AXI_ARBURST_i;
wire M_AXI_ARLOCK_i;
wire ar_push;
wire ar_fifo_ready;
wire ar_fifo_valid;
wire ar_pop;
wire s_rbuf_en;
wire [P_NUM_RAMB-1:0] m_rbuf_en;
reg [P_NUM_BUF_LOG-1:0] s_buf;
reg [P_NUM_BUF_LOG-1:0] m_buf;
reg [P_NUM_BUF_LOG-1:0] buf_cnt;
wire buf_limit;
reg [7:0] s_rcnt;
wire [P_NUM_RAMB*16-1 : 0] s_rdata ;
wire [C_M_AXI_DATA_WIDTH-1 : 0] m_rdata ;
reg [1:0] s_rburst;
reg [2:0] s_rsize;
reg [3:0] s_wrap_cnt;
reg s_rvalid;
reg s_rvalid_d1;
reg s_rvalid_d2;
reg first_rvalid_d1;
reg s_rlast;
reg s_rlast_d1;
reg s_rlast_d2;
wire [1:0] s_rresp;
wire [3:0] s_rresp_i;
wire [1:0] m_rresp;
wire [3:0] m_rresp_i;
reg [1:0] s_rresp_reg;
reg [1:0] m_rresp_reg;
reg [1:0] s_rresp_d1;
reg [1:0] s_rresp_d2;
reg [1:0] s_rresp_first;
reg [1:0] m_rburst;
reg [2:0] m_rsize;
reg [3:0] m_wrap_cnt;
wire s_cmd_push;
wire s_cmd_pop;
wire s_cmd_empty;
wire s_cmd_full;
wire m_cmd_push;
wire m_cmd_pop;
wire m_cmd_empty;
wire m_cmd_full;
reg m_cmd_valid;
wire [P_S_CMD_WIDTH-1 : 0] s_ar_cmd;
wire [P_S_CMD_WIDTH-1 : 0] s_r_cmd;
wire [P_M_CMD_WIDTH-1 : 0] m_ar_cmd;
wire [P_M_CMD_WIDTH-1 : 0] m_r_cmd;
wire [P_MI_SIZE+4-1:0] s_cmd_addr;
wire [C_AXI_ID_WIDTH-1:0] s_cmd_id;
reg [C_AXI_ID_WIDTH-1:0] s_id_reg;
reg [C_AXI_ID_WIDTH-1:0] s_id_d1;
reg [C_AXI_ID_WIDTH-1:0] s_id_d2;
wire [3:0] s_cmd_conv_len;
reg [3:0] s_conv_len;
wire [2:0] s_cmd_conv_size;
reg [2:0] s_conv_size;
wire [7:0] s_cmd_len;
wire [2:0] s_cmd_size;
wire [1:0] s_cmd_burst;
wire [P_MI_SIZE+4-1:0] m_cmd_addr;
wire [C_AXI_ID_WIDTH-1:0] m_cmd_id;
wire [7:0] m_cmd_len;
wire [2:0] m_cmd_size;
wire [1:0] m_cmd_burst;
wire m_transfer;
wire rresp_fifo_push;
wire rresp_fifo_pop;
wire rresp_fifo_empty;
wire rresp_fifo_full;
reg rresp_wrap;
wire rresp_reuse;
reg s_rresp_fifo_stall;
reg m_rresp_fifo_stall;
wire s_eol;
reg [P_M_RBUFFER_BYTES_LOG-1:0] s_raddr;
reg [P_M_RBUFFER_BYTES_LOG-1:0] m_raddr;
wire [P_M_RBUFFER_BYTES_LOG-1:0] m_raddr_incr;
reg [P_M_RBUFFER_BYTES_LOG-1:0] s_wrap_addr;
reg [P_M_RBUFFER_BYTES_LOG-1:0] m_wrap_addr;
wire [13:0] s_rbuf_addr;
wire [13:0] m_rbuf_addr;
wire [3:0] m_rbuf_we;
reg large_incr_last;
reg [3:0] large_incr_mask;
wire m_aclk;
wire m_aresetn;
wire s_aresetn;
wire ar_fifo_s_aclk;
wire ar_fifo_m_aclk;
wire ar_fifo_aresetn;
wire s_fifo_rst;
wire m_fifo_rst;
wire rresp_fifo_clk;
wire rresp_fifo_wrclk;
wire rresp_fifo_rdclk;
wire rresp_fifo_rst;
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire fast_aclk;
reg reset_r;
reg s_reset_r;
reg m_reset_r;
reg fast_aresetn_r;
reg fast_reset_r;
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// RAMB SI-side port address
function [13:0] f_s_rbuf_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [1:0] burst,
input [P_NUM_BUF_LOG-1:0] s_buf
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] sparse_addr;
begin
if (burst == P_FIXED) begin
sparse_addr = addr;
end else begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 3], addr_i[0:0], addr_i[2:0]};
default: sparse_addr = addr_i;
endcase
4: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 4], addr_i[1:0], addr_i[3:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 4], addr_i[1:1], addr_i[3:0]};
default: sparse_addr = addr_i;
endcase
5: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 5], addr_i[2:0], addr_i[4:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 5], addr_i[2:1], addr_i[4:0]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 5], addr_i[2:2], addr_i[4:0]};
default: sparse_addr = addr_i;
endcase
6: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:1], addr_i[5:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:1], addr_i[5:0]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:2], addr_i[5:0]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:3], addr_i[5:0]};
default: sparse_addr = addr_i;
endcase
7: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:2], addr_i[6:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:2], addr_i[6:0]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:2], addr_i[6:0]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:3], addr_i[6:0]};
3'h4: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:4], addr_i[6:0]};
default: sparse_addr = addr_i;
endcase
endcase
end
f_s_rbuf_addr = {s_buf, {14-P_NUM_BUF_LOG{1'b0}}};
f_s_rbuf_addr[13-P_NUM_BUF_LOG : 5-P_RATIO_LOG] = sparse_addr[P_SI_SIZE +: 9+P_RATIO_LOG-P_NUM_BUF_LOG];
end
endfunction
// RAMB MI-side port address
function [13:0] f_m_rbuf_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [1:0] burst,
input [P_NUM_BUF_LOG-1:0] m_buf
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] sparse_addr;
begin
addr_i = addr;
if (burst == P_FIXED) begin
sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
end else begin
case (P_MI_SIZE)
3: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[0:0]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
4: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[1:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[1:1]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
5: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[2:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[2:1]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[2:2]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
6: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:1]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:1]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:2]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:3]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
7: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:2]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:2]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:2]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:3]};
3'h4: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:4]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
endcase
end
f_m_rbuf_addr = {m_buf, sparse_addr[0 +: 9-P_NUM_BUF_LOG], 5'b0};
end
endfunction
// RAMB MI-side port write-enables
function [3:0] f_m_rbuf_we
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h2: f_m_rbuf_we = addr_i[2] ? 4'b1100 : 4'b0011;
3'h3: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[2:1];
endcase
4: case (size)
3'h3: f_m_rbuf_we = addr_i[3] ? 4'b1100 : 4'b0011;
3'h4: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[3:2];
endcase
5: case (size)
3'h4: f_m_rbuf_we = addr_i[4] ? 4'b1100 : 4'b0011;
3'h5: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[4:3];
endcase
6: case (size)
3'h5: f_m_rbuf_we = addr_i[5] ? 4'b1100 : 4'b0011;
3'h6: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[5:4];
endcase
7: case (size)
3'h6: f_m_rbuf_we = addr_i[6] ? 4'b1100 : 4'b0011;
3'h7: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[6:5];
endcase
endcase
end
endfunction
// RAMB MI-side write-enable mask for last beat of long unaligned INCR burst wrapping to 1st buffer addr.
// Only applies to full-size SI bursts when RATIO = 2 or 4.
function [3:0] f_large_incr_mask
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
reg [3:0] result;
begin
addr_i = addr;
result = 4'b1111;
case (P_MI_SIZE)
3: result = 4'b0011;
4: case (P_SI_SIZE)
3'h3: result = 4'b0011;
3'h2: case (addr_i[3:2])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
5: case (P_SI_SIZE)
3'h4: result = 4'b0011;
3'h3: case (addr_i[4:3])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
6: case (P_SI_SIZE)
3'h5: result = 4'b0011;
3'h4: case (addr_i[5:4])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
7: case (P_SI_SIZE)
3'h6: result = 4'b0011;
3'h5: case (addr_i[6:5])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
endcase
f_large_incr_mask = result;
end
endfunction
// RAMB MI-side port-enables
function [P_NUM_RAMB-1:0] f_m_rbuf_en
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
6: case (size)
3'h0: f_m_rbuf_en = addr_i[0] ? 16'hFF00 : 16'h00FF;
default: f_m_rbuf_en = 16'hFFFF;
endcase
7: case (size)
3'h0: case (addr_i[1:0])
2'b00: f_m_rbuf_en = 32'h000000FF;
2'b01: f_m_rbuf_en = 32'h0000FF00;
2'b10: f_m_rbuf_en = 32'h00FF0000;
2'b11: f_m_rbuf_en = 32'hFF000000;
endcase
3'h1: f_m_rbuf_en = addr_i[1] ? 32'hFFFF0000 : 32'h0000FFFF;
default: f_m_rbuf_en = 32'hFFFFFFFF;
endcase
default: f_m_rbuf_en = {P_NUM_RAMB{1'b1}};
endcase
end
endfunction
// SI-side buffer line fault detection
function f_s_eol
(
input [P_MI_SIZE-1:0] addr,
input [2:0] s_size,
input [2:0] m_size
);
reg [7-1:0] addr_i;
begin
addr_i = addr;
if (m_size == P_MI_SIZE) begin
case (P_MI_SIZE)
3: case (s_size)
3'h0: f_s_eol = &(addr_i[2:0]);
3'h1: f_s_eol = &(addr_i[2:1]);
3'h2: f_s_eol = &(addr_i[2:2]);
endcase
4: case (s_size)
3'h0: f_s_eol = &(addr_i[3:0]);
3'h1: f_s_eol = &(addr_i[3:1]);
3'h2: f_s_eol = &(addr_i[3:2]);
3'h3: f_s_eol = &(addr_i[3:3]);
endcase
5: case (s_size)
3'h0: f_s_eol = &(addr_i[4:0]);
3'h1: f_s_eol = &(addr_i[4:1]);
3'h2: f_s_eol = &(addr_i[4:2]);
3'h3: f_s_eol = &(addr_i[4:3]);
3'h4: f_s_eol = &(addr_i[4:4]);
endcase
6: case (s_size)
3'h0: f_s_eol = &(addr_i[5:0]);
3'h1: f_s_eol = &(addr_i[5:1]);
3'h2: f_s_eol = &(addr_i[5:2]);
3'h3: f_s_eol = &(addr_i[5:3]);
3'h4: f_s_eol = &(addr_i[5:4]);
3'h5: f_s_eol = &(addr_i[5:5]);
endcase
7: case (s_size)
3'h0: f_s_eol = &(addr_i[6:0]);
3'h1: f_s_eol = &(addr_i[6:1]);
3'h2: f_s_eol = &(addr_i[6:2]);
3'h3: f_s_eol = &(addr_i[6:3]);
3'h4: f_s_eol = &(addr_i[6:4]);
3'h5: f_s_eol = &(addr_i[6:5]);
3'h6: f_s_eol = &(addr_i[6:6]);
endcase
endcase
end else begin
// Assumes that AR transform is either fully-packed (m_size == P_MI_SIZE) or unpacked (m_size == s_size), no intermediate sizes.
f_s_eol = 1'b1;
end
end
endfunction
// Number of SI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_s_wrap_cnt
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
default: start = addr_i[ 2 +: 4];
endcase
3: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
2'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
endcase
f_s_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Number of MI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_m_wrap_cnt
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
7: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
3'h6: start = addr_i[ 6 +: 4];
default: start = addr_i[ 7 +: 4];
endcase
endcase
f_m_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Mask of address bits used to point to first SI wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_s_wrap_mask = {len[3:3], 3'b111 };
3'h1: f_s_wrap_mask = {len[3:2], 3'b110 };
3'h2: f_s_wrap_mask = {len[3:1], 3'b100 };
endcase
4: case (size)
3'h0: f_s_wrap_mask = 4'b1111 ;
3'h1: f_s_wrap_mask = {len[3:3], 4'b1110 };
3'h2: f_s_wrap_mask = {len[3:2], 4'b1100 };
3'h3: f_s_wrap_mask = {len[3:1], 4'b1000 };
endcase
5: case (size)
3'h0: f_s_wrap_mask = 5'b11111 ;
3'h1: f_s_wrap_mask = 5'b11110 ;
3'h2: f_s_wrap_mask = {len[3:3], 5'b11100 };
3'h3: f_s_wrap_mask = {len[3:2], 5'b11000 };
3'h4: f_s_wrap_mask = {len[3:1], 5'b10000 };
endcase
6: case (size)
3'h0: f_s_wrap_mask = 6'b111111 ;
3'h1: f_s_wrap_mask = 6'b111110 ;
3'h2: f_s_wrap_mask = 6'b111100 ;
3'h3: f_s_wrap_mask = {len[3:3], 6'b111000 };
3'h4: f_s_wrap_mask = {len[3:2], 6'b110000 };
3'h5: f_s_wrap_mask = {len[3:1], 6'b100000 };
endcase
7: case (size)
3'h0: f_s_wrap_mask = 7'b1111111 ;
3'h1: f_s_wrap_mask = 7'b1111110 ;
3'h2: f_s_wrap_mask = 7'b1111100 ;
3'h3: f_s_wrap_mask = 7'b1111000 ;
3'h4: f_s_wrap_mask = {len[3:3], 7'b1110000};
3'h5: f_s_wrap_mask = {len[3:2], 7'b1100000};
3'h6: f_s_wrap_mask = {len[3:1], 7'b1000000};
endcase
endcase
end
endfunction
// Mask of address bits used to point to first MI wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_m_wrap_mask = {len[3:3], 3'b111 };
3'h1: f_m_wrap_mask = {len[3:2], 3'b110 };
3'h2: f_m_wrap_mask = {len[3:1], 3'b100 };
3'h3: f_m_wrap_mask = {len[3:1], 4'b1000 };
endcase
4: case (size)
3'h0: f_m_wrap_mask = 4'b1111 ;
3'h1: f_m_wrap_mask = {len[3:3], 4'b1110 };
3'h2: f_m_wrap_mask = {len[3:2], 4'b1100 };
3'h3: f_m_wrap_mask = {len[3:1], 4'b1000 };
3'h4: f_m_wrap_mask = {len[3:1], 5'b10000 };
endcase
5: case (size)
3'h0: f_m_wrap_mask = 5'b11111 ;
3'h1: f_m_wrap_mask = 5'b11110 ;
3'h2: f_m_wrap_mask = {len[3:3], 5'b11100 };
3'h3: f_m_wrap_mask = {len[3:2], 5'b11000 };
3'h4: f_m_wrap_mask = {len[3:1], 5'b10000 };
3'h5: f_m_wrap_mask = {len[3:1], 6'b100000 };
endcase
6: case (size)
3'h0: f_m_wrap_mask = 6'b111111 ;
3'h1: f_m_wrap_mask = 6'b111110 ;
3'h2: f_m_wrap_mask = 6'b111100 ;
3'h3: f_m_wrap_mask = {len[3:3], 6'b111000 };
3'h4: f_m_wrap_mask = {len[3:2], 6'b110000 };
3'h5: f_m_wrap_mask = {len[3:1], 6'b100000 };
3'h6: f_m_wrap_mask = {len[3:1], 7'b1000000 };
endcase
7: case (size)
3'h0: f_m_wrap_mask = 7'b1111111 ;
3'h1: f_m_wrap_mask = 7'b1111110 ;
3'h2: f_m_wrap_mask = 7'b1111100 ;
3'h3: f_m_wrap_mask = 7'b1111000 ;
3'h4: f_m_wrap_mask = {len[3:3], 7'b1110000 };
3'h5: f_m_wrap_mask = {len[3:2], 7'b1100000 };
3'h6: f_m_wrap_mask = {len[3:1], 7'b1000000 };
3'h7: f_m_wrap_mask = {len[3:1], 8'b10000000};
endcase
endcase
end
endfunction
// Address of SI transfer following wrap
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_wrap_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [P_M_RBUFFER_BYTES_LOG-1:0] mask;
begin
case (P_MI_SIZE)
3: case (size)
3'h0: mask = { ~len[2:1], 1'b0};
3'h1: mask = { ~len[1:1], 2'b0};
default: mask = 3'b0 ;
endcase
4: case (size)
3'h0: mask = { ~len[3:1], 1'b0};
3'h1: mask = { ~len[2:1], 2'b0};
3'h2: mask = { ~len[1:1], 3'b0};
default: mask = 4'b0 ;
endcase
5: case (size)
3'h0: mask = {1'b1 , ~len[3:1], 1'b0};
3'h1: mask = { ~len[3:1], 2'b0};
3'h2: mask = { ~len[2:1], 3'b0};
3'h3: mask = { ~len[1:1], 4'b0};
default: mask = 5'b0 ;
endcase
6: case (size)
3'h0: mask = {2'b11 , ~len[3:1], 1'b0};
3'h1: mask = {1'b1 , ~len[3:1], 2'b0};
3'h2: mask = { ~len[3:1], 3'b0};
3'h3: mask = { ~len[2:1], 4'b0};
3'h4: mask = { ~len[1:1], 5'b0};
default: mask = 6'b0 ;
endcase
7: case (size)
3'h0: mask = {3'b111, ~len[3:1], 1'b0};
3'h1: mask = {2'b11 , ~len[3:1], 2'b0};
3'h2: mask = {1'b1 , ~len[3:1], 3'b0};
3'h3: mask = { ~len[3:1], 4'b0};
3'h4: mask = { ~len[2:1], 5'b0};
3'h5: mask = { ~len[1:1], 6'b0};
default: mask = 7'b0 ;
endcase
endcase
f_s_wrap_addr = addr & mask;
end
endfunction
// Address of MI transfer following wrap
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_wrap_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [P_M_RBUFFER_BYTES_LOG-1:0] mask;
begin
case (P_MI_SIZE)
3: case (size)
3'h0: mask = { ~len[2:1], 1'b0};
3'h1: mask = { ~len[1:1], 2'b0};
default: mask = 3'b0 ;
endcase
4: case (size)
3'h0: mask = { ~len[3:1], 1'b0};
3'h1: mask = { ~len[2:1], 2'b0};
3'h2: mask = { ~len[1:1], 3'b0};
default: mask = 4'b0 ;
endcase
5: case (size)
3'h0: mask = {1'b1 , ~len[3:1], 1'b0};
3'h1: mask = { ~len[3:1], 2'b0};
3'h2: mask = { ~len[2:1], 3'b0};
3'h3: mask = { ~len[1:1], 4'b0};
default: mask = 5'b0 ;
endcase
6: case (size)
3'h0: mask = {2'b11 , ~len[3:1], 1'b0};
3'h1: mask = {1'b1 , ~len[3:1], 2'b0};
3'h2: mask = { ~len[3:1], 3'b0};
3'h3: mask = { ~len[2:1], 4'b0};
3'h4: mask = { ~len[1:1], 5'b0};
default: mask = 6'b0 ;
endcase
7: case (size)
3'h0: mask = {3'b111, ~len[3:1], 1'b0};
3'h1: mask = {2'b11 , ~len[3:1], 2'b0};
3'h2: mask = {1'b1 , ~len[3:1], 3'b0};
3'h3: mask = { ~len[3:1], 4'b0};
3'h4: mask = { ~len[2:1], 5'b0};
3'h5: mask = { ~len[1:1], 6'b0};
default: mask = 7'b0 ;
endcase
endcase
f_m_wrap_addr = addr & mask;
end
endfunction
// Mask of address bits used to point to first SI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_size_mask
(
input [2:0] size
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_s_size_mask = 3'b111;
3'h1: f_s_size_mask = 3'b110;
3'h2: f_s_size_mask = 3'b100;
endcase
4: case (size)
3'h0: f_s_size_mask = 4'b1111;
3'h1: f_s_size_mask = 4'b1110;
3'h2: f_s_size_mask = 4'b1100;
3'h3: f_s_size_mask = 4'b1000;
endcase
5: case (size)
3'h0: f_s_size_mask = 5'b11111;
3'h1: f_s_size_mask = 5'b11110;
3'h2: f_s_size_mask = 5'b11100;
3'h3: f_s_size_mask = 5'b11000;
3'h4: f_s_size_mask = 5'b10000;
endcase
6: case (size)
3'h0: f_s_size_mask = 6'b111111;
3'h1: f_s_size_mask = 6'b111110;
3'h2: f_s_size_mask = 6'b111100;
3'h3: f_s_size_mask = 6'b111000;
3'h4: f_s_size_mask = 6'b110000;
3'h5: f_s_size_mask = 6'b100000;
endcase
7: case (size)
3'h0: f_s_size_mask = 7'b1111111;
3'h1: f_s_size_mask = 7'b1111110;
3'h2: f_s_size_mask = 7'b1111100;
3'h3: f_s_size_mask = 7'b1111000;
3'h4: f_s_size_mask = 7'b1110000;
3'h5: f_s_size_mask = 7'b1100000;
3'h6: f_s_size_mask = 7'b1000000;
endcase
endcase
end
endfunction
// Mask of address bits used to point to first MI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_size_mask
(
input [2:0] size
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_m_size_mask = 3'b111;
3'h1: f_m_size_mask = 3'b110;
3'h2: f_m_size_mask = 3'b100;
3'h3: f_m_size_mask = 3'b000;
endcase
4: case (size)
3'h0: f_m_size_mask = 4'b1111;
3'h1: f_m_size_mask = 4'b1110;
3'h2: f_m_size_mask = 4'b1100;
3'h3: f_m_size_mask = 4'b1000;
3'h4: f_m_size_mask = 4'b0000;
endcase
5: case (size)
3'h0: f_m_size_mask = 5'b11111;
3'h1: f_m_size_mask = 5'b11110;
3'h2: f_m_size_mask = 5'b11100;
3'h3: f_m_size_mask = 5'b11000;
3'h4: f_m_size_mask = 5'b10000;
3'h5: f_m_size_mask = 5'b00000;
endcase
6: case (size)
3'h0: f_m_size_mask = 6'b111111;
3'h1: f_m_size_mask = 6'b111110;
3'h2: f_m_size_mask = 6'b111100;
3'h3: f_m_size_mask = 6'b111000;
3'h4: f_m_size_mask = 6'b110000;
3'h5: f_m_size_mask = 6'b100000;
3'h6: f_m_size_mask = 6'b000000;
endcase
7: case (size)
3'h0: f_m_size_mask = 7'b1111111;
3'h1: f_m_size_mask = 7'b1111110;
3'h2: f_m_size_mask = 7'b1111100;
3'h3: f_m_size_mask = 7'b1111000;
3'h4: f_m_size_mask = 7'b1110000;
3'h5: f_m_size_mask = 7'b1100000;
3'h6: f_m_size_mask = 7'b1000000;
3'h7: f_m_size_mask = 7'b0000000;
endcase
endcase
end
endfunction
// Address increment for SI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_size_incr
(
input [2:0] size
);
begin
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_s_size_incr = 4'b001;
2'h1: f_s_size_incr = 4'b010;
2'h2: f_s_size_incr = 4'b100;
endcase
3: case (size[1:0])
2'h0: f_s_size_incr = 4'b0001;
2'h1: f_s_size_incr = 4'b0010;
2'h2: f_s_size_incr = 4'b0100;
2'h3: f_s_size_incr = 4'b1000;
endcase
4: case (size)
3'h0: f_s_size_incr = 5'b00001;
3'h1: f_s_size_incr = 5'b00010;
3'h2: f_s_size_incr = 5'b00100;
3'h3: f_s_size_incr = 5'b01000;
3'h4: f_s_size_incr = 5'b10000;
endcase
5: case (size)
3'h0: f_s_size_incr = 6'b000001;
3'h1: f_s_size_incr = 6'b000010;
3'h2: f_s_size_incr = 6'b000100;
3'h3: f_s_size_incr = 6'b001000;
3'h4: f_s_size_incr = 6'b010000;
3'h5: f_s_size_incr = 6'b100000;
endcase
6: case (size)
3'h0: f_s_size_incr = 7'b0000001;
3'h1: f_s_size_incr = 7'b0000010;
3'h2: f_s_size_incr = 7'b0000100;
3'h3: f_s_size_incr = 7'b0001000;
3'h4: f_s_size_incr = 7'b0010000;
3'h5: f_s_size_incr = 7'b0100000;
3'h6: f_s_size_incr = 7'b1000000;
endcase
endcase
end
endfunction
// Address increment for MI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_size_incr
(
input [2:0] size
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_m_size_incr = 4'b0001;
3'h1: f_m_size_incr = 4'b0010;
3'h2: f_m_size_incr = 4'b0100;
3'h3: f_m_size_incr = 4'b1000;
endcase
4: case (size)
3'h0: f_m_size_incr = 5'b00001;
3'h1: f_m_size_incr = 5'b00010;
3'h2: f_m_size_incr = 5'b00100;
3'h3: f_m_size_incr = 5'b01000;
3'h4: f_m_size_incr = 5'b10000;
endcase
5: case (size)
3'h0: f_m_size_incr = 6'b000001;
3'h1: f_m_size_incr = 6'b000010;
3'h2: f_m_size_incr = 6'b000100;
3'h3: f_m_size_incr = 6'b001000;
3'h4: f_m_size_incr = 6'b010000;
3'h5: f_m_size_incr = 6'b100000;
endcase
6: case (size)
3'h0: f_m_size_incr = 7'b0000001;
3'h1: f_m_size_incr = 7'b0000010;
3'h2: f_m_size_incr = 7'b0000100;
3'h3: f_m_size_incr = 7'b0001000;
3'h4: f_m_size_incr = 7'b0010000;
3'h5: f_m_size_incr = 7'b0100000;
3'h6: f_m_size_incr = 7'b1000000;
endcase
7: case (size)
3'h0: f_m_size_incr = 8'b00000001;
3'h1: f_m_size_incr = 8'b00000010;
3'h2: f_m_size_incr = 8'b00000100;
3'h3: f_m_size_incr = 8'b00001000;
3'h4: f_m_size_incr = 8'b00010000;
3'h5: f_m_size_incr = 8'b00100000;
3'h6: f_m_size_incr = 8'b01000000;
3'h7: f_m_size_incr = 8'b10000000;
endcase
endcase
end
endfunction
generate
if (C_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = M_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign ar_fifo_s_aclk = S_AXI_ACLK;
assign ar_fifo_m_aclk = M_AXI_ACLK;
assign ar_fifo_aresetn = S_AXI_ARESETN & M_AXI_ARESETN;
assign s_fifo_rst = ~S_AXI_ARESETN;
assign m_fifo_rst = ~M_AXI_ARESETN;
assign rresp_fifo_clk = 1'b0;
assign rresp_fifo_wrclk = M_AXI_ACLK;
assign rresp_fifo_rdclk = S_AXI_ACLK;
assign rresp_fifo_rst = ~S_AXI_ARESETN | ~M_AXI_ARESETN;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
end else begin : gen_sync_conv
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = M_AXI_ACLK;
end else begin : gen_fastclk_si
assign fast_aclk = S_AXI_ACLK;
end
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = fast_aresetn_r;
assign s_aresetn = fast_aresetn_r;
assign ar_fifo_s_aclk = fast_aclk;
assign ar_fifo_m_aclk = 1'b0;
assign ar_fifo_aresetn = fast_aresetn_r;
assign s_fifo_rst = fast_reset_r;
assign m_fifo_rst = fast_reset_r;
assign rresp_fifo_clk = fast_aclk;
assign rresp_fifo_wrclk = 1'b0;
assign rresp_fifo_rdclk = 1'b0;
assign rresp_fifo_rst = fast_reset_r;
assign s_sample_cycle_early = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign s_sample_cycle = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE;
assign m_sample_cycle_early = P_SI_LT_MI ? SAMPLE_CYCLE_EARLY : 1'b1;
assign m_sample_cycle = P_SI_LT_MI ? SAMPLE_CYCLE : 1'b1;
always @(posedge fast_aclk) begin
if (~S_AXI_ARESETN | ~M_AXI_ARESETN) begin
fast_aresetn_r <= 1'b0;
fast_reset_r <= 1'b1;
end else if (S_AXI_ARESETN & M_AXI_ARESETN & SAMPLE_CYCLE_EARLY) begin
fast_aresetn_r <= 1'b1;
fast_reset_r <= 1'b0;
end
end
end
end else begin : gen_no_clk_conv
assign m_aclk = S_AXI_ACLK;
assign m_aresetn = S_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign ar_fifo_s_aclk = S_AXI_ACLK;
assign ar_fifo_m_aclk = 1'b0;
assign ar_fifo_aresetn = S_AXI_ARESETN;
assign s_fifo_rst = reset_r;
assign m_fifo_rst = reset_r;
assign rresp_fifo_clk = S_AXI_ACLK;
assign rresp_fifo_wrclk = 1'b0;
assign rresp_fifo_rdclk = 1'b0;
assign rresp_fifo_rst = reset_r;
assign fast_aclk = S_AXI_ACLK;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
always @(posedge S_AXI_ACLK) begin
reset_r <= ~S_AXI_ARESETN;
end
end
for (i=0; i<P_NUM_RAMB; i=i+1) begin : gen_rdata
for (j=0; j<32; j=j+1) begin : gen_m_rdata
assign m_rdata[i*32+j] = M_AXI_RDATA[j*P_NUM_RAMB+i];
end
for (j=0; j<P_S_RAMB_WIDTH; j=j+1) begin : gen_s_rdata
assign S_AXI_RDATA[j*P_NUM_RAMB+i] = s_rdata[i*16+j];
end
end // gen_rdata
assign S_AXI_ARREADY = S_AXI_ARREADY_i;
assign S_AXI_RVALID = s_rvalid_d2;
assign S_AXI_RRESP = s_rresp_d2;
assign S_AXI_RLAST = s_rlast_d2;
assign S_AXI_RID = s_id_d2;
assign s_rbuf_en = ~s_rvalid_d2 | S_AXI_RREADY;
assign buf_limit = buf_cnt == P_BUF_LIMIT;
assign s_cmd_pop = (s_rbuf_en | ~s_rvalid) & (s_rcnt == 0) & ~s_cmd_empty & ~rresp_fifo_empty & ~s_rresp_fifo_stall;
assign s_eol = f_s_eol(s_raddr, s_rsize, s_conv_size) | (s_rburst == P_FIXED);
assign rresp_fifo_pop = (s_rbuf_en | ~s_rvalid) & (((s_rcnt == 0) ? ~s_cmd_empty : (s_eol & ~rresp_wrap)) | s_rresp_fifo_stall) &
~rresp_fifo_empty & m_sample_cycle; // Sample strobe when RRESP FIFO is on faster M_AXI_ACLK.
assign rresp_reuse = (s_rbuf_en | ~s_rvalid) & s_eol & rresp_wrap;
assign ar_push = S_AXI_ARVALID & S_AXI_ARREADY_i & m_sample_cycle; // Sample strobe when AR FIFO is on faster M_AXI_ACLK.
assign s_cmd_push = S_AXI_ARVALID & S_AXI_ARREADY_i;
assign s_ar_cmd = {cmd_si_addr[0 +: P_MI_SIZE+4], cmd_si_id, S_AXI_ARLEN[3:0], S_AXI_ARSIZE, cmd_si_len, cmd_si_size, cmd_si_burst};
assign s_cmd_addr = s_r_cmd[(20+C_AXI_ID_WIDTH) +: P_MI_SIZE+4];
assign s_cmd_id = s_r_cmd[20 +: C_AXI_ID_WIDTH];
assign s_cmd_conv_len = s_r_cmd[16 +: 4];
assign s_cmd_conv_size = s_r_cmd[13 +: 3];
assign s_cmd_len = s_r_cmd[5 +: 8];
assign s_cmd_size = s_r_cmd[2 +: 3];
assign s_cmd_burst = s_r_cmd[0 +: 2];
assign s_rbuf_addr = f_s_rbuf_addr(s_raddr, s_conv_size, s_rburst, s_buf);
assign s_rresp = s_rresp_i[1:0];
always @(posedge S_AXI_ACLK) begin
if (~s_aresetn) begin
S_AXI_ARREADY_i <= 1'b0;
buf_cnt <= 0;
end else begin
if (ar_push) begin
S_AXI_ARREADY_i <= 1'b0;
end else if (ar_fifo_ready & ~s_cmd_full & ~buf_limit) begin
S_AXI_ARREADY_i <= 1'b1; // pre-assert READY
end
if (s_cmd_push & ~s_cmd_pop) begin
buf_cnt <= buf_cnt + 1;
end else if (~s_cmd_push & s_cmd_pop & (buf_cnt != 0)) begin
buf_cnt <= buf_cnt - 1;
end
end
end
always @(posedge S_AXI_ACLK) begin
if (~s_aresetn) begin
s_rvalid <= 1'b0;
s_rvalid_d1 <= 1'b0;
s_rvalid_d2 <= 1'b0;
first_rvalid_d1 <= 1'b0;
s_rlast <= 1'b0;
s_rlast_d1 <= 1'b0;
s_rlast_d2 <= 1'b0;
s_rcnt <= 0;
s_buf <= 0;
rresp_wrap <= 1'b0;
s_rresp_fifo_stall <= 1'b0;
s_rresp_d2 <= 2'b00;
s_id_d2 <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if (s_rbuf_en) begin
s_rvalid_d2 <= s_rvalid_d1;
s_rvalid_d1 <= s_rvalid;
s_rlast_d2 <= s_rlast_d1;
s_rlast_d1 <= s_rlast;
if (first_rvalid_d1) begin
s_rresp_d2 <= s_rresp_d1;
s_id_d2 <= s_id_d1;
end
if (s_rvalid) begin
first_rvalid_d1 <= 1'b1; // forever
end
end
if (s_cmd_pop) begin
s_rlast <= (s_cmd_len == 0);
end else if (s_rvalid & s_rbuf_en & (s_rcnt != 0)) begin
s_rlast <= (s_rcnt == 1);
end
if ((s_rcnt == 0) & ~s_rresp_fifo_stall) begin
if (s_cmd_pop) begin
s_rvalid <= 1'b1;
s_rcnt <= s_cmd_len;
rresp_wrap <= (s_cmd_burst == P_WRAP) & (s_cmd_conv_len == 0);
s_buf <= s_buf + 1;
end else if (s_rbuf_en) begin
s_rvalid <= 1'b0;
end
end else begin
if (s_rvalid & s_rbuf_en) begin
s_rcnt <= s_rcnt - 1;
end
if ((s_eol & ~rresp_wrap) | s_rresp_fifo_stall) begin
if (rresp_fifo_pop) begin
rresp_wrap <= (s_rburst == P_WRAP) && (s_conv_len == 1); // Last rresp pop of wrap burst
s_rvalid <= 1'b1;
s_rresp_fifo_stall <= 1'b0;
end else if (s_rbuf_en) begin
s_rvalid <= 1'b0;
s_rresp_fifo_stall <= 1'b1;
end
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (s_rbuf_en) begin
s_rresp_d1 <= s_rresp_reg;
s_id_d1 <= s_id_reg;
end
if (s_cmd_pop) begin
if (s_cmd_burst == P_WRAP) begin
s_raddr <= s_cmd_addr & f_s_wrap_mask(s_cmd_size, s_cmd_len);
end else begin
s_raddr <= s_cmd_addr & f_s_size_mask(s_cmd_size);
end
s_rsize <= s_cmd_size;
s_rburst <= s_cmd_burst;
s_id_reg <= s_cmd_id;
s_wrap_cnt <= f_s_wrap_cnt(s_cmd_addr, s_cmd_size, s_cmd_len);
s_wrap_addr <= f_s_wrap_addr(s_cmd_addr, s_cmd_size, s_cmd_len);
s_conv_size <= s_cmd_conv_size;
s_conv_len <= s_cmd_conv_len; // MI len to count wrap beats for rresp reuse.
s_rresp_first <= s_rresp; // Save first beat of wrap burst.
end else if (s_rvalid & s_rbuf_en & (s_rcnt != 0)) begin
if ((s_rburst == P_WRAP) && (s_wrap_cnt == 0)) begin
s_raddr <= s_wrap_addr;
end else if (s_rburst == P_FIXED) begin
s_raddr <= s_raddr + P_MI_BYTES;
end else begin
s_raddr <= s_raddr + f_s_size_incr(s_rsize);
end
s_wrap_cnt <= s_wrap_cnt - 1;
end
if (rresp_fifo_pop) begin
s_rresp_reg <= s_rresp;
if (~s_cmd_pop) begin
s_conv_len <= s_conv_len - 1; // Count rresp pops during wrap burst
end
end else if (rresp_reuse) begin // SI wrap revisits first buffer line; reuse firt rresp.
s_rresp_reg <= s_rresp_first;
end
end
assign M_AXI_ARADDR = M_AXI_ARADDR_i;
assign M_AXI_ARLEN = M_AXI_ARLEN_i;
assign M_AXI_ARSIZE = M_AXI_ARSIZE_i;
assign M_AXI_ARBURST = M_AXI_ARBURST_i;
assign M_AXI_ARLOCK = {1'b0,M_AXI_ARLOCK_i};
assign M_AXI_ARVALID = M_AXI_ARVALID_i;
assign M_AXI_RREADY = M_AXI_RREADY_i;
assign ar_pop = M_AXI_ARVALID_i & M_AXI_ARREADY & s_sample_cycle; // Sample strobe when AR FIFO is on faster S_AXI_ACLK.
assign m_cmd_push = M_AXI_ARVALID_i & M_AXI_ARREADY;
assign m_transfer = M_AXI_RREADY_i & M_AXI_RVALID;
assign rresp_fifo_push = (m_transfer | m_rresp_fifo_stall) & ~rresp_fifo_full & s_sample_cycle; // Sample strobe when RRESP FIFO is on faster S_AXI_ACLK.
assign m_cmd_pop = ((m_transfer & M_AXI_RLAST) | (~m_cmd_valid & ~rresp_fifo_full)) & ~m_cmd_empty;
assign m_rresp = m_rresp_fifo_stall ? m_rresp_reg : M_AXI_RRESP;
assign m_rresp_i = {2'b0, m_rresp};
assign m_ar_cmd = {M_AXI_ARADDR_i[0 +: P_MI_SIZE+4], M_AXI_ARLEN_i, M_AXI_ARSIZE_i, M_AXI_ARBURST_i};
assign m_cmd_addr = m_r_cmd[13 +: P_MI_SIZE+4];
assign m_cmd_len = m_r_cmd[5 +: 8];
assign m_cmd_size = m_r_cmd[2 +: 3];
assign m_cmd_burst = m_r_cmd[0 +: 2];
assign m_rbuf_addr = f_m_rbuf_addr(m_raddr, m_rsize, m_rburst, m_buf);
assign m_rbuf_we = (large_incr_last ? large_incr_mask : 4'b1111) & f_m_rbuf_we(m_raddr, m_rsize);
assign m_rbuf_en = f_m_rbuf_en(m_raddr, m_rsize) & {P_NUM_RAMB{m_transfer}};
assign m_raddr_incr = m_raddr + f_m_size_incr(m_rsize);
always @(posedge m_aclk) begin
if (~m_aresetn) begin
M_AXI_ARVALID_i <= 1'b0;
end else begin
if (ar_pop) begin
M_AXI_ARVALID_i <= 1'b0;
end else if (ar_fifo_valid & ~m_cmd_full) begin
M_AXI_ARVALID_i <= 1'b1;
end
end
end
always @(posedge m_aclk) begin
if (~m_aresetn) begin
m_buf <= 0;
M_AXI_RREADY_i <= 1'b0;
m_cmd_valid <= 1'b0;
m_rresp_fifo_stall <= 1'b0;
end else begin
if (M_AXI_RREADY_i) begin
if (M_AXI_RVALID) begin
m_rresp_reg <= M_AXI_RRESP;
if (rresp_fifo_full) begin
M_AXI_RREADY_i <= 1'b0;
m_rresp_fifo_stall <= 1'b1;
end
if (M_AXI_RLAST & m_cmd_empty) begin
M_AXI_RREADY_i <= 1'b0;
m_cmd_valid <= 1'b0;
end
end
end else if (~rresp_fifo_full) begin
m_rresp_fifo_stall <= 1'b0;
if (m_cmd_valid) begin
M_AXI_RREADY_i <= 1'b1;
end else if (~m_cmd_empty) begin
m_cmd_valid <= 1'b1;
M_AXI_RREADY_i <= 1'b1;
end
end
if (m_cmd_pop) begin
m_buf <= m_buf + 1;
end
end
end
always @(posedge m_aclk) begin
if (m_cmd_pop) begin
if (m_cmd_burst == P_WRAP) begin
m_raddr <= m_cmd_addr & f_m_wrap_mask(m_cmd_size, m_cmd_len);
end else begin
m_raddr <= m_cmd_addr & f_m_size_mask(m_cmd_size);
end
m_rsize <= m_cmd_size;
m_rburst <= m_cmd_burst;
m_wrap_cnt <= f_m_wrap_cnt(m_cmd_addr, m_cmd_size, m_cmd_len);
m_wrap_addr <= f_m_wrap_addr(m_cmd_addr, m_cmd_size, m_cmd_len);
large_incr_last <= 1'b0;
large_incr_mask <= f_large_incr_mask(m_cmd_addr);
end else if (m_transfer) begin
if ((m_rburst == P_WRAP) && (m_wrap_cnt == 0)) begin
m_raddr <= m_wrap_addr;
end else if (m_rburst == P_FIXED) begin
m_raddr <= m_raddr + P_MI_BYTES;
end else begin
if (~|m_raddr_incr) begin // Addr pointer is about to wrap to zero?
large_incr_last <= 1'b1;
end
m_raddr <= m_raddr_incr;
end
m_wrap_cnt <= m_wrap_cnt - 1;
end
end
for (i=0; i<P_NUM_RAMB; i=i+1) begin : gen_ramb
RAMB18E1 #(
.READ_WIDTH_A(P_S_RAMB_PWIDTH),
.WRITE_WIDTH_B(36),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.SIM_COLLISION_CHECK("NONE"),
.DOA_REG(1),
.DOB_REG(1),
.RAM_MODE("SDP"),
.READ_WIDTH_B(0),
.WRITE_WIDTH_A(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.SIM_DEVICE("7SERIES"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
) ramb_inst (
.DOADO(s_rdata[(i*16) +: 16]),
.DIADI(m_rdata[(i*32) +: 16]),
.DIBDI(m_rdata[(i*32+16) +: 16]),
.WEBWE(m_rbuf_we),
.ADDRARDADDR(s_rbuf_addr),
.ADDRBWRADDR(m_rbuf_addr),
.ENARDEN(s_rbuf_en),
.REGCEAREGCE(s_rbuf_en),
.ENBWREN(m_rbuf_en[i]),
.CLKARDCLK(S_AXI_ACLK),
.CLKBWRCLK(m_aclk),
.RSTRAMARSTRAM(1'b0),
.RSTREGARSTREG(1'b0),
.WEA(2'b0),
.DIPADIP(2'b0),
.DIPBDIP(2'b0),
.REGCEB(1'b1),
.RSTRAMB(1'b0),
.RSTREGB(1'b0),
.DOBDO(),
.DOPADOP(),
.DOPBDOP()
);
end
fifo_generator_v12_0 #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(P_COMMON_CLOCK),
.C_MEMORY_TYPE(1),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_DIN_WIDTH_WACH(P_ARFIFO_WIDTH),
.C_DIN_WIDTH_WDCH(37),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(P_ARFIFO_WIDTH),
.C_DIN_WIDTH_RDCH(35),
.C_AXIS_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(2),
.C_IMPLEMENTATION_TYPE_WACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_WDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_WRCH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(P_COMMON_CLOCK ? 2 : 0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0)
) dw_fifogen_ar (
.s_aclk(ar_fifo_s_aclk),
.m_aclk(ar_fifo_m_aclk),
.s_aresetn(ar_fifo_aresetn),
.s_axi_arid (1'b0),
.s_axi_araddr (S_AXI_ARADDR),
.s_axi_arlen (S_AXI_ARLEN),
.s_axi_arsize (S_AXI_ARSIZE),
.s_axi_arburst (S_AXI_ARBURST),
.s_axi_arlock (S_AXI_ARLOCK[0]),
.s_axi_arcache (S_AXI_ARCACHE),
.s_axi_arprot (S_AXI_ARPROT),
.s_axi_arqos (S_AXI_ARQOS),
.s_axi_arregion (S_AXI_ARREGION),
.s_axi_aruser (1'b0),
.s_axi_arvalid (ar_push),
.s_axi_arready (ar_fifo_ready),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid (),
.m_axi_araddr (M_AXI_ARADDR_i),
.m_axi_arlen (M_AXI_ARLEN_i),
.m_axi_arsize (M_AXI_ARSIZE_i),
.m_axi_arburst (M_AXI_ARBURST_i),
.m_axi_arlock (M_AXI_ARLOCK_i),
.m_axi_arcache (M_AXI_ARCACHE),
.m_axi_arprot (M_AXI_ARPROT),
.m_axi_arqos (M_AXI_ARQOS),
.m_axi_arregion (M_AXI_ARREGION),
.m_axi_aruser (),
.m_axi_arvalid (ar_fifo_valid),
.m_axi_arready (ar_pop),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axi_awid(1'b0),
.s_axi_awaddr({C_AXI_ADDR_WIDTH{1'b0}}),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(1'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
fifo_generator_v12_0 #(
.C_DIN_WIDTH(P_S_CMD_WIDTH),
.C_DOUT_WIDTH(P_S_CMD_WIDTH),
.C_RD_DEPTH(32),
.C_RD_PNTR_WIDTH(5),
.C_RD_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_PNTR_WIDTH(5),
.C_WR_DATA_COUNT_WIDTH(5),
.C_DATA_COUNT_WIDTH(5),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) s_cmd_fifo (
.clk(S_AXI_ACLK),
.srst(s_fifo_rst),
.din(s_ar_cmd),
.dout(s_r_cmd),
.full(s_cmd_full),
.empty(s_cmd_empty),
.wr_en(s_cmd_push),
.rd_en(s_cmd_pop),
.backup(1'b0),
.backup_marker(1'b0),
.rst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
fifo_generator_v12_0 #(
.C_DIN_WIDTH(P_M_CMD_WIDTH),
.C_DOUT_WIDTH(P_M_CMD_WIDTH),
.C_RD_DEPTH(32),
.C_RD_PNTR_WIDTH(5),
.C_RD_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_PNTR_WIDTH(5),
.C_WR_DATA_COUNT_WIDTH(5),
.C_DATA_COUNT_WIDTH(5),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) m_cmd_fifo (
.clk(m_aclk),
.srst(m_fifo_rst),
.din(m_ar_cmd),
.dout(m_r_cmd),
.full(m_cmd_full),
.empty(m_cmd_empty),
.wr_en(m_cmd_push),
.rd_en(m_cmd_pop),
.backup(1'b0),
.backup_marker(1'b0),
.rst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
fifo_generator_v12_0 #(
.C_DIN_WIDTH(4),
.C_DOUT_WIDTH(4),
.C_RD_DEPTH(512),
.C_RD_PNTR_WIDTH(9),
.C_RD_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_PNTR_WIDTH(9),
.C_WR_DATA_COUNT_WIDTH(9),
.C_DATA_COUNT_WIDTH(9),
.C_COMMON_CLOCK(P_COMMON_CLOCK),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(P_COMMON_CLOCK ? 0 : 1),
.C_HAS_SRST(P_COMMON_CLOCK ? 1 : 0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(P_COMMON_CLOCK ? 0 : 2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) dw_fifogen_rresp (
.clk(rresp_fifo_clk),
.wr_clk(rresp_fifo_wrclk),
.rd_clk(rresp_fifo_rdclk),
.srst(P_COMMON_CLOCK ? rresp_fifo_rst : 1'b0),
.rst(P_COMMON_CLOCK ? 1'b0 : rresp_fifo_rst),
.wr_rst(1'b0),
.rd_rst(1'b0),
.din(m_rresp_i),
.dout(s_rresp_i),
.full(rresp_fifo_full),
.empty(rresp_fifo_empty),
.wr_en(rresp_fifo_push),
.rd_en(rresp_fifo_pop),
.backup(1'b0),
.backup_marker(1'b0),
.prog_empty_thresh(9'b0),
.prog_empty_thresh_assert(9'b0),
.prog_empty_thresh_negate(9'b0),
.prog_full_thresh(9'b0),
.prog_full_thresh_assert(9'b0),
.prog_full_thresh_negate(9'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endgenerate
endmodule
|
(** * StlcProp: Properties of STLC *)
Require Export Stlc.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * Canonical Forms *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
(* ###################################################################### *)
(** * Progress *)
(** As before, the _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take an evaluation step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
(** _Proof_: by induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we know immediately that [t] is a value.
- If the last rule of the derivation was [T_App], then [t = t1
t2], and we know that [t1] and [t2] are also well typed in the
empty context; in particular, there exists a type [T2] such that
[|- t1 \in T2 -> T] and [|- t2 \in T2]. By the induction
hypothesis, either [t1] is a value or it can take an evaluation
step.
- If [t1] is a value, we now consider [t2], which by the other
induction hypothesis must also either be a value or take an
evaluation step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation was [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]).
*)
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst Gamma...
Case "T_Var".
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
Case "T_App".
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is also a value".
assert (exists x0 t0, t1 = tabs x0 T11 t0).
eapply canonical_forms_fun; eauto.
destruct H1 as [x0 [t0 Heq]]. subst.
exists ([x0:=t2]t0)...
SSCase "t2 steps".
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
SCase "t1 is a value".
destruct (canonical_forms_bool t1); subst; eauto.
SCase "t1 also steps".
inversion H as [t1' Hstp]. exists (tif t1' t2 t3)...
Qed.
(** **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof.
intros t.
t_cases (induction t) Case; intros T Ht; auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Preservation *)
(** The other half of the type soundness property is the preservation
of types during reduction. For this, we need to develop some
technical machinery for reasoning about variables and
substitution. Working from top to bottom (the high-level property
we are actually interested in to the lowest-level technical lemmas
that are needed by various cases of the more interesting proofs),
the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter. The
one case that is significantly different is the one for the
[ST_AppAbs] rule, which is defined using the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both cases, we
discover that we need to take a term [s] that has been shown
to be well-typed in some context [Gamma] and consider the same
term [s] in a slightly different context [Gamma']. For this
we prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. For this, we need a careful definition
of
- the _free variables_ of a term -- i.e., the variables occuring
in the term that are not in the scope of a function
abstraction that binds them.
*)
(* ###################################################################### *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y] *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2"
| Case_aux c "afi_abs"
| Case_aux c "afi_if1" | Case_aux c "afi_if2"
| Case_aux c "afi_if3" ].
Hint Constructors appears_free_in.
(** A term in which no variables appear free is said to be _closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(* ###################################################################### *)
(** ** Substitution *)
(** We first need a technical lemma connecting free variables and
typing contexts. If a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it must
be the case that [Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [extend_neq], noting
that [x] and [y] are different variables. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
(** Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed -- that is, it has no free variables. *)
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of [Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 \in T12]. The induction
hypothesis is that for any context [Gamma''], if [Gamma,
y:T11] and [Gamma''] assign the same types to all the free
variables in [t12], then [t12] has type [T12] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the
free variables in [t]; we must show [Gamma' |- \y:T11. t12 \in
T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 \in
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must either be [y], or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, we note that any variable
other than [y] which occurs free in [t12] also occurs free in
[t = \y:T11. t12], and by assumption [Gamma] and [Gamma']
agree on all such variables, and hence so do [Gamma, y:T11]
and [Gamma', y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. However, we note that all
free variables in [t1] are also free in [t1 t2], and similarly
for free variables in [t2]; hence the desired result follows
by the two IHs.
*)
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** One technical subtlety in the statement of the lemma is that we
assign [v] the type [U] in the _empty_ context -- in other words,
we assume [v] is closed. This assumption considerably simplifies
the [T_Abs] case of the proof (compared to assuming [Gamma |- v \in
U], which would be the other reasonable assumption at this point)
because the context invariance lemma then tells us that [v] has
type [U] in any context at all -- we don't have to worry about
free variables in [v] clashing with the variable being introduced
into the context by [T_Abs].
_Proof_: We prove, by induction on [t], that, for all [T] and
[Gamma], if [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T].
- If [t] is a variable, there are two cases to consider, depending
on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x \in T] we
conclude that [U = T]. We must show that [[x:=v]x = v] has
type [T] under [Gamma], given the assumption that [v] has
type [U = T] under the empty context. This follows from
context invariance: if a closed term has type [T] in the
empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 \in T']
and [|- v \in U], then [Gamma' |- [x:=v]t12 \in T'].
The substitution in the conclusion behaves differently,
depending on whether [x] and [y] are the same variable name.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. But we know [Gamma,x:U |- t : T], and since the
variable [y] does not appear free in [\y:T11. t12], the
context invariance lemma yields [Gamma |- t \in T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 \in
T12] by inversion of the typing relation, and [Gamma,y:T11,x:U
|- t12 \in T12] follows from this by the context invariance
lemma, so the IH applies, giving us [Gamma,y:T11 |- [x:=v]t12 \in
T12]. By [T_Abs], [Gamma |- \y:T11. [x:=v]t12 \in T11->T12], and
by the definition of substitution (noting that [x <> y]),
[Gamma |- \y:T11. [x:=v]t12 \in T11->T12] as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
Another technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[extend Gamma x U |- t \in T] is not completely generic, in
the sense that one of the "slots" in the typing relation -- namely
the context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
(** The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way. *)
(* ###################################################################### *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T], and takes an evaluation step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
evaluation relation preserves types.
*)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
(** _Proof_: by induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis.
*)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(** **** Exercise: 2 stars (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty |- t \in T]? If so, prove it. If not, give a
counter-example not involving conditionals.
(* FILL IN HERE *)
[]
*)
(* ###################################################################### *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars (types_unique) *)
(** Another pleasant property of the STLC is that types are
unique: a given term (in a given context) has at most one
type. *)
(** Formalize this statement and prove it. *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 1 star (progress_preservation_statement) *)
(** Without peeking, write down the progress and preservation
theorems for the simply typed lambda-calculus. *)
(** [] *)
(** **** Exercise: 2 stars (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule:
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma |- zap : T
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing
relation of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool.t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
End STLCProp.
(* ###################################################################### *)
(* ###################################################################### *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity) *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing... *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tnat"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0" ].
(** **** Exercise: 4 stars (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Progress theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties (up to [soundness]) of
the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
(* FILL IN HERE *)
(** [] *)
End STLCArith.
(* $Date: 2014-04-23 09:37:37 -0400 (Wed, 23 Apr 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_SYMBOL_V
`define SKY130_FD_SC_HDLL__O2BB2A_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] d;
reg [31:0] c;
wire [31:0] q = crc (d, c);
reg [31:0] q_r;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
q_r <= q;
c <= q;
d <= {d[62:0], ^d[63:48]};
//$write("%d crc(%x,%x)=%x\n", cyc, d, c, q);
if (cyc==1) begin
// Assign inputs randomly
q_r <= 32'h12345678;
c <= 32'h12345678;
d <= 64'hffffffff_ffffffff;
end
if (cyc==2) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==3) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==4) begin
d <= 64'h50183721_81a04b1a;
end
if (cyc==5) begin
end
if (cyc==9) begin
if (q !== 32'h38295e96) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function [31:0] crc;
input [63:0] di;
input [31:0] ci;
reg [63:0] drev;
begin
drev = reverse(di);
crc = newcrc(drev, ci);
end
endfunction
function [63:0] reverse;
input [63:0] di;
integer i;
begin
reverse = 64'b0;
for (i=0; i<64; i=i+1) reverse[i] = di[63-i];
end
endfunction
function [31:0] newcrc;
input [63:0] D;
input [31:0] C;
reg [31:0] N;
reg [31:0] DT;
begin
N = 32'b0;
// Note this isn't a real CRC code; it's been munged for privacy
N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0]
^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1];
N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0]
^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0];
N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11]
^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7];
N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0]
^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1];
N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0]
^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2];
N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1]
^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1];
N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1]
^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0];
N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0]
^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4];
N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2]
^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6];
N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7]
^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1];
N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1]
^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2];
N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1]
^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1];
N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2]
^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6];
N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11]
^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9];
N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0]
^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1];
N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2]
^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5];
N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1]
^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6];
N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0]
^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0];
N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7]
^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0];
N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2]
^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0];
N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1]
^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4];
N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1]
^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2];
N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3]
^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5];
N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3]
^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1];
N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0]
^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0];
N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2]
^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6];
N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0]
^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1];
N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2]
^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3];
N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0]
^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0];
N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0]
^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0];
N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0]
^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0];
N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0]
^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2];
newcrc = N;
end
endfunction
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Euclidean Division *)
(** Initial Contribution by Claude Marché and Xavier Urbain *)
Require Export ZArith_base.
Require Import Zbool ZArithRing Zcomplements Setoid Morphisms.
Local Open Scope Z_scope.
(** The definition of the division is now in [BinIntDef], the initial
specifications and properties are in [BinInt]. *)
Notation Zdiv_eucl_POS := Z.pos_div_eucl (only parsing).
Notation Zmod := Z.modulo (only parsing).
Notation Zmod_POS_bound := Z.pos_div_eucl_bound (only parsing).
Notation Zmod_pos_bound := Z.mod_pos_bound (only parsing).
Notation Zmod_neg_bound := Z.mod_neg_bound (only parsing).
(** * Main division theorems *)
(** NB: many things are stated twice for compatibility reasons *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Z.pos_div_eucl a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
intros b Hb a. Z.swap_greater.
generalize (Z.pos_div_eucl_eq a b Hb) (Z.pos_div_eucl_bound a b Hb).
destruct Z.pos_div_eucl. rewrite Z.mul_comm. auto.
Qed.
Theorem Z_div_mod a b :
b > 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
Z.swap_greater. intros Hb.
assert (Hb' : b<>0) by (now destruct b).
generalize (Z.div_eucl_eq a b Hb') (Z.mod_pos_bound a b Hb).
unfold Z.modulo. destruct Z.div_eucl. auto.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Z.abs r < Z.abs b /\ Z.sgn r <> - Z.sgn b.
(* In the last formulation, [ Z.sgn r <> - Z.sgn b ] is less nice than saying
[ Z.sgn r = Z.sgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
unfold Remainder, Remainder_alt.
intros [ | r | r ] [ | b | b ]; intuition try easy.
- now apply Z.opp_lt_mono.
- right; split.
+ now apply Z.opp_lt_mono.
+ apply Pos2Z.neg_is_nonpos.
Qed.
#[global]
Hint Unfold Remainder : core.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full a b :
b <> 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
intros Hb.
generalize (Z.div_eucl_eq a b Hb)
(Z.mod_pos_bound a b) (Z.mod_neg_bound a b).
unfold Z.modulo. destruct Z.div_eucl as (q,r).
intros EQ POS NEG.
split; auto.
red; destruct b.
now destruct Hb. left; now apply POS. right; now apply NEG.
Qed.
(** The same results as before, stated separately in terms of Z.div and Z.modulo *)
Lemma Z_mod_remainder a b : b<>0 -> Remainder (a mod b) b.
Proof.
unfold Z.modulo; intros Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Z.div_eucl; tauto.
Qed.
Lemma Z_mod_lt a b : b > 0 -> 0 <= a mod b < b.
Proof (fun Hb => Z.mod_pos_bound a b (Z.gt_lt _ _ Hb)).
Lemma Z_mod_neg a b : b < 0 -> b < a mod b <= 0.
Proof (Z.mod_neg_bound a b).
Lemma Z_div_mod_eq_full a b : a = b*(a/b) + (a mod b).
Proof.
now destruct (Z.eq_dec b 0) as [->|?]; [destruct a|apply Z.div_mod].
Qed.
#[deprecated(since="8.14",note="Z_div_mod_eq_full instead")]
Lemma Z_div_mod_eq a b : b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros. apply Z_div_mod_eq_full.
Qed.
Lemma Zmod_eq_full a b : b<>0 -> a mod b = a - (a/b)*b.
Proof. intros. rewrite Z.mul_comm. now apply Z.mod_eq. Qed.
Lemma Zmod_eq a b : b>0 -> a mod b = a - (a/b)*b.
Proof. intros. apply Zmod_eq_full. now destruct b. Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Z.div_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Arguments Zdiv_eucl_exist : default implicits.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique b q1 q2 r1 r2 :
0 <= r1 < Z.abs b -> 0 <= r2 < Z.abs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros Hr1 Hr2 H. rewrite <- (Z.abs_sgn b), <- !Z.mul_assoc in H.
destruct (Z.div_mod_unique (Z.abs b) (Z.sgn b * q1) (Z.sgn b * q2) r1 r2); auto.
split; trivial.
apply Z.mul_cancel_l with (Z.sgn b); trivial.
rewrite Z.sgn_null_iff, <- Z.abs_0_iff. destruct Hr1; Z.order.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof Z.div_mod_unique.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof Z.div_unique.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof Z.mod_unique.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
intros a; destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = a.
Proof.
intros a; destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
intros a; destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
intros a; destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z.eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros a. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros a. zero_or_not a. apply Z.div_1_r. Qed.
#[global]
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof Z.div_1_l.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof Z.mod_1_l.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof Z.div_same.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros a. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros a b. now zero_or_not b; [apply Z.mul_0_r|apply Z.mod_mul]. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof Z.div_mul.
(** * Order results about Z.modulo and Z.div *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto using Z.gt_lt. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; apply Z.le_ge, Z_div_pos; auto using Z.ge_le.
Qed.
(* Division of non-negative numbers is non-negative. *)
Lemma Z_div_nonneg_nonneg : forall a b, 0 <= a -> 0 <= b -> 0 <= a / b.
Proof.
intros a b. destruct b; intros; now (rewrite Zdiv_0_r + apply Z_div_pos).
Qed.
(* Modulo for a non-negative divisor is non-negative. *)
Lemma Z_mod_nonneg_nonneg : forall a b, 0 <= a -> 0 <= b -> 0 <= a mod b.
Proof.
destruct b; intros; now (rewrite Zmod_0_r + apply Z_mod_lt).
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof.
intros a b b_ge_2 a_gt_0.
apply Z.div_lt.
- apply Z.gt_lt; exact a_gt_0.
- apply (Z.lt_le_trans _ 2).
+ reflexivity.
+ apply Z.ge_le; exact b_ge_2.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof Z.div_small.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof Z.mod_small.
(** [Z.ge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Z.le_ge. apply Z.div_le_mono; auto using Z.gt_lt, Z.ge_le. Qed.
(** Same, with [Z.le]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto using Z.gt_lt. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto using Z.gt_lt. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Z.le_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additional inequalities about Z.div. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; intuition auto using Z.lt_le_incl. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Z.sgn (a/b) * Z.sgn a * Z.sgn b.
Proof.
intros a b; destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z.div_pos (Zpos a) (Zpos b)); unfold Z.div, Z.div_eucl;
destruct Z.pos_div_eucl as (q,r); destruct r;
rewrite ?Z.mul_1_r, <-?Z.opp_eq_mul_m1, ?Z.sgn_opp, ?Z.opp_involutive;
match goal with [|- (_ -> _ -> ?P) -> _] =>
intros HH; assert (HH1 : P); auto with zarith
end; apply Z.sgn_nonneg; auto with zarith.
Qed.
(** * Relations between usual operations and Z.modulo and Z.div *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros a b c. zero_or_not c.
- now rewrite Z.mul_0_r, Z.add_0_r.
- now apply Z.mod_add.
Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof Z.div_add.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof Z.div_add_l.
(** [Z.opp] and [Z.div], [Z.modulo].
Due to the choice of convention for our Euclidean division,
some of the relations about [Z.opp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros a b. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros a b. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros a b. now zero_or_not b; [intros; subst|apply Z.mod_opp_l_z]. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros a b. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros a b. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros a b ?. now zero_or_not b; [destruct a|apply Z.mod_opp_r_nz]. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros a b ?. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, b <> 0 -> a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b; [easy|]. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros a b ?. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, b <> 0 -> a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b; [easy|]. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros a b c ?. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros a b c ?. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros a b c. zero_or_not c. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros a b c. zero_or_not b. rewrite (Z.mul_comm b c); zero_or_not c.
+ now rewrite !Z.mul_0_r.
+ rewrite (Z.mul_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros a n. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros a b n. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros a b n. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros a b n.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite (Zplus_mod _ ((-1) * (b mod n))).
rewrite Zmult_mod.
rewrite (Zmult_mod _ (b mod n)).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Section EqualityModulo.
Variable N:Z.
Definition eqm a b := (a mod N = b mod N).
Infix "==" := eqm (at level 70).
Lemma eqm_refl : forall a, a == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym : forall a b, a == b -> b == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans : forall a b c,
a == b -> b == c -> a == c.
Proof. now unfold eqm; intros a b c ->. Qed.
Instance eqm_setoid : Equivalence eqm.
Proof.
constructor; [exact eqm_refl | exact eqm_sym | exact eqm_trans].
Qed.
Instance Zplus_eqm : Proper (eqm ==> eqm ==> eqm) Z.add.
Proof.
unfold eqm; repeat red; intros ? ? H ? ? H0.
rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Instance Zminus_eqm : Proper (eqm ==> eqm ==> eqm) Z.sub.
Proof.
unfold eqm; repeat red; intros ? ? H ? ? H0.
rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Instance Zmult_eqm : Proper (eqm ==> eqm ==> eqm) Z.mul.
Proof.
unfold eqm; repeat red; intros ? ? H ? ? H0.
rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Instance Zopp_eqm : Proper (eqm ==> eqm) Z.opp.
Proof.
intros x y H. change ((-x)==(-y)) with ((0-x)==(0-y)). now rewrite H.
Qed.
Lemma Zmod_eqm : forall a, (a mod N) == a.
Proof.
intros a; exact (Zmod_mod a N).
Qed.
(* NB: Z.modulo and Z.div are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
End EqualityModulo.
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros a b c ? ?. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.div_div; auto.
apply Z.le_neq; auto.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
Lemma Zmod_div : forall a b, a mod b / b = 0.
Proof.
intros a b.
zero_or_not b.
auto using Z.mod_div.
Qed.
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros a b c ? ? ?. zero_or_not b. now rewrite Z.mul_0_r.
apply Z.div_mul_le; auto.
apply Z.le_neq; auto.
Qed.
(** Z.modulo is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
intros. rewrite Z.mod_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zdiv2_div : forall a, Z.div2 a = a/2.
Proof Z.div2_div.
Lemma Zmod_odd : forall a, a mod 2 = if Z.odd a then 1 else 0.
Proof.
intros a. now rewrite <- Z.bit0_odd, <- Z.bit0_mod.
Qed.
Lemma Zmod_even : forall a, a mod 2 = if Z.even a then 0 else 1.
Proof.
intros a. rewrite Zmod_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zodd_mod : forall a, Z.odd a = Zeq_bool (a mod 2) 1.
Proof.
intros a. rewrite Zmod_odd. now destruct Z.odd.
Qed.
Lemma Zeven_mod : forall a, Z.even a = Zeq_bool (a mod 2) 0.
Proof.
intros a. rewrite Zmod_even. now destruct Z.even.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
now intros; apply Z_div_same_full; intros ->.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
now intros; apply Z_div_plus_full; intros ->.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
now intros; apply Z_div_mult_full; intros ->.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
now intros; apply Z_div_exact_full_2; auto; intros ->.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Z.modulo *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if r' <? b then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if r' <? b then r' else (r' - b)
| xH => if 2 <=? b then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => a
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => a
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct a b : Zmod_POS a b = snd (Z.pos_div_eucl a b).
Proof.
induction a as [a IH|a IH| ]; simpl; rewrite ?IH.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
case Z.leb_spec; trivial.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = a mod b.
Proof.
intros a b; unfold Z.modulo; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Z.pos_div_eucl p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Z.abs b}.
Proof.
intros b Hb a.
destruct (Z_le_gt_dec 0 b) as [Hb'|Hb'].
- assert (Hb'' : b > 0) by (apply Z.lt_gt, Z.le_neq; auto).
rewrite Z.abs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
- assert (Hb'' : - b > 0).
{ now apply Z.lt_gt, Z.opp_lt_mono; rewrite Z.opp_involutive; apply Z.gt_lt. }
destruct (Zdiv_eucl_exist Hb'' a) as ((q,r),[]).
exists (- q, r).
split.
+ rewrite <- Z.mul_opp_comm; assumption.
+ rewrite Z.abs_neq; [ assumption | apply Z.lt_le_incl, Z.gt_lt; auto ].
Qed.
Arguments Zdiv_eucl_extended : default implicits.
(** * Division and modulo in Z agree with same in nat: *)
#[deprecated(since="8.14",note="Use Nat2Z.inj_div instead.")]
Lemma div_Zdiv (n m: nat): m <> O ->
Z.of_nat (n / m) = Z.of_nat n / Z.of_nat m.
Proof. intros. apply Nat2Z.inj_div. Qed.
#[deprecated(since="8.14",note="Use Nat2Z.inj_mod instead.")]
Lemma mod_Zmod (n m: nat): m <> O ->
Z.of_nat (n mod m) = (Z.of_nat n) mod (Z.of_nat m).
Proof. intros. apply Nat2Z.inj_mod. Qed.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] operand_a = crc[7:0];
wire [7:0] operand_b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[6:0]),
// Inputs
.clk (clk),
.operand_a (operand_a[7:0]),
.operand_b (operand_b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
// Inputs
input wire clk,
input wire [7:0] operand_a, // operand a
input wire [7:0] operand_b, // operand b
// Outputs
output wire [6:0] out
);
wire [6:0] clz_a;
wire [6:0] clz_b;
clz u_clz_a
(
// Inputs
.data_i (operand_a),
.out (clz_a));
clz u_clz_b
(
// Inputs
.data_i (operand_b),
.out (clz_b));
assign out = clz_a - clz_b;
`ifdef TEST_VERBOSE
always @(posedge clk)
$display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
`endif
endmodule
`define def_0000_001x 8'b0000_0010, 8'b0000_0011
`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111
`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011
`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111
`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx
`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011
`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111
`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011
`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111
`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011
`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111
`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011
`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111
`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011
`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111
`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011
`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111
`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011
`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111
`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011
`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111
`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011
`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111
`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011
`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111
`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011
`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111
`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011
`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111
`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011
`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111
`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011
`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111
`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011
`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111
`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011
`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111
`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011
`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111
`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011
`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111
`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011
`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111
`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011
`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111
`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011
`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111
`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011
`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111
`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011
`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111
`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011
`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111
`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011
`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111
`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011
`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111
`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011
`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111
`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011
`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111
`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011
`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111
`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011
`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111
`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx
`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx
`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx
`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx
`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx
`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx
`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx
`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx
`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx
`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx
`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx
`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx
`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx
`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx
`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx
`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \
`def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx
`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx
`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx
module clz(
input wire [7:0] data_i,
output wire [6:0] out
);
// -----------------------------
// Reg declarations
// -----------------------------
reg [2:0] clz_byte0;
reg [2:0] clz_byte1;
reg [2:0] clz_byte2;
reg [2:0] clz_byte3;
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte0 = 3'b000;
`def_01xx_xxxx : clz_byte0 = 3'b001;
`def_001x_xxxx : clz_byte0 = 3'b010;
`def_0001_xxxx : clz_byte0 = 3'b011;
`def_0000_1xxx : clz_byte0 = 3'b100;
`def_0000_01xx : clz_byte0 = 3'b101;
`def_0000_001x : clz_byte0 = 3'b110;
8'b0000_0001 : clz_byte0 = 3'b111;
8'b0000_0000 : clz_byte0 = 3'b111;
default : clz_byte0 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte1 = 3'b000;
`def_01xx_xxxx : clz_byte1 = 3'b001;
`def_001x_xxxx : clz_byte1 = 3'b010;
`def_0001_xxxx : clz_byte1 = 3'b011;
`def_0000_1xxx : clz_byte1 = 3'b100;
`def_0000_01xx : clz_byte1 = 3'b101;
`def_0000_001x : clz_byte1 = 3'b110;
8'b0000_0001 : clz_byte1 = 3'b111;
8'b0000_0000 : clz_byte1 = 3'b111;
default : clz_byte1 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte2 = 3'b000;
`def_01xx_xxxx : clz_byte2 = 3'b001;
`def_001x_xxxx : clz_byte2 = 3'b010;
`def_0001_xxxx : clz_byte2 = 3'b011;
`def_0000_1xxx : clz_byte2 = 3'b100;
`def_0000_01xx : clz_byte2 = 3'b101;
`def_0000_001x : clz_byte2 = 3'b110;
8'b0000_0001 : clz_byte2 = 3'b111;
8'b0000_0000 : clz_byte2 = 3'b111;
default : clz_byte2 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte3 = 3'b000;
`def_01xx_xxxx : clz_byte3 = 3'b001;
`def_001x_xxxx : clz_byte3 = 3'b010;
`def_0001_xxxx : clz_byte3 = 3'b011;
`def_0000_1xxx : clz_byte3 = 3'b100;
`def_0000_01xx : clz_byte3 = 3'b101;
`def_0000_001x : clz_byte3 = 3'b110;
8'b0000_0001 : clz_byte3 = 3'b111;
8'b0000_0000 : clz_byte3 = 3'b111;
default : clz_byte3 = 3'bxxx;
endcase
assign out = {4'b0000, clz_byte1};
endmodule // clz
|
/*
* Copyright (c) 2014, Franck Jullien <[email protected]>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "timescale.v"
module orpsoc_tb;
reg clk = 0;
reg rst_n = 0;
////////////////////////////////////////////////////////////////////////
//
// Generate clock (50MHz) and external reset
//
////////////////////////////////////////////////////////////////////////
always
#10 clk <= ~clk;
initial begin
#100 rst_n <= 0;
#200 rst_n <= 1;
end
////////////////////////////////////////////////////////////////////////
//
// Add --vcd and --timeout options to the simulation
//
////////////////////////////////////////////////////////////////////////
//Force simulation stop after timeout cycles
reg [63:0] timeout;
initial
if($value$plusargs("timeout=%d", timeout)) begin
#timeout $display("Timeout: Forcing end of simulation");
$finish;
end
//FIXME: Add more options for VCD logging
initial begin
if($test$plusargs("vcd")) begin
@(posedge orpsoc_tb.dut.init_done)
$dumpfile("neek.vcd");
$dumpvars(0);
end
end
initial begin
@(posedge orpsoc_tb.dut.init_done)
$display("----- DDR init done ----\n");
end
////////////////////////////////////////////////////////////////////////
//
// ELF program loading
//
////////////////////////////////////////////////////////////////////////
integer mem_words;
integer i;
reg [31:0] mem_word;
reg [1023:0] elf_file;
reg [31:0] temp;
initial begin
if($value$plusargs("elf_load=%s", elf_file)) begin
$elf_load_file(elf_file);
mem_words = $elf_get_size / 4;
$display("Loading %d words", mem_words);
for(i = 0; i < mem_words; i = i + 1) begin
temp = $elf_read_32(i * 4);
orpsoc_tb.ddr0.write_mem((i * 2), temp[15:0]);
orpsoc_tb.ddr0.write_mem((i * 2) + 1, temp[31:16]);
end
end else
$display("No ELF file specified");
end
////////////////////////////////////////////////////////////////////////
//
// DUT
//
////////////////////////////////////////////////////////////////////////
wire [12:0] ddr_a_pad_o;
wire [1:0] ddr_ba_pad_o;
wire ddr_cas_pad_o;
wire ddr_cke_pad_o;
wire ddr_clk_pad_o;
wire ddr_clk_n_pad_o;
wire ddr_cs_n_pad_o;
wire [15:0] ddr_dq_pad_io;
wire [1:0] ddr_dqs_pad_io;
wire [1:0] ddr_dqm_pad_o;
wire ddr_ras_pad_o;
wire ddr_we_pad_o;
wire uart_tx;
wire [15:0] flash_dq;
wire [22:0] flash_adr;
wire flash_adv_n;
wire flash_ce_n;
wire flash_clk;
wire flash_oe_n;
wire flash_rst_n;
wire flash_wait;
wire flash_we_n;
orpsoc_top dut
(
.clock_50_pad_i (clk),
.reset_n_pad_i (rst_n),
.ddr_dm_pad_o (ddr_dqm_pad_o),
.ddr_dq_pad_io (ddr_dq_pad_io),
.ddr_dqs_pad_io (ddr_dqs_pad_io),
.ddr_a_pad_o (ddr_a_pad_o),
.ddr_ba_pad_o (ddr_ba_pad_o),
.ddr_cas_n_pad_o (ddr_cas_pad_o),
.ddr_cke_pad_o (ddr_cke_pad_o),
.ddr_clk_pad_o (ddr_clk_pad_o),
.ddr_clk_n_pad_o (ddr_clk_n_pad_o),
.ddr_cs_n_pad_o (ddr_cs_n_pad_o),
.ddr_ras_n_pad_o (ddr_ras_pad_o),
.ddr_we_n_pad_o (ddr_we_pad_o),
.led_debug_pad_o (),
`ifdef VGA_LCD
.hsync_n_pad_o (),
.vsync_n_pad_o (),
.blank_n_pad_o (),
.lcd_data_pad_o (),
.pixel_clock_pad_o (),
.lcd_rst_n_pad_o (),
.lcd_scen_pad_o (),
.lcd_scl_pad_o (),
.lcd_sda_pad_io (),
.vga_data_pad_o (),
.vga_clock_pad_o (),
.vga_hsync_pad_o (),
.vga_vsync_pad_o (),
.vga_blank_pad_o (),
.vga_sync_pad_o (),
`endif
`ifdef ETHERNET
.eth0_tx_clk_pad_i (1'b0),
.eth0_tx_data_pad_o (),
.eth0_tx_en_pad_o (),
.eth0_rx_clk_pad_i (1'b0),
.eth0_rx_data_pad_i (4'b0),
.eth0_rx_dv_pad_i (1'b0),
.eth0_rx_err_pad_i (1'b0),
.eth0_col_pad_i (1'b0),
.eth0_crs_pad_i (1'b0),
.eth0_mdc_pad_o (),
.eth0_md_pad_io (),
.eth0_rst_n_pad_o (),
`endif
`ifdef SPI
.spi0_sck_pad_o (),
.spi0_mosi_pad_o (),
.spi0_miso_pad_i (1'b0),
.spi0_ss_pad_o (),
`endif
.flash_dq_pad_io (flash_dq),
.flash_adr_pad_o (flash_adr),
.flash_adv_n_pad_o (flash_adv_n),
.flash_ce_n_pad_o (flash_ce_n),
.flash_clk_pad_o (flash_clk),
.flash_oe_n_pad_o (flash_oe_n),
.flash_rst_n_pad_o (flash_rst_n),
.flash_wait_pad_i (flash_wait),
.flash_we_n_pad_o (flash_we_n),
.uart_rx_pad_i (),
.uart_tx_pad_o (uart_tx)
);
////////////////////////////////////////////////////////////////////////
//
// UART decoder
//
////////////////////////////////////////////////////////////////////////
//FIXME: Get correct baud rate from parameter
uart_decoder
#(.uart_baudrate_period_ns(8680 / 2))
uart_decoder0
(
.clk(clk),
.uart_tx(uart_tx)
);
////////////////////////////////////////////////////////////////////////
//
// SDRAM
//
////////////////////////////////////////////////////////////////////////
ddr #(.DEBUG(0))
ddr0
(
.Clk (ddr_clk_pad_o),
.Clk_n (ddr_clk_n_pad_o),
.Cke (ddr_cke_pad_o),
.Cs_n (ddr_cs_n_pad_o),
.Ras_n (ddr_ras_pad_o),
.Cas_n (ddr_cas_pad_o),
.We_n (ddr_we_pad_o),
.Ba (ddr_ba_pad_o),
.Addr (ddr_a_pad_o),
.Dm (ddr_dqm_pad_o),
.Dq (ddr_dq_pad_io),
.Dqs (ddr_dqs_pad_io)
);
////////////////////////////////////////////////////////////////////////
//
// FLAH
//
////////////////////////////////////////////////////////////////////////
x28fxxxp30 part
(
.A ({1'b0, flash_adr}),
.DQ (flash_dq),
.W_N (flash_we_n),
.G_N (flash_oe_n),
.E_N (flash_ce_n),
.L_N (flash_adv_n),
.K (flash_clk),
.WAIT (flash_wait),
.WP_N (1'b1),
.RP_N (flash_rst_n),
.VDD (36'd1800),
.VDDQ (36'd2500),
.VPP (36'd1800),
.Info (32'd1)
);
endmodule
|
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.2 Build 222 07/20/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
wire [2:0] sub_wire0;
wire [2:0] source = sub_wire0[2:0];
altsource_probe altsource_probe_component (
.probe (probe),
.source_clk (source_clk),
.source (sub_wire0)
// synopsys translate_off
,
.clr (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = "RST",
altsource_probe_component.probe_width = 0,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
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// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 11
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module sys_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_11_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
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//faux_hd_command_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module faux_hd_command_layer (
input rst, //reset
input clk,
output command_layer_ready,
output command_layer_busy,
output hd_read_from_host,
output [31:0] hd_data_from_host,
output hd_write_to_host,
input [31:0] hd_data_to_host,
input transport_layer_ready,
output reg send_reg_stb,
output reg send_dma_act_stb,
output reg send_data_stb,
output reg send_pio_stb,
output reg send_dev_bits_stb,
input remote_abort,
input xmit_error,
input read_crc_fail,
input h2d_reg_stb,
input h2d_data_stb,
input pio_request,
output reg [15:0] pio_transfer_count,
output reg pio_direction,
output reg [7:0] pio_e_status,
//FIS Structure
input [7:0] h2d_command,
input [15:0] h2d_features,
input h2d_cmd_bit,
input [3:0] h2d_port_mult,
input [7:0] h2d_control,
input [7:0] h2d_device,
input [47:0] h2d_lba,
input [15:0] h2d_sector_count,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [7:0] d2h_status,
output reg [7:0] d2h_error,
output reg [3:0] d2h_port_mult,
output reg [7:0] d2h_device,
output reg [47:0] d2h_lba,
output reg [15:0] d2h_sector_count,
//command layer data interface
input cl_if_strobe,
output [31:0] cl_if_data,
output cl_if_ready,
input cl_if_activate,
output [23:0] cl_if_size,
input cl_of_strobe,
input [31:0] cl_of_data,
output [1:0] cl_of_ready,
input [1:0] cl_of_activate,
output [23:0] cl_of_size,
output [3:0] cl_state
);
//Parameters
parameter SLEEP_START = 4'h0;
parameter SEND_DIAGNOSTICS = 4'h1;
parameter IDLE = 4'h2;
parameter DMA_READY = 4'h3;
parameter READ_DATA = 4'h4;
parameter SEND_DATA = 4'h5;
parameter READ_IN_PROGRESS = 4'h6;
parameter SEND_STATUS = 4'h7;
parameter SLEEP_LENGTH = 100;
//Registers/Wires
reg [3:0] state = SLEEP_START;
wire idle;
reg [8:0] byte_count = 0;
reg [16:0] sector_count = 0;
reg [16:0] sector_size = 16'h0000;
reg [15:0] sleep_count = 0;
wire soft_reset;
//Asynchronous Logic
assign idle = (state == IDLE);
assign command_layer_busy = !idle;
assign command_layer_ready = idle;
//Short circuit the ping pong fifos
assign hd_read_from_host = cl_of_strobe;
assign hd_data_from_host = cl_of_data;
assign cl_of_ready = 1;
assign cl_of_size = 2048;
assign hd_write_to_host = cl_if_strobe;
assign cl_if_data = hd_data_to_host;
assign cl_if_ready = 1;
assign cl_if_size = 24'h0100;
assign soft_reset = h2d_control[`CONTROL_SRST_BIT];
assign cl_state = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= SLEEP_START;
send_reg_stb <= 0;
send_dma_act_stb <= 0;
send_data_stb <= 0;
send_pio_stb <= 0;
send_dev_bits_stb <= 0;
sector_count <= 0;
sector_size <= 1000;
sleep_count <= 0;
pio_transfer_count <= 0;
pio_direction <= 0;
pio_e_status <= 0;
d2h_interrupt <= 0;
d2h_notification <= 0;
d2h_status <= 8'h50;
d2h_error <= 1;
d2h_port_mult <= 0;
d2h_lba <= 1;
d2h_sector_count <= 1;
d2h_device <= 0;
byte_count <= 0;
end
else begin
//Strobe Lines
send_reg_stb <= 0;
send_dma_act_stb <= 0;
send_data_stb <= 0;
send_pio_stb <= 0;
send_dev_bits_stb <= 0;
if (soft_reset) begin
if (soft_reset) begin
$display ("Reset from soft reset");
end
state <= SLEEP_START;
sleep_count <= 0;
end
case (state)
SLEEP_START: begin
if (sleep_count < SLEEP_LENGTH) begin
sleep_count <= sleep_count + 1;
end
else begin
state <= SEND_DIAGNOSTICS;
end
end
SEND_DIAGNOSTICS: begin
$display ("Send Diagnostics");
send_reg_stb <= 1;
state <= IDLE;
end
IDLE: begin
if (h2d_reg_stb) begin
if (h2d_cmd_bit) begin
d2h_lba <= h2d_lba;
d2h_sector_count <= h2d_sector_count;
if (h2d_sector_count == 0) begin
sector_size <= 17'h10000;
end
else begin
sector_size <= h2d_sector_count;
end
case (h2d_command)
`COMMAND_DMA_READ_EX: begin
//send_data_stb <= 1;
sector_count <= 0;
state <= SEND_DATA;
end
`COMMAND_DMA_WRITE_EX: begin
send_dma_act_stb <= 1;
sector_count <= 0;
state <= DMA_READY;
end
default: begin
//unrecognized command
$display ("fcl: Unrecognized command from host");
end
endcase
end
end
end
DMA_READY: begin
if (transport_layer_ready) begin
send_dma_act_stb <= 1;
byte_count <= 0;
state <= READ_DATA;
end
end
READ_DATA: begin
if (cl_of_activate && cl_of_strobe) begin
byte_count <= byte_count + 4;
end
if(byte_count == 508) begin
sector_count <= sector_count + 1;
end
if (h2d_data_stb) begin
if (sector_count < sector_size) begin
state <= DMA_READY;
end
else begin
state <= SEND_STATUS;
end
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
sector_count <= sector_count + 1;
send_data_stb <= 1;
state <= READ_IN_PROGRESS;
//state <= SEND_STATUS;
end
end
READ_IN_PROGRESS: begin
if (!transport_layer_ready) begin
state <= SEND_STATUS;
end
//if (sector_count < sector_size) begin
// state <= SEND_DATA;
//end
//else begin
// if (transport_layer_ready) begin
// send_reg_stb <= 1;
// //Send a done register
// state <= SEND_STATUS;
// end
//end
end
SEND_STATUS: begin
if (transport_layer_ready) begin
send_reg_stb <= 1;
//Send a done register
state <= IDLE;
end
end
default: begin
$display ("fcl: Entered illegal state, restart");
state <= SLEEP_START;
sleep_count <= 0;
end
endcase
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
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// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: axi_dwidth_converter
// AXI Memory-mapped data-width converter.
// This module instantiates downsizer and upsizer.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// top
// axi_downsizer
// a_downsizer
// axic_fifo
// fifo_gen
// fifo_coregen
// w_downsizer
// b_downsizer
// r_downsizer
// axi_upsizer
// a_upsizer
// fifo
// fifo_gen
// fifo_coregen
// w_upsizer
// w_upsizer_pktfifo
// r_upsizer
// r_upsizer_pktfifo
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_top #
(
parameter C_FAMILY = "virtex7",
// FPGA Family.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3, 2=AXI4LITE).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
// Range (AXI4LITE): 1 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of s_axi_wdata and s_axi_rdata.
// Range (AXI4, AXI3): 32, 64, 128, 256, 512, 1024.
// Range (AXILITE): 32, 64.
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of m_axi_wdata and m_axi_rdata.
// Range (AXI4, AXI3): 32, 64, 128, 256, 512, 1024.
// Range (AXILITE): 32, 64.
// S_DATA_WIDTH = M_DATA_WIDTH allowed only when AXI4/AXI3 and PACKING_LEVEL=2.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_FIFO_MODE = 0,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_MAX_SPLIT_BEATS = 256,
// Max burst length after transaction splitting due to downsizing.
// Range: 0 (no splitting), 1 (convert to singles), 16, 256.
parameter integer C_PACKING_LEVEL = 1,
// Upsizer packing mode.
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Global Signals
(* KEEP = "TRUE" *) input wire s_axi_aclk,
(* KEEP = "TRUE" *) input wire s_axi_aresetn,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface System Signals
(* KEEP = "TRUE" *) input wire m_axi_aclk,
(* KEEP = "TRUE" *) input wire m_axi_aresetn,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
wire aclk = s_axi_aclk;
wire aresetn = s_axi_aresetn;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_S_AXI_DATA_WIDTH / C_M_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_CONVERSION = 2;
localparam integer P_MAX_SPLIT_BEATS = (C_MAX_SPLIT_BEATS >= 16) ? C_MAX_SPLIT_BEATS :
(C_AXI_PROTOCOL == P_AXI4) ? 256 : 16;
wire [8-1:0] s_axi_awlen_i;
wire [2-1:0] s_axi_awlock_i;
wire [8-1:0] s_axi_arlen_i;
wire [2-1:0] s_axi_arlock_i;
wire [8-1:0] m_axi_awlen_i;
wire [2-1:0] m_axi_awlock_i;
wire [8-1:0] m_axi_arlen_i;
wire [2-1:0] m_axi_arlock_i;
wire [4-1:0] s_axi_awregion_i;
wire [4-1:0] s_axi_arregion_i;
wire [4-1:0] m_axi_awregion_i;
wire [4-1:0] m_axi_arregion_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_lite_tieoff
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}} ;
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}} ;
assign s_axi_rlast = 1'b0 ;
assign m_axi_awlen = 8'b0 ;
assign m_axi_awsize = 3'b0 ;
assign m_axi_awburst = 2'b0 ;
assign m_axi_awlock = 1'b0 ;
assign m_axi_awcache = 4'b0 ;
assign m_axi_awregion = 4'b0 ;
assign m_axi_awqos = 4'b0 ;
assign m_axi_wlast = 1'b0 ;
assign m_axi_arlen = 8'b0 ;
assign m_axi_arsize = 3'b0 ;
assign m_axi_arburst = 2'b0 ;
assign m_axi_arlock = 1'b0 ;
assign m_axi_arcache = 4'b0 ;
assign m_axi_arregion = 4'b0 ;
assign m_axi_arqos = 4'b0 ;
end else begin : gen_full_tieoff
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_awlen}: s_axi_awlen;
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock};
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI3) ? {4'b0000, s_axi_arlen}: s_axi_arlen;
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock};
assign m_axi_awlen = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_awlen_i[3:0]: m_axi_awlen_i;
assign m_axi_awlock = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_awlock_i : m_axi_awlock_i[0];
assign m_axi_arlen = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_arlen_i[3:0]: m_axi_arlen_i;
assign m_axi_arlock = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_arlock_i : m_axi_arlock_i[0];
assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;
assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;
assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;
assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;
end
if (C_S_AXI_DATA_WIDTH > C_M_AXI_DATA_WIDTH) begin : gen_downsizer
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_lite_downsizer
axi_dwidth_converter_v2_1_8_axi4lite_downsizer #(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ )
)
lite_downsizer_inst
(
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
end else if (((C_AXI_PROTOCOL == P_AXI3) && (P_MAX_SPLIT_BEATS > 0)) || (P_MAX_SPLIT_BEATS < 256) || (C_RATIO > 16)) begin : gen_cascaded_downsizer
localparam integer P_DATA_WIDTH_I = (C_RATIO > 16) ? 64 : C_M_AXI_DATA_WIDTH;
wire [C_AXI_ADDR_WIDTH-1:0] awaddr_i ;
wire [8-1:0] awlen_i ;
wire [3-1:0] awsize_i ;
wire [2-1:0] awburst_i ;
wire [2-1:0] awlock_i ;
wire [4-1:0] awcache_i ;
wire [3-1:0] awprot_i ;
wire [4-1:0] awregion_i ;
wire [4-1:0] awqos_i ;
wire awvalid_i ;
wire awready_i ;
wire [P_DATA_WIDTH_I-1:0] wdata_i ;
wire [P_DATA_WIDTH_I/8-1:0] wstrb_i ;
wire wlast_i ;
wire wvalid_i ;
wire wready_i ;
wire [2-1:0] bresp_i ;
wire bvalid_i ;
wire bready_i ;
wire [C_AXI_ADDR_WIDTH-1:0] araddr_i ;
wire [8-1:0] arlen_i ;
wire [3-1:0] arsize_i ;
wire [2-1:0] arburst_i ;
wire [2-1:0] arlock_i ;
wire [4-1:0] arcache_i ;
wire [3-1:0] arprot_i ;
wire [4-1:0] arregion_i ;
wire [4-1:0] arqos_i ;
wire arvalid_i ;
wire arready_i ;
wire [P_DATA_WIDTH_I-1:0] rdata_i ;
wire [2-1:0] rresp_i ;
wire rlast_i ;
wire rvalid_i ;
wire rready_i ;
wire [4-1:0] m_axi_awlen_ii;
wire [4-1:0] m_axi_arlen_ii;
wire [1-1:0] awlock_ii;
wire [1-1:0] arlock_ii;
axi_dwidth_converter_v2_1_8_axi_downsizer #(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_S_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,
.C_SUPPORTS_ID ( C_SUPPORTS_ID ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_S_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,
.C_M_AXI_DATA_WIDTH ( P_DATA_WIDTH_I ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ ) ,
.C_MAX_SPLIT_BEATS ( 256 )
)
first_downsizer_inst
(
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen_i ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock_i ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awregion ( s_axi_awregion_i) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen_i ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock_i ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arregion ( s_axi_arregion_i) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awaddr ( awaddr_i ) ,
.m_axi_awlen ( awlen_i ) ,
.m_axi_awsize ( awsize_i ) ,
.m_axi_awburst ( awburst_i ) ,
.m_axi_awlock ( awlock_i ) ,
.m_axi_awcache ( awcache_i ) ,
.m_axi_awprot ( awprot_i ) ,
.m_axi_awregion ( awregion_i ) ,
.m_axi_awqos ( awqos_i ) ,
.m_axi_awvalid ( awvalid_i ) ,
.m_axi_awready ( awready_i ) ,
.m_axi_wdata ( wdata_i ) ,
.m_axi_wstrb ( wstrb_i ) ,
.m_axi_wlast ( wlast_i ) ,
.m_axi_wvalid ( wvalid_i ) ,
.m_axi_wready ( wready_i ) ,
.m_axi_bresp ( bresp_i ) ,
.m_axi_bvalid ( bvalid_i ) ,
.m_axi_bready ( bready_i ) ,
.m_axi_araddr ( araddr_i ) ,
.m_axi_arlen ( arlen_i ) ,
.m_axi_arsize ( arsize_i ) ,
.m_axi_arburst ( arburst_i ) ,
.m_axi_arlock ( arlock_i ) ,
.m_axi_arcache ( arcache_i ) ,
.m_axi_arprot ( arprot_i ) ,
.m_axi_arregion ( arregion_i ) ,
.m_axi_arqos ( arqos_i ) ,
.m_axi_arvalid ( arvalid_i ) ,
.m_axi_arready ( arready_i ) ,
.m_axi_rdata ( rdata_i ) ,
.m_axi_rresp ( rresp_i ) ,
.m_axi_rlast ( rlast_i ) ,
.m_axi_rvalid ( rvalid_i ) ,
.m_axi_rready ( rready_i )
);
if (C_RATIO > 16) begin : gen_second_downsizer
axi_dwidth_converter_v2_1_8_axi_downsizer #(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_S_AXI_ID_WIDTH ( 1 ) ,
.C_SUPPORTS_ID ( 0 ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_S_AXI_DATA_WIDTH ( P_DATA_WIDTH_I ) ,
.C_M_AXI_DATA_WIDTH ( C_M_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ ) ,
.C_MAX_SPLIT_BEATS ( P_MAX_SPLIT_BEATS )
)
second_downsizer_inst
(
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( awaddr_i ) ,
.s_axi_awlen ( awlen_i ) ,
.s_axi_awsize ( awsize_i ) ,
.s_axi_awburst ( awburst_i ) ,
.s_axi_awlock ( awlock_i ) ,
.s_axi_awcache ( awcache_i ) ,
.s_axi_awprot ( awprot_i ) ,
.s_axi_awregion ( awregion_i ) ,
.s_axi_awqos ( awqos_i ) ,
.s_axi_awvalid ( awvalid_i ) ,
.s_axi_awready ( awready_i ) ,
.s_axi_wdata ( wdata_i ) ,
.s_axi_wstrb ( wstrb_i ) ,
.s_axi_wlast ( wlast_i ) ,
.s_axi_wvalid ( wvalid_i ) ,
.s_axi_wready ( wready_i ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( bresp_i ) ,
.s_axi_bvalid ( bvalid_i ) ,
.s_axi_bready ( bready_i ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( araddr_i ) ,
.s_axi_arlen ( arlen_i ) ,
.s_axi_arsize ( arsize_i ) ,
.s_axi_arburst ( arburst_i ) ,
.s_axi_arlock ( arlock_i ) ,
.s_axi_arcache ( arcache_i ) ,
.s_axi_arprot ( arprot_i ) ,
.s_axi_arregion ( arregion_i ) ,
.s_axi_arqos ( arqos_i ) ,
.s_axi_arvalid ( arvalid_i ) ,
.s_axi_arready ( arready_i ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rdata_i ) ,
.s_axi_rresp ( rresp_i ) ,
.s_axi_rlast ( rlast_i ) ,
.s_axi_rvalid ( rvalid_i ) ,
.s_axi_rready ( rready_i ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen_i ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock_i ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awregion ( m_axi_awregion_i) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen_i ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock_i ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arregion ( m_axi_arregion_i) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
end else begin : gen_axi3_conv
axi_protocol_converter_v2_1_8_axi_protocol_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_S_AXI_PROTOCOL ( P_AXI4 ) ,
.C_M_AXI_PROTOCOL ( P_AXI3 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_M_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ ) ,
.C_AXI_SUPPORTS_USER_SIGNALS (0) ,
.C_TRANSLATION_MODE ( P_CONVERSION )
)
axi3_conv_inst
(
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( awaddr_i ) ,
.s_axi_awlen ( awlen_i ) ,
.s_axi_awsize ( awsize_i ) ,
.s_axi_awburst ( awburst_i ) ,
.s_axi_awlock ( awlock_ii ) ,
.s_axi_awcache ( awcache_i ) ,
.s_axi_awprot ( awprot_i ) ,
.s_axi_awregion ( awregion_i ) ,
.s_axi_awqos ( awqos_i ) ,
.s_axi_awvalid ( awvalid_i ) ,
.s_axi_awready ( awready_i ) ,
.s_axi_wdata ( wdata_i ) ,
.s_axi_wstrb ( wstrb_i ) ,
.s_axi_wlast ( wlast_i ) ,
.s_axi_wvalid ( wvalid_i ) ,
.s_axi_wready ( wready_i ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( bresp_i ) ,
.s_axi_bvalid ( bvalid_i ) ,
.s_axi_bready ( bready_i ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( araddr_i ) ,
.s_axi_arlen ( arlen_i ) ,
.s_axi_arsize ( arsize_i ) ,
.s_axi_arburst ( arburst_i ) ,
.s_axi_arlock ( arlock_ii ) ,
.s_axi_arcache ( arcache_i ) ,
.s_axi_arprot ( arprot_i ) ,
.s_axi_arregion ( arregion_i ) ,
.s_axi_arqos ( arqos_i ) ,
.s_axi_arvalid ( arvalid_i ) ,
.s_axi_arready ( arready_i ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rdata_i ) ,
.s_axi_rresp ( rresp_i ) ,
.s_axi_rlast ( rlast_i ) ,
.s_axi_rvalid ( rvalid_i ) ,
.s_axi_rready ( rready_i ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen_ii ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock_i ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awregion ( m_axi_awregion_i) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen_ii ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock_i ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arregion ( m_axi_arregion_i) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_wid ( ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_arid ( ) ,
.m_axi_rid ( 1'b0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_buser ( ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_ruser ( ) ,
.m_axi_awuser ( ) ,
.m_axi_wuser ( ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_aruser ( ) ,
.m_axi_ruser ( 1'b0 )
);
assign awlock_ii = awlock_i[0];
assign arlock_ii = arlock_i[0];
assign m_axi_awlen_i = {4'b0, m_axi_awlen_ii};
assign m_axi_arlen_i = {4'b0, m_axi_arlen_ii};
end
end else begin : gen_simple_downsizer
axi_dwidth_converter_v2_1_8_axi_downsizer #(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_S_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,
.C_SUPPORTS_ID ( C_SUPPORTS_ID ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_S_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,
.C_M_AXI_DATA_WIDTH ( C_M_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ ) ,
.C_MAX_SPLIT_BEATS ( P_MAX_SPLIT_BEATS )
)
axi_downsizer_inst
(
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen_i ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock_i ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awregion ( s_axi_awregion_i) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen_i ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock_i ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arregion ( s_axi_arregion_i) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen_i ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock_i ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awregion ( m_axi_awregion_i) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen_i ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock_i ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arregion ( m_axi_arregion_i) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
end
end else begin : gen_upsizer
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_lite_upsizer
axi_dwidth_converter_v2_1_8_axi4lite_upsizer #(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ )
)
lite_upsizer_inst
(
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
end else begin : gen_full_upsizer
axi_dwidth_converter_v2_1_8_axi_upsizer #(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_S_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,
.C_SUPPORTS_ID ( C_SUPPORTS_ID ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_S_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,
.C_M_AXI_DATA_WIDTH ( C_M_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_WRITE ( C_AXI_SUPPORTS_WRITE ) ,
.C_AXI_SUPPORTS_READ ( C_AXI_SUPPORTS_READ ) ,
.C_FIFO_MODE (C_FIFO_MODE),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_PACKING_LEVEL ( C_PACKING_LEVEL ),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
axi_upsizer_inst
(
.s_axi_aresetn ( s_axi_aresetn ) ,
.s_axi_aclk ( s_axi_aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen_i ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock_i ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awregion ( s_axi_awregion_i) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen_i ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock_i ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arregion ( s_axi_arregion_i) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_aresetn ( m_axi_aresetn ) ,
.m_axi_aclk ( m_axi_aclk ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen_i ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock_i ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awregion ( m_axi_awregion_i) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen_i ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock_i ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arregion ( m_axi_arregion_i) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
end
end
endgenerate
endmodule
|
// altremote_remote_update_0.v
// This file was auto-generated from altera_remote_update_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module altremote_remote_update_0 (
output wire busy, // busy.busy
output wire [28:0] data_out, // data_out.data_out
input wire [2:0] param, // param.param
input wire read_param, // read_param.read_param
input wire reconfig, // reconfig.reconfig
input wire reset_timer, // reset_timer.reset_timer
input wire write_param, // write_param.write_param
input wire [23:0] data_in, // data_in.data_in
input wire [1:0] read_source, // read_source.read_source
input wire clock, // clock.clk
input wire reset // reset.reset
);
altera_remote_update_core remote_update_core (
.read_param (read_param), // read_param.read_param
.param (param), // param.param
.reconfig (reconfig), // reconfig.reconfig
.reset_timer (reset_timer), // reset_timer.reset_timer
.clock (clock), // clock.clk
.reset (reset), // reset.reset
.busy (busy), // busy.busy
.data_out (data_out), // data_out.data_out
.read_source (read_source), // read_source.read_source
.write_param (write_param), // write_param.write_param
.data_in (data_in), // data_in.data_in
.ctl_nupdt (1'b0) // (terminated)
);
endmodule
|
module issue_flow_control
(/*AUTOARG*/
// Outputs
wave_valid_entries,
// Inputs
clk, rst, tracemon_barrier_retire_en, valid_entry_out,
tracemon_barrier_retire_wf_bitmap, f_decode_wfid,
f_salu_branch_wfid, alu_wfid, f_decode_valid, f_decode_waitcnt,
f_salu_branch_en, alu_valid, alu_branch
);
input clk,rst;
input tracemon_barrier_retire_en;
input [`WF_PER_CU-1:0] valid_entry_out;
input [`WF_PER_CU-1:0] tracemon_barrier_retire_wf_bitmap;
input [`WF_ID_LENGTH-1:0] f_decode_wfid, f_salu_branch_wfid,
alu_wfid;
input f_decode_valid, f_decode_waitcnt,
f_salu_branch_en,
alu_valid, alu_branch;
wire [`WF_PER_CU-1:0] flopped_valid_entry_out;
wire [`WF_PER_CU-1:0] valid_barrier_retire_wf_bitmap;
wire [`WF_PER_CU-1:0] decoded_decode_waitcnt, decoded_branch_retired;
wire [`WF_PER_CU-1:0] decoded_branch_issued, flopped_decoded_branch_issued;
output [`WF_PER_CU-1:0] wave_valid_entries;
decoder_6b_40b_en branch_issue
(
.addr_in(alu_wfid),
.out(decoded_branch_issued),
.en(alu_valid & alu_branch)
);
decoder_6b_40b_en branch_retire
(
.addr_in(f_salu_branch_wfid),
.out(decoded_branch_retired),
.en(f_salu_branch_en)
);
decoder_6b_40b_en wait_cnt_decoder
(
.addr_in(f_decode_wfid),
.out(decoded_decode_waitcnt),
.en(f_decode_valid & f_decode_waitcnt)
);
dff valid_entry_out_flop[`WF_PER_CU-1:0]
(
.q(flopped_valid_entry_out),
.d(valid_entry_out),
.clk(clk),
.rst(rst)
);
dff branch_issued_flop[`WF_PER_CU-1:0]
(
.q(flopped_decoded_branch_issued),
.d(decoded_branch_issued),
.clk(clk),
.rst(rst)
);
assign valid_barrier_retire_wf_bitmap
= ( tracemon_barrier_retire_en )? tracemon_barrier_retire_wf_bitmap :
{`WF_PER_CU{1'b0}};
// Ask for new instructions when valid goes down (instruction is issued) or when
// a barrier or a branch of a waitcnt retire.
// Do not ask for new instructions when a branch was issued last cycle
assign wave_valid_entries
= ( ( (valid_entry_out ^ flopped_valid_entry_out) & flopped_valid_entry_out ) |
valid_barrier_retire_wf_bitmap | decoded_decode_waitcnt | decoded_branch_retired ) &
~flopped_decoded_branch_issued;
endmodule
|
/*
File: emesh_split.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Splitter
########################################################################
This block takes one eMesh input (104-bit transactions) and
copies it to two outputs. The wait signals are taken only from the
first slave port.
This block will hopefully be removed once I figure out how to get
Vivado to allow multiple slaves on one interface!
*/
module emesh_split (/*AUTOARG*/
// Outputs
ems_rd_wait, ems_wr_wait, emm0_access, emm0_write, emm0_datamode,
emm0_ctrlmode, emm0_dstaddr, emm0_srcaddr, emm0_data, emm1_access,
emm1_write, emm1_datamode, emm1_ctrlmode, emm1_dstaddr,
emm1_srcaddr, emm1_data,
// Inputs
ems_access, ems_write, ems_datamode, ems_ctrlmode, ems_dstaddr,
ems_srcaddr, ems_data, emm0_rd_wait, emm0_wr_wait
);
// Slave port
input ems_access;
input ems_write;
input [1:0] ems_datamode;
input [3:0] ems_ctrlmode;
input [31:0] ems_dstaddr;
input [31:0] ems_srcaddr;
input [31:0] ems_data;
output ems_rd_wait;
output ems_wr_wait;
// Master port #0 (with wait inputs)
output emm0_access;
output emm0_write;
output [1:0] emm0_datamode;
output [3:0] emm0_ctrlmode;
output [31:0] emm0_dstaddr;
output [31:0] emm0_srcaddr;
output [31:0] emm0_data;
input emm0_rd_wait;
input emm0_wr_wait;
// Master port #1 (NO wait inputs)
output emm1_access;
output emm1_write;
output [1:0] emm1_datamode;
output [3:0] emm1_ctrlmode;
output [31:0] emm1_dstaddr;
output [31:0] emm1_srcaddr;
output [31:0] emm1_data;
//############
//# Duplicate all slave->master signals
//############
wire emm0_access = ems_access;
wire emm0_write = ems_write;
wire [1:0] emm0_datamode = ems_datamode;
wire [3:0] emm0_ctrlmode = ems_ctrlmode;
wire [31:0] emm0_dstaddr = ems_dstaddr;
wire [31:0] emm0_srcaddr = ems_srcaddr;
wire [31:0] emm0_data = ems_data;
// Master port #1 (NO wait inputs)
wire emm1_access = ems_access;
wire emm1_write = ems_write;
wire [1:0] emm1_datamode = ems_datamode;
wire [3:0] emm1_ctrlmode = ems_ctrlmode;
wire [31:0] emm1_dstaddr = ems_dstaddr;
wire [31:0] emm1_srcaddr = ems_srcaddr;
wire [31:0] emm1_data = ems_data;
//#############################
//# Wait signal passthroughs, port 0 only
//#############################
wire ems_rd_wait = emm0_rd_wait;
wire ems_wr_wait = emm0_wr_wait;
endmodule // emesh_split
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_SYMBOL_V
`define SKY130_FD_SC_HD__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_SYMBOL_V
|
/*
I seem to have found a problem with the $monitor task/events.
(this is probably related to bug 399)
The problem only seems to arise in vvp mode and not in vvm.
Problem: $monitor seems to lose both the first and last time steps.
A complete copy of the run follows with source appended at the end.
(The correct output from vvm is shown in the last run)
This file compiles and produces the problem.
[email protected]
*/
/*
bubba> uname -a
Linux bubba 2.2.15-4mdk #1 Wed May 10 15:31:30 CEST 2000 i686 unknown
bubba> iverilog -V
Icarus Verilog version 0.6
Copyright 1998-2002 Stephen Williams
$Name: $
bubba> iverilog -Wall -tvvp stim.v
bubba> a.out
Time = 1 a = 1
bubba> iverilog -Wall -tvvm stim.v
bubba> a.out
Time = 0 a = 0
Time = 1 a = 1
Time = 2 a = 0
*/
// -------------------------------------------------------------------------stim
module stim;
reg a;
initial begin
a = 0;
#1 a = 1;
#1 a = 0;
end
initial begin
$monitor("Time = %0d a = %b", $time, a);
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
// DE0_Nano_SOPC_mm_interconnect_1.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2015.06.30.18:36:28
`timescale 1 ps / 1 ps
module DE0_Nano_SOPC_mm_interconnect_1 (
input wire altpll_sys_c2_clk, // altpll_sys_c2.clk
input wire clock_crossing_io_m0_reset_reset_bridge_in_reset_reset, // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
input wire [6:0] clock_crossing_io_m0_address, // clock_crossing_io_m0.address
output wire clock_crossing_io_m0_waitrequest, // .waitrequest
input wire [0:0] clock_crossing_io_m0_burstcount, // .burstcount
input wire [3:0] clock_crossing_io_m0_byteenable, // .byteenable
input wire clock_crossing_io_m0_read, // .read
output wire [31:0] clock_crossing_io_m0_readdata, // .readdata
output wire clock_crossing_io_m0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_m0_write, // .write
input wire [31:0] clock_crossing_io_m0_writedata, // .writedata
input wire clock_crossing_io_m0_debugaccess, // .debugaccess
output wire [1:0] g_sensor_int_s1_address, // g_sensor_int_s1.address
output wire g_sensor_int_s1_write, // .write
input wire [31:0] g_sensor_int_s1_readdata, // .readdata
output wire [31:0] g_sensor_int_s1_writedata, // .writedata
output wire g_sensor_int_s1_chipselect, // .chipselect
output wire [1:0] key_s1_address, // key_s1.address
output wire key_s1_write, // .write
input wire [31:0] key_s1_readdata, // .readdata
output wire [31:0] key_s1_writedata, // .writedata
output wire key_s1_chipselect, // .chipselect
output wire [1:0] led_s1_address, // led_s1.address
output wire led_s1_write, // .write
input wire [31:0] led_s1_readdata, // .readdata
output wire [31:0] led_s1_writedata, // .writedata
output wire led_s1_chipselect, // .chipselect
output wire [1:0] select_i2c_clk_s1_address, // select_i2c_clk_s1.address
output wire select_i2c_clk_s1_write, // .write
input wire [31:0] select_i2c_clk_s1_readdata, // .readdata
output wire [31:0] select_i2c_clk_s1_writedata, // .writedata
output wire select_i2c_clk_s1_chipselect, // .chipselect
output wire [1:0] sw_s1_address, // sw_s1.address
output wire sw_s1_write, // .write
input wire [31:0] sw_s1_readdata, // .readdata
output wire [31:0] sw_s1_writedata, // .writedata
output wire sw_s1_chipselect, // .chipselect
output wire [0:0] sysid_control_slave_address, // sysid_control_slave.address
input wire [31:0] sysid_control_slave_readdata // .readdata
);
wire clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> clock_crossing_io_m0_translator:uav_waitrequest
wire [2:0] clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount; // clock_crossing_io_m0_translator:uav_burstcount -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] clock_crossing_io_m0_translator_avalon_universal_master_0_writedata; // clock_crossing_io_m0_translator:uav_writedata -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_writedata
wire [6:0] clock_crossing_io_m0_translator_avalon_universal_master_0_address; // clock_crossing_io_m0_translator:uav_address -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_address
wire clock_crossing_io_m0_translator_avalon_universal_master_0_lock; // clock_crossing_io_m0_translator:uav_lock -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_lock
wire clock_crossing_io_m0_translator_avalon_universal_master_0_write; // clock_crossing_io_m0_translator:uav_write -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_write
wire clock_crossing_io_m0_translator_avalon_universal_master_0_read; // clock_crossing_io_m0_translator:uav_read -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_read
wire [31:0] clock_crossing_io_m0_translator_avalon_universal_master_0_readdata; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_readdata -> clock_crossing_io_m0_translator:uav_readdata
wire clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess; // clock_crossing_io_m0_translator:uav_debugaccess -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable; // clock_crossing_io_m0_translator:uav_byteenable -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_byteenable
wire clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> clock_crossing_io_m0_translator:uav_readdatavalid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
wire [6:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_control_slave_translator:uav_address
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_control_slave_translator:uav_write
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_control_slave_translator:uav_lock
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_control_slave_translator:uav_read
wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
wire [3:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire key_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // key_s1_translator:uav_waitrequest -> key_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] key_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // key_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> key_s1_translator:uav_burstcount
wire [31:0] key_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // key_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> key_s1_translator:uav_writedata
wire [6:0] key_s1_translator_avalon_universal_slave_0_agent_m0_address; // key_s1_translator_avalon_universal_slave_0_agent:m0_address -> key_s1_translator:uav_address
wire key_s1_translator_avalon_universal_slave_0_agent_m0_write; // key_s1_translator_avalon_universal_slave_0_agent:m0_write -> key_s1_translator:uav_write
wire key_s1_translator_avalon_universal_slave_0_agent_m0_lock; // key_s1_translator_avalon_universal_slave_0_agent:m0_lock -> key_s1_translator:uav_lock
wire key_s1_translator_avalon_universal_slave_0_agent_m0_read; // key_s1_translator_avalon_universal_slave_0_agent:m0_read -> key_s1_translator:uav_read
wire [31:0] key_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // key_s1_translator:uav_readdata -> key_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire key_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // key_s1_translator:uav_readdatavalid -> key_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire key_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // key_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> key_s1_translator:uav_debugaccess
wire [3:0] key_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // key_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> key_s1_translator:uav_byteenable
wire key_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // key_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire key_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // key_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire key_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // key_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] key_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // key_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire key_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> key_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> key_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> key_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> key_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> key_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // key_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> key_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> key_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> key_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> key_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> key_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_ready; // key_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
wire led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // led_s1_translator:uav_waitrequest -> led_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // led_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> led_s1_translator:uav_burstcount
wire [31:0] led_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // led_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> led_s1_translator:uav_writedata
wire [6:0] led_s1_translator_avalon_universal_slave_0_agent_m0_address; // led_s1_translator_avalon_universal_slave_0_agent:m0_address -> led_s1_translator:uav_address
wire led_s1_translator_avalon_universal_slave_0_agent_m0_write; // led_s1_translator_avalon_universal_slave_0_agent:m0_write -> led_s1_translator:uav_write
wire led_s1_translator_avalon_universal_slave_0_agent_m0_lock; // led_s1_translator_avalon_universal_slave_0_agent:m0_lock -> led_s1_translator:uav_lock
wire led_s1_translator_avalon_universal_slave_0_agent_m0_read; // led_s1_translator_avalon_universal_slave_0_agent:m0_read -> led_s1_translator:uav_read
wire [31:0] led_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // led_s1_translator:uav_readdata -> led_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // led_s1_translator:uav_readdatavalid -> led_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // led_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> led_s1_translator:uav_debugaccess
wire [3:0] led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // led_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> led_s1_translator:uav_byteenable
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // led_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // led_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // led_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] led_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // led_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> led_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> led_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> led_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> led_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> led_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // led_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cmd_xbar_mux_002_src_endofpacket; // cmd_xbar_mux_002:src_endofpacket -> led_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_002_src_valid; // cmd_xbar_mux_002:src_valid -> led_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_002_src_startofpacket; // cmd_xbar_mux_002:src_startofpacket -> led_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] cmd_xbar_mux_002_src_data; // cmd_xbar_mux_002:src_data -> led_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_002_src_channel; // cmd_xbar_mux_002:src_channel -> led_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_002_src_ready; // led_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready
wire sw_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sw_s1_translator:uav_waitrequest -> sw_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sw_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sw_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sw_s1_translator:uav_burstcount
wire [31:0] sw_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sw_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sw_s1_translator:uav_writedata
wire [6:0] sw_s1_translator_avalon_universal_slave_0_agent_m0_address; // sw_s1_translator_avalon_universal_slave_0_agent:m0_address -> sw_s1_translator:uav_address
wire sw_s1_translator_avalon_universal_slave_0_agent_m0_write; // sw_s1_translator_avalon_universal_slave_0_agent:m0_write -> sw_s1_translator:uav_write
wire sw_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sw_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sw_s1_translator:uav_lock
wire sw_s1_translator_avalon_universal_slave_0_agent_m0_read; // sw_s1_translator_avalon_universal_slave_0_agent:m0_read -> sw_s1_translator:uav_read
wire [31:0] sw_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sw_s1_translator:uav_readdata -> sw_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sw_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sw_s1_translator:uav_readdatavalid -> sw_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sw_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sw_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sw_s1_translator:uav_debugaccess
wire [3:0] sw_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sw_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sw_s1_translator:uav_byteenable
wire sw_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sw_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sw_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sw_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sw_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sw_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] sw_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sw_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sw_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sw_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> sw_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> sw_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> sw_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> sw_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> sw_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_003_src_ready; // sw_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // g_sensor_int_s1_translator:uav_waitrequest -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> g_sensor_int_s1_translator:uav_burstcount
wire [31:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> g_sensor_int_s1_translator:uav_writedata
wire [6:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_address; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_address -> g_sensor_int_s1_translator:uav_address
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_write; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_write -> g_sensor_int_s1_translator:uav_write
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_lock; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_lock -> g_sensor_int_s1_translator:uav_lock
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_read; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_read -> g_sensor_int_s1_translator:uav_read
wire [31:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // g_sensor_int_s1_translator:uav_readdata -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // g_sensor_int_s1_translator:uav_readdatavalid -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> g_sensor_int_s1_translator:uav_debugaccess
wire [3:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> g_sensor_int_s1_translator:uav_byteenable
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cmd_xbar_mux_004_src_endofpacket; // cmd_xbar_mux_004:src_endofpacket -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_004_src_valid; // cmd_xbar_mux_004:src_valid -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_004_src_startofpacket; // cmd_xbar_mux_004:src_startofpacket -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] cmd_xbar_mux_004_src_data; // cmd_xbar_mux_004:src_data -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_004_src_channel; // cmd_xbar_mux_004:src_channel -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_004_src_ready; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_004:src_ready
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // select_i2c_clk_s1_translator:uav_waitrequest -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> select_i2c_clk_s1_translator:uav_burstcount
wire [31:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> select_i2c_clk_s1_translator:uav_writedata
wire [6:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_address; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_address -> select_i2c_clk_s1_translator:uav_address
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_write; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_write -> select_i2c_clk_s1_translator:uav_write
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_lock; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_lock -> select_i2c_clk_s1_translator:uav_lock
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_read; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_read -> select_i2c_clk_s1_translator:uav_read
wire [31:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // select_i2c_clk_s1_translator:uav_readdata -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // select_i2c_clk_s1_translator:uav_readdatavalid -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> select_i2c_clk_s1_translator:uav_debugaccess
wire [3:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> select_i2c_clk_s1_translator:uav_byteenable
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cmd_xbar_mux_005_src_endofpacket; // cmd_xbar_mux_005:src_endofpacket -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_005_src_valid; // cmd_xbar_mux_005:src_valid -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_005_src_startofpacket; // cmd_xbar_mux_005:src_startofpacket -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] cmd_xbar_mux_005_src_data; // cmd_xbar_mux_005:src_data -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_005_src_channel; // cmd_xbar_mux_005:src_channel -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_005_src_ready; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_005:src_ready
wire clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_endofpacket; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_valid; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_startofpacket; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [80:0] clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_data; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:cp_ready
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [80:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [80:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [5:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire key_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // key_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire key_s1_translator_avalon_universal_slave_0_agent_rp_valid; // key_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire key_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // key_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [80:0] key_s1_translator_avalon_universal_slave_0_agent_rp_data; // key_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire key_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> key_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [80:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [5:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // led_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire led_s1_translator_avalon_universal_slave_0_agent_rp_valid; // led_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // led_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [80:0] led_s1_translator_avalon_universal_slave_0_agent_rp_data; // led_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire led_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> led_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [80:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [5:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire sw_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sw_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sw_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sw_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sw_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sw_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [80:0] sw_s1_translator_avalon_universal_slave_0_agent_rp_data; // sw_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sw_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sw_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [80:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [5:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_valid; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [80:0] g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_data; // g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> g_sensor_int_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [80:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [5:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_valid; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [80:0] select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_data; // select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> select_i2c_clk_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [80:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [5:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [80:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [5:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [80:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [5:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [80:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [5:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [80:0] limiter_rsp_src_data; // limiter:rsp_src_data -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> clock_crossing_io_m0_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // clock_crossing_io_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [80:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [5:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [80:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [5:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
wire [80:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
wire [5:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
wire cmd_xbar_demux_src2_ready; // cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [80:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [5:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_src4_endofpacket; // cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
wire cmd_xbar_demux_src4_valid; // cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
wire cmd_xbar_demux_src4_startofpacket; // cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
wire [80:0] cmd_xbar_demux_src4_data; // cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
wire [5:0] cmd_xbar_demux_src4_channel; // cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
wire cmd_xbar_demux_src4_ready; // cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
wire cmd_xbar_demux_src5_endofpacket; // cmd_xbar_demux:src5_endofpacket -> cmd_xbar_mux_005:sink0_endofpacket
wire cmd_xbar_demux_src5_valid; // cmd_xbar_demux:src5_valid -> cmd_xbar_mux_005:sink0_valid
wire cmd_xbar_demux_src5_startofpacket; // cmd_xbar_demux:src5_startofpacket -> cmd_xbar_mux_005:sink0_startofpacket
wire [80:0] cmd_xbar_demux_src5_data; // cmd_xbar_demux:src5_data -> cmd_xbar_mux_005:sink0_data
wire [5:0] cmd_xbar_demux_src5_channel; // cmd_xbar_demux:src5_channel -> cmd_xbar_mux_005:sink0_channel
wire cmd_xbar_demux_src5_ready; // cmd_xbar_mux_005:sink0_ready -> cmd_xbar_demux:src5_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [80:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [5:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [80:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [5:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [80:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [5:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [80:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [5:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
wire [80:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
wire [5:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
wire [80:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
wire [5:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire [5:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (7),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) clock_crossing_io_m0_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_crossing_io_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_crossing_io_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_crossing_io_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_crossing_io_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_m0_address), // avalon_anti_master_0.address
.av_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.av_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.av_read (clock_crossing_io_m0_read), // .read
.av_readdata (clock_crossing_io_m0_readdata), // .readdata
.av_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.av_write (clock_crossing_io_m0_write), // .write
.av_writedata (clock_crossing_io_m0_writedata), // .writedata
.av_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_control_slave_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) key_s1_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (key_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (key_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (key_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (key_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (key_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (key_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (key_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (key_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (key_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (key_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (key_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (key_s1_address), // avalon_anti_slave_0.address
.av_write (key_s1_write), // .write
.av_readdata (key_s1_readdata), // .readdata
.av_writedata (key_s1_writedata), // .writedata
.av_chipselect (key_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_s1_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (led_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (led_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (led_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (led_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (led_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (led_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (led_s1_address), // avalon_anti_slave_0.address
.av_write (led_s1_write), // .write
.av_readdata (led_s1_readdata), // .readdata
.av_writedata (led_s1_writedata), // .writedata
.av_chipselect (led_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_s1_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sw_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sw_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sw_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sw_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sw_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sw_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sw_s1_address), // avalon_anti_slave_0.address
.av_write (sw_s1_write), // .write
.av_readdata (sw_s1_readdata), // .readdata
.av_writedata (sw_s1_writedata), // .writedata
.av_chipselect (sw_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) g_sensor_int_s1_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (g_sensor_int_s1_address), // avalon_anti_slave_0.address
.av_write (g_sensor_int_s1_write), // .write
.av_readdata (g_sensor_int_s1_readdata), // .readdata
.av_writedata (g_sensor_int_s1_writedata), // .writedata
.av_chipselect (g_sensor_int_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (7),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) select_i2c_clk_s1_translator (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (select_i2c_clk_s1_address), // avalon_anti_slave_0.address
.av_write (select_i2c_clk_s1_write), // .write
.av_readdata (select_i2c_clk_s1_readdata), // .readdata
.av_writedata (select_i2c_clk_s1_writedata), // .writedata
.av_chipselect (select_i2c_clk_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_BEGIN_BURST (60),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_BURST_TYPE_H (57),
.PKT_BURST_TYPE_L (56),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_TRANS_EXCLUSIVE (48),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_THREAD_ID_H (68),
.PKT_THREAD_ID_L (68),
.PKT_CACHE_H (75),
.PKT_CACHE_L (72),
.PKT_DATA_SIDEBAND_H (59),
.PKT_DATA_SIDEBAND_L (59),
.PKT_QOS_H (61),
.PKT_QOS_L (61),
.PKT_ADDR_SIDEBAND_H (58),
.PKT_ADDR_SIDEBAND_L (58),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_DATA_W (81),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clock_crossing_io_m0_translator_avalon_universal_master_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (clock_crossing_io_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (clock_crossing_io_m0_translator_avalon_universal_master_0_write), // .write
.av_read (clock_crossing_io_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (clock_crossing_io_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (clock_crossing_io_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (clock_crossing_io_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (60),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_control_slave_translator_avalon_universal_slave_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (60),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) key_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (key_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (key_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (key_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (key_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (key_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (key_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (key_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (key_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (key_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (key_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (key_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (key_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (key_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (key_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (key_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (key_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_001_src_valid), // .valid
.cp_data (cmd_xbar_mux_001_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_001_src_channel), // .channel
.rf_sink_ready (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (key_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (key_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (key_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (key_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (key_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (key_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (key_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (key_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (key_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (key_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (60),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) led_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (led_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (led_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (led_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (led_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (led_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_002_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_002_src_valid), // .valid
.cp_data (cmd_xbar_mux_002_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_002_src_channel), // .channel
.rf_sink_ready (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (60),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sw_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sw_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sw_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sw_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sw_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sw_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_003_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_003_src_valid), // .valid
.cp_data (cmd_xbar_mux_003_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_003_src_channel), // .channel
.rf_sink_ready (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (60),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) g_sensor_int_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_004_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_004_src_valid), // .valid
.cp_data (cmd_xbar_mux_004_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_004_src_channel), // .channel
.rf_sink_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (60),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (42),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_BURSTWRAP_H (52),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (71),
.PKT_PROTECTION_L (69),
.PKT_RESPONSE_STATUS_H (77),
.PKT_RESPONSE_STATUS_L (76),
.PKT_BURST_SIZE_H (55),
.PKT_BURST_SIZE_L (53),
.PKT_ORI_BURST_SIZE_L (78),
.PKT_ORI_BURST_SIZE_H (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) select_i2c_clk_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_005_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_005_src_valid), // .valid
.cp_data (cmd_xbar_mux_005_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_005_src_channel), // .channel
.rf_sink_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
DE0_Nano_SOPC_mm_interconnect_1_addr_router addr_router (
.sink_ready (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (clock_crossing_io_m0_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_id_router id_router (
.sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_id_router id_router_001 (
.sink_ready (key_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (key_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (key_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (key_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (key_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_id_router id_router_002 (
.sink_ready (led_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (led_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (led_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_id_router id_router_003 (
.sink_ready (sw_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sw_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sw_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_id_router id_router_004 (
.sink_ready (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (g_sensor_int_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_id_router id_router_005 (
.sink_ready (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (select_i2c_clk_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (67),
.PKT_DEST_ID_L (65),
.PKT_SRC_ID_H (64),
.PKT_SRC_ID_L (62),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (81),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_demux cmd_xbar_demux (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_src4_valid), // .valid
.src4_data (cmd_xbar_demux_src4_data), // .data
.src4_channel (cmd_xbar_demux_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_src5_valid), // .valid
.src5_data (cmd_xbar_demux_src5_data), // .data
.src5_channel (cmd_xbar_demux_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_src5_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_002 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_002_src_ready), // src.ready
.src_valid (cmd_xbar_mux_002_src_valid), // .valid
.src_data (cmd_xbar_mux_002_src_data), // .data
.src_channel (cmd_xbar_mux_002_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src2_valid), // .valid
.sink0_channel (cmd_xbar_demux_src2_channel), // .channel
.sink0_data (cmd_xbar_demux_src2_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src2_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_003 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_004 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_004_src_ready), // src.ready
.src_valid (cmd_xbar_mux_004_src_valid), // .valid
.src_data (cmd_xbar_mux_004_src_data), // .data
.src_channel (cmd_xbar_mux_004_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src4_valid), // .valid
.sink0_channel (cmd_xbar_demux_src4_channel), // .channel
.sink0_data (cmd_xbar_demux_src4_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src4_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_005 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_005_src_ready), // src.ready
.src_valid (cmd_xbar_mux_005_src_valid), // .valid
.src_data (cmd_xbar_mux_005_src_data), // .data
.src_channel (cmd_xbar_mux_005_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src5_valid), // .valid
.sink0_channel (cmd_xbar_demux_src5_channel), // .channel
.sink0_data (cmd_xbar_demux_src5_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src5_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_002 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_003 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_004 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_005 (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
DE0_Nano_SOPC_mm_interconnect_1_rsp_xbar_mux rsp_xbar_mux (
.clk (altpll_sys_c2_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "usb_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
`timescale 1ns / 1ps
module mult
#(
parameter N=128,
parameter CC=1
)
(
clk,
rst,
g_input,
e_input,
o
);
input clk;
input rst;
input [N-1:0] g_input;
input [N-1:0] e_input;
output [N-1:0] o;
// input [N/CC-1:0] e_input;
// output [2*N-1:0] o;
// reg [2*N-1:0] sreg;
// wire [2*N-1:0] swire;
// wire [N+N/CC-1:0] clocal;
// assign clocal = g_input*e_input;
wire [2*N-1:0] o_large;
assign o = o_large[N-1:0];
MULT
#(
.N(N),
.M(N/CC)
) u_MULT (
.A(g_input),
.B(e_input),
.O(o_large)
);
// generate
// if(CC>1) begin:g1
// assign swire = sreg + {clocal,{(N-N/CC){1'b0}}};
// end
// endgenerate
// generate
// if(CC>1) begin:g2
// always@(posedge clk or posedge rst) begin
// if(rst) begin
// sreg <= 'b0;
// end else begin
// sreg <= {{N/CC{1'b0}},swire[2*N-1:N/CC]};
// end
// end
// end
// endgenerate
// generate
// if(CC>1) begin :g3
// assign o = swire;
// end else begin :g4
// assign o = clocal;
// end
// endgenerate
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
input ena_i;
input dbg_i;
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
input [15:0] pulse_num_i;
output [15:0] rx_i_o;
output [15:0] rx_q_o;
output reg rx_strobe_o;
reg [15:0] count;
always @(posedge clk_i)
if (rst_i | ~ena_i)
count <= 16'b0;
else
count <= count + 16'b1;
wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i};
// Buffer incoming samples every clock
wire [31:0] fifo_out;
reg fifo_ack;
wire fifo_empty;
// Use model if simulating, otherwise Altera Megacell
`ifdef SIMULATION
fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`else
fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`endif
// Write samples to rx_fifo every third clock
`define ST_FIFO_IDLE 3'b001
`define ST_FIFO_STROBE 3'b010
`define ST_FIFO_ACK 3'b100
reg [2:0] state;
always @(posedge clk_i)
if (rst_i)
begin
state <= `ST_FIFO_IDLE;
rx_strobe_o <= 1'b0;
fifo_ack <= 1'b0;
end
else
case (state)
`ST_FIFO_IDLE:
if (!fifo_empty)
begin
// Tell rx_fifo sample is ready
rx_strobe_o <= 1'b1;
state <= `ST_FIFO_STROBE;
end
`ST_FIFO_STROBE:
begin
rx_strobe_o <= 1'b0;
// Ack our FIFO
fifo_ack <= 1'b1;
state <= `ST_FIFO_ACK;
end
`ST_FIFO_ACK:
begin
fifo_ack <= 1'b0;
state <= `ST_FIFO_IDLE;
end
endcase // case(state)
assign rx_i_o = fifo_out[31:16];
assign rx_q_o = fifo_out[15:0];
endmodule // radar_rx
|
//////////////////////////////////////////////////////////////////////
//// ////
//// serialInterface.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Perform all serial to parallel, and parallel
//// to serial conversions. Perform device address matching
//// Handle arbitrary length I2C reads terminated by NAK
//// from host, and arbitrary length I2C writes terminated
//// by STOP from host
//// The second byte of a I2C write is always interpreted
//// as a register address, and becomes the base register address
//// for all read and write transactions.
//// I2C WRITE: devAddr, regAddr, data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// I2C READ: data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// Note that when regAddR reaches 255 it will automatically wrap round to 0
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "i2cSlave_define.v"
module serialInterface (clearStartStopDet, clk, dataIn, dataOut, regAddr, rst, scl, sdaIn, sdaOut, startStopDetState, writeEn, i2c_address);
input [7:1]i2c_address;
input clk;
input [7:0]dataIn;
input rst;
input scl;
input sdaIn;
input [1:0]startStopDetState;
output clearStartStopDet;
output [7:0]dataOut;
output [7:0]regAddr;
output sdaOut;
output writeEn;
reg clearStartStopDet, next_clearStartStopDet;
wire clk;
wire [7:0]dataIn;
reg [7:0]dataOut, next_dataOut;
reg [7:0]regAddr, next_regAddr;
wire rst;
wire scl;
wire sdaIn;
reg sdaOut, next_sdaOut;
wire [1:0]startStopDetState;
reg writeEn, next_writeEn;
// diagram signals declarations
reg [2:0]bitCnt, next_bitCnt;
reg [7:0]rxData, next_rxData;
reg [1:0]streamSt, next_streamSt;
reg [7:0]txData, next_txData;
// BINARY ENCODED state machine: SISt
// State codes definitions:
`define START 4'b0000
`define CHK_RD_WR 4'b0001
`define READ_RD_LOOP 4'b0010
`define READ_WT_HI 4'b0011
`define READ_CHK_LOOP_FIN 4'b0100
`define READ_WT_LO 4'b0101
`define READ_WT_ACK 4'b0110
`define WRITE_WT_LO 4'b0111
`define WRITE_WT_HI 4'b1000
`define WRITE_CHK_LOOP_FIN 4'b1001
`define WRITE_LOOP_WT_LO 4'b1010
`define WRITE_ST_LOOP 4'b1011
`define WRITE_WT_LO2 4'b1100
`define WRITE_WT_HI2 4'b1101
`define WRITE_CLR_WR 4'b1110
`define WRITE_CLR_ST_STOP 4'b1111
reg [3:0]CurrState_SISt, NextState_SISt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: SISt
// NextState logic (combinatorial)
always @ (startStopDetState or streamSt or scl or txData or bitCnt or rxData or sdaIn or regAddr or dataIn or sdaOut or writeEn or dataOut or clearStartStopDet or CurrState_SISt)
begin
NextState_SISt <= CurrState_SISt;
// Set default values for outputs and signals
next_streamSt <= streamSt;
next_txData <= txData;
next_rxData <= rxData;
next_sdaOut <= sdaOut;
next_writeEn <= writeEn;
next_dataOut <= dataOut;
next_bitCnt <= bitCnt;
next_clearStartStopDet <= clearStartStopDet;
next_regAddr <= regAddr;
case (CurrState_SISt) // synopsys parallel_case full_case
`START:
begin
next_streamSt <= `STREAM_IDLE;
next_txData <= 8'h00;
next_rxData <= 8'h00;
next_sdaOut <= 1'b1;
next_writeEn <= 1'b0;
next_dataOut <= 8'h00;
next_bitCnt <= 3'b000;
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
`CHK_RD_WR:
begin
if (streamSt == `STREAM_READ)
begin
NextState_SISt <= `READ_RD_LOOP;
next_txData <= dataIn;
next_regAddr <= regAddr + 1'b1;
next_bitCnt <= 3'b001;
end
else
begin
NextState_SISt <= `WRITE_WT_HI;
next_rxData <= 8'h00;
end
end
`READ_RD_LOOP:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_HI;
next_sdaOut <= txData [7];
next_txData <= {txData [6:0], 1'b0};
end
end
`READ_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `READ_CHK_LOOP_FIN;
end
end
`READ_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b000)
begin
NextState_SISt <= `READ_WT_LO;
end
else
begin
NextState_SISt <= `READ_RD_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`READ_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_ACK;
next_sdaOut <= 1'b1;
end
end
`READ_WT_ACK:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `CHK_RD_WR;
if (sdaIn == `I2C_NAK)
next_streamSt <= `STREAM_IDLE;
end
end
`WRITE_WT_LO:
begin
if ((scl == 1'b0) && (startStopDetState == `STOP_DET ||
(streamSt == `STREAM_IDLE && startStopDetState == `NULL_DET)))
begin
NextState_SISt <= `WRITE_CLR_ST_STOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
next_streamSt <= `STREAM_IDLE;
next_clearStartStopDet <= 1'b1;
end
else if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_ST_LOOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
end
end
`WRITE_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
next_bitCnt <= 3'b000;
end
end
`WRITE_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b111)
begin
NextState_SISt <= `WRITE_CLR_WR;
next_sdaOut <= `I2C_ACK;
case (streamSt)
`STREAM_IDLE: begin
if (rxData[7:1] == i2c_address &&
startStopDetState == `START_DET) begin
if (rxData[0] == 1'b1)
next_streamSt <= `STREAM_READ;
else
next_streamSt <= `STREAM_WRITE_ADDR;
end
else
next_sdaOut <= `I2C_NAK;
end
`STREAM_WRITE_ADDR: begin
next_streamSt <= `STREAM_WRITE_DATA;
next_regAddr <= rxData;
end
`STREAM_WRITE_DATA: begin
next_dataOut <= rxData;
next_writeEn <= 1'b1;
end
default:
next_streamSt <= streamSt;
endcase
end
else
begin
NextState_SISt <= `WRITE_ST_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`WRITE_LOOP_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_CHK_LOOP_FIN;
end
end
`WRITE_ST_LOOP:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_LOOP_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
end
end
`WRITE_WT_LO2:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `CHK_RD_WR;
next_sdaOut <= 1'b1;
end
end
`WRITE_WT_HI2:
begin
next_clearStartStopDet <= 1'b0;
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO2;
end
end
`WRITE_CLR_WR:
begin
if (writeEn == 1'b1)
next_regAddr <= regAddr + 1'b1;
next_writeEn <= 1'b0;
next_clearStartStopDet <= 1'b1;
NextState_SISt <= `WRITE_WT_HI2;
end
`WRITE_CLR_ST_STOP:
begin
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_SISt <= `START;
else
CurrState_SISt <= NextState_SISt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
sdaOut <= 1'b1;
writeEn <= 1'b0;
dataOut <= 8'h00;
clearStartStopDet <= 1'b0;
// regAddr <= // Initialization in the reset state or default value required!!
streamSt <= `STREAM_IDLE;
txData <= 8'h00;
rxData <= 8'h00;
bitCnt <= 3'b000;
end
else
begin
sdaOut <= next_sdaOut;
writeEn <= next_writeEn;
dataOut <= next_dataOut;
clearStartStopDet <= next_clearStartStopDet;
regAddr <= next_regAddr;
streamSt <= next_streamSt;
txData <= next_txData;
rxData <= next_rxData;
bitCnt <= next_bitCnt;
end
end
endmodule
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith development but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Z.gt_lt || apply Z.lt_gt || apply Z.le_ge || apply Z.ge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some relations on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some relations on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Z.le_lt_trans with (m := x).
apply Z.ge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Z.ge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Z.ge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Z.lt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z.eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Z.ge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Z.succ in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Z.lt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Z.ge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Z.lt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Z.le_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Z.lt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Z.gt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Z.lt in H0.
unfold Z.lt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Z.lt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Z.opp_involutive (x * z)).
exact (Z.opp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Z.opp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Z.opp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Z.gt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Z.gt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Z.gt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Z.lt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Z.lt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Z.lt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Z.opp_involutive.
apply Z.opp_involutive.
apply Z.gt_lt.
apply Zlt_opp.
apply Z.gt_lt.
assumption.
simpl in |- *.
rewrite Z.opp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Z.lt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Z.lt_irrefl (a * x)).
apply Z.le_lt_trans with (m := (a * y)%Z).
assumption.
apply Z.gt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Z.gt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Z.gt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Z.lt_gt.
assumption.
apply Z.lt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Z.lt_irrefl (a * y)).
apply Z.le_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Z.lt_gt.
assumption.
apply Z.gt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Z.succ x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Z.succ x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Z.gt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Z.lt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Z.lt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Pos.pred (Pos.succ p) = Pos.pred (P_of_succ_nat (S x))).
intro.
rewrite Pos.pred_succ in H2.
simpl in H2.
rewrite Pos.pred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Pos.pred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Z.lt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Z.lt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Z.succ (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Z.lt_gt.
change (0 < Z.succ (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Z.abs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Z.abs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Z.abs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Z.opp H5).
apply Z.opp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Z.lt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Z.abs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Z.abs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Z.lt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Z.abs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Z.abs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Z.abs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Z.abs_nat x <= Z.abs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Z.abs_nat x < Z.abs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Z.abs_nat (x + y) = Z.abs_nat x + Z.abs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Z.abs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Z.abs_nat x) = Z.abs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Z.abs_nat x) with (Z.abs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Z.abs_nat at 2, nat_of_P, Pos.iter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Z.abs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Z.abs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Z.sgn x = 0%Z} + {Z.sgn x = 1%Z} + {Z.sgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Z.sgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Z.sgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Z.sgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Z.sgn a * Z.abs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Z.sgn in |- *.
unfold Z.abs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Z.sgn in |- *.
unfold Z.abs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Z.sgn a * x)%Z = (Z.sgn b * y)%Z -> (Z.sgn a * y)%Z = (Z.sgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Z.sgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Z.sgn in |- *.
intro.
apply False_ind.
apply H0.
apply Z.opp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Z.sgn at 1 in |- *.
unfold Z.sgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Z.sgn b * (Z.sgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Z.sgn at 1 in |- *.
unfold Z.sgn at 2 in |- *.
intro.
transitivity (Z.sgn b * (-1 * (Z.sgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Z.opp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Z.opp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Z.sgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Z.sgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Z.lt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Z.lt_irrefl (Zneg p)).
apply Z.lt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Z.sgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Z.sgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Z.lt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Z.lt_irrefl 0).
apply Z.lt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Z.sgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Z.sgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Z.sgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Z.sgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Z.sgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Z.sgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Z.le_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Z.sgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Z.sgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Z.le_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Z.sgn (x * y) = (Z.sgn x * Z.sgn y)%Z.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Z.sgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Z.sgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Z.sgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Z.sgn x + Z.sgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Z.sgn x + Z.sgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Z.sgn x + Z.sgn y)%Z -> (0 <= x)%Z.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Z.sgn x + Z.sgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Z.sgn x + Z.sgn y)%Z -> (0 <= y)%Z.
Proof.
intros [|p1|p1] [|p2|p2]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Z.sgn x + Z.sgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [|p1|p1] [|p2|p2]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Z.sgn (- x) = (- Z.sgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Z.sgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Z.sgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Z.abs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Z.pred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Z.lt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Z.lt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Z.pred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Z.lt_gt.
apply Z.lt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Z.lt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Z.pred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Z.lt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Z.abs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Z.lt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Z.abs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Z.lt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Z.abs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Z.abs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Z.succ (- Z.succ p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Z.succ p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Z.succ in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Z.succ p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Z.abs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Z.abs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Z.abs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Z.lt_le_trans with (m := (- p)%Z).
apply Z.gt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Z.abs z = Z.abs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Z.abs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Z.abs z) with z.
assumption.
symmetry in |- *.
apply Z.abs_eq.
apply Zlt_le_weak.
apply Z.le_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Z.abs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Z.abs_eq.
apply Zlt_le_weak.
apply Z.le_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Z.abs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Z.le_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Z.le_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Z.le_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Z.abs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Z.le_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Z.abs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Z.opp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Z.abs (z * p) = (Z.abs z * Z.abs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Z.abs (z + p) <= Z.abs z + Z.abs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Z.le_refl.
case p.
intro.
simpl in |- *.
apply Z.le_refl.
intros.
simpl in |- *.
apply Z.le_refl.
intros.
unfold Z.abs at 2 in |- *.
unfold Z.abs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Z.le_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Z.le_refl.
intros.
unfold Z.abs at 2 in |- *.
unfold Z.abs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Z.le_refl.
intros.
simpl in |- *.
apply Z.le_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Z.abs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Z.abs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Z.succ in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Z.succ in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Z.opp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Z.ge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Z.succ in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Z.opp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Z.opp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Z.ge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Z.succ in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Z.opp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Z.succ q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Z.lt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Z.le_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Z.lt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Z.lt_gt.
elim H1.
intros.
unfold Z.succ in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Z.succ q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Z.lt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Z.le_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Z.lt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Z.lt_gt.
elim H1.
intros.
unfold Z.succ in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Z.min n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Z.min (n + 1) (m + 1)) with (Z.min n m + 1)%Z.
ring.
symmetry in |- *.
change (Z.min (Z.succ n) (Z.succ m) = Z.succ (Z.min n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Z.min n m)%Z).
ring_simplify (- n + Z.min n m + n)%Z.
ring_simplify (- n + Z.min n m + (n + m - Z.min n m))%Z.
apply Z.le_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Z.min n m)%Z).
ring_simplify (- m + Z.min n m + m)%Z.
ring_simplify (- m + Z.min n m + (n + m - Z.min n m))%Z.
apply Z.le_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Z.min n m = n} + {Z.min n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Z.min in |- *.
unfold Z.lt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Z.min in |- *.
unfold Z.gt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Z.lt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Z.ge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Z.ge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Z.ge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
Require Import NArith.
Require Import Bool.
Open Scope N.
(** This data types represents a number that is either negative (-1), zero (0) or
* positive.
* It is mostly used to represent the sign of differences (for example, the difference
* in the height of the two subtrees in an AVL tree).
*)
Inductive sign : Type :=
| negative : sign
| zero : sign
| positive : sign.
(** Get the opposite sign (maps negative to positive and positive to negative). *)
Definition sign_negate (a:sign) : sign :=
match a with
| negative => positive
| zero => zero
| positive => negative
end.
(** Two signs are either equal or not. *)
Definition sign_eq_dec (a b:sign) : {a = b} + {a <> b}.
Proof.
destruct a; destruct b; auto || (right; discriminate 1).
Defined.
Definition beq_sign (a b:sign) : bool :=
match (a,b) with
| (negative, negative) => true
| (zero, zero) => true
| (positive, positive) => true
| (_, _) => false
end.
(** Definition of an AVL tree. The invariant for this tree (defined later) is that
* the difference in height of the left and the right subtree is always between -1 and 1.
*)
Inductive avl_tree (T:Type) : Type :=
(** A branch consists of a balance, the left subtree, the key + value and the
* right subtree. The balance if [positive] if the left subtree's height is greater
* than the height of the right subtree. If the heights are the same, the balance is
* [zero], otherwise it will be [negative].
*)
| Avl_branch : sign -> avl_tree T -> N * T -> avl_tree T -> avl_tree T
| Avl_empty : avl_tree T.
Arguments Avl_branch [T] _ _ _ _.
Arguments Avl_empty [T].
(** Proposition that states that the given key/value pair is contained in the tree. *)
Fixpoint In {T:Type} (v:N * T) (t:avl_tree T) : Prop :=
match t with
| Avl_empty => False
| Avl_branch _ l v' r => v = v' \/ In v l \/ In v r
end.
(** A tree consisting only of a single element. *)
Definition avl_singleton {T:Type} (k:N) (v:T) : avl_tree T :=
Avl_branch zero Avl_empty (k,v) Avl_empty.
(** The empty tree doesn't contain any elements. *)
Theorem not_In_empty : forall (T:Type) (k:N) (v:T), ~In (k,v) Avl_empty.
Proof. intros. destruct 1. Qed.
Section Height.
Variable T : Type.
(** Calculate the height of an AVL tree. The height is maximal number of edges from
* the root to any leaf.
*)
Fixpoint avl_height (t:avl_tree T) : N :=
match t with
| Avl_empty => 0
| Avl_branch _ l _ r => N.succ (N.max (avl_height l) (avl_height r))
end.
Global Arguments avl_height : default implicits.
Example avl_height_ex_empty : avl_height Avl_empty = 0.
Proof. reflexivity. Qed.
Example avl_height_ex_1 :
forall a b c d : T,
avl_height
(Avl_branch
negative
(avl_singleton 1 a)
(2,b)
(Avl_branch
positive
(avl_singleton 3 c)
(4,d)
Avl_empty)) = 3.
Proof. reflexivity. Qed.
End Height.
Section Invariants.
Variable T : Type.
Fixpoint forall_keys (f:N -> Prop) (t:avl_tree T) : Prop :=
match t with
| Avl_empty => True
| Avl_branch _ l p r => f (fst p) /\ forall_keys f l /\ forall_keys f r
end.
Global Arguments forall_keys : default implicits.
Theorem all_keys_greater_chain :
forall (k k':N) (t:avl_tree T),
k' < k -> forall_keys (N.lt k) t -> forall_keys (N.lt k') t.
Proof.
Hint Resolve N.lt_trans.
intros k k' t ineq H.
induction t as [b l IHl [k'' v] r IHr|];
hnf in *;
intuition eauto.
Qed.
Theorem all_keys_smaller_chain :
forall (k k':N) (t:avl_tree T),
k < k' -> forall_keys (N.gt k) t -> forall_keys (N.gt k') t.
Proof.
Hint Resolve N.lt_trans.
intros k k' t ineq H.
induction t as [b l IHl [k'' v] r IHr|];
hnf in *;
rewrite_all N.gt_lt_iff;
intuition eauto.
Qed.
Theorem all_keys_greater_chain_eq :
forall (k k':N) (t:avl_tree T),
k' <= k -> forall_keys (N.lt k) t -> forall_keys (N.lt k') t.
Proof.
Hint Resolve N.le_lt_trans.
intros k k' t ineq H.
induction t as [b l IH [k'' v] r IHr|]; simpl in *; intuition eauto.
Qed.
Lemma invert_tuple_eq :
forall (A B:Type) (a a':A) (b b':B),
(a,b) = (a',b') <-> a = a' /\ b = b'.
Proof. split; inversion 1; subst; auto. Qed.
Theorem forall_keys_In_iff :
forall (P:N -> Prop) (t:avl_tree T),
forall_keys P t <-> (forall p, In p t -> P (fst p)).
Proof.
intros P t. induction t as [b l IHl p r IHr|].
- simpl. rewrite IHl. rewrite IHr. split; intuition (subst; eauto).
- split; simpl; intuition auto.
Qed.
Fixpoint binary_tree_invariant (t:avl_tree T) : Prop :=
match t with
| Avl_empty => True
| Avl_branch _ l p r =>
forall_keys (N.gt (fst p)) l /\ forall_keys (N.lt (fst p)) r /\
binary_tree_invariant l /\ binary_tree_invariant r
end.
Global Arguments binary_tree_invariant : default implicits.
Fixpoint avl_invariant (t:avl_tree T) : Prop :=
match t with
| Avl_empty => True
| Avl_branch _ l _ r =>
(avl_height l = avl_height r \/ avl_height l = N.succ (avl_height r) \/ N.succ (avl_height l) = avl_height r)
/\ avl_invariant l /\ avl_invariant r
end.
Global Arguments avl_invariant : default implicits.
Definition balanced_with (b:sign) (l r:avl_tree T) : Prop :=
match b with
| positive => avl_height l = N.succ (avl_height r)
| zero => avl_height l = avl_height r
| negative => N.succ (avl_height l) = avl_height r
end.
Fixpoint balance_correct (t:avl_tree T) : Prop :=
match t with
| Avl_empty => True
| Avl_branch b l _ r => balanced_with b l r /\ balance_correct l /\ balance_correct r
end.
Global Arguments balance_correct : default implicits.
Theorem balance_correct_implies_avl_invariant :
forall (t:avl_tree T), balance_correct t -> avl_invariant t.
Proof.
intros t H. induction t as [b l IHl p r IHr|].
- simpl in *. destruct b; simpl in *; tauto.
- auto.
Qed.
(** Combination of all invariants that an AVL tree has to satisfy. *)
Definition avl_tree_invariant (t:avl_tree T) : Prop :=
balance_correct t /\ binary_tree_invariant t.
Global Arguments avl_tree_invariant : default implicits.
Theorem In_inv_left :
forall (l r:avl_tree T) (k k':N) (v v':T),
forall_keys (N.lt k') r -> k < k' ->
((k,v) = (k',v') \/ In (k,v) l \/ In (k,v) r) ->
In (k,v) l.
Proof.
pose N.lt_irrefl as T1. pose N.lt_asymm as T2.
intros l r k k' v v' r_all_gt k_lt H.
destruct H as [H|[H|H]].
- inversion H. subst k'. absurd (k < k); auto.
- assumption.
- rewrite forall_keys_In_iff in r_all_gt. apply r_all_gt in H.
simpl in H. absurd (k < k'); auto.
Qed.
Theorem In_inv_right :
forall (l r:avl_tree T) (k k':N) (v v':T),
forall_keys (N.gt k') l -> k' < k ->
((k,v) = (k',v') \/ In (k,v) l \/ In (k,v) r) ->
In (k,v) r.
Proof.
pose N.gt_lt as T1. pose N.lt_irrefl as T2. pose N.lt_asymm as T3.
intros l r k k' v v' l_all_lt k_gt H. destruct H as [H|[H|H]].
- inversion H. subst k'. absurd (k < k); auto.
- rewrite forall_keys_In_iff in l_all_lt. apply l_all_lt in H.
simpl in *. absurd (k < k'); auto.
- assumption.
Qed.
Theorem In_inv_head :
forall (l r:avl_tree T) (k:N) (v v':T),
forall_keys (N.gt k) l /\ forall_keys (N.lt k) r ->
((k,v) = (k,v') \/ In (k,v) l \/ In (k,v) r) ->
v = v'.
Proof.
pose N.gt_lt as T1. pose N.lt_irrefl as T2. pose N.lt_asymm as T3.
intros l r k v v' [l_all_lt r_all_gt] H. destruct H as [H|[H|H]].
- inversion H. auto.
- rewrite forall_keys_In_iff in l_all_lt. apply l_all_lt in H.
absurd (k < k); auto.
- rewrite forall_keys_In_iff in r_all_gt. apply r_all_gt in H.
absurd (k < k); auto.
Qed.
End Invariants.
Section Node.
Variable T : Type.
(** Calculate the total balance change for this node from the height change
* of either the left or the right subtree.
* The returned balance change can be applied using [apply_balance_change].
*)
Let balance_change (a:sign + sign) : sign :=
match a with
| inl s => s
| inr s => sign_negate s
end.
(** Apply a balance change.
* Returns the new balance if we don't need to do a rotation.
* Otherwise, returns true if the left tree is higher or
false if the right tree is higher.
*)
Let apply_balance_change (c:sign) (b:sign) : bool + sign :=
match c with
| negative =>
match b with
| negative => inl false
| zero => inr negative
| positive => inr zero
end
| zero => inr b
| positive =>
match b with
| negative => inr zero
| zero => inr positive
| positive => inl true
end
end.
(** Return the height change of the subtree (discarding which subtree changed). *)
Let height_change (s:sign + sign) : sign := match s with | inr x => x | inl x => x end.
(** Rotation for when the right subtree is higher *)
Let rotate_right (removed:bool) (l:avl_tree T) (p:N * T) (r:avl_tree T)
: avl_tree T * sign :=
match r with
| Avl_branch positive (Avl_branch rlb rll rlp rlr) rp rr =>
( Avl_branch
zero
(Avl_branch (if beq_sign rlb negative then positive else zero) l p rll)
rlp
(Avl_branch (if beq_sign rlb positive then negative else zero) rlr rp rr)
, if removed then negative else zero
)
| Avl_branch b rl rp rr =>
let b' := if beq_sign b zero then positive else zero in
( Avl_branch
b'
(Avl_branch (sign_negate b') l p rl)
rp
rr
, if removed && beq_sign b negative then negative else zero
)
| Avl_empty =>
(* This branch should never happen, because if the right subtree has height zero,
* it cannot be higher than the left subtree.
* In this case, we still return the tree without doing a rotation, because that
* way the invariant of the tree is preserved, which makes the proofs simpler.
*)
let b := match l with
| Avl_empty => zero
| _ => positive
end
in (Avl_branch b l p r, zero)
end.
(** Rotation for when the left subtree is higher *)
Let rotate_left (removed:bool) (l:avl_tree T) (p:N * T) (r:avl_tree T)
: avl_tree T * sign :=
match l with
| Avl_branch negative ll lp (Avl_branch lrb lrl lrp lrr) =>
( Avl_branch
zero
(Avl_branch (if beq_sign lrb negative then positive else zero) ll lp lrl)
lrp
(Avl_branch (if beq_sign lrb positive then negative else zero) lrr p r)
, if removed then negative else zero
)
| Avl_branch b ll lp lr =>
let b' := if beq_sign zero b then negative else zero in
( Avl_branch
b'
ll
lp
(Avl_branch (sign_negate b') lr p r)
, if removed && beq_sign b positive then negative else zero
)
| Avl_empty =>
(* See comment for this branch in [rotate_right] *)
let b := match r with
| Avl_empty => zero
| _ => negative
end
in (Avl_branch b Avl_empty p r, zero)
end.
(* This function recreates a tree node after one of it's subtrees changed.
*
* Arguments:
*
* - [b] is the balance of the node before the change.
* - [s] is either [inl c] or [inr c], where [c : sign] is the change in the height
* of the left or right subtree respectively (the other subtree's height must stay
* the same). [c] is positive if the height increased by 1, zero if it stayed the
* same or negative if it decreased by 1.
* - [l] is the new left subtree.
* - [p] is the value at the node (should be the same as before the change)
* - [r] is the new right subtree
*
* Given these arguments, the function will compute the new balance and rebalance the
* tree if necessary. It returns the new tree and the height change for the whole
* new tree.
*)
Definition node (b:sign) (s:sign + sign) (l:avl_tree T) (p:N * T) (r:avl_tree T)
: avl_tree T * sign :=
if beq_sign (height_change s) zero
then
(* In this case, the subtree height did not change at all so the balance
* stays the same.
*)
(Avl_branch b l p r, zero)
else let hd := height_change s in
match apply_balance_change (balance_change s) b with
| inl true => rotate_left (beq_sign hd negative) l p r
| inl false => rotate_right (beq_sign hd negative) l p r
| inr b' =>
if beq_sign hd positive && beq_sign b' zero
then
(* The subtree height increased, but the balance is now zero. This means
* that the height of the smaller subtree must have increased (if not, the
* node would be unbalanced), so the height of the node did not change *)
(Avl_branch b' l p r, zero)
else
if beq_sign hd negative && negb (beq_sign b' zero)
then
(* The subtree height decreased, and the node's balance is not zero. This
* means that the balance was zero before, and because we only change
* one subtree, the height of the node cannot have changed if it is still
* balanced.
*)
(Avl_branch b' l p r, zero)
else
(* In all other cases, the change in the height of the node is the same
* as the subtree height change.
*)
(Avl_branch b' l p r, hd)
end.
Global Arguments node : default implicits.
(** Proof that [rotate_left] preserves the binary_tree_invariant *)
Lemma rotate_left_binary_tree_invariant :
forall (b:bool) (p:N * T) (l r:avl_tree T),
binary_tree_invariant l -> binary_tree_invariant r ->
forall_keys (N.gt (fst p)) l -> forall_keys (N.lt (fst p)) r ->
binary_tree_invariant (fst (rotate_left b l p r)).
Proof.
pose all_keys_smaller_chain as T1.
pose all_keys_greater_chain as T2.
intros b p l r bt_inv_l bt_inv_r l_smaller r_greater.
destruct l as [lb ll lp lr|].
- simpl. destruct lb; destruct lr as [lrb lrl lrp lrr|];
simpl in *;
rewrite_all N.gt_lt_iff;
intuition eauto.
- simpl. auto.
Qed.
(** Proof that [rotate_right] preserves the binary_tree_invariant *)
Lemma rotate_right_binary_tree_invariant :
forall (b:bool) (p:N * T) (l r:avl_tree T),
binary_tree_invariant l -> binary_tree_invariant r ->
forall_keys (N.gt (fst p)) l -> forall_keys (N.lt (fst p)) r ->
binary_tree_invariant (fst (rotate_right b l p r)).
Proof.
pose all_keys_smaller_chain as T1.
pose all_keys_greater_chain as T2.
intros b p l r bt_inv_l bt_inv_r l_smaller r_greater.
destruct r as [rb rl rp rr|].
- simpl. destruct rb; destruct rl as [rlb rll rlp rlr|];
simpl in *; simpl in *;
rewrite_all N.gt_lt_iff; intuition eauto.
- simpl. auto.
Qed.
(** Proof that the result of [rotate_left] contains exactly the same values as it's
* input tree.
*)
Lemma rotate_left_same_elements :
forall (b:bool) (p p':N * T) (l r:avl_tree T),
In p' (Avl_branch zero l p r) <->
In p' (fst (rotate_left b l p r)).
Proof.
intros b p p' l r.
destruct l as [lb ll lp lr|].
- simpl. destruct lb;
destruct lr as [lrb lrl lrp lrr|];
simpl in *;
intuition (subst; assumption || discriminate).
- simpl. reflexivity.
Qed.
(** Like [rotate_left_same_elements], but for [rotate_right] *)
Lemma rotate_right_same_elements :
forall (b:bool) (p p':N * T) (l r:avl_tree T),
In p' (Avl_branch zero l p r) <->
In p' (fst (rotate_right b l p r)).
Proof.
intros b p p' l r.
destruct r as [rb rl rp rr|].
- simpl. destruct rb;
destruct rl as [rlb rll rlp rlr|];
simpl in *;
intuition (subst; assumption || discriminate).
- simpl. reflexivity.
Qed.
(** Proof that [node] preserves the binary tree invariant. *)
Theorem node_binary_tree_invariant :
forall (b:sign) (s:sign + sign) (l r:avl_tree T) (p:N * T),
binary_tree_invariant l -> binary_tree_invariant r ->
forall_keys (N.gt (fst p)) l -> forall_keys (N.lt (fst p)) r ->
binary_tree_invariant (fst (node b s l p r)).
Proof.
pose rotate_right_binary_tree_invariant as T1.
pose rotate_left_binary_tree_invariant as T2.
intros b s l p v bt_inv_l bt_inv_r l_smaller r_greater. unfold node.
destruct s as [s|s]; destruct s; destruct b; simpl; auto.
Qed.
(** Proof that [node] doesn't change the elements that the tree contains. *)
Theorem node_same_elements :
forall (b:sign) (s:sign + sign) (l r:avl_tree T) (p p':N * T),
p' = p \/ In p' l \/ In p' r <->
In p' (fst (node b s l p r)).
Proof.
Hint Rewrite <- rotate_right_same_elements rotate_left_same_elements : core.
intros b s l r p p'.
destruct s as [s|s]; destruct s; destruct b; unfold node; simpl;
autorewrite with core; simpl; split; trivial.
Qed.
(** Proof that node preserves forall_keys (this is the case since it preserves all
* elements
*)
Lemma node_preserve_forall :
forall (l r:avl_tree T) (p:N * T) (b:sign) (s:sign + sign) (P:N -> Prop),
forall_keys P l -> forall_keys P r -> P (fst p) ->
forall_keys P (fst (node b s l p r)).
Proof.
Hint Rewrite -> forall_keys_In_iff.
Hint Rewrite <- node_same_elements.
intros l r p b s P forall_l forall_r P_k.
apply forall_keys_In_iff. intros. autorewrite with core in *.
rewrite_all invert_tuple_eq. intuition (subst; simpl in *; eauto).
Qed.
(** This proposition states that the height change returned by a function matches
* the real height change.
*)
Definition height_change_correct (c:sign) (t t':avl_tree T) : Prop :=
match c with
| negative => avl_height t = N.succ (avl_height t')
| zero => avl_height t = avl_height t'
| positive => N.succ (avl_height t) = avl_height t'
end.
Global Arguments height_change_correct : default implicits.
(** Proposition to state that either the left or the right subtree changed it's height
* by the given amount. The other subtree must not have changed at all.
*)
Definition changed_height_in (s:sign + sign) (l l' r r':avl_tree T) : Prop :=
match s with
| inl c => r = r' /\ height_change_correct c l l'
| inr c => l = l' /\ height_change_correct c r r'
end.
Global Arguments changed_height_in : default implicits.
Lemma max_succ_id_r :
forall (n:N), N.max n (N.succ n) = N.succ n.
Proof.
Hint Resolve N.le_succ_diag_r.
intros n. rewrite N.max_r; auto.
Qed.
Lemma max_succ_id_l :
forall (n:N), N.max (N.succ n) n = N.succ n.
Proof.
intros. rewrite N.max_comm. apply max_succ_id_r.
Qed.
Theorem rotate_right_balance_correct :
forall (rem:bool) (l r:avl_tree T) (p:N * T),
N.succ (N.succ (avl_height l)) = avl_height r ->
balance_correct l -> balance_correct r ->
balance_correct (fst (rotate_right rem l p r)).
Proof.
intros rem l r p heq bal_l bal_r.
pose max_succ_id_l. pose max_succ_id_r.
pose N.max_id. pose N.max_comm. pose N.max_assoc.
destruct r as [rb rl rp rr|].
- destruct bal_r as [rl_heq [bal_rl bal_rr]]. simpl in *. apply N.succ_inj in heq.
destruct rb.
+ simpl in *. rewrite <- rl_heq in heq. rewrite max_succ_id_r in heq.
apply N.succ_inj in heq. repeat split; congruence.
+ simpl in *. rewrite <- rl_heq in heq. rewrite N.max_id in heq.
repeat split; congruence.
+ destruct rl as [rlb rll rlp rlr|].
* simpl in *. apply N.succ_inj in rl_heq. rewrite_all <- rl_heq.
rewrite max_succ_id_l in heq. apply N.succ_inj in heq.
repeat split; destruct rlb; simpl in *; intuition congruence.
* simpl in *. exfalso. apply N.neq_0_succ with (avl_height rr). tauto.
- simpl in *. apply N.neq_succ_0 in heq. tauto.
Qed.
Theorem rotate_left_balance_correct :
forall (rem:bool) (l r:avl_tree T) (p:N * T),
N.succ (N.succ (avl_height r)) = avl_height l ->
balance_correct l -> balance_correct r ->
balance_correct (fst (rotate_left rem l p r)).
Proof.
intros rem l r p heq bal_l bal_r. pose max_succ_id_l. pose max_succ_id_r.
pose N.max_id. pose N.max_comm. pose N.max_assoc.
destruct l as [lb ll lp lr|].
- destruct bal_l as [lr_heq [bal_ll bal_lr]]. simpl in *. apply N.succ_inj in heq.
destruct lb.
+ destruct lr as [lrb lrl lrp lrr|].
* simpl in *. apply N.succ_inj in lr_heq. rewrite_all <- lr_heq.
rewrite max_succ_id_r in heq. apply N.succ_inj in heq.
repeat split; destruct lrb; simpl in *; intuition congruence.
* simpl in *. exfalso. apply N.neq_succ_0 with (avl_height ll). tauto.
+ simpl in *. rewrite <- lr_heq in heq. rewrite N.max_id in heq.
repeat split; congruence.
+ simpl in *. rewrite lr_heq in heq. rewrite max_succ_id_l in heq.
apply N.succ_inj in heq. repeat split; congruence.
- simpl in *. apply N.neq_succ_0 in heq. contradiction.
Qed.
(** Proof that the tree returned by [node] has correct balance values. *)
Theorem node_balance_correct :
forall (l l' r r':avl_tree T) (p:N * T) (b:sign) (s:sign + sign),
changed_height_in s l l' r r' ->
balance_correct (Avl_branch b l p r) ->
balance_correct l' -> balance_correct r' ->
balance_correct (fst (node b s l' p r')).
Proof.
intros l l' r r' p b s H bal_prev bal_l' bal_r'. unfold node.
destruct s as [hd|hd];
simpl in *;
destruct b; destruct hd; simpl in *;
try (apply rotate_right_balance_correct || apply rotate_left_balance_correct);
repeat split;
try (apply N.succ_inj);
intuition congruence.
Qed.
Theorem rotate_left_rem_height_change_correct :
forall (l r r':avl_tree T) (p:N * T),
N.succ (N.succ (avl_height r')) = avl_height l ->
avl_height r = N.succ (avl_height r') ->
balance_correct l ->
height_change_correct (snd (rotate_left true l p r'))
(Avl_branch positive l p r)
(fst (rotate_left true l p r')).
Proof.
pose max_succ_id_r. pose N.max_comm. pose N.max_assoc. pose N.max_id.
pose N.succ_inj_wd. pose max_succ_id_r. pose max_succ_id_l. pose N.succ_max_distr.
intros l r r' p l_heq r_heq bal_l. destruct l as [lb ll lp lr|].
- simpl in *. destruct lb.
+ destruct lr as [lrb lrl lrp lrr|]; simpl in *; intuition congruence.
+ simpl in *. intuition congruence.
+ simpl in *. intuition congruence.
- simpl in *. intuition congruence.
Qed.
Theorem rotate_right_rem_height_change_correct :
forall (l l' r:avl_tree T) (p:N * T),
N.succ (N.succ (avl_height l')) = avl_height r ->
avl_height l = N.succ (avl_height l') ->
balance_correct r ->
height_change_correct (snd (rotate_right true l' p r))
(Avl_branch negative l p r)
(fst (rotate_right true l' p r)).
Proof.
pose max_succ_id_r. pose N.max_comm. pose N.max_assoc. pose N.max_id.
pose N.succ_inj_wd. pose max_succ_id_r. pose max_succ_id_l. pose N.succ_max_distr.
intros l l' r p l_heq r_heq bal_r. destruct r as [rb rl rp rr|].
- simpl in *. destruct rb.
+ simpl in *. intuition congruence.
+ simpl in *. intuition congruence.
+ destruct rl as [rlb rll rlp rlr|]; simpl in *; intuition congruence.
- simpl in *. intuition congruence.
Qed.
(** Proposition that the given tree is a result of an insertion that triggered
* a rotation operation. For example, an empty tree can never be a result of an
* insert operation.
*)
Definition correct_for_insert (t:avl_tree T) : Prop :=
match t with
| Avl_branch _ Avl_empty _ Avl_empty => True
| Avl_branch b l _ r => b <> zero
| Avl_empty => False
end.
Global Arguments correct_for_insert : default implicits.
Theorem rotate_left_ins_height_change_correct :
forall (l l' r:avl_tree T) (p:N * T),
N.succ (N.succ (avl_height r)) = avl_height l' ->
avl_height l' = N.succ (avl_height l) ->
correct_for_insert l' -> balance_correct l' ->
height_change_correct (snd (rotate_left false l' p r))
(Avl_branch positive l p r)
(fst (rotate_left false l' p r)).
Proof.
pose max_succ_id_r. pose max_succ_id_l. pose N.max_id. pose N.succ_max_distr.
pose N.max_comm. pose N.max_assoc. pose N.succ_inj_wd.
intros l l' r p l'r_heq l_heq l'_c bal_l'.
assert (lr_heq := l'r_heq). rewrite l_heq in lr_heq. apply N.succ_inj in lr_heq.
destruct l' as [l'b l'l l'p l'r|].
- destruct l'b.
+ destruct l'r as [l'rb l'rl l'rp l'rr|].
* simpl in *; intuition congruence.
* simpl in *. exfalso. apply N.neq_succ_0 with (avl_height l'l). tauto.
+ simpl in *. destruct l'l; destruct l'r.
* exfalso. auto.
* exfalso. auto.
* exfalso. auto.
* simpl in *. exfalso. rewrite N.one_succ in l'r_heq.
apply N.succ_inj in l'r_heq. apply N.succ_0_discr in l'r_heq. auto.
+ simpl in *. intuition congruence.
- simpl in *. intuition congruence.
Qed.
Theorem rotate_right_ins_height_change_correct :
forall (l r r':avl_tree T) (p:N * T),
N.succ (N.succ (avl_height l)) = avl_height r' ->
avl_height r' = N.succ (avl_height r) ->
correct_for_insert r' -> balance_correct r' ->
height_change_correct (snd (rotate_right false l p r'))
(Avl_branch positive l p r)
(fst (rotate_right false l p r')).
Proof.
pose max_succ_id_r. pose max_succ_id_l. pose N.max_id. pose N.succ_max_distr.
pose N.max_comm. pose N.max_assoc. pose N.succ_inj_wd.
intros l r r' p lr'_heq r_heq r'_bal_nz bal_r'.
destruct r' as [r'b r'l r'p r'r|].
- destruct r'b.
+ simpl in *. intuition congruence.
+ simpl in *. destruct r'l; destruct r'r.
* exfalso. auto.
* exfalso. auto.
* exfalso. auto.
* simpl in *. rewrite N.one_succ in lr'_heq. apply N.succ_inj in lr'_heq.
apply N.succ_0_discr in lr'_heq. contradiction.
+ destruct r'l as [r'lb r'll r'lp r'lr|].
* simpl in *; intuition congruence.
* simpl in *. exfalso. apply N.neq_0_succ with (avl_height r'r). tauto.
- simpl in *. intuition congruence.
Qed.
(** Apply [correct_for_insert] only to the subtree which changed. *)
Definition correct_for_insert_in (s:sign + sign) (l r:avl_tree T) : Prop :=
match s with
| inl positive => correct_for_insert l
| inr positive => correct_for_insert r
| _ => True
end.
Theorem node_height_change_correct :
forall (b:sign) (s:sign + sign) (l l' r r':avl_tree T) (p:N * T),
changed_height_in s l l' r r' ->
correct_for_insert_in s l' r' ->
balance_correct (Avl_branch b l p r) -> balance_correct l' -> balance_correct r' ->
height_change_correct (snd (node b s l' p r'))
(Avl_branch b l p r)
(fst (node b s l' p r')).
Proof.
pose max_succ_id_r. pose max_succ_id_l. pose N.max_id. pose N.succ_max_distr.
pose N.max_comm. pose N.max_assoc. pose N.succ_inj_wd.
intros b s l l' r r' p ch bal_nz_in bal_t bal_l' bal_r'.
unfold node. destruct s as [hd|hd];
destruct hd; destruct b; simpl in *;
intuition (
subst;
try apply rotate_right_rem_height_change_correct;
try apply rotate_right_ins_height_change_correct;
try apply rotate_left_rem_height_change_correct;
try apply rotate_left_ins_height_change_correct;
congruence).
Qed.
Theorem rotate_right_correct_for_insert :
forall (rem:bool) (l r:avl_tree T) (p:N * T),
snd (rotate_right rem l p r) = positive ->
correct_for_insert (fst (rotate_right rem l p r)).
Proof.
intros rem l r p H.
destruct r as [rb rl rp rr|].
- destruct rl as [rlb rll rlp rlr|]; destruct rem; destruct rb; simpl in *;
discriminate.
- discriminate.
Qed.
Theorem rotate_left_correct_for_insert :
forall (rem:bool) (l r:avl_tree T) (p:N * T),
snd (rotate_left rem l p r) = positive ->
correct_for_insert (fst (rotate_left rem l p r)).
Proof.
intros rem l r p. destruct l as [lb ll lp lr|].
- destruct rem; destruct lb; destruct lr; discriminate.
- discriminate.
Qed.
Theorem node_correct_for_insert :
forall (b:sign) (s:sign + sign) (l r:avl_tree T) (p:N * T),
snd (node b s l p r) = positive ->
correct_for_insert (fst (node b s l p r)).
Proof.
intros b s l r p H.
pose rotate_right_correct_for_insert. pose rotate_left_correct_for_insert.
unfold node in *.
destruct s as [hd|hd]; destruct hd; destruct b; simpl in *;
(destruct l; destruct r; discriminate || constructor) || auto.
Qed.
Theorem rotate_right_height_change_not_positive :
forall (rem:bool) (l r:avl_tree T) (p:N * T),
snd (rotate_right rem l p r) <> positive.
Proof.
intros rem l r p. unfold rotate_right.
destruct r as [ [| |] [rlb rll rlp rlr|] rp rr|]; destruct rem; simpl in *;
discriminate.
Qed.
Theorem rotate_left_height_change_not_positive :
forall (rem:bool) (l r:avl_tree T) (p:N * T),
snd (rotate_left rem l p r) <> positive.
Proof.
intros rem l r p. unfold rotate_left.
destruct l as [ [| |] ll lp [lrb lrl lrp lrr|]|]; destruct rem; simpl in *;
discriminate.
Qed.
Theorem rotate_right_ins_height_change_not_negative :
forall (l r:avl_tree T) (p:N * T),
snd (rotate_right false l p r) <> negative.
Proof.
intros l r p.
destruct r as [ [| |] [rlb rll rlp rlr|] rp rr|]; simpl in *; discriminate.
Qed.
Theorem rotate_left_ins_height_change_not_negative :
forall (l r:avl_tree T) (p:N * T),
snd (rotate_left false l p r) <> negative.
Proof.
intros l r p.
destruct l as [ [| |] ll lp [lrb lrl lrp lrr|]|]; simpl in *; discriminate.
Qed.
Theorem node_height_change_not_negated_left :
forall (b:sign) (s:sign) (l r:avl_tree T) (p:N * T),
s <> zero ->
sign_negate s <> snd (node b (inl s) l p r).
Proof.
pose rotate_left_height_change_not_positive.
pose rotate_right_height_change_not_positive.
pose rotate_left_ins_height_change_not_negative.
pose rotate_right_ins_height_change_not_negative.
intros b s l r p. unfold node.
destruct s; destruct b; simpl; auto; try discriminate.
Qed.
Theorem node_height_change_not_negated_right :
forall (b:sign) (s:sign) (l r:avl_tree T) (p:N * T),
s <> zero ->
sign_negate s <> snd (node b (inr s) l p r).
Proof.
pose rotate_left_height_change_not_positive.
pose rotate_right_height_change_not_positive.
pose rotate_left_ins_height_change_not_negative.
pose rotate_right_ins_height_change_not_negative.
intros b s l r p. unfold node.
destruct s; destruct b; simpl; auto; try discriminate.
Qed.
End Node.
Section Insert.
Variable T : Type.
Fixpoint avl_insert_go (k:N) (v:T) (t:avl_tree T) : avl_tree T * sign :=
match t with
| Avl_empty => (Avl_branch zero Avl_empty (k,v) Avl_empty, positive)
| Avl_branch b l (k',v') r =>
match N.compare k k' with
| Eq => (Avl_branch b l (k,v) r, zero)
| Lt =>
let (l', s) := avl_insert_go k v l
in node b (inl s) l' (k',v') r
| Gt =>
let (r', s) := avl_insert_go k v r
in node b (inr s) l (k',v') r'
end
end.
Definition avl_insert (k:N) (v:T) (t:avl_tree T) : avl_tree T :=
fst (avl_insert_go k v t).
Global Arguments avl_insert : default implicits.
Example avl_insert_ex1 :
forall a b c : T,
avl_insert 1 a (avl_insert 2 b (avl_insert 3 c Avl_empty)) =
Avl_branch zero
(Avl_branch zero Avl_empty (1,a) Avl_empty)
(2,b)
(Avl_branch zero Avl_empty (3,c) Avl_empty).
Proof. intros. unfold avl_insert. simpl. reflexivity. Qed.
Example avl_insert_ex2 :
forall a b c d : T,
avl_insert 3 c (avl_insert 4 d (avl_insert 2 b (avl_insert 1 a Avl_empty))) =
Avl_branch negative
(Avl_branch zero Avl_empty (1,a) Avl_empty)
(2,b)
(Avl_branch positive
(Avl_branch zero Avl_empty (3,c) Avl_empty)
(4,d)
Avl_empty).
Proof. intros. reflexivity. Qed.
Example avl_insert_ex3 :
forall a b c d : T,
avl_insert 3 c (avl_insert 2 b (avl_insert 4 d (avl_insert 1 a Avl_empty))) =
avl_insert 3 c (avl_insert 4 d (avl_insert 2 b (avl_insert 1 a Avl_empty))).
Proof. intros. reflexivity. Qed.
Theorem insert_In :
forall (k:N) (v:T) (t:avl_tree T),
In (k,v) (avl_insert k v t).
Proof.
Hint Resolve -> node_same_elements.
intros k v t. induction t as [b l IHl [k' v'] r IHr|].
- unfold avl_insert in *. simpl. destruct (N.compare k k').
+ simpl. tauto.
+ destruct (avl_insert_go k v l). auto.
+ destruct (avl_insert_go k v r). auto.
- simpl. auto.
Qed.
Theorem insert_preserve_other :
forall (k k':N) (v v':T) (t:avl_tree T),
k <> k' -> (In (k,v) t <-> In (k,v) (avl_insert k' v' t)).
Proof.
Hint Rewrite invert_tuple_eq : core.
Hint Rewrite <- node_same_elements : core.
intros k k' v v' t ineq. induction t as [b l IHl [k'' v''] r IHr|].
- unfold avl_insert in *. simpl. destruct (N.compare k' k'') eqn:E.
+ apply N.compare_eq_iff in E. subst k''. simpl. rewrite_all invert_tuple_eq.
split; intuition (assumption || (exfalso; auto)).
+ destruct (avl_insert_go k' v' l). simpl in *.
autorewrite with core. rewrite IHl. reflexivity.
+ destruct (avl_insert_go k' v' r). simpl in *.
autorewrite with core. rewrite IHr. reflexivity.
- simpl. autorewrite with core. intuition auto.
Qed.
Theorem insert_forall_keys :
forall (k:N) (v:T) (t:avl_tree T) (P:N -> Prop),
forall_keys P t -> P k -> forall_keys P (avl_insert k v t).
Proof.
Hint Resolve <- insert_preserve_other.
setoid_rewrite forall_keys_In_iff. intros k v t P forall_t for_P [k' v'].
destruct (N.eq_dec k k'); subst; eauto.
Qed.
Theorem insert_binary_tree_invariant :
forall (k:N) (v:T) (t:avl_tree T),
binary_tree_invariant t -> binary_tree_invariant (avl_insert k v t).
Proof.
Hint Resolve node_binary_tree_invariant insert_forall_keys.
Hint Resolve -> N.gt_lt_iff.
Hint Resolve <- N.gt_lt_iff.
intros k v t bt_inv_t. induction t as [b l IHl [k' v'] r IHr|].
- unfold avl_insert in *. simpl. destruct (N.compare_spec k k') as [C|C|C].
+ simpl in *. subst k'. auto.
+ destruct (avl_insert_go k v l) as [a s] eqn:X.
replace a with (avl_insert k v l) in * by (unfold avl_insert; rewrite X; auto).
simpl in *. intuition auto.
+ destruct (avl_insert_go k v r) as [a s] eqn:X.
replace a with (avl_insert k v r) in * by (unfold avl_insert; rewrite X; auto).
simpl in *. intuition auto.
- simpl. auto.
Qed.
Theorem insert_correct_for_insert :
forall (k:N) (v:T) (t:avl_tree T),
snd (avl_insert_go k v t) = positive ->
correct_for_insert (fst (avl_insert_go k v t)).
Proof.
intros k v t hd_eq. destruct t as [b l [k' v'] r|].
- simpl in *. destruct (N.compare_spec k k') as [H|H|H].
+ discriminate.
+ destruct (avl_insert_go k v l) eqn:go_eq. apply node_correct_for_insert.
assumption.
+ destruct (avl_insert_go k v r) eqn:go_eq. apply node_correct_for_insert.
assumption.
- simpl in *. constructor.
Qed.
Theorem insert_balance_and_height_correct :
forall (k:N) (v:T) (t:avl_tree T),
balance_correct t ->
balance_correct (fst (avl_insert_go k v t)) /\
height_change_correct (snd (avl_insert_go k v t))
t
(fst (avl_insert_go k v t)).
Proof.
intros k v t bal_t. unfold avl_insert. induction t as [b l IHl [k' v'] r IHr|].
- simpl in *. destruct (N.compare_spec k k') as [H|H|H].
+ simpl. tauto.
+ destruct (avl_insert_go k v l) as [l' s] eqn:go_eq. split.
* apply node_balance_correct with (l := l) (r := r); simpl; tauto.
* assert (s = positive -> correct_for_insert l').
{ replace l' with (fst (l', s)) by reflexivity.
rewrite <- go_eq. intros. apply insert_correct_for_insert. rewrite go_eq.
auto.
}
apply node_height_change_correct; simpl; destruct s; tauto.
+ destruct (avl_insert_go k v r) as [r' s] eqn:go_eq. split.
* apply node_balance_correct with (l := l) (r := r); simpl; tauto.
* assert (s = positive -> correct_for_insert r').
{ replace r' with (fst (r', s)) by reflexivity.
rewrite <- go_eq. intros. apply insert_correct_for_insert. rewrite go_eq.
auto.
}
apply node_height_change_correct; simpl; destruct s; tauto.
- simpl. auto.
Qed.
Theorem insert_balance_correct :
forall (k:N) (v:T) (t:avl_tree T),
balance_correct t -> balance_correct (avl_insert k v t).
Proof.
intros k v t H. eapply proj1. eapply insert_balance_and_height_correct. assumption.
Qed.
Theorem insert_avl_invariant :
forall (k:N) (v:T) (t:avl_tree T),
balance_correct t -> avl_invariant (avl_insert k v t).
Proof.
intros k v t H.
destruct insert_balance_and_height_correct with (k := k) (v := v) (t := t).
- assumption.
- apply balance_correct_implies_avl_invariant. unfold avl_insert. auto.
Qed.
Theorem insert_In_inv :
forall (t:avl_tree T) (k:N) (v v':T),
binary_tree_invariant t -> In (k, v') (avl_insert k v t) -> v = v'.
Proof.
pose N.gt_lt as T1. pose N.lt_irrefl as T2. pose N.lt_gt as T3.
intros t k v v' bt_inv H. unfold avl_insert in H.
induction t as [b l IHl [k'' v''] r IHr|].
- simpl in *.
destruct (N.compare_spec k k'') as [C|C|C].
+ simpl in *. subst k''. apply In_inv_head in H; intuition eauto.
+ destruct (avl_insert_go k v l) as [l' s] eqn:go_eq.
rewrite <- node_same_elements in H.
simpl in *.
apply In_inv_left in H; intuition eauto.
+ destruct (avl_insert_go k v r) as [r' s] eqn:go_eq.
rewrite <- node_same_elements in H.
simpl in *.
apply In_inv_right in H; intuition eauto.
- simpl in *. destruct H as [H|[H|H]]; inversion H; auto.
Qed.
End Insert.
Section Minimum.
Variable T : Type.
Fixpoint avl_find_minimum (t:avl_tree T) (def:N * T): (N * T) :=
match t with
| Avl_empty => def
| Avl_branch lb ll lp lr => avl_find_minimum ll lp
end.
Global Arguments avl_find_minimum : default implicits.
Example avl_find_minimum_ex1 :
forall a b c d : T,
avl_find_minimum
(avl_insert 1 a (avl_insert 2 b (avl_insert 3 c (avl_insert 4 d Avl_empty))))
(5,d)
= (1,a).
Proof. intros. reflexivity. Qed.
Theorem avl_find_minimum_In :
forall (t:avl_tree T) (def:N * T),
In (avl_find_minimum t def) t \/ avl_find_minimum t def = def.
Proof.
intros t. induction t as [b l IHl p r IHr|].
- intros def. clear IHr. specialize IHl with p. simpl in *. intuition eauto.
- intros. simpl. tauto.
Qed.
Theorem avl_find_minimum_is_min :
forall (t:avl_tree T) (def:N * T),
binary_tree_invariant t ->
forall_keys (N.le (fst (avl_find_minimum t def))) t.
Proof.
intros t def bt_inv. pose N.gt_lt as T1. pose N.lt_le_incl as T2.
generalize dependent def. induction t as [b l IHl p r IHr|].
- intros def. clear IHr. simpl. specialize IHl with p. destruct p as [k v].
simpl in *.
assert (min_le_k: fst (avl_find_minimum l (k,v)) <= k).
{
destruct avl_find_minimum_In with (t := l) (def := (k,v)) as [H|H].
- rewrite_all forall_keys_In_iff. intuition eauto.
- rewrite H. reflexivity.
}
repeat split.
+ auto.
+ intuition auto.
+ rewrite_all forall_keys_In_iff. intros p in_r. rewrite min_le_k. intuition eauto.
- simpl. auto.
Qed.
Fixpoint avl_remove_minimum_go (b:sign) (l:avl_tree T) (p:N * T) (r:avl_tree T)
: (avl_tree T * sign) :=
match l with
| Avl_empty => (r, negative)
| Avl_branch lb ll lp lr =>
let (l',s) := avl_remove_minimum_go lb ll lp lr
in node b (inl s) l' p r
end.
Global Arguments avl_remove_minimum_go : default implicits.
Theorem avl_remove_minimum_go_preserve_other :
forall (l:avl_tree T) (p':N * T) (b:sign) (p:N * T) (r:avl_tree T),
p' = p \/ In p' l \/ In p' r <->
(In p' (fst (avl_remove_minimum_go b l p r)) \/ p' = avl_find_minimum l p).
Proof.
intros l p'. induction l as [lb ll IHll lp lr IHlr|].
- intros b p r. simpl in *.
destruct (avl_remove_minimum_go lb ll lp lr) as [l' s] eqn:rec_eq.
rewrite <- node_same_elements.
replace l' with (fst (l', s)) by reflexivity. rewrite <- rec_eq.
rewrite IHll with (b := lb). tauto.
- intros. simpl. tauto.
Qed.
Theorem avl_remove_minimum_go_subset :
forall (l:avl_tree T) (p':N * T) (b:sign) (p:N * T) (r:avl_tree T),
In p' (fst (avl_remove_minimum_go b l p r)) -> p' = p \/ In p' l \/ In p' r.
Proof.
intros l p'. induction l as [lb ll IHll lp lr IHlr|].
- intros b p r. clear IHlr. specialize IHll with lb lp lr. simpl in *.
destruct (avl_remove_minimum_go lb ll lp lr) as [l' s] eqn:rec_eq.
replace l' with (fst (l',s)) by reflexivity.
rewrite <- node_same_elements. intuition auto.
- intros. simpl. auto.
Qed.
Theorem avl_remove_minimum_go_preserve_forall :
forall (P:N -> Prop) (b:sign) (l:avl_tree T) (p:N * T) (r:avl_tree T),
P (fst p) /\ forall_keys P l /\ forall_keys P r ->
forall_keys P (fst (avl_remove_minimum_go b l p r)).
Proof.
pose avl_remove_minimum_go_subset as T1.
intros. rewrite_all forall_keys_In_iff. intros p' in_rm.
apply avl_remove_minimum_go_subset in in_rm. intuition (subst; eauto).
Qed.
Theorem avl_remove_minimum_go_binary_tree_invariant:
forall (l:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
binary_tree_invariant (Avl_branch b l p r) ->
binary_tree_invariant (fst (avl_remove_minimum_go b l p r)).
Proof.
pose node_binary_tree_invariant as T1.
pose avl_remove_minimum_go_preserve_forall as T2.
intros l. induction l as [lb ll IHll lp lr IHlr|].
- intros b p r bt_inv. simpl in *. clear IHlr. specialize IHll with lb lp lr.
simpl in *. destruct p as [k v]. destruct lp as [lk lv].
destruct (avl_remove_minimum_go lb ll (lk,lv) lr) as [l' s] eqn:min_eq.
replace l' with (fst (l',s)) by reflexivity. rewrite_all <- min_eq.
intuition eauto.
- intros b [k v] r. simpl in *. tauto.
Qed.
Theorem avl_remove_minimum_go_min_not_In :
forall (l:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
binary_tree_invariant (Avl_branch b l p r) ->
~In (avl_find_minimum l p) (fst (avl_remove_minimum_go b l p r)).
Proof.
pose N.gt_lt as T1.
intros l. induction l as [lb ll IHll lp lr IHlr|].
- intros b p r bt_inv H. simpl in *.
destruct (avl_remove_minimum_go lb ll lp lr) as [l' s] eqn:rec_eq.
rewrite <- node_same_elements in H. specialize IHll with lb lp lr.
clear IHlr. replace l' with (fst (l', s)) in H by reflexivity.
rewrite_all <- rec_eq. rewrite_all forall_keys_In_iff. destruct H as [H|[H|H]].
+ destruct avl_find_minimum_In with (t := ll) (def := lp) as [P|P].
* apply N.lt_irrefl with (x := fst p). subst. intuition eauto.
* apply N.lt_irrefl with (x := fst p). rewrite_all P. subst. intuition auto.
+ apply IHll; intuition eauto.
+ destruct avl_find_minimum_In with (t := ll) (def := lp) as [P|P].
* apply N.lt_asymm with (n := fst p) (m := fst (avl_find_minimum ll lp));
intuition eauto.
* rewrite_all P. apply N.lt_asymm with (n := fst lp) (m := fst p);
intuition eauto.
- intros b p r inv_bt H. simpl in *. rewrite_all forall_keys_In_iff.
apply N.lt_irrefl with (x := fst p). intuition eauto.
Qed.
Theorem avl_remove_minimum_go_removes_minimum :
forall (l:avl_tree T) (min_k:N) (b:sign) (p:N * T) (r:avl_tree T),
binary_tree_invariant (Avl_branch b l p r) ->
forall_keys (N.le min_k) (Avl_branch b l p r) ->
forall_keys (N.lt min_k) (fst (avl_remove_minimum_go b l p r)).
Proof.
pose all_keys_greater_chain_eq as T1. pose all_keys_greater_chain as T2.
pose N.le_lt_trans as T3. pose node_preserve_forall as T4. pose N.gt_lt as T5.
intros l min_k. induction l as [lb ll IHll lp lr IHlr|].
- intros b p r bt_inv H. simpl in *. clear IHlr. specialize IHll with lb lp lr.
destruct (avl_remove_minimum_go lb ll lp lr) as [l' s] eqn:rec_eq.
replace l' with (fst (l', s)) by reflexivity. rewrite_all <- rec_eq.
intuition eauto.
- intros. simpl in *. intuition eauto.
Qed.
Theorem avl_remove_minimum_go_all_greater :
forall (l:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
binary_tree_invariant (Avl_branch b l p r) ->
forall_keys (N.lt (fst (avl_find_minimum l p)))
(fst (avl_remove_minimum_go b l p r)).
Proof.
pose all_keys_greater_chain_eq as T1. pose all_keys_greater_chain as T2.
pose N.le_lt_trans as T3. pose node_preserve_forall as T4. pose N.gt_lt as T5.
pose N.lt_le_incl as T6.
intros l b p r bt_inv. apply avl_remove_minimum_go_removes_minimum.
- assumption.
- simpl.
destruct avl_find_minimum_In with (t := l) (def := p) as [H|H].
+ simpl in *. repeat split.
* rewrite_all forall_keys_In_iff. intuition eauto.
* apply avl_find_minimum_is_min. tauto.
* rewrite_all forall_keys_In_iff.
assert (pk_gt: fst (avl_find_minimum l p) <= fst p) by intuition eauto.
intros p' in_r. intuition eauto.
+ simpl in *. rewrite_all H. repeat split.
* reflexivity.
* rewrite <- H. apply avl_find_minimum_is_min. tauto.
* rewrite_all forall_keys_In_iff. intros p' in_r. intuition eauto.
Qed.
Theorem avl_remove_minimum_go_height_change_not_positive :
forall (l:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
positive <> snd (avl_remove_minimum_go b l p r).
Proof.
pose node_height_change_not_negated_left as NHL.
pose node_height_change_not_negated_right as NHR.
intros l. induction l as [b' l' IHl' p' r' _|].
- specialize IHl' with b' p' r'. intros b p r. simpl.
destruct (avl_remove_minimum_go b' l' p' r') as [l'' s] eqn:go_eq.
specialize NHL with T b s l'' r p.
specialize NHR with T b s l'' r p.
simpl in *. destruct s; intuition (discriminate || eauto).
- intros. simpl. discriminate.
Qed.
Theorem avl_remove_minimum_go_balance_and_height_change_correct :
forall (l:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
balance_correct (Avl_branch b l p r) ->
balance_correct (fst (avl_remove_minimum_go b l p r)) /\
height_change_correct (snd (avl_remove_minimum_go b l p r))
(Avl_branch b l p r)
(fst (avl_remove_minimum_go b l p r)).
Proof.
intros l. induction l as [b' l' IHl' p' r' IHr'|].
- intros b p r bal_t. clear IHr'. specialize IHl' with b' p' r'.
simpl. destruct (avl_remove_minimum_go b' l' p' r') as [l'' s] eqn:go_eq.
assert (s_not_positive: positive <> s).
{ replace s with (snd (l'', s)) by reflexivity.
rewrite <- go_eq. apply avl_remove_minimum_go_height_change_not_positive.
}
split.
+ apply node_balance_correct with (Avl_branch b' l' p' r') r; simpl in *; tauto.
+ apply node_height_change_correct; destruct s; simpl in *;
intuition (contradiction || tauto).
- intros. simpl in *. rewrite N.max_0_l. tauto.
Qed.
Theorem avl_remove_minimum_go_height_change_correct :
forall (l r:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
balance_correct (Avl_branch b l p r) ->
height_change_correct (snd (avl_remove_minimum_go b l p r))
(Avl_branch b l p r)
(fst (avl_remove_minimum_go b l p r)).
Proof.
pose avl_remove_minimum_go_balance_and_height_change_correct as H.
intros. edestruct H; eassumption.
Qed.
Theorem avl_remove_minimum_go_balance_correct :
forall (l r:avl_tree T) (b:sign) (p:N * T) (r:avl_tree T),
balance_correct (Avl_branch b l p r) ->
balance_correct (fst (avl_remove_minimum_go b l p r)).
Proof.
intros.
edestruct avl_remove_minimum_go_balance_and_height_change_correct; eassumption.
Qed.
End Minimum.
Section Remove.
Variable T : Type.
Definition avl_remove_top (b:sign) (l:avl_tree T) (r:avl_tree T) : avl_tree T * sign :=
match r with
| Avl_empty => (l, negative)
| Avl_branch rb rl rp rr =>
let (r',s) := avl_remove_minimum_go rb rl rp rr
in node b (inr s) l (avl_find_minimum rl rp) r'
end.
Theorem avl_remove_top_preserve_other :
forall (b:sign) (l:avl_tree T) (r:avl_tree T) (p:N * T),
(In p r \/ In p l) <-> In p (fst (avl_remove_top b l r)).
Proof.
intros b l r p. destruct r as [rb rl rp rr|] eqn:r_eq.
- simpl. destruct (avl_remove_minimum_go rb rl rp rr) as [r' s] eqn:rm_min_eq.
replace r' with (fst (r',s)) by reflexivity. rewrite <- rm_min_eq.
rewrite <- node_same_elements.
rewrite avl_remove_minimum_go_preserve_other with (b := rb).
tauto.
- subst. simpl. tauto.
Qed.
Theorem avl_remove_top_binary_tree_invariant :
forall (b:sign) (l:avl_tree T) (r:avl_tree T) (k:N),
forall_keys (N.gt k) l -> forall_keys (N.lt k) r ->
binary_tree_invariant l -> binary_tree_invariant r ->
binary_tree_invariant (fst (avl_remove_top b l r)).
Proof.
pose node_binary_tree_invariant as T1.
pose avl_remove_minimum_go_binary_tree_invariant as T2.
pose avl_remove_minimum_go_subset as T3.
pose N.gt_lt as T4.
intros b l r k k_gt_l k_lt_r bt_inv_l bt_inv_r. destruct r as [rb rl rp rr|].
- simpl in *. destruct (avl_remove_minimum_go rb rl rp rr) as [r' s] eqn:rm_min_eq.
replace r' with (fst (r', s)) by reflexivity. rewrite_all <- rm_min_eq.
apply node_binary_tree_invariant.
+ intuition auto.
+ apply avl_remove_minimum_go_binary_tree_invariant. simpl. intuition auto.
+ destruct avl_find_minimum_In with T rl rp as [H|H].
* rewrite_all forall_keys_In_iff. intros p' in_l.
apply N.lt_gt. apply N.lt_trans with k; intuition eauto.
* rewrite H. apply all_keys_smaller_chain with k; intuition eauto.
+ apply avl_remove_minimum_go_all_greater. simpl. intuition eauto.
- simpl in *. auto.
Qed.
Lemma height_change_correct_change_branch_value :
forall (t l r l' r':avl_tree T) (c b:sign) (p p':N * T),
height_change_correct c (Avl_branch b l' p r') t <->
height_change_correct c (Avl_branch b l' p' r') t.
Proof.
intros. destruct c; simpl; reflexivity.
Qed.
Theorem avl_remove_top_balance_and_height_correct :
forall (b:sign) (l:avl_tree T) (r:avl_tree T) (p:N * T) ,
balance_correct (Avl_branch b l p r) ->
balance_correct (fst (avl_remove_top b l r)) /\
height_change_correct (snd (avl_remove_top b l r))
(Avl_branch b l p r)
(fst (avl_remove_top b l r)).
Proof.
pose avl_remove_minimum_go_height_change_correct as T1.
pose avl_remove_minimum_go_balance_correct as T2.
pose node_balance_correct as T3.
pose node_height_change_correct as T4.
intros b l r p bal_t. destruct r as [rb rl rp rr|].
- simpl in *. destruct (avl_remove_minimum_go rb rl rp rr) as [r' s] eqn:min_eq.
rewrite surjective_pairing in min_eq at 1. inversion min_eq as [[r'_eq s_eq]].
split.
+ apply node_balance_correct with l (Avl_branch rb rl rp rr); simpl in *;
intuition auto.
+ rewrite height_change_correct_change_branch_value.
assert (positive <> s)
by (subst s; apply avl_remove_minimum_go_height_change_not_positive).
apply T4.
* simpl. intuition auto.
* simpl. rewrite s_eq. destruct s; constructor || (exfalso; auto).
* simpl. tauto.
* simpl. tauto.
* simpl. intuition auto.
* tauto.
* tauto.
- simpl in *. rewrite N.max_0_r. tauto.
Qed.
Theorem avl_remove_top_height_change_not_positive :
forall (b:sign) (l r:avl_tree T),
positive <> snd (avl_remove_top b l r).
Proof.
intros b l r. destruct r as [rb rl rp rr|].
- simpl in *. destruct (avl_remove_minimum_go rb rl rp rr) as [r' s] eqn:min_eq.
replace positive with (sign_negate negative) by reflexivity.
assert (s_not_positive: positive <> s).
{ replace s with (snd (r', s)) by reflexivity.
rewrite <- min_eq. apply avl_remove_minimum_go_height_change_not_positive.
}
destruct s.
+ apply node_height_change_not_negated_right. discriminate.
+ simpl. discriminate.
+ exfalso. auto.
- simpl. discriminate.
Qed.
Fixpoint avl_remove_go (k:N) (t:avl_tree T) : avl_tree T * sign :=
match t with
| Avl_empty => (Avl_empty, zero)
| Avl_branch b l (k',v') r =>
match N.compare k k' with
| Lt => let (l',s) := avl_remove_go k l in node b (inl s) l' (k',v') r
| Gt => let (r',s) := avl_remove_go k r in node b (inr s) l (k',v') r'
| Eq => avl_remove_top b l r
end
end.
Definition avl_remove (k:N) (t:avl_tree T) : avl_tree T := fst (avl_remove_go k t).
Global Arguments avl_remove : default implicits.
Example avl_remove_ex1 :
forall a b c : T,
avl_remove 2 (avl_insert 1 a (avl_insert 2 b (avl_insert 3 c Avl_empty))) =
Avl_branch positive (avl_insert 1 a Avl_empty) (3,c) Avl_empty.
Proof. reflexivity. Qed.
Example avl_remove_ex2 :
forall a b c d : T,
avl_remove
2
(avl_insert 3 c (avl_insert 4 d (avl_insert 2 b (avl_insert 1 a Avl_empty)))) =
avl_insert 1 a (avl_insert 4 d (avl_insert 3 c Avl_empty)).
Proof. reflexivity. Qed.
Example avl_remove_ex3 :
forall a b c d e f g h : T,
avl_remove
4
(Avl_branch
positive
(Avl_branch
positive
(Avl_branch
zero
(avl_singleton 1 a)
(2,b)
(avl_singleton 3 c))
(4,d)
(avl_singleton 5 e))
(6,f)
(Avl_branch negative Avl_empty (7,g) (avl_singleton 8 h)))
= Avl_branch
positive
(Avl_branch
negative
(avl_singleton 1 a)
(2,b)
(Avl_branch positive (avl_singleton 3 c) (5,e) Avl_empty))
(6,f)
(Avl_branch negative Avl_empty (7,g) (avl_singleton 8 h)).
Proof. reflexivity. Qed.
Theorem remove_not_In :
forall k v t,
binary_tree_invariant t ->
~In (k,v) (avl_remove k t).
Proof.
pose N.le_lt_trans as T1. pose N.gt_lt as T2. pose N.lt_le_incl as T3.
pose N.lt_irrefl as T4. pose N.lt_le_trans as T5. pose N.lt_gt as T6.
intros k v t bt_inv_t. induction t as [b l IHl p r IHr|].
- unfold avl_remove. simpl. destruct p as [k' v'] eqn:peq.
destruct (N.compare_spec k k') as [C|C|C].
+ intros H. rewrite <- avl_remove_top_preserve_other in H. simpl in *.
rewrite_all forall_keys_In_iff. subst k. apply N.lt_irrefl with k'.
replace k' with (fst (k', v)) by reflexivity. intuition eauto.
+ destruct (avl_remove_go k l) as [l' s] eqn:rec_eq.
replace l' with (fst (l', s)) by reflexivity.
rewrite <- rec_eq. unfold avl_remove in *. rewrite <- node_same_elements.
rewrite invert_tuple_eq. intros H. unfold not in *. simpl in *.
rewrite_all forall_keys_In_iff.
intuition (subst; eauto).
+ destruct (avl_remove_go k r) as [r' s] eqn:rec_eq.
replace r' with (fst (r',s)) by reflexivity.
rewrite <- rec_eq. unfold avl_remove in *. rewrite <- node_same_elements.
rewrite invert_tuple_eq. intros H. unfold not in *. simpl in *.
rewrite_all forall_keys_In_iff.
intuition (subst; (eapply N.lt_irrefl; eauto) || eauto).
- simpl. auto.
Qed.
Theorem remove_preserve_other :
forall (p:N * T) (k:N) (t:avl_tree T),
(In p t <-> (In p (avl_remove k t) \/ (fst p = k /\ In p t))).
Proof.
intros. unfold avl_remove. induction t as [b l IHl [k' v'] r IHr|].
- simpl. destruct (N.compare_spec k k') as [C|C|C].
+ rewrite <- avl_remove_top_preserve_other.
split; intuition (subst; auto).
+ destruct (avl_remove_go k l) as [l' s] eqn:rec_eq.
rewrite <- node_same_elements. replace l' with (fst (l', s)) by reflexivity.
rewrite IHl. tauto.
+ destruct (avl_remove_go k r) as [r' s] eqn:rec_eq.
rewrite <- node_same_elements. replace r' with (fst (r', s)) by reflexivity.
rewrite IHr. tauto.
- simpl. tauto.
Qed.
Theorem remove_subset :
forall (p:N * T) (k:N) (t:avl_tree T),
In p (avl_remove k t) -> In p t.
Proof.
intros. rewrite remove_preserve_other with (k := k). tauto.
Qed.
Theorem remove_preserve_forall :
forall (P:N -> Prop) (k:N) (t:avl_tree T),
forall_keys P t -> forall_keys P (avl_remove k t).
Proof.
Hint Resolve remove_subset.
intros P k t H. rewrite_all forall_keys_In_iff. intros p in_rm.
eauto.
Qed.
Theorem remove_binary_tree_invariant :
forall (k:N) (t:avl_tree T),
binary_tree_invariant t -> binary_tree_invariant (avl_remove k t).
Proof.
Hint Resolve avl_remove_top_binary_tree_invariant node_binary_tree_invariant
remove_preserve_forall.
intros k t bt_inv. unfold avl_remove. induction t as [b l IHl [k' v'] r IHr|].
- simpl. destruct (N.compare_spec k k') as [C|C|C].
+ subst k'. simpl in *. intuition eauto.
+ destruct (avl_remove_go k l) as [l' s] eqn:rec_eq.
replace l' with (fst (l', s)) by reflexivity. rewrite_all <- rec_eq.
simpl in *. fold (avl_remove k l) in *. intuition eauto.
+ destruct (avl_remove_go k r) as [r' s] eqn:rec_eq.
replace r' with (fst (r', s)) by reflexivity. rewrite_all <- rec_eq.
simpl in *. fold (avl_remove k r) in *. intuition eauto.
- simpl. constructor.
Qed.
Theorem remove_height_change_not_positive :
forall (k:N) (t:avl_tree T),
positive <> snd (avl_remove_go k t).
Proof.
intros k t. induction t as [b l IHl [k' v'] r IHr|].
- simpl. destruct (N.compare_spec k k') as [C|C|C].
+ simpl. apply avl_remove_top_height_change_not_positive.
+ destruct (avl_remove_go k l) as [l' s] eqn:go_eq.
simpl in *.
replace positive with (sign_negate negative) by reflexivity.
destruct s.
* apply node_height_change_not_negated_left. discriminate.
* simpl. discriminate.
* exfalso. auto.
+ destruct (avl_remove_go k r) as [r' s] eqn:go_eq.
simpl in *.
replace positive with (sign_negate negative) by reflexivity.
destruct s.
* apply node_height_change_not_negated_right. discriminate.
* simpl. discriminate.
* exfalso. auto.
- simpl. discriminate.
Qed.
Theorem remove_balance_and_height_correct :
forall (k:N) (t:avl_tree T),
balance_correct t ->
balance_correct (fst (avl_remove_go k t)) /\
height_change_correct (snd (avl_remove_go k t))
t
(fst (avl_remove_go k t)).
Proof.
intros k t bal_t. induction t as [b l IHl [k' v'] r IHr|].
- simpl in *. destruct (N.compare_spec k k') as [C|C|C].
+ subst k'. apply avl_remove_top_balance_and_height_correct. auto.
+ destruct (avl_remove_go k l) as [l' s] eqn:go_eq. split.
* apply node_balance_correct with l r; simpl in *; tauto.
* assert (s_not_positive: positive <> s).
{ replace s with (snd (l', s)) by reflexivity.
rewrite <- go_eq.
apply remove_height_change_not_positive.
}
apply node_height_change_correct; simpl in *;
tauto || (destruct s; auto || (exfalso; auto)).
+ destruct (avl_remove_go k r) as [r' s] eqn:go_eq. split.
* apply node_balance_correct with l r; simpl in *; tauto.
* assert (s_not_positive: positive <> s).
{ replace s with (snd (r',s)) by reflexivity.
rewrite <- go_eq.
apply remove_height_change_not_positive.
}
apply node_height_change_correct; simpl in *;
tauto || (destruct s; auto || (exfalso; auto)).
- simpl. auto.
Qed.
Theorem remove_balance_correct :
forall (t:avl_tree T) (k:N),
balance_correct t -> balance_correct (avl_remove k t).
Proof.
intros t k H.
eapply remove_balance_and_height_correct in H.
intuition eassumption.
Qed.
End Remove.
Section Contains.
Definition contains {T:Type} (k:N) (p:T -> Prop) (t:avl_tree T) :=
exists v, In (k,v) t /\ p v.
Definition in_domain {T:Type} (k:N) (t:avl_tree T) : Prop :=
exists v, In (k,v) t.
Theorem In_contains :
forall (T:Type) (k:N) (P:T -> Prop) (v:T) (t:avl_tree T),
In (k,v) t -> P v -> contains k P t.
Proof.
intros T k p v t H P. unfold contains. eauto.
Qed.
Theorem In_in_domain :
forall (T:Type) (t:avl_tree T) (k:N) (v:T), In (k,v) t -> in_domain k t.
Proof.
intros T t k v H. unfold in_domain. exists v. assumption.
Qed.
End Contains.
Section Lookup.
Variable T : Type.
Fixpoint avl_lookup (k:N) (t:avl_tree T) : option T :=
match t with
| Avl_empty => None
| Avl_branch _ l (k',v) r =>
match N.compare k k' with
| Lt => avl_lookup k l
| Gt => avl_lookup k r
| Eq => Some v
end
end.
Global Arguments avl_lookup : default implicits.
Example avl_lookup_ex1 :
forall a b c d : T,
avl_lookup
4
(avl_insert 3 c (avl_insert 4 d (avl_insert 2 b (avl_insert 1 a Avl_empty))))
= Some d.
Proof. reflexivity. Qed.
Example avl_lookup_ex2 :
forall a b c d : T,
avl_lookup
5
(avl_insert 3 c (avl_insert 4 d (avl_insert 2 b (avl_insert 1 a Avl_empty))))
= None.
Proof. reflexivity. Qed.
Theorem lookup_In :
forall (k:N) (v:T) (t:avl_tree T), avl_lookup k t = Some v -> In (k,v) t.
Proof.
intros k v t.
induction t as [b l IHl [k' v'] r IHr|].
- simpl. destruct (N.compare_spec k k') as [C|C|C].
+ injection 1. intros. subst. tauto.
+ intuition auto.
+ intuition auto.
- simpl. discriminate 1.
Qed.
Theorem lookup_not_In :
forall (t:avl_tree T) (k:N),
binary_tree_invariant t -> avl_lookup k t = None -> ~in_domain k t.
Proof.
intros t k bt_inv H. unfold in_domain. intros A.
induction t as [b l IHl [k' v'] r IHr|].
- simpl in *. destruct A as [v [A|[A|A]]].
+ inversion A. subst. rewrite N.compare_refl in H. discriminate.
+ rewrite_all forall_keys_In_iff.
replace (k ?= k') with Lt in H.
* intuition eauto.
* symmetry. apply N.compare_lt_iff. apply N.gt_lt_iff.
destruct bt_inv as [bt_inv _]. apply bt_inv with (p := (k,v)); auto.
+ rewrite_all forall_keys_In_iff.
replace (k ?= k') with Gt in H.
* intuition eauto.
* symmetry. apply N.compare_gt_iff.
destruct bt_inv as [_ [bt_inv _]]. apply bt_inv with (p := (k,v)); auto.
- simpl in *. destruct A. assumption.
Qed.
Theorem In_lookup :
forall (t:avl_tree T) (k:N) (v:T),
binary_tree_invariant t -> In (k,v) t -> avl_lookup k t = Some v.
Proof.
intros t k v bt_inv H. induction t as [b l IHl [k' v'] r IHr|].
- simpl in *. destruct (N.compare_spec k k') as [C|C|C].
+ subst k'. apply In_inv_head in H; subst; tauto.
+ apply In_inv_left in H; tauto.
+ apply In_inv_right in H; tauto.
- inversion H.
Qed.
Theorem In_lookup_iff :
forall (t:avl_tree T) (k:N) (v:T),
binary_tree_invariant t -> (In (k,v) t <-> avl_lookup k t = Some v).
Proof.
pose In_lookup as T1. pose lookup_In as T2.
intros t k v bt_inv. split; auto.
Qed.
Theorem In_eq :
forall (t:avl_tree T) (k:N) (v v':T),
binary_tree_invariant t ->
In (k,v) t -> In (k, v') t -> v = v'.
Proof.
intros t k v v' bt_inv. rewrite ?In_lookup_iff.
- intros P Q. rewrite P in Q. inversion Q. reflexivity.
- assumption.
- assumption.
Qed.
End Lookup.
Section Update.
Variable T : Type.
Definition avl_update (k:N) (f:T -> T) (t:avl_tree T) :=
match avl_lookup k t with
| None => t
| Some v => avl_insert k (f v) t
end.
Global Arguments avl_update : default implicits.
Theorem update_preserve_other :
forall (t:avl_tree T) (k:N) (f:T -> T) (p:N * T),
fst p <> k -> (In p t <-> In p (avl_update k f t)).
Proof.
pose insert_preserve_other as T1.
intros t k f p k_ineq. unfold avl_update. destruct p.
destruct (avl_lookup k t); auto || reflexivity.
Qed.
Theorem update_In_inv :
forall (t:avl_tree T) (k:N) (f:T -> T) (v:T),
binary_tree_invariant t ->
(In (k,v) (avl_update k f t) <-> (exists x, In (k,x) t /\ f x = v)).
Proof.
pose lookup_In as T1. pose insert_In_inv as T2. pose insert_In as T3.
intros t k f v bt_inv. unfold avl_update.
destruct (avl_lookup k t) as [x|] eqn:lookup.
- simpl. split.
+ eauto.
+ destruct 1 as [x' [in_t fe]]. apply In_lookup in in_t.
* rewrite lookup in in_t. inversion in_t. subst. auto.
* assumption.
- simpl. split.
+ rewrite In_lookup_iff.
* rewrite lookup. discriminate 1.
* assumption.
+ destruct 1 as [x [in_t fe]]. apply In_lookup in in_t.
* rewrite in_t in lookup. discriminate.
* assumption.
Qed.
Theorem update_binary_tree_invariant :
forall (t:avl_tree T) (k:N) (f:T -> T),
binary_tree_invariant t -> binary_tree_invariant (avl_update k f t).
Proof.
intros t k f bt_inv_t. unfold avl_update. pose insert_binary_tree_invariant as T1.
destruct (avl_lookup k t); auto.
Qed.
Theorem update_balance_correct :
forall (t:avl_tree T) (k:N) (f:T -> T),
balance_correct t -> balance_correct (avl_update k f t).
Proof.
intros t k f bt_inv_t. unfold avl_update. pose insert_balance_correct as T1.
destruct (avl_lookup k t); auto.
Qed.
End Update.
Section InsertMerge.
Variable T : Type.
Definition avl_insert_merge (k:N) (f:T -> T) (def:T) (t:avl_tree T) : avl_tree T :=
avl_insert k (match avl_lookup k t with | Some v => f v | None => def end) t.
Global Arguments avl_insert_merge : default implicits.
Theorem insert_merge_contains :
forall (t:avl_tree T) (k:N) (f:T -> T) (def:T) (P:T -> Prop),
binary_tree_invariant t ->
(~in_domain k t -> P def) ->
(forall v, In (k,v) t -> P (f v)) -> contains k P (avl_insert_merge k f def t).
Proof.
intros t k f def P bt_inv Pdef Pf. unfold contains. unfold avl_insert_merge.
pose lookup_In. pose insert_In. pose lookup_not_In.
destruct (avl_lookup k t) as [v|] eqn:lookup.
- exists (f v). split; auto.
- apply lookup_not_In in lookup; eauto.
Qed.
Theorem insert_merge_In_inv :
forall (t:avl_tree T) (k:N) (v def:T) (f:T -> T),
binary_tree_invariant t ->
In (k,v) (avl_insert_merge k f def t) ->
(~in_domain k t /\ v = def) \/ (contains k (fun x => f x = v) t).
Proof.
pose lookup_In as T1. pose lookup_not_In as T2.
intros t k v def f bt_inv in_merge.
unfold avl_insert_merge in in_merge. unfold contains.
apply insert_In_inv in in_merge.
- destruct (avl_lookup k t) as [v'|] eqn:lookup; eauto.
- assumption.
Qed.
Theorem insert_merge_preserve_other :
forall (t:avl_tree T) (k:N) (f:T -> T) (def:T) (p:N * T),
k <> fst p -> (In p t <-> In p (avl_insert_merge k f def t)).
Proof.
pose insert_preserve_other. destruct p. unfold avl_insert_merge. auto.
Qed.
Theorem insert_merge_binary_tree_invariant :
forall (t:avl_tree T) (k:N) (f:T -> T) (def:T),
binary_tree_invariant t -> binary_tree_invariant (avl_insert_merge k f def t).
Proof.
pose insert_binary_tree_invariant as T1.
intros t k f def inv_t. unfold avl_insert_merge. auto.
Qed.
Theorem insert_merge_balance_correct :
forall (t:avl_tree T) (k:N) (f:T -> T) (def:T),
balance_correct t -> balance_correct (avl_insert_merge k f def t).
Proof.
pose insert_balance_correct as T1.
intros t k f def bal_t. unfold avl_insert_merge. auto.
Qed.
End InsertMerge.
Require List.
Open Scope list.
Section Elems.
Variable T : Type.
Fixpoint avl_elems (t:avl_tree T) : list (N * T) :=
match t with
| Avl_empty => nil
| Avl_branch _ l e r => e :: avl_elems l ++ avl_elems r
end.
Global Arguments avl_elems : default implicits.
Theorem elems_In_iff :
forall (t:avl_tree T) (p:N * T),
List.In p (avl_elems t) <-> In p t.
Proof.
intros t p. induction t as [b l IHl tp r IHr|].
- simpl. rewrite <- IHr. rewrite <- IHl. rewrite List.in_app_iff.
assert (H: (tp = p) <-> (p = tp)) by (split; intros; subst; reflexivity).
rewrite H. reflexivity.
- reflexivity.
Qed.
End Elems.
Section Filter.
Variable T : Type.
Fixpoint avl_remove_many (ks:list N) (t:avl_tree T) : avl_tree T :=
match ks with
| nil => t
| k :: kt => avl_remove k (avl_remove_many kt t)
end.
Theorem remove_many_subset :
forall (ks:list N) (t:avl_tree T) (p:N * T),
In p (avl_remove_many ks t) -> In p t.
Proof.
intros ks t p in_remove. pose remove_subset.
induction ks as [|k kt IH]; eauto.
Qed.
Theorem remove_many_binary_tree_invariant :
forall (ks:list N) (t:avl_tree T) (k:N) (v:T),
binary_tree_invariant t -> binary_tree_invariant (avl_remove_many ks t).
Proof.
intros ks t k v. pose remove_binary_tree_invariant. induction ks; simpl; auto.
Qed.
Theorem remove_many_balance_correct :
forall (ks:list N) (t:avl_tree T) (k:N) (v:T),
balance_correct t -> balance_correct (avl_remove_many ks t).
Proof.
intros ks t k v H.
induction ks as [|kh kt IH].
- simpl. auto.
- eapply remove_balance_and_height_correct in IH. simpl in *.
unfold avl_remove. intuition eassumption.
Qed.
Theorem remove_many_not_In :
forall (ks:list N) (t:avl_tree T) (k:N) (v:T),
binary_tree_invariant t -> In (k,v) (avl_remove_many ks t) -> ~(List.In k ks).
Proof.
intros ks t k v bt_inv in_remove. induction ks as [|k' kt IH].
- simpl. auto.
- simpl.
pose remove_not_In as T1. pose remove_many_binary_tree_invariant as T2.
pose remove_subset as T3. unfold not in *.
destruct 1; simpl in *; subst; eauto.
Qed.
Theorem remove_many_preserve_other :
forall (ks:list N) (t:avl_tree T) (k:N) (v:T),
~(List.In k ks) -> (In (k,v) t <-> In (k,v) (avl_remove_many ks t)).
Proof.
intros ks t k v not_in_ks. induction ks as [|k' kt IH].
- simpl. reflexivity.
- simpl in *. assert (H:k <> k') by (intros eq; symmetry in eq; tauto).
rewrite IH by tauto. rewrite remove_preserve_other with (k := k'). simpl.
split.
+ destruct 1; assumption || exfalso; tauto.
+ tauto.
Qed.
Definition avl_filter (f:N -> T -> bool) (t:avl_tree T) : avl_tree T :=
avl_remove_many
(List.map (fun (p:N*T) => let (k,v) := p in k)
(List.filter (fun (p:N*T) => let (k,v) := p in negb (f k v)) (avl_elems t))) t.
Global Arguments avl_filter : default implicits.
Theorem filter_subset :
forall (t:avl_tree T) (p:N * T) (f:N -> T -> bool),
In p (avl_filter f t) -> In p t.
Proof.
unfold avl_filter.
intros t p f. apply remove_many_subset.
Qed.
Theorem filter_predicate_true :
forall (t:avl_tree T) (k:N) (v:T) (f:N -> T -> bool),
binary_tree_invariant t -> In (k,v) (avl_filter f t) -> f k v = true.
Proof.
unfold avl_filter. intros t k v f bt_inv in_filter.
assert (in_t := in_filter). apply remove_many_subset in in_t.
destruct (f k v) eqn:fe.
- reflexivity.
- apply remove_many_not_In in in_filter.
+ rewrite List.in_map_iff in in_filter.
exfalso. apply in_filter. exists (k,v). split.
* reflexivity.
* apply List.filter_In. rewrite elems_In_iff. rewrite fe. simpl. tauto.
+ assumption.
Qed.
Theorem filter_In :
forall (f:N -> T -> bool) (t:avl_tree T) (k:N) (v:T),
binary_tree_invariant t -> ((f k v = true /\ In (k,v) t) <-> In (k,v) (avl_filter f t)).
Proof.
intros f t k v bt_inv. split.
- destruct 1 as [ft in_t]. unfold avl_filter. apply remove_many_preserve_other.
+ intros H. rewrite List.in_map_iff in H. destruct H as [[k' v'] H].
rewrite List.filter_In in H. destruct H as [keq [k'_in_t fe]].
subst k'. replace v' with v in *.
* rewrite ft in fe. discriminate.
* apply elems_In_iff in k'_in_t. eapply In_eq in in_t; eauto.
+ auto.
- pose filter_subset as T1. pose filter_predicate_true as T2. eauto.
Qed.
Theorem filter_binary_tree_invariant :
forall (f:N -> T -> bool) (t:avl_tree T) (k:N) (v:T),
binary_tree_invariant t -> binary_tree_invariant (avl_filter f t).
Proof.
pose remove_many_binary_tree_invariant. unfold avl_filter. auto.
Qed.
Theorem filter_balance_correct :
forall (f:N -> T -> bool) (t:avl_tree T) (k:N) (v:T),
balance_correct t -> balance_correct (avl_filter f t).
Proof.
pose remove_many_balance_correct. unfold avl_filter. auto.
Qed.
End Filter.
Section Map.
Variable A B : Type.
Fixpoint avl_map (f:N -> A -> B) (t:avl_tree A) : avl_tree B :=
match t with
| Avl_empty => Avl_empty
| Avl_branch b l (k,v) r => Avl_branch b (avl_map f l) (k, f k v) (avl_map f r)
end.
Global Arguments avl_map : default implicits.
Theorem map_updates_all :
forall (t:avl_tree A) (f:N -> A -> B) (k:N) (v:A),
In (k,v) t -> In (k,f k v) (avl_map f t).
Proof.
intros t f k v in_t. induction t as [b l IHl [k' v'] r IHr|].
- simpl in *. rewrite invert_tuple_eq in in_t. intuition (subst; auto).
- contradiction.
Qed.
Theorem In_map_iff :
forall (f:N -> A -> B) (t:avl_tree A) (b:B) (k:N),
In (k, b) (avl_map f t) <-> exists a : A, b = f k a /\ In (k,a) t.
Proof.
intros f t b k. induction t as [tb tl tlIH [tk tv] tr trIH|].
- simpl in *. rewrite tlIH. rewrite trIH. rewrite invert_tuple_eq.
split.
+ destruct 1 as [H|[H|H]]; destruct H; subst; intuition eauto.
+ destruct 1 as [a H]. rewrite invert_tuple_eq in H. intuition (subst; eauto).
- simpl. split; destruct 1; intuition contradiction.
Qed.
Theorem map_preserve_domain :
forall (t:avl_tree A) (f:N -> A -> B) (k:N),
in_domain k t <-> in_domain k (avl_map f t).
Proof.
pose In_in_domain as T1. pose map_updates_all as T2.
split.
- destruct 1. eauto.
- unfold in_domain. destruct 1 as [v in_map]. apply In_map_iff in in_map as [a H].
intuition eauto.
Qed.
Theorem map_forall_keys :
forall (f:N -> A -> B) (t:avl_tree A) (P:N -> Prop),
forall_keys P t <-> forall_keys P (avl_map f t).
Proof.
intros f t P. induction t as [b l IHl [k v] r IHr|].
- simpl in *. rewrite IHl. rewrite IHr. reflexivity.
- simpl. reflexivity.
Qed.
Theorem map_binary_tree_invariant :
forall (f:N -> A -> B) (t:avl_tree A),
binary_tree_invariant t -> binary_tree_invariant (avl_map f t).
Proof.
intros f t bt_inv_t. induction t as [b l IHl [k v] r IHr|].
- simpl in *. rewrite <- ?map_forall_keys. intuition auto.
- simpl. auto.
Qed.
Theorem map_height_unchanged :
forall (f:N -> A -> B) (t:avl_tree A), avl_height t = avl_height (avl_map f t).
Proof.
intros f t. induction t as [b l IHl [k v] r IHr|].
- simpl in *. congruence.
- auto.
Qed.
Theorem map_balanced_with :
forall (f g:N -> A -> B) (l r:avl_tree A) (b:sign),
balanced_with A b l r <-> balanced_with B b (avl_map f l) (avl_map g r).
Proof.
pose map_height_unchanged as T1.
intros f g l r b. unfold balanced_with. destruct b; split; congruence.
Qed.
Theorem map_balance_correct :
forall (f:N -> A -> B) (t:avl_tree A),
balance_correct t -> balance_correct (avl_map f t).
Proof.
intros f t bal_t. induction t as [b l IHl [k v] r IHr|].
- simpl in *. rewrite <- map_balanced_with. tauto.
- simpl. auto.
Qed.
End Map.
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
module radio_controller_TxTiming
(
clk,
reset,
Tx_swEnable,
TxGain_target,
TxGain_rampGainStep,
TxGain_rampTimeStep,
dly_hwTxEn,
dly_TxStart,
dly_PowerAmpEn,
dly_RampGain,
hw_TxEn,
hw_TxGain,
hw_PAEn,
hw_TxStart
);
input clk;
input reset;
input Tx_swEnable;
input [0:5] TxGain_target;
input [0:3] TxGain_rampGainStep;
input [0:3] TxGain_rampTimeStep;
input [0:7] dly_hwTxEn;
input [0:11] dly_TxStart;
input [0:7] dly_PowerAmpEn;
input [0:7] dly_RampGain;
output hw_TxEn;
output hw_TxStart;
output hw_PAEn;
output [0:5] hw_TxGain;
reg [0:7] GainRamp_clockEn_counter;
reg [0:7] timing_counter;
reg [0:11] timing_counter_big;
wire [0:6] NewTxGain;
reg [0:6] TxGainBig;
wire AutoGainRampEn;
//The output gain signal is the output of an accumulator, enabled after dly_RampGain clock cycles
//This signal is the input to the accumulator register. TxGainBig has one extra MSB to ease overflow detection
assign NewTxGain = ( (TxGainBig + TxGain_rampGainStep) > TxGain_target) ? TxGain_target : (TxGainBig + TxGain_rampGainStep);
//The hw_TxGain output, which eventually connects to the radio's parallel gain control bus,
// gets the 6 LSB of the internal accumulator value
assign hw_TxGain = TxGainBig[1:6];
//Enable the outputs when the timing counter has excedded the various control thresholds given by the dly_* inputs
// A delay value of 254 will hold the corresponding output high forever
// A delay value of 255 will hold the corresponding output low forever (the counter below never reaches 255)
assign hw_TxEn = (timing_counter > dly_hwTxEn) || dly_hwTxEn == 8'd254;
assign hw_PAEn = (timing_counter > dly_PowerAmpEn) || dly_PowerAmpEn == 8'd254;
//TxStart can have a longer delay, up to 2^12 cycles (probably overkill)
// A delay value of 2^12-2 (4094) will hold TxStart high forever
// A delay value of 2^12-1 (4095) will hold TxStart low forever (timing_counter_big never reaches 4095)
assign hw_TxStart = (timing_counter_big > dly_TxStart) || dly_TxStart == 12'd4094;
//Enable the gain ramp accumulator after the given delay
// A delay value of 254 or 255 will disable the gain ramp, regardless of the ramp parameters
assign AutoGainRampEn = timing_counter > dly_RampGain;
//Instiantiates a counter which runs once the timing counter exceeds the threshold
// for starting the ramping of Tx gains; the counter increments every TxGain_rampTimeStep cycles
always @( posedge clk )
begin
if(reset | ~Tx_swEnable)
TxGainBig <= 0;
else if( AutoGainRampEn & (GainRamp_clockEn_counter==1))
TxGainBig <= NewTxGain;
end
//Instantiate a counter that starts when the software enables Tx mode
// This counter intentionally stops at 253, allowing delay values of 254 and 255 to have other uses
always @( posedge clk )
begin
if(reset | ~Tx_swEnable)
timing_counter <= 0;
else if(Tx_swEnable & timing_counter < 254)
timing_counter <= timing_counter + 1;
end
//Instantiate a counter that starts when the software enables Tx mode
// This counter intentionally stops at 4093, allowing delay values of 4094 and 4095 to have other uses
always @( posedge clk )
begin
if(reset | ~Tx_swEnable)
timing_counter_big <= 0;
else if(Tx_swEnable & timing_counter_big < 4094)
timing_counter_big <= timing_counter_big + 1;
end
//Instantiate a counter used to drive the clock enable of the gain ramp counter above
always @( posedge clk )
begin
if(reset | GainRamp_clockEn_counter == TxGain_rampTimeStep)
GainRamp_clockEn_counter <= 0;
else
GainRamp_clockEn_counter <= GainRamp_clockEn_counter + 1;
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// *******************************************************************************************************
// ** **
// ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) **
// ** **
// *******************************************************************************************************
// ** **
// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING **
// ** ALL RIGHTS RESERVED **
// ** **
// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR **
// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS **
// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN **
// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. **
// ** **
// *******************************************************************************************************
// ** Revision : 1.1 **
// ** Modified Date : 07/19/2004 **
// ** Revision History: **
// ** **
// ** 02/01/2003: Initial design **
// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. **
// ** **
// *******************************************************************************************************
// ** TABLE OF CONTENTS **
// *******************************************************************************************************
// **---------------------------------------------------------------------------------------------------**
// ** DECLARATIONS **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** INITIALIZATION **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** CORE LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 1.01: START Bit Detection **
// ** 1.02: STOP Bit Detection **
// ** 1.03: Input Shift Register **
// ** 1.04: Input Bit Counter **
// ** 1.05: Control Byte Register **
// ** 1.06: Byte Address Register **
// ** 1.07: Write Data Buffer **
// ** 1.08: Acknowledge Generator **
// ** 1.09: Acknowledge Detect **
// ** 1.10: Write Cycle Timer **
// ** 1.11: Write Cycle Processor **
// ** 1.12: Read Data Multiplexor **
// ** 1.13: Read Data Processor **
// ** 1.14: SDA Data I/O Buffer **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** DEBUG LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 2.01: Memory Data Bytes **
// ** 2.02: Write Data Buffer **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** TIMING CHECKS **
// **---------------------------------------------------------------------------------------------------**
// ** **
// *******************************************************************************************************
`timescale 1ns/10ps
module M24LC02B (A0, A1, A2, WP, SDA, SCL, RESET);
input A0; // unconnected pin
input A1; // unconnected pin
input A2; // unconnected pin
input WP; // write protect pin
inout SDA; // serial data I/O
input SCL; // serial data clock
input RESET; // system reset
// *******************************************************************************************************
// ** DECLARATIONS **
// *******************************************************************************************************
reg SDA_DO; // serial data - output
reg SDA_OE; // serial data - output enable
wire SDA_DriveEnable; // serial data output enable
reg SDA_DriveEnableDlyd; // serial data output enable - delayed
reg [03:00] BitCounter; // serial bit counter
reg START_Rcvd; // START bit received flag
reg STOP_Rcvd; // STOP bit received flag
reg CTRL_Rcvd; // control byte received flag
reg ADDR_Rcvd; // byte address received flag
reg MACK_Rcvd; // master acknowledge received flag
reg WrCycle; // memory write cycle
reg RdCycle; // memory read cycle
reg [07:00] ShiftRegister; // input data shift register
reg [07:00] ControlByte; // control byte register
wire RdWrBit; // read/write control bit
reg [07:00] StartAddress; // memory access starting address
reg [02:00] PageAddress; // memory page address
reg [07:00] WrDataByte [0:7]; // memory write data buffer
wire [07:00] RdDataByte; // memory read data
reg [15:00] WrCounter; // write buffer counter
reg [02:00] WrPointer; // write buffer pointer
reg [07:00] RdPointer; // read address pointer
reg WriteActive; // memory write cycle active
reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array
integer LoopIndex; // iterative loop index
integer tAA; // timing parameter
integer tWC; // timing parameter
// *******************************************************************************************************
// ** INITIALIZATION **
// *******************************************************************************************************
initial tAA = 900; // SCL to SDA output delay
initial tWC = 5000000; // memory write cycle time
initial begin
SDA_DO = 0;
SDA_OE = 0;
end
initial begin
START_Rcvd = 0;
STOP_Rcvd = 0;
CTRL_Rcvd = 0;
ADDR_Rcvd = 0;
MACK_Rcvd = 0;
end
initial begin
BitCounter = 0;
ControlByte = 0;
end
initial begin
WrCycle = 0;
RdCycle = 0;
WriteActive = 0;
end
// *******************************************************************************************************
// ** CORE LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.01: START Bit Detection
// -------------------------------------------------------------------------------------------------------
always @(negedge SDA) begin
if (SCL == 1) begin
START_Rcvd <= 1;
STOP_Rcvd <= 0;
CTRL_Rcvd <= 0;
ADDR_Rcvd <= 0;
MACK_Rcvd <= 0;
WrCycle <= #1 0;
RdCycle <= #1 0;
BitCounter <= 0;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.02: STOP Bit Detection
// -------------------------------------------------------------------------------------------------------
always @(posedge SDA) begin
if (SCL == 1) begin
START_Rcvd <= 0;
STOP_Rcvd <= 1;
CTRL_Rcvd <= 0;
ADDR_Rcvd <= 0;
MACK_Rcvd <= 0;
WrCycle <= #1 0;
RdCycle <= #1 0;
BitCounter <= 10;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.03: Input Shift Register
// -------------------------------------------------------------------------------------------------------
always @(posedge SCL) begin
ShiftRegister[00] <= SDA;
ShiftRegister[01] <= ShiftRegister[00];
ShiftRegister[02] <= ShiftRegister[01];
ShiftRegister[03] <= ShiftRegister[02];
ShiftRegister[04] <= ShiftRegister[03];
ShiftRegister[05] <= ShiftRegister[04];
ShiftRegister[06] <= ShiftRegister[05];
ShiftRegister[07] <= ShiftRegister[06];
end
// -------------------------------------------------------------------------------------------------------
// 1.04: Input Bit Counter
// -------------------------------------------------------------------------------------------------------
always @(posedge SCL) begin
if (BitCounter < 10) BitCounter <= BitCounter + 1;
end
// -------------------------------------------------------------------------------------------------------
// 1.05: Control Byte Register
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (START_Rcvd & (BitCounter == 8)) begin
if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin
if (ShiftRegister[00] == 0) WrCycle <= 1;
if (ShiftRegister[00] == 1) RdCycle <= 1;
ControlByte <= ShiftRegister[07:00];
CTRL_Rcvd <= 1;
end
START_Rcvd <= 0;
end
end
assign RdWrBit = ControlByte[00];
// -------------------------------------------------------------------------------------------------------
// 1.06: Byte Address Register
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (CTRL_Rcvd & (BitCounter == 8)) begin
if (RdWrBit == 0) begin
StartAddress <= ShiftRegister[07:00];
RdPointer <= ShiftRegister[07:00];
ADDR_Rcvd <= 1;
end
WrCounter <= 0;
WrPointer <= 0;
CTRL_Rcvd <= 0;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.07: Write Data Buffer
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (ADDR_Rcvd & (BitCounter == 8)) begin
if ((WP == 0) & (RdWrBit == 0)) begin
WrDataByte[WrPointer] <= ShiftRegister[07:00];
WrCounter <= WrCounter + 1;
WrPointer <= WrPointer + 1;
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.08: Acknowledge Generator
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (!WriteActive) begin
if (BitCounter == 8) begin
if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin
SDA_DO <= 0;
SDA_OE <= 1;
end
end
if (BitCounter == 9) begin
BitCounter <= 0;
if (!RdCycle) begin
SDA_DO <= 0;
SDA_OE <= 0;
end
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.09: Acknowledge Detect
// -------------------------------------------------------------------------------------------------------
always @(posedge SCL) begin
if (RdCycle & (BitCounter == 8)) begin
if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1;
end
end
always @(negedge SCL) MACK_Rcvd <= 0;
// -------------------------------------------------------------------------------------------------------
// 1.10: Write Cycle Timer
// -------------------------------------------------------------------------------------------------------
always @(posedge STOP_Rcvd) begin
if (WrCycle & (WP == 0) & (WrCounter > 0)) begin
WriteActive = 1;
#(tWC);
WriteActive = 0;
end
end
always @(posedge STOP_Rcvd) begin
#(1.0);
STOP_Rcvd = 0;
end
// -------------------------------------------------------------------------------------------------------
// 1.11: Write Cycle Processor
// -------------------------------------------------------------------------------------------------------
always @(posedge WriteActive) begin
for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin
PageAddress = StartAddress[02:00] + LoopIndex;
MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]];
end
end
// -------------------------------------------------------------------------------------------------------
// 1.12: Read Data Multiplexor
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (BitCounter == 8) begin
if (WrCycle & ADDR_Rcvd) begin
RdPointer <= StartAddress + WrPointer + 1;
end
if (RdCycle) begin
RdPointer <= RdPointer + 1;
end
end
end
assign RdDataByte = MemoryBlock[RdPointer[07:00]];
// -------------------------------------------------------------------------------------------------------
// 1.13: Read Data Processor
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (RdCycle) begin
if (BitCounter == 8) begin
SDA_DO <= 0;
SDA_OE <= 0;
end
else if (BitCounter == 9) begin
SDA_DO <= RdDataByte[07];
if (MACK_Rcvd) SDA_OE <= 1;
end
else begin
SDA_DO <= RdDataByte[7-BitCounter];
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.14: SDA Data I/O Buffer
// -------------------------------------------------------------------------------------------------------
bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd);
assign SDA_DriveEnable = !SDA_DO & SDA_OE;
always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable;
// *******************************************************************************************************
// ** DEBUG LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 2.01: Memory Data Bytes
// -------------------------------------------------------------------------------------------------------
wire [07:00] MemoryByte00 = MemoryBlock[00];
wire [07:00] MemoryByte01 = MemoryBlock[01];
wire [07:00] MemoryByte02 = MemoryBlock[02];
wire [07:00] MemoryByte03 = MemoryBlock[03];
wire [07:00] MemoryByte04 = MemoryBlock[04];
wire [07:00] MemoryByte05 = MemoryBlock[05];
wire [07:00] MemoryByte06 = MemoryBlock[06];
wire [07:00] MemoryByte07 = MemoryBlock[07];
wire [07:00] MemoryByte08 = MemoryBlock[08];
wire [07:00] MemoryByte09 = MemoryBlock[09];
wire [07:00] MemoryByte0A = MemoryBlock[10];
wire [07:00] MemoryByte0B = MemoryBlock[11];
wire [07:00] MemoryByte0C = MemoryBlock[12];
wire [07:00] MemoryByte0D = MemoryBlock[13];
wire [07:00] MemoryByte0E = MemoryBlock[14];
wire [07:00] MemoryByte0F = MemoryBlock[15];
// -------------------------------------------------------------------------------------------------------
// 2.02: Write Data Buffer
// -------------------------------------------------------------------------------------------------------
wire [07:00] WriteData_0 = WrDataByte[00];
wire [07:00] WriteData_1 = WrDataByte[01];
wire [07:00] WriteData_2 = WrDataByte[02];
wire [07:00] WriteData_3 = WrDataByte[03];
wire [07:00] WriteData_4 = WrDataByte[04];
wire [07:00] WriteData_5 = WrDataByte[05];
wire [07:00] WriteData_6 = WrDataByte[06];
wire [07:00] WriteData_7 = WrDataByte[07];
// *******************************************************************************************************
// ** TIMING CHECKS **
// *******************************************************************************************************
wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0);
specify
specparam
tHI = 600, // SCL pulse width - high
tLO = 1300, // SCL pulse width - low
tSU_STA = 600, // SCL to SDA setup time
tHD_STA = 600, // SCL to SDA hold time
tSU_DAT = 100, // SDA to SCL setup time
tSU_STO = 600; // SCL to SDA setup time
$width (posedge SCL, tHI);
$width (negedge SCL, tLO);
$setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA);
$setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT);
$setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO);
$hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA);
endspecify
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
//-----------------------------------------------------------------
// Module - Instruction Cache
//-----------------------------------------------------------------
module altor32_icache
(
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
// Processor interface
input rd_i /*verilator public*/,
input [31:0] pc_i /*verilator public*/,
output [31:0] instruction_o /*verilator public*/,
output valid_o /*verilator public*/,
input invalidate_i /*verilator public*/,
// Memory interface
output [31:0] wbm_addr_o /*verilator public*/,
input [31:0] wbm_dat_i /*verilator public*/,
output [2:0] wbm_cti_o /*verilator public*/,
output wbm_cyc_o /*verilator public*/,
output wbm_stb_o /*verilator public*/,
input wbm_stall_i/*verilator public*/,
input wbm_ack_i/*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter BOOT_VECTOR = 32'h00000000;
// Option: Number of ways (supports 1 or 2)
parameter CACHE_NUM_WAYS = 1;
// Option: Number of cache lines (2^param) * line_size_bytes = cache size
parameter CACHE_LINE_ADDR_WIDTH = 8 - (CACHE_NUM_WAYS-1); /* 256 lines total across all ways */
parameter CACHE_LINE_SIZE_WIDTH = 5; /* 5-bits -> 32 entries */
parameter CACHE_LINE_SIZE_BYTES = 2 ** CACHE_LINE_SIZE_WIDTH; /* 32 bytes / 8 words per line */
parameter CACHE_TAG_ENTRIES = 2 ** CACHE_LINE_ADDR_WIDTH ; /* 128 tag entries */
parameter CACHE_DSIZE = CACHE_NUM_WAYS * (2 ** CACHE_LINE_ADDR_WIDTH) * CACHE_LINE_SIZE_BYTES; /* 8KB data */
parameter CACHE_DWIDTH = CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 2; /* 10-bits */
parameter CACHE_TAG_WIDTH = 16; /* 16-bit tag entry size */
parameter CACHE_TAG_STAT_BITS = 1 + (CACHE_NUM_WAYS-1);
parameter CACHE_TAG_LINE_ADDR_WIDTH = CACHE_TAG_WIDTH - CACHE_TAG_STAT_BITS; /* 15 bits of data (tag entry size minus valid / LRU bit) */
parameter CACHE_TAG_ADDR_LOW = CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH;
parameter CACHE_TAG_ADDR_HIGH = CACHE_TAG_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH + CACHE_LINE_ADDR_WIDTH - 1;
// Tag fields
parameter CACHE_TAG_VALID_BIT = 15;
parameter CACHE_TAG_LRU_BIT = 14; // If CACHE_NUM_WAYS > 1
parameter CACHE_TAG_ADDR_BITS = CACHE_TAG_WIDTH - CACHE_TAG_STAT_BITS;
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// |--------------| | | | | | | | | | | | | | | | |
// +-----------------+ +-------------------+ +-----------+
// Tag entry Line address Address
// (14/15-bits) (7/8-bits) within line
// (5-bits)
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// Tag read / write data
reg tag_wr_r;
wire [CACHE_TAG_WIDTH-1:0] tag_out0_w;
reg [CACHE_TAG_WIDTH-1:0] tag_in0_r;
wire [CACHE_TAG_WIDTH-1:0] tag_out1_w;
reg [CACHE_TAG_WIDTH-1:0] tag_in1_r;
// Tag address
wire [CACHE_LINE_ADDR_WIDTH-1:0] tag_address_w;
// Data memory read / write
wire [CACHE_DWIDTH-1:0] address_rd_w;
wire [CACHE_DWIDTH-1:0] address_wr_w;
wire cache_wr0_w;
wire cache_wr1_w;
reg way_update_q;
// Current / Miss PC
reg [31:0] last_pc_q;
reg [31:0] miss_pc_q;
// Flush state
reg flush_q;
reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr_q;
reg flush_wr_q;
// Other state
reg read_while_busy_q;
// Current state
parameter STATE_CHECK = 0;
parameter STATE_FETCH = 1;
parameter STATE_WAIT = 2;
parameter STATE_FLUSH = 3;
reg [1:0] state_q;
// Tag address from input PC or flopped version of it
assign tag_address_w = (state_q != STATE_CHECK) ?
miss_pc_q[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] :
pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
// Cache read address
assign address_rd_w = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
// Cache miss output if requested PC is not in the tag memory
wire miss0_w = ~tag_out0_w[CACHE_TAG_VALID_BIT] |
(last_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_out0_w[CACHE_TAG_ADDR_BITS-1:0]);
wire miss1_w = ~tag_out1_w[CACHE_TAG_VALID_BIT] |
(last_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_out1_w[CACHE_TAG_ADDR_BITS-1:0]);
// Stall the CPU if cache state machine is not idle!
wire busy_w = (state_q != STATE_CHECK) | read_while_busy_q;
// Cache output valid
assign valid_o = busy_w ? 1'b0 : ~(miss0_w & miss1_w);
// Flushing: Last line to flush
wire flush_last_w = (flush_addr_q == {CACHE_LINE_ADDR_WIDTH{1'b0}});
// Is this a cache miss?
wire cache_miss_w = miss0_w & miss1_w & // Tag lookup failed
!rd_i & // NOT new read request cycle
!read_while_busy_q & // NOT pending read whilst busy
!flush_q & // NOT flush request
!invalidate_i;
wire mem_fetch_w = (state_q == STATE_CHECK) & cache_miss_w;
wire [31:0] mem_data_w;
wire [31:0] mem_resp_addr_w;
wire mem_valid_w;
wire mem_final_w;
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
reg [1:0] next_state_r;
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// CHECK - check cache for hit or miss
//-----------------------------------------
STATE_CHECK :
begin
// Cache flush request pending?
if (flush_q || invalidate_i)
next_state_r = STATE_FLUSH;
// Cache miss (& new read request not pending)
else if (cache_miss_w)
next_state_r = STATE_FETCH;
// Cache hit (or new read request)
else
next_state_r = STATE_CHECK;
end
//-----------------------------------------
// FETCH - Fetch row from memory
//-----------------------------------------
STATE_FETCH :
begin
// Line fetch complete?
if (mem_final_w)
next_state_r = STATE_WAIT;
end
//-----------------------------------------
// FLUSH - Invalidate tag memory
//-----------------------------------------
STATE_FLUSH :
begin
if (flush_last_w)
next_state_r = STATE_CHECK;
else
next_state_r = STATE_FLUSH;
end
//-----------------------------------------
// WAIT - Wait cycle
//-----------------------------------------
STATE_WAIT :
next_state_r = STATE_CHECK;
default:
;
endcase
end
// Update state
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
state_q <= STATE_FLUSH;
else
state_q <= next_state_r;
end
//-----------------------------------------------------------------
// Select way to be replaced
//-----------------------------------------------------------------
reg lru_way_r;
// 2-Way
generate
if (CACHE_NUM_WAYS >= 2)
begin: LRU_SELECT
always @ *
begin
if (tag_out0_w[CACHE_TAG_LRU_BIT])
lru_way_r = 1'b0;
else
lru_way_r = 1'b1;
end
end
// 1-Way
else
begin: LRU_FIXED
wire lru_way_w = 1'b0;
always @ *
lru_way_r = lru_way_w;
end
endgenerate
//-----------------------------------------------------------------
// Flop request details
//-----------------------------------------------------------------
reg [CACHE_LINE_ADDR_WIDTH-1:0] tag_address_q;
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
miss_pc_q <= BOOT_VECTOR + `VECTOR_RESET;
last_pc_q <= 32'h00000000;
tag_address_q <= {CACHE_LINE_ADDR_WIDTH{1'b0}};
way_update_q <= 1'b0;
end
else
begin
last_pc_q <= pc_i;
tag_address_q <= tag_address_w;
case (state_q)
//-----------------------------------------
// CHECK - check cache for hit or miss
//-----------------------------------------
STATE_CHECK :
begin
// Cache hit (or new read request), store fetch PC
if (!cache_miss_w)
begin
miss_pc_q <= pc_i;
end
// Cache miss
else
begin
// Select line way to replace
way_update_q <= lru_way_r;
end
end
default:
;
endcase
end
end
//-----------------------------------------------------------------
// Detect new read request whilst busy
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
read_while_busy_q <= 1'b0;
end
else
begin
case (state_q)
//-----------------------------------------
// CHECK - Check cache for hit or miss
//-----------------------------------------
STATE_CHECK :
begin
read_while_busy_q <= 1'b0;
end
//-----------------------------------------
// OTHER - Fetching, flushing, waiting
//-----------------------------------------
default:
begin
// New request whilst cache busy?
if (rd_i)
read_while_busy_q <= 1'b1;
end
endcase
end
end
//-----------------------------------------------------------------
// Cache Tag Write
//-----------------------------------------------------------------
always @ *
begin
tag_in0_r = tag_out0_w;
tag_in1_r = tag_out1_w;
tag_wr_r = 1'b0;
case (state_q)
//-----------------------------------------
// CHECK - check cache for hit or miss
//-----------------------------------------
STATE_CHECK :
begin
// Cache miss (& new read request not pending)
if (cache_miss_w)
begin
// Update tag memory with this line's details
if (lru_way_r)
begin
tag_in1_r[CACHE_TAG_ADDR_BITS-1:0] = miss_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW];
tag_in1_r[CACHE_TAG_VALID_BIT] = 1'b1;
if (CACHE_NUM_WAYS >= 2)
begin
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b0;
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b1;
end
end
else
begin
tag_in0_r[CACHE_TAG_ADDR_BITS-1:0] = miss_pc_q[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW];
tag_in0_r[CACHE_TAG_VALID_BIT] = 1'b1;
if (CACHE_NUM_WAYS >= 2)
begin
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b0;
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b1;
end
end
tag_wr_r = 1'b1;
end
// Update LRU (if possible)
else if ((tag_address_q == tag_address_w) && (CACHE_NUM_WAYS >= 2))
begin
// Hit Way 0
if (!miss0_w)
begin
// Least recently used way is 1
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b1;
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b0;
end
// Hit Way 1
else
begin
// Least recently used way is 0
tag_in0_r[CACHE_TAG_LRU_BIT] = 1'b1;
tag_in1_r[CACHE_TAG_LRU_BIT] = 1'b0;
end
tag_wr_r = 1'b1;
end
end
default:
;
endcase
end
//-----------------------------------------------------------------
// Flush Logic
//-----------------------------------------------------------------
reg flush_r;
reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr_r;
reg flush_wr_r;
always @ *
begin
flush_wr_r = 1'b0;
flush_addr_r = flush_addr_q;
flush_r = flush_q;
case (state_q)
//-----------------------------------------
// CHECK - Check cache for hit or miss
//-----------------------------------------
STATE_CHECK :
begin
// Cache flush request pending?
if (flush_q || invalidate_i)
begin
flush_r = 1'b0;
flush_addr_r = {CACHE_LINE_ADDR_WIDTH{1'b1}};
flush_wr_r = 1'b1;
end
end
//-----------------------------------------
// FLUSH - Invalidate tag memory
//-----------------------------------------
STATE_FLUSH :
begin
flush_addr_r = flush_addr_q - 1;
flush_wr_r = 1'b1;
end
//-----------------------------------------
// OTHER - Fetching / wait cycles
//-----------------------------------------
default:
begin
// Latch invalidate request even if can't be actioned now...
if (invalidate_i)
flush_r = 1'b1;
end
endcase
end
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
flush_addr_q <= {CACHE_LINE_ADDR_WIDTH{1'b1}};
flush_wr_q <= 1'b0;
flush_q <= 1'b0;
end
else
begin
flush_addr_q <= flush_addr_r;
flush_wr_q <= flush_wr_r;
flush_q <= flush_r;
end
end
//-----------------------------------------------------------------
// External Mem Access
//-----------------------------------------------------------------
altor32_wb_fetch
u_wb
(
.clk_i(clk_i),
.rst_i(rst_i),
// Request
.fetch_i(mem_fetch_w),
.burst_i(1'b1),
.address_i(miss_pc_q),
// Response
.resp_addr_o(mem_resp_addr_w),
.data_o(mem_data_w),
.valid_o(mem_valid_w),
.final_o(mem_final_w),
// Wishbone interface
.wbm_addr_o(wbm_addr_o),
.wbm_dat_i(wbm_dat_i),
.wbm_cti_o(wbm_cti_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_stall_i(wbm_stall_i),
.wbm_ack_i(wbm_ack_i)
);
//-----------------------------------------------------------------
// Tag memory
//-----------------------------------------------------------------
wire [(CACHE_NUM_WAYS*CACHE_TAG_WIDTH)-1:0] tag_in;
wire [(CACHE_NUM_WAYS*CACHE_TAG_WIDTH)-1:0] tag_out;
altor32_ram_dp
#(
.WIDTH(CACHE_TAG_WIDTH * CACHE_NUM_WAYS),
.SIZE(CACHE_LINE_ADDR_WIDTH)
)
u_tag_mem
(
// Tag read/write port
.aclk_i(clk_i),
.adat_o(tag_out),
.adat_i(tag_in),
.aadr_i(tag_address_w),
.awr_i(tag_wr_r),
// Tag invalidate port
.bclk_i(clk_i),
.badr_i(flush_addr_q),
.bdat_o(/*open*/),
.bdat_i({(CACHE_NUM_WAYS*CACHE_TAG_WIDTH){1'b0}}),
.bwr_i(flush_wr_q)
);
// 2-Way
generate
if (CACHE_NUM_WAYS >= 2)
begin: TAG_2WAY
assign tag_in = {tag_in1_r, tag_in0_r};
assign {tag_out1_w, tag_out0_w} = tag_out;
end
// 1-Way
else
begin: TAG_1WAY
assign tag_in = tag_in0_r;
assign tag_out0_w = tag_out;
assign tag_out1_w = {(CACHE_TAG_WIDTH){1'b0}};
end
endgenerate
//-----------------------------------------------------------------
// Data memory
//-----------------------------------------------------------------
wire [31:0] way0_instruction_w /*verilator public*/;
wire [31:0] way1_instruction_w /*verilator public*/;
// Way 0 Instruction Memory
altor32_ram_dp
#(
.WIDTH(32),
.SIZE(CACHE_DWIDTH)
)
u2_data_way0
(
// Data read port
.aclk_i(clk_i),
.aadr_i(address_rd_w),
.adat_o(way0_instruction_w),
.adat_i(32'h00),
.awr_i(1'b0),
// Data write port
.bclk_i(clk_i),
.badr_i(address_wr_w),
.bdat_o(/*open*/),
.bdat_i(mem_data_w),
.bwr_i(cache_wr0_w)
);
// Way 1 Instruction Memory
altor32_ram_dp
#(
.WIDTH(32),
.SIZE(CACHE_DWIDTH)
)
u2_data_way1
(
// Data read port
.aclk_i(clk_i),
.aadr_i(address_rd_w),
.adat_o(way1_instruction_w),
.adat_i(32'h00),
.awr_i(1'b0),
// Data write port
.bclk_i(clk_i),
.badr_i(address_wr_w),
.bdat_o(/*open*/),
.bdat_i(mem_data_w),
.bwr_i(cache_wr1_w)
);
// Select between ways for result
assign instruction_o = (miss0_w == 1'b0) ? way0_instruction_w : way1_instruction_w;
// Write to cache on wishbone response
assign address_wr_w = {miss_pc_q[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH], mem_resp_addr_w[CACHE_LINE_SIZE_WIDTH-1:2]};
assign cache_wr0_w = (state_q == STATE_FETCH) & mem_valid_w & ~way_update_q;
assign cache_wr1_w = (state_q == STATE_FETCH) & mem_valid_w & way_update_q;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module title3 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("title3.mif"),
.C_INIT_FILE("title3.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(3725),
.C_READ_DEPTH_A(3725),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(3725),
.C_READ_DEPTH_B(3725),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.822999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v2_3_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
module top;
reg passed = 1'b1;
wire out, cout0, cout1;
reg sel, in_1, in_0;
reg pout;
`ifdef __ICARUS__
// This is technically incorrect for 1'bz inputs. The standard
// states that we should produce 1'bx for that case (idiotic)!
localparam zz_blend = 1'bz;
`else
localparam zz_blend = 1'bx;
`endif
assign cout0 = sel ? 1'bz : in_0;
assign cout1 = sel ? in_1: 1'bz;
assign out = sel ? in_1: in_0;
task automatic check;
input bit, in_1, in_0;
input [63:0] comment;
begin
if (sel === 1'b1) begin
if (bit !== in_1) begin
$display("FAILED: %0s sel = 1'b1, expected %b, got %b",
comment, in_1, bit);
passed = 1'b0;
end
end else if (sel === 1'b0) begin
if (bit !== in_0) begin
$display("FAILED: %0s sel = 1'b0, expected %b, got %b",
comment, in_0, bit);
passed = 1'b0;
end
end else begin
if (in_0 === 1'bz && in_1 === 1'bz && bit !== zz_blend) begin
$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
comment, in_0, zz_blend, bit);
passed = 1'b0;
end else if (in_0 === in_1 && in_0 !== bit) begin
$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
comment, in_0, in_0, bit);
passed = 1'b0;
end else if (in_0 !== in_1 && bit !== 1'bx) begin
$display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
comment, in_1, in_0, bit);
passed = 1'b0;
end
end
end
endtask
// Check the 1 case as a constant Z
always @(cout0) begin
check(cout0, 1'bz, in_0, "CZ 1");
end
// Check the 0 case as a constant Z
always @(cout1) begin
check(cout1, in_1, 1'bz, "CZ 0");
end
// Check the continuous assign
always @(out) begin
check(out, in_1, in_0, "CA");
end
// Check procedural assign.
always @(sel, in_1, in_0) begin
check(sel ? in_1 : in_0, in_1, in_0, "PR");
end
initial begin
#1 sel = 1'b1;
#1 in_1 = 1'b0;
#1 in_1 = 1'b1;
#1 in_1 = 1'bz;
#1 in_1 = 1'bx;
#1 sel = 1'b0;
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bx;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bz;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 if (passed) $display("PASSED");
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// DCFIFO_64x16_DR for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Dual clock distributed ram FIFO (64 width, 16 depth) wrapper
// Module Name: DCFIFO_64x16_DR
// File Name: DCFIFO_64x16_DR.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DCFIFO_64x16_DR
(
input iWClock ,
input iWReset ,
input [63:0] iPushData ,
input iPushEnable ,
output oIsFull ,
input iRClock ,
input iRReset ,
output [63:0] oPopData ,
input iPopEnable ,
output oIsEmpty
);
DPBDCFIFO64x16DR
Inst_DPBDCFIFO64x16DR
(
.wr_clk (iWClock ),
.wr_rst (iWReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.rd_clk (iRClock ),
.rd_rst (iRReset ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty )
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of all IC blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_ic_top.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Instruction cache top
//
module or1200_ic_top(
// Rst, clk and clock control
clk, rst,
// External i/f
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o,
icbiu_sel_o, icbiu_cab_o, icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
// Internal i/f
ic_en,
icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i, icqmem_sel_i, icqmem_tag_i,
icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPRs
spr_cs, spr_write, spr_dat_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External I/F
//
output [dw-1:0] icbiu_dat_o;
output [31:0] icbiu_adr_o;
output icbiu_cyc_o;
output icbiu_stb_o;
output icbiu_we_o;
output [3:0] icbiu_sel_o;
output icbiu_cab_o;
input [dw-1:0] icbiu_dat_i;
input icbiu_ack_i;
input icbiu_err_i;
//
// Internal I/F
//
input ic_en;
input [31:0] icqmem_adr_i;
input icqmem_cycstb_i;
input icqmem_ci_i;
input [3:0] icqmem_sel_i;
input [3:0] icqmem_tag_i;
output [dw-1:0] icqmem_dat_o;
output icqmem_ack_o;
output icqmem_rty_o;
output icqmem_err_o;
output [3:0] icqmem_tag_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_dat_i;
//
// Internal wires and regs
//
wire tag_v;
wire [`OR1200_ICTAG_W-2:0] tag;
wire [dw-1:0] to_icram;
wire [dw-1:0] from_icram;
wire [31:0] saved_addr;
wire [3:0] icram_we;
wire ictag_we;
wire [31:0] ic_addr;
wire icfsm_biu_read;
/* verilator lint_off UNOPTFLAT */
reg tagcomp_miss;
/* verilator lint_on UNOPTFLAT */
wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
wire ictag_en;
wire ictag_v;
wire ic_inv;
wire icfsm_first_hit_ack;
wire icfsm_first_miss_ack;
wire icfsm_first_miss_err;
wire icfsm_burst;
wire icfsm_tag_we;
reg ic_inv_q;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
//
// Simple assignments
//
assign icbiu_adr_o = ic_addr;
assign ic_inv = spr_cs & spr_write;
assign ictag_we = icfsm_tag_we | ic_inv;
assign ictag_addr = ic_inv ?
spr_dat_i[`OR1200_ICINDXH:`OR1200_ICLS] :
ic_addr[`OR1200_ICINDXH:`OR1200_ICLS];
assign ictag_en = ic_inv | ic_en;
assign ictag_v = ~ic_inv;
//
// Data to BIU is from ICRAM when IC is enabled or from LSU when
// IC is disabled
//
assign icbiu_dat_o = 32'h00000000;
//
// Bypases of the IC when IC is disabled
//
assign icbiu_cyc_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_stb_o = (ic_en) ? icfsm_biu_read : icqmem_cycstb_i;
assign icbiu_we_o = 1'b0;
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icqmem_sel_i;
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
assign icqmem_rty_o = ~icqmem_ack_o & ~icqmem_err_o;
assign icqmem_tag_o = icqmem_err_o ? `OR1200_ITAG_BE : icqmem_tag_i;
//
// CPU normal and error termination
//
assign icqmem_ack_o = ic_en ? (icfsm_first_hit_ack | icfsm_first_miss_ack) : icbiu_ack_i;
assign icqmem_err_o = ic_en ? icfsm_first_miss_err : icbiu_err_i;
//
// Select between claddr generated by IC FSM and addr[3:2] generated by LSU
//
assign ic_addr = (icfsm_biu_read) ? saved_addr : icqmem_adr_i;
//
// Select between input data generated by LSU or by BIU
//
assign to_icram = icbiu_dat_i;
//
// Select between data generated by ICRAM or passed by BIU
//
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
//
// Detect falling edge of IC invalidate signal
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst==`OR1200_RST_VALUE)
ic_inv_q <= 1'b0;
else
ic_inv_q <= ic_inv;
//
// Tag comparison
//
// During line invalidate, ensure it stays the same
always @(tag or saved_addr or tag_v) begin
if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
tagcomp_miss = 1'b1;
else
tagcomp_miss = 1'b0;
end
//
// Instantiation of IC Finite State Machine
//
or1200_ic_fsm or1200_ic_fsm(
.clk(clk),
.rst(rst),
.ic_en(ic_en),
.icqmem_cycstb_i(icqmem_cycstb_i),
.icqmem_ci_i(icqmem_ci_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(icbiu_ack_i),
.biudata_error(icbiu_err_i),
.start_addr(icqmem_adr_i),
.saved_addr(saved_addr),
.icram_we(icram_we),
.biu_read(icfsm_biu_read),
.first_hit_ack(icfsm_first_hit_ack),
.first_miss_ack(icfsm_first_miss_ack),
.first_miss_err(icfsm_first_miss_err),
.burst(icfsm_burst),
.tag_we(icfsm_tag_we)
);
//
// Instantiation of IC main memory
//
or1200_ic_ram or1200_ic_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ic_addr[`OR1200_ICINDXH:2]),
.en(ic_en),
.we(icram_we),
.datain(to_icram),
.dataout(from_icram)
);
//
// Instantiation of IC TAG memory
//
or1200_ic_tag or1200_ic_tag(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(ictag_addr),
.en(ictag_en),
.we(ictag_we),
.datain({ic_addr[31:`OR1200_ICTAGL], ictag_v}),
.tag_v(tag_v),
.tag(tag)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_SYMBOL_V
`define SKY130_FD_SC_HDLL__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_4_V
`define SKY130_FD_SC_HS__OR4BB_4_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4bb_4 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4bb_4 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_4_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module erosion_basic_block_0
(
input clock,
input resetn,
input start,
input [31:0] input_iterations,
input valid_in,
output stall_out,
output valid_out,
input stall_in,
output lvb_bb0_cmp6,
input [31:0] workgroup_size
);
// Values used for debugging. These are swept away by synthesis.
wire _entry;
wire _exit;
reg [31:0] _num_entry_NO_SHIFT_REG;
reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;
assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
_num_entry_NO_SHIFT_REG <= 32'h0;
_num_exit_NO_SHIFT_REG <= 32'h0;
end
else
begin
if (_entry)
begin
_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
end
if (_exit)
begin
_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
end
end
end
// This section defines the behaviour of the MERGE node
wire merge_node_stall_in_0;
reg merge_node_valid_out_0_NO_SHIFT_REG;
wire merge_node_stall_in_1;
reg merge_node_valid_out_1_NO_SHIFT_REG;
wire merge_stalled_by_successors;
reg merge_block_selector_NO_SHIFT_REG;
reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
reg invariant_valid_NO_SHIFT_REG;
assign merge_stalled_by_successors = ((merge_node_stall_in_0 & merge_node_valid_out_0_NO_SHIFT_REG) | (merge_node_stall_in_1 & merge_node_valid_out_1_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;
always @(*)
begin
if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
end
else
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
begin
if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
end
end
else
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (~(merge_stalled_by_successors))
begin
merge_node_valid_out_0_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
merge_node_valid_out_1_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
end
else
begin
if (~(merge_node_stall_in_0))
begin
merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
end
if (~(merge_node_stall_in_1))
begin
merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
end
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
invariant_valid_NO_SHIFT_REG <= 1'b0;
end
else
begin
invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
end
end
// This section implements a registered operation.
//
wire local_bb0_cmp6_inputs_ready;
reg local_bb0_cmp6_wii_reg_NO_SHIFT_REG;
reg local_bb0_cmp6_valid_out_NO_SHIFT_REG;
wire local_bb0_cmp6_stall_in;
wire local_bb0_cmp6_output_regs_ready;
reg local_bb0_cmp6_NO_SHIFT_REG;
wire local_bb0_cmp6_causedstall;
assign local_bb0_cmp6_inputs_ready = merge_node_valid_out_0_NO_SHIFT_REG;
assign local_bb0_cmp6_output_regs_ready = (~(local_bb0_cmp6_wii_reg_NO_SHIFT_REG) & (&(~(local_bb0_cmp6_valid_out_NO_SHIFT_REG) | ~(local_bb0_cmp6_stall_in))));
assign merge_node_stall_in_0 = (~(local_bb0_cmp6_wii_reg_NO_SHIFT_REG) & (~(local_bb0_cmp6_output_regs_ready) | ~(local_bb0_cmp6_inputs_ready)));
assign local_bb0_cmp6_causedstall = (local_bb0_cmp6_inputs_ready && (~(local_bb0_cmp6_output_regs_ready) && !(~(local_bb0_cmp6_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb0_cmp6_NO_SHIFT_REG <= 'x;
local_bb0_cmp6_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (start)
begin
local_bb0_cmp6_NO_SHIFT_REG <= 'x;
local_bb0_cmp6_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb0_cmp6_output_regs_ready)
begin
local_bb0_cmp6_NO_SHIFT_REG <= (input_iterations == 32'h0);
local_bb0_cmp6_valid_out_NO_SHIFT_REG <= local_bb0_cmp6_inputs_ready;
end
else
begin
if (~(local_bb0_cmp6_stall_in))
begin
local_bb0_cmp6_valid_out_NO_SHIFT_REG <= local_bb0_cmp6_wii_reg_NO_SHIFT_REG;
end
end
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb0_cmp6_wii_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (start)
begin
local_bb0_cmp6_wii_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb0_cmp6_inputs_ready)
begin
local_bb0_cmp6_wii_reg_NO_SHIFT_REG <= 1'b1;
end
end
end
end
// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
reg branch_node_valid_out_NO_SHIFT_REG;
wire branch_var__output_regs_ready;
wire combined_branch_stall_in_signal;
reg lvb_bb0_cmp6_reg_NO_SHIFT_REG;
assign branch_var__inputs_ready = (local_bb0_cmp6_valid_out_NO_SHIFT_REG & merge_node_valid_out_1_NO_SHIFT_REG);
assign branch_var__output_regs_ready = (~(stall_in) | ~(branch_node_valid_out_NO_SHIFT_REG));
assign local_bb0_cmp6_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign merge_node_stall_in_1 = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign lvb_bb0_cmp6 = lvb_bb0_cmp6_reg_NO_SHIFT_REG;
assign valid_out = branch_node_valid_out_NO_SHIFT_REG;
assign combined_branch_stall_in_signal = stall_in;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
branch_node_valid_out_NO_SHIFT_REG <= 1'b0;
lvb_bb0_cmp6_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (branch_var__output_regs_ready)
begin
branch_node_valid_out_NO_SHIFT_REG <= branch_var__inputs_ready;
lvb_bb0_cmp6_reg_NO_SHIFT_REG <= local_bb0_cmp6_NO_SHIFT_REG;
end
else
begin
if (~(combined_branch_stall_in_signal))
begin
branch_node_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module erosion_basic_block_1
(
input clock,
input resetn,
input [63:0] input_img_in,
input [63:0] input_img_out,
input [31:0] input_iterations,
input input_wii_cmp6,
input valid_in_0,
output stall_out_0,
input input_forked_0,
input valid_in_1,
output stall_out_1,
input input_forked_1,
output valid_out_0,
input stall_in_0,
output valid_out_1,
input stall_in_1,
input [31:0] workgroup_size,
input start,
input feedback_valid_in_55,
output feedback_stall_out_55,
input [3:0] feedback_data_in_55,
input feedback_valid_in_0,
output feedback_stall_out_0,
input feedback_data_in_0,
input feedback_valid_in_1,
output feedback_stall_out_1,
input feedback_data_in_1,
output acl_pipelined_valid,
input acl_pipelined_stall,
output acl_pipelined_exiting_valid,
output acl_pipelined_exiting_stall,
input feedback_valid_in_53,
output feedback_stall_out_53,
input [3:0] feedback_data_in_53,
input feedback_valid_in_52,
output feedback_stall_out_52,
input [63:0] feedback_data_in_52,
output feedback_valid_out_53,
input feedback_stall_in_53,
output [3:0] feedback_data_out_53,
output feedback_valid_out_0,
input feedback_stall_in_0,
output feedback_data_out_0,
output feedback_valid_out_52,
input feedback_stall_in_52,
output [63:0] feedback_data_out_52,
output feedback_valid_out_55,
input feedback_stall_in_55,
output [3:0] feedback_data_out_55,
input [255:0] avm_local_bb1_ld__readdata,
input avm_local_bb1_ld__readdatavalid,
input avm_local_bb1_ld__waitrequest,
output [29:0] avm_local_bb1_ld__address,
output avm_local_bb1_ld__read,
output avm_local_bb1_ld__write,
input avm_local_bb1_ld__writeack,
output [255:0] avm_local_bb1_ld__writedata,
output [31:0] avm_local_bb1_ld__byteenable,
output [4:0] avm_local_bb1_ld__burstcount,
output local_bb1_ld__active,
input clock2x,
output feedback_valid_out_1,
input feedback_stall_in_1,
output feedback_data_out_1,
input feedback_valid_in_34,
output feedback_stall_out_34,
input [7:0] feedback_data_in_34,
input feedback_valid_in_35,
output feedback_stall_out_35,
input [7:0] feedback_data_in_35,
input feedback_valid_in_33,
output feedback_stall_out_33,
input [7:0] feedback_data_in_33,
input feedback_valid_in_32,
output feedback_stall_out_32,
input [7:0] feedback_data_in_32,
input feedback_valid_in_31,
output feedback_stall_out_31,
input [7:0] feedback_data_in_31,
input feedback_valid_in_30,
output feedback_stall_out_30,
input [7:0] feedback_data_in_30,
input feedback_valid_in_28,
output feedback_stall_out_28,
input [7:0] feedback_data_in_28,
input feedback_valid_in_27,
output feedback_stall_out_27,
input [7:0] feedback_data_in_27,
input feedback_valid_in_26,
output feedback_stall_out_26,
input [7:0] feedback_data_in_26,
input feedback_valid_in_20,
output feedback_stall_out_20,
input [7:0] feedback_data_in_20,
input feedback_valid_in_19,
output feedback_stall_out_19,
input [7:0] feedback_data_in_19,
input feedback_valid_in_21,
output feedback_stall_out_21,
input [7:0] feedback_data_in_21,
input feedback_valid_in_22,
output feedback_stall_out_22,
input [7:0] feedback_data_in_22,
input feedback_valid_in_23,
output feedback_stall_out_23,
input [7:0] feedback_data_in_23,
input feedback_valid_in_24,
output feedback_stall_out_24,
input [7:0] feedback_data_in_24,
input feedback_valid_in_54,
output feedback_stall_out_54,
input [11:0] feedback_data_in_54,
input feedback_valid_in_25,
output feedback_stall_out_25,
input [7:0] feedback_data_in_25,
input feedback_valid_in_29,
output feedback_stall_out_29,
input [7:0] feedback_data_in_29,
output feedback_valid_out_35,
input feedback_stall_in_35,
output [7:0] feedback_data_out_35,
output feedback_valid_out_31,
input feedback_stall_in_31,
output [7:0] feedback_data_out_31,
output feedback_valid_out_30,
input feedback_stall_in_30,
output [7:0] feedback_data_out_30,
output feedback_valid_out_29,
input feedback_stall_in_29,
output [7:0] feedback_data_out_29,
input feedback_valid_in_13,
output feedback_stall_out_13,
input [7:0] feedback_data_in_13,
input feedback_valid_in_14,
output feedback_stall_out_14,
input [7:0] feedback_data_in_14,
input feedback_valid_in_15,
output feedback_stall_out_15,
input [7:0] feedback_data_in_15,
input feedback_valid_in_16,
output feedback_stall_out_16,
input [7:0] feedback_data_in_16,
input feedback_valid_in_17,
output feedback_stall_out_17,
input [7:0] feedback_data_in_17,
input feedback_valid_in_18,
output feedback_stall_out_18,
input [7:0] feedback_data_in_18,
output feedback_valid_out_3,
input feedback_stall_in_3,
output [7:0] feedback_data_out_3,
output feedback_valid_out_18,
input feedback_stall_in_18,
output [7:0] feedback_data_out_18,
output feedback_valid_out_20,
input feedback_stall_in_20,
output [7:0] feedback_data_out_20,
output feedback_valid_out_21,
input feedback_stall_in_21,
output [7:0] feedback_data_out_21,
output feedback_valid_out_22,
input feedback_stall_in_22,
output [7:0] feedback_data_out_22,
input feedback_valid_in_3,
output feedback_stall_out_3,
input [7:0] feedback_data_in_3,
input feedback_valid_in_10,
output feedback_stall_out_10,
input [7:0] feedback_data_in_10,
input feedback_valid_in_8,
output feedback_stall_out_8,
input [7:0] feedback_data_in_8,
input feedback_valid_in_7,
output feedback_stall_out_7,
input [7:0] feedback_data_in_7,
input feedback_valid_in_9,
output feedback_stall_out_9,
input [7:0] feedback_data_in_9,
input feedback_valid_in_12,
output feedback_stall_out_12,
input [7:0] feedback_data_in_12,
input feedback_valid_in_11,
output feedback_stall_out_11,
input [7:0] feedback_data_in_11,
output feedback_valid_out_23,
input feedback_stall_in_23,
output [7:0] feedback_data_out_23,
output feedback_valid_out_12,
input feedback_stall_in_12,
output [7:0] feedback_data_out_12,
output feedback_valid_out_13,
input feedback_stall_in_13,
output [7:0] feedback_data_out_13,
output feedback_valid_out_14,
input feedback_stall_in_14,
output [7:0] feedback_data_out_14,
output feedback_valid_out_15,
input feedback_stall_in_15,
output [7:0] feedback_data_out_15,
output feedback_valid_out_16,
input feedback_stall_in_16,
output [7:0] feedback_data_out_16,
output feedback_valid_out_17,
input feedback_stall_in_17,
output [7:0] feedback_data_out_17,
input feedback_valid_in_40,
output feedback_stall_out_40,
input [7:0] feedback_data_in_40,
input feedback_valid_in_41,
output feedback_stall_out_41,
input [7:0] feedback_data_in_41,
input feedback_valid_in_42,
output feedback_stall_out_42,
input [7:0] feedback_data_in_42,
input feedback_valid_in_36,
output feedback_stall_out_36,
input [7:0] feedback_data_in_36,
input feedback_valid_in_37,
output feedback_stall_out_37,
input [7:0] feedback_data_in_37,
input feedback_valid_in_38,
output feedback_stall_out_38,
input [7:0] feedback_data_in_38,
input feedback_valid_in_39,
output feedback_stall_out_39,
input [7:0] feedback_data_in_39,
input feedback_valid_in_6,
output feedback_stall_out_6,
input [7:0] feedback_data_in_6,
input feedback_valid_in_5,
output feedback_stall_out_5,
input [7:0] feedback_data_in_5,
input feedback_valid_in_4,
output feedback_stall_out_4,
input [7:0] feedback_data_in_4,
output feedback_valid_out_54,
input feedback_stall_in_54,
output [11:0] feedback_data_out_54,
output feedback_valid_out_19,
input feedback_stall_in_19,
output [7:0] feedback_data_out_19,
output feedback_valid_out_9,
input feedback_stall_in_9,
output [7:0] feedback_data_out_9,
output feedback_valid_out_7,
input feedback_stall_in_7,
output [7:0] feedback_data_out_7,
output feedback_valid_out_6,
input feedback_stall_in_6,
output [7:0] feedback_data_out_6,
output feedback_valid_out_8,
input feedback_stall_in_8,
output [7:0] feedback_data_out_8,
output feedback_valid_out_10,
input feedback_stall_in_10,
output [7:0] feedback_data_out_10,
input feedback_valid_in_48,
output feedback_stall_out_48,
input [7:0] feedback_data_in_48,
input feedback_valid_in_43,
output feedback_stall_out_43,
input [7:0] feedback_data_in_43,
input feedback_valid_in_44,
output feedback_stall_out_44,
input [7:0] feedback_data_in_44,
input feedback_valid_in_46,
output feedback_stall_out_46,
input [7:0] feedback_data_in_46,
input feedback_valid_in_47,
output feedback_stall_out_47,
input [7:0] feedback_data_in_47,
input feedback_valid_in_45,
output feedback_stall_out_45,
input [7:0] feedback_data_in_45,
output feedback_valid_out_41,
input feedback_stall_in_41,
output [7:0] feedback_data_out_41,
output feedback_valid_out_42,
input feedback_stall_in_42,
output [7:0] feedback_data_out_42,
output feedback_valid_out_43,
input feedback_stall_in_43,
output [7:0] feedback_data_out_43,
output feedback_valid_out_37,
input feedback_stall_in_37,
output [7:0] feedback_data_out_37,
output feedback_valid_out_38,
input feedback_stall_in_38,
output [7:0] feedback_data_out_38,
output feedback_valid_out_39,
input feedback_stall_in_39,
output [7:0] feedback_data_out_39,
output feedback_valid_out_40,
input feedback_stall_in_40,
output [7:0] feedback_data_out_40,
input feedback_valid_in_49,
output feedback_stall_out_49,
input [7:0] feedback_data_in_49,
input feedback_valid_in_50,
output feedback_stall_out_50,
input [7:0] feedback_data_in_50,
input feedback_valid_in_51,
output feedback_stall_out_51,
input [7:0] feedback_data_in_51,
output feedback_valid_out_49,
input feedback_stall_in_49,
output [7:0] feedback_data_out_49,
output feedback_valid_out_44,
input feedback_stall_in_44,
output [7:0] feedback_data_out_44,
output feedback_valid_out_45,
input feedback_stall_in_45,
output [7:0] feedback_data_out_45,
output feedback_valid_out_47,
input feedback_stall_in_47,
output [7:0] feedback_data_out_47,
output feedback_valid_out_48,
input feedback_stall_in_48,
output [7:0] feedback_data_out_48,
output feedback_valid_out_46,
input feedback_stall_in_46,
output [7:0] feedback_data_out_46,
input feedback_valid_in_2,
output feedback_stall_out_2,
input [7:0] feedback_data_in_2,
output feedback_valid_out_50,
input feedback_stall_in_50,
output [7:0] feedback_data_out_50,
output feedback_valid_out_51,
input feedback_stall_in_51,
output [7:0] feedback_data_out_51,
output feedback_valid_out_36,
input feedback_stall_in_36,
output [7:0] feedback_data_out_36,
output feedback_valid_out_33,
input feedback_stall_in_33,
output [7:0] feedback_data_out_33,
output feedback_valid_out_34,
input feedback_stall_in_34,
output [7:0] feedback_data_out_34,
output feedback_valid_out_32,
input feedback_stall_in_32,
output [7:0] feedback_data_out_32,
output feedback_valid_out_27,
input feedback_stall_in_27,
output [7:0] feedback_data_out_27,
output feedback_valid_out_26,
input feedback_stall_in_26,
output [7:0] feedback_data_out_26,
output feedback_valid_out_25,
input feedback_stall_in_25,
output [7:0] feedback_data_out_25,
output feedback_valid_out_28,
input feedback_stall_in_28,
output [7:0] feedback_data_out_28,
output feedback_valid_out_24,
input feedback_stall_in_24,
output [7:0] feedback_data_out_24,
output feedback_valid_out_11,
input feedback_stall_in_11,
output [7:0] feedback_data_out_11,
output feedback_valid_out_5,
input feedback_stall_in_5,
output [7:0] feedback_data_out_5,
output feedback_valid_out_4,
input feedback_stall_in_4,
output [7:0] feedback_data_out_4,
output feedback_valid_out_2,
input feedback_stall_in_2,
output [7:0] feedback_data_out_2,
input [255:0] avm_local_bb1_st_c0_exe1_readdata,
input avm_local_bb1_st_c0_exe1_readdatavalid,
input avm_local_bb1_st_c0_exe1_waitrequest,
output [29:0] avm_local_bb1_st_c0_exe1_address,
output avm_local_bb1_st_c0_exe1_read,
output avm_local_bb1_st_c0_exe1_write,
input avm_local_bb1_st_c0_exe1_writeack,
output [255:0] avm_local_bb1_st_c0_exe1_writedata,
output [31:0] avm_local_bb1_st_c0_exe1_byteenable,
output [4:0] avm_local_bb1_st_c0_exe1_burstcount,
output local_bb1_st_c0_exe1_active
);
// Values used for debugging. These are swept away by synthesis.
wire _entry;
wire _exit;
reg [31:0] _num_entry_NO_SHIFT_REG;
reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;
assign _entry = ((valid_in_0 & valid_in_1) & ~((stall_out_0 | stall_out_1)));
assign _exit = ((valid_out_0 & valid_out_1) & ~((stall_in_0 | stall_in_1)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
_num_entry_NO_SHIFT_REG <= 32'h0;
_num_exit_NO_SHIFT_REG <= 32'h0;
end
else
begin
if (_entry)
begin
_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
end
if (_exit)
begin
_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
end
end
end
// This section defines the behaviour of the MERGE node
wire merge_node_stall_in_0;
reg merge_node_valid_out_0_NO_SHIFT_REG;
wire merge_node_stall_in_1;
reg merge_node_valid_out_1_NO_SHIFT_REG;
wire merge_node_stall_in_2;
reg merge_node_valid_out_2_NO_SHIFT_REG;
wire merge_node_stall_in_3;
reg merge_node_valid_out_3_NO_SHIFT_REG;
wire merge_node_stall_in_4;
reg merge_node_valid_out_4_NO_SHIFT_REG;
wire merge_stalled_by_successors;
reg merge_block_selector_NO_SHIFT_REG;
reg merge_node_valid_in_0_staging_reg_NO_SHIFT_REG;
reg input_forked_0_staging_reg_NO_SHIFT_REG;
reg local_lvm_forked_NO_SHIFT_REG;
reg merge_node_valid_in_1_staging_reg_NO_SHIFT_REG;
reg input_forked_1_staging_reg_NO_SHIFT_REG;
reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
reg invariant_valid_NO_SHIFT_REG;
assign merge_stalled_by_successors = ((merge_node_stall_in_0 & merge_node_valid_out_0_NO_SHIFT_REG) | (merge_node_stall_in_1 & merge_node_valid_out_1_NO_SHIFT_REG) | (merge_node_stall_in_2 & merge_node_valid_out_2_NO_SHIFT_REG) | (merge_node_stall_in_3 & merge_node_valid_out_3_NO_SHIFT_REG) | (merge_node_stall_in_4 & merge_node_valid_out_4_NO_SHIFT_REG));
assign stall_out_0 = merge_node_valid_in_0_staging_reg_NO_SHIFT_REG;
assign stall_out_1 = merge_node_valid_in_1_staging_reg_NO_SHIFT_REG;
always @(*)
begin
if ((merge_node_valid_in_0_staging_reg_NO_SHIFT_REG | valid_in_0))
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
end
else
begin
if ((merge_node_valid_in_1_staging_reg_NO_SHIFT_REG | valid_in_1))
begin
merge_block_selector_NO_SHIFT_REG = 1'b1;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
end
else
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
input_forked_0_staging_reg_NO_SHIFT_REG <= 'x;
merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= 1'b0;
input_forked_1_staging_reg_NO_SHIFT_REG <= 'x;
merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
begin
if (~(merge_node_valid_in_0_staging_reg_NO_SHIFT_REG))
begin
input_forked_0_staging_reg_NO_SHIFT_REG <= input_forked_0;
merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= valid_in_0;
end
end
else
begin
merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= 1'b0;
end
if (((merge_block_selector_NO_SHIFT_REG != 1'b1) | merge_stalled_by_successors))
begin
if (~(merge_node_valid_in_1_staging_reg_NO_SHIFT_REG))
begin
input_forked_1_staging_reg_NO_SHIFT_REG <= input_forked_1;
merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= valid_in_1;
end
end
else
begin
merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= 1'b0;
end
end
end
always @(posedge clock)
begin
if (~(merge_stalled_by_successors))
begin
case (merge_block_selector_NO_SHIFT_REG)
1'b0:
begin
if (merge_node_valid_in_0_staging_reg_NO_SHIFT_REG)
begin
local_lvm_forked_NO_SHIFT_REG <= input_forked_0_staging_reg_NO_SHIFT_REG;
end
else
begin
local_lvm_forked_NO_SHIFT_REG <= input_forked_0;
end
end
1'b1:
begin
if (merge_node_valid_in_1_staging_reg_NO_SHIFT_REG)
begin
local_lvm_forked_NO_SHIFT_REG <= input_forked_1_staging_reg_NO_SHIFT_REG;
end
else
begin
local_lvm_forked_NO_SHIFT_REG <= input_forked_1;
end
end
default:
begin
end
endcase
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
merge_node_valid_out_2_NO_SHIFT_REG <= 1'b0;
merge_node_valid_out_3_NO_SHIFT_REG <= 1'b0;
merge_node_valid_out_4_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (~(merge_stalled_by_successors))
begin
merge_node_valid_out_0_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
merge_node_valid_out_1_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
merge_node_valid_out_2_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
merge_node_valid_out_3_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
merge_node_valid_out_4_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
end
else
begin
if (~(merge_node_stall_in_0))
begin
merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
end
if (~(merge_node_stall_in_1))
begin
merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
end
if (~(merge_node_stall_in_2))
begin
merge_node_valid_out_2_NO_SHIFT_REG <= 1'b0;
end
if (~(merge_node_stall_in_3))
begin
merge_node_valid_out_3_NO_SHIFT_REG <= 1'b0;
end
if (~(merge_node_stall_in_4))
begin
merge_node_valid_out_4_NO_SHIFT_REG <= 1'b0;
end
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
invariant_valid_NO_SHIFT_REG <= 1'b0;
end
else
begin
invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
end
end
// This section implements a registered operation.
//
wire local_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready;
reg local_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_NO_SHIFT_REG;
wire local_bb1_cleanups_pop55_acl_pop_i4_7_stall_in;
wire local_bb1_cleanups_pop55_acl_pop_i4_7_output_regs_ready;
wire [3:0] local_bb1_cleanups_pop55_acl_pop_i4_7_result;
wire local_bb1_cleanups_pop55_acl_pop_i4_7_fu_valid_out;
wire local_bb1_cleanups_pop55_acl_pop_i4_7_fu_stall_out;
reg [3:0] local_bb1_cleanups_pop55_acl_pop_i4_7_NO_SHIFT_REG;
wire local_bb1_cleanups_pop55_acl_pop_i4_7_causedstall;
acl_pop local_bb1_cleanups_pop55_acl_pop_i4_7_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_lvm_forked_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(4'h7),
.stall_out(local_bb1_cleanups_pop55_acl_pop_i4_7_fu_stall_out),
.valid_in(local_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready),
.valid_out(local_bb1_cleanups_pop55_acl_pop_i4_7_fu_valid_out),
.stall_in(~(local_bb1_cleanups_pop55_acl_pop_i4_7_output_regs_ready)),
.data_out(local_bb1_cleanups_pop55_acl_pop_i4_7_result),
.feedback_in(feedback_data_in_55),
.feedback_valid_in(feedback_valid_in_55),
.feedback_stall_out(feedback_stall_out_55)
);
defparam local_bb1_cleanups_pop55_acl_pop_i4_7_feedback.DATA_WIDTH = 4;
defparam local_bb1_cleanups_pop55_acl_pop_i4_7_feedback.STYLE = "REGULAR";
assign local_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready = merge_node_valid_out_0_NO_SHIFT_REG;
assign local_bb1_cleanups_pop55_acl_pop_i4_7_output_regs_ready = (&(~(local_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_NO_SHIFT_REG) | ~(local_bb1_cleanups_pop55_acl_pop_i4_7_stall_in)));
assign merge_node_stall_in_0 = (local_bb1_cleanups_pop55_acl_pop_i4_7_fu_stall_out | ~(local_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready));
assign local_bb1_cleanups_pop55_acl_pop_i4_7_causedstall = (local_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready && (local_bb1_cleanups_pop55_acl_pop_i4_7_fu_stall_out && !(~(local_bb1_cleanups_pop55_acl_pop_i4_7_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_cleanups_pop55_acl_pop_i4_7_NO_SHIFT_REG <= 'x;
local_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_cleanups_pop55_acl_pop_i4_7_output_regs_ready)
begin
local_bb1_cleanups_pop55_acl_pop_i4_7_NO_SHIFT_REG <= local_bb1_cleanups_pop55_acl_pop_i4_7_result;
local_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_NO_SHIFT_REG <= local_bb1_cleanups_pop55_acl_pop_i4_7_fu_valid_out;
end
else
begin
if (~(local_bb1_cleanups_pop55_acl_pop_i4_7_stall_in))
begin
local_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_keep_going_forked_inputs_ready;
reg local_bb1_keep_going_forked_valid_out_NO_SHIFT_REG;
wire local_bb1_keep_going_forked_stall_in;
wire local_bb1_keep_going_forked_output_regs_ready;
wire local_bb1_keep_going_forked_keep_going;
wire local_bb1_keep_going_forked_fu_valid_out;
wire local_bb1_keep_going_forked_fu_stall_out;
reg local_bb1_keep_going_forked_NO_SHIFT_REG;
wire local_bb1_keep_going_forked_feedback_pipelined;
wire local_bb1_keep_going_forked_causedstall;
acl_pipeline local_bb1_keep_going_forked_pipelined (
.clock(clock),
.resetn(resetn),
.data_in(local_lvm_forked_NO_SHIFT_REG),
.stall_out(local_bb1_keep_going_forked_fu_stall_out),
.valid_in(local_bb1_keep_going_forked_inputs_ready),
.valid_out(local_bb1_keep_going_forked_fu_valid_out),
.stall_in(~(local_bb1_keep_going_forked_output_regs_ready)),
.data_out(local_bb1_keep_going_forked_keep_going),
.initeration_in(feedback_data_in_0),
.initeration_valid_in(feedback_valid_in_0),
.initeration_stall_out(feedback_stall_out_0),
.not_exitcond_in(feedback_data_in_1),
.not_exitcond_valid_in(feedback_valid_in_1),
.not_exitcond_stall_out(feedback_stall_out_1),
.pipeline_valid_out(acl_pipelined_valid),
.pipeline_stall_in(acl_pipelined_stall),
.exiting_valid_out(acl_pipelined_exiting_valid)
);
defparam local_bb1_keep_going_forked_pipelined.FIFO_DEPTH = 2;
defparam local_bb1_keep_going_forked_pipelined.STYLE = "SPECULATIVE";
assign local_bb1_keep_going_forked_inputs_ready = merge_node_valid_out_1_NO_SHIFT_REG;
assign local_bb1_keep_going_forked_output_regs_ready = (&(~(local_bb1_keep_going_forked_valid_out_NO_SHIFT_REG) | ~(local_bb1_keep_going_forked_stall_in)));
assign acl_pipelined_exiting_stall = acl_pipelined_stall;
assign merge_node_stall_in_1 = (local_bb1_keep_going_forked_fu_stall_out | ~(local_bb1_keep_going_forked_inputs_ready));
assign local_bb1_keep_going_forked_causedstall = (local_bb1_keep_going_forked_inputs_ready && (local_bb1_keep_going_forked_fu_stall_out && !(~(local_bb1_keep_going_forked_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_keep_going_forked_NO_SHIFT_REG <= 'x;
local_bb1_keep_going_forked_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_keep_going_forked_output_regs_ready)
begin
local_bb1_keep_going_forked_NO_SHIFT_REG <= local_bb1_keep_going_forked_keep_going;
local_bb1_keep_going_forked_valid_out_NO_SHIFT_REG <= local_bb1_keep_going_forked_fu_valid_out;
end
else
begin
if (~(local_bb1_keep_going_forked_stall_in))
begin
local_bb1_keep_going_forked_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_initerations_pop53_acl_pop_i4_7_inputs_ready;
reg local_bb1_initerations_pop53_acl_pop_i4_7_valid_out_NO_SHIFT_REG;
wire local_bb1_initerations_pop53_acl_pop_i4_7_stall_in;
wire local_bb1_initerations_pop53_acl_pop_i4_7_output_regs_ready;
wire [3:0] local_bb1_initerations_pop53_acl_pop_i4_7_result;
wire local_bb1_initerations_pop53_acl_pop_i4_7_fu_valid_out;
wire local_bb1_initerations_pop53_acl_pop_i4_7_fu_stall_out;
reg [3:0] local_bb1_initerations_pop53_acl_pop_i4_7_NO_SHIFT_REG;
wire local_bb1_initerations_pop53_acl_pop_i4_7_causedstall;
acl_pop local_bb1_initerations_pop53_acl_pop_i4_7_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_lvm_forked_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(4'h7),
.stall_out(local_bb1_initerations_pop53_acl_pop_i4_7_fu_stall_out),
.valid_in(local_bb1_initerations_pop53_acl_pop_i4_7_inputs_ready),
.valid_out(local_bb1_initerations_pop53_acl_pop_i4_7_fu_valid_out),
.stall_in(~(local_bb1_initerations_pop53_acl_pop_i4_7_output_regs_ready)),
.data_out(local_bb1_initerations_pop53_acl_pop_i4_7_result),
.feedback_in(feedback_data_in_53),
.feedback_valid_in(feedback_valid_in_53),
.feedback_stall_out(feedback_stall_out_53)
);
defparam local_bb1_initerations_pop53_acl_pop_i4_7_feedback.DATA_WIDTH = 4;
defparam local_bb1_initerations_pop53_acl_pop_i4_7_feedback.STYLE = "REGULAR";
assign local_bb1_initerations_pop53_acl_pop_i4_7_inputs_ready = merge_node_valid_out_2_NO_SHIFT_REG;
assign local_bb1_initerations_pop53_acl_pop_i4_7_output_regs_ready = (&(~(local_bb1_initerations_pop53_acl_pop_i4_7_valid_out_NO_SHIFT_REG) | ~(local_bb1_initerations_pop53_acl_pop_i4_7_stall_in)));
assign merge_node_stall_in_2 = (local_bb1_initerations_pop53_acl_pop_i4_7_fu_stall_out | ~(local_bb1_initerations_pop53_acl_pop_i4_7_inputs_ready));
assign local_bb1_initerations_pop53_acl_pop_i4_7_causedstall = (local_bb1_initerations_pop53_acl_pop_i4_7_inputs_ready && (local_bb1_initerations_pop53_acl_pop_i4_7_fu_stall_out && !(~(local_bb1_initerations_pop53_acl_pop_i4_7_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_initerations_pop53_acl_pop_i4_7_NO_SHIFT_REG <= 'x;
local_bb1_initerations_pop53_acl_pop_i4_7_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_initerations_pop53_acl_pop_i4_7_output_regs_ready)
begin
local_bb1_initerations_pop53_acl_pop_i4_7_NO_SHIFT_REG <= local_bb1_initerations_pop53_acl_pop_i4_7_result;
local_bb1_initerations_pop53_acl_pop_i4_7_valid_out_NO_SHIFT_REG <= local_bb1_initerations_pop53_acl_pop_i4_7_fu_valid_out;
end
else
begin
if (~(local_bb1_initerations_pop53_acl_pop_i4_7_stall_in))
begin
local_bb1_initerations_pop53_acl_pop_i4_7_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready;
reg local_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_NO_SHIFT_REG;
wire local_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in;
wire local_bb1_indvars_iv16_pop52_acl_pop_i64_0_output_regs_ready;
wire [63:0] local_bb1_indvars_iv16_pop52_acl_pop_i64_0_result;
wire local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_valid_out;
wire local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_stall_out;
reg [63:0] local_bb1_indvars_iv16_pop52_acl_pop_i64_0_NO_SHIFT_REG;
wire local_bb1_indvars_iv16_pop52_acl_pop_i64_0_causedstall;
acl_pop local_bb1_indvars_iv16_pop52_acl_pop_i64_0_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_lvm_forked_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(64'h0),
.stall_out(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_stall_out),
.valid_in(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready),
.valid_out(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_valid_out),
.stall_in(~(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_output_regs_ready)),
.data_out(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_result),
.feedback_in(feedback_data_in_52),
.feedback_valid_in(feedback_valid_in_52),
.feedback_stall_out(feedback_stall_out_52)
);
defparam local_bb1_indvars_iv16_pop52_acl_pop_i64_0_feedback.DATA_WIDTH = 64;
defparam local_bb1_indvars_iv16_pop52_acl_pop_i64_0_feedback.STYLE = "REGULAR";
assign local_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready = merge_node_valid_out_3_NO_SHIFT_REG;
assign local_bb1_indvars_iv16_pop52_acl_pop_i64_0_output_regs_ready = (&(~(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_NO_SHIFT_REG) | ~(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in)));
assign merge_node_stall_in_3 = (local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_stall_out | ~(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready));
assign local_bb1_indvars_iv16_pop52_acl_pop_i64_0_causedstall = (local_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready && (local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_stall_out && !(~(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_indvars_iv16_pop52_acl_pop_i64_0_NO_SHIFT_REG <= 'x;
local_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_indvars_iv16_pop52_acl_pop_i64_0_output_regs_ready)
begin
local_bb1_indvars_iv16_pop52_acl_pop_i64_0_NO_SHIFT_REG <= local_bb1_indvars_iv16_pop52_acl_pop_i64_0_result;
local_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_NO_SHIFT_REG <= local_bb1_indvars_iv16_pop52_acl_pop_i64_0_fu_valid_out;
end
else
begin
if (~(local_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in))
begin
local_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 160
// * capacity = 160
logic rnode_1to161_forked_0_valid_out_NO_SHIFT_REG;
logic rnode_1to161_forked_0_stall_in_NO_SHIFT_REG;
logic rnode_1to161_forked_0_NO_SHIFT_REG;
logic rnode_1to161_forked_0_reg_161_inputs_ready_NO_SHIFT_REG;
logic rnode_1to161_forked_0_reg_161_NO_SHIFT_REG;
logic rnode_1to161_forked_0_valid_out_reg_161_NO_SHIFT_REG;
logic rnode_1to161_forked_0_stall_in_reg_161_NO_SHIFT_REG;
logic rnode_1to161_forked_0_stall_out_reg_161_NO_SHIFT_REG;
acl_data_fifo rnode_1to161_forked_0_reg_161_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_1to161_forked_0_reg_161_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_1to161_forked_0_stall_in_reg_161_NO_SHIFT_REG),
.valid_out(rnode_1to161_forked_0_valid_out_reg_161_NO_SHIFT_REG),
.stall_out(rnode_1to161_forked_0_stall_out_reg_161_NO_SHIFT_REG),
.data_in(local_lvm_forked_NO_SHIFT_REG),
.data_out(rnode_1to161_forked_0_reg_161_NO_SHIFT_REG)
);
defparam rnode_1to161_forked_0_reg_161_fifo.DEPTH = 161;
defparam rnode_1to161_forked_0_reg_161_fifo.DATA_WIDTH = 1;
defparam rnode_1to161_forked_0_reg_161_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to161_forked_0_reg_161_fifo.IMPL = "ram";
assign rnode_1to161_forked_0_reg_161_inputs_ready_NO_SHIFT_REG = merge_node_valid_out_4_NO_SHIFT_REG;
assign merge_node_stall_in_4 = rnode_1to161_forked_0_stall_out_reg_161_NO_SHIFT_REG;
assign rnode_1to161_forked_0_NO_SHIFT_REG = rnode_1to161_forked_0_reg_161_NO_SHIFT_REG;
assign rnode_1to161_forked_0_stall_in_reg_161_NO_SHIFT_REG = rnode_1to161_forked_0_stall_in_NO_SHIFT_REG;
assign rnode_1to161_forked_0_valid_out_NO_SHIFT_REG = rnode_1to161_forked_0_valid_out_reg_161_NO_SHIFT_REG;
// This section implements a staging register.
//
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_0;
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_0;
reg rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_0_NO_SHIFT_REG;
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_1;
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_1;
reg rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_1_NO_SHIFT_REG;
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready;
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_local;
reg rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG;
wire rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_combined_valid;
reg [3:0] rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_reg_NO_SHIFT_REG;
wire [3:0] rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7;
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready = local_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_NO_SHIFT_REG;
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7 = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG ? rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_reg_NO_SHIFT_REG : local_bb1_cleanups_pop55_acl_pop_i4_7_NO_SHIFT_REG);
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_combined_valid = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG | rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready);
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_local = ((rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_0 & ~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_0_NO_SHIFT_REG)) | (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_1 & ~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_1_NO_SHIFT_REG)));
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_0 = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_combined_valid & ~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_0_NO_SHIFT_REG));
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_1 = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_combined_valid & ~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_1_NO_SHIFT_REG));
assign local_bb1_cleanups_pop55_acl_pop_i4_7_stall_in = (|rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_local)
begin
if (~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG <= rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_inputs_ready;
end
end
else
begin
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_staging_reg_NO_SHIFT_REG <= local_bb1_cleanups_pop55_acl_pop_i4_7_NO_SHIFT_REG;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_0_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_1_NO_SHIFT_REG <= 1'b0;
end
else
begin
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_0_NO_SHIFT_REG <= (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_combined_valid & (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_0_NO_SHIFT_REG | ~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_0)) & rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_local);
rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_1_NO_SHIFT_REG <= (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_combined_valid & (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_consumed_1_NO_SHIFT_REG | ~(rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_1)) & rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_local);
end
end
// This section implements a staging register.
//
wire rstag_2to2_bb1_keep_going_forked_valid_out_0;
wire rstag_2to2_bb1_keep_going_forked_stall_in_0;
reg rstag_2to2_bb1_keep_going_forked_consumed_0_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked_valid_out_1;
wire rstag_2to2_bb1_keep_going_forked_stall_in_1;
reg rstag_2to2_bb1_keep_going_forked_consumed_1_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked_valid_out_2;
wire rstag_2to2_bb1_keep_going_forked_stall_in_2;
reg rstag_2to2_bb1_keep_going_forked_consumed_2_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked_valid_out_3;
wire rstag_2to2_bb1_keep_going_forked_stall_in_3;
reg rstag_2to2_bb1_keep_going_forked_consumed_3_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked_valid_out_4;
wire rstag_2to2_bb1_keep_going_forked_stall_in_4;
reg rstag_2to2_bb1_keep_going_forked_consumed_4_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked_inputs_ready;
wire rstag_2to2_bb1_keep_going_forked_stall_local;
reg rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked_combined_valid;
reg rstag_2to2_bb1_keep_going_forked_staging_reg_NO_SHIFT_REG;
wire rstag_2to2_bb1_keep_going_forked;
assign rstag_2to2_bb1_keep_going_forked_inputs_ready = local_bb1_keep_going_forked_valid_out_NO_SHIFT_REG;
assign rstag_2to2_bb1_keep_going_forked = (rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG ? rstag_2to2_bb1_keep_going_forked_staging_reg_NO_SHIFT_REG : local_bb1_keep_going_forked_NO_SHIFT_REG);
assign rstag_2to2_bb1_keep_going_forked_combined_valid = (rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG | rstag_2to2_bb1_keep_going_forked_inputs_ready);
assign rstag_2to2_bb1_keep_going_forked_stall_local = ((rstag_2to2_bb1_keep_going_forked_stall_in_0 & ~(rstag_2to2_bb1_keep_going_forked_consumed_0_NO_SHIFT_REG)) | (rstag_2to2_bb1_keep_going_forked_stall_in_1 & ~(rstag_2to2_bb1_keep_going_forked_consumed_1_NO_SHIFT_REG)) | (rstag_2to2_bb1_keep_going_forked_stall_in_2 & ~(rstag_2to2_bb1_keep_going_forked_consumed_2_NO_SHIFT_REG)) | (rstag_2to2_bb1_keep_going_forked_stall_in_3 & ~(rstag_2to2_bb1_keep_going_forked_consumed_3_NO_SHIFT_REG)) | (rstag_2to2_bb1_keep_going_forked_stall_in_4 & ~(rstag_2to2_bb1_keep_going_forked_consumed_4_NO_SHIFT_REG)));
assign rstag_2to2_bb1_keep_going_forked_valid_out_0 = (rstag_2to2_bb1_keep_going_forked_combined_valid & ~(rstag_2to2_bb1_keep_going_forked_consumed_0_NO_SHIFT_REG));
assign rstag_2to2_bb1_keep_going_forked_valid_out_1 = (rstag_2to2_bb1_keep_going_forked_combined_valid & ~(rstag_2to2_bb1_keep_going_forked_consumed_1_NO_SHIFT_REG));
assign rstag_2to2_bb1_keep_going_forked_valid_out_2 = (rstag_2to2_bb1_keep_going_forked_combined_valid & ~(rstag_2to2_bb1_keep_going_forked_consumed_2_NO_SHIFT_REG));
assign rstag_2to2_bb1_keep_going_forked_valid_out_3 = (rstag_2to2_bb1_keep_going_forked_combined_valid & ~(rstag_2to2_bb1_keep_going_forked_consumed_3_NO_SHIFT_REG));
assign rstag_2to2_bb1_keep_going_forked_valid_out_4 = (rstag_2to2_bb1_keep_going_forked_combined_valid & ~(rstag_2to2_bb1_keep_going_forked_consumed_4_NO_SHIFT_REG));
assign local_bb1_keep_going_forked_stall_in = (|rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_keep_going_forked_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_2to2_bb1_keep_going_forked_stall_local)
begin
if (~(rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG <= rstag_2to2_bb1_keep_going_forked_inputs_ready;
end
end
else
begin
rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_2to2_bb1_keep_going_forked_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_keep_going_forked_staging_reg_NO_SHIFT_REG <= local_bb1_keep_going_forked_NO_SHIFT_REG;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_keep_going_forked_consumed_0_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_keep_going_forked_consumed_1_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_keep_going_forked_consumed_2_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_keep_going_forked_consumed_3_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_keep_going_forked_consumed_4_NO_SHIFT_REG <= 1'b0;
end
else
begin
rstag_2to2_bb1_keep_going_forked_consumed_0_NO_SHIFT_REG <= (rstag_2to2_bb1_keep_going_forked_combined_valid & (rstag_2to2_bb1_keep_going_forked_consumed_0_NO_SHIFT_REG | ~(rstag_2to2_bb1_keep_going_forked_stall_in_0)) & rstag_2to2_bb1_keep_going_forked_stall_local);
rstag_2to2_bb1_keep_going_forked_consumed_1_NO_SHIFT_REG <= (rstag_2to2_bb1_keep_going_forked_combined_valid & (rstag_2to2_bb1_keep_going_forked_consumed_1_NO_SHIFT_REG | ~(rstag_2to2_bb1_keep_going_forked_stall_in_1)) & rstag_2to2_bb1_keep_going_forked_stall_local);
rstag_2to2_bb1_keep_going_forked_consumed_2_NO_SHIFT_REG <= (rstag_2to2_bb1_keep_going_forked_combined_valid & (rstag_2to2_bb1_keep_going_forked_consumed_2_NO_SHIFT_REG | ~(rstag_2to2_bb1_keep_going_forked_stall_in_2)) & rstag_2to2_bb1_keep_going_forked_stall_local);
rstag_2to2_bb1_keep_going_forked_consumed_3_NO_SHIFT_REG <= (rstag_2to2_bb1_keep_going_forked_combined_valid & (rstag_2to2_bb1_keep_going_forked_consumed_3_NO_SHIFT_REG | ~(rstag_2to2_bb1_keep_going_forked_stall_in_3)) & rstag_2to2_bb1_keep_going_forked_stall_local);
rstag_2to2_bb1_keep_going_forked_consumed_4_NO_SHIFT_REG <= (rstag_2to2_bb1_keep_going_forked_combined_valid & (rstag_2to2_bb1_keep_going_forked_consumed_4_NO_SHIFT_REG | ~(rstag_2to2_bb1_keep_going_forked_stall_in_4)) & rstag_2to2_bb1_keep_going_forked_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_next_initerations_stall_local;
wire [3:0] local_bb1_next_initerations;
assign local_bb1_next_initerations = (local_bb1_initerations_pop53_acl_pop_i4_7_NO_SHIFT_REG >> 4'h1);
// This section implements a staging register.
//
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_0;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_0;
reg rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_0_NO_SHIFT_REG;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_1;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_1;
reg rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_1_NO_SHIFT_REG;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_2;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_2;
reg rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_2_NO_SHIFT_REG;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_local;
reg rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG;
wire rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid;
reg [63:0] rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0;
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready = local_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_NO_SHIFT_REG;
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0 = (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG ? rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_reg_NO_SHIFT_REG : local_bb1_indvars_iv16_pop52_acl_pop_i64_0_NO_SHIFT_REG);
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid = (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG | rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready);
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_local = ((rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_0 & ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_0_NO_SHIFT_REG)) | (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_1 & ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_1_NO_SHIFT_REG)) | (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_2 & ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_2_NO_SHIFT_REG)));
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_0 = (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid & ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_0_NO_SHIFT_REG));
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_1 = (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid & ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_1_NO_SHIFT_REG));
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_2 = (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid & ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_2_NO_SHIFT_REG));
assign local_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in = (|rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_local)
begin
if (~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG <= rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_inputs_ready;
end
end
else
begin
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_staging_reg_NO_SHIFT_REG <= local_bb1_indvars_iv16_pop52_acl_pop_i64_0_NO_SHIFT_REG;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_0_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_1_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_2_NO_SHIFT_REG <= 1'b0;
end
else
begin
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_0_NO_SHIFT_REG <= (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid & (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_0_NO_SHIFT_REG | ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_0)) & rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_local);
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_1_NO_SHIFT_REG <= (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid & (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_1_NO_SHIFT_REG | ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_1)) & rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_local);
rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_2_NO_SHIFT_REG <= (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_combined_valid & (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_consumed_2_NO_SHIFT_REG | ~(rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_2)) & rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_161to162_forked_0_valid_out_0_NO_SHIFT_REG;
logic rnode_161to162_forked_0_stall_in_0_NO_SHIFT_REG;
logic rnode_161to162_forked_0_NO_SHIFT_REG;
logic rnode_161to162_forked_0_valid_out_1_NO_SHIFT_REG;
logic rnode_161to162_forked_0_stall_in_1_NO_SHIFT_REG;
logic rnode_161to162_forked_1_NO_SHIFT_REG;
logic rnode_161to162_forked_0_reg_162_inputs_ready_NO_SHIFT_REG;
logic rnode_161to162_forked_0_reg_162_NO_SHIFT_REG;
logic rnode_161to162_forked_0_valid_out_0_reg_162_NO_SHIFT_REG;
logic rnode_161to162_forked_0_stall_in_0_reg_162_NO_SHIFT_REG;
logic rnode_161to162_forked_0_stall_out_reg_162_NO_SHIFT_REG;
logic rnode_161to162_forked_0_reg_162_NO_SHIFT_REG_fa;
acl_multi_fanout_adaptor rnode_161to162_forked_0_reg_162_fanout_adaptor (
.clock(clock),
.resetn(resetn),
.data_in(rnode_161to162_forked_0_reg_162_NO_SHIFT_REG),
.valid_in(rnode_161to162_forked_0_valid_out_0_reg_162_NO_SHIFT_REG),
.stall_out(rnode_161to162_forked_0_stall_in_0_reg_162_NO_SHIFT_REG),
.data_out(rnode_161to162_forked_0_reg_162_NO_SHIFT_REG_fa),
.valid_out({rnode_161to162_forked_0_valid_out_0_NO_SHIFT_REG, rnode_161to162_forked_0_valid_out_1_NO_SHIFT_REG}),
.stall_in({rnode_161to162_forked_0_stall_in_0_NO_SHIFT_REG, rnode_161to162_forked_0_stall_in_1_NO_SHIFT_REG})
);
defparam rnode_161to162_forked_0_reg_162_fanout_adaptor.DATA_WIDTH = 1;
defparam rnode_161to162_forked_0_reg_162_fanout_adaptor.NUM_FANOUTS = 2;
acl_data_fifo rnode_161to162_forked_0_reg_162_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_161to162_forked_0_reg_162_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_161to162_forked_0_stall_in_0_reg_162_NO_SHIFT_REG),
.valid_out(rnode_161to162_forked_0_valid_out_0_reg_162_NO_SHIFT_REG),
.stall_out(rnode_161to162_forked_0_stall_out_reg_162_NO_SHIFT_REG),
.data_in(rnode_1to161_forked_0_NO_SHIFT_REG),
.data_out(rnode_161to162_forked_0_reg_162_NO_SHIFT_REG)
);
defparam rnode_161to162_forked_0_reg_162_fifo.DEPTH = 2;
defparam rnode_161to162_forked_0_reg_162_fifo.DATA_WIDTH = 1;
defparam rnode_161to162_forked_0_reg_162_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to162_forked_0_reg_162_fifo.IMPL = "ll_reg";
assign rnode_161to162_forked_0_reg_162_inputs_ready_NO_SHIFT_REG = rnode_1to161_forked_0_valid_out_NO_SHIFT_REG;
assign rnode_1to161_forked_0_stall_in_NO_SHIFT_REG = rnode_161to162_forked_0_stall_out_reg_162_NO_SHIFT_REG;
assign rnode_161to162_forked_0_NO_SHIFT_REG = rnode_161to162_forked_0_reg_162_NO_SHIFT_REG_fa;
assign rnode_161to162_forked_1_NO_SHIFT_REG = rnode_161to162_forked_0_reg_162_NO_SHIFT_REG_fa;
// This section implements an unregistered operation.
//
wire local_bb1_var__stall_local;
wire [3:0] local_bb1_var_;
assign local_bb1_var_ = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7 & 4'h1);
// Register node:
// * latency = 159
// * capacity = 159
logic rnode_2to161_bb1_keep_going_forked_0_valid_out_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_stall_in_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_reg_161_inputs_ready_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_reg_161_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_valid_out_reg_161_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_stall_in_reg_161_NO_SHIFT_REG;
logic rnode_2to161_bb1_keep_going_forked_0_stall_out_reg_161_NO_SHIFT_REG;
acl_data_fifo rnode_2to161_bb1_keep_going_forked_0_reg_161_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_2to161_bb1_keep_going_forked_0_reg_161_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_2to161_bb1_keep_going_forked_0_stall_in_reg_161_NO_SHIFT_REG),
.valid_out(rnode_2to161_bb1_keep_going_forked_0_valid_out_reg_161_NO_SHIFT_REG),
.stall_out(rnode_2to161_bb1_keep_going_forked_0_stall_out_reg_161_NO_SHIFT_REG),
.data_in(rstag_2to2_bb1_keep_going_forked),
.data_out(rnode_2to161_bb1_keep_going_forked_0_reg_161_NO_SHIFT_REG)
);
defparam rnode_2to161_bb1_keep_going_forked_0_reg_161_fifo.DEPTH = 160;
defparam rnode_2to161_bb1_keep_going_forked_0_reg_161_fifo.DATA_WIDTH = 1;
defparam rnode_2to161_bb1_keep_going_forked_0_reg_161_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_2to161_bb1_keep_going_forked_0_reg_161_fifo.IMPL = "ram";
assign rnode_2to161_bb1_keep_going_forked_0_reg_161_inputs_ready_NO_SHIFT_REG = rstag_2to2_bb1_keep_going_forked_valid_out_0;
assign rstag_2to2_bb1_keep_going_forked_stall_in_0 = rnode_2to161_bb1_keep_going_forked_0_stall_out_reg_161_NO_SHIFT_REG;
assign rnode_2to161_bb1_keep_going_forked_0_NO_SHIFT_REG = rnode_2to161_bb1_keep_going_forked_0_reg_161_NO_SHIFT_REG;
assign rnode_2to161_bb1_keep_going_forked_0_stall_in_reg_161_NO_SHIFT_REG = rnode_2to161_bb1_keep_going_forked_0_stall_in_NO_SHIFT_REG;
assign rnode_2to161_bb1_keep_going_forked_0_valid_out_NO_SHIFT_REG = rnode_2to161_bb1_keep_going_forked_0_valid_out_reg_161_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_var__u0_stall_local;
wire [3:0] local_bb1_var__u0;
assign local_bb1_var__u0 = (local_bb1_next_initerations & 4'h1);
// This section implements an unregistered operation.
//
wire local_bb1_arrayidx34_valid_out;
wire local_bb1_arrayidx34_stall_in;
wire local_bb1_arrayidx34_inputs_ready;
wire local_bb1_arrayidx34_stall_local;
wire [63:0] local_bb1_arrayidx34;
assign local_bb1_arrayidx34_inputs_ready = rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_0;
assign local_bb1_arrayidx34 = (input_img_out + rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0);
assign local_bb1_arrayidx34_valid_out = local_bb1_arrayidx34_inputs_ready;
assign local_bb1_arrayidx34_stall_local = local_bb1_arrayidx34_stall_in;
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_0 = (|local_bb1_arrayidx34_stall_local);
// This section implements an unregistered operation.
//
wire local_bb1_arrayidx5_valid_out;
wire local_bb1_arrayidx5_stall_in;
wire local_bb1_arrayidx5_inputs_ready;
wire local_bb1_arrayidx5_stall_local;
wire [63:0] local_bb1_arrayidx5;
assign local_bb1_arrayidx5_inputs_ready = rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_1;
assign local_bb1_arrayidx5 = (input_img_in + rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0);
assign local_bb1_arrayidx5_valid_out = local_bb1_arrayidx5_inputs_ready;
assign local_bb1_arrayidx5_stall_local = local_bb1_arrayidx5_stall_in;
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_1 = (|local_bb1_arrayidx5_stall_local);
// This section implements an unregistered operation.
//
wire local_bb1_indvars_iv_next17_stall_local;
wire [63:0] local_bb1_indvars_iv_next17;
assign local_bb1_indvars_iv_next17 = (rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0 + 64'h1);
// This section implements an unregistered operation.
//
wire local_bb1_c0_eni1_stall_local;
wire [31:0] local_bb1_c0_eni1;
assign local_bb1_c0_eni1[7:0] = 8'bxxxxxxxx;
assign local_bb1_c0_eni1[8] = rnode_161to162_forked_0_NO_SHIFT_REG;
assign local_bb1_c0_eni1[31:9] = 23'bxxxxxxxxxxxxxxxxxxxxxxx;
// This section implements an unregistered operation.
//
wire local_bb1_first_cleanup_stall_local;
wire local_bb1_first_cleanup;
assign local_bb1_first_cleanup = (local_bb1_var_ != 4'h0);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_161to162_bb1_keep_going_forked_0_valid_out_0_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_stall_in_0_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_valid_out_1_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_stall_in_1_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_1_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_reg_162_inputs_ready_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_valid_out_0_reg_162_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_stall_in_0_reg_162_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_stall_out_reg_162_NO_SHIFT_REG;
logic rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG_fa;
acl_multi_fanout_adaptor rnode_161to162_bb1_keep_going_forked_0_reg_162_fanout_adaptor (
.clock(clock),
.resetn(resetn),
.data_in(rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG),
.valid_in(rnode_161to162_bb1_keep_going_forked_0_valid_out_0_reg_162_NO_SHIFT_REG),
.stall_out(rnode_161to162_bb1_keep_going_forked_0_stall_in_0_reg_162_NO_SHIFT_REG),
.data_out(rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG_fa),
.valid_out({rnode_161to162_bb1_keep_going_forked_0_valid_out_0_NO_SHIFT_REG, rnode_161to162_bb1_keep_going_forked_0_valid_out_1_NO_SHIFT_REG}),
.stall_in({rnode_161to162_bb1_keep_going_forked_0_stall_in_0_NO_SHIFT_REG, rnode_161to162_bb1_keep_going_forked_0_stall_in_1_NO_SHIFT_REG})
);
defparam rnode_161to162_bb1_keep_going_forked_0_reg_162_fanout_adaptor.DATA_WIDTH = 1;
defparam rnode_161to162_bb1_keep_going_forked_0_reg_162_fanout_adaptor.NUM_FANOUTS = 2;
acl_data_fifo rnode_161to162_bb1_keep_going_forked_0_reg_162_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_161to162_bb1_keep_going_forked_0_reg_162_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_161to162_bb1_keep_going_forked_0_stall_in_0_reg_162_NO_SHIFT_REG),
.valid_out(rnode_161to162_bb1_keep_going_forked_0_valid_out_0_reg_162_NO_SHIFT_REG),
.stall_out(rnode_161to162_bb1_keep_going_forked_0_stall_out_reg_162_NO_SHIFT_REG),
.data_in(rnode_2to161_bb1_keep_going_forked_0_NO_SHIFT_REG),
.data_out(rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG)
);
defparam rnode_161to162_bb1_keep_going_forked_0_reg_162_fifo.DEPTH = 2;
defparam rnode_161to162_bb1_keep_going_forked_0_reg_162_fifo.DATA_WIDTH = 1;
defparam rnode_161to162_bb1_keep_going_forked_0_reg_162_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to162_bb1_keep_going_forked_0_reg_162_fifo.IMPL = "ll_reg";
assign rnode_161to162_bb1_keep_going_forked_0_reg_162_inputs_ready_NO_SHIFT_REG = rnode_2to161_bb1_keep_going_forked_0_valid_out_NO_SHIFT_REG;
assign rnode_2to161_bb1_keep_going_forked_0_stall_in_NO_SHIFT_REG = rnode_161to162_bb1_keep_going_forked_0_stall_out_reg_162_NO_SHIFT_REG;
assign rnode_161to162_bb1_keep_going_forked_0_NO_SHIFT_REG = rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG_fa;
assign rnode_161to162_bb1_keep_going_forked_1_NO_SHIFT_REG = rnode_161to162_bb1_keep_going_forked_0_reg_162_NO_SHIFT_REG_fa;
// This section implements an unregistered operation.
//
wire local_bb1_next_initerations_valid_out_0;
wire local_bb1_next_initerations_stall_in_0;
reg local_bb1_next_initerations_consumed_0_NO_SHIFT_REG;
wire local_bb1_last_initeration_valid_out;
wire local_bb1_last_initeration_stall_in;
reg local_bb1_last_initeration_consumed_0_NO_SHIFT_REG;
wire local_bb1_last_initeration_inputs_ready;
wire local_bb1_last_initeration_stall_local;
wire local_bb1_last_initeration;
assign local_bb1_last_initeration_inputs_ready = local_bb1_initerations_pop53_acl_pop_i4_7_valid_out_NO_SHIFT_REG;
assign local_bb1_last_initeration = (local_bb1_var__u0 != 4'h0);
assign local_bb1_last_initeration_stall_local = ((local_bb1_next_initerations_stall_in_0 & ~(local_bb1_next_initerations_consumed_0_NO_SHIFT_REG)) | (local_bb1_last_initeration_stall_in & ~(local_bb1_last_initeration_consumed_0_NO_SHIFT_REG)));
assign local_bb1_next_initerations_valid_out_0 = (local_bb1_last_initeration_inputs_ready & ~(local_bb1_next_initerations_consumed_0_NO_SHIFT_REG));
assign local_bb1_last_initeration_valid_out = (local_bb1_last_initeration_inputs_ready & ~(local_bb1_last_initeration_consumed_0_NO_SHIFT_REG));
assign local_bb1_initerations_pop53_acl_pop_i4_7_stall_in = (|local_bb1_last_initeration_stall_local);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_next_initerations_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_last_initeration_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_next_initerations_consumed_0_NO_SHIFT_REG <= (local_bb1_last_initeration_inputs_ready & (local_bb1_next_initerations_consumed_0_NO_SHIFT_REG | ~(local_bb1_next_initerations_stall_in_0)) & local_bb1_last_initeration_stall_local);
local_bb1_last_initeration_consumed_0_NO_SHIFT_REG <= (local_bb1_last_initeration_inputs_ready & (local_bb1_last_initeration_consumed_0_NO_SHIFT_REG | ~(local_bb1_last_initeration_stall_in)) & local_bb1_last_initeration_stall_local);
end
end
// Register node:
// * latency = 173
// * capacity = 173
logic rnode_2to175_bb1_arrayidx34_0_valid_out_NO_SHIFT_REG;
logic rnode_2to175_bb1_arrayidx34_0_stall_in_NO_SHIFT_REG;
logic [63:0] rnode_2to175_bb1_arrayidx34_0_NO_SHIFT_REG;
logic rnode_2to175_bb1_arrayidx34_0_reg_175_inputs_ready_NO_SHIFT_REG;
logic [63:0] rnode_2to175_bb1_arrayidx34_0_reg_175_NO_SHIFT_REG;
logic rnode_2to175_bb1_arrayidx34_0_valid_out_reg_175_NO_SHIFT_REG;
logic rnode_2to175_bb1_arrayidx34_0_stall_in_reg_175_NO_SHIFT_REG;
logic rnode_2to175_bb1_arrayidx34_0_stall_out_reg_175_NO_SHIFT_REG;
acl_data_fifo rnode_2to175_bb1_arrayidx34_0_reg_175_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_2to175_bb1_arrayidx34_0_reg_175_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_2to175_bb1_arrayidx34_0_stall_in_reg_175_NO_SHIFT_REG),
.valid_out(rnode_2to175_bb1_arrayidx34_0_valid_out_reg_175_NO_SHIFT_REG),
.stall_out(rnode_2to175_bb1_arrayidx34_0_stall_out_reg_175_NO_SHIFT_REG),
.data_in(local_bb1_arrayidx34),
.data_out(rnode_2to175_bb1_arrayidx34_0_reg_175_NO_SHIFT_REG)
);
defparam rnode_2to175_bb1_arrayidx34_0_reg_175_fifo.DEPTH = 174;
defparam rnode_2to175_bb1_arrayidx34_0_reg_175_fifo.DATA_WIDTH = 64;
defparam rnode_2to175_bb1_arrayidx34_0_reg_175_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_2to175_bb1_arrayidx34_0_reg_175_fifo.IMPL = "ram";
assign rnode_2to175_bb1_arrayidx34_0_reg_175_inputs_ready_NO_SHIFT_REG = local_bb1_arrayidx34_valid_out;
assign local_bb1_arrayidx34_stall_in = rnode_2to175_bb1_arrayidx34_0_stall_out_reg_175_NO_SHIFT_REG;
assign rnode_2to175_bb1_arrayidx34_0_NO_SHIFT_REG = rnode_2to175_bb1_arrayidx34_0_reg_175_NO_SHIFT_REG;
assign rnode_2to175_bb1_arrayidx34_0_stall_in_reg_175_NO_SHIFT_REG = rnode_2to175_bb1_arrayidx34_0_stall_in_NO_SHIFT_REG;
assign rnode_2to175_bb1_arrayidx34_0_valid_out_NO_SHIFT_REG = rnode_2to175_bb1_arrayidx34_0_valid_out_reg_175_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_lftr_wideiv18_stall_local;
wire [31:0] local_bb1_lftr_wideiv18;
assign local_bb1_lftr_wideiv18 = local_bb1_indvars_iv_next17[31:0];
// This section implements an unregistered operation.
//
wire local_bb1_xor_stall_local;
wire local_bb1_xor;
assign local_bb1_xor = (local_bb1_first_cleanup ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_c0_eni2_stall_local;
wire [31:0] local_bb1_c0_eni2;
assign local_bb1_c0_eni2[15:0] = local_bb1_c0_eni1[15:0];
assign local_bb1_c0_eni2[16] = rnode_161to162_bb1_keep_going_forked_0_NO_SHIFT_REG;
assign local_bb1_c0_eni2[31:17] = local_bb1_c0_eni1[31:17];
// This section implements a registered operation.
//
wire local_bb1_initerations_push53_next_initerations_inputs_ready;
reg local_bb1_initerations_push53_next_initerations_valid_out_NO_SHIFT_REG;
wire local_bb1_initerations_push53_next_initerations_stall_in;
wire local_bb1_initerations_push53_next_initerations_output_regs_ready;
wire [3:0] local_bb1_initerations_push53_next_initerations_result;
wire local_bb1_initerations_push53_next_initerations_fu_valid_out;
wire local_bb1_initerations_push53_next_initerations_fu_stall_out;
reg [3:0] local_bb1_initerations_push53_next_initerations_NO_SHIFT_REG;
wire local_bb1_initerations_push53_next_initerations_causedstall;
acl_push local_bb1_initerations_push53_next_initerations_feedback (
.clock(clock),
.resetn(resetn),
.dir(rstag_2to2_bb1_keep_going_forked),
.predicate(1'b0),
.data_in(local_bb1_next_initerations),
.stall_out(local_bb1_initerations_push53_next_initerations_fu_stall_out),
.valid_in(local_bb1_initerations_push53_next_initerations_inputs_ready),
.valid_out(local_bb1_initerations_push53_next_initerations_fu_valid_out),
.stall_in(~(local_bb1_initerations_push53_next_initerations_output_regs_ready)),
.data_out(local_bb1_initerations_push53_next_initerations_result),
.feedback_out(feedback_data_out_53),
.feedback_valid_out(feedback_valid_out_53),
.feedback_stall_in(feedback_stall_in_53)
);
defparam local_bb1_initerations_push53_next_initerations_feedback.STALLFREE = 0;
defparam local_bb1_initerations_push53_next_initerations_feedback.DATA_WIDTH = 4;
defparam local_bb1_initerations_push53_next_initerations_feedback.FIFO_DEPTH = 2;
defparam local_bb1_initerations_push53_next_initerations_feedback.MIN_FIFO_LATENCY = 0;
defparam local_bb1_initerations_push53_next_initerations_feedback.STYLE = "REGULAR";
assign local_bb1_initerations_push53_next_initerations_inputs_ready = (local_bb1_next_initerations_valid_out_0 & rstag_2to2_bb1_keep_going_forked_valid_out_4);
assign local_bb1_initerations_push53_next_initerations_output_regs_ready = (&(~(local_bb1_initerations_push53_next_initerations_valid_out_NO_SHIFT_REG) | ~(local_bb1_initerations_push53_next_initerations_stall_in)));
assign local_bb1_next_initerations_stall_in_0 = (local_bb1_initerations_push53_next_initerations_fu_stall_out | ~(local_bb1_initerations_push53_next_initerations_inputs_ready));
assign rstag_2to2_bb1_keep_going_forked_stall_in_4 = (local_bb1_initerations_push53_next_initerations_fu_stall_out | ~(local_bb1_initerations_push53_next_initerations_inputs_ready));
assign local_bb1_initerations_push53_next_initerations_causedstall = (local_bb1_initerations_push53_next_initerations_inputs_ready && (local_bb1_initerations_push53_next_initerations_fu_stall_out && !(~(local_bb1_initerations_push53_next_initerations_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_initerations_push53_next_initerations_NO_SHIFT_REG <= 'x;
local_bb1_initerations_push53_next_initerations_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_initerations_push53_next_initerations_output_regs_ready)
begin
local_bb1_initerations_push53_next_initerations_NO_SHIFT_REG <= local_bb1_initerations_push53_next_initerations_result;
local_bb1_initerations_push53_next_initerations_valid_out_NO_SHIFT_REG <= local_bb1_initerations_push53_next_initerations_fu_valid_out;
end
else
begin
if (~(local_bb1_initerations_push53_next_initerations_stall_in))
begin
local_bb1_initerations_push53_next_initerations_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_lastiniteration_last_initeration_inputs_ready;
reg local_bb1_lastiniteration_last_initeration_valid_out_NO_SHIFT_REG;
wire local_bb1_lastiniteration_last_initeration_stall_in;
wire local_bb1_lastiniteration_last_initeration_output_regs_ready;
wire local_bb1_lastiniteration_last_initeration_result;
wire local_bb1_lastiniteration_last_initeration_fu_valid_out;
wire local_bb1_lastiniteration_last_initeration_fu_stall_out;
reg local_bb1_lastiniteration_last_initeration_NO_SHIFT_REG;
wire local_bb1_lastiniteration_last_initeration_causedstall;
acl_push local_bb1_lastiniteration_last_initeration_feedback (
.clock(clock),
.resetn(resetn),
.dir(rstag_2to2_bb1_keep_going_forked),
.predicate(1'b0),
.data_in(local_bb1_last_initeration),
.stall_out(local_bb1_lastiniteration_last_initeration_fu_stall_out),
.valid_in(local_bb1_lastiniteration_last_initeration_inputs_ready),
.valid_out(local_bb1_lastiniteration_last_initeration_fu_valid_out),
.stall_in(~(local_bb1_lastiniteration_last_initeration_output_regs_ready)),
.data_out(local_bb1_lastiniteration_last_initeration_result),
.feedback_out(feedback_data_out_0),
.feedback_valid_out(feedback_valid_out_0),
.feedback_stall_in(feedback_stall_in_0)
);
defparam local_bb1_lastiniteration_last_initeration_feedback.STALLFREE = 0;
defparam local_bb1_lastiniteration_last_initeration_feedback.DATA_WIDTH = 1;
defparam local_bb1_lastiniteration_last_initeration_feedback.FIFO_DEPTH = 2;
defparam local_bb1_lastiniteration_last_initeration_feedback.MIN_FIFO_LATENCY = 0;
defparam local_bb1_lastiniteration_last_initeration_feedback.STYLE = "REGULAR";
assign local_bb1_lastiniteration_last_initeration_inputs_ready = (local_bb1_last_initeration_valid_out & rstag_2to2_bb1_keep_going_forked_valid_out_2);
assign local_bb1_lastiniteration_last_initeration_output_regs_ready = (&(~(local_bb1_lastiniteration_last_initeration_valid_out_NO_SHIFT_REG) | ~(local_bb1_lastiniteration_last_initeration_stall_in)));
assign local_bb1_last_initeration_stall_in = (local_bb1_lastiniteration_last_initeration_fu_stall_out | ~(local_bb1_lastiniteration_last_initeration_inputs_ready));
assign rstag_2to2_bb1_keep_going_forked_stall_in_2 = (local_bb1_lastiniteration_last_initeration_fu_stall_out | ~(local_bb1_lastiniteration_last_initeration_inputs_ready));
assign local_bb1_lastiniteration_last_initeration_causedstall = (local_bb1_lastiniteration_last_initeration_inputs_ready && (local_bb1_lastiniteration_last_initeration_fu_stall_out && !(~(local_bb1_lastiniteration_last_initeration_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_lastiniteration_last_initeration_NO_SHIFT_REG <= 'x;
local_bb1_lastiniteration_last_initeration_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_lastiniteration_last_initeration_output_regs_ready)
begin
local_bb1_lastiniteration_last_initeration_NO_SHIFT_REG <= local_bb1_lastiniteration_last_initeration_result;
local_bb1_lastiniteration_last_initeration_valid_out_NO_SHIFT_REG <= local_bb1_lastiniteration_last_initeration_fu_valid_out;
end
else
begin
if (~(local_bb1_lastiniteration_last_initeration_stall_in))
begin
local_bb1_lastiniteration_last_initeration_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_175to176_bb1_arrayidx34_0_valid_out_NO_SHIFT_REG;
logic rnode_175to176_bb1_arrayidx34_0_stall_in_NO_SHIFT_REG;
logic [63:0] rnode_175to176_bb1_arrayidx34_0_NO_SHIFT_REG;
logic rnode_175to176_bb1_arrayidx34_0_reg_176_inputs_ready_NO_SHIFT_REG;
logic [63:0] rnode_175to176_bb1_arrayidx34_0_reg_176_NO_SHIFT_REG;
logic rnode_175to176_bb1_arrayidx34_0_valid_out_reg_176_NO_SHIFT_REG;
logic rnode_175to176_bb1_arrayidx34_0_stall_in_reg_176_NO_SHIFT_REG;
logic rnode_175to176_bb1_arrayidx34_0_stall_out_reg_176_NO_SHIFT_REG;
acl_data_fifo rnode_175to176_bb1_arrayidx34_0_reg_176_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_175to176_bb1_arrayidx34_0_reg_176_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_175to176_bb1_arrayidx34_0_stall_in_reg_176_NO_SHIFT_REG),
.valid_out(rnode_175to176_bb1_arrayidx34_0_valid_out_reg_176_NO_SHIFT_REG),
.stall_out(rnode_175to176_bb1_arrayidx34_0_stall_out_reg_176_NO_SHIFT_REG),
.data_in(rnode_2to175_bb1_arrayidx34_0_NO_SHIFT_REG),
.data_out(rnode_175to176_bb1_arrayidx34_0_reg_176_NO_SHIFT_REG)
);
defparam rnode_175to176_bb1_arrayidx34_0_reg_176_fifo.DEPTH = 2;
defparam rnode_175to176_bb1_arrayidx34_0_reg_176_fifo.DATA_WIDTH = 64;
defparam rnode_175to176_bb1_arrayidx34_0_reg_176_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_175to176_bb1_arrayidx34_0_reg_176_fifo.IMPL = "ll_reg";
assign rnode_175to176_bb1_arrayidx34_0_reg_176_inputs_ready_NO_SHIFT_REG = rnode_2to175_bb1_arrayidx34_0_valid_out_NO_SHIFT_REG;
assign rnode_2to175_bb1_arrayidx34_0_stall_in_NO_SHIFT_REG = rnode_175to176_bb1_arrayidx34_0_stall_out_reg_176_NO_SHIFT_REG;
assign rnode_175to176_bb1_arrayidx34_0_NO_SHIFT_REG = rnode_175to176_bb1_arrayidx34_0_reg_176_NO_SHIFT_REG;
assign rnode_175to176_bb1_arrayidx34_0_stall_in_reg_176_NO_SHIFT_REG = rnode_175to176_bb1_arrayidx34_0_stall_in_NO_SHIFT_REG;
assign rnode_175to176_bb1_arrayidx34_0_valid_out_NO_SHIFT_REG = rnode_175to176_bb1_arrayidx34_0_valid_out_reg_176_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_exitcond19_stall_local;
wire local_bb1_exitcond19;
assign local_bb1_exitcond19 = (local_bb1_lftr_wideiv18 == input_iterations);
// This section implements an unregistered operation.
//
wire local_bb1_first_cleanup_xor_or_stall_local;
wire local_bb1_first_cleanup_xor_or;
assign local_bb1_first_cleanup_xor_or = (input_wii_cmp6 | local_bb1_xor);
// Register node:
// * latency = 176
// * capacity = 176
logic rnode_3to179_bb1_initerations_push53_next_initerations_0_valid_out_NO_SHIFT_REG;
logic rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_in_NO_SHIFT_REG;
logic [3:0] rnode_3to179_bb1_initerations_push53_next_initerations_0_NO_SHIFT_REG;
logic rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_inputs_ready_NO_SHIFT_REG;
logic [3:0] rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_initerations_push53_next_initerations_0_valid_out_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_in_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_out_reg_179_NO_SHIFT_REG;
acl_data_fifo rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_in_reg_179_NO_SHIFT_REG),
.valid_out(rnode_3to179_bb1_initerations_push53_next_initerations_0_valid_out_reg_179_NO_SHIFT_REG),
.stall_out(rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_out_reg_179_NO_SHIFT_REG),
.data_in(local_bb1_initerations_push53_next_initerations_NO_SHIFT_REG),
.data_out(rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_NO_SHIFT_REG)
);
defparam rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_fifo.DEPTH = 177;
defparam rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_fifo.DATA_WIDTH = 4;
defparam rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_fifo.IMPL = "ram";
assign rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_inputs_ready_NO_SHIFT_REG = local_bb1_initerations_push53_next_initerations_valid_out_NO_SHIFT_REG;
assign local_bb1_initerations_push53_next_initerations_stall_in = rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_out_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_initerations_push53_next_initerations_0_NO_SHIFT_REG = rnode_3to179_bb1_initerations_push53_next_initerations_0_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_in_reg_179_NO_SHIFT_REG = rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_in_NO_SHIFT_REG;
assign rnode_3to179_bb1_initerations_push53_next_initerations_0_valid_out_NO_SHIFT_REG = rnode_3to179_bb1_initerations_push53_next_initerations_0_valid_out_reg_179_NO_SHIFT_REG;
// Register node:
// * latency = 176
// * capacity = 176
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_valid_out_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_in_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_inputs_ready_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_valid_out_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_in_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_out_reg_179_NO_SHIFT_REG;
acl_data_fifo rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_in_reg_179_NO_SHIFT_REG),
.valid_out(rnode_3to179_bb1_lastiniteration_last_initeration_0_valid_out_reg_179_NO_SHIFT_REG),
.stall_out(rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_out_reg_179_NO_SHIFT_REG),
.data_in(local_bb1_lastiniteration_last_initeration_NO_SHIFT_REG),
.data_out(rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_NO_SHIFT_REG)
);
defparam rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_fifo.DEPTH = 177;
defparam rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_fifo.DATA_WIDTH = 1;
defparam rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_fifo.IMPL = "ram";
assign rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_inputs_ready_NO_SHIFT_REG = local_bb1_lastiniteration_last_initeration_valid_out_NO_SHIFT_REG;
assign local_bb1_lastiniteration_last_initeration_stall_in = rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_out_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_lastiniteration_last_initeration_0_NO_SHIFT_REG = rnode_3to179_bb1_lastiniteration_last_initeration_0_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_in_reg_179_NO_SHIFT_REG = rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_in_NO_SHIFT_REG;
assign rnode_3to179_bb1_lastiniteration_last_initeration_0_valid_out_NO_SHIFT_REG = rnode_3to179_bb1_lastiniteration_last_initeration_0_valid_out_reg_179_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_var__u1_stall_local;
wire local_bb1_var__u1;
assign local_bb1_var__u1 = (input_wii_cmp6 | local_bb1_exitcond19);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_179to180_bb1_initerations_push53_next_initerations_0_valid_out_NO_SHIFT_REG;
logic rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_in_NO_SHIFT_REG;
logic [3:0] rnode_179to180_bb1_initerations_push53_next_initerations_0_NO_SHIFT_REG;
logic rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_inputs_ready_NO_SHIFT_REG;
logic [3:0] rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_initerations_push53_next_initerations_0_valid_out_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_in_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_out_reg_180_NO_SHIFT_REG;
acl_data_fifo rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_in_reg_180_NO_SHIFT_REG),
.valid_out(rnode_179to180_bb1_initerations_push53_next_initerations_0_valid_out_reg_180_NO_SHIFT_REG),
.stall_out(rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_out_reg_180_NO_SHIFT_REG),
.data_in(rnode_3to179_bb1_initerations_push53_next_initerations_0_NO_SHIFT_REG),
.data_out(rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_NO_SHIFT_REG)
);
defparam rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_fifo.DEPTH = 2;
defparam rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_fifo.DATA_WIDTH = 4;
defparam rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_fifo.IMPL = "ll_reg";
assign rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_inputs_ready_NO_SHIFT_REG = rnode_3to179_bb1_initerations_push53_next_initerations_0_valid_out_NO_SHIFT_REG;
assign rnode_3to179_bb1_initerations_push53_next_initerations_0_stall_in_NO_SHIFT_REG = rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_out_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_initerations_push53_next_initerations_0_NO_SHIFT_REG = rnode_179to180_bb1_initerations_push53_next_initerations_0_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_in_reg_180_NO_SHIFT_REG = rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_in_NO_SHIFT_REG;
assign rnode_179to180_bb1_initerations_push53_next_initerations_0_valid_out_NO_SHIFT_REG = rnode_179to180_bb1_initerations_push53_next_initerations_0_valid_out_reg_180_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_valid_out_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_in_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_inputs_ready_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_valid_out_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_in_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_out_reg_180_NO_SHIFT_REG;
acl_data_fifo rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_in_reg_180_NO_SHIFT_REG),
.valid_out(rnode_179to180_bb1_lastiniteration_last_initeration_0_valid_out_reg_180_NO_SHIFT_REG),
.stall_out(rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_out_reg_180_NO_SHIFT_REG),
.data_in(rnode_3to179_bb1_lastiniteration_last_initeration_0_NO_SHIFT_REG),
.data_out(rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_NO_SHIFT_REG)
);
defparam rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_fifo.DEPTH = 2;
defparam rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_fifo.DATA_WIDTH = 1;
defparam rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_fifo.IMPL = "ll_reg";
assign rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_inputs_ready_NO_SHIFT_REG = rnode_3to179_bb1_lastiniteration_last_initeration_0_valid_out_NO_SHIFT_REG;
assign rnode_3to179_bb1_lastiniteration_last_initeration_0_stall_in_NO_SHIFT_REG = rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_out_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_lastiniteration_last_initeration_0_NO_SHIFT_REG = rnode_179to180_bb1_lastiniteration_last_initeration_0_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_in_reg_180_NO_SHIFT_REG = rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_in_NO_SHIFT_REG;
assign rnode_179to180_bb1_lastiniteration_last_initeration_0_valid_out_NO_SHIFT_REG = rnode_179to180_bb1_lastiniteration_last_initeration_0_valid_out_reg_180_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_notexit_stall_local;
wire local_bb1_notexit;
assign local_bb1_notexit = (local_bb1_var__u1 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_or_stall_local;
wire local_bb1_or;
assign local_bb1_or = (local_bb1_var__u1 | local_bb1_xor);
// This section implements an unregistered operation.
//
wire local_bb1_masked_stall_local;
wire local_bb1_masked;
assign local_bb1_masked = (local_bb1_var__u1 & local_bb1_first_cleanup);
// This section implements an unregistered operation.
//
wire local_bb1_cleanups_shl_stall_local;
wire [3:0] local_bb1_cleanups_shl;
assign local_bb1_cleanups_shl[3:1] = 3'h0;
assign local_bb1_cleanups_shl[0] = local_bb1_or;
// This section implements an unregistered operation.
//
wire local_bb1_next_cleanups_valid_out;
wire local_bb1_next_cleanups_stall_in;
reg local_bb1_next_cleanups_consumed_0_NO_SHIFT_REG;
wire local_bb1_first_cleanup_valid_out_2;
wire local_bb1_first_cleanup_stall_in_2;
reg local_bb1_first_cleanup_consumed_2_NO_SHIFT_REG;
wire local_bb1_masked_valid_out;
wire local_bb1_masked_stall_in;
reg local_bb1_masked_consumed_0_NO_SHIFT_REG;
wire local_bb1_first_cleanup_xor_or_valid_out;
wire local_bb1_first_cleanup_xor_or_stall_in;
reg local_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG;
wire local_bb1_indvars_iv_next17_valid_out_0;
wire local_bb1_indvars_iv_next17_stall_in_0;
reg local_bb1_indvars_iv_next17_consumed_0_NO_SHIFT_REG;
wire local_bb1_notexit_valid_out;
wire local_bb1_notexit_stall_in;
reg local_bb1_notexit_consumed_0_NO_SHIFT_REG;
wire local_bb1_next_cleanups_inputs_ready;
wire local_bb1_next_cleanups_stall_local;
wire [3:0] local_bb1_next_cleanups;
assign local_bb1_next_cleanups_inputs_ready = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_0 & rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_valid_out_1 & rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_valid_out_2);
assign local_bb1_next_cleanups = (rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7 << local_bb1_cleanups_shl);
assign local_bb1_next_cleanups_stall_local = ((local_bb1_next_cleanups_stall_in & ~(local_bb1_next_cleanups_consumed_0_NO_SHIFT_REG)) | (local_bb1_first_cleanup_stall_in_2 & ~(local_bb1_first_cleanup_consumed_2_NO_SHIFT_REG)) | (local_bb1_masked_stall_in & ~(local_bb1_masked_consumed_0_NO_SHIFT_REG)) | (local_bb1_first_cleanup_xor_or_stall_in & ~(local_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG)) | (local_bb1_indvars_iv_next17_stall_in_0 & ~(local_bb1_indvars_iv_next17_consumed_0_NO_SHIFT_REG)) | (local_bb1_notexit_stall_in & ~(local_bb1_notexit_consumed_0_NO_SHIFT_REG)));
assign local_bb1_next_cleanups_valid_out = (local_bb1_next_cleanups_inputs_ready & ~(local_bb1_next_cleanups_consumed_0_NO_SHIFT_REG));
assign local_bb1_first_cleanup_valid_out_2 = (local_bb1_next_cleanups_inputs_ready & ~(local_bb1_first_cleanup_consumed_2_NO_SHIFT_REG));
assign local_bb1_masked_valid_out = (local_bb1_next_cleanups_inputs_ready & ~(local_bb1_masked_consumed_0_NO_SHIFT_REG));
assign local_bb1_first_cleanup_xor_or_valid_out = (local_bb1_next_cleanups_inputs_ready & ~(local_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG));
assign local_bb1_indvars_iv_next17_valid_out_0 = (local_bb1_next_cleanups_inputs_ready & ~(local_bb1_indvars_iv_next17_consumed_0_NO_SHIFT_REG));
assign local_bb1_notexit_valid_out = (local_bb1_next_cleanups_inputs_ready & ~(local_bb1_notexit_consumed_0_NO_SHIFT_REG));
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_0 = (local_bb1_next_cleanups_stall_local | ~(local_bb1_next_cleanups_inputs_ready));
assign rstag_2to2_bb1_cleanups_pop55_acl_pop_i4_7_stall_in_1 = (local_bb1_next_cleanups_stall_local | ~(local_bb1_next_cleanups_inputs_ready));
assign rstag_2to2_bb1_indvars_iv16_pop52_acl_pop_i64_0_stall_in_2 = (local_bb1_next_cleanups_stall_local | ~(local_bb1_next_cleanups_inputs_ready));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_next_cleanups_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_first_cleanup_consumed_2_NO_SHIFT_REG <= 1'b0;
local_bb1_masked_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_indvars_iv_next17_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_notexit_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_next_cleanups_consumed_0_NO_SHIFT_REG <= (local_bb1_next_cleanups_inputs_ready & (local_bb1_next_cleanups_consumed_0_NO_SHIFT_REG | ~(local_bb1_next_cleanups_stall_in)) & local_bb1_next_cleanups_stall_local);
local_bb1_first_cleanup_consumed_2_NO_SHIFT_REG <= (local_bb1_next_cleanups_inputs_ready & (local_bb1_first_cleanup_consumed_2_NO_SHIFT_REG | ~(local_bb1_first_cleanup_stall_in_2)) & local_bb1_next_cleanups_stall_local);
local_bb1_masked_consumed_0_NO_SHIFT_REG <= (local_bb1_next_cleanups_inputs_ready & (local_bb1_masked_consumed_0_NO_SHIFT_REG | ~(local_bb1_masked_stall_in)) & local_bb1_next_cleanups_stall_local);
local_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG <= (local_bb1_next_cleanups_inputs_ready & (local_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG | ~(local_bb1_first_cleanup_xor_or_stall_in)) & local_bb1_next_cleanups_stall_local);
local_bb1_indvars_iv_next17_consumed_0_NO_SHIFT_REG <= (local_bb1_next_cleanups_inputs_ready & (local_bb1_indvars_iv_next17_consumed_0_NO_SHIFT_REG | ~(local_bb1_indvars_iv_next17_stall_in_0)) & local_bb1_next_cleanups_stall_local);
local_bb1_notexit_consumed_0_NO_SHIFT_REG <= (local_bb1_next_cleanups_inputs_ready & (local_bb1_notexit_consumed_0_NO_SHIFT_REG | ~(local_bb1_notexit_stall_in)) & local_bb1_next_cleanups_stall_local);
end
end
// This section implements a staging register.
//
wire rstag_2to2_bb1_next_cleanups_valid_out;
wire rstag_2to2_bb1_next_cleanups_stall_in;
wire rstag_2to2_bb1_next_cleanups_inputs_ready;
wire rstag_2to2_bb1_next_cleanups_stall_local;
reg rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG;
wire rstag_2to2_bb1_next_cleanups_combined_valid;
reg [3:0] rstag_2to2_bb1_next_cleanups_staging_reg_NO_SHIFT_REG;
wire [3:0] rstag_2to2_bb1_next_cleanups;
assign rstag_2to2_bb1_next_cleanups_inputs_ready = local_bb1_next_cleanups_valid_out;
assign rstag_2to2_bb1_next_cleanups = (rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG ? rstag_2to2_bb1_next_cleanups_staging_reg_NO_SHIFT_REG : local_bb1_next_cleanups);
assign rstag_2to2_bb1_next_cleanups_combined_valid = (rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG | rstag_2to2_bb1_next_cleanups_inputs_ready);
assign rstag_2to2_bb1_next_cleanups_valid_out = rstag_2to2_bb1_next_cleanups_combined_valid;
assign rstag_2to2_bb1_next_cleanups_stall_local = rstag_2to2_bb1_next_cleanups_stall_in;
assign local_bb1_next_cleanups_stall_in = (|rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_next_cleanups_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_2to2_bb1_next_cleanups_stall_local)
begin
if (~(rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG <= rstag_2to2_bb1_next_cleanups_inputs_ready;
end
end
else
begin
rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_2to2_bb1_next_cleanups_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_next_cleanups_staging_reg_NO_SHIFT_REG <= local_bb1_next_cleanups;
end
end
end
// Register node:
// * latency = 177
// * capacity = 177
logic rnode_2to179_bb1_masked_0_valid_out_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_stall_in_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_reg_179_inputs_ready_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_reg_179_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_valid_out_reg_179_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_stall_in_reg_179_NO_SHIFT_REG;
logic rnode_2to179_bb1_masked_0_stall_out_reg_179_NO_SHIFT_REG;
acl_data_fifo rnode_2to179_bb1_masked_0_reg_179_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_2to179_bb1_masked_0_reg_179_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_2to179_bb1_masked_0_stall_in_reg_179_NO_SHIFT_REG),
.valid_out(rnode_2to179_bb1_masked_0_valid_out_reg_179_NO_SHIFT_REG),
.stall_out(rnode_2to179_bb1_masked_0_stall_out_reg_179_NO_SHIFT_REG),
.data_in(local_bb1_masked),
.data_out(rnode_2to179_bb1_masked_0_reg_179_NO_SHIFT_REG)
);
defparam rnode_2to179_bb1_masked_0_reg_179_fifo.DEPTH = 178;
defparam rnode_2to179_bb1_masked_0_reg_179_fifo.DATA_WIDTH = 1;
defparam rnode_2to179_bb1_masked_0_reg_179_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_2to179_bb1_masked_0_reg_179_fifo.IMPL = "ram";
assign rnode_2to179_bb1_masked_0_reg_179_inputs_ready_NO_SHIFT_REG = local_bb1_masked_valid_out;
assign local_bb1_masked_stall_in = rnode_2to179_bb1_masked_0_stall_out_reg_179_NO_SHIFT_REG;
assign rnode_2to179_bb1_masked_0_NO_SHIFT_REG = rnode_2to179_bb1_masked_0_reg_179_NO_SHIFT_REG;
assign rnode_2to179_bb1_masked_0_stall_in_reg_179_NO_SHIFT_REG = rnode_2to179_bb1_masked_0_stall_in_NO_SHIFT_REG;
assign rnode_2to179_bb1_masked_0_valid_out_NO_SHIFT_REG = rnode_2to179_bb1_masked_0_valid_out_reg_179_NO_SHIFT_REG;
// This section implements a staging register.
//
wire rstag_2to2_bb1_first_cleanup_xor_or_valid_out_0;
wire rstag_2to2_bb1_first_cleanup_xor_or_stall_in_0;
reg rstag_2to2_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG;
wire rstag_2to2_bb1_first_cleanup_xor_or_valid_out_1;
wire rstag_2to2_bb1_first_cleanup_xor_or_stall_in_1;
reg rstag_2to2_bb1_first_cleanup_xor_or_consumed_1_NO_SHIFT_REG;
wire rstag_2to2_bb1_first_cleanup_xor_or_inputs_ready;
wire rstag_2to2_bb1_first_cleanup_xor_or_stall_local;
reg rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG;
wire rstag_2to2_bb1_first_cleanup_xor_or_combined_valid;
reg rstag_2to2_bb1_first_cleanup_xor_or_staging_reg_NO_SHIFT_REG;
wire rstag_2to2_bb1_first_cleanup_xor_or;
assign rstag_2to2_bb1_first_cleanup_xor_or_inputs_ready = local_bb1_first_cleanup_xor_or_valid_out;
assign rstag_2to2_bb1_first_cleanup_xor_or = (rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG ? rstag_2to2_bb1_first_cleanup_xor_or_staging_reg_NO_SHIFT_REG : local_bb1_first_cleanup_xor_or);
assign rstag_2to2_bb1_first_cleanup_xor_or_combined_valid = (rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG | rstag_2to2_bb1_first_cleanup_xor_or_inputs_ready);
assign rstag_2to2_bb1_first_cleanup_xor_or_stall_local = ((rstag_2to2_bb1_first_cleanup_xor_or_stall_in_0 & ~(rstag_2to2_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG)) | (rstag_2to2_bb1_first_cleanup_xor_or_stall_in_1 & ~(rstag_2to2_bb1_first_cleanup_xor_or_consumed_1_NO_SHIFT_REG)));
assign rstag_2to2_bb1_first_cleanup_xor_or_valid_out_0 = (rstag_2to2_bb1_first_cleanup_xor_or_combined_valid & ~(rstag_2to2_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG));
assign rstag_2to2_bb1_first_cleanup_xor_or_valid_out_1 = (rstag_2to2_bb1_first_cleanup_xor_or_combined_valid & ~(rstag_2to2_bb1_first_cleanup_xor_or_consumed_1_NO_SHIFT_REG));
assign local_bb1_first_cleanup_xor_or_stall_in = (|rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_first_cleanup_xor_or_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_2to2_bb1_first_cleanup_xor_or_stall_local)
begin
if (~(rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG <= rstag_2to2_bb1_first_cleanup_xor_or_inputs_ready;
end
end
else
begin
rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_2to2_bb1_first_cleanup_xor_or_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_first_cleanup_xor_or_staging_reg_NO_SHIFT_REG <= local_bb1_first_cleanup_xor_or;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_first_cleanup_xor_or_consumed_1_NO_SHIFT_REG <= 1'b0;
end
else
begin
rstag_2to2_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG <= (rstag_2to2_bb1_first_cleanup_xor_or_combined_valid & (rstag_2to2_bb1_first_cleanup_xor_or_consumed_0_NO_SHIFT_REG | ~(rstag_2to2_bb1_first_cleanup_xor_or_stall_in_0)) & rstag_2to2_bb1_first_cleanup_xor_or_stall_local);
rstag_2to2_bb1_first_cleanup_xor_or_consumed_1_NO_SHIFT_REG <= (rstag_2to2_bb1_first_cleanup_xor_or_combined_valid & (rstag_2to2_bb1_first_cleanup_xor_or_consumed_1_NO_SHIFT_REG | ~(rstag_2to2_bb1_first_cleanup_xor_or_stall_in_1)) & rstag_2to2_bb1_first_cleanup_xor_or_stall_local);
end
end
// This section implements a registered operation.
//
wire local_bb1_indvars_iv16_push52_indvars_iv_next17_inputs_ready;
reg local_bb1_indvars_iv16_push52_indvars_iv_next17_valid_out_NO_SHIFT_REG;
wire local_bb1_indvars_iv16_push52_indvars_iv_next17_stall_in;
wire local_bb1_indvars_iv16_push52_indvars_iv_next17_output_regs_ready;
wire [63:0] local_bb1_indvars_iv16_push52_indvars_iv_next17_result;
wire local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_valid_out;
wire local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_stall_out;
reg [63:0] local_bb1_indvars_iv16_push52_indvars_iv_next17_NO_SHIFT_REG;
wire local_bb1_indvars_iv16_push52_indvars_iv_next17_causedstall;
acl_push local_bb1_indvars_iv16_push52_indvars_iv_next17_feedback (
.clock(clock),
.resetn(resetn),
.dir(rstag_2to2_bb1_keep_going_forked),
.predicate(1'b0),
.data_in(local_bb1_indvars_iv_next17),
.stall_out(local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_stall_out),
.valid_in(local_bb1_indvars_iv16_push52_indvars_iv_next17_inputs_ready),
.valid_out(local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_valid_out),
.stall_in(~(local_bb1_indvars_iv16_push52_indvars_iv_next17_output_regs_ready)),
.data_out(local_bb1_indvars_iv16_push52_indvars_iv_next17_result),
.feedback_out(feedback_data_out_52),
.feedback_valid_out(feedback_valid_out_52),
.feedback_stall_in(feedback_stall_in_52)
);
defparam local_bb1_indvars_iv16_push52_indvars_iv_next17_feedback.STALLFREE = 0;
defparam local_bb1_indvars_iv16_push52_indvars_iv_next17_feedback.DATA_WIDTH = 64;
defparam local_bb1_indvars_iv16_push52_indvars_iv_next17_feedback.FIFO_DEPTH = 2;
defparam local_bb1_indvars_iv16_push52_indvars_iv_next17_feedback.MIN_FIFO_LATENCY = 0;
defparam local_bb1_indvars_iv16_push52_indvars_iv_next17_feedback.STYLE = "REGULAR";
assign local_bb1_indvars_iv16_push52_indvars_iv_next17_inputs_ready = (local_bb1_indvars_iv_next17_valid_out_0 & rstag_2to2_bb1_keep_going_forked_valid_out_3);
assign local_bb1_indvars_iv16_push52_indvars_iv_next17_output_regs_ready = (&(~(local_bb1_indvars_iv16_push52_indvars_iv_next17_valid_out_NO_SHIFT_REG) | ~(local_bb1_indvars_iv16_push52_indvars_iv_next17_stall_in)));
assign local_bb1_indvars_iv_next17_stall_in_0 = (local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_stall_out | ~(local_bb1_indvars_iv16_push52_indvars_iv_next17_inputs_ready));
assign rstag_2to2_bb1_keep_going_forked_stall_in_3 = (local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_stall_out | ~(local_bb1_indvars_iv16_push52_indvars_iv_next17_inputs_ready));
assign local_bb1_indvars_iv16_push52_indvars_iv_next17_causedstall = (local_bb1_indvars_iv16_push52_indvars_iv_next17_inputs_ready && (local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_stall_out && !(~(local_bb1_indvars_iv16_push52_indvars_iv_next17_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_indvars_iv16_push52_indvars_iv_next17_NO_SHIFT_REG <= 'x;
local_bb1_indvars_iv16_push52_indvars_iv_next17_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_indvars_iv16_push52_indvars_iv_next17_output_regs_ready)
begin
local_bb1_indvars_iv16_push52_indvars_iv_next17_NO_SHIFT_REG <= local_bb1_indvars_iv16_push52_indvars_iv_next17_result;
local_bb1_indvars_iv16_push52_indvars_iv_next17_valid_out_NO_SHIFT_REG <= local_bb1_indvars_iv16_push52_indvars_iv_next17_fu_valid_out;
end
else
begin
if (~(local_bb1_indvars_iv16_push52_indvars_iv_next17_stall_in))
begin
local_bb1_indvars_iv16_push52_indvars_iv_next17_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a staging register.
//
wire rstag_2to2_bb1_notexit_valid_out;
wire rstag_2to2_bb1_notexit_stall_in;
wire rstag_2to2_bb1_notexit_inputs_ready;
wire rstag_2to2_bb1_notexit_stall_local;
reg rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG;
wire rstag_2to2_bb1_notexit_combined_valid;
reg rstag_2to2_bb1_notexit_staging_reg_NO_SHIFT_REG;
wire rstag_2to2_bb1_notexit;
assign rstag_2to2_bb1_notexit_inputs_ready = local_bb1_notexit_valid_out;
assign rstag_2to2_bb1_notexit = (rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG ? rstag_2to2_bb1_notexit_staging_reg_NO_SHIFT_REG : local_bb1_notexit);
assign rstag_2to2_bb1_notexit_combined_valid = (rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG | rstag_2to2_bb1_notexit_inputs_ready);
assign rstag_2to2_bb1_notexit_valid_out = rstag_2to2_bb1_notexit_combined_valid;
assign rstag_2to2_bb1_notexit_stall_local = rstag_2to2_bb1_notexit_stall_in;
assign local_bb1_notexit_stall_in = (|rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_2to2_bb1_notexit_staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_2to2_bb1_notexit_stall_local)
begin
if (~(rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG <= rstag_2to2_bb1_notexit_inputs_ready;
end
end
else
begin
rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_2to2_bb1_notexit_staging_valid_NO_SHIFT_REG))
begin
rstag_2to2_bb1_notexit_staging_reg_NO_SHIFT_REG <= local_bb1_notexit;
end
end
end
// This section implements a registered operation.
//
wire local_bb1_cleanups_push55_next_cleanups_inputs_ready;
reg local_bb1_cleanups_push55_next_cleanups_valid_out_NO_SHIFT_REG;
wire local_bb1_cleanups_push55_next_cleanups_stall_in;
wire local_bb1_cleanups_push55_next_cleanups_output_regs_ready;
wire [3:0] local_bb1_cleanups_push55_next_cleanups_result;
wire local_bb1_cleanups_push55_next_cleanups_fu_valid_out;
wire local_bb1_cleanups_push55_next_cleanups_fu_stall_out;
reg [3:0] local_bb1_cleanups_push55_next_cleanups_NO_SHIFT_REG;
wire local_bb1_cleanups_push55_next_cleanups_causedstall;
acl_push local_bb1_cleanups_push55_next_cleanups_feedback (
.clock(clock),
.resetn(resetn),
.dir(rstag_2to2_bb1_keep_going_forked),
.predicate(1'b0),
.data_in(rstag_2to2_bb1_next_cleanups),
.stall_out(local_bb1_cleanups_push55_next_cleanups_fu_stall_out),
.valid_in(local_bb1_cleanups_push55_next_cleanups_inputs_ready),
.valid_out(local_bb1_cleanups_push55_next_cleanups_fu_valid_out),
.stall_in(~(local_bb1_cleanups_push55_next_cleanups_output_regs_ready)),
.data_out(local_bb1_cleanups_push55_next_cleanups_result),
.feedback_out(feedback_data_out_55),
.feedback_valid_out(feedback_valid_out_55),
.feedback_stall_in(feedback_stall_in_55)
);
defparam local_bb1_cleanups_push55_next_cleanups_feedback.STALLFREE = 0;
defparam local_bb1_cleanups_push55_next_cleanups_feedback.DATA_WIDTH = 4;
defparam local_bb1_cleanups_push55_next_cleanups_feedback.FIFO_DEPTH = 2;
defparam local_bb1_cleanups_push55_next_cleanups_feedback.MIN_FIFO_LATENCY = 0;
defparam local_bb1_cleanups_push55_next_cleanups_feedback.STYLE = "REGULAR";
assign local_bb1_cleanups_push55_next_cleanups_inputs_ready = (rstag_2to2_bb1_next_cleanups_valid_out & rstag_2to2_bb1_keep_going_forked_valid_out_1);
assign local_bb1_cleanups_push55_next_cleanups_output_regs_ready = (&(~(local_bb1_cleanups_push55_next_cleanups_valid_out_NO_SHIFT_REG) | ~(local_bb1_cleanups_push55_next_cleanups_stall_in)));
assign rstag_2to2_bb1_next_cleanups_stall_in = (local_bb1_cleanups_push55_next_cleanups_fu_stall_out | ~(local_bb1_cleanups_push55_next_cleanups_inputs_ready));
assign rstag_2to2_bb1_keep_going_forked_stall_in_1 = (local_bb1_cleanups_push55_next_cleanups_fu_stall_out | ~(local_bb1_cleanups_push55_next_cleanups_inputs_ready));
assign local_bb1_cleanups_push55_next_cleanups_causedstall = (local_bb1_cleanups_push55_next_cleanups_inputs_ready && (local_bb1_cleanups_push55_next_cleanups_fu_stall_out && !(~(local_bb1_cleanups_push55_next_cleanups_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_cleanups_push55_next_cleanups_NO_SHIFT_REG <= 'x;
local_bb1_cleanups_push55_next_cleanups_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_cleanups_push55_next_cleanups_output_regs_ready)
begin
local_bb1_cleanups_push55_next_cleanups_NO_SHIFT_REG <= local_bb1_cleanups_push55_next_cleanups_result;
local_bb1_cleanups_push55_next_cleanups_valid_out_NO_SHIFT_REG <= local_bb1_cleanups_push55_next_cleanups_fu_valid_out;
end
else
begin
if (~(local_bb1_cleanups_push55_next_cleanups_stall_in))
begin
local_bb1_cleanups_push55_next_cleanups_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_179to180_bb1_masked_0_valid_out_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_stall_in_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_reg_180_inputs_ready_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_valid_out_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_stall_in_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_masked_0_stall_out_reg_180_NO_SHIFT_REG;
acl_data_fifo rnode_179to180_bb1_masked_0_reg_180_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_179to180_bb1_masked_0_reg_180_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_179to180_bb1_masked_0_stall_in_reg_180_NO_SHIFT_REG),
.valid_out(rnode_179to180_bb1_masked_0_valid_out_reg_180_NO_SHIFT_REG),
.stall_out(rnode_179to180_bb1_masked_0_stall_out_reg_180_NO_SHIFT_REG),
.data_in(rnode_2to179_bb1_masked_0_NO_SHIFT_REG),
.data_out(rnode_179to180_bb1_masked_0_reg_180_NO_SHIFT_REG)
);
defparam rnode_179to180_bb1_masked_0_reg_180_fifo.DEPTH = 2;
defparam rnode_179to180_bb1_masked_0_reg_180_fifo.DATA_WIDTH = 1;
defparam rnode_179to180_bb1_masked_0_reg_180_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_179to180_bb1_masked_0_reg_180_fifo.IMPL = "ll_reg";
assign rnode_179to180_bb1_masked_0_reg_180_inputs_ready_NO_SHIFT_REG = rnode_2to179_bb1_masked_0_valid_out_NO_SHIFT_REG;
assign rnode_2to179_bb1_masked_0_stall_in_NO_SHIFT_REG = rnode_179to180_bb1_masked_0_stall_out_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_masked_0_NO_SHIFT_REG = rnode_179to180_bb1_masked_0_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_masked_0_stall_in_reg_180_NO_SHIFT_REG = rnode_179to180_bb1_masked_0_stall_in_NO_SHIFT_REG;
assign rnode_179to180_bb1_masked_0_valid_out_NO_SHIFT_REG = rnode_179to180_bb1_masked_0_valid_out_reg_180_NO_SHIFT_REG;
// Register node:
// * latency = 173
// * capacity = 173
logic rnode_2to175_bb1_first_cleanup_xor_or_0_valid_out_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_stall_in_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_inputs_ready_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_valid_out_reg_175_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_stall_in_reg_175_NO_SHIFT_REG;
logic rnode_2to175_bb1_first_cleanup_xor_or_0_stall_out_reg_175_NO_SHIFT_REG;
acl_data_fifo rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_2to175_bb1_first_cleanup_xor_or_0_stall_in_reg_175_NO_SHIFT_REG),
.valid_out(rnode_2to175_bb1_first_cleanup_xor_or_0_valid_out_reg_175_NO_SHIFT_REG),
.stall_out(rnode_2to175_bb1_first_cleanup_xor_or_0_stall_out_reg_175_NO_SHIFT_REG),
.data_in(rstag_2to2_bb1_first_cleanup_xor_or),
.data_out(rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_NO_SHIFT_REG)
);
defparam rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_fifo.DEPTH = 174;
defparam rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_fifo.DATA_WIDTH = 1;
defparam rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_fifo.IMPL = "ram";
assign rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_inputs_ready_NO_SHIFT_REG = rstag_2to2_bb1_first_cleanup_xor_or_valid_out_0;
assign rstag_2to2_bb1_first_cleanup_xor_or_stall_in_0 = rnode_2to175_bb1_first_cleanup_xor_or_0_stall_out_reg_175_NO_SHIFT_REG;
assign rnode_2to175_bb1_first_cleanup_xor_or_0_NO_SHIFT_REG = rnode_2to175_bb1_first_cleanup_xor_or_0_reg_175_NO_SHIFT_REG;
assign rnode_2to175_bb1_first_cleanup_xor_or_0_stall_in_reg_175_NO_SHIFT_REG = rnode_2to175_bb1_first_cleanup_xor_or_0_stall_in_NO_SHIFT_REG;
assign rnode_2to175_bb1_first_cleanup_xor_or_0_valid_out_NO_SHIFT_REG = rnode_2to175_bb1_first_cleanup_xor_or_0_valid_out_reg_175_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_ld__inputs_ready;
reg local_bb1_ld__valid_out_NO_SHIFT_REG;
wire local_bb1_ld__stall_in;
wire local_bb1_ld__output_regs_ready;
wire local_bb1_ld__fu_stall_out;
wire local_bb1_ld__fu_valid_out;
wire [7:0] local_bb1_ld__lsu_dataout;
reg [7:0] local_bb1_ld__NO_SHIFT_REG;
wire local_bb1_ld__causedstall;
lsu_top lsu_local_bb1_ld_ (
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.flush(start),
.stream_base_addr(),
.stream_size(),
.stream_reset(),
.o_stall(local_bb1_ld__fu_stall_out),
.i_valid(local_bb1_ld__inputs_ready),
.i_address(local_bb1_arrayidx5),
.i_writedata(),
.i_cmpdata(),
.i_predicate(rstag_2to2_bb1_first_cleanup_xor_or),
.i_bitwiseor(64'h0),
.i_byteenable(),
.i_stall(~(local_bb1_ld__output_regs_ready)),
.o_valid(local_bb1_ld__fu_valid_out),
.o_readdata(local_bb1_ld__lsu_dataout),
.o_input_fifo_depth(),
.o_writeack(),
.i_atomic_op(3'h0),
.o_active(local_bb1_ld__active),
.avm_address(avm_local_bb1_ld__address),
.avm_read(avm_local_bb1_ld__read),
.avm_readdata(avm_local_bb1_ld__readdata),
.avm_write(avm_local_bb1_ld__write),
.avm_writeack(avm_local_bb1_ld__writeack),
.avm_burstcount(avm_local_bb1_ld__burstcount),
.avm_writedata(avm_local_bb1_ld__writedata),
.avm_byteenable(avm_local_bb1_ld__byteenable),
.avm_waitrequest(avm_local_bb1_ld__waitrequest),
.avm_readdatavalid(avm_local_bb1_ld__readdatavalid),
.profile_bw(),
.profile_bw_incr(),
.profile_total_ivalid(),
.profile_total_req(),
.profile_i_stall_count(),
.profile_o_stall_count(),
.profile_avm_readwrite_count(),
.profile_avm_burstcount_total(),
.profile_avm_burstcount_total_incr(),
.profile_req_cache_hit_count(),
.profile_extra_unaligned_reqs(),
.profile_avm_stall()
);
defparam lsu_local_bb1_ld_.AWIDTH = 30;
defparam lsu_local_bb1_ld_.WIDTH_BYTES = 1;
defparam lsu_local_bb1_ld_.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld_.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld_.ALIGNMENT_BYTES = 1;
defparam lsu_local_bb1_ld_.READ = 1;
defparam lsu_local_bb1_ld_.ATOMIC = 0;
defparam lsu_local_bb1_ld_.WIDTH = 8;
defparam lsu_local_bb1_ld_.MWIDTH = 256;
defparam lsu_local_bb1_ld_.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_ld_.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_ld_.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_ld_.MEMORY_SIDE_MEM_LATENCY = 73;
defparam lsu_local_bb1_ld_.USE_WRITE_ACK = 0;
defparam lsu_local_bb1_ld_.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_ld_.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_ld_.NUMBER_BANKS = 1;
defparam lsu_local_bb1_ld_.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_ld_.USEINPUTFIFO = 0;
defparam lsu_local_bb1_ld_.USECACHING = 0;
defparam lsu_local_bb1_ld_.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_ld_.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_ld_.HIGH_FMAX = 1;
defparam lsu_local_bb1_ld_.ADDRSPACE = 1;
defparam lsu_local_bb1_ld_.STYLE = "BURST-COALESCED";
assign local_bb1_ld__inputs_ready = (local_bb1_arrayidx5_valid_out & rstag_2to2_bb1_first_cleanup_xor_or_valid_out_1);
assign local_bb1_ld__output_regs_ready = (&(~(local_bb1_ld__valid_out_NO_SHIFT_REG) | ~(local_bb1_ld__stall_in)));
assign local_bb1_arrayidx5_stall_in = (local_bb1_ld__fu_stall_out | ~(local_bb1_ld__inputs_ready));
assign rstag_2to2_bb1_first_cleanup_xor_or_stall_in_1 = (local_bb1_ld__fu_stall_out | ~(local_bb1_ld__inputs_ready));
assign local_bb1_ld__causedstall = (local_bb1_ld__inputs_ready && (local_bb1_ld__fu_stall_out && !(~(local_bb1_ld__output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_ld__NO_SHIFT_REG <= 'x;
local_bb1_ld__valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_ld__output_regs_ready)
begin
local_bb1_ld__NO_SHIFT_REG <= local_bb1_ld__lsu_dataout;
local_bb1_ld__valid_out_NO_SHIFT_REG <= local_bb1_ld__fu_valid_out;
end
else
begin
if (~(local_bb1_ld__stall_in))
begin
local_bb1_ld__valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 176
// * capacity = 176
logic rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_NO_SHIFT_REG;
logic rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_NO_SHIFT_REG;
logic [63:0] rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_NO_SHIFT_REG;
logic rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_inputs_ready_NO_SHIFT_REG;
logic [63:0] rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_out_reg_179_NO_SHIFT_REG;
acl_data_fifo rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_reg_179_NO_SHIFT_REG),
.valid_out(rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_reg_179_NO_SHIFT_REG),
.stall_out(rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_out_reg_179_NO_SHIFT_REG),
.data_in(local_bb1_indvars_iv16_push52_indvars_iv_next17_NO_SHIFT_REG),
.data_out(rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_NO_SHIFT_REG)
);
defparam rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_fifo.DEPTH = 177;
defparam rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_fifo.DATA_WIDTH = 64;
defparam rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_fifo.IMPL = "ram";
assign rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_inputs_ready_NO_SHIFT_REG = local_bb1_indvars_iv16_push52_indvars_iv_next17_valid_out_NO_SHIFT_REG;
assign local_bb1_indvars_iv16_push52_indvars_iv_next17_stall_in = rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_out_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_NO_SHIFT_REG = rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_reg_179_NO_SHIFT_REG = rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_NO_SHIFT_REG;
assign rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_NO_SHIFT_REG = rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_reg_179_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_notexitcond_notexit_inputs_ready;
reg local_bb1_notexitcond_notexit_valid_out_NO_SHIFT_REG;
wire local_bb1_notexitcond_notexit_stall_in;
wire local_bb1_notexitcond_notexit_output_regs_ready;
wire local_bb1_notexitcond_notexit_result;
wire local_bb1_notexitcond_notexit_fu_valid_out;
wire local_bb1_notexitcond_notexit_fu_stall_out;
reg local_bb1_notexitcond_notexit_NO_SHIFT_REG;
wire local_bb1_notexitcond_notexit_causedstall;
acl_push local_bb1_notexitcond_notexit_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_first_cleanup),
.predicate(1'b0),
.data_in(rstag_2to2_bb1_notexit),
.stall_out(local_bb1_notexitcond_notexit_fu_stall_out),
.valid_in(local_bb1_notexitcond_notexit_inputs_ready),
.valid_out(local_bb1_notexitcond_notexit_fu_valid_out),
.stall_in(~(local_bb1_notexitcond_notexit_output_regs_ready)),
.data_out(local_bb1_notexitcond_notexit_result),
.feedback_out(feedback_data_out_1),
.feedback_valid_out(feedback_valid_out_1),
.feedback_stall_in(feedback_stall_in_1)
);
defparam local_bb1_notexitcond_notexit_feedback.STALLFREE = 0;
defparam local_bb1_notexitcond_notexit_feedback.DATA_WIDTH = 1;
defparam local_bb1_notexitcond_notexit_feedback.FIFO_DEPTH = 4;
defparam local_bb1_notexitcond_notexit_feedback.MIN_FIFO_LATENCY = 2;
defparam local_bb1_notexitcond_notexit_feedback.STYLE = "REGULAR";
assign local_bb1_notexitcond_notexit_inputs_ready = (local_bb1_first_cleanup_valid_out_2 & rstag_2to2_bb1_notexit_valid_out);
assign local_bb1_notexitcond_notexit_output_regs_ready = (&(~(local_bb1_notexitcond_notexit_valid_out_NO_SHIFT_REG) | ~(local_bb1_notexitcond_notexit_stall_in)));
assign local_bb1_first_cleanup_stall_in_2 = (local_bb1_notexitcond_notexit_fu_stall_out | ~(local_bb1_notexitcond_notexit_inputs_ready));
assign rstag_2to2_bb1_notexit_stall_in = (local_bb1_notexitcond_notexit_fu_stall_out | ~(local_bb1_notexitcond_notexit_inputs_ready));
assign local_bb1_notexitcond_notexit_causedstall = (local_bb1_notexitcond_notexit_inputs_ready && (local_bb1_notexitcond_notexit_fu_stall_out && !(~(local_bb1_notexitcond_notexit_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_notexitcond_notexit_NO_SHIFT_REG <= 'x;
local_bb1_notexitcond_notexit_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_notexitcond_notexit_output_regs_ready)
begin
local_bb1_notexitcond_notexit_NO_SHIFT_REG <= local_bb1_notexitcond_notexit_result;
local_bb1_notexitcond_notexit_valid_out_NO_SHIFT_REG <= local_bb1_notexitcond_notexit_fu_valid_out;
end
else
begin
if (~(local_bb1_notexitcond_notexit_stall_in))
begin
local_bb1_notexitcond_notexit_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 176
// * capacity = 176
logic rnode_3to179_bb1_cleanups_push55_next_cleanups_0_valid_out_NO_SHIFT_REG;
logic rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_in_NO_SHIFT_REG;
logic [3:0] rnode_3to179_bb1_cleanups_push55_next_cleanups_0_NO_SHIFT_REG;
logic rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_inputs_ready_NO_SHIFT_REG;
logic [3:0] rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_cleanups_push55_next_cleanups_0_valid_out_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_in_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_out_reg_179_NO_SHIFT_REG;
acl_data_fifo rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_in_reg_179_NO_SHIFT_REG),
.valid_out(rnode_3to179_bb1_cleanups_push55_next_cleanups_0_valid_out_reg_179_NO_SHIFT_REG),
.stall_out(rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_out_reg_179_NO_SHIFT_REG),
.data_in(local_bb1_cleanups_push55_next_cleanups_NO_SHIFT_REG),
.data_out(rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_NO_SHIFT_REG)
);
defparam rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_fifo.DEPTH = 177;
defparam rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_fifo.DATA_WIDTH = 4;
defparam rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_fifo.IMPL = "ram";
assign rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_inputs_ready_NO_SHIFT_REG = local_bb1_cleanups_push55_next_cleanups_valid_out_NO_SHIFT_REG;
assign local_bb1_cleanups_push55_next_cleanups_stall_in = rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_out_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_cleanups_push55_next_cleanups_0_NO_SHIFT_REG = rnode_3to179_bb1_cleanups_push55_next_cleanups_0_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_in_reg_179_NO_SHIFT_REG = rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_in_NO_SHIFT_REG;
assign rnode_3to179_bb1_cleanups_push55_next_cleanups_0_valid_out_NO_SHIFT_REG = rnode_3to179_bb1_cleanups_push55_next_cleanups_0_valid_out_reg_179_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_175to176_bb1_first_cleanup_xor_or_0_valid_out_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_stall_in_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_inputs_ready_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_valid_out_reg_176_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_stall_in_reg_176_NO_SHIFT_REG;
logic rnode_175to176_bb1_first_cleanup_xor_or_0_stall_out_reg_176_NO_SHIFT_REG;
acl_data_fifo rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_175to176_bb1_first_cleanup_xor_or_0_stall_in_reg_176_NO_SHIFT_REG),
.valid_out(rnode_175to176_bb1_first_cleanup_xor_or_0_valid_out_reg_176_NO_SHIFT_REG),
.stall_out(rnode_175to176_bb1_first_cleanup_xor_or_0_stall_out_reg_176_NO_SHIFT_REG),
.data_in(rnode_2to175_bb1_first_cleanup_xor_or_0_NO_SHIFT_REG),
.data_out(rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_NO_SHIFT_REG)
);
defparam rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_fifo.DEPTH = 2;
defparam rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_fifo.DATA_WIDTH = 1;
defparam rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_fifo.IMPL = "ll_reg";
assign rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_inputs_ready_NO_SHIFT_REG = rnode_2to175_bb1_first_cleanup_xor_or_0_valid_out_NO_SHIFT_REG;
assign rnode_2to175_bb1_first_cleanup_xor_or_0_stall_in_NO_SHIFT_REG = rnode_175to176_bb1_first_cleanup_xor_or_0_stall_out_reg_176_NO_SHIFT_REG;
assign rnode_175to176_bb1_first_cleanup_xor_or_0_NO_SHIFT_REG = rnode_175to176_bb1_first_cleanup_xor_or_0_reg_176_NO_SHIFT_REG;
assign rnode_175to176_bb1_first_cleanup_xor_or_0_stall_in_reg_176_NO_SHIFT_REG = rnode_175to176_bb1_first_cleanup_xor_or_0_stall_in_NO_SHIFT_REG;
assign rnode_175to176_bb1_first_cleanup_xor_or_0_valid_out_NO_SHIFT_REG = rnode_175to176_bb1_first_cleanup_xor_or_0_valid_out_reg_176_NO_SHIFT_REG;
// This section implements a staging register.
//
wire rstag_162to162_bb1_ld__valid_out;
wire rstag_162to162_bb1_ld__stall_in;
wire rstag_162to162_bb1_ld__inputs_ready;
wire rstag_162to162_bb1_ld__stall_local;
reg rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG;
wire rstag_162to162_bb1_ld__combined_valid;
reg [7:0] rstag_162to162_bb1_ld__staging_reg_NO_SHIFT_REG;
wire [7:0] rstag_162to162_bb1_ld_;
assign rstag_162to162_bb1_ld__inputs_ready = local_bb1_ld__valid_out_NO_SHIFT_REG;
assign rstag_162to162_bb1_ld_ = (rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG ? rstag_162to162_bb1_ld__staging_reg_NO_SHIFT_REG : local_bb1_ld__NO_SHIFT_REG);
assign rstag_162to162_bb1_ld__combined_valid = (rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG | rstag_162to162_bb1_ld__inputs_ready);
assign rstag_162to162_bb1_ld__valid_out = rstag_162to162_bb1_ld__combined_valid;
assign rstag_162to162_bb1_ld__stall_local = rstag_162to162_bb1_ld__stall_in;
assign local_bb1_ld__stall_in = (|rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
rstag_162to162_bb1_ld__staging_reg_NO_SHIFT_REG <= 'x;
end
else
begin
if (rstag_162to162_bb1_ld__stall_local)
begin
if (~(rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG))
begin
rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG <= rstag_162to162_bb1_ld__inputs_ready;
end
end
else
begin
rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
end
if (~(rstag_162to162_bb1_ld__staging_valid_NO_SHIFT_REG))
begin
rstag_162to162_bb1_ld__staging_reg_NO_SHIFT_REG <= local_bb1_ld__NO_SHIFT_REG;
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_NO_SHIFT_REG;
logic rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_NO_SHIFT_REG;
logic [63:0] rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_NO_SHIFT_REG;
logic rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_inputs_ready_NO_SHIFT_REG;
logic [63:0] rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_out_reg_180_NO_SHIFT_REG;
acl_data_fifo rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_reg_180_NO_SHIFT_REG),
.valid_out(rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_reg_180_NO_SHIFT_REG),
.stall_out(rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_out_reg_180_NO_SHIFT_REG),
.data_in(rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_NO_SHIFT_REG),
.data_out(rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_NO_SHIFT_REG)
);
defparam rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_fifo.DEPTH = 2;
defparam rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_fifo.DATA_WIDTH = 64;
defparam rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_fifo.IMPL = "ll_reg";
assign rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_inputs_ready_NO_SHIFT_REG = rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_NO_SHIFT_REG;
assign rnode_3to179_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_NO_SHIFT_REG = rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_out_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_NO_SHIFT_REG = rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_reg_180_NO_SHIFT_REG = rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_NO_SHIFT_REG;
assign rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_NO_SHIFT_REG = rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_reg_180_NO_SHIFT_REG;
// Register node:
// * latency = 176
// * capacity = 176
logic rnode_3to179_bb1_notexitcond_notexit_0_valid_out_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_stall_in_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_reg_179_inputs_ready_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_valid_out_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_stall_in_reg_179_NO_SHIFT_REG;
logic rnode_3to179_bb1_notexitcond_notexit_0_stall_out_reg_179_NO_SHIFT_REG;
acl_data_fifo rnode_3to179_bb1_notexitcond_notexit_0_reg_179_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_3to179_bb1_notexitcond_notexit_0_reg_179_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_3to179_bb1_notexitcond_notexit_0_stall_in_reg_179_NO_SHIFT_REG),
.valid_out(rnode_3to179_bb1_notexitcond_notexit_0_valid_out_reg_179_NO_SHIFT_REG),
.stall_out(rnode_3to179_bb1_notexitcond_notexit_0_stall_out_reg_179_NO_SHIFT_REG),
.data_in(local_bb1_notexitcond_notexit_NO_SHIFT_REG),
.data_out(rnode_3to179_bb1_notexitcond_notexit_0_reg_179_NO_SHIFT_REG)
);
defparam rnode_3to179_bb1_notexitcond_notexit_0_reg_179_fifo.DEPTH = 177;
defparam rnode_3to179_bb1_notexitcond_notexit_0_reg_179_fifo.DATA_WIDTH = 1;
defparam rnode_3to179_bb1_notexitcond_notexit_0_reg_179_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_3to179_bb1_notexitcond_notexit_0_reg_179_fifo.IMPL = "ram";
assign rnode_3to179_bb1_notexitcond_notexit_0_reg_179_inputs_ready_NO_SHIFT_REG = local_bb1_notexitcond_notexit_valid_out_NO_SHIFT_REG;
assign local_bb1_notexitcond_notexit_stall_in = rnode_3to179_bb1_notexitcond_notexit_0_stall_out_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_notexitcond_notexit_0_NO_SHIFT_REG = rnode_3to179_bb1_notexitcond_notexit_0_reg_179_NO_SHIFT_REG;
assign rnode_3to179_bb1_notexitcond_notexit_0_stall_in_reg_179_NO_SHIFT_REG = rnode_3to179_bb1_notexitcond_notexit_0_stall_in_NO_SHIFT_REG;
assign rnode_3to179_bb1_notexitcond_notexit_0_valid_out_NO_SHIFT_REG = rnode_3to179_bb1_notexitcond_notexit_0_valid_out_reg_179_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_179to180_bb1_cleanups_push55_next_cleanups_0_valid_out_NO_SHIFT_REG;
logic rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_in_NO_SHIFT_REG;
logic [3:0] rnode_179to180_bb1_cleanups_push55_next_cleanups_0_NO_SHIFT_REG;
logic rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_inputs_ready_NO_SHIFT_REG;
logic [3:0] rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_cleanups_push55_next_cleanups_0_valid_out_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_in_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_out_reg_180_NO_SHIFT_REG;
acl_data_fifo rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_in_reg_180_NO_SHIFT_REG),
.valid_out(rnode_179to180_bb1_cleanups_push55_next_cleanups_0_valid_out_reg_180_NO_SHIFT_REG),
.stall_out(rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_out_reg_180_NO_SHIFT_REG),
.data_in(rnode_3to179_bb1_cleanups_push55_next_cleanups_0_NO_SHIFT_REG),
.data_out(rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_NO_SHIFT_REG)
);
defparam rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_fifo.DEPTH = 2;
defparam rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_fifo.DATA_WIDTH = 4;
defparam rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_fifo.IMPL = "ll_reg";
assign rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_inputs_ready_NO_SHIFT_REG = rnode_3to179_bb1_cleanups_push55_next_cleanups_0_valid_out_NO_SHIFT_REG;
assign rnode_3to179_bb1_cleanups_push55_next_cleanups_0_stall_in_NO_SHIFT_REG = rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_out_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_cleanups_push55_next_cleanups_0_NO_SHIFT_REG = rnode_179to180_bb1_cleanups_push55_next_cleanups_0_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_in_reg_180_NO_SHIFT_REG = rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_in_NO_SHIFT_REG;
assign rnode_179to180_bb1_cleanups_push55_next_cleanups_0_valid_out_NO_SHIFT_REG = rnode_179to180_bb1_cleanups_push55_next_cleanups_0_valid_out_reg_180_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_c0_eni3_valid_out;
wire local_bb1_c0_eni3_stall_in;
wire local_bb1_c0_eni3_inputs_ready;
wire local_bb1_c0_eni3_stall_local;
wire [31:0] local_bb1_c0_eni3;
assign local_bb1_c0_eni3_inputs_ready = (rnode_161to162_forked_0_valid_out_0_NO_SHIFT_REG & rnode_161to162_bb1_keep_going_forked_0_valid_out_0_NO_SHIFT_REG & rstag_162to162_bb1_ld__valid_out);
assign local_bb1_c0_eni3[23:0] = local_bb1_c0_eni2[23:0];
assign local_bb1_c0_eni3[31:24] = rstag_162to162_bb1_ld_;
assign local_bb1_c0_eni3_valid_out = local_bb1_c0_eni3_inputs_ready;
assign local_bb1_c0_eni3_stall_local = local_bb1_c0_eni3_stall_in;
assign rnode_161to162_forked_0_stall_in_0_NO_SHIFT_REG = (local_bb1_c0_eni3_stall_local | ~(local_bb1_c0_eni3_inputs_ready));
assign rnode_161to162_bb1_keep_going_forked_0_stall_in_0_NO_SHIFT_REG = (local_bb1_c0_eni3_stall_local | ~(local_bb1_c0_eni3_inputs_ready));
assign rstag_162to162_bb1_ld__stall_in = (local_bb1_c0_eni3_stall_local | ~(local_bb1_c0_eni3_inputs_ready));
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_179to180_bb1_notexitcond_notexit_0_valid_out_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_stall_in_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_reg_180_inputs_ready_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_valid_out_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_stall_in_reg_180_NO_SHIFT_REG;
logic rnode_179to180_bb1_notexitcond_notexit_0_stall_out_reg_180_NO_SHIFT_REG;
acl_data_fifo rnode_179to180_bb1_notexitcond_notexit_0_reg_180_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_179to180_bb1_notexitcond_notexit_0_reg_180_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_179to180_bb1_notexitcond_notexit_0_stall_in_reg_180_NO_SHIFT_REG),
.valid_out(rnode_179to180_bb1_notexitcond_notexit_0_valid_out_reg_180_NO_SHIFT_REG),
.stall_out(rnode_179to180_bb1_notexitcond_notexit_0_stall_out_reg_180_NO_SHIFT_REG),
.data_in(rnode_3to179_bb1_notexitcond_notexit_0_NO_SHIFT_REG),
.data_out(rnode_179to180_bb1_notexitcond_notexit_0_reg_180_NO_SHIFT_REG)
);
defparam rnode_179to180_bb1_notexitcond_notexit_0_reg_180_fifo.DEPTH = 2;
defparam rnode_179to180_bb1_notexitcond_notexit_0_reg_180_fifo.DATA_WIDTH = 1;
defparam rnode_179to180_bb1_notexitcond_notexit_0_reg_180_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_179to180_bb1_notexitcond_notexit_0_reg_180_fifo.IMPL = "ll_reg";
assign rnode_179to180_bb1_notexitcond_notexit_0_reg_180_inputs_ready_NO_SHIFT_REG = rnode_3to179_bb1_notexitcond_notexit_0_valid_out_NO_SHIFT_REG;
assign rnode_3to179_bb1_notexitcond_notexit_0_stall_in_NO_SHIFT_REG = rnode_179to180_bb1_notexitcond_notexit_0_stall_out_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_notexitcond_notexit_0_NO_SHIFT_REG = rnode_179to180_bb1_notexitcond_notexit_0_reg_180_NO_SHIFT_REG;
assign rnode_179to180_bb1_notexitcond_notexit_0_stall_in_reg_180_NO_SHIFT_REG = rnode_179to180_bb1_notexitcond_notexit_0_stall_in_NO_SHIFT_REG;
assign rnode_179to180_bb1_notexitcond_notexit_0_valid_out_NO_SHIFT_REG = rnode_179to180_bb1_notexitcond_notexit_0_valid_out_reg_180_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_c0_enter_c0_eni3_inputs_ready;
reg local_bb1_c0_enter_c0_eni3_valid_out_0_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni3_stall_in_0;
reg local_bb1_c0_enter_c0_eni3_valid_out_1_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni3_stall_in_1;
reg local_bb1_c0_enter_c0_eni3_valid_out_2_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni3_stall_in_2;
wire local_bb1_c0_enter_c0_eni3_output_regs_ready;
reg [31:0] local_bb1_c0_enter_c0_eni3_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni3_input_accepted;
wire local_bb1_c0_exit_c0_exi1_entry_stall;
wire local_bb1_c0_exit_c0_exi1_output_regs_ready;
wire [9:0] local_bb1_c0_exit_c0_exi1_valid_bits;
wire local_bb1_c0_exit_c0_exi1_phases;
wire local_bb1_c0_enter_c0_eni3_inc_pipelined_thread;
wire local_bb1_c0_enter_c0_eni3_dec_pipelined_thread;
wire local_bb1_c0_enter_c0_eni3_causedstall;
assign local_bb1_c0_enter_c0_eni3_inputs_ready = (local_bb1_c0_eni3_valid_out & rnode_161to162_forked_0_valid_out_1_NO_SHIFT_REG & rnode_161to162_bb1_keep_going_forked_0_valid_out_1_NO_SHIFT_REG);
assign local_bb1_c0_enter_c0_eni3_output_regs_ready = 1'b1;
assign local_bb1_c0_enter_c0_eni3_input_accepted = (local_bb1_c0_enter_c0_eni3_inputs_ready && !(local_bb1_c0_exit_c0_exi1_entry_stall));
assign local_bb1_c0_enter_c0_eni3_inc_pipelined_thread = rnode_161to162_forked_1_NO_SHIFT_REG;
assign local_bb1_c0_enter_c0_eni3_dec_pipelined_thread = ~(rnode_161to162_bb1_keep_going_forked_1_NO_SHIFT_REG);
assign local_bb1_c0_eni3_stall_in = ((~(local_bb1_c0_enter_c0_eni3_inputs_ready) | local_bb1_c0_exit_c0_exi1_entry_stall) | ~(1'b1));
assign rnode_161to162_forked_0_stall_in_1_NO_SHIFT_REG = ((~(local_bb1_c0_enter_c0_eni3_inputs_ready) | local_bb1_c0_exit_c0_exi1_entry_stall) | ~(1'b1));
assign rnode_161to162_bb1_keep_going_forked_0_stall_in_1_NO_SHIFT_REG = ((~(local_bb1_c0_enter_c0_eni3_inputs_ready) | local_bb1_c0_exit_c0_exi1_entry_stall) | ~(1'b1));
assign local_bb1_c0_enter_c0_eni3_causedstall = (1'b1 && ((~(local_bb1_c0_enter_c0_eni3_inputs_ready) | local_bb1_c0_exit_c0_exi1_entry_stall) && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_c0_enter_c0_eni3_NO_SHIFT_REG <= 'x;
local_bb1_c0_enter_c0_eni3_valid_out_0_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_enter_c0_eni3_valid_out_1_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_enter_c0_eni3_valid_out_2_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_c0_enter_c0_eni3_output_regs_ready)
begin
local_bb1_c0_enter_c0_eni3_NO_SHIFT_REG <= local_bb1_c0_eni3;
local_bb1_c0_enter_c0_eni3_valid_out_0_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_enter_c0_eni3_valid_out_1_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_enter_c0_eni3_valid_out_2_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_c0_enter_c0_eni3_stall_in_0))
begin
local_bb1_c0_enter_c0_eni3_valid_out_0_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_enter_c0_eni3_stall_in_1))
begin
local_bb1_c0_enter_c0_eni3_valid_out_1_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_enter_c0_eni3_stall_in_2))
begin
local_bb1_c0_enter_c0_eni3_valid_out_2_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_c0_ene1_inputs_ready;
reg local_bb1_c0_ene1_valid_out_0_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_0;
reg local_bb1_c0_ene1_valid_out_1_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_1;
reg local_bb1_c0_ene1_valid_out_2_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_2;
reg local_bb1_c0_ene1_valid_out_3_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_3;
reg local_bb1_c0_ene1_valid_out_4_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_4;
reg local_bb1_c0_ene1_valid_out_5_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_5;
reg local_bb1_c0_ene1_valid_out_6_NO_SHIFT_REG;
wire local_bb1_c0_ene1_stall_in_6;
wire local_bb1_c0_ene1_output_regs_ready;
reg local_bb1_c0_ene1_NO_SHIFT_REG;
wire local_bb1_c0_ene1_op_wire;
wire local_bb1_c0_ene1_causedstall;
assign local_bb1_c0_ene1_inputs_ready = 1'b1;
assign local_bb1_c0_ene1_output_regs_ready = 1'b1;
assign local_bb1_c0_ene1_op_wire = local_bb1_c0_enter_c0_eni3_NO_SHIFT_REG[8];
assign local_bb1_c0_enter_c0_eni3_stall_in_0 = 1'b0;
assign local_bb1_c0_ene1_causedstall = (1'b1 && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_c0_ene1_NO_SHIFT_REG <= 'x;
local_bb1_c0_ene1_valid_out_0_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene1_valid_out_1_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene1_valid_out_2_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene1_valid_out_3_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene1_valid_out_4_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene1_valid_out_5_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene1_valid_out_6_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_c0_ene1_output_regs_ready)
begin
local_bb1_c0_ene1_NO_SHIFT_REG <= local_bb1_c0_ene1_op_wire;
local_bb1_c0_ene1_valid_out_0_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene1_valid_out_1_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene1_valid_out_2_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene1_valid_out_3_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene1_valid_out_4_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene1_valid_out_5_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene1_valid_out_6_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_c0_ene1_stall_in_0))
begin
local_bb1_c0_ene1_valid_out_0_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene1_stall_in_1))
begin
local_bb1_c0_ene1_valid_out_1_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene1_stall_in_2))
begin
local_bb1_c0_ene1_valid_out_2_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene1_stall_in_3))
begin
local_bb1_c0_ene1_valid_out_3_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene1_stall_in_4))
begin
local_bb1_c0_ene1_valid_out_4_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene1_stall_in_5))
begin
local_bb1_c0_ene1_valid_out_5_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene1_stall_in_6))
begin
local_bb1_c0_ene1_valid_out_6_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_c0_ene2_inputs_ready;
reg local_bb1_c0_ene2_valid_out_0_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_0;
reg local_bb1_c0_ene2_valid_out_1_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_1;
reg local_bb1_c0_ene2_valid_out_2_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_2;
reg local_bb1_c0_ene2_valid_out_3_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_3;
reg local_bb1_c0_ene2_valid_out_4_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_4;
reg local_bb1_c0_ene2_valid_out_5_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_5;
reg local_bb1_c0_ene2_valid_out_6_NO_SHIFT_REG;
wire local_bb1_c0_ene2_stall_in_6;
wire local_bb1_c0_ene2_output_regs_ready;
reg local_bb1_c0_ene2_NO_SHIFT_REG;
wire local_bb1_c0_ene2_op_wire;
wire local_bb1_c0_ene2_causedstall;
assign local_bb1_c0_ene2_inputs_ready = 1'b1;
assign local_bb1_c0_ene2_output_regs_ready = 1'b1;
assign local_bb1_c0_ene2_op_wire = local_bb1_c0_enter_c0_eni3_NO_SHIFT_REG[16];
assign local_bb1_c0_enter_c0_eni3_stall_in_1 = 1'b0;
assign local_bb1_c0_ene2_causedstall = (1'b1 && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_c0_ene2_NO_SHIFT_REG <= 'x;
local_bb1_c0_ene2_valid_out_0_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene2_valid_out_1_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene2_valid_out_2_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene2_valid_out_3_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene2_valid_out_4_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene2_valid_out_5_NO_SHIFT_REG <= 1'b0;
local_bb1_c0_ene2_valid_out_6_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_c0_ene2_output_regs_ready)
begin
local_bb1_c0_ene2_NO_SHIFT_REG <= local_bb1_c0_ene2_op_wire;
local_bb1_c0_ene2_valid_out_0_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene2_valid_out_1_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene2_valid_out_2_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene2_valid_out_3_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene2_valid_out_4_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene2_valid_out_5_NO_SHIFT_REG <= 1'b1;
local_bb1_c0_ene2_valid_out_6_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_c0_ene2_stall_in_0))
begin
local_bb1_c0_ene2_valid_out_0_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene2_stall_in_1))
begin
local_bb1_c0_ene2_valid_out_1_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene2_stall_in_2))
begin
local_bb1_c0_ene2_valid_out_2_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene2_stall_in_3))
begin
local_bb1_c0_ene2_valid_out_3_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene2_stall_in_4))
begin
local_bb1_c0_ene2_valid_out_4_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene2_stall_in_5))
begin
local_bb1_c0_ene2_valid_out_5_NO_SHIFT_REG <= 1'b0;
end
if (~(local_bb1_c0_ene2_stall_in_6))
begin
local_bb1_c0_ene2_valid_out_6_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_c0_ene3_valid_out;
wire local_bb1_c0_ene3_stall_in;
wire local_bb1_c0_ene3_inputs_ready;
wire local_bb1_c0_ene3_stall_local;
wire [7:0] local_bb1_c0_ene3;
assign local_bb1_c0_ene3_inputs_ready = local_bb1_c0_enter_c0_eni3_valid_out_2_NO_SHIFT_REG;
assign local_bb1_c0_ene3 = local_bb1_c0_enter_c0_eni3_NO_SHIFT_REG[31:24];
assign local_bb1_c0_ene3_valid_out = 1'b1;
assign local_bb1_c0_enter_c0_eni3_stall_in_2 = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1_0_pop34__stall_local;
wire [7:0] local_bb1_rows_1_0_pop34_;
wire local_bb1_rows_1_0_pop34__fu_valid_out;
wire local_bb1_rows_1_0_pop34__fu_stall_out;
acl_pop local_bb1_rows_1_0_pop34__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1_0_pop34__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_1_0_pop34__fu_valid_out),
.stall_in(local_bb1_rows_1_0_pop34__stall_local),
.data_out(local_bb1_rows_1_0_pop34_),
.feedback_in(feedback_data_in_34),
.feedback_valid_in(feedback_valid_in_34),
.feedback_stall_out(feedback_stall_out_34)
);
defparam local_bb1_rows_1_0_pop34__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1_0_pop34__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1_0_pop34__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_0_0_pop35__stall_local;
wire [7:0] local_bb1_rows_0_0_pop35_;
wire local_bb1_rows_0_0_pop35__fu_valid_out;
wire local_bb1_rows_0_0_pop35__fu_stall_out;
acl_pop local_bb1_rows_0_0_pop35__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_0_0_pop35__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_0_0_pop35__fu_valid_out),
.stall_in(local_bb1_rows_0_0_pop35__stall_local),
.data_out(local_bb1_rows_0_0_pop35_),
.feedback_in(feedback_data_in_35),
.feedback_valid_in(feedback_valid_in_35),
.feedback_stall_out(feedback_stall_out_35)
);
defparam local_bb1_rows_0_0_pop35__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_0_0_pop35__feedback.STYLE = "REGULAR";
assign local_bb1_rows_0_0_pop35__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_2_0_pop33__stall_local;
wire [7:0] local_bb1_rows_2_0_pop33_;
wire local_bb1_rows_2_0_pop33__fu_valid_out;
wire local_bb1_rows_2_0_pop33__fu_stall_out;
acl_pop local_bb1_rows_2_0_pop33__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_2_0_pop33__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_2_0_pop33__fu_valid_out),
.stall_in(local_bb1_rows_2_0_pop33__stall_local),
.data_out(local_bb1_rows_2_0_pop33_),
.feedback_in(feedback_data_in_33),
.feedback_valid_in(feedback_valid_in_33),
.feedback_stall_out(feedback_stall_out_33)
);
defparam local_bb1_rows_2_0_pop33__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_2_0_pop33__feedback.STYLE = "REGULAR";
assign local_bb1_rows_2_0_pop33__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_3_0_pop32__stall_local;
wire [7:0] local_bb1_rows_3_0_pop32_;
wire local_bb1_rows_3_0_pop32__fu_valid_out;
wire local_bb1_rows_3_0_pop32__fu_stall_out;
acl_pop local_bb1_rows_3_0_pop32__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_3_0_pop32__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_3_0_pop32__fu_valid_out),
.stall_in(local_bb1_rows_3_0_pop32__stall_local),
.data_out(local_bb1_rows_3_0_pop32_),
.feedback_in(feedback_data_in_32),
.feedback_valid_in(feedback_valid_in_32),
.feedback_stall_out(feedback_stall_out_32)
);
defparam local_bb1_rows_3_0_pop32__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_3_0_pop32__feedback.STYLE = "REGULAR";
assign local_bb1_rows_3_0_pop32__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_4_0_pop31__stall_local;
wire [7:0] local_bb1_rows_4_0_pop31_;
wire local_bb1_rows_4_0_pop31__fu_valid_out;
wire local_bb1_rows_4_0_pop31__fu_stall_out;
acl_pop local_bb1_rows_4_0_pop31__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_4_0_pop31__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_4_0_pop31__fu_valid_out),
.stall_in(local_bb1_rows_4_0_pop31__stall_local),
.data_out(local_bb1_rows_4_0_pop31_),
.feedback_in(feedback_data_in_31),
.feedback_valid_in(feedback_valid_in_31),
.feedback_stall_out(feedback_stall_out_31)
);
defparam local_bb1_rows_4_0_pop31__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_4_0_pop31__feedback.STYLE = "REGULAR";
assign local_bb1_rows_4_0_pop31__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_5_0_pop30__valid_out;
wire local_bb1_rows_5_0_pop30__stall_in;
wire local_bb1_rows_5_0_pop30__inputs_ready;
wire local_bb1_rows_5_0_pop30__stall_local;
wire [7:0] local_bb1_rows_5_0_pop30_;
wire local_bb1_rows_5_0_pop30__fu_valid_out;
wire local_bb1_rows_5_0_pop30__fu_stall_out;
acl_pop local_bb1_rows_5_0_pop30__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_5_0_pop30__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_5_0_pop30__fu_valid_out),
.stall_in(local_bb1_rows_5_0_pop30__stall_local),
.data_out(local_bb1_rows_5_0_pop30_),
.feedback_in(feedback_data_in_30),
.feedback_valid_in(feedback_valid_in_30),
.feedback_stall_out(feedback_stall_out_30)
);
defparam local_bb1_rows_5_0_pop30__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_5_0_pop30__feedback.STYLE = "REGULAR";
assign local_bb1_rows_5_0_pop30__inputs_ready = local_bb1_c0_ene1_valid_out_5_NO_SHIFT_REG;
assign local_bb1_rows_5_0_pop30__stall_local = 1'b0;
assign local_bb1_rows_5_0_pop30__valid_out = 1'b1;
assign local_bb1_c0_ene1_stall_in_5 = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_164to165_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_2_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_3_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_4_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_5_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_6_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_7_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_7_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_7_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_8_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_8_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_8_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_9_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_9_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_9_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_10_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_10_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_10_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_11_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_11_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_11_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_12_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_12_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_12_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_reg_165_inputs_ready_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_valid_out_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_in_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene1_0_stall_out_reg_165_NO_SHIFT_REG;
acl_data_fifo rnode_164to165_bb1_c0_ene1_0_reg_165_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_164to165_bb1_c0_ene1_0_reg_165_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_164to165_bb1_c0_ene1_0_stall_in_0_reg_165_NO_SHIFT_REG),
.valid_out(rnode_164to165_bb1_c0_ene1_0_valid_out_0_reg_165_NO_SHIFT_REG),
.stall_out(rnode_164to165_bb1_c0_ene1_0_stall_out_reg_165_NO_SHIFT_REG),
.data_in(local_bb1_c0_ene1_NO_SHIFT_REG),
.data_out(rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG)
);
defparam rnode_164to165_bb1_c0_ene1_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_c0_ene1_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_164to165_bb1_c0_ene1_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_c0_ene1_0_reg_165_fifo.IMPL = "shift_reg";
assign rnode_164to165_bb1_c0_ene1_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_c0_ene1_stall_in_6 = 1'b0;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_1_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_2_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_3_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_4_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_5_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_6_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_7_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_7_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_8_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_8_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_9_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_9_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_10_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_10_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_11_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_11_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene1_0_valid_out_12_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_12_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene1_0_reg_165_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_164to165_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_2_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_3_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_4_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_5_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_6_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_7_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_8_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_8_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_8_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_9_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_9_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_9_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_10_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_10_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_10_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_11_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_11_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_11_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_reg_165_inputs_ready_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_valid_out_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_in_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_c0_ene2_0_stall_out_reg_165_NO_SHIFT_REG;
acl_data_fifo rnode_164to165_bb1_c0_ene2_0_reg_165_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_164to165_bb1_c0_ene2_0_reg_165_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_164to165_bb1_c0_ene2_0_stall_in_0_reg_165_NO_SHIFT_REG),
.valid_out(rnode_164to165_bb1_c0_ene2_0_valid_out_0_reg_165_NO_SHIFT_REG),
.stall_out(rnode_164to165_bb1_c0_ene2_0_stall_out_reg_165_NO_SHIFT_REG),
.data_in(local_bb1_c0_ene2_NO_SHIFT_REG),
.data_out(rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG)
);
defparam rnode_164to165_bb1_c0_ene2_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_c0_ene2_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_164to165_bb1_c0_ene2_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_c0_ene2_0_reg_165_fifo.IMPL = "shift_reg";
assign rnode_164to165_bb1_c0_ene2_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_c0_ene2_stall_in_6 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_0_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_1_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_2_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_3_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_4_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_5_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_6_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_7_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_8_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_8_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_9_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_9_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_10_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_10_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_c0_ene2_0_valid_out_11_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_11_NO_SHIFT_REG = rnode_164to165_bb1_c0_ene2_0_reg_165_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_163to164_bb1_c0_ene3_0_valid_out_0_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_163to164_bb1_c0_ene3_0_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_valid_out_1_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_163to164_bb1_c0_ene3_1_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_reg_164_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_163to164_bb1_c0_ene3_0_reg_164_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_valid_out_0_reg_164_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_stall_in_0_reg_164_NO_SHIFT_REG;
logic rnode_163to164_bb1_c0_ene3_0_stall_out_reg_164_NO_SHIFT_REG;
acl_data_fifo rnode_163to164_bb1_c0_ene3_0_reg_164_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_163to164_bb1_c0_ene3_0_reg_164_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_163to164_bb1_c0_ene3_0_stall_in_0_reg_164_NO_SHIFT_REG),
.valid_out(rnode_163to164_bb1_c0_ene3_0_valid_out_0_reg_164_NO_SHIFT_REG),
.stall_out(rnode_163to164_bb1_c0_ene3_0_stall_out_reg_164_NO_SHIFT_REG),
.data_in(local_bb1_c0_ene3),
.data_out(rnode_163to164_bb1_c0_ene3_0_reg_164_NO_SHIFT_REG)
);
defparam rnode_163to164_bb1_c0_ene3_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_c0_ene3_0_reg_164_fifo.DATA_WIDTH = 8;
defparam rnode_163to164_bb1_c0_ene3_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_c0_ene3_0_reg_164_fifo.IMPL = "shift_reg";
assign rnode_163to164_bb1_c0_ene3_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_c0_ene3_stall_in = 1'b0;
assign rnode_163to164_bb1_c0_ene3_0_stall_in_0_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_c0_ene3_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_c0_ene3_0_NO_SHIFT_REG = rnode_163to164_bb1_c0_ene3_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_c0_ene3_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_c0_ene3_1_NO_SHIFT_REG = rnode_163to164_bb1_c0_ene3_0_reg_164_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_2_stall_local;
wire local_bb1_cmp16_2;
assign local_bb1_cmp16_2 = (local_bb1_rows_1_0_pop34_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_1_stall_local;
wire local_bb1_cmp16_1;
assign local_bb1_cmp16_1 = (local_bb1_rows_0_0_pop35_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_3_stall_local;
wire local_bb1_cmp16_3;
assign local_bb1_cmp16_3 = (local_bb1_rows_2_0_pop33_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_rows_3_0_pop32__valid_out_0;
wire local_bb1_rows_3_0_pop32__stall_in_0;
reg local_bb1_rows_3_0_pop32__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_4_valid_out;
wire local_bb1_cmp16_4_stall_in;
reg local_bb1_cmp16_4_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_4_inputs_ready;
wire local_bb1_cmp16_4_stall_local;
wire local_bb1_cmp16_4;
assign local_bb1_cmp16_4_inputs_ready = local_bb1_c0_ene1_valid_out_3_NO_SHIFT_REG;
assign local_bb1_cmp16_4 = (local_bb1_rows_3_0_pop32_ == 8'h0);
assign local_bb1_rows_3_0_pop32__valid_out_0 = 1'b1;
assign local_bb1_cmp16_4_valid_out = 1'b1;
assign local_bb1_c0_ene1_stall_in_3 = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_3_0_pop32__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_4_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_3_0_pop32__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_4_inputs_ready & (local_bb1_rows_3_0_pop32__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_3_0_pop32__stall_in_0)) & local_bb1_cmp16_4_stall_local);
local_bb1_cmp16_4_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_4_inputs_ready & (local_bb1_cmp16_4_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_4_stall_in)) & local_bb1_cmp16_4_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_4_0_pop31__valid_out_0;
wire local_bb1_rows_4_0_pop31__stall_in_0;
reg local_bb1_rows_4_0_pop31__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_5_valid_out;
wire local_bb1_cmp16_5_stall_in;
reg local_bb1_cmp16_5_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_5_inputs_ready;
wire local_bb1_cmp16_5_stall_local;
wire local_bb1_cmp16_5;
assign local_bb1_cmp16_5_inputs_ready = local_bb1_c0_ene1_valid_out_4_NO_SHIFT_REG;
assign local_bb1_cmp16_5 = (local_bb1_rows_4_0_pop31_ == 8'h0);
assign local_bb1_rows_4_0_pop31__valid_out_0 = 1'b1;
assign local_bb1_cmp16_5_valid_out = 1'b1;
assign local_bb1_c0_ene1_stall_in_4 = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_4_0_pop31__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_5_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_4_0_pop31__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_5_inputs_ready & (local_bb1_rows_4_0_pop31__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_4_0_pop31__stall_in_0)) & local_bb1_cmp16_5_stall_local);
local_bb1_cmp16_5_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_5_inputs_ready & (local_bb1_cmp16_5_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_5_stall_in)) & local_bb1_cmp16_5_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_164to165_bb1_rows_5_0_pop30__0_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_164to165_bb1_rows_5_0_pop30__1_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_rows_5_0_pop30__0_stall_out_reg_165_NO_SHIFT_REG;
acl_data_fifo rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_0_reg_165_NO_SHIFT_REG),
.valid_out(rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_0_reg_165_NO_SHIFT_REG),
.stall_out(rnode_164to165_bb1_rows_5_0_pop30__0_stall_out_reg_165_NO_SHIFT_REG),
.data_in(local_bb1_rows_5_0_pop30_),
.data_out(rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_NO_SHIFT_REG)
);
defparam rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_fifo.DATA_WIDTH = 8;
defparam rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_fifo.IMPL = "shift_reg";
assign rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_5_0_pop30__stall_in = 1'b0;
assign rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_rows_5_0_pop30__0_NO_SHIFT_REG = rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_rows_5_0_pop30__1_NO_SHIFT_REG = rnode_164to165_bb1_rows_5_0_pop30__0_reg_165_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_rows_7_0_pop28__stall_local;
wire [7:0] local_bb1_rows_7_0_pop28_;
wire local_bb1_rows_7_0_pop28__fu_valid_out;
wire local_bb1_rows_7_0_pop28__fu_stall_out;
acl_pop local_bb1_rows_7_0_pop28__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_7_0_pop28__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_7_0_pop28__fu_valid_out),
.stall_in(local_bb1_rows_7_0_pop28__stall_local),
.data_out(local_bb1_rows_7_0_pop28_),
.feedback_in(feedback_data_in_28),
.feedback_valid_in(feedback_valid_in_28),
.feedback_stall_out(feedback_stall_out_28)
);
defparam local_bb1_rows_7_0_pop28__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_7_0_pop28__feedback.STYLE = "REGULAR";
assign local_bb1_rows_7_0_pop28__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_8_0_pop27__stall_local;
wire [7:0] local_bb1_rows_8_0_pop27_;
wire local_bb1_rows_8_0_pop27__fu_valid_out;
wire local_bb1_rows_8_0_pop27__fu_stall_out;
acl_pop local_bb1_rows_8_0_pop27__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_8_0_pop27__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_8_0_pop27__fu_valid_out),
.stall_in(local_bb1_rows_8_0_pop27__stall_local),
.data_out(local_bb1_rows_8_0_pop27_),
.feedback_in(feedback_data_in_27),
.feedback_valid_in(feedback_valid_in_27),
.feedback_stall_out(feedback_stall_out_27)
);
defparam local_bb1_rows_8_0_pop27__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_8_0_pop27__feedback.STYLE = "REGULAR";
assign local_bb1_rows_8_0_pop27__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_9_0_pop26__stall_local;
wire [7:0] local_bb1_rows_9_0_pop26_;
wire local_bb1_rows_9_0_pop26__fu_valid_out;
wire local_bb1_rows_9_0_pop26__fu_stall_out;
acl_pop local_bb1_rows_9_0_pop26__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_9_0_pop26__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_9_0_pop26__fu_valid_out),
.stall_in(local_bb1_rows_9_0_pop26__stall_local),
.data_out(local_bb1_rows_9_0_pop26_),
.feedback_in(feedback_data_in_26),
.feedback_valid_in(feedback_valid_in_26),
.feedback_stall_out(feedback_stall_out_26)
);
defparam local_bb1_rows_9_0_pop26__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_9_0_pop26__feedback.STYLE = "REGULAR";
assign local_bb1_rows_9_0_pop26__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_15_0_pop20__stall_local;
wire [7:0] local_bb1_rows_15_0_pop20_;
wire local_bb1_rows_15_0_pop20__fu_valid_out;
wire local_bb1_rows_15_0_pop20__fu_stall_out;
acl_pop local_bb1_rows_15_0_pop20__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_15_0_pop20__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_15_0_pop20__fu_valid_out),
.stall_in(local_bb1_rows_15_0_pop20__stall_local),
.data_out(local_bb1_rows_15_0_pop20_),
.feedback_in(feedback_data_in_20),
.feedback_valid_in(feedback_valid_in_20),
.feedback_stall_out(feedback_stall_out_20)
);
defparam local_bb1_rows_15_0_pop20__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_15_0_pop20__feedback.STYLE = "REGULAR";
assign local_bb1_rows_15_0_pop20__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1920_0_pop19__valid_out;
wire local_bb1_rows_1920_0_pop19__stall_in;
wire local_bb1_rows_1920_0_pop19__inputs_ready;
wire local_bb1_rows_1920_0_pop19__stall_local;
wire [7:0] local_bb1_rows_1920_0_pop19_;
wire local_bb1_rows_1920_0_pop19__fu_valid_out;
wire local_bb1_rows_1920_0_pop19__fu_stall_out;
acl_pop local_bb1_rows_1920_0_pop19__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1920_0_pop19__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_1920_0_pop19__fu_valid_out),
.stall_in(local_bb1_rows_1920_0_pop19__stall_local),
.data_out(local_bb1_rows_1920_0_pop19_),
.feedback_in(feedback_data_in_19),
.feedback_valid_in(feedback_valid_in_19),
.feedback_stall_out(feedback_stall_out_19)
);
defparam local_bb1_rows_1920_0_pop19__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1920_0_pop19__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1920_0_pop19__inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
assign local_bb1_rows_1920_0_pop19__stall_local = 1'b0;
assign local_bb1_rows_1920_0_pop19__valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_14_0_pop21__stall_local;
wire [7:0] local_bb1_rows_14_0_pop21_;
wire local_bb1_rows_14_0_pop21__fu_valid_out;
wire local_bb1_rows_14_0_pop21__fu_stall_out;
acl_pop local_bb1_rows_14_0_pop21__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_14_0_pop21__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_14_0_pop21__fu_valid_out),
.stall_in(local_bb1_rows_14_0_pop21__stall_local),
.data_out(local_bb1_rows_14_0_pop21_),
.feedback_in(feedback_data_in_21),
.feedback_valid_in(feedback_valid_in_21),
.feedback_stall_out(feedback_stall_out_21)
);
defparam local_bb1_rows_14_0_pop21__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_14_0_pop21__feedback.STYLE = "REGULAR";
assign local_bb1_rows_14_0_pop21__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_13_0_pop22__stall_local;
wire [7:0] local_bb1_rows_13_0_pop22_;
wire local_bb1_rows_13_0_pop22__fu_valid_out;
wire local_bb1_rows_13_0_pop22__fu_stall_out;
acl_pop local_bb1_rows_13_0_pop22__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_6_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_13_0_pop22__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_13_0_pop22__fu_valid_out),
.stall_in(local_bb1_rows_13_0_pop22__stall_local),
.data_out(local_bb1_rows_13_0_pop22_),
.feedback_in(feedback_data_in_22),
.feedback_valid_in(feedback_valid_in_22),
.feedback_stall_out(feedback_stall_out_22)
);
defparam local_bb1_rows_13_0_pop22__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_13_0_pop22__feedback.STYLE = "REGULAR";
assign local_bb1_rows_13_0_pop22__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_12_0_pop23__stall_local;
wire [7:0] local_bb1_rows_12_0_pop23_;
wire local_bb1_rows_12_0_pop23__fu_valid_out;
wire local_bb1_rows_12_0_pop23__fu_stall_out;
acl_pop local_bb1_rows_12_0_pop23__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_7_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_12_0_pop23__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_12_0_pop23__fu_valid_out),
.stall_in(local_bb1_rows_12_0_pop23__stall_local),
.data_out(local_bb1_rows_12_0_pop23_),
.feedback_in(feedback_data_in_23),
.feedback_valid_in(feedback_valid_in_23),
.feedback_stall_out(feedback_stall_out_23)
);
defparam local_bb1_rows_12_0_pop23__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_12_0_pop23__feedback.STYLE = "REGULAR";
assign local_bb1_rows_12_0_pop23__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_11_0_pop24__stall_local;
wire [7:0] local_bb1_rows_11_0_pop24_;
wire local_bb1_rows_11_0_pop24__fu_valid_out;
wire local_bb1_rows_11_0_pop24__fu_stall_out;
acl_pop local_bb1_rows_11_0_pop24__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_8_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_11_0_pop24__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_11_0_pop24__fu_valid_out),
.stall_in(local_bb1_rows_11_0_pop24__stall_local),
.data_out(local_bb1_rows_11_0_pop24_),
.feedback_in(feedback_data_in_24),
.feedback_valid_in(feedback_valid_in_24),
.feedback_stall_out(feedback_stall_out_24)
);
defparam local_bb1_rows_11_0_pop24__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_11_0_pop24__feedback.STYLE = "REGULAR";
assign local_bb1_rows_11_0_pop24__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_stall_local;
wire [11:0] local_bb1_coalesce_counter_pop54_acl_pop_i12_1903;
wire local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_fu_valid_out;
wire local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_fu_stall_out;
acl_pop local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_9_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(12'h76F),
.stall_out(local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_fu_valid_out),
.stall_in(local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_stall_local),
.data_out(local_bb1_coalesce_counter_pop54_acl_pop_i12_1903),
.feedback_in(feedback_data_in_54),
.feedback_valid_in(feedback_valid_in_54),
.feedback_stall_out(feedback_stall_out_54)
);
defparam local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_feedback.DATA_WIDTH = 12;
defparam local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_feedback.STYLE = "REGULAR";
assign local_bb1_coalesce_counter_pop54_acl_pop_i12_1903_stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_10_0_pop25__stall_local;
wire [7:0] local_bb1_rows_10_0_pop25_;
wire local_bb1_rows_10_0_pop25__fu_valid_out;
wire local_bb1_rows_10_0_pop25__fu_stall_out;
acl_pop local_bb1_rows_10_0_pop25__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_10_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_10_0_pop25__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_10_0_pop25__fu_valid_out),
.stall_in(local_bb1_rows_10_0_pop25__stall_local),
.data_out(local_bb1_rows_10_0_pop25_),
.feedback_in(feedback_data_in_25),
.feedback_valid_in(feedback_valid_in_25),
.feedback_stall_out(feedback_stall_out_25)
);
defparam local_bb1_rows_10_0_pop25__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_10_0_pop25__feedback.STYLE = "REGULAR";
assign local_bb1_rows_10_0_pop25__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_6_0_pop29__stall_local;
wire [7:0] local_bb1_rows_6_0_pop29_;
wire local_bb1_rows_6_0_pop29__fu_valid_out;
wire local_bb1_rows_6_0_pop29__fu_stall_out;
acl_pop local_bb1_rows_6_0_pop29__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene1_11_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_6_0_pop29__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_6_0_pop29__fu_valid_out),
.stall_in(local_bb1_rows_6_0_pop29__stall_local),
.data_out(local_bb1_rows_6_0_pop29_),
.feedback_in(feedback_data_in_29),
.feedback_valid_in(feedback_valid_in_29),
.feedback_stall_out(feedback_stall_out_29)
);
defparam local_bb1_rows_6_0_pop29__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_6_0_pop29__feedback.STYLE = "REGULAR";
assign local_bb1_rows_6_0_pop29__stall_local = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_2_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_3_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_4_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_5_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_6_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene1_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_c0_ene1_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_c0_ene1_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_c0_ene1_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_c0_ene1_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_c0_ene1_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(rnode_164to165_bb1_c0_ene1_12_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_c0_ene1_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_c0_ene1_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_c0_ene1_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_c0_ene1_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_c0_ene1_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_12_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_1_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_2_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_3_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_4_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_5_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_6_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene1_0_reg_166_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_2_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_3_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_4_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_5_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_6_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_7_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_c0_ene2_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_c0_ene2_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_c0_ene2_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_c0_ene2_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_c0_ene2_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_c0_ene2_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(rnode_164to165_bb1_c0_ene2_11_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_c0_ene2_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_c0_ene2_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_c0_ene2_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_c0_ene2_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_c0_ene2_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_11_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_0_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_1_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_2_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_3_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_4_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_5_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_6_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_7_NO_SHIFT_REG = rnode_165to166_bb1_c0_ene2_0_reg_166_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_0_0_push35_c0_ene3_inputs_ready;
reg local_bb1_rows_0_0_push35_c0_ene3_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_0_0_push35_c0_ene3_stall_in;
wire local_bb1_rows_0_0_push35_c0_ene3_output_regs_ready;
wire [7:0] local_bb1_rows_0_0_push35_c0_ene3_result;
wire local_bb1_rows_0_0_push35_c0_ene3_fu_valid_out;
wire local_bb1_rows_0_0_push35_c0_ene3_fu_stall_out;
reg [7:0] local_bb1_rows_0_0_push35_c0_ene3_NO_SHIFT_REG;
wire local_bb1_rows_0_0_push35_c0_ene3_causedstall;
acl_push local_bb1_rows_0_0_push35_c0_ene3_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_163to164_bb1_c0_ene3_0_NO_SHIFT_REG),
.stall_out(local_bb1_rows_0_0_push35_c0_ene3_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_0_0_push35_c0_ene3_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_0_0_push35_c0_ene3_result),
.feedback_out(feedback_data_out_35),
.feedback_valid_out(feedback_valid_out_35),
.feedback_stall_in(feedback_stall_in_35)
);
defparam local_bb1_rows_0_0_push35_c0_ene3_feedback.STALLFREE = 1;
defparam local_bb1_rows_0_0_push35_c0_ene3_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_0_0_push35_c0_ene3_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_0_0_push35_c0_ene3_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_0_0_push35_c0_ene3_feedback.STYLE = "REGULAR";
assign local_bb1_rows_0_0_push35_c0_ene3_inputs_ready = 1'b1;
assign local_bb1_rows_0_0_push35_c0_ene3_output_regs_ready = 1'b1;
assign local_bb1_c0_ene2_stall_in_5 = 1'b0;
assign rnode_163to164_bb1_c0_ene3_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_0_0_push35_c0_ene3_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[2] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_0_0_push35_c0_ene3_NO_SHIFT_REG <= 'x;
local_bb1_rows_0_0_push35_c0_ene3_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_0_0_push35_c0_ene3_output_regs_ready)
begin
local_bb1_rows_0_0_push35_c0_ene3_NO_SHIFT_REG <= local_bb1_rows_0_0_push35_c0_ene3_result;
local_bb1_rows_0_0_push35_c0_ene3_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_0_0_push35_c0_ene3_stall_in))
begin
local_bb1_rows_0_0_push35_c0_ene3_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_stall_local;
wire local_bb1_cmp16;
assign local_bb1_cmp16 = (rnode_163to164_bb1_c0_ene3_1_NO_SHIFT_REG == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_2_stall_local;
wire local_bb1_not_cmp16_2;
assign local_bb1_not_cmp16_2 = (local_bb1_cmp16_2 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_1_stall_local;
wire local_bb1_not_cmp16_1;
assign local_bb1_not_cmp16_1 = (local_bb1_cmp16_1 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_3_stall_local;
wire local_bb1_not_cmp16_3;
assign local_bb1_not_cmp16_3 = (local_bb1_cmp16_3 ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1_rows_4_0_push31_rows_3_0_pop32_inputs_ready;
reg local_bb1_rows_4_0_push31_rows_3_0_pop32_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_4_0_push31_rows_3_0_pop32_stall_in;
wire local_bb1_rows_4_0_push31_rows_3_0_pop32_output_regs_ready;
wire [7:0] local_bb1_rows_4_0_push31_rows_3_0_pop32_result;
wire local_bb1_rows_4_0_push31_rows_3_0_pop32_fu_valid_out;
wire local_bb1_rows_4_0_push31_rows_3_0_pop32_fu_stall_out;
reg [7:0] local_bb1_rows_4_0_push31_rows_3_0_pop32_NO_SHIFT_REG;
wire local_bb1_rows_4_0_push31_rows_3_0_pop32_causedstall;
acl_push local_bb1_rows_4_0_push31_rows_3_0_pop32_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_3_0_pop32_),
.stall_out(local_bb1_rows_4_0_push31_rows_3_0_pop32_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_4_0_push31_rows_3_0_pop32_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_4_0_push31_rows_3_0_pop32_result),
.feedback_out(feedback_data_out_31),
.feedback_valid_out(feedback_valid_out_31),
.feedback_stall_in(feedback_stall_in_31)
);
defparam local_bb1_rows_4_0_push31_rows_3_0_pop32_feedback.STALLFREE = 1;
defparam local_bb1_rows_4_0_push31_rows_3_0_pop32_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_4_0_push31_rows_3_0_pop32_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_4_0_push31_rows_3_0_pop32_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_4_0_push31_rows_3_0_pop32_feedback.STYLE = "REGULAR";
assign local_bb1_rows_4_0_push31_rows_3_0_pop32_inputs_ready = 1'b1;
assign local_bb1_rows_4_0_push31_rows_3_0_pop32_output_regs_ready = 1'b1;
assign local_bb1_rows_3_0_pop32__stall_in_0 = 1'b0;
assign local_bb1_c0_ene2_stall_in_3 = 1'b0;
assign local_bb1_rows_4_0_push31_rows_3_0_pop32_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[2] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_4_0_push31_rows_3_0_pop32_NO_SHIFT_REG <= 'x;
local_bb1_rows_4_0_push31_rows_3_0_pop32_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_4_0_push31_rows_3_0_pop32_output_regs_ready)
begin
local_bb1_rows_4_0_push31_rows_3_0_pop32_NO_SHIFT_REG <= local_bb1_rows_4_0_push31_rows_3_0_pop32_result;
local_bb1_rows_4_0_push31_rows_3_0_pop32_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_4_0_push31_rows_3_0_pop32_stall_in))
begin
local_bb1_rows_4_0_push31_rows_3_0_pop32_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_164to165_bb1_cmp16_4_0_valid_out_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_stall_in_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_valid_out_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_stall_in_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_reg_165_inputs_ready_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_valid_out_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_stall_in_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_4_0_stall_out_reg_165_NO_SHIFT_REG;
acl_data_fifo rnode_164to165_bb1_cmp16_4_0_reg_165_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_164to165_bb1_cmp16_4_0_reg_165_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_164to165_bb1_cmp16_4_0_stall_in_0_reg_165_NO_SHIFT_REG),
.valid_out(rnode_164to165_bb1_cmp16_4_0_valid_out_0_reg_165_NO_SHIFT_REG),
.stall_out(rnode_164to165_bb1_cmp16_4_0_stall_out_reg_165_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_4),
.data_out(rnode_164to165_bb1_cmp16_4_0_reg_165_NO_SHIFT_REG)
);
defparam rnode_164to165_bb1_cmp16_4_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_cmp16_4_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_164to165_bb1_cmp16_4_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_cmp16_4_0_reg_165_fifo.IMPL = "shift_reg";
assign rnode_164to165_bb1_cmp16_4_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_4_stall_in = 1'b0;
assign rnode_164to165_bb1_cmp16_4_0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_cmp16_4_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_cmp16_4_0_NO_SHIFT_REG = rnode_164to165_bb1_cmp16_4_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_cmp16_4_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_cmp16_4_1_NO_SHIFT_REG = rnode_164to165_bb1_cmp16_4_0_reg_165_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_5_0_push30_rows_4_0_pop31_inputs_ready;
reg local_bb1_rows_5_0_push30_rows_4_0_pop31_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_5_0_push30_rows_4_0_pop31_stall_in;
wire local_bb1_rows_5_0_push30_rows_4_0_pop31_output_regs_ready;
wire [7:0] local_bb1_rows_5_0_push30_rows_4_0_pop31_result;
wire local_bb1_rows_5_0_push30_rows_4_0_pop31_fu_valid_out;
wire local_bb1_rows_5_0_push30_rows_4_0_pop31_fu_stall_out;
reg [7:0] local_bb1_rows_5_0_push30_rows_4_0_pop31_NO_SHIFT_REG;
wire local_bb1_rows_5_0_push30_rows_4_0_pop31_causedstall;
acl_push local_bb1_rows_5_0_push30_rows_4_0_pop31_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_4_0_pop31_),
.stall_out(local_bb1_rows_5_0_push30_rows_4_0_pop31_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_5_0_push30_rows_4_0_pop31_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_5_0_push30_rows_4_0_pop31_result),
.feedback_out(feedback_data_out_30),
.feedback_valid_out(feedback_valid_out_30),
.feedback_stall_in(feedback_stall_in_30)
);
defparam local_bb1_rows_5_0_push30_rows_4_0_pop31_feedback.STALLFREE = 1;
defparam local_bb1_rows_5_0_push30_rows_4_0_pop31_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_5_0_push30_rows_4_0_pop31_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_5_0_push30_rows_4_0_pop31_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_5_0_push30_rows_4_0_pop31_feedback.STYLE = "REGULAR";
assign local_bb1_rows_5_0_push30_rows_4_0_pop31_inputs_ready = 1'b1;
assign local_bb1_rows_5_0_push30_rows_4_0_pop31_output_regs_ready = 1'b1;
assign local_bb1_rows_4_0_pop31__stall_in_0 = 1'b0;
assign local_bb1_c0_ene2_stall_in_4 = 1'b0;
assign local_bb1_rows_5_0_push30_rows_4_0_pop31_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[2] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_5_0_push30_rows_4_0_pop31_NO_SHIFT_REG <= 'x;
local_bb1_rows_5_0_push30_rows_4_0_pop31_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_5_0_push30_rows_4_0_pop31_output_regs_ready)
begin
local_bb1_rows_5_0_push30_rows_4_0_pop31_NO_SHIFT_REG <= local_bb1_rows_5_0_push30_rows_4_0_pop31_result;
local_bb1_rows_5_0_push30_rows_4_0_pop31_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_5_0_push30_rows_4_0_pop31_stall_in))
begin
local_bb1_rows_5_0_push30_rows_4_0_pop31_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_164to165_bb1_cmp16_5_0_valid_out_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_stall_in_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_valid_out_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_stall_in_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_1_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_reg_165_inputs_ready_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_valid_out_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_stall_in_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1_cmp16_5_0_stall_out_reg_165_NO_SHIFT_REG;
acl_data_fifo rnode_164to165_bb1_cmp16_5_0_reg_165_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_164to165_bb1_cmp16_5_0_reg_165_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_164to165_bb1_cmp16_5_0_stall_in_0_reg_165_NO_SHIFT_REG),
.valid_out(rnode_164to165_bb1_cmp16_5_0_valid_out_0_reg_165_NO_SHIFT_REG),
.stall_out(rnode_164to165_bb1_cmp16_5_0_stall_out_reg_165_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_5),
.data_out(rnode_164to165_bb1_cmp16_5_0_reg_165_NO_SHIFT_REG)
);
defparam rnode_164to165_bb1_cmp16_5_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_cmp16_5_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_164to165_bb1_cmp16_5_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_cmp16_5_0_reg_165_fifo.IMPL = "shift_reg";
assign rnode_164to165_bb1_cmp16_5_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_5_stall_in = 1'b0;
assign rnode_164to165_bb1_cmp16_5_0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_cmp16_5_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_cmp16_5_0_NO_SHIFT_REG = rnode_164to165_bb1_cmp16_5_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_cmp16_5_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_cmp16_5_1_NO_SHIFT_REG = rnode_164to165_bb1_cmp16_5_0_reg_165_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_6_0_push29_rows_5_0_pop30_inputs_ready;
reg local_bb1_rows_6_0_push29_rows_5_0_pop30_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_6_0_push29_rows_5_0_pop30_stall_in;
wire local_bb1_rows_6_0_push29_rows_5_0_pop30_output_regs_ready;
wire [7:0] local_bb1_rows_6_0_push29_rows_5_0_pop30_result;
wire local_bb1_rows_6_0_push29_rows_5_0_pop30_fu_valid_out;
wire local_bb1_rows_6_0_push29_rows_5_0_pop30_fu_stall_out;
reg [7:0] local_bb1_rows_6_0_push29_rows_5_0_pop30_NO_SHIFT_REG;
wire local_bb1_rows_6_0_push29_rows_5_0_pop30_causedstall;
acl_push local_bb1_rows_6_0_push29_rows_5_0_pop30_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_8_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_164to165_bb1_rows_5_0_pop30__0_NO_SHIFT_REG),
.stall_out(local_bb1_rows_6_0_push29_rows_5_0_pop30_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_6_0_push29_rows_5_0_pop30_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_6_0_push29_rows_5_0_pop30_result),
.feedback_out(feedback_data_out_29),
.feedback_valid_out(feedback_valid_out_29),
.feedback_stall_in(feedback_stall_in_29)
);
defparam local_bb1_rows_6_0_push29_rows_5_0_pop30_feedback.STALLFREE = 1;
defparam local_bb1_rows_6_0_push29_rows_5_0_pop30_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_6_0_push29_rows_5_0_pop30_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_6_0_push29_rows_5_0_pop30_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_6_0_push29_rows_5_0_pop30_feedback.STYLE = "REGULAR";
assign local_bb1_rows_6_0_push29_rows_5_0_pop30_inputs_ready = 1'b1;
assign local_bb1_rows_6_0_push29_rows_5_0_pop30_output_regs_ready = 1'b1;
assign rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_8_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_6_0_push29_rows_5_0_pop30_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_6_0_push29_rows_5_0_pop30_NO_SHIFT_REG <= 'x;
local_bb1_rows_6_0_push29_rows_5_0_pop30_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_6_0_push29_rows_5_0_pop30_output_regs_ready)
begin
local_bb1_rows_6_0_push29_rows_5_0_pop30_NO_SHIFT_REG <= local_bb1_rows_6_0_push29_rows_5_0_pop30_result;
local_bb1_rows_6_0_push29_rows_5_0_pop30_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_6_0_push29_rows_5_0_pop30_stall_in))
begin
local_bb1_rows_6_0_push29_rows_5_0_pop30_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_6_stall_local;
wire local_bb1_cmp16_6;
assign local_bb1_cmp16_6 = (rnode_164to165_bb1_rows_5_0_pop30__1_NO_SHIFT_REG == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_8_stall_local;
wire local_bb1_cmp16_8;
assign local_bb1_cmp16_8 = (local_bb1_rows_7_0_pop28_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_9_stall_local;
wire local_bb1_cmp16_9;
assign local_bb1_cmp16_9 = (local_bb1_rows_8_0_pop27_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_10_stall_local;
wire local_bb1_cmp16_10;
assign local_bb1_cmp16_10 = (local_bb1_rows_9_0_pop26_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_rows_15_0_pop20__valid_out_0;
wire local_bb1_rows_15_0_pop20__stall_in_0;
reg local_bb1_rows_15_0_pop20__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_16_valid_out;
wire local_bb1_cmp16_16_stall_in;
reg local_bb1_cmp16_16_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_16_inputs_ready;
wire local_bb1_cmp16_16_stall_local;
wire local_bb1_cmp16_16;
assign local_bb1_cmp16_16_inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
assign local_bb1_cmp16_16 = (local_bb1_rows_15_0_pop20_ == 8'h0);
assign local_bb1_rows_15_0_pop20__valid_out_0 = 1'b1;
assign local_bb1_cmp16_16_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_15_0_pop20__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_16_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_15_0_pop20__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_16_inputs_ready & (local_bb1_rows_15_0_pop20__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_15_0_pop20__stall_in_0)) & local_bb1_cmp16_16_stall_local);
local_bb1_cmp16_16_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_16_inputs_ready & (local_bb1_cmp16_16_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_16_stall_in)) & local_bb1_cmp16_16_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_1920_0_pop19__0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_1920_0_pop19__1_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1920_0_pop19__0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_1920_0_pop19__0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_1920_0_pop19_),
.data_out(rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1920_0_pop19__stall_in = 1'b0;
assign rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_1920_0_pop19__0_NO_SHIFT_REG = rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_1920_0_pop19__1_NO_SHIFT_REG = rnode_165to166_bb1_rows_1920_0_pop19__0_reg_166_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_rows_14_0_pop21__valid_out_0;
wire local_bb1_rows_14_0_pop21__stall_in_0;
reg local_bb1_rows_14_0_pop21__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_15_valid_out;
wire local_bb1_cmp16_15_stall_in;
reg local_bb1_cmp16_15_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_15_inputs_ready;
wire local_bb1_cmp16_15_stall_local;
wire local_bb1_cmp16_15;
assign local_bb1_cmp16_15_inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
assign local_bb1_cmp16_15 = (local_bb1_rows_14_0_pop21_ == 8'h0);
assign local_bb1_rows_14_0_pop21__valid_out_0 = 1'b1;
assign local_bb1_cmp16_15_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_14_0_pop21__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_15_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_14_0_pop21__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_15_inputs_ready & (local_bb1_rows_14_0_pop21__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_14_0_pop21__stall_in_0)) & local_bb1_cmp16_15_stall_local);
local_bb1_cmp16_15_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_15_inputs_ready & (local_bb1_cmp16_15_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_15_stall_in)) & local_bb1_cmp16_15_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_13_0_pop22__valid_out_0;
wire local_bb1_rows_13_0_pop22__stall_in_0;
reg local_bb1_rows_13_0_pop22__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_14_valid_out;
wire local_bb1_cmp16_14_stall_in;
reg local_bb1_cmp16_14_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_14_inputs_ready;
wire local_bb1_cmp16_14_stall_local;
wire local_bb1_cmp16_14;
assign local_bb1_cmp16_14_inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
assign local_bb1_cmp16_14 = (local_bb1_rows_13_0_pop22_ == 8'h0);
assign local_bb1_rows_13_0_pop22__valid_out_0 = 1'b1;
assign local_bb1_cmp16_14_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_13_0_pop22__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_14_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_13_0_pop22__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_14_inputs_ready & (local_bb1_rows_13_0_pop22__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_13_0_pop22__stall_in_0)) & local_bb1_cmp16_14_stall_local);
local_bb1_cmp16_14_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_14_inputs_ready & (local_bb1_cmp16_14_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_14_stall_in)) & local_bb1_cmp16_14_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_12_0_pop23__valid_out_0;
wire local_bb1_rows_12_0_pop23__stall_in_0;
reg local_bb1_rows_12_0_pop23__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_13_valid_out;
wire local_bb1_cmp16_13_stall_in;
reg local_bb1_cmp16_13_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_13_inputs_ready;
wire local_bb1_cmp16_13_stall_local;
wire local_bb1_cmp16_13;
assign local_bb1_cmp16_13_inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_7_NO_SHIFT_REG;
assign local_bb1_cmp16_13 = (local_bb1_rows_12_0_pop23_ == 8'h0);
assign local_bb1_rows_12_0_pop23__valid_out_0 = 1'b1;
assign local_bb1_cmp16_13_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_7_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_12_0_pop23__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_13_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_12_0_pop23__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_13_inputs_ready & (local_bb1_rows_12_0_pop23__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_12_0_pop23__stall_in_0)) & local_bb1_cmp16_13_stall_local);
local_bb1_cmp16_13_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_13_inputs_ready & (local_bb1_cmp16_13_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_13_stall_in)) & local_bb1_cmp16_13_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_11_0_pop24__valid_out_1;
wire local_bb1_rows_11_0_pop24__stall_in_1;
reg local_bb1_rows_11_0_pop24__consumed_1_NO_SHIFT_REG;
wire local_bb1_cmp16_12_valid_out;
wire local_bb1_cmp16_12_stall_in;
reg local_bb1_cmp16_12_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_12_inputs_ready;
wire local_bb1_cmp16_12_stall_local;
wire local_bb1_cmp16_12;
assign local_bb1_cmp16_12_inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_8_NO_SHIFT_REG;
assign local_bb1_cmp16_12 = (local_bb1_rows_11_0_pop24_ == 8'h0);
assign local_bb1_rows_11_0_pop24__valid_out_1 = 1'b1;
assign local_bb1_cmp16_12_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_8_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_11_0_pop24__consumed_1_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_12_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_11_0_pop24__consumed_1_NO_SHIFT_REG <= (local_bb1_cmp16_12_inputs_ready & (local_bb1_rows_11_0_pop24__consumed_1_NO_SHIFT_REG | ~(local_bb1_rows_11_0_pop24__stall_in_1)) & local_bb1_cmp16_12_stall_local);
local_bb1_cmp16_12_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_12_inputs_ready & (local_bb1_cmp16_12_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_12_stall_in)) & local_bb1_cmp16_12_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_not_select6_stall_local;
wire local_bb1_not_select6;
assign local_bb1_not_select6 = ($signed(local_bb1_coalesce_counter_pop54_acl_pop_i12_1903) > $signed(12'hFFF));
// This section implements an unregistered operation.
//
wire local_bb1_coalesce_counter_lobit_stall_local;
wire [11:0] local_bb1_coalesce_counter_lobit;
assign local_bb1_coalesce_counter_lobit = (local_bb1_coalesce_counter_pop54_acl_pop_i12_1903 >> 12'hB);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_11_stall_local;
wire local_bb1_cmp16_11;
assign local_bb1_cmp16_11 = (local_bb1_rows_10_0_pop25_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_7_stall_local;
wire local_bb1_cmp16_7;
assign local_bb1_cmp16_7 = (local_bb1_rows_6_0_pop29_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_rows_1926_0_pop13__valid_out;
wire local_bb1_rows_1926_0_pop13__stall_in;
wire local_bb1_rows_1926_0_pop13__inputs_ready;
wire local_bb1_rows_1926_0_pop13__stall_local;
wire [7:0] local_bb1_rows_1926_0_pop13_;
wire local_bb1_rows_1926_0_pop13__fu_valid_out;
wire local_bb1_rows_1926_0_pop13__fu_stall_out;
acl_pop local_bb1_rows_1926_0_pop13__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene1_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1926_0_pop13__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1926_0_pop13__fu_valid_out),
.stall_in(local_bb1_rows_1926_0_pop13__stall_local),
.data_out(local_bb1_rows_1926_0_pop13_),
.feedback_in(feedback_data_in_13),
.feedback_valid_in(feedback_valid_in_13),
.feedback_stall_out(feedback_stall_out_13)
);
defparam local_bb1_rows_1926_0_pop13__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1926_0_pop13__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1926_0_pop13__inputs_ready = rnode_165to166_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_rows_1926_0_pop13__stall_local = 1'b0;
assign local_bb1_rows_1926_0_pop13__valid_out = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1925_0_pop14__stall_local;
wire [7:0] local_bb1_rows_1925_0_pop14_;
wire local_bb1_rows_1925_0_pop14__fu_valid_out;
wire local_bb1_rows_1925_0_pop14__fu_stall_out;
acl_pop local_bb1_rows_1925_0_pop14__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene1_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1925_0_pop14__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1925_0_pop14__fu_valid_out),
.stall_in(local_bb1_rows_1925_0_pop14__stall_local),
.data_out(local_bb1_rows_1925_0_pop14_),
.feedback_in(feedback_data_in_14),
.feedback_valid_in(feedback_valid_in_14),
.feedback_stall_out(feedback_stall_out_14)
);
defparam local_bb1_rows_1925_0_pop14__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1925_0_pop14__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1925_0_pop14__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1924_0_pop15__stall_local;
wire [7:0] local_bb1_rows_1924_0_pop15_;
wire local_bb1_rows_1924_0_pop15__fu_valid_out;
wire local_bb1_rows_1924_0_pop15__fu_stall_out;
acl_pop local_bb1_rows_1924_0_pop15__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene1_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1924_0_pop15__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1924_0_pop15__fu_valid_out),
.stall_in(local_bb1_rows_1924_0_pop15__stall_local),
.data_out(local_bb1_rows_1924_0_pop15_),
.feedback_in(feedback_data_in_15),
.feedback_valid_in(feedback_valid_in_15),
.feedback_stall_out(feedback_stall_out_15)
);
defparam local_bb1_rows_1924_0_pop15__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1924_0_pop15__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1924_0_pop15__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1923_0_pop16__stall_local;
wire [7:0] local_bb1_rows_1923_0_pop16_;
wire local_bb1_rows_1923_0_pop16__fu_valid_out;
wire local_bb1_rows_1923_0_pop16__fu_stall_out;
acl_pop local_bb1_rows_1923_0_pop16__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene1_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1923_0_pop16__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1923_0_pop16__fu_valid_out),
.stall_in(local_bb1_rows_1923_0_pop16__stall_local),
.data_out(local_bb1_rows_1923_0_pop16_),
.feedback_in(feedback_data_in_16),
.feedback_valid_in(feedback_valid_in_16),
.feedback_stall_out(feedback_stall_out_16)
);
defparam local_bb1_rows_1923_0_pop16__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1923_0_pop16__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1923_0_pop16__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1922_0_pop17__stall_local;
wire [7:0] local_bb1_rows_1922_0_pop17_;
wire local_bb1_rows_1922_0_pop17__fu_valid_out;
wire local_bb1_rows_1922_0_pop17__fu_stall_out;
acl_pop local_bb1_rows_1922_0_pop17__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene1_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1922_0_pop17__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1922_0_pop17__fu_valid_out),
.stall_in(local_bb1_rows_1922_0_pop17__stall_local),
.data_out(local_bb1_rows_1922_0_pop17_),
.feedback_in(feedback_data_in_17),
.feedback_valid_in(feedback_valid_in_17),
.feedback_stall_out(feedback_stall_out_17)
);
defparam local_bb1_rows_1922_0_pop17__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1922_0_pop17__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1922_0_pop17__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1921_0_pop18__stall_local;
wire [7:0] local_bb1_rows_1921_0_pop18_;
wire local_bb1_rows_1921_0_pop18__fu_valid_out;
wire local_bb1_rows_1921_0_pop18__fu_stall_out;
acl_pop local_bb1_rows_1921_0_pop18__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene1_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1921_0_pop18__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1921_0_pop18__fu_valid_out),
.stall_in(local_bb1_rows_1921_0_pop18__stall_local),
.data_out(local_bb1_rows_1921_0_pop18_),
.feedback_in(feedback_data_in_18),
.feedback_valid_in(feedback_valid_in_18),
.feedback_stall_out(feedback_stall_out_18)
);
defparam local_bb1_rows_1921_0_pop18__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1921_0_pop18__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1921_0_pop18__stall_local = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_2_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_3_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_4_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_5_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_6_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene1_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_c0_ene1_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_c0_ene1_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_c0_ene1_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_c0_ene1_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_c0_ene1_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_c0_ene1_6_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_c0_ene1_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_c0_ene1_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_c0_ene1_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_c0_ene1_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_c0_ene1_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_1_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_2_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_3_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_4_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_5_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_6_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene1_0_reg_167_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_2_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_3_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_4_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_5_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_6_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_c0_ene2_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_c0_ene2_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_c0_ene2_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_c0_ene2_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_c0_ene2_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_c0_ene2_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_c0_ene2_7_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_c0_ene2_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_c0_ene2_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_c0_ene2_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_c0_ene2_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_c0_ene2_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_0_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_1_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_2_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_3_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_4_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_5_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_6_NO_SHIFT_REG = rnode_166to167_bb1_c0_ene2_0_reg_167_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_0_0_push35_c0_ene3_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_0_0_push35_c0_ene3_stall_in = 1'b0;
assign rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG = rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_isMin_3_stall_local;
wire [7:0] local_bb1_isMin_3;
assign local_bb1_isMin_3[7:1] = 7'h0;
assign local_bb1_isMin_3[0] = local_bb1_cmp16;
// This section implements an unregistered operation.
//
wire local_bb1__334_demorgan_stall_local;
wire local_bb1__334_demorgan;
assign local_bb1__334_demorgan = (local_bb1_cmp16_1 | local_bb1_cmp16);
// This section implements an unregistered operation.
//
wire local_bb1___stall_local;
wire local_bb1__;
assign local_bb1__ = (local_bb1_cmp16 & local_bb1_not_cmp16_1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_4_0_push31_rows_3_0_pop32_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_4_0_push31_rows_3_0_pop32_stall_in = 1'b0;
assign rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG = rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_4_stall_local;
wire local_bb1_not_cmp16_4;
assign local_bb1_not_cmp16_4 = (rnode_164to165_bb1_cmp16_4_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_5_0_push30_rows_4_0_pop31_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_5_0_push30_rows_4_0_pop31_stall_in = 1'b0;
assign rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG = rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_5_stall_local;
wire local_bb1_not_cmp16_5;
assign local_bb1_not_cmp16_5 = (rnode_164to165_bb1_cmp16_5_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_6_0_push29_rows_5_0_pop30_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_6_0_push29_rows_5_0_pop30_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_6_stall_local;
wire local_bb1_not_cmp16_6;
assign local_bb1_not_cmp16_6 = (local_bb1_cmp16_6 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_8_stall_local;
wire local_bb1_not_cmp16_8;
assign local_bb1_not_cmp16_8 = (local_bb1_cmp16_8 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_9_stall_local;
wire local_bb1_not_cmp16_9;
assign local_bb1_not_cmp16_9 = (local_bb1_cmp16_9 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_10_stall_local;
wire local_bb1_not_cmp16_10;
assign local_bb1_not_cmp16_10 = (local_bb1_cmp16_10 ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_inputs_ready;
reg local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_stall_in;
wire local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_output_regs_ready;
wire [7:0] local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_result;
wire local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_fu_valid_out;
wire local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_fu_stall_out;
reg [7:0] local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_NO_SHIFT_REG;
wire local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_causedstall;
acl_push local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_feedback (
.clock(clock),
.resetn(resetn),
.dir(1'b1),
.predicate(1'b0),
.data_in(local_bb1_rows_15_0_pop20_),
.stall_out(local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_result),
.feedback_out(feedback_data_out_3),
.feedback_valid_out(feedback_valid_out_3),
.feedback_stall_in(feedback_stall_in_3)
);
defparam local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_feedback.STALLFREE = 1;
defparam local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_feedback.FIFO_DEPTH = 1904;
defparam local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_feedback.MIN_FIFO_LATENCY = 1904;
defparam local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_inputs_ready = 1'b1;
assign local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_output_regs_ready = 1'b1;
assign local_bb1_rows_15_0_pop20__stall_in_0 = 1'b0;
assign local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_NO_SHIFT_REG <= 'x;
local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_output_regs_ready)
begin
local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_NO_SHIFT_REG <= local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_result;
local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_stall_in))
begin
local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_cmp16_16_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_16_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_cmp16_16_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_cmp16_16_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_cmp16_16_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_cmp16_16_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_cmp16_16_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_16),
.data_out(rnode_165to166_bb1_cmp16_16_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_cmp16_16_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_cmp16_16_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_cmp16_16_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_cmp16_16_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_cmp16_16_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_16_stall_in = 1'b0;
assign rnode_165to166_bb1_cmp16_16_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_16_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_16_0_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_16_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_cmp16_16_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_16_1_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_16_0_reg_166_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1921_0_push18_rows_1920_0_pop19_inputs_ready;
reg local_bb1_rows_1921_0_push18_rows_1920_0_pop19_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1921_0_push18_rows_1920_0_pop19_stall_in;
wire local_bb1_rows_1921_0_push18_rows_1920_0_pop19_output_regs_ready;
wire [7:0] local_bb1_rows_1921_0_push18_rows_1920_0_pop19_result;
wire local_bb1_rows_1921_0_push18_rows_1920_0_pop19_fu_valid_out;
wire local_bb1_rows_1921_0_push18_rows_1920_0_pop19_fu_stall_out;
reg [7:0] local_bb1_rows_1921_0_push18_rows_1920_0_pop19_NO_SHIFT_REG;
wire local_bb1_rows_1921_0_push18_rows_1920_0_pop19_causedstall;
acl_push local_bb1_rows_1921_0_push18_rows_1920_0_pop19_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_6_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_165to166_bb1_rows_1920_0_pop19__0_NO_SHIFT_REG),
.stall_out(local_bb1_rows_1921_0_push18_rows_1920_0_pop19_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1921_0_push18_rows_1920_0_pop19_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1921_0_push18_rows_1920_0_pop19_result),
.feedback_out(feedback_data_out_18),
.feedback_valid_out(feedback_valid_out_18),
.feedback_stall_in(feedback_stall_in_18)
);
defparam local_bb1_rows_1921_0_push18_rows_1920_0_pop19_feedback.STALLFREE = 1;
defparam local_bb1_rows_1921_0_push18_rows_1920_0_pop19_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1921_0_push18_rows_1920_0_pop19_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1921_0_push18_rows_1920_0_pop19_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1921_0_push18_rows_1920_0_pop19_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1921_0_push18_rows_1920_0_pop19_inputs_ready = 1'b1;
assign local_bb1_rows_1921_0_push18_rows_1920_0_pop19_output_regs_ready = 1'b1;
assign rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1921_0_push18_rows_1920_0_pop19_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1921_0_push18_rows_1920_0_pop19_NO_SHIFT_REG <= 'x;
local_bb1_rows_1921_0_push18_rows_1920_0_pop19_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1921_0_push18_rows_1920_0_pop19_output_regs_ready)
begin
local_bb1_rows_1921_0_push18_rows_1920_0_pop19_NO_SHIFT_REG <= local_bb1_rows_1921_0_push18_rows_1920_0_pop19_result;
local_bb1_rows_1921_0_push18_rows_1920_0_pop19_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1921_0_push18_rows_1920_0_pop19_stall_in))
begin
local_bb1_rows_1921_0_push18_rows_1920_0_pop19_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_1_1_stall_local;
wire local_bb1_cmp16_1_1;
assign local_bb1_cmp16_1_1 = (rnode_165to166_bb1_rows_1920_0_pop19__1_NO_SHIFT_REG == 8'h0);
// This section implements a registered operation.
//
wire local_bb1_rows_15_0_push20_rows_14_0_pop21_inputs_ready;
reg local_bb1_rows_15_0_push20_rows_14_0_pop21_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_15_0_push20_rows_14_0_pop21_stall_in;
wire local_bb1_rows_15_0_push20_rows_14_0_pop21_output_regs_ready;
wire [7:0] local_bb1_rows_15_0_push20_rows_14_0_pop21_result;
wire local_bb1_rows_15_0_push20_rows_14_0_pop21_fu_valid_out;
wire local_bb1_rows_15_0_push20_rows_14_0_pop21_fu_stall_out;
reg [7:0] local_bb1_rows_15_0_push20_rows_14_0_pop21_NO_SHIFT_REG;
wire local_bb1_rows_15_0_push20_rows_14_0_pop21_causedstall;
acl_push local_bb1_rows_15_0_push20_rows_14_0_pop21_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_14_0_pop21_),
.stall_out(local_bb1_rows_15_0_push20_rows_14_0_pop21_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_15_0_push20_rows_14_0_pop21_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_15_0_push20_rows_14_0_pop21_result),
.feedback_out(feedback_data_out_20),
.feedback_valid_out(feedback_valid_out_20),
.feedback_stall_in(feedback_stall_in_20)
);
defparam local_bb1_rows_15_0_push20_rows_14_0_pop21_feedback.STALLFREE = 1;
defparam local_bb1_rows_15_0_push20_rows_14_0_pop21_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_15_0_push20_rows_14_0_pop21_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_15_0_push20_rows_14_0_pop21_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_15_0_push20_rows_14_0_pop21_feedback.STYLE = "REGULAR";
assign local_bb1_rows_15_0_push20_rows_14_0_pop21_inputs_ready = 1'b1;
assign local_bb1_rows_15_0_push20_rows_14_0_pop21_output_regs_ready = 1'b1;
assign local_bb1_rows_14_0_pop21__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_15_0_push20_rows_14_0_pop21_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_15_0_push20_rows_14_0_pop21_NO_SHIFT_REG <= 'x;
local_bb1_rows_15_0_push20_rows_14_0_pop21_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_15_0_push20_rows_14_0_pop21_output_regs_ready)
begin
local_bb1_rows_15_0_push20_rows_14_0_pop21_NO_SHIFT_REG <= local_bb1_rows_15_0_push20_rows_14_0_pop21_result;
local_bb1_rows_15_0_push20_rows_14_0_pop21_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_15_0_push20_rows_14_0_pop21_stall_in))
begin
local_bb1_rows_15_0_push20_rows_14_0_pop21_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_cmp16_15_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_15_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_cmp16_15_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_cmp16_15_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_cmp16_15_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_cmp16_15_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_cmp16_15_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_15),
.data_out(rnode_165to166_bb1_cmp16_15_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_cmp16_15_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_cmp16_15_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_cmp16_15_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_cmp16_15_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_cmp16_15_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_15_stall_in = 1'b0;
assign rnode_165to166_bb1_cmp16_15_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_15_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_15_0_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_15_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_cmp16_15_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_15_1_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_15_0_reg_166_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_14_0_push21_rows_13_0_pop22_inputs_ready;
reg local_bb1_rows_14_0_push21_rows_13_0_pop22_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_14_0_push21_rows_13_0_pop22_stall_in;
wire local_bb1_rows_14_0_push21_rows_13_0_pop22_output_regs_ready;
wire [7:0] local_bb1_rows_14_0_push21_rows_13_0_pop22_result;
wire local_bb1_rows_14_0_push21_rows_13_0_pop22_fu_valid_out;
wire local_bb1_rows_14_0_push21_rows_13_0_pop22_fu_stall_out;
reg [7:0] local_bb1_rows_14_0_push21_rows_13_0_pop22_NO_SHIFT_REG;
wire local_bb1_rows_14_0_push21_rows_13_0_pop22_causedstall;
acl_push local_bb1_rows_14_0_push21_rows_13_0_pop22_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_13_0_pop22_),
.stall_out(local_bb1_rows_14_0_push21_rows_13_0_pop22_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_14_0_push21_rows_13_0_pop22_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_14_0_push21_rows_13_0_pop22_result),
.feedback_out(feedback_data_out_21),
.feedback_valid_out(feedback_valid_out_21),
.feedback_stall_in(feedback_stall_in_21)
);
defparam local_bb1_rows_14_0_push21_rows_13_0_pop22_feedback.STALLFREE = 1;
defparam local_bb1_rows_14_0_push21_rows_13_0_pop22_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_14_0_push21_rows_13_0_pop22_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_14_0_push21_rows_13_0_pop22_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_14_0_push21_rows_13_0_pop22_feedback.STYLE = "REGULAR";
assign local_bb1_rows_14_0_push21_rows_13_0_pop22_inputs_ready = 1'b1;
assign local_bb1_rows_14_0_push21_rows_13_0_pop22_output_regs_ready = 1'b1;
assign local_bb1_rows_13_0_pop22__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_14_0_push21_rows_13_0_pop22_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_14_0_push21_rows_13_0_pop22_NO_SHIFT_REG <= 'x;
local_bb1_rows_14_0_push21_rows_13_0_pop22_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_14_0_push21_rows_13_0_pop22_output_regs_ready)
begin
local_bb1_rows_14_0_push21_rows_13_0_pop22_NO_SHIFT_REG <= local_bb1_rows_14_0_push21_rows_13_0_pop22_result;
local_bb1_rows_14_0_push21_rows_13_0_pop22_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_14_0_push21_rows_13_0_pop22_stall_in))
begin
local_bb1_rows_14_0_push21_rows_13_0_pop22_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_cmp16_14_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_14_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_cmp16_14_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_cmp16_14_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_cmp16_14_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_cmp16_14_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_cmp16_14_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_14),
.data_out(rnode_165to166_bb1_cmp16_14_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_cmp16_14_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_cmp16_14_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_cmp16_14_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_cmp16_14_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_cmp16_14_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_14_stall_in = 1'b0;
assign rnode_165to166_bb1_cmp16_14_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_14_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_14_0_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_14_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_cmp16_14_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_14_1_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_14_0_reg_166_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_13_0_push22_rows_12_0_pop23_inputs_ready;
reg local_bb1_rows_13_0_push22_rows_12_0_pop23_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_13_0_push22_rows_12_0_pop23_stall_in;
wire local_bb1_rows_13_0_push22_rows_12_0_pop23_output_regs_ready;
wire [7:0] local_bb1_rows_13_0_push22_rows_12_0_pop23_result;
wire local_bb1_rows_13_0_push22_rows_12_0_pop23_fu_valid_out;
wire local_bb1_rows_13_0_push22_rows_12_0_pop23_fu_stall_out;
reg [7:0] local_bb1_rows_13_0_push22_rows_12_0_pop23_NO_SHIFT_REG;
wire local_bb1_rows_13_0_push22_rows_12_0_pop23_causedstall;
acl_push local_bb1_rows_13_0_push22_rows_12_0_pop23_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_7_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_12_0_pop23_),
.stall_out(local_bb1_rows_13_0_push22_rows_12_0_pop23_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_13_0_push22_rows_12_0_pop23_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_13_0_push22_rows_12_0_pop23_result),
.feedback_out(feedback_data_out_22),
.feedback_valid_out(feedback_valid_out_22),
.feedback_stall_in(feedback_stall_in_22)
);
defparam local_bb1_rows_13_0_push22_rows_12_0_pop23_feedback.STALLFREE = 1;
defparam local_bb1_rows_13_0_push22_rows_12_0_pop23_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_13_0_push22_rows_12_0_pop23_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_13_0_push22_rows_12_0_pop23_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_13_0_push22_rows_12_0_pop23_feedback.STYLE = "REGULAR";
assign local_bb1_rows_13_0_push22_rows_12_0_pop23_inputs_ready = 1'b1;
assign local_bb1_rows_13_0_push22_rows_12_0_pop23_output_regs_ready = 1'b1;
assign local_bb1_rows_12_0_pop23__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_13_0_push22_rows_12_0_pop23_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_13_0_push22_rows_12_0_pop23_NO_SHIFT_REG <= 'x;
local_bb1_rows_13_0_push22_rows_12_0_pop23_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_13_0_push22_rows_12_0_pop23_output_regs_ready)
begin
local_bb1_rows_13_0_push22_rows_12_0_pop23_NO_SHIFT_REG <= local_bb1_rows_13_0_push22_rows_12_0_pop23_result;
local_bb1_rows_13_0_push22_rows_12_0_pop23_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_13_0_push22_rows_12_0_pop23_stall_in))
begin
local_bb1_rows_13_0_push22_rows_12_0_pop23_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_cmp16_13_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_13_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_cmp16_13_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_cmp16_13_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_cmp16_13_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_cmp16_13_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_cmp16_13_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_13),
.data_out(rnode_165to166_bb1_cmp16_13_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_cmp16_13_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_cmp16_13_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_cmp16_13_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_cmp16_13_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_cmp16_13_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_13_stall_in = 1'b0;
assign rnode_165to166_bb1_cmp16_13_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_13_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_13_0_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_13_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_cmp16_13_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_13_1_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_13_0_reg_166_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_11_0_pop24__0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_11_0_pop24__0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_11_0_pop24__0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_11_0_pop24__0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_11_0_pop24__0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_11_0_pop24__0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_11_0_pop24__0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_11_0_pop24__0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_11_0_pop24__0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_11_0_pop24_),
.data_out(rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_11_0_pop24__stall_in_1 = 1'b0;
assign rnode_165to166_bb1_rows_11_0_pop24__0_NO_SHIFT_REG = rnode_165to166_bb1_rows_11_0_pop24__0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_11_0_pop24__0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_11_0_pop24__0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_cmp16_12_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_12_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_cmp16_12_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_cmp16_12_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_cmp16_12_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_cmp16_12_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_cmp16_12_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_12),
.data_out(rnode_165to166_bb1_cmp16_12_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_cmp16_12_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_cmp16_12_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_cmp16_12_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_cmp16_12_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_cmp16_12_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_12_stall_in = 1'b0;
assign rnode_165to166_bb1_cmp16_12_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_12_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_12_0_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_12_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_cmp16_12_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_12_1_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_12_0_reg_166_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1919_0_coalesced_pop3__stall_local;
wire [7:0] local_bb1_rows_1919_0_coalesced_pop3_;
wire local_bb1_rows_1919_0_coalesced_pop3__fu_valid_out;
wire local_bb1_rows_1919_0_coalesced_pop3__fu_stall_out;
acl_pop local_bb1_rows_1919_0_coalesced_pop3__feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_not_select6),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1919_0_coalesced_pop3__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_1919_0_coalesced_pop3__fu_valid_out),
.stall_in(local_bb1_rows_1919_0_coalesced_pop3__stall_local),
.data_out(local_bb1_rows_1919_0_coalesced_pop3_),
.feedback_in(feedback_data_in_3),
.feedback_valid_in(feedback_valid_in_3),
.feedback_stall_out(feedback_stall_out_3)
);
defparam local_bb1_rows_1919_0_coalesced_pop3__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1919_0_coalesced_pop3__feedback.STYLE = "COALESCE";
assign local_bb1_rows_1919_0_coalesced_pop3__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_next_coalesce_select_stall_local;
wire [11:0] local_bb1_next_coalesce_select;
assign local_bb1_next_coalesce_select = (local_bb1_coalesce_counter_lobit ^ 12'h1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_11_stall_local;
wire local_bb1_not_cmp16_11;
assign local_bb1_not_cmp16_11 = (local_bb1_cmp16_11 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_7_stall_local;
wire local_bb1_not_cmp16_7;
assign local_bb1_not_cmp16_7 = (local_bb1_cmp16_7 ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1926_0_pop13__0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1926_0_pop13__1_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1926_0_pop13__0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_1926_0_pop13__0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_1926_0_pop13_),
.data_out(rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1926_0_pop13__stall_in = 1'b0;
assign rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_1926_0_pop13__0_NO_SHIFT_REG = rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_1926_0_pop13__1_NO_SHIFT_REG = rnode_166to167_bb1_rows_1926_0_pop13__0_reg_167_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1925_0_pop14__valid_out_0;
wire local_bb1_rows_1925_0_pop14__stall_in_0;
reg local_bb1_rows_1925_0_pop14__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_6_1_valid_out;
wire local_bb1_cmp16_6_1_stall_in;
reg local_bb1_cmp16_6_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_6_1_inputs_ready;
wire local_bb1_cmp16_6_1_stall_local;
wire local_bb1_cmp16_6_1;
assign local_bb1_cmp16_6_1_inputs_ready = rnode_165to166_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_cmp16_6_1 = (local_bb1_rows_1925_0_pop14_ == 8'h0);
assign local_bb1_rows_1925_0_pop14__valid_out_0 = 1'b1;
assign local_bb1_cmp16_6_1_valid_out = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1925_0_pop14__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_6_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1925_0_pop14__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_6_1_inputs_ready & (local_bb1_rows_1925_0_pop14__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1925_0_pop14__stall_in_0)) & local_bb1_cmp16_6_1_stall_local);
local_bb1_cmp16_6_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_6_1_inputs_ready & (local_bb1_cmp16_6_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_6_1_stall_in)) & local_bb1_cmp16_6_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_1924_0_pop15__valid_out_0;
wire local_bb1_rows_1924_0_pop15__stall_in_0;
reg local_bb1_rows_1924_0_pop15__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_5_1_valid_out;
wire local_bb1_cmp16_5_1_stall_in;
reg local_bb1_cmp16_5_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_5_1_inputs_ready;
wire local_bb1_cmp16_5_1_stall_local;
wire local_bb1_cmp16_5_1;
assign local_bb1_cmp16_5_1_inputs_ready = rnode_165to166_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1_cmp16_5_1 = (local_bb1_rows_1924_0_pop15_ == 8'h0);
assign local_bb1_rows_1924_0_pop15__valid_out_0 = 1'b1;
assign local_bb1_cmp16_5_1_valid_out = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1924_0_pop15__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_5_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1924_0_pop15__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_5_1_inputs_ready & (local_bb1_rows_1924_0_pop15__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1924_0_pop15__stall_in_0)) & local_bb1_cmp16_5_1_stall_local);
local_bb1_cmp16_5_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_5_1_inputs_ready & (local_bb1_cmp16_5_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_5_1_stall_in)) & local_bb1_cmp16_5_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_1923_0_pop16__valid_out_0;
wire local_bb1_rows_1923_0_pop16__stall_in_0;
reg local_bb1_rows_1923_0_pop16__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_4_1_valid_out;
wire local_bb1_cmp16_4_1_stall_in;
reg local_bb1_cmp16_4_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_4_1_inputs_ready;
wire local_bb1_cmp16_4_1_stall_local;
wire local_bb1_cmp16_4_1;
assign local_bb1_cmp16_4_1_inputs_ready = rnode_165to166_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
assign local_bb1_cmp16_4_1 = (local_bb1_rows_1923_0_pop16_ == 8'h0);
assign local_bb1_rows_1923_0_pop16__valid_out_0 = 1'b1;
assign local_bb1_cmp16_4_1_valid_out = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1923_0_pop16__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_4_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1923_0_pop16__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_4_1_inputs_ready & (local_bb1_rows_1923_0_pop16__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1923_0_pop16__stall_in_0)) & local_bb1_cmp16_4_1_stall_local);
local_bb1_cmp16_4_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_4_1_inputs_ready & (local_bb1_cmp16_4_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_4_1_stall_in)) & local_bb1_cmp16_4_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_1922_0_pop17__valid_out_0;
wire local_bb1_rows_1922_0_pop17__stall_in_0;
reg local_bb1_rows_1922_0_pop17__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_3_1_valid_out;
wire local_bb1_cmp16_3_1_stall_in;
reg local_bb1_cmp16_3_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_3_1_inputs_ready;
wire local_bb1_cmp16_3_1_stall_local;
wire local_bb1_cmp16_3_1;
assign local_bb1_cmp16_3_1_inputs_ready = rnode_165to166_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
assign local_bb1_cmp16_3_1 = (local_bb1_rows_1922_0_pop17_ == 8'h0);
assign local_bb1_rows_1922_0_pop17__valid_out_0 = 1'b1;
assign local_bb1_cmp16_3_1_valid_out = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1922_0_pop17__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_3_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1922_0_pop17__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_3_1_inputs_ready & (local_bb1_rows_1922_0_pop17__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1922_0_pop17__stall_in_0)) & local_bb1_cmp16_3_1_stall_local);
local_bb1_cmp16_3_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_3_1_inputs_ready & (local_bb1_cmp16_3_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_3_1_stall_in)) & local_bb1_cmp16_3_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_1921_0_pop18__valid_out_0;
wire local_bb1_rows_1921_0_pop18__stall_in_0;
reg local_bb1_rows_1921_0_pop18__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_2_1_valid_out;
wire local_bb1_cmp16_2_1_stall_in;
reg local_bb1_cmp16_2_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_2_1_inputs_ready;
wire local_bb1_cmp16_2_1_stall_local;
wire local_bb1_cmp16_2_1;
assign local_bb1_cmp16_2_1_inputs_ready = rnode_165to166_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
assign local_bb1_cmp16_2_1 = (local_bb1_rows_1921_0_pop18_ == 8'h0);
assign local_bb1_rows_1921_0_pop18__valid_out_0 = 1'b1;
assign local_bb1_cmp16_2_1_valid_out = 1'b1;
assign rnode_165to166_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1921_0_pop18__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_2_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1921_0_pop18__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_2_1_inputs_ready & (local_bb1_rows_1921_0_pop18__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1921_0_pop18__stall_in_0)) & local_bb1_cmp16_2_1_stall_local);
local_bb1_cmp16_2_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_2_1_inputs_ready & (local_bb1_cmp16_2_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_2_1_stall_in)) & local_bb1_cmp16_2_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_1929_0_pop10__stall_local;
wire [7:0] local_bb1_rows_1929_0_pop10_;
wire local_bb1_rows_1929_0_pop10__fu_valid_out;
wire local_bb1_rows_1929_0_pop10__fu_stall_out;
acl_pop local_bb1_rows_1929_0_pop10__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene1_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1929_0_pop10__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1929_0_pop10__fu_valid_out),
.stall_in(local_bb1_rows_1929_0_pop10__stall_local),
.data_out(local_bb1_rows_1929_0_pop10_),
.feedback_in(feedback_data_in_10),
.feedback_valid_in(feedback_valid_in_10),
.feedback_stall_out(feedback_stall_out_10)
);
defparam local_bb1_rows_1929_0_pop10__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1929_0_pop10__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1929_0_pop10__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1931_0_pop8__stall_local;
wire [7:0] local_bb1_rows_1931_0_pop8_;
wire local_bb1_rows_1931_0_pop8__fu_valid_out;
wire local_bb1_rows_1931_0_pop8__fu_stall_out;
acl_pop local_bb1_rows_1931_0_pop8__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene1_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1931_0_pop8__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1931_0_pop8__fu_valid_out),
.stall_in(local_bb1_rows_1931_0_pop8__stall_local),
.data_out(local_bb1_rows_1931_0_pop8_),
.feedback_in(feedback_data_in_8),
.feedback_valid_in(feedback_valid_in_8),
.feedback_stall_out(feedback_stall_out_8)
);
defparam local_bb1_rows_1931_0_pop8__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1931_0_pop8__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1931_0_pop8__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1932_0_pop7__valid_out;
wire local_bb1_rows_1932_0_pop7__stall_in;
wire local_bb1_rows_1932_0_pop7__inputs_ready;
wire local_bb1_rows_1932_0_pop7__stall_local;
wire [7:0] local_bb1_rows_1932_0_pop7_;
wire local_bb1_rows_1932_0_pop7__fu_valid_out;
wire local_bb1_rows_1932_0_pop7__fu_stall_out;
acl_pop local_bb1_rows_1932_0_pop7__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene1_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1932_0_pop7__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1932_0_pop7__fu_valid_out),
.stall_in(local_bb1_rows_1932_0_pop7__stall_local),
.data_out(local_bb1_rows_1932_0_pop7_),
.feedback_in(feedback_data_in_7),
.feedback_valid_in(feedback_valid_in_7),
.feedback_stall_out(feedback_stall_out_7)
);
defparam local_bb1_rows_1932_0_pop7__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1932_0_pop7__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1932_0_pop7__inputs_ready = rnode_166to167_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1_rows_1932_0_pop7__stall_local = 1'b0;
assign local_bb1_rows_1932_0_pop7__valid_out = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1930_0_pop9__stall_local;
wire [7:0] local_bb1_rows_1930_0_pop9_;
wire local_bb1_rows_1930_0_pop9__fu_valid_out;
wire local_bb1_rows_1930_0_pop9__fu_stall_out;
acl_pop local_bb1_rows_1930_0_pop9__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene1_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1930_0_pop9__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1930_0_pop9__fu_valid_out),
.stall_in(local_bb1_rows_1930_0_pop9__stall_local),
.data_out(local_bb1_rows_1930_0_pop9_),
.feedback_in(feedback_data_in_9),
.feedback_valid_in(feedback_valid_in_9),
.feedback_stall_out(feedback_stall_out_9)
);
defparam local_bb1_rows_1930_0_pop9__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1930_0_pop9__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1930_0_pop9__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1927_0_pop12__stall_local;
wire [7:0] local_bb1_rows_1927_0_pop12_;
wire local_bb1_rows_1927_0_pop12__fu_valid_out;
wire local_bb1_rows_1927_0_pop12__fu_stall_out;
acl_pop local_bb1_rows_1927_0_pop12__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene1_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1927_0_pop12__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1927_0_pop12__fu_valid_out),
.stall_in(local_bb1_rows_1927_0_pop12__stall_local),
.data_out(local_bb1_rows_1927_0_pop12_),
.feedback_in(feedback_data_in_12),
.feedback_valid_in(feedback_valid_in_12),
.feedback_stall_out(feedback_stall_out_12)
);
defparam local_bb1_rows_1927_0_pop12__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1927_0_pop12__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1927_0_pop12__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1928_0_pop11__stall_local;
wire [7:0] local_bb1_rows_1928_0_pop11_;
wire local_bb1_rows_1928_0_pop11__fu_valid_out;
wire local_bb1_rows_1928_0_pop11__fu_stall_out;
acl_pop local_bb1_rows_1928_0_pop11__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene1_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1928_0_pop11__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1928_0_pop11__fu_valid_out),
.stall_in(local_bb1_rows_1928_0_pop11__stall_local),
.data_out(local_bb1_rows_1928_0_pop11_),
.feedback_in(feedback_data_in_11),
.feedback_valid_in(feedback_valid_in_11),
.feedback_stall_out(feedback_stall_out_11)
);
defparam local_bb1_rows_1928_0_pop11__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1928_0_pop11__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1928_0_pop11__stall_local = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_2_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_3_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_4_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_5_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_6_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_7_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_7_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_7_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_8_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_8_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_8_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_9_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_9_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_9_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_10_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_10_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_10_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene1_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_c0_ene1_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_c0_ene1_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_c0_ene1_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_c0_ene1_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_c0_ene1_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_c0_ene1_6_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_c0_ene1_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_c0_ene1_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_c0_ene1_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_c0_ene1_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_c0_ene1_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_1_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_2_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_3_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_4_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_5_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_6_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_7_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_7_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_8_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_8_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_9_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_9_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene1_0_valid_out_10_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_10_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene1_0_reg_168_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_2_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_3_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_4_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_5_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_6_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_7_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_8_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_8_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_8_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_9_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_9_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_9_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_c0_ene2_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_c0_ene2_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_c0_ene2_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_c0_ene2_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_c0_ene2_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_c0_ene2_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_c0_ene2_6_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_c0_ene2_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_c0_ene2_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_c0_ene2_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_c0_ene2_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_c0_ene2_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_0_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_1_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_2_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_3_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_4_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_5_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_6_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_7_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_8_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_8_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_c0_ene2_0_valid_out_9_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_9_NO_SHIFT_REG = rnode_167to168_bb1_c0_ene2_0_reg_168_NO_SHIFT_REG;
// Register node:
// * latency = 4
// * capacity = 4
logic rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_valid_out_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG),
.data_out(rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_fifo.DEPTH = 4;
defparam rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_0_0_push35_c0_ene3_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG = rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_reg_170_NO_SHIFT_REG;
assign rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__333_stall_local;
wire [7:0] local_bb1__333;
assign local_bb1__333 = (local_bb1__ ? local_bb1_isMin_3 : 8'h1);
// Register node:
// * latency = 4
// * capacity = 4
logic rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG),
.data_out(rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_fifo.DEPTH = 4;
defparam rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG = rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_170_NO_SHIFT_REG;
assign rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 4
// * capacity = 4
logic rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG),
.data_out(rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_fifo.DEPTH = 4;
defparam rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG = rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_170_NO_SHIFT_REG;
assign rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_16_stall_local;
wire local_bb1_not_cmp16_16;
assign local_bb1_not_cmp16_16 = (rnode_165to166_bb1_cmp16_16_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1921_0_push18_rows_1920_0_pop19_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1921_0_push18_rows_1920_0_pop19_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_1_1_stall_local;
wire local_bb1_not_cmp16_1_1;
assign local_bb1_not_cmp16_1_1 = (local_bb1_cmp16_1_1 ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_15_0_push20_rows_14_0_pop21_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_15_0_push20_rows_14_0_pop21_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_15_stall_local;
wire local_bb1_not_cmp16_15;
assign local_bb1_not_cmp16_15 = (rnode_165to166_bb1_cmp16_15_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_14_0_push21_rows_13_0_pop22_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_14_0_push21_rows_13_0_pop22_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_14_stall_local;
wire local_bb1_not_cmp16_14;
assign local_bb1_not_cmp16_14 = (rnode_165to166_bb1_cmp16_14_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_13_0_push22_rows_12_0_pop23_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_13_0_push22_rows_12_0_pop23_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_13_stall_local;
wire local_bb1_not_cmp16_13;
assign local_bb1_not_cmp16_13 = (rnode_165to166_bb1_cmp16_13_1_NO_SHIFT_REG ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1_rows_12_0_push23_rows_11_0_pop24_inputs_ready;
reg local_bb1_rows_12_0_push23_rows_11_0_pop24_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_12_0_push23_rows_11_0_pop24_stall_in;
wire local_bb1_rows_12_0_push23_rows_11_0_pop24_output_regs_ready;
wire [7:0] local_bb1_rows_12_0_push23_rows_11_0_pop24_result;
wire local_bb1_rows_12_0_push23_rows_11_0_pop24_fu_valid_out;
wire local_bb1_rows_12_0_push23_rows_11_0_pop24_fu_stall_out;
reg [7:0] local_bb1_rows_12_0_push23_rows_11_0_pop24_NO_SHIFT_REG;
wire local_bb1_rows_12_0_push23_rows_11_0_pop24_causedstall;
acl_push local_bb1_rows_12_0_push23_rows_11_0_pop24_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_165to166_bb1_rows_11_0_pop24__0_NO_SHIFT_REG),
.stall_out(local_bb1_rows_12_0_push23_rows_11_0_pop24_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_12_0_push23_rows_11_0_pop24_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_12_0_push23_rows_11_0_pop24_result),
.feedback_out(feedback_data_out_23),
.feedback_valid_out(feedback_valid_out_23),
.feedback_stall_in(feedback_stall_in_23)
);
defparam local_bb1_rows_12_0_push23_rows_11_0_pop24_feedback.STALLFREE = 1;
defparam local_bb1_rows_12_0_push23_rows_11_0_pop24_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_12_0_push23_rows_11_0_pop24_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_12_0_push23_rows_11_0_pop24_feedback.MIN_FIFO_LATENCY = 0;
defparam local_bb1_rows_12_0_push23_rows_11_0_pop24_feedback.STYLE = "REGULAR";
assign local_bb1_rows_12_0_push23_rows_11_0_pop24_inputs_ready = 1'b1;
assign local_bb1_rows_12_0_push23_rows_11_0_pop24_output_regs_ready = 1'b1;
assign rnode_165to166_bb1_rows_11_0_pop24__0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_12_0_push23_rows_11_0_pop24_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_12_0_push23_rows_11_0_pop24_NO_SHIFT_REG <= 'x;
local_bb1_rows_12_0_push23_rows_11_0_pop24_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_12_0_push23_rows_11_0_pop24_output_regs_ready)
begin
local_bb1_rows_12_0_push23_rows_11_0_pop24_NO_SHIFT_REG <= local_bb1_rows_12_0_push23_rows_11_0_pop24_result;
local_bb1_rows_12_0_push23_rows_11_0_pop24_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_12_0_push23_rows_11_0_pop24_stall_in))
begin
local_bb1_rows_12_0_push23_rows_11_0_pop24_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_12_stall_local;
wire local_bb1_not_cmp16_12;
assign local_bb1_not_cmp16_12 = (rnode_165to166_bb1_cmp16_12_1_NO_SHIFT_REG ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_121_stall_local;
wire local_bb1_cmp16_121;
assign local_bb1_cmp16_121 = (local_bb1_rows_1919_0_coalesced_pop3_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_not_select6_valid_out_1;
wire local_bb1_not_select6_stall_in_1;
reg local_bb1_not_select6_consumed_1_NO_SHIFT_REG;
wire local_bb1_next_coalesce_valid_out;
wire local_bb1_next_coalesce_stall_in;
reg local_bb1_next_coalesce_consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_1919_0_coalesced_pop3__valid_out_0;
wire local_bb1_rows_1919_0_coalesced_pop3__stall_in_0;
reg local_bb1_rows_1919_0_coalesced_pop3__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_121_valid_out;
wire local_bb1_cmp16_121_stall_in;
reg local_bb1_cmp16_121_consumed_0_NO_SHIFT_REG;
wire local_bb1_next_coalesce_inputs_ready;
wire local_bb1_next_coalesce_stall_local;
wire [11:0] local_bb1_next_coalesce;
assign local_bb1_next_coalesce_inputs_ready = rnode_164to165_bb1_c0_ene1_0_valid_out_9_NO_SHIFT_REG;
assign local_bb1_next_coalesce = (local_bb1_coalesce_counter_pop54_acl_pop_i12_1903 - local_bb1_next_coalesce_select);
assign local_bb1_not_select6_valid_out_1 = 1'b1;
assign local_bb1_next_coalesce_valid_out = 1'b1;
assign local_bb1_rows_1919_0_coalesced_pop3__valid_out_0 = 1'b1;
assign local_bb1_cmp16_121_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_9_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_not_select6_consumed_1_NO_SHIFT_REG <= 1'b0;
local_bb1_next_coalesce_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_1919_0_coalesced_pop3__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_121_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_not_select6_consumed_1_NO_SHIFT_REG <= (local_bb1_next_coalesce_inputs_ready & (local_bb1_not_select6_consumed_1_NO_SHIFT_REG | ~(local_bb1_not_select6_stall_in_1)) & local_bb1_next_coalesce_stall_local);
local_bb1_next_coalesce_consumed_0_NO_SHIFT_REG <= (local_bb1_next_coalesce_inputs_ready & (local_bb1_next_coalesce_consumed_0_NO_SHIFT_REG | ~(local_bb1_next_coalesce_stall_in)) & local_bb1_next_coalesce_stall_local);
local_bb1_rows_1919_0_coalesced_pop3__consumed_0_NO_SHIFT_REG <= (local_bb1_next_coalesce_inputs_ready & (local_bb1_rows_1919_0_coalesced_pop3__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1919_0_coalesced_pop3__stall_in_0)) & local_bb1_next_coalesce_stall_local);
local_bb1_cmp16_121_consumed_0_NO_SHIFT_REG <= (local_bb1_next_coalesce_inputs_ready & (local_bb1_cmp16_121_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_121_stall_in)) & local_bb1_next_coalesce_stall_local);
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_1927_0_push12_rows_1926_0_pop13_inputs_ready;
reg local_bb1_rows_1927_0_push12_rows_1926_0_pop13_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1927_0_push12_rows_1926_0_pop13_stall_in;
wire local_bb1_rows_1927_0_push12_rows_1926_0_pop13_output_regs_ready;
wire [7:0] local_bb1_rows_1927_0_push12_rows_1926_0_pop13_result;
wire local_bb1_rows_1927_0_push12_rows_1926_0_pop13_fu_valid_out;
wire local_bb1_rows_1927_0_push12_rows_1926_0_pop13_fu_stall_out;
reg [7:0] local_bb1_rows_1927_0_push12_rows_1926_0_pop13_NO_SHIFT_REG;
wire local_bb1_rows_1927_0_push12_rows_1926_0_pop13_causedstall;
acl_push local_bb1_rows_1927_0_push12_rows_1926_0_pop13_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene2_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_166to167_bb1_rows_1926_0_pop13__0_NO_SHIFT_REG),
.stall_out(local_bb1_rows_1927_0_push12_rows_1926_0_pop13_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1927_0_push12_rows_1926_0_pop13_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1927_0_push12_rows_1926_0_pop13_result),
.feedback_out(feedback_data_out_12),
.feedback_valid_out(feedback_valid_out_12),
.feedback_stall_in(feedback_stall_in_12)
);
defparam local_bb1_rows_1927_0_push12_rows_1926_0_pop13_feedback.STALLFREE = 1;
defparam local_bb1_rows_1927_0_push12_rows_1926_0_pop13_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1927_0_push12_rows_1926_0_pop13_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1927_0_push12_rows_1926_0_pop13_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1927_0_push12_rows_1926_0_pop13_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1927_0_push12_rows_1926_0_pop13_inputs_ready = 1'b1;
assign local_bb1_rows_1927_0_push12_rows_1926_0_pop13_output_regs_ready = 1'b1;
assign rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1927_0_push12_rows_1926_0_pop13_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[5] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1927_0_push12_rows_1926_0_pop13_NO_SHIFT_REG <= 'x;
local_bb1_rows_1927_0_push12_rows_1926_0_pop13_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1927_0_push12_rows_1926_0_pop13_output_regs_ready)
begin
local_bb1_rows_1927_0_push12_rows_1926_0_pop13_NO_SHIFT_REG <= local_bb1_rows_1927_0_push12_rows_1926_0_pop13_result;
local_bb1_rows_1927_0_push12_rows_1926_0_pop13_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1927_0_push12_rows_1926_0_pop13_stall_in))
begin
local_bb1_rows_1927_0_push12_rows_1926_0_pop13_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_7_1_stall_local;
wire local_bb1_cmp16_7_1;
assign local_bb1_cmp16_7_1 = (rnode_166to167_bb1_rows_1926_0_pop13__1_NO_SHIFT_REG == 8'h0);
// This section implements a registered operation.
//
wire local_bb1_rows_1926_0_push13_rows_1925_0_pop14_inputs_ready;
reg local_bb1_rows_1926_0_push13_rows_1925_0_pop14_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1926_0_push13_rows_1925_0_pop14_stall_in;
wire local_bb1_rows_1926_0_push13_rows_1925_0_pop14_output_regs_ready;
wire [7:0] local_bb1_rows_1926_0_push13_rows_1925_0_pop14_result;
wire local_bb1_rows_1926_0_push13_rows_1925_0_pop14_fu_valid_out;
wire local_bb1_rows_1926_0_push13_rows_1925_0_pop14_fu_stall_out;
reg [7:0] local_bb1_rows_1926_0_push13_rows_1925_0_pop14_NO_SHIFT_REG;
wire local_bb1_rows_1926_0_push13_rows_1925_0_pop14_causedstall;
acl_push local_bb1_rows_1926_0_push13_rows_1925_0_pop14_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1925_0_pop14_),
.stall_out(local_bb1_rows_1926_0_push13_rows_1925_0_pop14_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1926_0_push13_rows_1925_0_pop14_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1926_0_push13_rows_1925_0_pop14_result),
.feedback_out(feedback_data_out_13),
.feedback_valid_out(feedback_valid_out_13),
.feedback_stall_in(feedback_stall_in_13)
);
defparam local_bb1_rows_1926_0_push13_rows_1925_0_pop14_feedback.STALLFREE = 1;
defparam local_bb1_rows_1926_0_push13_rows_1925_0_pop14_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1926_0_push13_rows_1925_0_pop14_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1926_0_push13_rows_1925_0_pop14_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1926_0_push13_rows_1925_0_pop14_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1926_0_push13_rows_1925_0_pop14_inputs_ready = 1'b1;
assign local_bb1_rows_1926_0_push13_rows_1925_0_pop14_output_regs_ready = 1'b1;
assign local_bb1_rows_1925_0_pop14__stall_in_0 = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1926_0_push13_rows_1925_0_pop14_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1926_0_push13_rows_1925_0_pop14_NO_SHIFT_REG <= 'x;
local_bb1_rows_1926_0_push13_rows_1925_0_pop14_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1926_0_push13_rows_1925_0_pop14_output_regs_ready)
begin
local_bb1_rows_1926_0_push13_rows_1925_0_pop14_NO_SHIFT_REG <= local_bb1_rows_1926_0_push13_rows_1925_0_pop14_result;
local_bb1_rows_1926_0_push13_rows_1925_0_pop14_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1926_0_push13_rows_1925_0_pop14_stall_in))
begin
local_bb1_rows_1926_0_push13_rows_1925_0_pop14_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_cmp16_6_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_6_1_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_cmp16_6_1_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_cmp16_6_1_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_cmp16_6_1_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_cmp16_6_1_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_cmp16_6_1_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_6_1),
.data_out(rnode_166to167_bb1_cmp16_6_1_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_cmp16_6_1_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp16_6_1_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp16_6_1_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp16_6_1_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_cmp16_6_1_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_6_1_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp16_6_1_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_6_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_6_1_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_6_1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp16_6_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_6_1_1_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_6_1_0_reg_167_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1925_0_push14_rows_1924_0_pop15_inputs_ready;
reg local_bb1_rows_1925_0_push14_rows_1924_0_pop15_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1925_0_push14_rows_1924_0_pop15_stall_in;
wire local_bb1_rows_1925_0_push14_rows_1924_0_pop15_output_regs_ready;
wire [7:0] local_bb1_rows_1925_0_push14_rows_1924_0_pop15_result;
wire local_bb1_rows_1925_0_push14_rows_1924_0_pop15_fu_valid_out;
wire local_bb1_rows_1925_0_push14_rows_1924_0_pop15_fu_stall_out;
reg [7:0] local_bb1_rows_1925_0_push14_rows_1924_0_pop15_NO_SHIFT_REG;
wire local_bb1_rows_1925_0_push14_rows_1924_0_pop15_causedstall;
acl_push local_bb1_rows_1925_0_push14_rows_1924_0_pop15_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1924_0_pop15_),
.stall_out(local_bb1_rows_1925_0_push14_rows_1924_0_pop15_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1925_0_push14_rows_1924_0_pop15_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1925_0_push14_rows_1924_0_pop15_result),
.feedback_out(feedback_data_out_14),
.feedback_valid_out(feedback_valid_out_14),
.feedback_stall_in(feedback_stall_in_14)
);
defparam local_bb1_rows_1925_0_push14_rows_1924_0_pop15_feedback.STALLFREE = 1;
defparam local_bb1_rows_1925_0_push14_rows_1924_0_pop15_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1925_0_push14_rows_1924_0_pop15_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1925_0_push14_rows_1924_0_pop15_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1925_0_push14_rows_1924_0_pop15_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1925_0_push14_rows_1924_0_pop15_inputs_ready = 1'b1;
assign local_bb1_rows_1925_0_push14_rows_1924_0_pop15_output_regs_ready = 1'b1;
assign local_bb1_rows_1924_0_pop15__stall_in_0 = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1925_0_push14_rows_1924_0_pop15_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1925_0_push14_rows_1924_0_pop15_NO_SHIFT_REG <= 'x;
local_bb1_rows_1925_0_push14_rows_1924_0_pop15_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1925_0_push14_rows_1924_0_pop15_output_regs_ready)
begin
local_bb1_rows_1925_0_push14_rows_1924_0_pop15_NO_SHIFT_REG <= local_bb1_rows_1925_0_push14_rows_1924_0_pop15_result;
local_bb1_rows_1925_0_push14_rows_1924_0_pop15_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1925_0_push14_rows_1924_0_pop15_stall_in))
begin
local_bb1_rows_1925_0_push14_rows_1924_0_pop15_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_cmp16_5_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_5_1_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_cmp16_5_1_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_cmp16_5_1_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_cmp16_5_1_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_cmp16_5_1_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_cmp16_5_1_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_5_1),
.data_out(rnode_166to167_bb1_cmp16_5_1_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_cmp16_5_1_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp16_5_1_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp16_5_1_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp16_5_1_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_cmp16_5_1_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_5_1_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp16_5_1_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_5_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_5_1_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_5_1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp16_5_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_5_1_1_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_5_1_0_reg_167_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1924_0_push15_rows_1923_0_pop16_inputs_ready;
reg local_bb1_rows_1924_0_push15_rows_1923_0_pop16_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1924_0_push15_rows_1923_0_pop16_stall_in;
wire local_bb1_rows_1924_0_push15_rows_1923_0_pop16_output_regs_ready;
wire [7:0] local_bb1_rows_1924_0_push15_rows_1923_0_pop16_result;
wire local_bb1_rows_1924_0_push15_rows_1923_0_pop16_fu_valid_out;
wire local_bb1_rows_1924_0_push15_rows_1923_0_pop16_fu_stall_out;
reg [7:0] local_bb1_rows_1924_0_push15_rows_1923_0_pop16_NO_SHIFT_REG;
wire local_bb1_rows_1924_0_push15_rows_1923_0_pop16_causedstall;
acl_push local_bb1_rows_1924_0_push15_rows_1923_0_pop16_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1923_0_pop16_),
.stall_out(local_bb1_rows_1924_0_push15_rows_1923_0_pop16_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1924_0_push15_rows_1923_0_pop16_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1924_0_push15_rows_1923_0_pop16_result),
.feedback_out(feedback_data_out_15),
.feedback_valid_out(feedback_valid_out_15),
.feedback_stall_in(feedback_stall_in_15)
);
defparam local_bb1_rows_1924_0_push15_rows_1923_0_pop16_feedback.STALLFREE = 1;
defparam local_bb1_rows_1924_0_push15_rows_1923_0_pop16_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1924_0_push15_rows_1923_0_pop16_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1924_0_push15_rows_1923_0_pop16_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1924_0_push15_rows_1923_0_pop16_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1924_0_push15_rows_1923_0_pop16_inputs_ready = 1'b1;
assign local_bb1_rows_1924_0_push15_rows_1923_0_pop16_output_regs_ready = 1'b1;
assign local_bb1_rows_1923_0_pop16__stall_in_0 = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1924_0_push15_rows_1923_0_pop16_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1924_0_push15_rows_1923_0_pop16_NO_SHIFT_REG <= 'x;
local_bb1_rows_1924_0_push15_rows_1923_0_pop16_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1924_0_push15_rows_1923_0_pop16_output_regs_ready)
begin
local_bb1_rows_1924_0_push15_rows_1923_0_pop16_NO_SHIFT_REG <= local_bb1_rows_1924_0_push15_rows_1923_0_pop16_result;
local_bb1_rows_1924_0_push15_rows_1923_0_pop16_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1924_0_push15_rows_1923_0_pop16_stall_in))
begin
local_bb1_rows_1924_0_push15_rows_1923_0_pop16_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_cmp16_4_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_4_1_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_cmp16_4_1_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_cmp16_4_1_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_cmp16_4_1_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_cmp16_4_1_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_cmp16_4_1_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_4_1),
.data_out(rnode_166to167_bb1_cmp16_4_1_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_cmp16_4_1_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp16_4_1_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp16_4_1_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp16_4_1_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_cmp16_4_1_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_4_1_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp16_4_1_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_4_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_4_1_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_4_1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp16_4_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_4_1_1_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_4_1_0_reg_167_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1923_0_push16_rows_1922_0_pop17_inputs_ready;
reg local_bb1_rows_1923_0_push16_rows_1922_0_pop17_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1923_0_push16_rows_1922_0_pop17_stall_in;
wire local_bb1_rows_1923_0_push16_rows_1922_0_pop17_output_regs_ready;
wire [7:0] local_bb1_rows_1923_0_push16_rows_1922_0_pop17_result;
wire local_bb1_rows_1923_0_push16_rows_1922_0_pop17_fu_valid_out;
wire local_bb1_rows_1923_0_push16_rows_1922_0_pop17_fu_stall_out;
reg [7:0] local_bb1_rows_1923_0_push16_rows_1922_0_pop17_NO_SHIFT_REG;
wire local_bb1_rows_1923_0_push16_rows_1922_0_pop17_causedstall;
acl_push local_bb1_rows_1923_0_push16_rows_1922_0_pop17_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1922_0_pop17_),
.stall_out(local_bb1_rows_1923_0_push16_rows_1922_0_pop17_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1923_0_push16_rows_1922_0_pop17_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1923_0_push16_rows_1922_0_pop17_result),
.feedback_out(feedback_data_out_16),
.feedback_valid_out(feedback_valid_out_16),
.feedback_stall_in(feedback_stall_in_16)
);
defparam local_bb1_rows_1923_0_push16_rows_1922_0_pop17_feedback.STALLFREE = 1;
defparam local_bb1_rows_1923_0_push16_rows_1922_0_pop17_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1923_0_push16_rows_1922_0_pop17_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1923_0_push16_rows_1922_0_pop17_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1923_0_push16_rows_1922_0_pop17_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1923_0_push16_rows_1922_0_pop17_inputs_ready = 1'b1;
assign local_bb1_rows_1923_0_push16_rows_1922_0_pop17_output_regs_ready = 1'b1;
assign local_bb1_rows_1922_0_pop17__stall_in_0 = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1923_0_push16_rows_1922_0_pop17_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1923_0_push16_rows_1922_0_pop17_NO_SHIFT_REG <= 'x;
local_bb1_rows_1923_0_push16_rows_1922_0_pop17_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1923_0_push16_rows_1922_0_pop17_output_regs_ready)
begin
local_bb1_rows_1923_0_push16_rows_1922_0_pop17_NO_SHIFT_REG <= local_bb1_rows_1923_0_push16_rows_1922_0_pop17_result;
local_bb1_rows_1923_0_push16_rows_1922_0_pop17_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1923_0_push16_rows_1922_0_pop17_stall_in))
begin
local_bb1_rows_1923_0_push16_rows_1922_0_pop17_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_cmp16_3_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_3_1_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_cmp16_3_1_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_cmp16_3_1_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_cmp16_3_1_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_cmp16_3_1_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_cmp16_3_1_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_3_1),
.data_out(rnode_166to167_bb1_cmp16_3_1_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_cmp16_3_1_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp16_3_1_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp16_3_1_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp16_3_1_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_cmp16_3_1_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_3_1_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp16_3_1_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_3_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_3_1_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_3_1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp16_3_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_3_1_1_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_3_1_0_reg_167_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1922_0_push17_rows_1921_0_pop18_inputs_ready;
reg local_bb1_rows_1922_0_push17_rows_1921_0_pop18_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1922_0_push17_rows_1921_0_pop18_stall_in;
wire local_bb1_rows_1922_0_push17_rows_1921_0_pop18_output_regs_ready;
wire [7:0] local_bb1_rows_1922_0_push17_rows_1921_0_pop18_result;
wire local_bb1_rows_1922_0_push17_rows_1921_0_pop18_fu_valid_out;
wire local_bb1_rows_1922_0_push17_rows_1921_0_pop18_fu_stall_out;
reg [7:0] local_bb1_rows_1922_0_push17_rows_1921_0_pop18_NO_SHIFT_REG;
wire local_bb1_rows_1922_0_push17_rows_1921_0_pop18_causedstall;
acl_push local_bb1_rows_1922_0_push17_rows_1921_0_pop18_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_165to166_bb1_c0_ene2_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1921_0_pop18_),
.stall_out(local_bb1_rows_1922_0_push17_rows_1921_0_pop18_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[4]),
.valid_out(local_bb1_rows_1922_0_push17_rows_1921_0_pop18_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1922_0_push17_rows_1921_0_pop18_result),
.feedback_out(feedback_data_out_17),
.feedback_valid_out(feedback_valid_out_17),
.feedback_stall_in(feedback_stall_in_17)
);
defparam local_bb1_rows_1922_0_push17_rows_1921_0_pop18_feedback.STALLFREE = 1;
defparam local_bb1_rows_1922_0_push17_rows_1921_0_pop18_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1922_0_push17_rows_1921_0_pop18_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1922_0_push17_rows_1921_0_pop18_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1922_0_push17_rows_1921_0_pop18_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1922_0_push17_rows_1921_0_pop18_inputs_ready = 1'b1;
assign local_bb1_rows_1922_0_push17_rows_1921_0_pop18_output_regs_ready = 1'b1;
assign local_bb1_rows_1921_0_pop18__stall_in_0 = 1'b0;
assign rnode_165to166_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1922_0_push17_rows_1921_0_pop18_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[4] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1922_0_push17_rows_1921_0_pop18_NO_SHIFT_REG <= 'x;
local_bb1_rows_1922_0_push17_rows_1921_0_pop18_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1922_0_push17_rows_1921_0_pop18_output_regs_ready)
begin
local_bb1_rows_1922_0_push17_rows_1921_0_pop18_NO_SHIFT_REG <= local_bb1_rows_1922_0_push17_rows_1921_0_pop18_result;
local_bb1_rows_1922_0_push17_rows_1921_0_pop18_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1922_0_push17_rows_1921_0_pop18_stall_in))
begin
local_bb1_rows_1922_0_push17_rows_1921_0_pop18_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_cmp16_2_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_1_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_valid_out_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_stall_in_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_cmp16_2_1_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_cmp16_2_1_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_cmp16_2_1_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_cmp16_2_1_0_stall_in_0_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_cmp16_2_1_0_valid_out_0_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_cmp16_2_1_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_2_1),
.data_out(rnode_166to167_bb1_cmp16_2_1_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_cmp16_2_1_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp16_2_1_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp16_2_1_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp16_2_1_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_cmp16_2_1_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_2_1_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp16_2_1_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_2_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_2_1_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_2_1_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp16_2_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_cmp16_2_1_1_NO_SHIFT_REG = rnode_166to167_bb1_cmp16_2_1_0_reg_167_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1929_0_pop10__valid_out_0;
wire local_bb1_rows_1929_0_pop10__stall_in_0;
reg local_bb1_rows_1929_0_pop10__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_10_1_valid_out;
wire local_bb1_cmp16_10_1_stall_in;
reg local_bb1_cmp16_10_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_10_1_inputs_ready;
wire local_bb1_cmp16_10_1_stall_local;
wire local_bb1_cmp16_10_1;
assign local_bb1_cmp16_10_1_inputs_ready = rnode_166to167_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_cmp16_10_1 = (local_bb1_rows_1929_0_pop10_ == 8'h0);
assign local_bb1_rows_1929_0_pop10__valid_out_0 = 1'b1;
assign local_bb1_cmp16_10_1_valid_out = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1929_0_pop10__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_10_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1929_0_pop10__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_10_1_inputs_ready & (local_bb1_rows_1929_0_pop10__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1929_0_pop10__stall_in_0)) & local_bb1_cmp16_10_1_stall_local);
local_bb1_cmp16_10_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_10_1_inputs_ready & (local_bb1_cmp16_10_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_10_1_stall_in)) & local_bb1_cmp16_10_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_rows_1931_0_pop8__valid_out_0;
wire local_bb1_rows_1931_0_pop8__stall_in_0;
reg local_bb1_rows_1931_0_pop8__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_12_1_valid_out;
wire local_bb1_cmp16_12_1_stall_in;
reg local_bb1_cmp16_12_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_12_1_inputs_ready;
wire local_bb1_cmp16_12_1_stall_local;
wire local_bb1_cmp16_12_1;
assign local_bb1_cmp16_12_1_inputs_ready = rnode_166to167_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_cmp16_12_1 = (local_bb1_rows_1931_0_pop8_ == 8'h0);
assign local_bb1_rows_1931_0_pop8__valid_out_0 = 1'b1;
assign local_bb1_cmp16_12_1_valid_out = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1931_0_pop8__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_12_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1931_0_pop8__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_12_1_inputs_ready & (local_bb1_rows_1931_0_pop8__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1931_0_pop8__stall_in_0)) & local_bb1_cmp16_12_1_stall_local);
local_bb1_cmp16_12_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_12_1_inputs_ready & (local_bb1_cmp16_12_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_12_1_stall_in)) & local_bb1_cmp16_12_1_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1932_0_pop7__0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1932_0_pop7__1_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1932_0_pop7__0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1932_0_pop7__0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1932_0_pop7_),
.data_out(rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1932_0_pop7__stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1932_0_pop7__0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1932_0_pop7__1_NO_SHIFT_REG = rnode_167to168_bb1_rows_1932_0_pop7__0_reg_168_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1930_0_pop9__valid_out_0;
wire local_bb1_rows_1930_0_pop9__stall_in_0;
reg local_bb1_rows_1930_0_pop9__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_11_1_valid_out;
wire local_bb1_cmp16_11_1_stall_in;
reg local_bb1_cmp16_11_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_11_1_inputs_ready;
wire local_bb1_cmp16_11_1_stall_local;
wire local_bb1_cmp16_11_1;
assign local_bb1_cmp16_11_1_inputs_ready = rnode_166to167_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
assign local_bb1_cmp16_11_1 = (local_bb1_rows_1930_0_pop9_ == 8'h0);
assign local_bb1_rows_1930_0_pop9__valid_out_0 = 1'b1;
assign local_bb1_cmp16_11_1_valid_out = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1930_0_pop9__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_11_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1930_0_pop9__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_11_1_inputs_ready & (local_bb1_rows_1930_0_pop9__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1930_0_pop9__stall_in_0)) & local_bb1_cmp16_11_1_stall_local);
local_bb1_cmp16_11_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_11_1_inputs_ready & (local_bb1_cmp16_11_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_11_1_stall_in)) & local_bb1_cmp16_11_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_8_1_stall_local;
wire local_bb1_cmp16_8_1;
assign local_bb1_cmp16_8_1 = (local_bb1_rows_1927_0_pop12_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_rows_1928_0_pop11__valid_out_0;
wire local_bb1_rows_1928_0_pop11__stall_in_0;
reg local_bb1_rows_1928_0_pop11__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_9_1_valid_out;
wire local_bb1_cmp16_9_1_stall_in;
reg local_bb1_cmp16_9_1_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_9_1_inputs_ready;
wire local_bb1_cmp16_9_1_stall_local;
wire local_bb1_cmp16_9_1;
assign local_bb1_cmp16_9_1_inputs_ready = rnode_166to167_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
assign local_bb1_cmp16_9_1 = (local_bb1_rows_1928_0_pop11_ == 8'h0);
assign local_bb1_rows_1928_0_pop11__valid_out_0 = 1'b1;
assign local_bb1_cmp16_9_1_valid_out = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1928_0_pop11__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_9_1_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1928_0_pop11__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_9_1_inputs_ready & (local_bb1_rows_1928_0_pop11__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1928_0_pop11__stall_in_0)) & local_bb1_cmp16_9_1_stall_local);
local_bb1_cmp16_9_1_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_9_1_inputs_ready & (local_bb1_cmp16_9_1_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_9_1_stall_in)) & local_bb1_cmp16_9_1_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop40__stall_local;
wire [7:0] local_bb1__pop40_;
wire local_bb1__pop40__fu_valid_out;
wire local_bb1__pop40__fu_stall_out;
acl_pop local_bb1__pop40__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop40__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop40__fu_valid_out),
.stall_in(local_bb1__pop40__stall_local),
.data_out(local_bb1__pop40_),
.feedback_in(feedback_data_in_40),
.feedback_valid_in(feedback_valid_in_40),
.feedback_stall_out(feedback_stall_out_40)
);
defparam local_bb1__pop40__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop40__feedback.STYLE = "REGULAR";
assign local_bb1__pop40__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop41__stall_local;
wire [7:0] local_bb1__pop41_;
wire local_bb1__pop41__fu_valid_out;
wire local_bb1__pop41__fu_stall_out;
acl_pop local_bb1__pop41__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop41__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop41__fu_valid_out),
.stall_in(local_bb1__pop41__stall_local),
.data_out(local_bb1__pop41_),
.feedback_in(feedback_data_in_41),
.feedback_valid_in(feedback_valid_in_41),
.feedback_stall_out(feedback_stall_out_41)
);
defparam local_bb1__pop41__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop41__feedback.STYLE = "REGULAR";
assign local_bb1__pop41__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop42__valid_out;
wire local_bb1__pop42__stall_in;
wire local_bb1__pop42__inputs_ready;
wire local_bb1__pop42__stall_local;
wire [7:0] local_bb1__pop42_;
wire local_bb1__pop42__fu_valid_out;
wire local_bb1__pop42__fu_stall_out;
acl_pop local_bb1__pop42__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop42__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop42__fu_valid_out),
.stall_in(local_bb1__pop42__stall_local),
.data_out(local_bb1__pop42_),
.feedback_in(feedback_data_in_42),
.feedback_valid_in(feedback_valid_in_42),
.feedback_stall_out(feedback_stall_out_42)
);
defparam local_bb1__pop42__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop42__feedback.STYLE = "REGULAR";
assign local_bb1__pop42__inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1__pop42__stall_local = 1'b0;
assign local_bb1__pop42__valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop36__valid_out;
wire local_bb1__pop36__stall_in;
wire local_bb1__pop36__inputs_ready;
wire local_bb1__pop36__stall_local;
wire [7:0] local_bb1__pop36_;
wire local_bb1__pop36__fu_valid_out;
wire local_bb1__pop36__fu_stall_out;
acl_pop local_bb1__pop36__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop36__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop36__fu_valid_out),
.stall_in(local_bb1__pop36__stall_local),
.data_out(local_bb1__pop36_),
.feedback_in(feedback_data_in_36),
.feedback_valid_in(feedback_valid_in_36),
.feedback_stall_out(feedback_stall_out_36)
);
defparam local_bb1__pop36__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop36__feedback.STYLE = "REGULAR";
assign local_bb1__pop36__inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
assign local_bb1__pop36__stall_local = 1'b0;
assign local_bb1__pop36__valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop37__stall_local;
wire [7:0] local_bb1__pop37_;
wire local_bb1__pop37__fu_valid_out;
wire local_bb1__pop37__fu_stall_out;
acl_pop local_bb1__pop37__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop37__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop37__fu_valid_out),
.stall_in(local_bb1__pop37__stall_local),
.data_out(local_bb1__pop37_),
.feedback_in(feedback_data_in_37),
.feedback_valid_in(feedback_valid_in_37),
.feedback_stall_out(feedback_stall_out_37)
);
defparam local_bb1__pop37__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop37__feedback.STYLE = "REGULAR";
assign local_bb1__pop37__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop38__stall_local;
wire [7:0] local_bb1__pop38_;
wire local_bb1__pop38__fu_valid_out;
wire local_bb1__pop38__fu_stall_out;
acl_pop local_bb1__pop38__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop38__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop38__fu_valid_out),
.stall_in(local_bb1__pop38__stall_local),
.data_out(local_bb1__pop38_),
.feedback_in(feedback_data_in_38),
.feedback_valid_in(feedback_valid_in_38),
.feedback_stall_out(feedback_stall_out_38)
);
defparam local_bb1__pop38__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop38__feedback.STYLE = "REGULAR";
assign local_bb1__pop38__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop39__stall_local;
wire [7:0] local_bb1__pop39_;
wire local_bb1__pop39__fu_valid_out;
wire local_bb1__pop39__fu_stall_out;
acl_pop local_bb1__pop39__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_6_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop39__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__pop39__fu_valid_out),
.stall_in(local_bb1__pop39__stall_local),
.data_out(local_bb1__pop39_),
.feedback_in(feedback_data_in_39),
.feedback_valid_in(feedback_valid_in_39),
.feedback_stall_out(feedback_stall_out_39)
);
defparam local_bb1__pop39__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop39__feedback.STYLE = "REGULAR";
assign local_bb1__pop39__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1933_0_pop6__stall_local;
wire [7:0] local_bb1_rows_1933_0_pop6_;
wire local_bb1_rows_1933_0_pop6__fu_valid_out;
wire local_bb1_rows_1933_0_pop6__fu_stall_out;
acl_pop local_bb1_rows_1933_0_pop6__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_7_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1933_0_pop6__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1_rows_1933_0_pop6__fu_valid_out),
.stall_in(local_bb1_rows_1933_0_pop6__stall_local),
.data_out(local_bb1_rows_1933_0_pop6_),
.feedback_in(feedback_data_in_6),
.feedback_valid_in(feedback_valid_in_6),
.feedback_stall_out(feedback_stall_out_6)
);
defparam local_bb1_rows_1933_0_pop6__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1933_0_pop6__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1933_0_pop6__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1934_0_pop5__stall_local;
wire [7:0] local_bb1_rows_1934_0_pop5_;
wire local_bb1_rows_1934_0_pop5__fu_valid_out;
wire local_bb1_rows_1934_0_pop5__fu_stall_out;
acl_pop local_bb1_rows_1934_0_pop5__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_8_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1934_0_pop5__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1_rows_1934_0_pop5__fu_valid_out),
.stall_in(local_bb1_rows_1934_0_pop5__stall_local),
.data_out(local_bb1_rows_1934_0_pop5_),
.feedback_in(feedback_data_in_5),
.feedback_valid_in(feedback_valid_in_5),
.feedback_stall_out(feedback_stall_out_5)
);
defparam local_bb1_rows_1934_0_pop5__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1934_0_pop5__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1934_0_pop5__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1_rows_1935_0_pop4__stall_local;
wire [7:0] local_bb1_rows_1935_0_pop4_;
wire local_bb1_rows_1935_0_pop4__fu_valid_out;
wire local_bb1_rows_1935_0_pop4__fu_stall_out;
acl_pop local_bb1_rows_1935_0_pop4__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene1_9_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1_rows_1935_0_pop4__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1_rows_1935_0_pop4__fu_valid_out),
.stall_in(local_bb1_rows_1935_0_pop4__stall_local),
.data_out(local_bb1_rows_1935_0_pop4_),
.feedback_in(feedback_data_in_4),
.feedback_valid_in(feedback_valid_in_4),
.feedback_stall_out(feedback_stall_out_4)
);
defparam local_bb1_rows_1935_0_pop4__feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1935_0_pop4__feedback.STYLE = "REGULAR";
assign local_bb1_rows_1935_0_pop4__stall_local = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_2_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_3_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_4_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_5_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_6_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene1_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_c0_ene1_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_c0_ene1_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_c0_ene1_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_c0_ene1_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_c0_ene1_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_c0_ene1_10_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_c0_ene1_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_c0_ene1_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_c0_ene1_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_c0_ene1_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_c0_ene1_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_10_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_1_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_2_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_3_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_4_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_5_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_6_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene1_0_reg_169_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_2_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_3_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_4_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_5_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_6_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_7_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_c0_ene2_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_c0_ene2_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_c0_ene2_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_c0_ene2_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_c0_ene2_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_c0_ene2_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_c0_ene2_9_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_c0_ene2_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_c0_ene2_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_c0_ene2_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_c0_ene2_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_c0_ene2_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_9_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_0_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_1_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_2_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_3_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_4_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_4_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_5_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_5_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_6_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_6_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_c0_ene2_0_valid_out_7_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_7_NO_SHIFT_REG = rnode_168to169_bb1_c0_ene2_0_reg_169_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to170_bb1_rows_0_0_push35_c0_ene3_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__335_stall_local;
wire [7:0] local_bb1__335;
assign local_bb1__335 = (local_bb1__334_demorgan ? local_bb1__333 : 8'h0);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to170_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to170_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_12_0_push23_rows_11_0_pop24_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_12_0_push23_rows_11_0_pop24_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_not_select6_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_stall_in_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_not_select6_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_not_select6_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_not_select6_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_not_select6_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_not_select6_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_not_select6_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_not_select6),
.data_out(rnode_165to166_bb1_not_select6_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_not_select6_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_not_select6_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_not_select6_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_not_select6_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_not_select6_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_not_select6_stall_in_1 = 1'b0;
assign rnode_165to166_bb1_not_select6_0_NO_SHIFT_REG = rnode_165to166_bb1_not_select6_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_not_select6_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_not_select6_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements a registered operation.
//
wire local_bb1_coalesce_counter_push54_next_coalesce_inputs_ready;
reg local_bb1_coalesce_counter_push54_next_coalesce_valid_out_NO_SHIFT_REG;
wire local_bb1_coalesce_counter_push54_next_coalesce_stall_in;
wire local_bb1_coalesce_counter_push54_next_coalesce_output_regs_ready;
wire [11:0] local_bb1_coalesce_counter_push54_next_coalesce_result;
wire local_bb1_coalesce_counter_push54_next_coalesce_fu_valid_out;
wire local_bb1_coalesce_counter_push54_next_coalesce_fu_stall_out;
reg [11:0] local_bb1_coalesce_counter_push54_next_coalesce_NO_SHIFT_REG;
wire local_bb1_coalesce_counter_push54_next_coalesce_causedstall;
acl_push local_bb1_coalesce_counter_push54_next_coalesce_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_9_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_next_coalesce),
.stall_out(local_bb1_coalesce_counter_push54_next_coalesce_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_coalesce_counter_push54_next_coalesce_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_coalesce_counter_push54_next_coalesce_result),
.feedback_out(feedback_data_out_54),
.feedback_valid_out(feedback_valid_out_54),
.feedback_stall_in(feedback_stall_in_54)
);
defparam local_bb1_coalesce_counter_push54_next_coalesce_feedback.STALLFREE = 1;
defparam local_bb1_coalesce_counter_push54_next_coalesce_feedback.DATA_WIDTH = 12;
defparam local_bb1_coalesce_counter_push54_next_coalesce_feedback.FIFO_DEPTH = 1;
defparam local_bb1_coalesce_counter_push54_next_coalesce_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_coalesce_counter_push54_next_coalesce_feedback.STYLE = "REGULAR";
assign local_bb1_coalesce_counter_push54_next_coalesce_inputs_ready = 1'b1;
assign local_bb1_coalesce_counter_push54_next_coalesce_output_regs_ready = 1'b1;
assign local_bb1_next_coalesce_stall_in = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_9_NO_SHIFT_REG = 1'b0;
assign local_bb1_coalesce_counter_push54_next_coalesce_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_coalesce_counter_push54_next_coalesce_NO_SHIFT_REG <= 'x;
local_bb1_coalesce_counter_push54_next_coalesce_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_coalesce_counter_push54_next_coalesce_output_regs_ready)
begin
local_bb1_coalesce_counter_push54_next_coalesce_NO_SHIFT_REG <= local_bb1_coalesce_counter_push54_next_coalesce_result;
local_bb1_coalesce_counter_push54_next_coalesce_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_coalesce_counter_push54_next_coalesce_stall_in))
begin
local_bb1_coalesce_counter_push54_next_coalesce_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_inputs_ready;
reg local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_stall_in;
wire local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_output_regs_ready;
wire [7:0] local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_result;
wire local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_fu_valid_out;
wire local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_fu_stall_out;
reg [7:0] local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_NO_SHIFT_REG;
wire local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_causedstall;
acl_push local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_10_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1919_0_coalesced_pop3_),
.stall_out(local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_result),
.feedback_out(feedback_data_out_19),
.feedback_valid_out(feedback_valid_out_19),
.feedback_stall_in(feedback_stall_in_19)
);
defparam local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_feedback.STALLFREE = 1;
defparam local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_inputs_ready = 1'b1;
assign local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_output_regs_ready = 1'b1;
assign local_bb1_rows_1919_0_coalesced_pop3__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_10_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_NO_SHIFT_REG <= 'x;
local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_output_regs_ready)
begin
local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_NO_SHIFT_REG <= local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_result;
local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_stall_in))
begin
local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_cmp16_121_0_valid_out_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_stall_in_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_valid_out_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_stall_in_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_1_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_valid_out_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_stall_in_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_cmp16_121_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_cmp16_121_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_cmp16_121_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_cmp16_121_0_stall_in_0_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_cmp16_121_0_valid_out_0_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_cmp16_121_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_121),
.data_out(rnode_165to166_bb1_cmp16_121_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_cmp16_121_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_cmp16_121_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_cmp16_121_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_cmp16_121_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_cmp16_121_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_121_stall_in = 1'b0;
assign rnode_165to166_bb1_cmp16_121_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_121_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_121_0_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_121_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_cmp16_121_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_cmp16_121_1_NO_SHIFT_REG = rnode_165to166_bb1_cmp16_121_0_reg_166_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_rows_1927_0_push12_rows_1926_0_pop13_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1927_0_push12_rows_1926_0_pop13_stall_in = 1'b0;
assign rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG = rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_7_1_stall_local;
wire local_bb1_not_cmp16_7_1;
assign local_bb1_not_cmp16_7_1 = (local_bb1_cmp16_7_1 ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1926_0_push13_rows_1925_0_pop14_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1926_0_push13_rows_1925_0_pop14_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_6_1_stall_local;
wire local_bb1_not_cmp16_6_1;
assign local_bb1_not_cmp16_6_1 = (rnode_166to167_bb1_cmp16_6_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1925_0_push14_rows_1924_0_pop15_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1925_0_push14_rows_1924_0_pop15_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_5_1_stall_local;
wire local_bb1_not_cmp16_5_1;
assign local_bb1_not_cmp16_5_1 = (rnode_166to167_bb1_cmp16_5_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1924_0_push15_rows_1923_0_pop16_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1924_0_push15_rows_1923_0_pop16_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_4_1_stall_local;
wire local_bb1_not_cmp16_4_1;
assign local_bb1_not_cmp16_4_1 = (rnode_166to167_bb1_cmp16_4_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1923_0_push16_rows_1922_0_pop17_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1923_0_push16_rows_1922_0_pop17_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_3_1_stall_local;
wire local_bb1_not_cmp16_3_1;
assign local_bb1_not_cmp16_3_1 = (rnode_166to167_bb1_cmp16_3_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_rows_1922_0_push17_rows_1921_0_pop18_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1922_0_push17_rows_1921_0_pop18_stall_in = 1'b0;
assign rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG = rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_2_1_stall_local;
wire local_bb1_not_cmp16_2_1;
assign local_bb1_not_cmp16_2_1 = (rnode_166to167_bb1_cmp16_2_1_1_NO_SHIFT_REG ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1_rows_1930_0_push9_rows_1929_0_pop10_inputs_ready;
reg local_bb1_rows_1930_0_push9_rows_1929_0_pop10_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1930_0_push9_rows_1929_0_pop10_stall_in;
wire local_bb1_rows_1930_0_push9_rows_1929_0_pop10_output_regs_ready;
wire [7:0] local_bb1_rows_1930_0_push9_rows_1929_0_pop10_result;
wire local_bb1_rows_1930_0_push9_rows_1929_0_pop10_fu_valid_out;
wire local_bb1_rows_1930_0_push9_rows_1929_0_pop10_fu_stall_out;
reg [7:0] local_bb1_rows_1930_0_push9_rows_1929_0_pop10_NO_SHIFT_REG;
wire local_bb1_rows_1930_0_push9_rows_1929_0_pop10_causedstall;
acl_push local_bb1_rows_1930_0_push9_rows_1929_0_pop10_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene2_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1929_0_pop10_),
.stall_out(local_bb1_rows_1930_0_push9_rows_1929_0_pop10_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1930_0_push9_rows_1929_0_pop10_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1930_0_push9_rows_1929_0_pop10_result),
.feedback_out(feedback_data_out_9),
.feedback_valid_out(feedback_valid_out_9),
.feedback_stall_in(feedback_stall_in_9)
);
defparam local_bb1_rows_1930_0_push9_rows_1929_0_pop10_feedback.STALLFREE = 1;
defparam local_bb1_rows_1930_0_push9_rows_1929_0_pop10_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1930_0_push9_rows_1929_0_pop10_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1930_0_push9_rows_1929_0_pop10_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1930_0_push9_rows_1929_0_pop10_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1930_0_push9_rows_1929_0_pop10_inputs_ready = 1'b1;
assign local_bb1_rows_1930_0_push9_rows_1929_0_pop10_output_regs_ready = 1'b1;
assign local_bb1_rows_1929_0_pop10__stall_in_0 = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1930_0_push9_rows_1929_0_pop10_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[5] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1930_0_push9_rows_1929_0_pop10_NO_SHIFT_REG <= 'x;
local_bb1_rows_1930_0_push9_rows_1929_0_pop10_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1930_0_push9_rows_1929_0_pop10_output_regs_ready)
begin
local_bb1_rows_1930_0_push9_rows_1929_0_pop10_NO_SHIFT_REG <= local_bb1_rows_1930_0_push9_rows_1929_0_pop10_result;
local_bb1_rows_1930_0_push9_rows_1929_0_pop10_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1930_0_push9_rows_1929_0_pop10_stall_in))
begin
local_bb1_rows_1930_0_push9_rows_1929_0_pop10_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_cmp16_10_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_10_1_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_cmp16_10_1_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_cmp16_10_1_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_cmp16_10_1_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_cmp16_10_1_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_cmp16_10_1_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_10_1),
.data_out(rnode_167to168_bb1_cmp16_10_1_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_cmp16_10_1_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_cmp16_10_1_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_cmp16_10_1_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_cmp16_10_1_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_cmp16_10_1_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_10_1_stall_in = 1'b0;
assign rnode_167to168_bb1_cmp16_10_1_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_10_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_10_1_0_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_10_1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_cmp16_10_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_10_1_1_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_10_1_0_reg_168_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1932_0_push7_rows_1931_0_pop8_inputs_ready;
reg local_bb1_rows_1932_0_push7_rows_1931_0_pop8_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1932_0_push7_rows_1931_0_pop8_stall_in;
wire local_bb1_rows_1932_0_push7_rows_1931_0_pop8_output_regs_ready;
wire [7:0] local_bb1_rows_1932_0_push7_rows_1931_0_pop8_result;
wire local_bb1_rows_1932_0_push7_rows_1931_0_pop8_fu_valid_out;
wire local_bb1_rows_1932_0_push7_rows_1931_0_pop8_fu_stall_out;
reg [7:0] local_bb1_rows_1932_0_push7_rows_1931_0_pop8_NO_SHIFT_REG;
wire local_bb1_rows_1932_0_push7_rows_1931_0_pop8_causedstall;
acl_push local_bb1_rows_1932_0_push7_rows_1931_0_pop8_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene2_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1931_0_pop8_),
.stall_out(local_bb1_rows_1932_0_push7_rows_1931_0_pop8_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1932_0_push7_rows_1931_0_pop8_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1932_0_push7_rows_1931_0_pop8_result),
.feedback_out(feedback_data_out_7),
.feedback_valid_out(feedback_valid_out_7),
.feedback_stall_in(feedback_stall_in_7)
);
defparam local_bb1_rows_1932_0_push7_rows_1931_0_pop8_feedback.STALLFREE = 1;
defparam local_bb1_rows_1932_0_push7_rows_1931_0_pop8_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1932_0_push7_rows_1931_0_pop8_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1932_0_push7_rows_1931_0_pop8_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1932_0_push7_rows_1931_0_pop8_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1932_0_push7_rows_1931_0_pop8_inputs_ready = 1'b1;
assign local_bb1_rows_1932_0_push7_rows_1931_0_pop8_output_regs_ready = 1'b1;
assign local_bb1_rows_1931_0_pop8__stall_in_0 = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1932_0_push7_rows_1931_0_pop8_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[5] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1932_0_push7_rows_1931_0_pop8_NO_SHIFT_REG <= 'x;
local_bb1_rows_1932_0_push7_rows_1931_0_pop8_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1932_0_push7_rows_1931_0_pop8_output_regs_ready)
begin
local_bb1_rows_1932_0_push7_rows_1931_0_pop8_NO_SHIFT_REG <= local_bb1_rows_1932_0_push7_rows_1931_0_pop8_result;
local_bb1_rows_1932_0_push7_rows_1931_0_pop8_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1932_0_push7_rows_1931_0_pop8_stall_in))
begin
local_bb1_rows_1932_0_push7_rows_1931_0_pop8_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_cmp16_12_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_12_1_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_cmp16_12_1_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_cmp16_12_1_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_cmp16_12_1_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_cmp16_12_1_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_cmp16_12_1_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_12_1),
.data_out(rnode_167to168_bb1_cmp16_12_1_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_cmp16_12_1_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_cmp16_12_1_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_cmp16_12_1_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_cmp16_12_1_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_cmp16_12_1_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_12_1_stall_in = 1'b0;
assign rnode_167to168_bb1_cmp16_12_1_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_12_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_12_1_0_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_12_1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_cmp16_12_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_12_1_1_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_12_1_0_reg_168_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1_rows_1933_0_push6_rows_1932_0_pop7_inputs_ready;
reg local_bb1_rows_1933_0_push6_rows_1932_0_pop7_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1933_0_push6_rows_1932_0_pop7_stall_in;
wire local_bb1_rows_1933_0_push6_rows_1932_0_pop7_output_regs_ready;
wire [7:0] local_bb1_rows_1933_0_push6_rows_1932_0_pop7_result;
wire local_bb1_rows_1933_0_push6_rows_1932_0_pop7_fu_valid_out;
wire local_bb1_rows_1933_0_push6_rows_1932_0_pop7_fu_stall_out;
reg [7:0] local_bb1_rows_1933_0_push6_rows_1932_0_pop7_NO_SHIFT_REG;
wire local_bb1_rows_1933_0_push6_rows_1932_0_pop7_causedstall;
acl_push local_bb1_rows_1933_0_push6_rows_1932_0_pop7_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_167to168_bb1_rows_1932_0_pop7__0_NO_SHIFT_REG),
.stall_out(local_bb1_rows_1933_0_push6_rows_1932_0_pop7_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1_rows_1933_0_push6_rows_1932_0_pop7_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1933_0_push6_rows_1932_0_pop7_result),
.feedback_out(feedback_data_out_6),
.feedback_valid_out(feedback_valid_out_6),
.feedback_stall_in(feedback_stall_in_6)
);
defparam local_bb1_rows_1933_0_push6_rows_1932_0_pop7_feedback.STALLFREE = 1;
defparam local_bb1_rows_1933_0_push6_rows_1932_0_pop7_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1933_0_push6_rows_1932_0_pop7_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1933_0_push6_rows_1932_0_pop7_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1933_0_push6_rows_1932_0_pop7_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1933_0_push6_rows_1932_0_pop7_inputs_ready = 1'b1;
assign local_bb1_rows_1933_0_push6_rows_1932_0_pop7_output_regs_ready = 1'b1;
assign rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1933_0_push6_rows_1932_0_pop7_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1933_0_push6_rows_1932_0_pop7_NO_SHIFT_REG <= 'x;
local_bb1_rows_1933_0_push6_rows_1932_0_pop7_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1933_0_push6_rows_1932_0_pop7_output_regs_ready)
begin
local_bb1_rows_1933_0_push6_rows_1932_0_pop7_NO_SHIFT_REG <= local_bb1_rows_1933_0_push6_rows_1932_0_pop7_result;
local_bb1_rows_1933_0_push6_rows_1932_0_pop7_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1933_0_push6_rows_1932_0_pop7_stall_in))
begin
local_bb1_rows_1933_0_push6_rows_1932_0_pop7_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_13_1_stall_local;
wire local_bb1_cmp16_13_1;
assign local_bb1_cmp16_13_1 = (rnode_167to168_bb1_rows_1932_0_pop7__1_NO_SHIFT_REG == 8'h0);
// This section implements a registered operation.
//
wire local_bb1_rows_1931_0_push8_rows_1930_0_pop9_inputs_ready;
reg local_bb1_rows_1931_0_push8_rows_1930_0_pop9_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1931_0_push8_rows_1930_0_pop9_stall_in;
wire local_bb1_rows_1931_0_push8_rows_1930_0_pop9_output_regs_ready;
wire [7:0] local_bb1_rows_1931_0_push8_rows_1930_0_pop9_result;
wire local_bb1_rows_1931_0_push8_rows_1930_0_pop9_fu_valid_out;
wire local_bb1_rows_1931_0_push8_rows_1930_0_pop9_fu_stall_out;
reg [7:0] local_bb1_rows_1931_0_push8_rows_1930_0_pop9_NO_SHIFT_REG;
wire local_bb1_rows_1931_0_push8_rows_1930_0_pop9_causedstall;
acl_push local_bb1_rows_1931_0_push8_rows_1930_0_pop9_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene2_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1930_0_pop9_),
.stall_out(local_bb1_rows_1931_0_push8_rows_1930_0_pop9_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1931_0_push8_rows_1930_0_pop9_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1931_0_push8_rows_1930_0_pop9_result),
.feedback_out(feedback_data_out_8),
.feedback_valid_out(feedback_valid_out_8),
.feedback_stall_in(feedback_stall_in_8)
);
defparam local_bb1_rows_1931_0_push8_rows_1930_0_pop9_feedback.STALLFREE = 1;
defparam local_bb1_rows_1931_0_push8_rows_1930_0_pop9_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1931_0_push8_rows_1930_0_pop9_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1931_0_push8_rows_1930_0_pop9_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1931_0_push8_rows_1930_0_pop9_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1931_0_push8_rows_1930_0_pop9_inputs_ready = 1'b1;
assign local_bb1_rows_1931_0_push8_rows_1930_0_pop9_output_regs_ready = 1'b1;
assign local_bb1_rows_1930_0_pop9__stall_in_0 = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1931_0_push8_rows_1930_0_pop9_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[5] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1931_0_push8_rows_1930_0_pop9_NO_SHIFT_REG <= 'x;
local_bb1_rows_1931_0_push8_rows_1930_0_pop9_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1931_0_push8_rows_1930_0_pop9_output_regs_ready)
begin
local_bb1_rows_1931_0_push8_rows_1930_0_pop9_NO_SHIFT_REG <= local_bb1_rows_1931_0_push8_rows_1930_0_pop9_result;
local_bb1_rows_1931_0_push8_rows_1930_0_pop9_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1931_0_push8_rows_1930_0_pop9_stall_in))
begin
local_bb1_rows_1931_0_push8_rows_1930_0_pop9_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_cmp16_11_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_11_1_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_cmp16_11_1_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_cmp16_11_1_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_cmp16_11_1_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_cmp16_11_1_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_cmp16_11_1_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_11_1),
.data_out(rnode_167to168_bb1_cmp16_11_1_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_cmp16_11_1_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_cmp16_11_1_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_cmp16_11_1_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_cmp16_11_1_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_cmp16_11_1_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_11_1_stall_in = 1'b0;
assign rnode_167to168_bb1_cmp16_11_1_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_11_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_11_1_0_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_11_1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_cmp16_11_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_11_1_1_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_11_1_0_reg_168_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_8_1_stall_local;
wire local_bb1_not_cmp16_8_1;
assign local_bb1_not_cmp16_8_1 = (local_bb1_cmp16_8_1 ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1_rows_1929_0_push10_rows_1928_0_pop11_inputs_ready;
reg local_bb1_rows_1929_0_push10_rows_1928_0_pop11_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1929_0_push10_rows_1928_0_pop11_stall_in;
wire local_bb1_rows_1929_0_push10_rows_1928_0_pop11_output_regs_ready;
wire [7:0] local_bb1_rows_1929_0_push10_rows_1928_0_pop11_result;
wire local_bb1_rows_1929_0_push10_rows_1928_0_pop11_fu_valid_out;
wire local_bb1_rows_1929_0_push10_rows_1928_0_pop11_fu_stall_out;
reg [7:0] local_bb1_rows_1929_0_push10_rows_1928_0_pop11_NO_SHIFT_REG;
wire local_bb1_rows_1929_0_push10_rows_1928_0_pop11_causedstall;
acl_push local_bb1_rows_1929_0_push10_rows_1928_0_pop11_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene2_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1928_0_pop11_),
.stall_out(local_bb1_rows_1929_0_push10_rows_1928_0_pop11_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1929_0_push10_rows_1928_0_pop11_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1929_0_push10_rows_1928_0_pop11_result),
.feedback_out(feedback_data_out_10),
.feedback_valid_out(feedback_valid_out_10),
.feedback_stall_in(feedback_stall_in_10)
);
defparam local_bb1_rows_1929_0_push10_rows_1928_0_pop11_feedback.STALLFREE = 1;
defparam local_bb1_rows_1929_0_push10_rows_1928_0_pop11_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1929_0_push10_rows_1928_0_pop11_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1929_0_push10_rows_1928_0_pop11_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1929_0_push10_rows_1928_0_pop11_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1929_0_push10_rows_1928_0_pop11_inputs_ready = 1'b1;
assign local_bb1_rows_1929_0_push10_rows_1928_0_pop11_output_regs_ready = 1'b1;
assign local_bb1_rows_1928_0_pop11__stall_in_0 = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1929_0_push10_rows_1928_0_pop11_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[5] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1929_0_push10_rows_1928_0_pop11_NO_SHIFT_REG <= 'x;
local_bb1_rows_1929_0_push10_rows_1928_0_pop11_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1929_0_push10_rows_1928_0_pop11_output_regs_ready)
begin
local_bb1_rows_1929_0_push10_rows_1928_0_pop11_NO_SHIFT_REG <= local_bb1_rows_1929_0_push10_rows_1928_0_pop11_result;
local_bb1_rows_1929_0_push10_rows_1928_0_pop11_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1929_0_push10_rows_1928_0_pop11_stall_in))
begin
local_bb1_rows_1929_0_push10_rows_1928_0_pop11_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_cmp16_9_1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_1_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_cmp16_9_1_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_cmp16_9_1_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_cmp16_9_1_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_cmp16_9_1_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_cmp16_9_1_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_cmp16_9_1_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_9_1),
.data_out(rnode_167to168_bb1_cmp16_9_1_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_cmp16_9_1_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_cmp16_9_1_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_cmp16_9_1_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_cmp16_9_1_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_cmp16_9_1_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_9_1_stall_in = 1'b0;
assign rnode_167to168_bb1_cmp16_9_1_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_9_1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_9_1_0_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_9_1_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_cmp16_9_1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_cmp16_9_1_1_NO_SHIFT_REG = rnode_167to168_bb1_cmp16_9_1_0_reg_168_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1__pop40__valid_out_0;
wire local_bb1__pop40__stall_in_0;
reg local_bb1__pop40__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_5_2_valid_out;
wire local_bb1_cmp16_5_2_stall_in;
reg local_bb1_cmp16_5_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_5_2_inputs_ready;
wire local_bb1_cmp16_5_2_stall_local;
wire local_bb1_cmp16_5_2;
assign local_bb1_cmp16_5_2_inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_cmp16_5_2 = (local_bb1__pop40_ == 8'h0);
assign local_bb1__pop40__valid_out_0 = 1'b1;
assign local_bb1_cmp16_5_2_valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop40__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_5_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop40__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_5_2_inputs_ready & (local_bb1__pop40__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop40__stall_in_0)) & local_bb1_cmp16_5_2_stall_local);
local_bb1_cmp16_5_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_5_2_inputs_ready & (local_bb1_cmp16_5_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_5_2_stall_in)) & local_bb1_cmp16_5_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop41__valid_out_0;
wire local_bb1__pop41__stall_in_0;
reg local_bb1__pop41__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_6_2_valid_out;
wire local_bb1_cmp16_6_2_stall_in;
reg local_bb1_cmp16_6_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_6_2_inputs_ready;
wire local_bb1_cmp16_6_2_stall_local;
wire local_bb1_cmp16_6_2;
assign local_bb1_cmp16_6_2_inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_cmp16_6_2 = (local_bb1__pop41_ == 8'h0);
assign local_bb1__pop41__valid_out_0 = 1'b1;
assign local_bb1_cmp16_6_2_valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop41__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_6_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop41__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_6_2_inputs_ready & (local_bb1__pop41__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop41__stall_in_0)) & local_bb1_cmp16_6_2_stall_local);
local_bb1_cmp16_6_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_6_2_inputs_ready & (local_bb1_cmp16_6_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_6_2_stall_in)) & local_bb1_cmp16_6_2_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1__pop42__0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__pop42__0_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__pop42__1_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__pop42__0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop42__0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1__pop42__0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1__pop42__0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1__pop42__0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1__pop42__0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1__pop42__0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1__pop42_),
.data_out(rnode_168to169_bb1__pop42__0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1__pop42__0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1__pop42__0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1__pop42__0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1__pop42__0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1__pop42__0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__pop42__stall_in = 1'b0;
assign rnode_168to169_bb1__pop42__0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__pop42__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1__pop42__0_NO_SHIFT_REG = rnode_168to169_bb1__pop42__0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1__pop42__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1__pop42__1_NO_SHIFT_REG = rnode_168to169_bb1__pop42__0_reg_169_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1__pop36__0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__pop36__0_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__pop36__1_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__pop36__0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__pop36__0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1__pop36__0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1__pop36__0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1__pop36__0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1__pop36__0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1__pop36__0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1__pop36_),
.data_out(rnode_168to169_bb1__pop36__0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1__pop36__0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1__pop36__0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1__pop36__0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1__pop36__0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1__pop36__0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__pop36__stall_in = 1'b0;
assign rnode_168to169_bb1__pop36__0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__pop36__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1__pop36__0_NO_SHIFT_REG = rnode_168to169_bb1__pop36__0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1__pop36__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1__pop36__1_NO_SHIFT_REG = rnode_168to169_bb1__pop36__0_reg_169_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1__pop37__valid_out_0;
wire local_bb1__pop37__stall_in_0;
reg local_bb1__pop37__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_2_2_valid_out;
wire local_bb1_cmp16_2_2_stall_in;
reg local_bb1_cmp16_2_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_2_2_inputs_ready;
wire local_bb1_cmp16_2_2_stall_local;
wire local_bb1_cmp16_2_2;
assign local_bb1_cmp16_2_2_inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
assign local_bb1_cmp16_2_2 = (local_bb1__pop37_ == 8'h0);
assign local_bb1__pop37__valid_out_0 = 1'b1;
assign local_bb1_cmp16_2_2_valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop37__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_2_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop37__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_2_2_inputs_ready & (local_bb1__pop37__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop37__stall_in_0)) & local_bb1_cmp16_2_2_stall_local);
local_bb1_cmp16_2_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_2_2_inputs_ready & (local_bb1_cmp16_2_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_2_2_stall_in)) & local_bb1_cmp16_2_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop38__valid_out_0;
wire local_bb1__pop38__stall_in_0;
reg local_bb1__pop38__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_3_2_valid_out;
wire local_bb1_cmp16_3_2_stall_in;
reg local_bb1_cmp16_3_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_3_2_inputs_ready;
wire local_bb1_cmp16_3_2_stall_local;
wire local_bb1_cmp16_3_2;
assign local_bb1_cmp16_3_2_inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
assign local_bb1_cmp16_3_2 = (local_bb1__pop38_ == 8'h0);
assign local_bb1__pop38__valid_out_0 = 1'b1;
assign local_bb1_cmp16_3_2_valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop38__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_3_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop38__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_3_2_inputs_ready & (local_bb1__pop38__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop38__stall_in_0)) & local_bb1_cmp16_3_2_stall_local);
local_bb1_cmp16_3_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_3_2_inputs_ready & (local_bb1_cmp16_3_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_3_2_stall_in)) & local_bb1_cmp16_3_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop39__valid_out_0;
wire local_bb1__pop39__stall_in_0;
reg local_bb1__pop39__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_4_2_valid_out;
wire local_bb1_cmp16_4_2_stall_in;
reg local_bb1_cmp16_4_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_4_2_inputs_ready;
wire local_bb1_cmp16_4_2_stall_local;
wire local_bb1_cmp16_4_2;
assign local_bb1_cmp16_4_2_inputs_ready = rnode_167to168_bb1_c0_ene1_0_valid_out_6_NO_SHIFT_REG;
assign local_bb1_cmp16_4_2 = (local_bb1__pop39_ == 8'h0);
assign local_bb1__pop39__valid_out_0 = 1'b1;
assign local_bb1_cmp16_4_2_valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop39__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_4_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop39__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_4_2_inputs_ready & (local_bb1__pop39__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop39__stall_in_0)) & local_bb1_cmp16_4_2_stall_local);
local_bb1_cmp16_4_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_4_2_inputs_ready & (local_bb1_cmp16_4_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_4_2_stall_in)) & local_bb1_cmp16_4_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_14_1_stall_local;
wire local_bb1_cmp16_14_1;
assign local_bb1_cmp16_14_1 = (local_bb1_rows_1933_0_pop6_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_15_1_stall_local;
wire local_bb1_cmp16_15_1;
assign local_bb1_cmp16_15_1 = (local_bb1_rows_1934_0_pop5_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_16_1_stall_local;
wire local_bb1_cmp16_16_1;
assign local_bb1_cmp16_16_1 = (local_bb1_rows_1935_0_pop4_ == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__pop48__valid_out;
wire local_bb1__pop48__stall_in;
wire local_bb1__pop48__inputs_ready;
wire local_bb1__pop48__stall_local;
wire [7:0] local_bb1__pop48_;
wire local_bb1__pop48__fu_valid_out;
wire local_bb1__pop48__fu_stall_out;
acl_pop local_bb1__pop48__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene1_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop48__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__pop48__fu_valid_out),
.stall_in(local_bb1__pop48__stall_local),
.data_out(local_bb1__pop48_),
.feedback_in(feedback_data_in_48),
.feedback_valid_in(feedback_valid_in_48),
.feedback_stall_out(feedback_stall_out_48)
);
defparam local_bb1__pop48__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop48__feedback.STYLE = "REGULAR";
assign local_bb1__pop48__inputs_ready = rnode_168to169_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1__pop48__stall_local = 1'b0;
assign local_bb1__pop48__valid_out = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop43__stall_local;
wire [7:0] local_bb1__pop43_;
wire local_bb1__pop43__fu_valid_out;
wire local_bb1__pop43__fu_stall_out;
acl_pop local_bb1__pop43__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene1_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop43__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__pop43__fu_valid_out),
.stall_in(local_bb1__pop43__stall_local),
.data_out(local_bb1__pop43_),
.feedback_in(feedback_data_in_43),
.feedback_valid_in(feedback_valid_in_43),
.feedback_stall_out(feedback_stall_out_43)
);
defparam local_bb1__pop43__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop43__feedback.STYLE = "REGULAR";
assign local_bb1__pop43__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop44__stall_local;
wire [7:0] local_bb1__pop44_;
wire local_bb1__pop44__fu_valid_out;
wire local_bb1__pop44__fu_stall_out;
acl_pop local_bb1__pop44__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene1_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop44__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__pop44__fu_valid_out),
.stall_in(local_bb1__pop44__stall_local),
.data_out(local_bb1__pop44_),
.feedback_in(feedback_data_in_44),
.feedback_valid_in(feedback_valid_in_44),
.feedback_stall_out(feedback_stall_out_44)
);
defparam local_bb1__pop44__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop44__feedback.STYLE = "REGULAR";
assign local_bb1__pop44__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop46__stall_local;
wire [7:0] local_bb1__pop46_;
wire local_bb1__pop46__fu_valid_out;
wire local_bb1__pop46__fu_stall_out;
acl_pop local_bb1__pop46__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene1_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop46__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__pop46__fu_valid_out),
.stall_in(local_bb1__pop46__stall_local),
.data_out(local_bb1__pop46_),
.feedback_in(feedback_data_in_46),
.feedback_valid_in(feedback_valid_in_46),
.feedback_stall_out(feedback_stall_out_46)
);
defparam local_bb1__pop46__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop46__feedback.STYLE = "REGULAR";
assign local_bb1__pop46__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop47__stall_local;
wire [7:0] local_bb1__pop47_;
wire local_bb1__pop47__fu_valid_out;
wire local_bb1__pop47__fu_stall_out;
acl_pop local_bb1__pop47__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene1_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop47__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__pop47__fu_valid_out),
.stall_in(local_bb1__pop47__stall_local),
.data_out(local_bb1__pop47_),
.feedback_in(feedback_data_in_47),
.feedback_valid_in(feedback_valid_in_47),
.feedback_stall_out(feedback_stall_out_47)
);
defparam local_bb1__pop47__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop47__feedback.STYLE = "REGULAR";
assign local_bb1__pop47__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop45__stall_local;
wire [7:0] local_bb1__pop45_;
wire local_bb1__pop45__fu_valid_out;
wire local_bb1__pop45__fu_stall_out;
acl_pop local_bb1__pop45__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene1_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop45__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__pop45__fu_valid_out),
.stall_in(local_bb1__pop45__stall_local),
.data_out(local_bb1__pop45_),
.feedback_in(feedback_data_in_45),
.feedback_valid_in(feedback_valid_in_45),
.feedback_stall_out(feedback_stall_out_45)
);
defparam local_bb1__pop45__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop45__feedback.STYLE = "REGULAR";
assign local_bb1__pop45__stall_local = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_2_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene1_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_c0_ene1_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_c0_ene1_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_c0_ene1_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_c0_ene1_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_c0_ene1_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_c0_ene1_6_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_c0_ene1_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_c0_ene1_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_c0_ene1_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_c0_ene1_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_c0_ene1_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_c0_ene1_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_c0_ene1_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_c0_ene1_0_NO_SHIFT_REG = rnode_169to170_bb1_c0_ene1_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_c0_ene1_1_NO_SHIFT_REG = rnode_169to170_bb1_c0_ene1_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_c0_ene1_2_NO_SHIFT_REG = rnode_169to170_bb1_c0_ene1_0_reg_170_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_2_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_c0_ene2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_c0_ene2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_c0_ene2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_c0_ene2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_c0_ene2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_c0_ene2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_c0_ene2_7_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_c0_ene2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_c0_ene2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_c0_ene2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_c0_ene2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_c0_ene2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_c0_ene2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_c0_ene2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_c0_ene2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_c0_ene2_0_NO_SHIFT_REG = rnode_169to170_bb1_c0_ene2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_c0_ene2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_c0_ene2_1_NO_SHIFT_REG = rnode_169to170_bb1_c0_ene2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_c0_ene2_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_c0_ene2_2_NO_SHIFT_REG = rnode_169to170_bb1_c0_ene2_0_reg_170_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_2_stall_local;
wire local_bb1_cmp19_2;
assign local_bb1_cmp19_2 = (local_bb1__335 == 8'h0);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_not_select6_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_stall_in_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_not_select6_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_not_select6_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_not_select6_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_not_select6_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_not_select6_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_not_select6_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_not_select6_0_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_not_select6_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_not_select6_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_not_select6_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_not_select6_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_not_select6_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_not_select6_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_not_select6_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_not_select6_0_NO_SHIFT_REG = rnode_166to167_bb1_not_select6_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_not_select6_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_not_select6_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_NO_SHIFT_REG;
logic [11:0] rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [11:0] rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_coalesce_counter_push54_next_coalesce_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_fifo.DATA_WIDTH = 12;
defparam rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_coalesce_counter_push54_next_coalesce_stall_in = 1'b0;
assign rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG = rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_121_stall_local;
wire local_bb1_not_cmp16_121;
assign local_bb1_not_cmp16_121 = (rnode_165to166_bb1_cmp16_121_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG = rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG),
.data_out(rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_fifo.DEPTH = 2;
defparam rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG = rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_170_NO_SHIFT_REG;
assign rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_rows_1930_0_push9_rows_1929_0_pop10_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1930_0_push9_rows_1929_0_pop10_stall_in = 1'b0;
assign rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG = rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_10_1_stall_local;
wire local_bb1_not_cmp16_10_1;
assign local_bb1_not_cmp16_10_1 = (rnode_167to168_bb1_cmp16_10_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_rows_1932_0_push7_rows_1931_0_pop8_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1932_0_push7_rows_1931_0_pop8_stall_in = 1'b0;
assign rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG = rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_12_1_stall_local;
wire local_bb1_not_cmp16_12_1;
assign local_bb1_not_cmp16_12_1 = (rnode_167to168_bb1_cmp16_12_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_rows_1933_0_push6_rows_1932_0_pop7_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1933_0_push6_rows_1932_0_pop7_stall_in = 1'b0;
assign rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_NO_SHIFT_REG = rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_13_1_stall_local;
wire local_bb1_not_cmp16_13_1;
assign local_bb1_not_cmp16_13_1 = (local_bb1_cmp16_13_1 ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_rows_1931_0_push8_rows_1930_0_pop9_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1931_0_push8_rows_1930_0_pop9_stall_in = 1'b0;
assign rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG = rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_11_1_stall_local;
wire local_bb1_not_cmp16_11_1;
assign local_bb1_not_cmp16_11_1 = (rnode_167to168_bb1_cmp16_11_1_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_rows_1929_0_push10_rows_1928_0_pop11_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1929_0_push10_rows_1928_0_pop11_stall_in = 1'b0;
assign rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG = rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_9_1_stall_local;
wire local_bb1_not_cmp16_9_1;
assign local_bb1_not_cmp16_9_1 = (rnode_167to168_bb1_cmp16_9_1_1_NO_SHIFT_REG ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1__push41__pop40_inputs_ready;
reg local_bb1__push41__pop40_valid_out_NO_SHIFT_REG;
wire local_bb1__push41__pop40_stall_in;
wire local_bb1__push41__pop40_output_regs_ready;
wire [7:0] local_bb1__push41__pop40_result;
wire local_bb1__push41__pop40_fu_valid_out;
wire local_bb1__push41__pop40_fu_stall_out;
reg [7:0] local_bb1__push41__pop40_NO_SHIFT_REG;
wire local_bb1__push41__pop40_causedstall;
acl_push local_bb1__push41__pop40_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_6_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop40_),
.stall_out(local_bb1__push41__pop40_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__push41__pop40_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push41__pop40_result),
.feedback_out(feedback_data_out_41),
.feedback_valid_out(feedback_valid_out_41),
.feedback_stall_in(feedback_stall_in_41)
);
defparam local_bb1__push41__pop40_feedback.STALLFREE = 1;
defparam local_bb1__push41__pop40_feedback.DATA_WIDTH = 8;
defparam local_bb1__push41__pop40_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push41__pop40_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push41__pop40_feedback.STYLE = "REGULAR";
assign local_bb1__push41__pop40_inputs_ready = 1'b1;
assign local_bb1__push41__pop40_output_regs_ready = 1'b1;
assign local_bb1__pop40__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign local_bb1__push41__pop40_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push41__pop40_NO_SHIFT_REG <= 'x;
local_bb1__push41__pop40_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push41__pop40_output_regs_ready)
begin
local_bb1__push41__pop40_NO_SHIFT_REG <= local_bb1__push41__pop40_result;
local_bb1__push41__pop40_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push41__pop40_stall_in))
begin
local_bb1__push41__pop40_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_cmp16_5_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_5_2_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_cmp16_5_2_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_cmp16_5_2_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_cmp16_5_2_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_cmp16_5_2_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_cmp16_5_2_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_5_2),
.data_out(rnode_168to169_bb1_cmp16_5_2_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_cmp16_5_2_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_cmp16_5_2_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_cmp16_5_2_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_cmp16_5_2_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_cmp16_5_2_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_5_2_stall_in = 1'b0;
assign rnode_168to169_bb1_cmp16_5_2_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_5_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_5_2_0_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_5_2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_cmp16_5_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_5_2_1_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_5_2_0_reg_169_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push42__pop41_inputs_ready;
reg local_bb1__push42__pop41_valid_out_NO_SHIFT_REG;
wire local_bb1__push42__pop41_stall_in;
wire local_bb1__push42__pop41_output_regs_ready;
wire [7:0] local_bb1__push42__pop41_result;
wire local_bb1__push42__pop41_fu_valid_out;
wire local_bb1__push42__pop41_fu_stall_out;
reg [7:0] local_bb1__push42__pop41_NO_SHIFT_REG;
wire local_bb1__push42__pop41_causedstall;
acl_push local_bb1__push42__pop41_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_7_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop41_),
.stall_out(local_bb1__push42__pop41_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__push42__pop41_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push42__pop41_result),
.feedback_out(feedback_data_out_42),
.feedback_valid_out(feedback_valid_out_42),
.feedback_stall_in(feedback_stall_in_42)
);
defparam local_bb1__push42__pop41_feedback.STALLFREE = 1;
defparam local_bb1__push42__pop41_feedback.DATA_WIDTH = 8;
defparam local_bb1__push42__pop41_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push42__pop41_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push42__pop41_feedback.STYLE = "REGULAR";
assign local_bb1__push42__pop41_inputs_ready = 1'b1;
assign local_bb1__push42__pop41_output_regs_ready = 1'b1;
assign local_bb1__pop41__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_7_NO_SHIFT_REG = 1'b0;
assign local_bb1__push42__pop41_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push42__pop41_NO_SHIFT_REG <= 'x;
local_bb1__push42__pop41_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push42__pop41_output_regs_ready)
begin
local_bb1__push42__pop41_NO_SHIFT_REG <= local_bb1__push42__pop41_result;
local_bb1__push42__pop41_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push42__pop41_stall_in))
begin
local_bb1__push42__pop41_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_cmp16_6_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_6_2_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_cmp16_6_2_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_cmp16_6_2_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_cmp16_6_2_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_cmp16_6_2_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_cmp16_6_2_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_6_2),
.data_out(rnode_168to169_bb1_cmp16_6_2_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_cmp16_6_2_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_cmp16_6_2_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_cmp16_6_2_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_cmp16_6_2_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_cmp16_6_2_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_6_2_stall_in = 1'b0;
assign rnode_168to169_bb1_cmp16_6_2_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_6_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_6_2_0_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_6_2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_cmp16_6_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_6_2_1_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_6_2_0_reg_169_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push43__pop42_inputs_ready;
reg local_bb1__push43__pop42_valid_out_NO_SHIFT_REG;
wire local_bb1__push43__pop42_stall_in;
wire local_bb1__push43__pop42_output_regs_ready;
wire [7:0] local_bb1__push43__pop42_result;
wire local_bb1__push43__pop42_fu_valid_out;
wire local_bb1__push43__pop42_fu_stall_out;
reg [7:0] local_bb1__push43__pop42_NO_SHIFT_REG;
wire local_bb1__push43__pop42_causedstall;
acl_push local_bb1__push43__pop42_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_168to169_bb1__pop42__0_NO_SHIFT_REG),
.stall_out(local_bb1__push43__pop42_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push43__pop42_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push43__pop42_result),
.feedback_out(feedback_data_out_43),
.feedback_valid_out(feedback_valid_out_43),
.feedback_stall_in(feedback_stall_in_43)
);
defparam local_bb1__push43__pop42_feedback.STALLFREE = 1;
defparam local_bb1__push43__pop42_feedback.DATA_WIDTH = 8;
defparam local_bb1__push43__pop42_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push43__pop42_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push43__pop42_feedback.STYLE = "REGULAR";
assign local_bb1__push43__pop42_inputs_ready = 1'b1;
assign local_bb1__push43__pop42_output_regs_ready = 1'b1;
assign rnode_168to169_bb1__pop42__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1__push43__pop42_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push43__pop42_NO_SHIFT_REG <= 'x;
local_bb1__push43__pop42_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push43__pop42_output_regs_ready)
begin
local_bb1__push43__pop42_NO_SHIFT_REG <= local_bb1__push43__pop42_result;
local_bb1__push43__pop42_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push43__pop42_stall_in))
begin
local_bb1__push43__pop42_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_7_2_valid_out;
wire local_bb1_cmp16_7_2_stall_in;
wire local_bb1_cmp16_7_2_inputs_ready;
wire local_bb1_cmp16_7_2_stall_local;
wire local_bb1_cmp16_7_2;
assign local_bb1_cmp16_7_2_inputs_ready = rnode_168to169_bb1__pop42__0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_cmp16_7_2 = (rnode_168to169_bb1__pop42__1_NO_SHIFT_REG == 8'h0);
assign local_bb1_cmp16_7_2_valid_out = 1'b1;
assign rnode_168to169_bb1__pop42__0_stall_in_1_NO_SHIFT_REG = 1'b0;
// This section implements a registered operation.
//
wire local_bb1__push37__pop36_inputs_ready;
reg local_bb1__push37__pop36_valid_out_NO_SHIFT_REG;
wire local_bb1__push37__pop36_stall_in;
wire local_bb1__push37__pop36_output_regs_ready;
wire [7:0] local_bb1__push37__pop36_result;
wire local_bb1__push37__pop36_fu_valid_out;
wire local_bb1__push37__pop36_fu_stall_out;
reg [7:0] local_bb1__push37__pop36_NO_SHIFT_REG;
wire local_bb1__push37__pop36_causedstall;
acl_push local_bb1__push37__pop36_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_6_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_168to169_bb1__pop36__0_NO_SHIFT_REG),
.stall_out(local_bb1__push37__pop36_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push37__pop36_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push37__pop36_result),
.feedback_out(feedback_data_out_37),
.feedback_valid_out(feedback_valid_out_37),
.feedback_stall_in(feedback_stall_in_37)
);
defparam local_bb1__push37__pop36_feedback.STALLFREE = 1;
defparam local_bb1__push37__pop36_feedback.DATA_WIDTH = 8;
defparam local_bb1__push37__pop36_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push37__pop36_feedback.MIN_FIFO_LATENCY = 0;
defparam local_bb1__push37__pop36_feedback.STYLE = "REGULAR";
assign local_bb1__push37__pop36_inputs_ready = 1'b1;
assign local_bb1__push37__pop36_output_regs_ready = 1'b1;
assign rnode_168to169_bb1__pop36__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign local_bb1__push37__pop36_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push37__pop36_NO_SHIFT_REG <= 'x;
local_bb1__push37__pop36_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push37__pop36_output_regs_ready)
begin
local_bb1__push37__pop36_NO_SHIFT_REG <= local_bb1__push37__pop36_result;
local_bb1__push37__pop36_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push37__pop36_stall_in))
begin
local_bb1__push37__pop36_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_1_2_stall_local;
wire local_bb1_cmp16_1_2;
assign local_bb1_cmp16_1_2 = (rnode_168to169_bb1__pop36__1_NO_SHIFT_REG == 8'h0);
// This section implements a registered operation.
//
wire local_bb1__push38__pop37_inputs_ready;
reg local_bb1__push38__pop37_valid_out_NO_SHIFT_REG;
wire local_bb1__push38__pop37_stall_in;
wire local_bb1__push38__pop37_output_regs_ready;
wire [7:0] local_bb1__push38__pop37_result;
wire local_bb1__push38__pop37_fu_valid_out;
wire local_bb1__push38__pop37_fu_stall_out;
reg [7:0] local_bb1__push38__pop37_NO_SHIFT_REG;
wire local_bb1__push38__pop37_causedstall;
acl_push local_bb1__push38__pop37_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop37_),
.stall_out(local_bb1__push38__pop37_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__push38__pop37_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push38__pop37_result),
.feedback_out(feedback_data_out_38),
.feedback_valid_out(feedback_valid_out_38),
.feedback_stall_in(feedback_stall_in_38)
);
defparam local_bb1__push38__pop37_feedback.STALLFREE = 1;
defparam local_bb1__push38__pop37_feedback.DATA_WIDTH = 8;
defparam local_bb1__push38__pop37_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push38__pop37_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push38__pop37_feedback.STYLE = "REGULAR";
assign local_bb1__push38__pop37_inputs_ready = 1'b1;
assign local_bb1__push38__pop37_output_regs_ready = 1'b1;
assign local_bb1__pop37__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign local_bb1__push38__pop37_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push38__pop37_NO_SHIFT_REG <= 'x;
local_bb1__push38__pop37_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push38__pop37_output_regs_ready)
begin
local_bb1__push38__pop37_NO_SHIFT_REG <= local_bb1__push38__pop37_result;
local_bb1__push38__pop37_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push38__pop37_stall_in))
begin
local_bb1__push38__pop37_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_cmp16_2_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_2_2_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_cmp16_2_2_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_cmp16_2_2_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_cmp16_2_2_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_cmp16_2_2_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_cmp16_2_2_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_2_2),
.data_out(rnode_168to169_bb1_cmp16_2_2_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_cmp16_2_2_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_cmp16_2_2_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_cmp16_2_2_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_cmp16_2_2_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_cmp16_2_2_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_2_2_stall_in = 1'b0;
assign rnode_168to169_bb1_cmp16_2_2_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_2_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_2_2_0_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_2_2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_cmp16_2_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_2_2_1_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_2_2_0_reg_169_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push39__pop38_inputs_ready;
reg local_bb1__push39__pop38_valid_out_NO_SHIFT_REG;
wire local_bb1__push39__pop38_stall_in;
wire local_bb1__push39__pop38_output_regs_ready;
wire [7:0] local_bb1__push39__pop38_result;
wire local_bb1__push39__pop38_fu_valid_out;
wire local_bb1__push39__pop38_fu_stall_out;
reg [7:0] local_bb1__push39__pop38_NO_SHIFT_REG;
wire local_bb1__push39__pop38_causedstall;
acl_push local_bb1__push39__pop38_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop38_),
.stall_out(local_bb1__push39__pop38_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__push39__pop38_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push39__pop38_result),
.feedback_out(feedback_data_out_39),
.feedback_valid_out(feedback_valid_out_39),
.feedback_stall_in(feedback_stall_in_39)
);
defparam local_bb1__push39__pop38_feedback.STALLFREE = 1;
defparam local_bb1__push39__pop38_feedback.DATA_WIDTH = 8;
defparam local_bb1__push39__pop38_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push39__pop38_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push39__pop38_feedback.STYLE = "REGULAR";
assign local_bb1__push39__pop38_inputs_ready = 1'b1;
assign local_bb1__push39__pop38_output_regs_ready = 1'b1;
assign local_bb1__pop38__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1__push39__pop38_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push39__pop38_NO_SHIFT_REG <= 'x;
local_bb1__push39__pop38_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push39__pop38_output_regs_ready)
begin
local_bb1__push39__pop38_NO_SHIFT_REG <= local_bb1__push39__pop38_result;
local_bb1__push39__pop38_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push39__pop38_stall_in))
begin
local_bb1__push39__pop38_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_cmp16_3_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_3_2_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_cmp16_3_2_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_cmp16_3_2_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_cmp16_3_2_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_cmp16_3_2_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_cmp16_3_2_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_3_2),
.data_out(rnode_168to169_bb1_cmp16_3_2_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_cmp16_3_2_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_cmp16_3_2_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_cmp16_3_2_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_cmp16_3_2_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_cmp16_3_2_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_3_2_stall_in = 1'b0;
assign rnode_168to169_bb1_cmp16_3_2_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_3_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_3_2_0_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_3_2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_cmp16_3_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_3_2_1_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_3_2_0_reg_169_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push40__pop39_inputs_ready;
reg local_bb1__push40__pop39_valid_out_NO_SHIFT_REG;
wire local_bb1__push40__pop39_stall_in;
wire local_bb1__push40__pop39_output_regs_ready;
wire [7:0] local_bb1__push40__pop39_result;
wire local_bb1__push40__pop39_fu_valid_out;
wire local_bb1__push40__pop39_fu_stall_out;
reg [7:0] local_bb1__push40__pop39_NO_SHIFT_REG;
wire local_bb1__push40__pop39_causedstall;
acl_push local_bb1__push40__pop39_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop39_),
.stall_out(local_bb1__push40__pop39_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__push40__pop39_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push40__pop39_result),
.feedback_out(feedback_data_out_40),
.feedback_valid_out(feedback_valid_out_40),
.feedback_stall_in(feedback_stall_in_40)
);
defparam local_bb1__push40__pop39_feedback.STALLFREE = 1;
defparam local_bb1__push40__pop39_feedback.DATA_WIDTH = 8;
defparam local_bb1__push40__pop39_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push40__pop39_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push40__pop39_feedback.STYLE = "REGULAR";
assign local_bb1__push40__pop39_inputs_ready = 1'b1;
assign local_bb1__push40__pop39_output_regs_ready = 1'b1;
assign local_bb1__pop39__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1__push40__pop39_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push40__pop39_NO_SHIFT_REG <= 'x;
local_bb1__push40__pop39_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push40__pop39_output_regs_ready)
begin
local_bb1__push40__pop39_NO_SHIFT_REG <= local_bb1__push40__pop39_result;
local_bb1__push40__pop39_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push40__pop39_stall_in))
begin
local_bb1__push40__pop39_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_cmp16_4_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_4_2_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_cmp16_4_2_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_cmp16_4_2_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_cmp16_4_2_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_cmp16_4_2_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_cmp16_4_2_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_4_2),
.data_out(rnode_168to169_bb1_cmp16_4_2_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_cmp16_4_2_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_cmp16_4_2_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_cmp16_4_2_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_cmp16_4_2_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_cmp16_4_2_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_4_2_stall_in = 1'b0;
assign rnode_168to169_bb1_cmp16_4_2_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_4_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_4_2_0_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_4_2_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_cmp16_4_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_4_2_1_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_4_2_0_reg_169_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_14_1_stall_local;
wire local_bb1_not_cmp16_14_1;
assign local_bb1_not_cmp16_14_1 = (local_bb1_cmp16_14_1 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_15_1_stall_local;
wire local_bb1_not_cmp16_15_1;
assign local_bb1_not_cmp16_15_1 = (local_bb1_cmp16_15_1 ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_16_1_stall_local;
wire local_bb1_not_cmp16_16_1;
assign local_bb1_not_cmp16_16_1 = (local_bb1_cmp16_16_1 ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1__pop48__0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1__pop48__0_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1__pop48__1_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1__pop48__0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__pop48__0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1__pop48__0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1__pop48__0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1__pop48__0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1__pop48__0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1__pop48__0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1__pop48_),
.data_out(rnode_169to170_bb1__pop48__0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1__pop48__0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1__pop48__0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1__pop48__0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1__pop48__0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1__pop48__0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__pop48__stall_in = 1'b0;
assign rnode_169to170_bb1__pop48__0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1__pop48__0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1__pop48__0_NO_SHIFT_REG = rnode_169to170_bb1__pop48__0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1__pop48__0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1__pop48__1_NO_SHIFT_REG = rnode_169to170_bb1__pop48__0_reg_170_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1__pop43__valid_out_0;
wire local_bb1__pop43__stall_in_0;
reg local_bb1__pop43__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_8_2_valid_out;
wire local_bb1_cmp16_8_2_stall_in;
reg local_bb1_cmp16_8_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_8_2_inputs_ready;
wire local_bb1_cmp16_8_2_stall_local;
wire local_bb1_cmp16_8_2;
assign local_bb1_cmp16_8_2_inputs_ready = rnode_168to169_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_cmp16_8_2 = (local_bb1__pop43_ == 8'h0);
assign local_bb1__pop43__valid_out_0 = 1'b1;
assign local_bb1_cmp16_8_2_valid_out = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop43__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_8_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop43__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_8_2_inputs_ready & (local_bb1__pop43__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop43__stall_in_0)) & local_bb1_cmp16_8_2_stall_local);
local_bb1_cmp16_8_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_8_2_inputs_ready & (local_bb1_cmp16_8_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_8_2_stall_in)) & local_bb1_cmp16_8_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop44__valid_out_0;
wire local_bb1__pop44__stall_in_0;
reg local_bb1__pop44__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_9_2_valid_out;
wire local_bb1_cmp16_9_2_stall_in;
reg local_bb1_cmp16_9_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_9_2_inputs_ready;
wire local_bb1_cmp16_9_2_stall_local;
wire local_bb1_cmp16_9_2;
assign local_bb1_cmp16_9_2_inputs_ready = rnode_168to169_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1_cmp16_9_2 = (local_bb1__pop44_ == 8'h0);
assign local_bb1__pop44__valid_out_0 = 1'b1;
assign local_bb1_cmp16_9_2_valid_out = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop44__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_9_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop44__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_9_2_inputs_ready & (local_bb1__pop44__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop44__stall_in_0)) & local_bb1_cmp16_9_2_stall_local);
local_bb1_cmp16_9_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_9_2_inputs_ready & (local_bb1_cmp16_9_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_9_2_stall_in)) & local_bb1_cmp16_9_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop46__valid_out_0;
wire local_bb1__pop46__stall_in_0;
reg local_bb1__pop46__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_11_2_valid_out;
wire local_bb1_cmp16_11_2_stall_in;
reg local_bb1_cmp16_11_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_11_2_inputs_ready;
wire local_bb1_cmp16_11_2_stall_local;
wire local_bb1_cmp16_11_2;
assign local_bb1_cmp16_11_2_inputs_ready = rnode_168to169_bb1_c0_ene1_0_valid_out_3_NO_SHIFT_REG;
assign local_bb1_cmp16_11_2 = (local_bb1__pop46_ == 8'h0);
assign local_bb1__pop46__valid_out_0 = 1'b1;
assign local_bb1_cmp16_11_2_valid_out = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_3_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop46__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_11_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop46__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_11_2_inputs_ready & (local_bb1__pop46__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop46__stall_in_0)) & local_bb1_cmp16_11_2_stall_local);
local_bb1_cmp16_11_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_11_2_inputs_ready & (local_bb1_cmp16_11_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_11_2_stall_in)) & local_bb1_cmp16_11_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop47__valid_out_0;
wire local_bb1__pop47__stall_in_0;
reg local_bb1__pop47__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_12_2_valid_out;
wire local_bb1_cmp16_12_2_stall_in;
reg local_bb1_cmp16_12_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_12_2_inputs_ready;
wire local_bb1_cmp16_12_2_stall_local;
wire local_bb1_cmp16_12_2;
assign local_bb1_cmp16_12_2_inputs_ready = rnode_168to169_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG;
assign local_bb1_cmp16_12_2 = (local_bb1__pop47_ == 8'h0);
assign local_bb1__pop47__valid_out_0 = 1'b1;
assign local_bb1_cmp16_12_2_valid_out = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop47__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_12_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop47__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_12_2_inputs_ready & (local_bb1__pop47__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop47__stall_in_0)) & local_bb1_cmp16_12_2_stall_local);
local_bb1_cmp16_12_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_12_2_inputs_ready & (local_bb1_cmp16_12_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_12_2_stall_in)) & local_bb1_cmp16_12_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop45__valid_out_0;
wire local_bb1__pop45__stall_in_0;
reg local_bb1__pop45__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_10_2_valid_out;
wire local_bb1_cmp16_10_2_stall_in;
reg local_bb1_cmp16_10_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_10_2_inputs_ready;
wire local_bb1_cmp16_10_2_stall_local;
wire local_bb1_cmp16_10_2;
assign local_bb1_cmp16_10_2_inputs_ready = rnode_168to169_bb1_c0_ene1_0_valid_out_5_NO_SHIFT_REG;
assign local_bb1_cmp16_10_2 = (local_bb1__pop45_ == 8'h0);
assign local_bb1__pop45__valid_out_0 = 1'b1;
assign local_bb1_cmp16_10_2_valid_out = 1'b1;
assign rnode_168to169_bb1_c0_ene1_0_stall_in_5_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop45__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_10_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop45__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_10_2_inputs_ready & (local_bb1__pop45__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop45__stall_in_0)) & local_bb1_cmp16_10_2_stall_local);
local_bb1_cmp16_10_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_10_2_inputs_ready & (local_bb1_cmp16_10_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_10_2_stall_in)) & local_bb1_cmp16_10_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop49__stall_local;
wire [7:0] local_bb1__pop49_;
wire local_bb1__pop49__fu_valid_out;
wire local_bb1__pop49__fu_stall_out;
acl_pop local_bb1__pop49__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_169to170_bb1_c0_ene1_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop49__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[8]),
.valid_out(local_bb1__pop49__fu_valid_out),
.stall_in(local_bb1__pop49__stall_local),
.data_out(local_bb1__pop49_),
.feedback_in(feedback_data_in_49),
.feedback_valid_in(feedback_valid_in_49),
.feedback_stall_out(feedback_stall_out_49)
);
defparam local_bb1__pop49__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop49__feedback.STYLE = "REGULAR";
assign local_bb1__pop49__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop50__stall_local;
wire [7:0] local_bb1__pop50_;
wire local_bb1__pop50__fu_valid_out;
wire local_bb1__pop50__fu_stall_out;
acl_pop local_bb1__pop50__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_169to170_bb1_c0_ene1_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop50__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[8]),
.valid_out(local_bb1__pop50__fu_valid_out),
.stall_in(local_bb1__pop50__stall_local),
.data_out(local_bb1__pop50_),
.feedback_in(feedback_data_in_50),
.feedback_valid_in(feedback_valid_in_50),
.feedback_stall_out(feedback_stall_out_50)
);
defparam local_bb1__pop50__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop50__feedback.STYLE = "REGULAR";
assign local_bb1__pop50__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__pop51__stall_local;
wire [7:0] local_bb1__pop51_;
wire local_bb1__pop51__fu_valid_out;
wire local_bb1__pop51__fu_stall_out;
acl_pop local_bb1__pop51__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_169to170_bb1_c0_ene1_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__pop51__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[8]),
.valid_out(local_bb1__pop51__fu_valid_out),
.stall_in(local_bb1__pop51__stall_local),
.data_out(local_bb1__pop51_),
.feedback_in(feedback_data_in_51),
.feedback_valid_in(feedback_valid_in_51),
.feedback_stall_out(feedback_stall_out_51)
);
defparam local_bb1__pop51__feedback.DATA_WIDTH = 8;
defparam local_bb1__pop51__feedback.STYLE = "REGULAR";
assign local_bb1__pop51__stall_local = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__336_demorgan_stall_local;
wire local_bb1__336_demorgan;
assign local_bb1__336_demorgan = (local_bb1_cmp16_2 | local_bb1_cmp19_2);
// This section implements an unregistered operation.
//
wire local_bb1__338_stall_local;
wire local_bb1__338;
assign local_bb1__338 = (local_bb1_cmp19_2 & local_bb1_not_cmp16_2);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1_not_select6_0_valid_out_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_stall_in_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_valid_out_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_stall_in_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1_not_select6_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1_not_select6_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1_not_select6_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1_not_select6_0_stall_in_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1_not_select6_0_valid_out_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1_not_select6_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_not_select6_0_NO_SHIFT_REG),
.data_out(rnode_167to168_bb1_not_select6_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1_not_select6_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_not_select6_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_not_select6_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_not_select6_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1_not_select6_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_not_select6_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_not_select6_0_NO_SHIFT_REG = rnode_167to168_bb1_not_select6_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_not_select6_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_not_select6_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_NO_SHIFT_REG;
logic [11:0] rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [11:0] rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_fifo.DATA_WIDTH = 12;
defparam rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG = rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to170_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG = rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG = rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG = rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG = rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__push41__pop40_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__push41__pop40_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push41__pop40_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__push41__pop40_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push41__pop40_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push41__pop40_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push41__pop40_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push41__pop40_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__push41__pop40_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__push41__pop40_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__push41__pop40_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__push41__pop40_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__push41__pop40_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push41__pop40_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__push41__pop40_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__push41__pop40_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__push41__pop40_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__push41__pop40_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__push41__pop40_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__push41__pop40_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push41__pop40_stall_in = 1'b0;
assign rnode_169to171_bb1__push41__pop40_0_NO_SHIFT_REG = rnode_169to171_bb1__push41__pop40_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__push41__pop40_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push41__pop40_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_5_2_stall_local;
wire local_bb1_not_cmp16_5_2;
assign local_bb1_not_cmp16_5_2 = (rnode_168to169_bb1_cmp16_5_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__push42__pop41_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__push42__pop41_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push42__pop41_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__push42__pop41_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push42__pop41_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push42__pop41_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push42__pop41_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push42__pop41_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__push42__pop41_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__push42__pop41_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__push42__pop41_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__push42__pop41_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__push42__pop41_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push42__pop41_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__push42__pop41_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__push42__pop41_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__push42__pop41_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__push42__pop41_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__push42__pop41_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__push42__pop41_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push42__pop41_stall_in = 1'b0;
assign rnode_169to171_bb1__push42__pop41_0_NO_SHIFT_REG = rnode_169to171_bb1__push42__pop41_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__push42__pop41_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push42__pop41_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_6_2_stall_local;
wire local_bb1_not_cmp16_6_2;
assign local_bb1_not_cmp16_6_2 = (rnode_168to169_bb1_cmp16_6_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push43__pop42_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push43__pop42_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push43__pop42_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push43__pop42_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push43__pop42_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push43__pop42_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push43__pop42_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push43__pop42_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push43__pop42_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push43__pop42_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push43__pop42_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push43__pop42_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push43__pop42_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push43__pop42_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push43__pop42_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push43__pop42_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push43__pop42_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push43__pop42_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push43__pop42_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push43__pop42_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push43__pop42_stall_in = 1'b0;
assign rnode_170to171_bb1__push43__pop42_0_NO_SHIFT_REG = rnode_170to171_bb1__push43__pop42_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push43__pop42_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push43__pop42_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_cmp16_7_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_7_2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_cmp16_7_2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_cmp16_7_2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_cmp16_7_2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_cmp16_7_2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_cmp16_7_2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_7_2),
.data_out(rnode_169to170_bb1_cmp16_7_2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_cmp16_7_2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_cmp16_7_2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_cmp16_7_2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_cmp16_7_2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_cmp16_7_2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_7_2_stall_in = 1'b0;
assign rnode_169to170_bb1_cmp16_7_2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_7_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_7_2_0_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_7_2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_cmp16_7_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_7_2_1_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_7_2_0_reg_170_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push37__pop36_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push37__pop36_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push37__pop36_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push37__pop36_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push37__pop36_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push37__pop36_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push37__pop36_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push37__pop36_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push37__pop36_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push37__pop36_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push37__pop36_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push37__pop36_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push37__pop36_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push37__pop36_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push37__pop36_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push37__pop36_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push37__pop36_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push37__pop36_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push37__pop36_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push37__pop36_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push37__pop36_stall_in = 1'b0;
assign rnode_170to171_bb1__push37__pop36_0_NO_SHIFT_REG = rnode_170to171_bb1__push37__pop36_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push37__pop36_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push37__pop36_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_1_2_stall_local;
wire local_bb1_not_cmp16_1_2;
assign local_bb1_not_cmp16_1_2 = (local_bb1_cmp16_1_2 ^ 1'b1);
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__push38__pop37_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__push38__pop37_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push38__pop37_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__push38__pop37_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push38__pop37_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push38__pop37_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push38__pop37_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push38__pop37_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__push38__pop37_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__push38__pop37_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__push38__pop37_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__push38__pop37_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__push38__pop37_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push38__pop37_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__push38__pop37_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__push38__pop37_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__push38__pop37_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__push38__pop37_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__push38__pop37_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__push38__pop37_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push38__pop37_stall_in = 1'b0;
assign rnode_169to171_bb1__push38__pop37_0_NO_SHIFT_REG = rnode_169to171_bb1__push38__pop37_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__push38__pop37_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push38__pop37_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_2_2_stall_local;
wire local_bb1_not_cmp16_2_2;
assign local_bb1_not_cmp16_2_2 = (rnode_168to169_bb1_cmp16_2_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__push39__pop38_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__push39__pop38_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push39__pop38_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__push39__pop38_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push39__pop38_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push39__pop38_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push39__pop38_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push39__pop38_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__push39__pop38_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__push39__pop38_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__push39__pop38_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__push39__pop38_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__push39__pop38_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push39__pop38_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__push39__pop38_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__push39__pop38_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__push39__pop38_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__push39__pop38_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__push39__pop38_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__push39__pop38_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push39__pop38_stall_in = 1'b0;
assign rnode_169to171_bb1__push39__pop38_0_NO_SHIFT_REG = rnode_169to171_bb1__push39__pop38_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__push39__pop38_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push39__pop38_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_3_2_stall_local;
wire local_bb1_not_cmp16_3_2;
assign local_bb1_not_cmp16_3_2 = (rnode_168to169_bb1_cmp16_3_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__push40__pop39_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__push40__pop39_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push40__pop39_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__push40__pop39_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push40__pop39_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push40__pop39_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push40__pop39_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push40__pop39_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__push40__pop39_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__push40__pop39_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__push40__pop39_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__push40__pop39_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__push40__pop39_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push40__pop39_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__push40__pop39_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__push40__pop39_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__push40__pop39_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__push40__pop39_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__push40__pop39_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__push40__pop39_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push40__pop39_stall_in = 1'b0;
assign rnode_169to171_bb1__push40__pop39_0_NO_SHIFT_REG = rnode_169to171_bb1__push40__pop39_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__push40__pop39_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push40__pop39_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_4_2_stall_local;
wire local_bb1_not_cmp16_4_2;
assign local_bb1_not_cmp16_4_2 = (rnode_168to169_bb1_cmp16_4_2_1_NO_SHIFT_REG ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1__push49__pop48_inputs_ready;
reg local_bb1__push49__pop48_valid_out_NO_SHIFT_REG;
wire local_bb1__push49__pop48_stall_in;
wire local_bb1__push49__pop48_output_regs_ready;
wire [7:0] local_bb1__push49__pop48_result;
wire local_bb1__push49__pop48_fu_valid_out;
wire local_bb1__push49__pop48_fu_stall_out;
reg [7:0] local_bb1__push49__pop48_NO_SHIFT_REG;
wire local_bb1__push49__pop48_causedstall;
acl_push local_bb1__push49__pop48_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_169to170_bb1_c0_ene2_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(rnode_169to170_bb1__pop48__0_NO_SHIFT_REG),
.stall_out(local_bb1__push49__pop48_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[8]),
.valid_out(local_bb1__push49__pop48_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push49__pop48_result),
.feedback_out(feedback_data_out_49),
.feedback_valid_out(feedback_valid_out_49),
.feedback_stall_in(feedback_stall_in_49)
);
defparam local_bb1__push49__pop48_feedback.STALLFREE = 1;
defparam local_bb1__push49__pop48_feedback.DATA_WIDTH = 8;
defparam local_bb1__push49__pop48_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push49__pop48_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push49__pop48_feedback.STYLE = "REGULAR";
assign local_bb1__push49__pop48_inputs_ready = 1'b1;
assign local_bb1__push49__pop48_output_regs_ready = 1'b1;
assign rnode_169to170_bb1__pop48__0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1__push49__pop48_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[8] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push49__pop48_NO_SHIFT_REG <= 'x;
local_bb1__push49__pop48_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push49__pop48_output_regs_ready)
begin
local_bb1__push49__pop48_NO_SHIFT_REG <= local_bb1__push49__pop48_result;
local_bb1__push49__pop48_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push49__pop48_stall_in))
begin
local_bb1__push49__pop48_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_13_2_stall_local;
wire local_bb1_cmp16_13_2;
assign local_bb1_cmp16_13_2 = (rnode_169to170_bb1__pop48__1_NO_SHIFT_REG == 8'h0);
// This section implements a registered operation.
//
wire local_bb1__push44__pop43_inputs_ready;
reg local_bb1__push44__pop43_valid_out_NO_SHIFT_REG;
wire local_bb1__push44__pop43_stall_in;
wire local_bb1__push44__pop43_output_regs_ready;
wire [7:0] local_bb1__push44__pop43_result;
wire local_bb1__push44__pop43_fu_valid_out;
wire local_bb1__push44__pop43_fu_stall_out;
reg [7:0] local_bb1__push44__pop43_NO_SHIFT_REG;
wire local_bb1__push44__pop43_causedstall;
acl_push local_bb1__push44__pop43_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop43_),
.stall_out(local_bb1__push44__pop43_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push44__pop43_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push44__pop43_result),
.feedback_out(feedback_data_out_44),
.feedback_valid_out(feedback_valid_out_44),
.feedback_stall_in(feedback_stall_in_44)
);
defparam local_bb1__push44__pop43_feedback.STALLFREE = 1;
defparam local_bb1__push44__pop43_feedback.DATA_WIDTH = 8;
defparam local_bb1__push44__pop43_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push44__pop43_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push44__pop43_feedback.STYLE = "REGULAR";
assign local_bb1__push44__pop43_inputs_ready = 1'b1;
assign local_bb1__push44__pop43_output_regs_ready = 1'b1;
assign local_bb1__pop43__stall_in_0 = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1__push44__pop43_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push44__pop43_NO_SHIFT_REG <= 'x;
local_bb1__push44__pop43_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push44__pop43_output_regs_ready)
begin
local_bb1__push44__pop43_NO_SHIFT_REG <= local_bb1__push44__pop43_result;
local_bb1__push44__pop43_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push44__pop43_stall_in))
begin
local_bb1__push44__pop43_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_cmp16_8_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_8_2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_cmp16_8_2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_cmp16_8_2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_cmp16_8_2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_cmp16_8_2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_cmp16_8_2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_8_2),
.data_out(rnode_169to170_bb1_cmp16_8_2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_cmp16_8_2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_cmp16_8_2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_cmp16_8_2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_cmp16_8_2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_cmp16_8_2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_8_2_stall_in = 1'b0;
assign rnode_169to170_bb1_cmp16_8_2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_8_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_8_2_0_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_8_2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_cmp16_8_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_8_2_1_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_8_2_0_reg_170_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push45__pop44_inputs_ready;
reg local_bb1__push45__pop44_valid_out_NO_SHIFT_REG;
wire local_bb1__push45__pop44_stall_in;
wire local_bb1__push45__pop44_output_regs_ready;
wire [7:0] local_bb1__push45__pop44_result;
wire local_bb1__push45__pop44_fu_valid_out;
wire local_bb1__push45__pop44_fu_stall_out;
reg [7:0] local_bb1__push45__pop44_NO_SHIFT_REG;
wire local_bb1__push45__pop44_causedstall;
acl_push local_bb1__push45__pop44_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop44_),
.stall_out(local_bb1__push45__pop44_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push45__pop44_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push45__pop44_result),
.feedback_out(feedback_data_out_45),
.feedback_valid_out(feedback_valid_out_45),
.feedback_stall_in(feedback_stall_in_45)
);
defparam local_bb1__push45__pop44_feedback.STALLFREE = 1;
defparam local_bb1__push45__pop44_feedback.DATA_WIDTH = 8;
defparam local_bb1__push45__pop44_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push45__pop44_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push45__pop44_feedback.STYLE = "REGULAR";
assign local_bb1__push45__pop44_inputs_ready = 1'b1;
assign local_bb1__push45__pop44_output_regs_ready = 1'b1;
assign local_bb1__pop44__stall_in_0 = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign local_bb1__push45__pop44_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push45__pop44_NO_SHIFT_REG <= 'x;
local_bb1__push45__pop44_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push45__pop44_output_regs_ready)
begin
local_bb1__push45__pop44_NO_SHIFT_REG <= local_bb1__push45__pop44_result;
local_bb1__push45__pop44_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push45__pop44_stall_in))
begin
local_bb1__push45__pop44_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_cmp16_9_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_9_2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_cmp16_9_2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_cmp16_9_2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_cmp16_9_2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_cmp16_9_2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_cmp16_9_2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_9_2),
.data_out(rnode_169to170_bb1_cmp16_9_2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_cmp16_9_2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_cmp16_9_2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_cmp16_9_2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_cmp16_9_2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_cmp16_9_2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_9_2_stall_in = 1'b0;
assign rnode_169to170_bb1_cmp16_9_2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_9_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_9_2_0_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_9_2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_cmp16_9_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_9_2_1_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_9_2_0_reg_170_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push47__pop46_inputs_ready;
reg local_bb1__push47__pop46_valid_out_NO_SHIFT_REG;
wire local_bb1__push47__pop46_stall_in;
wire local_bb1__push47__pop46_output_regs_ready;
wire [7:0] local_bb1__push47__pop46_result;
wire local_bb1__push47__pop46_fu_valid_out;
wire local_bb1__push47__pop46_fu_stall_out;
reg [7:0] local_bb1__push47__pop46_NO_SHIFT_REG;
wire local_bb1__push47__pop46_causedstall;
acl_push local_bb1__push47__pop46_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_3_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop46_),
.stall_out(local_bb1__push47__pop46_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push47__pop46_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push47__pop46_result),
.feedback_out(feedback_data_out_47),
.feedback_valid_out(feedback_valid_out_47),
.feedback_stall_in(feedback_stall_in_47)
);
defparam local_bb1__push47__pop46_feedback.STALLFREE = 1;
defparam local_bb1__push47__pop46_feedback.DATA_WIDTH = 8;
defparam local_bb1__push47__pop46_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push47__pop46_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push47__pop46_feedback.STYLE = "REGULAR";
assign local_bb1__push47__pop46_inputs_ready = 1'b1;
assign local_bb1__push47__pop46_output_regs_ready = 1'b1;
assign local_bb1__pop46__stall_in_0 = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign local_bb1__push47__pop46_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push47__pop46_NO_SHIFT_REG <= 'x;
local_bb1__push47__pop46_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push47__pop46_output_regs_ready)
begin
local_bb1__push47__pop46_NO_SHIFT_REG <= local_bb1__push47__pop46_result;
local_bb1__push47__pop46_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push47__pop46_stall_in))
begin
local_bb1__push47__pop46_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_cmp16_11_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_11_2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_cmp16_11_2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_cmp16_11_2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_cmp16_11_2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_cmp16_11_2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_cmp16_11_2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_11_2),
.data_out(rnode_169to170_bb1_cmp16_11_2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_cmp16_11_2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_cmp16_11_2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_cmp16_11_2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_cmp16_11_2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_cmp16_11_2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_11_2_stall_in = 1'b0;
assign rnode_169to170_bb1_cmp16_11_2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_11_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_11_2_0_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_11_2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_cmp16_11_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_11_2_1_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_11_2_0_reg_170_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push48__pop47_inputs_ready;
reg local_bb1__push48__pop47_valid_out_NO_SHIFT_REG;
wire local_bb1__push48__pop47_stall_in;
wire local_bb1__push48__pop47_output_regs_ready;
wire [7:0] local_bb1__push48__pop47_result;
wire local_bb1__push48__pop47_fu_valid_out;
wire local_bb1__push48__pop47_fu_stall_out;
reg [7:0] local_bb1__push48__pop47_NO_SHIFT_REG;
wire local_bb1__push48__pop47_causedstall;
acl_push local_bb1__push48__pop47_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop47_),
.stall_out(local_bb1__push48__pop47_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push48__pop47_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push48__pop47_result),
.feedback_out(feedback_data_out_48),
.feedback_valid_out(feedback_valid_out_48),
.feedback_stall_in(feedback_stall_in_48)
);
defparam local_bb1__push48__pop47_feedback.STALLFREE = 1;
defparam local_bb1__push48__pop47_feedback.DATA_WIDTH = 8;
defparam local_bb1__push48__pop47_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push48__pop47_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push48__pop47_feedback.STYLE = "REGULAR";
assign local_bb1__push48__pop47_inputs_ready = 1'b1;
assign local_bb1__push48__pop47_output_regs_ready = 1'b1;
assign local_bb1__pop47__stall_in_0 = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG = 1'b0;
assign local_bb1__push48__pop47_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push48__pop47_NO_SHIFT_REG <= 'x;
local_bb1__push48__pop47_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push48__pop47_output_regs_ready)
begin
local_bb1__push48__pop47_NO_SHIFT_REG <= local_bb1__push48__pop47_result;
local_bb1__push48__pop47_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push48__pop47_stall_in))
begin
local_bb1__push48__pop47_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_cmp16_12_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_12_2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_cmp16_12_2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_cmp16_12_2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_cmp16_12_2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_cmp16_12_2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_cmp16_12_2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_12_2),
.data_out(rnode_169to170_bb1_cmp16_12_2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_cmp16_12_2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_cmp16_12_2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_cmp16_12_2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_cmp16_12_2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_cmp16_12_2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_12_2_stall_in = 1'b0;
assign rnode_169to170_bb1_cmp16_12_2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_12_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_12_2_0_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_12_2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_cmp16_12_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_12_2_1_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_12_2_0_reg_170_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push46__pop45_inputs_ready;
reg local_bb1__push46__pop45_valid_out_NO_SHIFT_REG;
wire local_bb1__push46__pop45_stall_in;
wire local_bb1__push46__pop45_output_regs_ready;
wire [7:0] local_bb1__push46__pop45_result;
wire local_bb1__push46__pop45_fu_valid_out;
wire local_bb1__push46__pop45_fu_stall_out;
reg [7:0] local_bb1__push46__pop45_NO_SHIFT_REG;
wire local_bb1__push46__pop45_causedstall;
acl_push local_bb1__push46__pop45_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_168to169_bb1_c0_ene2_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop45_),
.stall_out(local_bb1__push46__pop45_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[7]),
.valid_out(local_bb1__push46__pop45_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push46__pop45_result),
.feedback_out(feedback_data_out_46),
.feedback_valid_out(feedback_valid_out_46),
.feedback_stall_in(feedback_stall_in_46)
);
defparam local_bb1__push46__pop45_feedback.STALLFREE = 1;
defparam local_bb1__push46__pop45_feedback.DATA_WIDTH = 8;
defparam local_bb1__push46__pop45_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push46__pop45_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push46__pop45_feedback.STYLE = "REGULAR";
assign local_bb1__push46__pop45_inputs_ready = 1'b1;
assign local_bb1__push46__pop45_output_regs_ready = 1'b1;
assign local_bb1__pop45__stall_in_0 = 1'b0;
assign rnode_168to169_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG = 1'b0;
assign local_bb1__push46__pop45_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[7] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push46__pop45_NO_SHIFT_REG <= 'x;
local_bb1__push46__pop45_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push46__pop45_output_regs_ready)
begin
local_bb1__push46__pop45_NO_SHIFT_REG <= local_bb1__push46__pop45_result;
local_bb1__push46__pop45_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push46__pop45_stall_in))
begin
local_bb1__push46__pop45_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_cmp16_10_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_1_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_valid_out_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_stall_in_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_cmp16_10_2_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_cmp16_10_2_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_cmp16_10_2_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_cmp16_10_2_0_stall_in_0_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_cmp16_10_2_0_valid_out_0_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_cmp16_10_2_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_10_2),
.data_out(rnode_169to170_bb1_cmp16_10_2_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_cmp16_10_2_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_cmp16_10_2_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1_cmp16_10_2_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_cmp16_10_2_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_cmp16_10_2_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_10_2_stall_in = 1'b0;
assign rnode_169to170_bb1_cmp16_10_2_0_stall_in_0_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_10_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_10_2_0_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_10_2_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_cmp16_10_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_cmp16_10_2_1_NO_SHIFT_REG = rnode_169to170_bb1_cmp16_10_2_0_reg_170_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1__pop49__valid_out_0;
wire local_bb1__pop49__stall_in_0;
reg local_bb1__pop49__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_14_2_valid_out;
wire local_bb1_cmp16_14_2_stall_in;
reg local_bb1_cmp16_14_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_14_2_inputs_ready;
wire local_bb1_cmp16_14_2_stall_local;
wire local_bb1_cmp16_14_2;
assign local_bb1_cmp16_14_2_inputs_ready = rnode_169to170_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_cmp16_14_2 = (local_bb1__pop49_ == 8'h0);
assign local_bb1__pop49__valid_out_0 = 1'b1;
assign local_bb1_cmp16_14_2_valid_out = 1'b1;
assign rnode_169to170_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop49__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_14_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop49__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_14_2_inputs_ready & (local_bb1__pop49__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop49__stall_in_0)) & local_bb1_cmp16_14_2_stall_local);
local_bb1_cmp16_14_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_14_2_inputs_ready & (local_bb1_cmp16_14_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_14_2_stall_in)) & local_bb1_cmp16_14_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1__pop50__valid_out_0;
wire local_bb1__pop50__stall_in_0;
reg local_bb1__pop50__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_15_2_valid_out;
wire local_bb1_cmp16_15_2_stall_in;
reg local_bb1_cmp16_15_2_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_15_2_inputs_ready;
wire local_bb1_cmp16_15_2_stall_local;
wire local_bb1_cmp16_15_2;
assign local_bb1_cmp16_15_2_inputs_ready = rnode_169to170_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_cmp16_15_2 = (local_bb1__pop50_ == 8'h0);
assign local_bb1__pop50__valid_out_0 = 1'b1;
assign local_bb1_cmp16_15_2_valid_out = 1'b1;
assign rnode_169to170_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__pop50__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_15_2_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__pop50__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_15_2_inputs_ready & (local_bb1__pop50__consumed_0_NO_SHIFT_REG | ~(local_bb1__pop50__stall_in_0)) & local_bb1_cmp16_15_2_stall_local);
local_bb1_cmp16_15_2_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_15_2_inputs_ready & (local_bb1_cmp16_15_2_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_15_2_stall_in)) & local_bb1_cmp16_15_2_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_cmp16_16_2_valid_out;
wire local_bb1_cmp16_16_2_stall_in;
wire local_bb1_cmp16_16_2_inputs_ready;
wire local_bb1_cmp16_16_2_stall_local;
wire local_bb1_cmp16_16_2;
assign local_bb1_cmp16_16_2_inputs_ready = rnode_169to170_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1_cmp16_16_2 = (local_bb1__pop51_ == 8'h0);
assign local_bb1_cmp16_16_2_valid_out = 1'b1;
assign rnode_169to170_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG = 1'b0;
// This section implements an unregistered operation.
//
wire local_bb1__337_stall_local;
wire [7:0] local_bb1__337;
assign local_bb1__337 = (local_bb1__336_demorgan ? 8'h1 : local_bb1__335);
// This section implements an unregistered operation.
//
wire local_bb1__coalesced_pop2__stall_local;
wire [7:0] local_bb1__coalesced_pop2_;
wire local_bb1__coalesced_pop2__fu_valid_out;
wire local_bb1__coalesced_pop2__fu_stall_out;
acl_pop local_bb1__coalesced_pop2__feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_not_select6_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in('x),
.stall_out(local_bb1__coalesced_pop2__fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__coalesced_pop2__fu_valid_out),
.stall_in(local_bb1__coalesced_pop2__stall_local),
.data_out(local_bb1__coalesced_pop2_),
.feedback_in(feedback_data_in_2),
.feedback_valid_in(feedback_valid_in_2),
.feedback_stall_out(feedback_stall_out_2)
);
defparam local_bb1__coalesced_pop2__feedback.DATA_WIDTH = 8;
defparam local_bb1__coalesced_pop2__feedback.STYLE = "COALESCE";
assign local_bb1__coalesced_pop2__stall_local = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_NO_SHIFT_REG;
logic [11:0] rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [11:0] rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_fifo.DATA_WIDTH = 12;
defparam rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_NO_SHIFT_REG = rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_7_2_stall_local;
wire local_bb1_not_cmp16_7_2;
assign local_bb1_not_cmp16_7_2 = (rnode_169to170_bb1_cmp16_7_2_1_NO_SHIFT_REG ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_13_2_stall_local;
wire local_bb1_not_cmp16_13_2;
assign local_bb1_not_cmp16_13_2 = (local_bb1_cmp16_13_2 ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push44__pop43_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push44__pop43_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push44__pop43_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push44__pop43_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push44__pop43_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push44__pop43_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push44__pop43_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push44__pop43_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push44__pop43_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push44__pop43_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push44__pop43_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push44__pop43_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push44__pop43_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push44__pop43_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push44__pop43_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push44__pop43_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push44__pop43_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push44__pop43_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push44__pop43_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push44__pop43_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push44__pop43_stall_in = 1'b0;
assign rnode_170to171_bb1__push44__pop43_0_NO_SHIFT_REG = rnode_170to171_bb1__push44__pop43_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push44__pop43_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push44__pop43_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_8_2_stall_local;
wire local_bb1_not_cmp16_8_2;
assign local_bb1_not_cmp16_8_2 = (rnode_169to170_bb1_cmp16_8_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push45__pop44_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push45__pop44_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push45__pop44_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push45__pop44_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push45__pop44_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push45__pop44_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push45__pop44_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push45__pop44_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push45__pop44_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push45__pop44_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push45__pop44_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push45__pop44_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push45__pop44_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push45__pop44_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push45__pop44_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push45__pop44_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push45__pop44_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push45__pop44_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push45__pop44_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push45__pop44_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push45__pop44_stall_in = 1'b0;
assign rnode_170to171_bb1__push45__pop44_0_NO_SHIFT_REG = rnode_170to171_bb1__push45__pop44_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push45__pop44_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push45__pop44_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_9_2_stall_local;
wire local_bb1_not_cmp16_9_2;
assign local_bb1_not_cmp16_9_2 = (rnode_169to170_bb1_cmp16_9_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push47__pop46_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push47__pop46_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push47__pop46_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push47__pop46_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push47__pop46_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push47__pop46_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push47__pop46_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push47__pop46_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push47__pop46_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push47__pop46_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push47__pop46_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push47__pop46_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push47__pop46_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push47__pop46_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push47__pop46_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push47__pop46_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push47__pop46_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push47__pop46_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push47__pop46_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push47__pop46_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push47__pop46_stall_in = 1'b0;
assign rnode_170to171_bb1__push47__pop46_0_NO_SHIFT_REG = rnode_170to171_bb1__push47__pop46_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push47__pop46_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push47__pop46_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_11_2_stall_local;
wire local_bb1_not_cmp16_11_2;
assign local_bb1_not_cmp16_11_2 = (rnode_169to170_bb1_cmp16_11_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push48__pop47_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push48__pop47_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push48__pop47_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push48__pop47_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push48__pop47_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push48__pop47_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push48__pop47_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push48__pop47_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push48__pop47_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push48__pop47_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push48__pop47_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push48__pop47_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push48__pop47_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push48__pop47_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push48__pop47_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push48__pop47_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push48__pop47_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push48__pop47_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push48__pop47_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push48__pop47_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push48__pop47_stall_in = 1'b0;
assign rnode_170to171_bb1__push48__pop47_0_NO_SHIFT_REG = rnode_170to171_bb1__push48__pop47_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push48__pop47_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push48__pop47_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_12_2_stall_local;
wire local_bb1_not_cmp16_12_2;
assign local_bb1_not_cmp16_12_2 = (rnode_169to170_bb1_cmp16_12_2_1_NO_SHIFT_REG ^ 1'b1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1__push46__pop45_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1__push46__pop45_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push46__pop45_0_NO_SHIFT_REG;
logic rnode_170to171_bb1__push46__pop45_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1__push46__pop45_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push46__pop45_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push46__pop45_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1__push46__pop45_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1__push46__pop45_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1__push46__pop45_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1__push46__pop45_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1__push46__pop45_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1__push46__pop45_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push46__pop45_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1__push46__pop45_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1__push46__pop45_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1__push46__pop45_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1__push46__pop45_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1__push46__pop45_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1__push46__pop45_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push46__pop45_stall_in = 1'b0;
assign rnode_170to171_bb1__push46__pop45_0_NO_SHIFT_REG = rnode_170to171_bb1__push46__pop45_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1__push46__pop45_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push46__pop45_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_10_2_stall_local;
wire local_bb1_not_cmp16_10_2;
assign local_bb1_not_cmp16_10_2 = (rnode_169to170_bb1_cmp16_10_2_1_NO_SHIFT_REG ^ 1'b1);
// This section implements a registered operation.
//
wire local_bb1__push50__pop49_inputs_ready;
reg local_bb1__push50__pop49_valid_out_NO_SHIFT_REG;
wire local_bb1__push50__pop49_stall_in;
wire local_bb1__push50__pop49_output_regs_ready;
wire [7:0] local_bb1__push50__pop49_result;
wire local_bb1__push50__pop49_fu_valid_out;
wire local_bb1__push50__pop49_fu_stall_out;
reg [7:0] local_bb1__push50__pop49_NO_SHIFT_REG;
wire local_bb1__push50__pop49_causedstall;
acl_push local_bb1__push50__pop49_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_169to170_bb1_c0_ene2_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop49_),
.stall_out(local_bb1__push50__pop49_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[8]),
.valid_out(local_bb1__push50__pop49_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push50__pop49_result),
.feedback_out(feedback_data_out_50),
.feedback_valid_out(feedback_valid_out_50),
.feedback_stall_in(feedback_stall_in_50)
);
defparam local_bb1__push50__pop49_feedback.STALLFREE = 1;
defparam local_bb1__push50__pop49_feedback.DATA_WIDTH = 8;
defparam local_bb1__push50__pop49_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push50__pop49_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push50__pop49_feedback.STYLE = "REGULAR";
assign local_bb1__push50__pop49_inputs_ready = 1'b1;
assign local_bb1__push50__pop49_output_regs_ready = 1'b1;
assign local_bb1__pop49__stall_in_0 = 1'b0;
assign rnode_169to170_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1__push50__pop49_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[8] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push50__pop49_NO_SHIFT_REG <= 'x;
local_bb1__push50__pop49_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push50__pop49_output_regs_ready)
begin
local_bb1__push50__pop49_NO_SHIFT_REG <= local_bb1__push50__pop49_result;
local_bb1__push50__pop49_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push50__pop49_stall_in))
begin
local_bb1__push50__pop49_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_cmp16_14_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_valid_out_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_stall_in_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_14_2_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_cmp16_14_2_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_cmp16_14_2_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_cmp16_14_2_0_stall_in_0_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_cmp16_14_2_0_valid_out_0_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_cmp16_14_2_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_14_2),
.data_out(rnode_170to171_bb1_cmp16_14_2_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_cmp16_14_2_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_cmp16_14_2_0_reg_171_fifo.DATA_WIDTH = 1;
defparam rnode_170to171_bb1_cmp16_14_2_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_cmp16_14_2_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_cmp16_14_2_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_14_2_stall_in = 1'b0;
assign rnode_170to171_bb1_cmp16_14_2_0_stall_in_0_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_14_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_cmp16_14_2_0_NO_SHIFT_REG = rnode_170to171_bb1_cmp16_14_2_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_cmp16_14_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_cmp16_14_2_1_NO_SHIFT_REG = rnode_170to171_bb1_cmp16_14_2_0_reg_171_NO_SHIFT_REG;
// This section implements a registered operation.
//
wire local_bb1__push51__pop50_inputs_ready;
reg local_bb1__push51__pop50_valid_out_NO_SHIFT_REG;
wire local_bb1__push51__pop50_stall_in;
wire local_bb1__push51__pop50_output_regs_ready;
wire [7:0] local_bb1__push51__pop50_result;
wire local_bb1__push51__pop50_fu_valid_out;
wire local_bb1__push51__pop50_fu_stall_out;
reg [7:0] local_bb1__push51__pop50_NO_SHIFT_REG;
wire local_bb1__push51__pop50_causedstall;
acl_push local_bb1__push51__pop50_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_169to170_bb1_c0_ene2_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__pop50_),
.stall_out(local_bb1__push51__pop50_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[8]),
.valid_out(local_bb1__push51__pop50_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push51__pop50_result),
.feedback_out(feedback_data_out_51),
.feedback_valid_out(feedback_valid_out_51),
.feedback_stall_in(feedback_stall_in_51)
);
defparam local_bb1__push51__pop50_feedback.STALLFREE = 1;
defparam local_bb1__push51__pop50_feedback.DATA_WIDTH = 8;
defparam local_bb1__push51__pop50_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push51__pop50_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push51__pop50_feedback.STYLE = "REGULAR";
assign local_bb1__push51__pop50_inputs_ready = 1'b1;
assign local_bb1__push51__pop50_output_regs_ready = 1'b1;
assign local_bb1__pop50__stall_in_0 = 1'b0;
assign rnode_169to170_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign local_bb1__push51__pop50_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[8] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push51__pop50_NO_SHIFT_REG <= 'x;
local_bb1__push51__pop50_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push51__pop50_output_regs_ready)
begin
local_bb1__push51__pop50_NO_SHIFT_REG <= local_bb1__push51__pop50_result;
local_bb1__push51__pop50_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push51__pop50_stall_in))
begin
local_bb1__push51__pop50_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_cmp16_15_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_valid_out_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_stall_in_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_15_2_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_cmp16_15_2_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_cmp16_15_2_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_cmp16_15_2_0_stall_in_0_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_cmp16_15_2_0_valid_out_0_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_cmp16_15_2_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_15_2),
.data_out(rnode_170to171_bb1_cmp16_15_2_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_cmp16_15_2_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_cmp16_15_2_0_reg_171_fifo.DATA_WIDTH = 1;
defparam rnode_170to171_bb1_cmp16_15_2_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_cmp16_15_2_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_cmp16_15_2_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_15_2_stall_in = 1'b0;
assign rnode_170to171_bb1_cmp16_15_2_0_stall_in_0_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_15_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_cmp16_15_2_0_NO_SHIFT_REG = rnode_170to171_bb1_cmp16_15_2_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_cmp16_15_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_cmp16_15_2_1_NO_SHIFT_REG = rnode_170to171_bb1_cmp16_15_2_0_reg_171_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_cmp16_16_2_0_valid_out_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_stall_in_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_valid_out_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_stall_in_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_valid_out_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_stall_in_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_cmp16_16_2_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_cmp16_16_2_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_cmp16_16_2_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_cmp16_16_2_0_stall_in_0_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_cmp16_16_2_0_valid_out_0_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_cmp16_16_2_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_16_2),
.data_out(rnode_170to171_bb1_cmp16_16_2_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_cmp16_16_2_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_cmp16_16_2_0_reg_171_fifo.DATA_WIDTH = 1;
defparam rnode_170to171_bb1_cmp16_16_2_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_cmp16_16_2_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_cmp16_16_2_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_16_2_stall_in = 1'b0;
assign rnode_170to171_bb1_cmp16_16_2_0_stall_in_0_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_16_2_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_cmp16_16_2_0_NO_SHIFT_REG = rnode_170to171_bb1_cmp16_16_2_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_cmp16_16_2_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_cmp16_16_2_1_NO_SHIFT_REG = rnode_170to171_bb1_cmp16_16_2_0_reg_171_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1__339_stall_local;
wire [7:0] local_bb1__339;
assign local_bb1__339 = (local_bb1__338 ? 8'h0 : local_bb1__337);
// This section implements an unregistered operation.
//
wire local_bb1__coalesced_pop2__valid_out_0;
wire local_bb1__coalesced_pop2__stall_in_0;
reg local_bb1__coalesced_pop2__consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_228_valid_out;
wire local_bb1_cmp16_228_stall_in;
reg local_bb1_cmp16_228_consumed_0_NO_SHIFT_REG;
wire local_bb1_cmp16_228_inputs_ready;
wire local_bb1_cmp16_228_stall_local;
wire local_bb1_cmp16_228;
assign local_bb1_cmp16_228_inputs_ready = rnode_167to168_bb1_not_select6_0_valid_out_NO_SHIFT_REG;
assign local_bb1_cmp16_228 = (local_bb1__coalesced_pop2_ == 8'h0);
assign local_bb1__coalesced_pop2__valid_out_0 = 1'b1;
assign local_bb1_cmp16_228_valid_out = 1'b1;
assign rnode_167to168_bb1_not_select6_0_stall_in_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__coalesced_pop2__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_cmp16_228_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__coalesced_pop2__consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_228_inputs_ready & (local_bb1__coalesced_pop2__consumed_0_NO_SHIFT_REG | ~(local_bb1__coalesced_pop2__stall_in_0)) & local_bb1_cmp16_228_stall_local);
local_bb1_cmp16_228_consumed_0_NO_SHIFT_REG <= (local_bb1_cmp16_228_inputs_ready & (local_bb1_cmp16_228_consumed_0_NO_SHIFT_REG | ~(local_bb1_cmp16_228_stall_in)) & local_bb1_cmp16_228_stall_local);
end
end
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_14_2_stall_local;
wire local_bb1_not_cmp16_14_2;
assign local_bb1_not_cmp16_14_2 = (rnode_170to171_bb1_cmp16_14_2_1_NO_SHIFT_REG ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_15_2_stall_local;
wire local_bb1_not_cmp16_15_2;
assign local_bb1_not_cmp16_15_2 = (rnode_170to171_bb1_cmp16_15_2_1_NO_SHIFT_REG ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_16_2_stall_local;
wire local_bb1_not_cmp16_16_2;
assign local_bb1_not_cmp16_16_2 = (rnode_170to171_bb1_cmp16_16_2_1_NO_SHIFT_REG ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1_var__u2_stall_local;
wire [7:0] local_bb1_var__u2;
assign local_bb1_var__u2 = (local_bb1__339 & 8'h1);
// This section implements a registered operation.
//
wire local_bb1__push36__coalesced_pop2_inputs_ready;
reg local_bb1__push36__coalesced_pop2_valid_out_NO_SHIFT_REG;
wire local_bb1__push36__coalesced_pop2_stall_in;
wire local_bb1__push36__coalesced_pop2_output_regs_ready;
wire [7:0] local_bb1__push36__coalesced_pop2_result;
wire local_bb1__push36__coalesced_pop2_fu_valid_out;
wire local_bb1__push36__coalesced_pop2_fu_stall_out;
reg [7:0] local_bb1__push36__coalesced_pop2_NO_SHIFT_REG;
wire local_bb1__push36__coalesced_pop2_causedstall;
acl_push local_bb1__push36__coalesced_pop2_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_8_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1__coalesced_pop2_),
.stall_out(local_bb1__push36__coalesced_pop2_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__push36__coalesced_pop2_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__push36__coalesced_pop2_result),
.feedback_out(feedback_data_out_36),
.feedback_valid_out(feedback_valid_out_36),
.feedback_stall_in(feedback_stall_in_36)
);
defparam local_bb1__push36__coalesced_pop2_feedback.STALLFREE = 1;
defparam local_bb1__push36__coalesced_pop2_feedback.DATA_WIDTH = 8;
defparam local_bb1__push36__coalesced_pop2_feedback.FIFO_DEPTH = 1;
defparam local_bb1__push36__coalesced_pop2_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1__push36__coalesced_pop2_feedback.STYLE = "REGULAR";
assign local_bb1__push36__coalesced_pop2_inputs_ready = 1'b1;
assign local_bb1__push36__coalesced_pop2_output_regs_ready = 1'b1;
assign local_bb1__coalesced_pop2__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_8_NO_SHIFT_REG = 1'b0;
assign local_bb1__push36__coalesced_pop2_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__push36__coalesced_pop2_NO_SHIFT_REG <= 'x;
local_bb1__push36__coalesced_pop2_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__push36__coalesced_pop2_output_regs_ready)
begin
local_bb1__push36__coalesced_pop2_NO_SHIFT_REG <= local_bb1__push36__coalesced_pop2_result;
local_bb1__push36__coalesced_pop2_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__push36__coalesced_pop2_stall_in))
begin
local_bb1__push36__coalesced_pop2_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_cmp16_228_0_valid_out_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_stall_in_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_valid_out_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_stall_in_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_1_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_valid_out_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_stall_in_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_cmp16_228_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_cmp16_228_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_cmp16_228_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_cmp16_228_0_stall_in_0_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_cmp16_228_0_valid_out_0_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_cmp16_228_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_cmp16_228),
.data_out(rnode_168to169_bb1_cmp16_228_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_cmp16_228_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_cmp16_228_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1_cmp16_228_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_cmp16_228_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_cmp16_228_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp16_228_stall_in = 1'b0;
assign rnode_168to169_bb1_cmp16_228_0_stall_in_0_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_228_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_228_0_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_228_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_cmp16_228_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_cmp16_228_1_NO_SHIFT_REG = rnode_168to169_bb1_cmp16_228_0_reg_169_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_3_stall_local;
wire local_bb1_cmp19_3;
assign local_bb1_cmp19_3 = (local_bb1_var__u2 == 8'h0);
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__push36__coalesced_pop2_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__push36__coalesced_pop2_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push36__coalesced_pop2_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push36__coalesced_pop2_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push36__coalesced_pop2_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__push36__coalesced_pop2_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__push36__coalesced_pop2_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__push36__coalesced_pop2_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__push36__coalesced_pop2_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__push36__coalesced_pop2_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__push36__coalesced_pop2_stall_in = 1'b0;
assign rnode_169to171_bb1__push36__coalesced_pop2_0_NO_SHIFT_REG = rnode_169to171_bb1__push36__coalesced_pop2_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__push36__coalesced_pop2_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push36__coalesced_pop2_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_not_cmp16_228_stall_local;
wire local_bb1_not_cmp16_228;
assign local_bb1_not_cmp16_228 = (rnode_168to169_bb1_cmp16_228_1_NO_SHIFT_REG ^ 1'b1);
// This section implements an unregistered operation.
//
wire local_bb1__340_demorgan_stall_local;
wire local_bb1__340_demorgan;
assign local_bb1__340_demorgan = (local_bb1_cmp16_3 | local_bb1_cmp19_3);
// This section implements an unregistered operation.
//
wire local_bb1__342_stall_local;
wire local_bb1__342;
assign local_bb1__342 = (local_bb1_cmp19_3 & local_bb1_not_cmp16_3);
// This section implements an unregistered operation.
//
wire local_bb1__341_stall_local;
wire [7:0] local_bb1__341;
assign local_bb1__341 = (local_bb1__340_demorgan ? 8'h1 : local_bb1__339);
// This section implements an unregistered operation.
//
wire local_bb1_rows_1_0_pop34__valid_out_0;
wire local_bb1_rows_1_0_pop34__stall_in_0;
reg local_bb1_rows_1_0_pop34__consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_0_0_pop35__valid_out_0;
wire local_bb1_rows_0_0_pop35__stall_in_0;
reg local_bb1_rows_0_0_pop35__consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_2_0_pop33__valid_out_0;
wire local_bb1_rows_2_0_pop33__stall_in_0;
reg local_bb1_rows_2_0_pop33__consumed_0_NO_SHIFT_REG;
wire local_bb1__343_valid_out;
wire local_bb1__343_stall_in;
reg local_bb1__343_consumed_0_NO_SHIFT_REG;
wire local_bb1__343_inputs_ready;
wire local_bb1__343_stall_local;
wire [7:0] local_bb1__343;
assign local_bb1__343_inputs_ready = (local_bb1_c0_ene1_valid_out_0_NO_SHIFT_REG & local_bb1_c0_ene1_valid_out_1_NO_SHIFT_REG & rnode_163to164_bb1_c0_ene3_0_valid_out_1_NO_SHIFT_REG & local_bb1_c0_ene1_valid_out_2_NO_SHIFT_REG);
assign local_bb1__343 = (local_bb1__342 ? 8'h0 : local_bb1__341);
assign local_bb1_rows_1_0_pop34__valid_out_0 = 1'b1;
assign local_bb1_rows_0_0_pop35__valid_out_0 = 1'b1;
assign local_bb1_rows_2_0_pop33__valid_out_0 = 1'b1;
assign local_bb1__343_valid_out = 1'b1;
assign local_bb1_c0_ene1_stall_in_0 = 1'b0;
assign local_bb1_c0_ene1_stall_in_1 = 1'b0;
assign rnode_163to164_bb1_c0_ene3_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1_c0_ene1_stall_in_2 = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1_0_pop34__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_0_0_pop35__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_2_0_pop33__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__343_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1_0_pop34__consumed_0_NO_SHIFT_REG <= (local_bb1__343_inputs_ready & (local_bb1_rows_1_0_pop34__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1_0_pop34__stall_in_0)) & local_bb1__343_stall_local);
local_bb1_rows_0_0_pop35__consumed_0_NO_SHIFT_REG <= (local_bb1__343_inputs_ready & (local_bb1_rows_0_0_pop35__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_0_0_pop35__stall_in_0)) & local_bb1__343_stall_local);
local_bb1_rows_2_0_pop33__consumed_0_NO_SHIFT_REG <= (local_bb1__343_inputs_ready & (local_bb1_rows_2_0_pop33__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_2_0_pop33__stall_in_0)) & local_bb1__343_stall_local);
local_bb1__343_consumed_0_NO_SHIFT_REG <= (local_bb1__343_inputs_ready & (local_bb1__343_consumed_0_NO_SHIFT_REG | ~(local_bb1__343_stall_in)) & local_bb1__343_stall_local);
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_2_0_push33_rows_1_0_pop34_inputs_ready;
reg local_bb1_rows_2_0_push33_rows_1_0_pop34_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_2_0_push33_rows_1_0_pop34_stall_in;
wire local_bb1_rows_2_0_push33_rows_1_0_pop34_output_regs_ready;
wire [7:0] local_bb1_rows_2_0_push33_rows_1_0_pop34_result;
wire local_bb1_rows_2_0_push33_rows_1_0_pop34_fu_valid_out;
wire local_bb1_rows_2_0_push33_rows_1_0_pop34_fu_stall_out;
reg [7:0] local_bb1_rows_2_0_push33_rows_1_0_pop34_NO_SHIFT_REG;
wire local_bb1_rows_2_0_push33_rows_1_0_pop34_causedstall;
acl_push local_bb1_rows_2_0_push33_rows_1_0_pop34_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1_0_pop34_),
.stall_out(local_bb1_rows_2_0_push33_rows_1_0_pop34_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_2_0_push33_rows_1_0_pop34_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_2_0_push33_rows_1_0_pop34_result),
.feedback_out(feedback_data_out_33),
.feedback_valid_out(feedback_valid_out_33),
.feedback_stall_in(feedback_stall_in_33)
);
defparam local_bb1_rows_2_0_push33_rows_1_0_pop34_feedback.STALLFREE = 1;
defparam local_bb1_rows_2_0_push33_rows_1_0_pop34_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_2_0_push33_rows_1_0_pop34_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_2_0_push33_rows_1_0_pop34_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_2_0_push33_rows_1_0_pop34_feedback.STYLE = "REGULAR";
assign local_bb1_rows_2_0_push33_rows_1_0_pop34_inputs_ready = 1'b1;
assign local_bb1_rows_2_0_push33_rows_1_0_pop34_output_regs_ready = 1'b1;
assign local_bb1_rows_1_0_pop34__stall_in_0 = 1'b0;
assign local_bb1_c0_ene2_stall_in_1 = 1'b0;
assign local_bb1_rows_2_0_push33_rows_1_0_pop34_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[2] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_2_0_push33_rows_1_0_pop34_NO_SHIFT_REG <= 'x;
local_bb1_rows_2_0_push33_rows_1_0_pop34_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_2_0_push33_rows_1_0_pop34_output_regs_ready)
begin
local_bb1_rows_2_0_push33_rows_1_0_pop34_NO_SHIFT_REG <= local_bb1_rows_2_0_push33_rows_1_0_pop34_result;
local_bb1_rows_2_0_push33_rows_1_0_pop34_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_2_0_push33_rows_1_0_pop34_stall_in))
begin
local_bb1_rows_2_0_push33_rows_1_0_pop34_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_1_0_push34_rows_0_0_pop35_inputs_ready;
reg local_bb1_rows_1_0_push34_rows_0_0_pop35_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1_0_push34_rows_0_0_pop35_stall_in;
wire local_bb1_rows_1_0_push34_rows_0_0_pop35_output_regs_ready;
wire [7:0] local_bb1_rows_1_0_push34_rows_0_0_pop35_result;
wire local_bb1_rows_1_0_push34_rows_0_0_pop35_fu_valid_out;
wire local_bb1_rows_1_0_push34_rows_0_0_pop35_fu_stall_out;
reg [7:0] local_bb1_rows_1_0_push34_rows_0_0_pop35_NO_SHIFT_REG;
wire local_bb1_rows_1_0_push34_rows_0_0_pop35_causedstall;
acl_push local_bb1_rows_1_0_push34_rows_0_0_pop35_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_0_0_pop35_),
.stall_out(local_bb1_rows_1_0_push34_rows_0_0_pop35_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_1_0_push34_rows_0_0_pop35_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1_0_push34_rows_0_0_pop35_result),
.feedback_out(feedback_data_out_34),
.feedback_valid_out(feedback_valid_out_34),
.feedback_stall_in(feedback_stall_in_34)
);
defparam local_bb1_rows_1_0_push34_rows_0_0_pop35_feedback.STALLFREE = 1;
defparam local_bb1_rows_1_0_push34_rows_0_0_pop35_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1_0_push34_rows_0_0_pop35_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1_0_push34_rows_0_0_pop35_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1_0_push34_rows_0_0_pop35_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1_0_push34_rows_0_0_pop35_inputs_ready = 1'b1;
assign local_bb1_rows_1_0_push34_rows_0_0_pop35_output_regs_ready = 1'b1;
assign local_bb1_rows_0_0_pop35__stall_in_0 = 1'b0;
assign local_bb1_c0_ene2_stall_in_0 = 1'b0;
assign local_bb1_rows_1_0_push34_rows_0_0_pop35_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[2] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1_0_push34_rows_0_0_pop35_NO_SHIFT_REG <= 'x;
local_bb1_rows_1_0_push34_rows_0_0_pop35_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1_0_push34_rows_0_0_pop35_output_regs_ready)
begin
local_bb1_rows_1_0_push34_rows_0_0_pop35_NO_SHIFT_REG <= local_bb1_rows_1_0_push34_rows_0_0_pop35_result;
local_bb1_rows_1_0_push34_rows_0_0_pop35_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1_0_push34_rows_0_0_pop35_stall_in))
begin
local_bb1_rows_1_0_push34_rows_0_0_pop35_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_3_0_push32_rows_2_0_pop33_inputs_ready;
reg local_bb1_rows_3_0_push32_rows_2_0_pop33_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_3_0_push32_rows_2_0_pop33_stall_in;
wire local_bb1_rows_3_0_push32_rows_2_0_pop33_output_regs_ready;
wire [7:0] local_bb1_rows_3_0_push32_rows_2_0_pop33_result;
wire local_bb1_rows_3_0_push32_rows_2_0_pop33_fu_valid_out;
wire local_bb1_rows_3_0_push32_rows_2_0_pop33_fu_stall_out;
reg [7:0] local_bb1_rows_3_0_push32_rows_2_0_pop33_NO_SHIFT_REG;
wire local_bb1_rows_3_0_push32_rows_2_0_pop33_causedstall;
acl_push local_bb1_rows_3_0_push32_rows_2_0_pop33_feedback (
.clock(clock),
.resetn(resetn),
.dir(local_bb1_c0_ene2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_2_0_pop33_),
.stall_out(local_bb1_rows_3_0_push32_rows_2_0_pop33_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[2]),
.valid_out(local_bb1_rows_3_0_push32_rows_2_0_pop33_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_3_0_push32_rows_2_0_pop33_result),
.feedback_out(feedback_data_out_32),
.feedback_valid_out(feedback_valid_out_32),
.feedback_stall_in(feedback_stall_in_32)
);
defparam local_bb1_rows_3_0_push32_rows_2_0_pop33_feedback.STALLFREE = 1;
defparam local_bb1_rows_3_0_push32_rows_2_0_pop33_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_3_0_push32_rows_2_0_pop33_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_3_0_push32_rows_2_0_pop33_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_3_0_push32_rows_2_0_pop33_feedback.STYLE = "REGULAR";
assign local_bb1_rows_3_0_push32_rows_2_0_pop33_inputs_ready = 1'b1;
assign local_bb1_rows_3_0_push32_rows_2_0_pop33_output_regs_ready = 1'b1;
assign local_bb1_rows_2_0_pop33__stall_in_0 = 1'b0;
assign local_bb1_c0_ene2_stall_in_2 = 1'b0;
assign local_bb1_rows_3_0_push32_rows_2_0_pop33_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[2] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_3_0_push32_rows_2_0_pop33_NO_SHIFT_REG <= 'x;
local_bb1_rows_3_0_push32_rows_2_0_pop33_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_3_0_push32_rows_2_0_pop33_output_regs_ready)
begin
local_bb1_rows_3_0_push32_rows_2_0_pop33_NO_SHIFT_REG <= local_bb1_rows_3_0_push32_rows_2_0_pop33_result;
local_bb1_rows_3_0_push32_rows_2_0_pop33_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_3_0_push32_rows_2_0_pop33_stall_in))
begin
local_bb1_rows_3_0_push32_rows_2_0_pop33_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_164to165_bb1__343_0_valid_out_0_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_164to165_bb1__343_0_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_valid_out_1_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_164to165_bb1__343_1_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_reg_165_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_164to165_bb1__343_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_valid_out_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_stall_in_0_reg_165_NO_SHIFT_REG;
logic rnode_164to165_bb1__343_0_stall_out_reg_165_NO_SHIFT_REG;
acl_data_fifo rnode_164to165_bb1__343_0_reg_165_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_164to165_bb1__343_0_reg_165_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_164to165_bb1__343_0_stall_in_0_reg_165_NO_SHIFT_REG),
.valid_out(rnode_164to165_bb1__343_0_valid_out_0_reg_165_NO_SHIFT_REG),
.stall_out(rnode_164to165_bb1__343_0_stall_out_reg_165_NO_SHIFT_REG),
.data_in(local_bb1__343),
.data_out(rnode_164to165_bb1__343_0_reg_165_NO_SHIFT_REG)
);
defparam rnode_164to165_bb1__343_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1__343_0_reg_165_fifo.DATA_WIDTH = 8;
defparam rnode_164to165_bb1__343_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1__343_0_reg_165_fifo.IMPL = "shift_reg";
assign rnode_164to165_bb1__343_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__343_stall_in = 1'b0;
assign rnode_164to165_bb1__343_0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1__343_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1__343_0_NO_SHIFT_REG = rnode_164to165_bb1__343_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1__343_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1__343_1_NO_SHIFT_REG = rnode_164to165_bb1__343_0_reg_165_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_2_0_push33_rows_1_0_pop34_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_2_0_push33_rows_1_0_pop34_stall_in = 1'b0;
assign rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG = rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_1_0_push34_rows_0_0_pop35_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1_0_push34_rows_0_0_pop35_stall_in = 1'b0;
assign rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG = rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1_rows_3_0_push32_rows_2_0_pop33_NO_SHIFT_REG),
.data_out(rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_3_0_push32_rows_2_0_pop33_stall_in = 1'b0;
assign rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG = rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_var__u3_stall_local;
wire [7:0] local_bb1_var__u3;
assign local_bb1_var__u3 = (rnode_164to165_bb1__343_0_NO_SHIFT_REG & 8'h1);
// Register node:
// * latency = 4
// * capacity = 4
logic rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG),
.data_out(rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_fifo.DEPTH = 4;
defparam rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG = rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_170_NO_SHIFT_REG;
assign rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 4
// * capacity = 4
logic rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG),
.data_out(rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_fifo.DEPTH = 4;
defparam rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG = rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_170_NO_SHIFT_REG;
assign rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 4
// * capacity = 4
logic rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG),
.data_out(rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_fifo.DEPTH = 4;
defparam rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG = rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_170_NO_SHIFT_REG;
assign rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_4_stall_local;
wire local_bb1_cmp19_4;
assign local_bb1_cmp19_4 = (local_bb1_var__u3 == 8'h0);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to170_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to170_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to170_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__344_demorgan_stall_local;
wire local_bb1__344_demorgan;
assign local_bb1__344_demorgan = (rnode_164to165_bb1_cmp16_4_0_NO_SHIFT_REG | local_bb1_cmp19_4);
// This section implements an unregistered operation.
//
wire local_bb1__346_stall_local;
wire local_bb1__346;
assign local_bb1__346 = (local_bb1_cmp19_4 & local_bb1_not_cmp16_4);
// This section implements an unregistered operation.
//
wire local_bb1__345_stall_local;
wire [7:0] local_bb1__345;
assign local_bb1__345 = (local_bb1__344_demorgan ? 8'h1 : rnode_164to165_bb1__343_1_NO_SHIFT_REG);
// This section implements an unregistered operation.
//
wire local_bb1__347_stall_local;
wire [7:0] local_bb1__347;
assign local_bb1__347 = (local_bb1__346 ? 8'h0 : local_bb1__345);
// This section implements an unregistered operation.
//
wire local_bb1_var__u4_stall_local;
wire [7:0] local_bb1_var__u4;
assign local_bb1_var__u4 = (local_bb1__347 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_5_stall_local;
wire local_bb1_cmp19_5;
assign local_bb1_cmp19_5 = (local_bb1_var__u4 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__348_demorgan_stall_local;
wire local_bb1__348_demorgan;
assign local_bb1__348_demorgan = (rnode_164to165_bb1_cmp16_5_0_NO_SHIFT_REG | local_bb1_cmp19_5);
// This section implements an unregistered operation.
//
wire local_bb1__350_stall_local;
wire local_bb1__350;
assign local_bb1__350 = (local_bb1_cmp19_5 & local_bb1_not_cmp16_5);
// This section implements an unregistered operation.
//
wire local_bb1__349_stall_local;
wire [7:0] local_bb1__349;
assign local_bb1__349 = (local_bb1__348_demorgan ? 8'h1 : local_bb1__347);
// This section implements an unregistered operation.
//
wire local_bb1__351_stall_local;
wire [7:0] local_bb1__351;
assign local_bb1__351 = (local_bb1__350 ? 8'h0 : local_bb1__349);
// This section implements an unregistered operation.
//
wire local_bb1_var__u5_stall_local;
wire [7:0] local_bb1_var__u5;
assign local_bb1_var__u5 = (local_bb1__351 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_6_stall_local;
wire local_bb1_cmp19_6;
assign local_bb1_cmp19_6 = (local_bb1_var__u5 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__352_demorgan_stall_local;
wire local_bb1__352_demorgan;
assign local_bb1__352_demorgan = (local_bb1_cmp16_6 | local_bb1_cmp19_6);
// This section implements an unregistered operation.
//
wire local_bb1__354_stall_local;
wire local_bb1__354;
assign local_bb1__354 = (local_bb1_cmp19_6 & local_bb1_not_cmp16_6);
// This section implements an unregistered operation.
//
wire local_bb1__353_stall_local;
wire [7:0] local_bb1__353;
assign local_bb1__353 = (local_bb1__352_demorgan ? 8'h1 : local_bb1__351);
// This section implements an unregistered operation.
//
wire local_bb1__355_stall_local;
wire [7:0] local_bb1__355;
assign local_bb1__355 = (local_bb1__354 ? 8'h0 : local_bb1__353);
// This section implements an unregistered operation.
//
wire local_bb1_var__u6_stall_local;
wire [7:0] local_bb1_var__u6;
assign local_bb1_var__u6 = (local_bb1__355 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_7_stall_local;
wire local_bb1_cmp19_7;
assign local_bb1_cmp19_7 = (local_bb1_var__u6 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__356_demorgan_stall_local;
wire local_bb1__356_demorgan;
assign local_bb1__356_demorgan = (local_bb1_cmp16_7 | local_bb1_cmp19_7);
// This section implements an unregistered operation.
//
wire local_bb1__358_stall_local;
wire local_bb1__358;
assign local_bb1__358 = (local_bb1_cmp19_7 & local_bb1_not_cmp16_7);
// This section implements an unregistered operation.
//
wire local_bb1__357_stall_local;
wire [7:0] local_bb1__357;
assign local_bb1__357 = (local_bb1__356_demorgan ? 8'h1 : local_bb1__355);
// This section implements an unregistered operation.
//
wire local_bb1__359_stall_local;
wire [7:0] local_bb1__359;
assign local_bb1__359 = (local_bb1__358 ? 8'h0 : local_bb1__357);
// This section implements an unregistered operation.
//
wire local_bb1_var__u7_stall_local;
wire [7:0] local_bb1_var__u7;
assign local_bb1_var__u7 = (local_bb1__359 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_8_stall_local;
wire local_bb1_cmp19_8;
assign local_bb1_cmp19_8 = (local_bb1_var__u7 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__360_demorgan_stall_local;
wire local_bb1__360_demorgan;
assign local_bb1__360_demorgan = (local_bb1_cmp16_8 | local_bb1_cmp19_8);
// This section implements an unregistered operation.
//
wire local_bb1__362_stall_local;
wire local_bb1__362;
assign local_bb1__362 = (local_bb1_cmp19_8 & local_bb1_not_cmp16_8);
// This section implements an unregistered operation.
//
wire local_bb1__361_stall_local;
wire [7:0] local_bb1__361;
assign local_bb1__361 = (local_bb1__360_demorgan ? 8'h1 : local_bb1__359);
// This section implements an unregistered operation.
//
wire local_bb1__363_stall_local;
wire [7:0] local_bb1__363;
assign local_bb1__363 = (local_bb1__362 ? 8'h0 : local_bb1__361);
// This section implements an unregistered operation.
//
wire local_bb1_var__u8_stall_local;
wire [7:0] local_bb1_var__u8;
assign local_bb1_var__u8 = (local_bb1__363 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_9_stall_local;
wire local_bb1_cmp19_9;
assign local_bb1_cmp19_9 = (local_bb1_var__u8 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__364_demorgan_stall_local;
wire local_bb1__364_demorgan;
assign local_bb1__364_demorgan = (local_bb1_cmp16_9 | local_bb1_cmp19_9);
// This section implements an unregistered operation.
//
wire local_bb1__366_stall_local;
wire local_bb1__366;
assign local_bb1__366 = (local_bb1_cmp19_9 & local_bb1_not_cmp16_9);
// This section implements an unregistered operation.
//
wire local_bb1__365_stall_local;
wire [7:0] local_bb1__365;
assign local_bb1__365 = (local_bb1__364_demorgan ? 8'h1 : local_bb1__363);
// This section implements an unregistered operation.
//
wire local_bb1__367_stall_local;
wire [7:0] local_bb1__367;
assign local_bb1__367 = (local_bb1__366 ? 8'h0 : local_bb1__365);
// This section implements an unregistered operation.
//
wire local_bb1_var__u9_stall_local;
wire [7:0] local_bb1_var__u9;
assign local_bb1_var__u9 = (local_bb1__367 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_10_stall_local;
wire local_bb1_cmp19_10;
assign local_bb1_cmp19_10 = (local_bb1_var__u9 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__368_demorgan_stall_local;
wire local_bb1__368_demorgan;
assign local_bb1__368_demorgan = (local_bb1_cmp16_10 | local_bb1_cmp19_10);
// This section implements an unregistered operation.
//
wire local_bb1__370_stall_local;
wire local_bb1__370;
assign local_bb1__370 = (local_bb1_cmp19_10 & local_bb1_not_cmp16_10);
// This section implements an unregistered operation.
//
wire local_bb1__369_stall_local;
wire [7:0] local_bb1__369;
assign local_bb1__369 = (local_bb1__368_demorgan ? 8'h1 : local_bb1__367);
// This section implements an unregistered operation.
//
wire local_bb1__371_stall_local;
wire [7:0] local_bb1__371;
assign local_bb1__371 = (local_bb1__370 ? 8'h0 : local_bb1__369);
// This section implements an unregistered operation.
//
wire local_bb1_var__u10_stall_local;
wire [7:0] local_bb1_var__u10;
assign local_bb1_var__u10 = (local_bb1__371 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_11_stall_local;
wire local_bb1_cmp19_11;
assign local_bb1_cmp19_11 = (local_bb1_var__u10 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__372_demorgan_stall_local;
wire local_bb1__372_demorgan;
assign local_bb1__372_demorgan = (local_bb1_cmp16_11 | local_bb1_cmp19_11);
// This section implements an unregistered operation.
//
wire local_bb1_rows_7_0_pop28__valid_out_0;
wire local_bb1_rows_7_0_pop28__stall_in_0;
reg local_bb1_rows_7_0_pop28__consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_8_0_pop27__valid_out_0;
wire local_bb1_rows_8_0_pop27__stall_in_0;
reg local_bb1_rows_8_0_pop27__consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_9_0_pop26__valid_out_0;
wire local_bb1_rows_9_0_pop26__stall_in_0;
reg local_bb1_rows_9_0_pop26__consumed_0_NO_SHIFT_REG;
wire local_bb1__371_valid_out_1;
wire local_bb1__371_stall_in_1;
reg local_bb1__371_consumed_1_NO_SHIFT_REG;
wire local_bb1_rows_6_0_pop29__valid_out_0;
wire local_bb1_rows_6_0_pop29__stall_in_0;
reg local_bb1_rows_6_0_pop29__consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_10_0_pop25__valid_out_0;
wire local_bb1_rows_10_0_pop25__stall_in_0;
reg local_bb1_rows_10_0_pop25__consumed_0_NO_SHIFT_REG;
wire local_bb1__372_demorgan_valid_out;
wire local_bb1__372_demorgan_stall_in;
reg local_bb1__372_demorgan_consumed_0_NO_SHIFT_REG;
wire local_bb1__374_valid_out;
wire local_bb1__374_stall_in;
reg local_bb1__374_consumed_0_NO_SHIFT_REG;
wire local_bb1__374_inputs_ready;
wire local_bb1__374_stall_local;
wire local_bb1__374;
assign local_bb1__374_inputs_ready = (rnode_164to165_bb1_c0_ene1_0_valid_out_0_NO_SHIFT_REG & rnode_164to165_bb1_c0_ene1_0_valid_out_1_NO_SHIFT_REG & rnode_164to165_bb1_c0_ene1_0_valid_out_2_NO_SHIFT_REG & rnode_164to165_bb1_c0_ene1_0_valid_out_11_NO_SHIFT_REG & rnode_164to165_bb1_rows_5_0_pop30__0_valid_out_1_NO_SHIFT_REG & rnode_164to165_bb1_cmp16_4_0_valid_out_0_NO_SHIFT_REG & rnode_164to165_bb1__343_0_valid_out_1_NO_SHIFT_REG & rnode_164to165_bb1_cmp16_4_0_valid_out_1_NO_SHIFT_REG & rnode_164to165_bb1_cmp16_5_0_valid_out_0_NO_SHIFT_REG & rnode_164to165_bb1_cmp16_5_0_valid_out_1_NO_SHIFT_REG & rnode_164to165_bb1__343_0_valid_out_0_NO_SHIFT_REG & rnode_164to165_bb1_c0_ene1_0_valid_out_10_NO_SHIFT_REG);
assign local_bb1__374 = (local_bb1_cmp19_11 & local_bb1_not_cmp16_11);
assign local_bb1_rows_7_0_pop28__valid_out_0 = 1'b1;
assign local_bb1_rows_8_0_pop27__valid_out_0 = 1'b1;
assign local_bb1_rows_9_0_pop26__valid_out_0 = 1'b1;
assign local_bb1__371_valid_out_1 = 1'b1;
assign local_bb1_rows_6_0_pop29__valid_out_0 = 1'b1;
assign local_bb1_rows_10_0_pop25__valid_out_0 = 1'b1;
assign local_bb1__372_demorgan_valid_out = 1'b1;
assign local_bb1__374_valid_out = 1'b1;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_11_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_rows_5_0_pop30__0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_cmp16_4_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1__343_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_cmp16_4_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_cmp16_5_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_cmp16_5_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1__343_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_c0_ene1_0_stall_in_10_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_7_0_pop28__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_8_0_pop27__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_9_0_pop26__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__371_consumed_1_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_6_0_pop29__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_10_0_pop25__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__372_demorgan_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__374_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_7_0_pop28__consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1_rows_7_0_pop28__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_7_0_pop28__stall_in_0)) & local_bb1__374_stall_local);
local_bb1_rows_8_0_pop27__consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1_rows_8_0_pop27__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_8_0_pop27__stall_in_0)) & local_bb1__374_stall_local);
local_bb1_rows_9_0_pop26__consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1_rows_9_0_pop26__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_9_0_pop26__stall_in_0)) & local_bb1__374_stall_local);
local_bb1__371_consumed_1_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1__371_consumed_1_NO_SHIFT_REG | ~(local_bb1__371_stall_in_1)) & local_bb1__374_stall_local);
local_bb1_rows_6_0_pop29__consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1_rows_6_0_pop29__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_6_0_pop29__stall_in_0)) & local_bb1__374_stall_local);
local_bb1_rows_10_0_pop25__consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1_rows_10_0_pop25__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_10_0_pop25__stall_in_0)) & local_bb1__374_stall_local);
local_bb1__372_demorgan_consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1__372_demorgan_consumed_0_NO_SHIFT_REG | ~(local_bb1__372_demorgan_stall_in)) & local_bb1__374_stall_local);
local_bb1__374_consumed_0_NO_SHIFT_REG <= (local_bb1__374_inputs_ready & (local_bb1__374_consumed_0_NO_SHIFT_REG | ~(local_bb1__374_stall_in)) & local_bb1__374_stall_local);
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_8_0_push27_rows_7_0_pop28_inputs_ready;
reg local_bb1_rows_8_0_push27_rows_7_0_pop28_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_8_0_push27_rows_7_0_pop28_stall_in;
wire local_bb1_rows_8_0_push27_rows_7_0_pop28_output_regs_ready;
wire [7:0] local_bb1_rows_8_0_push27_rows_7_0_pop28_result;
wire local_bb1_rows_8_0_push27_rows_7_0_pop28_fu_valid_out;
wire local_bb1_rows_8_0_push27_rows_7_0_pop28_fu_stall_out;
reg [7:0] local_bb1_rows_8_0_push27_rows_7_0_pop28_NO_SHIFT_REG;
wire local_bb1_rows_8_0_push27_rows_7_0_pop28_causedstall;
acl_push local_bb1_rows_8_0_push27_rows_7_0_pop28_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_2_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_7_0_pop28_),
.stall_out(local_bb1_rows_8_0_push27_rows_7_0_pop28_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_8_0_push27_rows_7_0_pop28_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_8_0_push27_rows_7_0_pop28_result),
.feedback_out(feedback_data_out_27),
.feedback_valid_out(feedback_valid_out_27),
.feedback_stall_in(feedback_stall_in_27)
);
defparam local_bb1_rows_8_0_push27_rows_7_0_pop28_feedback.STALLFREE = 1;
defparam local_bb1_rows_8_0_push27_rows_7_0_pop28_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_8_0_push27_rows_7_0_pop28_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_8_0_push27_rows_7_0_pop28_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_8_0_push27_rows_7_0_pop28_feedback.STYLE = "REGULAR";
assign local_bb1_rows_8_0_push27_rows_7_0_pop28_inputs_ready = 1'b1;
assign local_bb1_rows_8_0_push27_rows_7_0_pop28_output_regs_ready = 1'b1;
assign local_bb1_rows_7_0_pop28__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_8_0_push27_rows_7_0_pop28_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_8_0_push27_rows_7_0_pop28_NO_SHIFT_REG <= 'x;
local_bb1_rows_8_0_push27_rows_7_0_pop28_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_8_0_push27_rows_7_0_pop28_output_regs_ready)
begin
local_bb1_rows_8_0_push27_rows_7_0_pop28_NO_SHIFT_REG <= local_bb1_rows_8_0_push27_rows_7_0_pop28_result;
local_bb1_rows_8_0_push27_rows_7_0_pop28_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_8_0_push27_rows_7_0_pop28_stall_in))
begin
local_bb1_rows_8_0_push27_rows_7_0_pop28_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_9_0_push26_rows_8_0_pop27_inputs_ready;
reg local_bb1_rows_9_0_push26_rows_8_0_pop27_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_9_0_push26_rows_8_0_pop27_stall_in;
wire local_bb1_rows_9_0_push26_rows_8_0_pop27_output_regs_ready;
wire [7:0] local_bb1_rows_9_0_push26_rows_8_0_pop27_result;
wire local_bb1_rows_9_0_push26_rows_8_0_pop27_fu_valid_out;
wire local_bb1_rows_9_0_push26_rows_8_0_pop27_fu_stall_out;
reg [7:0] local_bb1_rows_9_0_push26_rows_8_0_pop27_NO_SHIFT_REG;
wire local_bb1_rows_9_0_push26_rows_8_0_pop27_causedstall;
acl_push local_bb1_rows_9_0_push26_rows_8_0_pop27_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_8_0_pop27_),
.stall_out(local_bb1_rows_9_0_push26_rows_8_0_pop27_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_9_0_push26_rows_8_0_pop27_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_9_0_push26_rows_8_0_pop27_result),
.feedback_out(feedback_data_out_26),
.feedback_valid_out(feedback_valid_out_26),
.feedback_stall_in(feedback_stall_in_26)
);
defparam local_bb1_rows_9_0_push26_rows_8_0_pop27_feedback.STALLFREE = 1;
defparam local_bb1_rows_9_0_push26_rows_8_0_pop27_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_9_0_push26_rows_8_0_pop27_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_9_0_push26_rows_8_0_pop27_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_9_0_push26_rows_8_0_pop27_feedback.STYLE = "REGULAR";
assign local_bb1_rows_9_0_push26_rows_8_0_pop27_inputs_ready = 1'b1;
assign local_bb1_rows_9_0_push26_rows_8_0_pop27_output_regs_ready = 1'b1;
assign local_bb1_rows_8_0_pop27__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_9_0_push26_rows_8_0_pop27_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_9_0_push26_rows_8_0_pop27_NO_SHIFT_REG <= 'x;
local_bb1_rows_9_0_push26_rows_8_0_pop27_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_9_0_push26_rows_8_0_pop27_output_regs_ready)
begin
local_bb1_rows_9_0_push26_rows_8_0_pop27_NO_SHIFT_REG <= local_bb1_rows_9_0_push26_rows_8_0_pop27_result;
local_bb1_rows_9_0_push26_rows_8_0_pop27_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_9_0_push26_rows_8_0_pop27_stall_in))
begin
local_bb1_rows_9_0_push26_rows_8_0_pop27_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_10_0_push25_rows_9_0_pop26_inputs_ready;
reg local_bb1_rows_10_0_push25_rows_9_0_pop26_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_10_0_push25_rows_9_0_pop26_stall_in;
wire local_bb1_rows_10_0_push25_rows_9_0_pop26_output_regs_ready;
wire [7:0] local_bb1_rows_10_0_push25_rows_9_0_pop26_result;
wire local_bb1_rows_10_0_push25_rows_9_0_pop26_fu_valid_out;
wire local_bb1_rows_10_0_push25_rows_9_0_pop26_fu_stall_out;
reg [7:0] local_bb1_rows_10_0_push25_rows_9_0_pop26_NO_SHIFT_REG;
wire local_bb1_rows_10_0_push25_rows_9_0_pop26_causedstall;
acl_push local_bb1_rows_10_0_push25_rows_9_0_pop26_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_9_0_pop26_),
.stall_out(local_bb1_rows_10_0_push25_rows_9_0_pop26_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_10_0_push25_rows_9_0_pop26_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_10_0_push25_rows_9_0_pop26_result),
.feedback_out(feedback_data_out_25),
.feedback_valid_out(feedback_valid_out_25),
.feedback_stall_in(feedback_stall_in_25)
);
defparam local_bb1_rows_10_0_push25_rows_9_0_pop26_feedback.STALLFREE = 1;
defparam local_bb1_rows_10_0_push25_rows_9_0_pop26_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_10_0_push25_rows_9_0_pop26_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_10_0_push25_rows_9_0_pop26_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_10_0_push25_rows_9_0_pop26_feedback.STYLE = "REGULAR";
assign local_bb1_rows_10_0_push25_rows_9_0_pop26_inputs_ready = 1'b1;
assign local_bb1_rows_10_0_push25_rows_9_0_pop26_output_regs_ready = 1'b1;
assign local_bb1_rows_9_0_pop26__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_10_0_push25_rows_9_0_pop26_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_10_0_push25_rows_9_0_pop26_NO_SHIFT_REG <= 'x;
local_bb1_rows_10_0_push25_rows_9_0_pop26_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_10_0_push25_rows_9_0_pop26_output_regs_ready)
begin
local_bb1_rows_10_0_push25_rows_9_0_pop26_NO_SHIFT_REG <= local_bb1_rows_10_0_push25_rows_9_0_pop26_result;
local_bb1_rows_10_0_push25_rows_9_0_pop26_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_10_0_push25_rows_9_0_pop26_stall_in))
begin
local_bb1_rows_10_0_push25_rows_9_0_pop26_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1__371_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1__371_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1__371_0_NO_SHIFT_REG;
logic rnode_165to166_bb1__371_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_165to166_bb1__371_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__371_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__371_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__371_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1__371_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1__371_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1__371_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1__371_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1__371_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1__371),
.data_out(rnode_165to166_bb1__371_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1__371_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1__371_0_reg_166_fifo.DATA_WIDTH = 8;
defparam rnode_165to166_bb1__371_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1__371_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1__371_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__371_stall_in_1 = 1'b0;
assign rnode_165to166_bb1__371_0_NO_SHIFT_REG = rnode_165to166_bb1__371_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1__371_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__371_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements a registered operation.
//
wire local_bb1_rows_7_0_push28_rows_6_0_pop29_inputs_ready;
reg local_bb1_rows_7_0_push28_rows_6_0_pop29_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_7_0_push28_rows_6_0_pop29_stall_in;
wire local_bb1_rows_7_0_push28_rows_6_0_pop29_output_regs_ready;
wire [7:0] local_bb1_rows_7_0_push28_rows_6_0_pop29_result;
wire local_bb1_rows_7_0_push28_rows_6_0_pop29_fu_valid_out;
wire local_bb1_rows_7_0_push28_rows_6_0_pop29_fu_stall_out;
reg [7:0] local_bb1_rows_7_0_push28_rows_6_0_pop29_NO_SHIFT_REG;
wire local_bb1_rows_7_0_push28_rows_6_0_pop29_causedstall;
acl_push local_bb1_rows_7_0_push28_rows_6_0_pop29_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_0_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_6_0_pop29_),
.stall_out(local_bb1_rows_7_0_push28_rows_6_0_pop29_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_7_0_push28_rows_6_0_pop29_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_7_0_push28_rows_6_0_pop29_result),
.feedback_out(feedback_data_out_28),
.feedback_valid_out(feedback_valid_out_28),
.feedback_stall_in(feedback_stall_in_28)
);
defparam local_bb1_rows_7_0_push28_rows_6_0_pop29_feedback.STALLFREE = 1;
defparam local_bb1_rows_7_0_push28_rows_6_0_pop29_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_7_0_push28_rows_6_0_pop29_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_7_0_push28_rows_6_0_pop29_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_7_0_push28_rows_6_0_pop29_feedback.STYLE = "REGULAR";
assign local_bb1_rows_7_0_push28_rows_6_0_pop29_inputs_ready = 1'b1;
assign local_bb1_rows_7_0_push28_rows_6_0_pop29_output_regs_ready = 1'b1;
assign local_bb1_rows_6_0_pop29__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_7_0_push28_rows_6_0_pop29_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_7_0_push28_rows_6_0_pop29_NO_SHIFT_REG <= 'x;
local_bb1_rows_7_0_push28_rows_6_0_pop29_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_7_0_push28_rows_6_0_pop29_output_regs_ready)
begin
local_bb1_rows_7_0_push28_rows_6_0_pop29_NO_SHIFT_REG <= local_bb1_rows_7_0_push28_rows_6_0_pop29_result;
local_bb1_rows_7_0_push28_rows_6_0_pop29_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_7_0_push28_rows_6_0_pop29_stall_in))
begin
local_bb1_rows_7_0_push28_rows_6_0_pop29_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_11_0_push24_rows_10_0_pop25_inputs_ready;
reg local_bb1_rows_11_0_push24_rows_10_0_pop25_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_11_0_push24_rows_10_0_pop25_stall_in;
wire local_bb1_rows_11_0_push24_rows_10_0_pop25_output_regs_ready;
wire [7:0] local_bb1_rows_11_0_push24_rows_10_0_pop25_result;
wire local_bb1_rows_11_0_push24_rows_10_0_pop25_fu_valid_out;
wire local_bb1_rows_11_0_push24_rows_10_0_pop25_fu_stall_out;
reg [7:0] local_bb1_rows_11_0_push24_rows_10_0_pop25_NO_SHIFT_REG;
wire local_bb1_rows_11_0_push24_rows_10_0_pop25_causedstall;
acl_push local_bb1_rows_11_0_push24_rows_10_0_pop25_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_164to165_bb1_c0_ene2_6_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_10_0_pop25_),
.stall_out(local_bb1_rows_11_0_push24_rows_10_0_pop25_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[3]),
.valid_out(local_bb1_rows_11_0_push24_rows_10_0_pop25_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_11_0_push24_rows_10_0_pop25_result),
.feedback_out(feedback_data_out_24),
.feedback_valid_out(feedback_valid_out_24),
.feedback_stall_in(feedback_stall_in_24)
);
defparam local_bb1_rows_11_0_push24_rows_10_0_pop25_feedback.STALLFREE = 1;
defparam local_bb1_rows_11_0_push24_rows_10_0_pop25_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_11_0_push24_rows_10_0_pop25_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_11_0_push24_rows_10_0_pop25_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_11_0_push24_rows_10_0_pop25_feedback.STYLE = "REGULAR";
assign local_bb1_rows_11_0_push24_rows_10_0_pop25_inputs_ready = 1'b1;
assign local_bb1_rows_11_0_push24_rows_10_0_pop25_output_regs_ready = 1'b1;
assign local_bb1_rows_10_0_pop25__stall_in_0 = 1'b0;
assign rnode_164to165_bb1_c0_ene2_0_stall_in_6_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_11_0_push24_rows_10_0_pop25_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[3] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_11_0_push24_rows_10_0_pop25_NO_SHIFT_REG <= 'x;
local_bb1_rows_11_0_push24_rows_10_0_pop25_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_11_0_push24_rows_10_0_pop25_output_regs_ready)
begin
local_bb1_rows_11_0_push24_rows_10_0_pop25_NO_SHIFT_REG <= local_bb1_rows_11_0_push24_rows_10_0_pop25_result;
local_bb1_rows_11_0_push24_rows_10_0_pop25_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_11_0_push24_rows_10_0_pop25_stall_in))
begin
local_bb1_rows_11_0_push24_rows_10_0_pop25_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1__372_demorgan_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_stall_in_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__372_demorgan_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1__372_demorgan_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1__372_demorgan_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1__372_demorgan_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1__372_demorgan_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1__372_demorgan_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1__372_demorgan),
.data_out(rnode_165to166_bb1__372_demorgan_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1__372_demorgan_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1__372_demorgan_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1__372_demorgan_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1__372_demorgan_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1__372_demorgan_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__372_demorgan_stall_in = 1'b0;
assign rnode_165to166_bb1__372_demorgan_0_NO_SHIFT_REG = rnode_165to166_bb1__372_demorgan_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1__372_demorgan_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__372_demorgan_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_165to166_bb1__374_0_valid_out_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_stall_in_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_reg_166_inputs_ready_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_valid_out_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_stall_in_reg_166_NO_SHIFT_REG;
logic rnode_165to166_bb1__374_0_stall_out_reg_166_NO_SHIFT_REG;
acl_data_fifo rnode_165to166_bb1__374_0_reg_166_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_165to166_bb1__374_0_reg_166_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_165to166_bb1__374_0_stall_in_reg_166_NO_SHIFT_REG),
.valid_out(rnode_165to166_bb1__374_0_valid_out_reg_166_NO_SHIFT_REG),
.stall_out(rnode_165to166_bb1__374_0_stall_out_reg_166_NO_SHIFT_REG),
.data_in(local_bb1__374),
.data_out(rnode_165to166_bb1__374_0_reg_166_NO_SHIFT_REG)
);
defparam rnode_165to166_bb1__374_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1__374_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1__374_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1__374_0_reg_166_fifo.IMPL = "shift_reg";
assign rnode_165to166_bb1__374_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__374_stall_in = 1'b0;
assign rnode_165to166_bb1__374_0_NO_SHIFT_REG = rnode_165to166_bb1__374_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1__374_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__374_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_8_0_push27_rows_7_0_pop28_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_8_0_push27_rows_7_0_pop28_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_9_0_push26_rows_8_0_pop27_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_9_0_push26_rows_8_0_pop27_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_10_0_push25_rows_9_0_pop26_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_10_0_push25_rows_9_0_pop26_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_7_0_push28_rows_6_0_pop29_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_7_0_push28_rows_6_0_pop29_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1_rows_11_0_push24_rows_10_0_pop25_NO_SHIFT_REG),
.data_out(rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_11_0_push24_rows_10_0_pop25_stall_in = 1'b0;
assign rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG = rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__373_stall_local;
wire [7:0] local_bb1__373;
assign local_bb1__373 = (rnode_165to166_bb1__372_demorgan_0_NO_SHIFT_REG ? 8'h1 : rnode_165to166_bb1__371_0_NO_SHIFT_REG);
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 3
// * capacity = 3
logic rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG),
.data_out(rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_fifo.DEPTH = 3;
defparam rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG = rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_170_NO_SHIFT_REG;
assign rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__375_stall_local;
wire [7:0] local_bb1__375;
assign local_bb1__375 = (rnode_165to166_bb1__374_0_NO_SHIFT_REG ? 8'h0 : local_bb1__373);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_167to170_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_var__u11_stall_local;
wire [7:0] local_bb1_var__u11;
assign local_bb1_var__u11 = (local_bb1__375 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_12_stall_local;
wire local_bb1_cmp19_12;
assign local_bb1_cmp19_12 = (local_bb1_var__u11 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__376_demorgan_stall_local;
wire local_bb1__376_demorgan;
assign local_bb1__376_demorgan = (rnode_165to166_bb1_cmp16_12_0_NO_SHIFT_REG | local_bb1_cmp19_12);
// This section implements an unregistered operation.
//
wire local_bb1__378_stall_local;
wire local_bb1__378;
assign local_bb1__378 = (local_bb1_cmp19_12 & local_bb1_not_cmp16_12);
// This section implements an unregistered operation.
//
wire local_bb1__377_stall_local;
wire [7:0] local_bb1__377;
assign local_bb1__377 = (local_bb1__376_demorgan ? 8'h1 : local_bb1__375);
// This section implements an unregistered operation.
//
wire local_bb1__379_stall_local;
wire [7:0] local_bb1__379;
assign local_bb1__379 = (local_bb1__378 ? 8'h0 : local_bb1__377);
// This section implements an unregistered operation.
//
wire local_bb1_var__u12_stall_local;
wire [7:0] local_bb1_var__u12;
assign local_bb1_var__u12 = (local_bb1__379 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_13_stall_local;
wire local_bb1_cmp19_13;
assign local_bb1_cmp19_13 = (local_bb1_var__u12 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__380_demorgan_stall_local;
wire local_bb1__380_demorgan;
assign local_bb1__380_demorgan = (rnode_165to166_bb1_cmp16_13_0_NO_SHIFT_REG | local_bb1_cmp19_13);
// This section implements an unregistered operation.
//
wire local_bb1__382_stall_local;
wire local_bb1__382;
assign local_bb1__382 = (local_bb1_cmp19_13 & local_bb1_not_cmp16_13);
// This section implements an unregistered operation.
//
wire local_bb1__381_stall_local;
wire [7:0] local_bb1__381;
assign local_bb1__381 = (local_bb1__380_demorgan ? 8'h1 : local_bb1__379);
// This section implements an unregistered operation.
//
wire local_bb1__383_stall_local;
wire [7:0] local_bb1__383;
assign local_bb1__383 = (local_bb1__382 ? 8'h0 : local_bb1__381);
// This section implements an unregistered operation.
//
wire local_bb1_var__u13_stall_local;
wire [7:0] local_bb1_var__u13;
assign local_bb1_var__u13 = (local_bb1__383 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_14_stall_local;
wire local_bb1_cmp19_14;
assign local_bb1_cmp19_14 = (local_bb1_var__u13 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__384_demorgan_stall_local;
wire local_bb1__384_demorgan;
assign local_bb1__384_demorgan = (rnode_165to166_bb1_cmp16_14_0_NO_SHIFT_REG | local_bb1_cmp19_14);
// This section implements an unregistered operation.
//
wire local_bb1__386_stall_local;
wire local_bb1__386;
assign local_bb1__386 = (local_bb1_cmp19_14 & local_bb1_not_cmp16_14);
// This section implements an unregistered operation.
//
wire local_bb1__385_stall_local;
wire [7:0] local_bb1__385;
assign local_bb1__385 = (local_bb1__384_demorgan ? 8'h1 : local_bb1__383);
// This section implements an unregistered operation.
//
wire local_bb1__387_stall_local;
wire [7:0] local_bb1__387;
assign local_bb1__387 = (local_bb1__386 ? 8'h0 : local_bb1__385);
// This section implements an unregistered operation.
//
wire local_bb1_var__u14_stall_local;
wire [7:0] local_bb1_var__u14;
assign local_bb1_var__u14 = (local_bb1__387 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_15_stall_local;
wire local_bb1_cmp19_15;
assign local_bb1_cmp19_15 = (local_bb1_var__u14 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__388_demorgan_stall_local;
wire local_bb1__388_demorgan;
assign local_bb1__388_demorgan = (rnode_165to166_bb1_cmp16_15_0_NO_SHIFT_REG | local_bb1_cmp19_15);
// This section implements an unregistered operation.
//
wire local_bb1__390_stall_local;
wire local_bb1__390;
assign local_bb1__390 = (local_bb1_cmp19_15 & local_bb1_not_cmp16_15);
// This section implements an unregistered operation.
//
wire local_bb1__389_stall_local;
wire [7:0] local_bb1__389;
assign local_bb1__389 = (local_bb1__388_demorgan ? 8'h1 : local_bb1__387);
// This section implements an unregistered operation.
//
wire local_bb1__391_stall_local;
wire [7:0] local_bb1__391;
assign local_bb1__391 = (local_bb1__390 ? 8'h0 : local_bb1__389);
// This section implements an unregistered operation.
//
wire local_bb1_var__u15_stall_local;
wire [7:0] local_bb1_var__u15;
assign local_bb1_var__u15 = (local_bb1__391 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_16_stall_local;
wire local_bb1_cmp19_16;
assign local_bb1_cmp19_16 = (local_bb1_var__u15 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__392_demorgan_stall_local;
wire local_bb1__392_demorgan;
assign local_bb1__392_demorgan = (rnode_165to166_bb1_cmp16_16_0_NO_SHIFT_REG | local_bb1_cmp19_16);
// This section implements an unregistered operation.
//
wire local_bb1__394_stall_local;
wire local_bb1__394;
assign local_bb1__394 = (local_bb1_cmp19_16 & local_bb1_not_cmp16_16);
// This section implements an unregistered operation.
//
wire local_bb1__393_stall_local;
wire [7:0] local_bb1__393;
assign local_bb1__393 = (local_bb1__392_demorgan ? 8'h1 : local_bb1__391);
// This section implements an unregistered operation.
//
wire local_bb1__395_stall_local;
wire [7:0] local_bb1__395;
assign local_bb1__395 = (local_bb1__394 ? 8'h0 : local_bb1__393);
// This section implements an unregistered operation.
//
wire local_bb1_var__u16_stall_local;
wire [7:0] local_bb1_var__u16;
assign local_bb1_var__u16 = (local_bb1__395 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_122_stall_local;
wire local_bb1_cmp19_122;
assign local_bb1_cmp19_122 = (local_bb1_var__u16 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__396_demorgan_stall_local;
wire local_bb1__396_demorgan;
assign local_bb1__396_demorgan = (rnode_165to166_bb1_cmp16_121_0_NO_SHIFT_REG | local_bb1_cmp19_122);
// This section implements an unregistered operation.
//
wire local_bb1__398_stall_local;
wire local_bb1__398;
assign local_bb1__398 = (local_bb1_cmp19_122 & local_bb1_not_cmp16_121);
// This section implements an unregistered operation.
//
wire local_bb1__397_stall_local;
wire [7:0] local_bb1__397;
assign local_bb1__397 = (local_bb1__396_demorgan ? 8'h1 : local_bb1__395);
// This section implements an unregistered operation.
//
wire local_bb1__399_stall_local;
wire [7:0] local_bb1__399;
assign local_bb1__399 = (local_bb1__398 ? 8'h0 : local_bb1__397);
// This section implements an unregistered operation.
//
wire local_bb1_var__u17_stall_local;
wire [7:0] local_bb1_var__u17;
assign local_bb1_var__u17 = (local_bb1__399 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_1_1_stall_local;
wire local_bb1_cmp19_1_1;
assign local_bb1_cmp19_1_1 = (local_bb1_var__u17 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__400_demorgan_stall_local;
wire local_bb1__400_demorgan;
assign local_bb1__400_demorgan = (local_bb1_cmp16_1_1 | local_bb1_cmp19_1_1);
// This section implements an unregistered operation.
//
wire local_bb1__402_stall_local;
wire local_bb1__402;
assign local_bb1__402 = (local_bb1_cmp19_1_1 & local_bb1_not_cmp16_1_1);
// This section implements an unregistered operation.
//
wire local_bb1__401_valid_out;
wire local_bb1__401_stall_in;
reg local_bb1__401_consumed_0_NO_SHIFT_REG;
wire local_bb1__402_valid_out;
wire local_bb1__402_stall_in;
reg local_bb1__402_consumed_0_NO_SHIFT_REG;
wire local_bb1__401_inputs_ready;
wire local_bb1__401_stall_local;
wire [7:0] local_bb1__401;
assign local_bb1__401_inputs_ready = (rnode_165to166_bb1_rows_1920_0_pop19__0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_16_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_16_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_15_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_15_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_14_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_14_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_13_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_13_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_12_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_12_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_121_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1__372_demorgan_0_valid_out_NO_SHIFT_REG & rnode_165to166_bb1__371_0_valid_out_NO_SHIFT_REG & rnode_165to166_bb1__374_0_valid_out_NO_SHIFT_REG & rnode_165to166_bb1_cmp16_121_0_valid_out_1_NO_SHIFT_REG);
assign local_bb1__401 = (local_bb1__400_demorgan ? 8'h1 : local_bb1__399);
assign local_bb1__401_valid_out = 1'b1;
assign local_bb1__402_valid_out = 1'b1;
assign rnode_165to166_bb1_rows_1920_0_pop19__0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_16_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_16_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_15_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_15_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_14_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_14_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_13_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_13_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_12_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_12_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_121_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__372_demorgan_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__371_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__374_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_cmp16_121_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__401_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__402_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__401_consumed_0_NO_SHIFT_REG <= (local_bb1__401_inputs_ready & (local_bb1__401_consumed_0_NO_SHIFT_REG | ~(local_bb1__401_stall_in)) & local_bb1__401_stall_local);
local_bb1__402_consumed_0_NO_SHIFT_REG <= (local_bb1__401_inputs_ready & (local_bb1__402_consumed_0_NO_SHIFT_REG | ~(local_bb1__402_stall_in)) & local_bb1__401_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1__401_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1__401_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1__401_0_NO_SHIFT_REG;
logic rnode_166to167_bb1__401_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_166to167_bb1__401_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1__401_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1__401_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1__401_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1__401_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1__401_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1__401_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1__401_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1__401_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1__401),
.data_out(rnode_166to167_bb1__401_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1__401_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1__401_0_reg_167_fifo.DATA_WIDTH = 8;
defparam rnode_166to167_bb1__401_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1__401_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1__401_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__401_stall_in = 1'b0;
assign rnode_166to167_bb1__401_0_NO_SHIFT_REG = rnode_166to167_bb1__401_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1__401_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__401_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_166to167_bb1__402_0_valid_out_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_stall_in_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_reg_167_inputs_ready_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_valid_out_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_stall_in_reg_167_NO_SHIFT_REG;
logic rnode_166to167_bb1__402_0_stall_out_reg_167_NO_SHIFT_REG;
acl_data_fifo rnode_166to167_bb1__402_0_reg_167_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_166to167_bb1__402_0_reg_167_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_166to167_bb1__402_0_stall_in_reg_167_NO_SHIFT_REG),
.valid_out(rnode_166to167_bb1__402_0_valid_out_reg_167_NO_SHIFT_REG),
.stall_out(rnode_166to167_bb1__402_0_stall_out_reg_167_NO_SHIFT_REG),
.data_in(local_bb1__402),
.data_out(rnode_166to167_bb1__402_0_reg_167_NO_SHIFT_REG)
);
defparam rnode_166to167_bb1__402_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1__402_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1__402_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1__402_0_reg_167_fifo.IMPL = "shift_reg";
assign rnode_166to167_bb1__402_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__402_stall_in = 1'b0;
assign rnode_166to167_bb1__402_0_NO_SHIFT_REG = rnode_166to167_bb1__402_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1__402_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__402_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__403_stall_local;
wire [7:0] local_bb1__403;
assign local_bb1__403 = (rnode_166to167_bb1__402_0_NO_SHIFT_REG ? 8'h0 : rnode_166to167_bb1__401_0_NO_SHIFT_REG);
// This section implements an unregistered operation.
//
wire local_bb1_var__u18_stall_local;
wire [7:0] local_bb1_var__u18;
assign local_bb1_var__u18 = (local_bb1__403 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_2_1_stall_local;
wire local_bb1_cmp19_2_1;
assign local_bb1_cmp19_2_1 = (local_bb1_var__u18 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__404_demorgan_stall_local;
wire local_bb1__404_demorgan;
assign local_bb1__404_demorgan = (rnode_166to167_bb1_cmp16_2_1_0_NO_SHIFT_REG | local_bb1_cmp19_2_1);
// This section implements an unregistered operation.
//
wire local_bb1__406_stall_local;
wire local_bb1__406;
assign local_bb1__406 = (local_bb1_cmp19_2_1 & local_bb1_not_cmp16_2_1);
// This section implements an unregistered operation.
//
wire local_bb1__405_stall_local;
wire [7:0] local_bb1__405;
assign local_bb1__405 = (local_bb1__404_demorgan ? 8'h1 : local_bb1__403);
// This section implements an unregistered operation.
//
wire local_bb1__407_stall_local;
wire [7:0] local_bb1__407;
assign local_bb1__407 = (local_bb1__406 ? 8'h0 : local_bb1__405);
// This section implements an unregistered operation.
//
wire local_bb1_var__u19_stall_local;
wire [7:0] local_bb1_var__u19;
assign local_bb1_var__u19 = (local_bb1__407 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_3_1_stall_local;
wire local_bb1_cmp19_3_1;
assign local_bb1_cmp19_3_1 = (local_bb1_var__u19 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__408_demorgan_stall_local;
wire local_bb1__408_demorgan;
assign local_bb1__408_demorgan = (rnode_166to167_bb1_cmp16_3_1_0_NO_SHIFT_REG | local_bb1_cmp19_3_1);
// This section implements an unregistered operation.
//
wire local_bb1__410_stall_local;
wire local_bb1__410;
assign local_bb1__410 = (local_bb1_cmp19_3_1 & local_bb1_not_cmp16_3_1);
// This section implements an unregistered operation.
//
wire local_bb1__409_stall_local;
wire [7:0] local_bb1__409;
assign local_bb1__409 = (local_bb1__408_demorgan ? 8'h1 : local_bb1__407);
// This section implements an unregistered operation.
//
wire local_bb1__411_stall_local;
wire [7:0] local_bb1__411;
assign local_bb1__411 = (local_bb1__410 ? 8'h0 : local_bb1__409);
// This section implements an unregistered operation.
//
wire local_bb1_var__u20_stall_local;
wire [7:0] local_bb1_var__u20;
assign local_bb1_var__u20 = (local_bb1__411 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_4_1_stall_local;
wire local_bb1_cmp19_4_1;
assign local_bb1_cmp19_4_1 = (local_bb1_var__u20 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__412_demorgan_stall_local;
wire local_bb1__412_demorgan;
assign local_bb1__412_demorgan = (rnode_166to167_bb1_cmp16_4_1_0_NO_SHIFT_REG | local_bb1_cmp19_4_1);
// This section implements an unregistered operation.
//
wire local_bb1__414_stall_local;
wire local_bb1__414;
assign local_bb1__414 = (local_bb1_cmp19_4_1 & local_bb1_not_cmp16_4_1);
// This section implements an unregistered operation.
//
wire local_bb1__413_stall_local;
wire [7:0] local_bb1__413;
assign local_bb1__413 = (local_bb1__412_demorgan ? 8'h1 : local_bb1__411);
// This section implements an unregistered operation.
//
wire local_bb1__415_stall_local;
wire [7:0] local_bb1__415;
assign local_bb1__415 = (local_bb1__414 ? 8'h0 : local_bb1__413);
// This section implements an unregistered operation.
//
wire local_bb1_var__u21_stall_local;
wire [7:0] local_bb1_var__u21;
assign local_bb1_var__u21 = (local_bb1__415 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_5_1_stall_local;
wire local_bb1_cmp19_5_1;
assign local_bb1_cmp19_5_1 = (local_bb1_var__u21 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__416_demorgan_stall_local;
wire local_bb1__416_demorgan;
assign local_bb1__416_demorgan = (rnode_166to167_bb1_cmp16_5_1_0_NO_SHIFT_REG | local_bb1_cmp19_5_1);
// This section implements an unregistered operation.
//
wire local_bb1__418_stall_local;
wire local_bb1__418;
assign local_bb1__418 = (local_bb1_cmp19_5_1 & local_bb1_not_cmp16_5_1);
// This section implements an unregistered operation.
//
wire local_bb1__417_stall_local;
wire [7:0] local_bb1__417;
assign local_bb1__417 = (local_bb1__416_demorgan ? 8'h1 : local_bb1__415);
// This section implements an unregistered operation.
//
wire local_bb1__419_stall_local;
wire [7:0] local_bb1__419;
assign local_bb1__419 = (local_bb1__418 ? 8'h0 : local_bb1__417);
// This section implements an unregistered operation.
//
wire local_bb1_var__u22_stall_local;
wire [7:0] local_bb1_var__u22;
assign local_bb1_var__u22 = (local_bb1__419 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_6_1_stall_local;
wire local_bb1_cmp19_6_1;
assign local_bb1_cmp19_6_1 = (local_bb1_var__u22 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__420_demorgan_stall_local;
wire local_bb1__420_demorgan;
assign local_bb1__420_demorgan = (rnode_166to167_bb1_cmp16_6_1_0_NO_SHIFT_REG | local_bb1_cmp19_6_1);
// This section implements an unregistered operation.
//
wire local_bb1__422_stall_local;
wire local_bb1__422;
assign local_bb1__422 = (local_bb1_cmp19_6_1 & local_bb1_not_cmp16_6_1);
// This section implements an unregistered operation.
//
wire local_bb1__421_stall_local;
wire [7:0] local_bb1__421;
assign local_bb1__421 = (local_bb1__420_demorgan ? 8'h1 : local_bb1__419);
// This section implements an unregistered operation.
//
wire local_bb1__423_stall_local;
wire [7:0] local_bb1__423;
assign local_bb1__423 = (local_bb1__422 ? 8'h0 : local_bb1__421);
// This section implements an unregistered operation.
//
wire local_bb1_var__u23_stall_local;
wire [7:0] local_bb1_var__u23;
assign local_bb1_var__u23 = (local_bb1__423 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_7_1_stall_local;
wire local_bb1_cmp19_7_1;
assign local_bb1_cmp19_7_1 = (local_bb1_var__u23 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__424_demorgan_stall_local;
wire local_bb1__424_demorgan;
assign local_bb1__424_demorgan = (local_bb1_cmp16_7_1 | local_bb1_cmp19_7_1);
// This section implements an unregistered operation.
//
wire local_bb1__426_stall_local;
wire local_bb1__426;
assign local_bb1__426 = (local_bb1_cmp19_7_1 & local_bb1_not_cmp16_7_1);
// This section implements an unregistered operation.
//
wire local_bb1__425_stall_local;
wire [7:0] local_bb1__425;
assign local_bb1__425 = (local_bb1__424_demorgan ? 8'h1 : local_bb1__423);
// This section implements an unregistered operation.
//
wire local_bb1__427_stall_local;
wire [7:0] local_bb1__427;
assign local_bb1__427 = (local_bb1__426 ? 8'h0 : local_bb1__425);
// This section implements an unregistered operation.
//
wire local_bb1_var__u24_stall_local;
wire [7:0] local_bb1_var__u24;
assign local_bb1_var__u24 = (local_bb1__427 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_8_1_stall_local;
wire local_bb1_cmp19_8_1;
assign local_bb1_cmp19_8_1 = (local_bb1_var__u24 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__428_demorgan_stall_local;
wire local_bb1__428_demorgan;
assign local_bb1__428_demorgan = (local_bb1_cmp16_8_1 | local_bb1_cmp19_8_1);
// This section implements an unregistered operation.
//
wire local_bb1__430_stall_local;
wire local_bb1__430;
assign local_bb1__430 = (local_bb1_cmp19_8_1 & local_bb1_not_cmp16_8_1);
// This section implements an unregistered operation.
//
wire local_bb1__429_stall_local;
wire [7:0] local_bb1__429;
assign local_bb1__429 = (local_bb1__428_demorgan ? 8'h1 : local_bb1__427);
// This section implements an unregistered operation.
//
wire local_bb1_rows_1927_0_pop12__valid_out_0;
wire local_bb1_rows_1927_0_pop12__stall_in_0;
reg local_bb1_rows_1927_0_pop12__consumed_0_NO_SHIFT_REG;
wire local_bb1__431_valid_out;
wire local_bb1__431_stall_in;
reg local_bb1__431_consumed_0_NO_SHIFT_REG;
wire local_bb1__431_inputs_ready;
wire local_bb1__431_stall_local;
wire [7:0] local_bb1__431;
assign local_bb1__431_inputs_ready = (rnode_166to167_bb1_c0_ene1_0_valid_out_4_NO_SHIFT_REG & rnode_166to167_bb1_rows_1926_0_pop13__0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_6_1_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_6_1_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_5_1_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_5_1_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_4_1_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_4_1_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_3_1_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_3_1_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_2_1_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_cmp16_2_1_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1__402_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1__401_0_valid_out_NO_SHIFT_REG);
assign local_bb1__431 = (local_bb1__430 ? 8'h0 : local_bb1__429);
assign local_bb1_rows_1927_0_pop12__valid_out_0 = 1'b1;
assign local_bb1__431_valid_out = 1'b1;
assign rnode_166to167_bb1_c0_ene1_0_stall_in_4_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_rows_1926_0_pop13__0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_6_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_6_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_5_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_5_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_4_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_4_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_3_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_3_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_2_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp16_2_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__402_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__401_0_stall_in_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1927_0_pop12__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__431_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1927_0_pop12__consumed_0_NO_SHIFT_REG <= (local_bb1__431_inputs_ready & (local_bb1_rows_1927_0_pop12__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1927_0_pop12__stall_in_0)) & local_bb1__431_stall_local);
local_bb1__431_consumed_0_NO_SHIFT_REG <= (local_bb1__431_inputs_ready & (local_bb1__431_consumed_0_NO_SHIFT_REG | ~(local_bb1__431_stall_in)) & local_bb1__431_stall_local);
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_1928_0_push11_rows_1927_0_pop12_inputs_ready;
reg local_bb1_rows_1928_0_push11_rows_1927_0_pop12_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1928_0_push11_rows_1927_0_pop12_stall_in;
wire local_bb1_rows_1928_0_push11_rows_1927_0_pop12_output_regs_ready;
wire [7:0] local_bb1_rows_1928_0_push11_rows_1927_0_pop12_result;
wire local_bb1_rows_1928_0_push11_rows_1927_0_pop12_fu_valid_out;
wire local_bb1_rows_1928_0_push11_rows_1927_0_pop12_fu_stall_out;
reg [7:0] local_bb1_rows_1928_0_push11_rows_1927_0_pop12_NO_SHIFT_REG;
wire local_bb1_rows_1928_0_push11_rows_1927_0_pop12_causedstall;
acl_push local_bb1_rows_1928_0_push11_rows_1927_0_pop12_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_166to167_bb1_c0_ene2_1_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1927_0_pop12_),
.stall_out(local_bb1_rows_1928_0_push11_rows_1927_0_pop12_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[5]),
.valid_out(local_bb1_rows_1928_0_push11_rows_1927_0_pop12_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1928_0_push11_rows_1927_0_pop12_result),
.feedback_out(feedback_data_out_11),
.feedback_valid_out(feedback_valid_out_11),
.feedback_stall_in(feedback_stall_in_11)
);
defparam local_bb1_rows_1928_0_push11_rows_1927_0_pop12_feedback.STALLFREE = 1;
defparam local_bb1_rows_1928_0_push11_rows_1927_0_pop12_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1928_0_push11_rows_1927_0_pop12_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1928_0_push11_rows_1927_0_pop12_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1928_0_push11_rows_1927_0_pop12_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1928_0_push11_rows_1927_0_pop12_inputs_ready = 1'b1;
assign local_bb1_rows_1928_0_push11_rows_1927_0_pop12_output_regs_ready = 1'b1;
assign local_bb1_rows_1927_0_pop12__stall_in_0 = 1'b0;
assign rnode_166to167_bb1_c0_ene2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1928_0_push11_rows_1927_0_pop12_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[5] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1928_0_push11_rows_1927_0_pop12_NO_SHIFT_REG <= 'x;
local_bb1_rows_1928_0_push11_rows_1927_0_pop12_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1928_0_push11_rows_1927_0_pop12_output_regs_ready)
begin
local_bb1_rows_1928_0_push11_rows_1927_0_pop12_NO_SHIFT_REG <= local_bb1_rows_1928_0_push11_rows_1927_0_pop12_result;
local_bb1_rows_1928_0_push11_rows_1927_0_pop12_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1928_0_push11_rows_1927_0_pop12_stall_in))
begin
local_bb1_rows_1928_0_push11_rows_1927_0_pop12_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_167to168_bb1__431_0_valid_out_0_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1__431_0_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_valid_out_1_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1__431_1_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_reg_168_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_167to168_bb1__431_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_valid_out_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_stall_in_0_reg_168_NO_SHIFT_REG;
logic rnode_167to168_bb1__431_0_stall_out_reg_168_NO_SHIFT_REG;
acl_data_fifo rnode_167to168_bb1__431_0_reg_168_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_167to168_bb1__431_0_reg_168_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_167to168_bb1__431_0_stall_in_0_reg_168_NO_SHIFT_REG),
.valid_out(rnode_167to168_bb1__431_0_valid_out_0_reg_168_NO_SHIFT_REG),
.stall_out(rnode_167to168_bb1__431_0_stall_out_reg_168_NO_SHIFT_REG),
.data_in(local_bb1__431),
.data_out(rnode_167to168_bb1__431_0_reg_168_NO_SHIFT_REG)
);
defparam rnode_167to168_bb1__431_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1__431_0_reg_168_fifo.DATA_WIDTH = 8;
defparam rnode_167to168_bb1__431_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1__431_0_reg_168_fifo.IMPL = "shift_reg";
assign rnode_167to168_bb1__431_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__431_stall_in = 1'b0;
assign rnode_167to168_bb1__431_0_stall_in_0_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1__431_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1__431_0_NO_SHIFT_REG = rnode_167to168_bb1__431_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1__431_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_167to168_bb1__431_1_NO_SHIFT_REG = rnode_167to168_bb1__431_0_reg_168_NO_SHIFT_REG;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1_rows_1928_0_push11_rows_1927_0_pop12_NO_SHIFT_REG),
.data_out(rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1928_0_push11_rows_1927_0_pop12_stall_in = 1'b0;
assign rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG = rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_var__u25_stall_local;
wire [7:0] local_bb1_var__u25;
assign local_bb1_var__u25 = (rnode_167to168_bb1__431_0_NO_SHIFT_REG & 8'h1);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG),
.data_out(rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_168to169_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG = rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_9_1_stall_local;
wire local_bb1_cmp19_9_1;
assign local_bb1_cmp19_9_1 = (local_bb1_var__u25 == 8'h0);
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG),
.data_out(rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_169to170_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_NO_SHIFT_REG = rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__432_demorgan_stall_local;
wire local_bb1__432_demorgan;
assign local_bb1__432_demorgan = (rnode_167to168_bb1_cmp16_9_1_0_NO_SHIFT_REG | local_bb1_cmp19_9_1);
// This section implements an unregistered operation.
//
wire local_bb1__434_stall_local;
wire local_bb1__434;
assign local_bb1__434 = (local_bb1_cmp19_9_1 & local_bb1_not_cmp16_9_1);
// This section implements an unregistered operation.
//
wire local_bb1__433_stall_local;
wire [7:0] local_bb1__433;
assign local_bb1__433 = (local_bb1__432_demorgan ? 8'h1 : rnode_167to168_bb1__431_1_NO_SHIFT_REG);
// This section implements an unregistered operation.
//
wire local_bb1__435_stall_local;
wire [7:0] local_bb1__435;
assign local_bb1__435 = (local_bb1__434 ? 8'h0 : local_bb1__433);
// This section implements an unregistered operation.
//
wire local_bb1_var__u26_stall_local;
wire [7:0] local_bb1_var__u26;
assign local_bb1_var__u26 = (local_bb1__435 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_10_1_stall_local;
wire local_bb1_cmp19_10_1;
assign local_bb1_cmp19_10_1 = (local_bb1_var__u26 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__436_demorgan_stall_local;
wire local_bb1__436_demorgan;
assign local_bb1__436_demorgan = (rnode_167to168_bb1_cmp16_10_1_0_NO_SHIFT_REG | local_bb1_cmp19_10_1);
// This section implements an unregistered operation.
//
wire local_bb1__438_stall_local;
wire local_bb1__438;
assign local_bb1__438 = (local_bb1_cmp19_10_1 & local_bb1_not_cmp16_10_1);
// This section implements an unregistered operation.
//
wire local_bb1__437_stall_local;
wire [7:0] local_bb1__437;
assign local_bb1__437 = (local_bb1__436_demorgan ? 8'h1 : local_bb1__435);
// This section implements an unregistered operation.
//
wire local_bb1__439_stall_local;
wire [7:0] local_bb1__439;
assign local_bb1__439 = (local_bb1__438 ? 8'h0 : local_bb1__437);
// This section implements an unregistered operation.
//
wire local_bb1_var__u27_stall_local;
wire [7:0] local_bb1_var__u27;
assign local_bb1_var__u27 = (local_bb1__439 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_11_1_stall_local;
wire local_bb1_cmp19_11_1;
assign local_bb1_cmp19_11_1 = (local_bb1_var__u27 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__440_demorgan_stall_local;
wire local_bb1__440_demorgan;
assign local_bb1__440_demorgan = (rnode_167to168_bb1_cmp16_11_1_0_NO_SHIFT_REG | local_bb1_cmp19_11_1);
// This section implements an unregistered operation.
//
wire local_bb1__442_stall_local;
wire local_bb1__442;
assign local_bb1__442 = (local_bb1_cmp19_11_1 & local_bb1_not_cmp16_11_1);
// This section implements an unregistered operation.
//
wire local_bb1__441_stall_local;
wire [7:0] local_bb1__441;
assign local_bb1__441 = (local_bb1__440_demorgan ? 8'h1 : local_bb1__439);
// This section implements an unregistered operation.
//
wire local_bb1__443_stall_local;
wire [7:0] local_bb1__443;
assign local_bb1__443 = (local_bb1__442 ? 8'h0 : local_bb1__441);
// This section implements an unregistered operation.
//
wire local_bb1_var__u28_stall_local;
wire [7:0] local_bb1_var__u28;
assign local_bb1_var__u28 = (local_bb1__443 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_12_1_stall_local;
wire local_bb1_cmp19_12_1;
assign local_bb1_cmp19_12_1 = (local_bb1_var__u28 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__444_demorgan_stall_local;
wire local_bb1__444_demorgan;
assign local_bb1__444_demorgan = (rnode_167to168_bb1_cmp16_12_1_0_NO_SHIFT_REG | local_bb1_cmp19_12_1);
// This section implements an unregistered operation.
//
wire local_bb1__446_stall_local;
wire local_bb1__446;
assign local_bb1__446 = (local_bb1_cmp19_12_1 & local_bb1_not_cmp16_12_1);
// This section implements an unregistered operation.
//
wire local_bb1__445_stall_local;
wire [7:0] local_bb1__445;
assign local_bb1__445 = (local_bb1__444_demorgan ? 8'h1 : local_bb1__443);
// This section implements an unregistered operation.
//
wire local_bb1__447_stall_local;
wire [7:0] local_bb1__447;
assign local_bb1__447 = (local_bb1__446 ? 8'h0 : local_bb1__445);
// This section implements an unregistered operation.
//
wire local_bb1_var__u29_stall_local;
wire [7:0] local_bb1_var__u29;
assign local_bb1_var__u29 = (local_bb1__447 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_13_1_stall_local;
wire local_bb1_cmp19_13_1;
assign local_bb1_cmp19_13_1 = (local_bb1_var__u29 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__448_demorgan_stall_local;
wire local_bb1__448_demorgan;
assign local_bb1__448_demorgan = (local_bb1_cmp16_13_1 | local_bb1_cmp19_13_1);
// This section implements an unregistered operation.
//
wire local_bb1__450_stall_local;
wire local_bb1__450;
assign local_bb1__450 = (local_bb1_cmp19_13_1 & local_bb1_not_cmp16_13_1);
// This section implements an unregistered operation.
//
wire local_bb1__449_stall_local;
wire [7:0] local_bb1__449;
assign local_bb1__449 = (local_bb1__448_demorgan ? 8'h1 : local_bb1__447);
// This section implements an unregistered operation.
//
wire local_bb1__451_stall_local;
wire [7:0] local_bb1__451;
assign local_bb1__451 = (local_bb1__450 ? 8'h0 : local_bb1__449);
// This section implements an unregistered operation.
//
wire local_bb1_var__u30_stall_local;
wire [7:0] local_bb1_var__u30;
assign local_bb1_var__u30 = (local_bb1__451 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_14_1_stall_local;
wire local_bb1_cmp19_14_1;
assign local_bb1_cmp19_14_1 = (local_bb1_var__u30 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__452_demorgan_stall_local;
wire local_bb1__452_demorgan;
assign local_bb1__452_demorgan = (local_bb1_cmp16_14_1 | local_bb1_cmp19_14_1);
// This section implements an unregistered operation.
//
wire local_bb1__454_stall_local;
wire local_bb1__454;
assign local_bb1__454 = (local_bb1_cmp19_14_1 & local_bb1_not_cmp16_14_1);
// This section implements an unregistered operation.
//
wire local_bb1__453_stall_local;
wire [7:0] local_bb1__453;
assign local_bb1__453 = (local_bb1__452_demorgan ? 8'h1 : local_bb1__451);
// This section implements an unregistered operation.
//
wire local_bb1__455_stall_local;
wire [7:0] local_bb1__455;
assign local_bb1__455 = (local_bb1__454 ? 8'h0 : local_bb1__453);
// This section implements an unregistered operation.
//
wire local_bb1_var__u31_stall_local;
wire [7:0] local_bb1_var__u31;
assign local_bb1_var__u31 = (local_bb1__455 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_15_1_stall_local;
wire local_bb1_cmp19_15_1;
assign local_bb1_cmp19_15_1 = (local_bb1_var__u31 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__456_demorgan_stall_local;
wire local_bb1__456_demorgan;
assign local_bb1__456_demorgan = (local_bb1_cmp16_15_1 | local_bb1_cmp19_15_1);
// This section implements an unregistered operation.
//
wire local_bb1__458_stall_local;
wire local_bb1__458;
assign local_bb1__458 = (local_bb1_cmp19_15_1 & local_bb1_not_cmp16_15_1);
// This section implements an unregistered operation.
//
wire local_bb1__457_stall_local;
wire [7:0] local_bb1__457;
assign local_bb1__457 = (local_bb1__456_demorgan ? 8'h1 : local_bb1__455);
// This section implements an unregistered operation.
//
wire local_bb1__459_stall_local;
wire [7:0] local_bb1__459;
assign local_bb1__459 = (local_bb1__458 ? 8'h0 : local_bb1__457);
// This section implements an unregistered operation.
//
wire local_bb1_var__u32_stall_local;
wire [7:0] local_bb1_var__u32;
assign local_bb1_var__u32 = (local_bb1__459 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_16_1_stall_local;
wire local_bb1_cmp19_16_1;
assign local_bb1_cmp19_16_1 = (local_bb1_var__u32 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__460_demorgan_stall_local;
wire local_bb1__460_demorgan;
assign local_bb1__460_demorgan = (local_bb1_cmp16_16_1 | local_bb1_cmp19_16_1);
// This section implements an unregistered operation.
//
wire local_bb1_rows_1933_0_pop6__valid_out_0;
wire local_bb1_rows_1933_0_pop6__stall_in_0;
reg local_bb1_rows_1933_0_pop6__consumed_0_NO_SHIFT_REG;
wire local_bb1_rows_1934_0_pop5__valid_out_0;
wire local_bb1_rows_1934_0_pop5__stall_in_0;
reg local_bb1_rows_1934_0_pop5__consumed_0_NO_SHIFT_REG;
wire local_bb1__459_valid_out_1;
wire local_bb1__459_stall_in_1;
reg local_bb1__459_consumed_1_NO_SHIFT_REG;
wire local_bb1_rows_1935_0_pop4__valid_out_0;
wire local_bb1_rows_1935_0_pop4__stall_in_0;
reg local_bb1_rows_1935_0_pop4__consumed_0_NO_SHIFT_REG;
wire local_bb1__460_demorgan_valid_out;
wire local_bb1__460_demorgan_stall_in;
reg local_bb1__460_demorgan_consumed_0_NO_SHIFT_REG;
wire local_bb1__462_valid_out;
wire local_bb1__462_stall_in;
reg local_bb1__462_consumed_0_NO_SHIFT_REG;
wire local_bb1__462_inputs_ready;
wire local_bb1__462_stall_local;
wire local_bb1__462;
assign local_bb1__462_inputs_ready = (rnode_167to168_bb1_c0_ene1_0_valid_out_7_NO_SHIFT_REG & rnode_167to168_bb1_rows_1932_0_pop7__0_valid_out_1_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_12_1_0_valid_out_0_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_12_1_0_valid_out_1_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_10_1_0_valid_out_0_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_10_1_0_valid_out_1_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_11_1_0_valid_out_0_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_11_1_0_valid_out_1_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_9_1_0_valid_out_0_NO_SHIFT_REG & rnode_167to168_bb1__431_0_valid_out_1_NO_SHIFT_REG & rnode_167to168_bb1_cmp16_9_1_0_valid_out_1_NO_SHIFT_REG & rnode_167to168_bb1_c0_ene1_0_valid_out_8_NO_SHIFT_REG & rnode_167to168_bb1__431_0_valid_out_0_NO_SHIFT_REG & rnode_167to168_bb1_c0_ene1_0_valid_out_9_NO_SHIFT_REG);
assign local_bb1__462 = (local_bb1_cmp19_16_1 & local_bb1_not_cmp16_16_1);
assign local_bb1_rows_1933_0_pop6__valid_out_0 = 1'b1;
assign local_bb1_rows_1934_0_pop5__valid_out_0 = 1'b1;
assign local_bb1__459_valid_out_1 = 1'b1;
assign local_bb1_rows_1935_0_pop4__valid_out_0 = 1'b1;
assign local_bb1__460_demorgan_valid_out = 1'b1;
assign local_bb1__462_valid_out = 1'b1;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_7_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_rows_1932_0_pop7__0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_12_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_12_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_10_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_10_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_11_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_11_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_9_1_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1__431_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_cmp16_9_1_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_8_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1__431_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_c0_ene1_0_stall_in_9_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1933_0_pop6__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_1934_0_pop5__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__459_consumed_1_NO_SHIFT_REG <= 1'b0;
local_bb1_rows_1935_0_pop4__consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__460_demorgan_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__462_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1_rows_1933_0_pop6__consumed_0_NO_SHIFT_REG <= (local_bb1__462_inputs_ready & (local_bb1_rows_1933_0_pop6__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1933_0_pop6__stall_in_0)) & local_bb1__462_stall_local);
local_bb1_rows_1934_0_pop5__consumed_0_NO_SHIFT_REG <= (local_bb1__462_inputs_ready & (local_bb1_rows_1934_0_pop5__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1934_0_pop5__stall_in_0)) & local_bb1__462_stall_local);
local_bb1__459_consumed_1_NO_SHIFT_REG <= (local_bb1__462_inputs_ready & (local_bb1__459_consumed_1_NO_SHIFT_REG | ~(local_bb1__459_stall_in_1)) & local_bb1__462_stall_local);
local_bb1_rows_1935_0_pop4__consumed_0_NO_SHIFT_REG <= (local_bb1__462_inputs_ready & (local_bb1_rows_1935_0_pop4__consumed_0_NO_SHIFT_REG | ~(local_bb1_rows_1935_0_pop4__stall_in_0)) & local_bb1__462_stall_local);
local_bb1__460_demorgan_consumed_0_NO_SHIFT_REG <= (local_bb1__462_inputs_ready & (local_bb1__460_demorgan_consumed_0_NO_SHIFT_REG | ~(local_bb1__460_demorgan_stall_in)) & local_bb1__462_stall_local);
local_bb1__462_consumed_0_NO_SHIFT_REG <= (local_bb1__462_inputs_ready & (local_bb1__462_consumed_0_NO_SHIFT_REG | ~(local_bb1__462_stall_in)) & local_bb1__462_stall_local);
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_1934_0_push5_rows_1933_0_pop6_inputs_ready;
reg local_bb1_rows_1934_0_push5_rows_1933_0_pop6_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1934_0_push5_rows_1933_0_pop6_stall_in;
wire local_bb1_rows_1934_0_push5_rows_1933_0_pop6_output_regs_ready;
wire [7:0] local_bb1_rows_1934_0_push5_rows_1933_0_pop6_result;
wire local_bb1_rows_1934_0_push5_rows_1933_0_pop6_fu_valid_out;
wire local_bb1_rows_1934_0_push5_rows_1933_0_pop6_fu_stall_out;
reg [7:0] local_bb1_rows_1934_0_push5_rows_1933_0_pop6_NO_SHIFT_REG;
wire local_bb1_rows_1934_0_push5_rows_1933_0_pop6_causedstall;
acl_push local_bb1_rows_1934_0_push5_rows_1933_0_pop6_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_4_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1933_0_pop6_),
.stall_out(local_bb1_rows_1934_0_push5_rows_1933_0_pop6_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1_rows_1934_0_push5_rows_1933_0_pop6_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1934_0_push5_rows_1933_0_pop6_result),
.feedback_out(feedback_data_out_5),
.feedback_valid_out(feedback_valid_out_5),
.feedback_stall_in(feedback_stall_in_5)
);
defparam local_bb1_rows_1934_0_push5_rows_1933_0_pop6_feedback.STALLFREE = 1;
defparam local_bb1_rows_1934_0_push5_rows_1933_0_pop6_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1934_0_push5_rows_1933_0_pop6_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1934_0_push5_rows_1933_0_pop6_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1934_0_push5_rows_1933_0_pop6_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1934_0_push5_rows_1933_0_pop6_inputs_ready = 1'b1;
assign local_bb1_rows_1934_0_push5_rows_1933_0_pop6_output_regs_ready = 1'b1;
assign local_bb1_rows_1933_0_pop6__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_4_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1934_0_push5_rows_1933_0_pop6_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1934_0_push5_rows_1933_0_pop6_NO_SHIFT_REG <= 'x;
local_bb1_rows_1934_0_push5_rows_1933_0_pop6_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1934_0_push5_rows_1933_0_pop6_output_regs_ready)
begin
local_bb1_rows_1934_0_push5_rows_1933_0_pop6_NO_SHIFT_REG <= local_bb1_rows_1934_0_push5_rows_1933_0_pop6_result;
local_bb1_rows_1934_0_push5_rows_1933_0_pop6_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1934_0_push5_rows_1933_0_pop6_stall_in))
begin
local_bb1_rows_1934_0_push5_rows_1933_0_pop6_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a registered operation.
//
wire local_bb1_rows_1935_0_push4_rows_1934_0_pop5_inputs_ready;
reg local_bb1_rows_1935_0_push4_rows_1934_0_pop5_valid_out_NO_SHIFT_REG;
wire local_bb1_rows_1935_0_push4_rows_1934_0_pop5_stall_in;
wire local_bb1_rows_1935_0_push4_rows_1934_0_pop5_output_regs_ready;
wire [7:0] local_bb1_rows_1935_0_push4_rows_1934_0_pop5_result;
wire local_bb1_rows_1935_0_push4_rows_1934_0_pop5_fu_valid_out;
wire local_bb1_rows_1935_0_push4_rows_1934_0_pop5_fu_stall_out;
reg [7:0] local_bb1_rows_1935_0_push4_rows_1934_0_pop5_NO_SHIFT_REG;
wire local_bb1_rows_1935_0_push4_rows_1934_0_pop5_causedstall;
acl_push local_bb1_rows_1935_0_push4_rows_1934_0_pop5_feedback (
.clock(clock),
.resetn(resetn),
.dir(rnode_167to168_bb1_c0_ene2_5_NO_SHIFT_REG),
.predicate(1'b0),
.data_in(local_bb1_rows_1934_0_pop5_),
.stall_out(local_bb1_rows_1935_0_push4_rows_1934_0_pop5_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1_rows_1935_0_push4_rows_1934_0_pop5_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1_rows_1935_0_push4_rows_1934_0_pop5_result),
.feedback_out(feedback_data_out_4),
.feedback_valid_out(feedback_valid_out_4),
.feedback_stall_in(feedback_stall_in_4)
);
defparam local_bb1_rows_1935_0_push4_rows_1934_0_pop5_feedback.STALLFREE = 1;
defparam local_bb1_rows_1935_0_push4_rows_1934_0_pop5_feedback.DATA_WIDTH = 8;
defparam local_bb1_rows_1935_0_push4_rows_1934_0_pop5_feedback.FIFO_DEPTH = 1;
defparam local_bb1_rows_1935_0_push4_rows_1934_0_pop5_feedback.MIN_FIFO_LATENCY = 1;
defparam local_bb1_rows_1935_0_push4_rows_1934_0_pop5_feedback.STYLE = "REGULAR";
assign local_bb1_rows_1935_0_push4_rows_1934_0_pop5_inputs_ready = 1'b1;
assign local_bb1_rows_1935_0_push4_rows_1934_0_pop5_output_regs_ready = 1'b1;
assign local_bb1_rows_1934_0_pop5__stall_in_0 = 1'b0;
assign rnode_167to168_bb1_c0_ene2_0_stall_in_5_NO_SHIFT_REG = 1'b0;
assign local_bb1_rows_1935_0_push4_rows_1934_0_pop5_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_rows_1935_0_push4_rows_1934_0_pop5_NO_SHIFT_REG <= 'x;
local_bb1_rows_1935_0_push4_rows_1934_0_pop5_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_rows_1935_0_push4_rows_1934_0_pop5_output_regs_ready)
begin
local_bb1_rows_1935_0_push4_rows_1934_0_pop5_NO_SHIFT_REG <= local_bb1_rows_1935_0_push4_rows_1934_0_pop5_result;
local_bb1_rows_1935_0_push4_rows_1934_0_pop5_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1_rows_1935_0_push4_rows_1934_0_pop5_stall_in))
begin
local_bb1_rows_1935_0_push4_rows_1934_0_pop5_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1__459_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1__459_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__459_0_NO_SHIFT_REG;
logic rnode_168to169_bb1__459_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_168to169_bb1__459_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__459_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__459_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__459_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1__459_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1__459_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1__459_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1__459_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1__459_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1__459),
.data_out(rnode_168to169_bb1__459_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1__459_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1__459_0_reg_169_fifo.DATA_WIDTH = 8;
defparam rnode_168to169_bb1__459_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1__459_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1__459_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__459_stall_in_1 = 1'b0;
assign rnode_168to169_bb1__459_0_NO_SHIFT_REG = rnode_168to169_bb1__459_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1__459_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__459_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements a registered operation.
//
wire local_bb1__coalesced_push2_rows_1935_0_pop4_inputs_ready;
reg local_bb1__coalesced_push2_rows_1935_0_pop4_valid_out_NO_SHIFT_REG;
wire local_bb1__coalesced_push2_rows_1935_0_pop4_stall_in;
wire local_bb1__coalesced_push2_rows_1935_0_pop4_output_regs_ready;
wire [7:0] local_bb1__coalesced_push2_rows_1935_0_pop4_result;
wire local_bb1__coalesced_push2_rows_1935_0_pop4_fu_valid_out;
wire local_bb1__coalesced_push2_rows_1935_0_pop4_fu_stall_out;
reg [7:0] local_bb1__coalesced_push2_rows_1935_0_pop4_NO_SHIFT_REG;
wire local_bb1__coalesced_push2_rows_1935_0_pop4_causedstall;
acl_push local_bb1__coalesced_push2_rows_1935_0_pop4_feedback (
.clock(clock),
.resetn(resetn),
.dir(1'b1),
.predicate(1'b0),
.data_in(local_bb1_rows_1935_0_pop4_),
.stall_out(local_bb1__coalesced_push2_rows_1935_0_pop4_fu_stall_out),
.valid_in(local_bb1_c0_exit_c0_exi1_valid_bits[6]),
.valid_out(local_bb1__coalesced_push2_rows_1935_0_pop4_fu_valid_out),
.stall_in(1'b0),
.data_out(local_bb1__coalesced_push2_rows_1935_0_pop4_result),
.feedback_out(feedback_data_out_2),
.feedback_valid_out(feedback_valid_out_2),
.feedback_stall_in(feedback_stall_in_2)
);
defparam local_bb1__coalesced_push2_rows_1935_0_pop4_feedback.STALLFREE = 1;
defparam local_bb1__coalesced_push2_rows_1935_0_pop4_feedback.DATA_WIDTH = 8;
defparam local_bb1__coalesced_push2_rows_1935_0_pop4_feedback.FIFO_DEPTH = 1904;
defparam local_bb1__coalesced_push2_rows_1935_0_pop4_feedback.MIN_FIFO_LATENCY = 1904;
defparam local_bb1__coalesced_push2_rows_1935_0_pop4_feedback.STYLE = "REGULAR";
assign local_bb1__coalesced_push2_rows_1935_0_pop4_inputs_ready = 1'b1;
assign local_bb1__coalesced_push2_rows_1935_0_pop4_output_regs_ready = 1'b1;
assign local_bb1_rows_1935_0_pop4__stall_in_0 = 1'b0;
assign local_bb1__coalesced_push2_rows_1935_0_pop4_causedstall = (local_bb1_c0_exit_c0_exi1_valid_bits[6] && (1'b0 && !(1'b0)));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__coalesced_push2_rows_1935_0_pop4_NO_SHIFT_REG <= 'x;
local_bb1__coalesced_push2_rows_1935_0_pop4_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1__coalesced_push2_rows_1935_0_pop4_output_regs_ready)
begin
local_bb1__coalesced_push2_rows_1935_0_pop4_NO_SHIFT_REG <= local_bb1__coalesced_push2_rows_1935_0_pop4_result;
local_bb1__coalesced_push2_rows_1935_0_pop4_valid_out_NO_SHIFT_REG <= 1'b1;
end
else
begin
if (~(local_bb1__coalesced_push2_rows_1935_0_pop4_stall_in))
begin
local_bb1__coalesced_push2_rows_1935_0_pop4_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1__460_demorgan_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_stall_in_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__460_demorgan_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1__460_demorgan_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1__460_demorgan_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1__460_demorgan_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1__460_demorgan_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1__460_demorgan_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1__460_demorgan),
.data_out(rnode_168to169_bb1__460_demorgan_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1__460_demorgan_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1__460_demorgan_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1__460_demorgan_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1__460_demorgan_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1__460_demorgan_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__460_demorgan_stall_in = 1'b0;
assign rnode_168to169_bb1__460_demorgan_0_NO_SHIFT_REG = rnode_168to169_bb1__460_demorgan_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1__460_demorgan_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__460_demorgan_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_168to169_bb1__462_0_valid_out_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_stall_in_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_reg_169_inputs_ready_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_valid_out_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_stall_in_reg_169_NO_SHIFT_REG;
logic rnode_168to169_bb1__462_0_stall_out_reg_169_NO_SHIFT_REG;
acl_data_fifo rnode_168to169_bb1__462_0_reg_169_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_168to169_bb1__462_0_reg_169_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_168to169_bb1__462_0_stall_in_reg_169_NO_SHIFT_REG),
.valid_out(rnode_168to169_bb1__462_0_valid_out_reg_169_NO_SHIFT_REG),
.stall_out(rnode_168to169_bb1__462_0_stall_out_reg_169_NO_SHIFT_REG),
.data_in(local_bb1__462),
.data_out(rnode_168to169_bb1__462_0_reg_169_NO_SHIFT_REG)
);
defparam rnode_168to169_bb1__462_0_reg_169_fifo.DEPTH = 1;
defparam rnode_168to169_bb1__462_0_reg_169_fifo.DATA_WIDTH = 1;
defparam rnode_168to169_bb1__462_0_reg_169_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_168to169_bb1__462_0_reg_169_fifo.IMPL = "shift_reg";
assign rnode_168to169_bb1__462_0_reg_169_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__462_stall_in = 1'b0;
assign rnode_168to169_bb1__462_0_NO_SHIFT_REG = rnode_168to169_bb1__462_0_reg_169_NO_SHIFT_REG;
assign rnode_168to169_bb1__462_0_stall_in_reg_169_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__462_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_rows_1934_0_push5_rows_1933_0_pop6_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1934_0_push5_rows_1933_0_pop6_stall_in = 1'b0;
assign rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_NO_SHIFT_REG = rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_rows_1935_0_push4_rows_1934_0_pop5_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_rows_1935_0_push4_rows_1934_0_pop5_stall_in = 1'b0;
assign rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_NO_SHIFT_REG = rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 2
// * capacity = 2
logic rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_valid_out_NO_SHIFT_REG;
logic rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_NO_SHIFT_REG;
logic rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_valid_out_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_in_reg_171_NO_SHIFT_REG;
logic rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_in_reg_171_NO_SHIFT_REG),
.valid_out(rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_valid_out_reg_171_NO_SHIFT_REG),
.stall_out(rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1__coalesced_push2_rows_1935_0_pop4_NO_SHIFT_REG),
.data_out(rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_fifo.DEPTH = 2;
defparam rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__coalesced_push2_rows_1935_0_pop4_stall_in = 1'b0;
assign rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_NO_SHIFT_REG = rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_reg_171_NO_SHIFT_REG;
assign rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_in_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__461_stall_local;
wire [7:0] local_bb1__461;
assign local_bb1__461 = (rnode_168to169_bb1__460_demorgan_0_NO_SHIFT_REG ? 8'h1 : rnode_168to169_bb1__459_0_NO_SHIFT_REG);
// This section implements an unregistered operation.
//
wire local_bb1__463_stall_local;
wire [7:0] local_bb1__463;
assign local_bb1__463 = (rnode_168to169_bb1__462_0_NO_SHIFT_REG ? 8'h0 : local_bb1__461);
// This section implements an unregistered operation.
//
wire local_bb1_var__u33_stall_local;
wire [7:0] local_bb1_var__u33;
assign local_bb1_var__u33 = (local_bb1__463 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_229_stall_local;
wire local_bb1_cmp19_229;
assign local_bb1_cmp19_229 = (local_bb1_var__u33 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__464_demorgan_stall_local;
wire local_bb1__464_demorgan;
assign local_bb1__464_demorgan = (rnode_168to169_bb1_cmp16_228_0_NO_SHIFT_REG | local_bb1_cmp19_229);
// This section implements an unregistered operation.
//
wire local_bb1__466_stall_local;
wire local_bb1__466;
assign local_bb1__466 = (local_bb1_cmp19_229 & local_bb1_not_cmp16_228);
// This section implements an unregistered operation.
//
wire local_bb1__465_stall_local;
wire [7:0] local_bb1__465;
assign local_bb1__465 = (local_bb1__464_demorgan ? 8'h1 : local_bb1__463);
// This section implements an unregistered operation.
//
wire local_bb1__467_stall_local;
wire [7:0] local_bb1__467;
assign local_bb1__467 = (local_bb1__466 ? 8'h0 : local_bb1__465);
// This section implements an unregistered operation.
//
wire local_bb1_var__u34_stall_local;
wire [7:0] local_bb1_var__u34;
assign local_bb1_var__u34 = (local_bb1__467 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_1_2_stall_local;
wire local_bb1_cmp19_1_2;
assign local_bb1_cmp19_1_2 = (local_bb1_var__u34 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__468_demorgan_stall_local;
wire local_bb1__468_demorgan;
assign local_bb1__468_demorgan = (local_bb1_cmp16_1_2 | local_bb1_cmp19_1_2);
// This section implements an unregistered operation.
//
wire local_bb1__470_stall_local;
wire local_bb1__470;
assign local_bb1__470 = (local_bb1_cmp19_1_2 & local_bb1_not_cmp16_1_2);
// This section implements an unregistered operation.
//
wire local_bb1__469_stall_local;
wire [7:0] local_bb1__469;
assign local_bb1__469 = (local_bb1__468_demorgan ? 8'h1 : local_bb1__467);
// This section implements an unregistered operation.
//
wire local_bb1__471_stall_local;
wire [7:0] local_bb1__471;
assign local_bb1__471 = (local_bb1__470 ? 8'h0 : local_bb1__469);
// This section implements an unregistered operation.
//
wire local_bb1_var__u35_stall_local;
wire [7:0] local_bb1_var__u35;
assign local_bb1_var__u35 = (local_bb1__471 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_2_2_stall_local;
wire local_bb1_cmp19_2_2;
assign local_bb1_cmp19_2_2 = (local_bb1_var__u35 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__472_demorgan_stall_local;
wire local_bb1__472_demorgan;
assign local_bb1__472_demorgan = (rnode_168to169_bb1_cmp16_2_2_0_NO_SHIFT_REG | local_bb1_cmp19_2_2);
// This section implements an unregistered operation.
//
wire local_bb1__474_stall_local;
wire local_bb1__474;
assign local_bb1__474 = (local_bb1_cmp19_2_2 & local_bb1_not_cmp16_2_2);
// This section implements an unregistered operation.
//
wire local_bb1__473_stall_local;
wire [7:0] local_bb1__473;
assign local_bb1__473 = (local_bb1__472_demorgan ? 8'h1 : local_bb1__471);
// This section implements an unregistered operation.
//
wire local_bb1__475_stall_local;
wire [7:0] local_bb1__475;
assign local_bb1__475 = (local_bb1__474 ? 8'h0 : local_bb1__473);
// This section implements an unregistered operation.
//
wire local_bb1_var__u36_stall_local;
wire [7:0] local_bb1_var__u36;
assign local_bb1_var__u36 = (local_bb1__475 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_3_2_stall_local;
wire local_bb1_cmp19_3_2;
assign local_bb1_cmp19_3_2 = (local_bb1_var__u36 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__476_demorgan_stall_local;
wire local_bb1__476_demorgan;
assign local_bb1__476_demorgan = (rnode_168to169_bb1_cmp16_3_2_0_NO_SHIFT_REG | local_bb1_cmp19_3_2);
// This section implements an unregistered operation.
//
wire local_bb1__478_stall_local;
wire local_bb1__478;
assign local_bb1__478 = (local_bb1_cmp19_3_2 & local_bb1_not_cmp16_3_2);
// This section implements an unregistered operation.
//
wire local_bb1__477_stall_local;
wire [7:0] local_bb1__477;
assign local_bb1__477 = (local_bb1__476_demorgan ? 8'h1 : local_bb1__475);
// This section implements an unregistered operation.
//
wire local_bb1__479_stall_local;
wire [7:0] local_bb1__479;
assign local_bb1__479 = (local_bb1__478 ? 8'h0 : local_bb1__477);
// This section implements an unregistered operation.
//
wire local_bb1_var__u37_stall_local;
wire [7:0] local_bb1_var__u37;
assign local_bb1_var__u37 = (local_bb1__479 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_4_2_stall_local;
wire local_bb1_cmp19_4_2;
assign local_bb1_cmp19_4_2 = (local_bb1_var__u37 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__480_demorgan_stall_local;
wire local_bb1__480_demorgan;
assign local_bb1__480_demorgan = (rnode_168to169_bb1_cmp16_4_2_0_NO_SHIFT_REG | local_bb1_cmp19_4_2);
// This section implements an unregistered operation.
//
wire local_bb1__482_stall_local;
wire local_bb1__482;
assign local_bb1__482 = (local_bb1_cmp19_4_2 & local_bb1_not_cmp16_4_2);
// This section implements an unregistered operation.
//
wire local_bb1__481_stall_local;
wire [7:0] local_bb1__481;
assign local_bb1__481 = (local_bb1__480_demorgan ? 8'h1 : local_bb1__479);
// This section implements an unregistered operation.
//
wire local_bb1__483_stall_local;
wire [7:0] local_bb1__483;
assign local_bb1__483 = (local_bb1__482 ? 8'h0 : local_bb1__481);
// This section implements an unregistered operation.
//
wire local_bb1_var__u38_stall_local;
wire [7:0] local_bb1_var__u38;
assign local_bb1_var__u38 = (local_bb1__483 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_5_2_stall_local;
wire local_bb1_cmp19_5_2;
assign local_bb1_cmp19_5_2 = (local_bb1_var__u38 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__484_demorgan_stall_local;
wire local_bb1__484_demorgan;
assign local_bb1__484_demorgan = (rnode_168to169_bb1_cmp16_5_2_0_NO_SHIFT_REG | local_bb1_cmp19_5_2);
// This section implements an unregistered operation.
//
wire local_bb1__486_stall_local;
wire local_bb1__486;
assign local_bb1__486 = (local_bb1_cmp19_5_2 & local_bb1_not_cmp16_5_2);
// This section implements an unregistered operation.
//
wire local_bb1__485_stall_local;
wire [7:0] local_bb1__485;
assign local_bb1__485 = (local_bb1__484_demorgan ? 8'h1 : local_bb1__483);
// This section implements an unregistered operation.
//
wire local_bb1__487_stall_local;
wire [7:0] local_bb1__487;
assign local_bb1__487 = (local_bb1__486 ? 8'h0 : local_bb1__485);
// This section implements an unregistered operation.
//
wire local_bb1_var__u39_stall_local;
wire [7:0] local_bb1_var__u39;
assign local_bb1_var__u39 = (local_bb1__487 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_6_2_stall_local;
wire local_bb1_cmp19_6_2;
assign local_bb1_cmp19_6_2 = (local_bb1_var__u39 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__488_demorgan_stall_local;
wire local_bb1__488_demorgan;
assign local_bb1__488_demorgan = (rnode_168to169_bb1_cmp16_6_2_0_NO_SHIFT_REG | local_bb1_cmp19_6_2);
// This section implements an unregistered operation.
//
wire local_bb1__490_stall_local;
wire local_bb1__490;
assign local_bb1__490 = (local_bb1_cmp19_6_2 & local_bb1_not_cmp16_6_2);
// This section implements an unregistered operation.
//
wire local_bb1__489_valid_out;
wire local_bb1__489_stall_in;
reg local_bb1__489_consumed_0_NO_SHIFT_REG;
wire local_bb1__490_valid_out;
wire local_bb1__490_stall_in;
reg local_bb1__490_consumed_0_NO_SHIFT_REG;
wire local_bb1__489_inputs_ready;
wire local_bb1__489_stall_local;
wire [7:0] local_bb1__489;
assign local_bb1__489_inputs_ready = (rnode_168to169_bb1__pop36__0_valid_out_1_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_2_2_0_valid_out_0_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_2_2_0_valid_out_1_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_3_2_0_valid_out_0_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_3_2_0_valid_out_1_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_4_2_0_valid_out_0_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_4_2_0_valid_out_1_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_5_2_0_valid_out_0_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_5_2_0_valid_out_1_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_6_2_0_valid_out_0_NO_SHIFT_REG & rnode_168to169_bb1__460_demorgan_0_valid_out_NO_SHIFT_REG & rnode_168to169_bb1__459_0_valid_out_NO_SHIFT_REG & rnode_168to169_bb1__462_0_valid_out_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_228_0_valid_out_0_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_228_0_valid_out_1_NO_SHIFT_REG & rnode_168to169_bb1_cmp16_6_2_0_valid_out_1_NO_SHIFT_REG);
assign local_bb1__489 = (local_bb1__488_demorgan ? 8'h1 : local_bb1__487);
assign local_bb1__489_valid_out = 1'b1;
assign local_bb1__490_valid_out = 1'b1;
assign rnode_168to169_bb1__pop36__0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_2_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_2_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_3_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_3_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_4_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_4_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_5_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_5_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_6_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__460_demorgan_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__459_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1__462_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_228_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_228_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_168to169_bb1_cmp16_6_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1__489_consumed_0_NO_SHIFT_REG <= 1'b0;
local_bb1__490_consumed_0_NO_SHIFT_REG <= 1'b0;
end
else
begin
local_bb1__489_consumed_0_NO_SHIFT_REG <= (local_bb1__489_inputs_ready & (local_bb1__489_consumed_0_NO_SHIFT_REG | ~(local_bb1__489_stall_in)) & local_bb1__489_stall_local);
local_bb1__490_consumed_0_NO_SHIFT_REG <= (local_bb1__489_inputs_ready & (local_bb1__490_consumed_0_NO_SHIFT_REG | ~(local_bb1__490_stall_in)) & local_bb1__489_stall_local);
end
end
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1__489_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1__489_0_stall_in_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1__489_0_NO_SHIFT_REG;
logic rnode_169to170_bb1__489_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_169to170_bb1__489_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__489_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__489_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__489_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1__489_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1__489_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1__489_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1__489_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1__489_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1__489),
.data_out(rnode_169to170_bb1__489_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1__489_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1__489_0_reg_170_fifo.DATA_WIDTH = 8;
defparam rnode_169to170_bb1__489_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1__489_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1__489_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__489_stall_in = 1'b0;
assign rnode_169to170_bb1__489_0_NO_SHIFT_REG = rnode_169to170_bb1__489_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1__489_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1__489_0_valid_out_NO_SHIFT_REG = 1'b1;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_169to170_bb1__490_0_valid_out_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_stall_in_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_reg_170_inputs_ready_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_valid_out_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_stall_in_reg_170_NO_SHIFT_REG;
logic rnode_169to170_bb1__490_0_stall_out_reg_170_NO_SHIFT_REG;
acl_data_fifo rnode_169to170_bb1__490_0_reg_170_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_169to170_bb1__490_0_reg_170_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_169to170_bb1__490_0_stall_in_reg_170_NO_SHIFT_REG),
.valid_out(rnode_169to170_bb1__490_0_valid_out_reg_170_NO_SHIFT_REG),
.stall_out(rnode_169to170_bb1__490_0_stall_out_reg_170_NO_SHIFT_REG),
.data_in(local_bb1__490),
.data_out(rnode_169to170_bb1__490_0_reg_170_NO_SHIFT_REG)
);
defparam rnode_169to170_bb1__490_0_reg_170_fifo.DEPTH = 1;
defparam rnode_169to170_bb1__490_0_reg_170_fifo.DATA_WIDTH = 1;
defparam rnode_169to170_bb1__490_0_reg_170_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_169to170_bb1__490_0_reg_170_fifo.IMPL = "shift_reg";
assign rnode_169to170_bb1__490_0_reg_170_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__490_stall_in = 1'b0;
assign rnode_169to170_bb1__490_0_NO_SHIFT_REG = rnode_169to170_bb1__490_0_reg_170_NO_SHIFT_REG;
assign rnode_169to170_bb1__490_0_stall_in_reg_170_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1__490_0_valid_out_NO_SHIFT_REG = 1'b1;
// This section implements an unregistered operation.
//
wire local_bb1__491_stall_local;
wire [7:0] local_bb1__491;
assign local_bb1__491 = (rnode_169to170_bb1__490_0_NO_SHIFT_REG ? 8'h0 : rnode_169to170_bb1__489_0_NO_SHIFT_REG);
// This section implements an unregistered operation.
//
wire local_bb1_var__u40_stall_local;
wire [7:0] local_bb1_var__u40;
assign local_bb1_var__u40 = (local_bb1__491 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_7_2_stall_local;
wire local_bb1_cmp19_7_2;
assign local_bb1_cmp19_7_2 = (local_bb1_var__u40 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__492_demorgan_stall_local;
wire local_bb1__492_demorgan;
assign local_bb1__492_demorgan = (rnode_169to170_bb1_cmp16_7_2_0_NO_SHIFT_REG | local_bb1_cmp19_7_2);
// This section implements an unregistered operation.
//
wire local_bb1__494_stall_local;
wire local_bb1__494;
assign local_bb1__494 = (local_bb1_cmp19_7_2 & local_bb1_not_cmp16_7_2);
// This section implements an unregistered operation.
//
wire local_bb1__493_stall_local;
wire [7:0] local_bb1__493;
assign local_bb1__493 = (local_bb1__492_demorgan ? 8'h1 : local_bb1__491);
// This section implements an unregistered operation.
//
wire local_bb1__495_stall_local;
wire [7:0] local_bb1__495;
assign local_bb1__495 = (local_bb1__494 ? 8'h0 : local_bb1__493);
// This section implements an unregistered operation.
//
wire local_bb1_var__u41_stall_local;
wire [7:0] local_bb1_var__u41;
assign local_bb1_var__u41 = (local_bb1__495 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_8_2_stall_local;
wire local_bb1_cmp19_8_2;
assign local_bb1_cmp19_8_2 = (local_bb1_var__u41 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__496_demorgan_stall_local;
wire local_bb1__496_demorgan;
assign local_bb1__496_demorgan = (rnode_169to170_bb1_cmp16_8_2_0_NO_SHIFT_REG | local_bb1_cmp19_8_2);
// This section implements an unregistered operation.
//
wire local_bb1__498_stall_local;
wire local_bb1__498;
assign local_bb1__498 = (local_bb1_cmp19_8_2 & local_bb1_not_cmp16_8_2);
// This section implements an unregistered operation.
//
wire local_bb1__497_stall_local;
wire [7:0] local_bb1__497;
assign local_bb1__497 = (local_bb1__496_demorgan ? 8'h1 : local_bb1__495);
// This section implements an unregistered operation.
//
wire local_bb1__499_stall_local;
wire [7:0] local_bb1__499;
assign local_bb1__499 = (local_bb1__498 ? 8'h0 : local_bb1__497);
// This section implements an unregistered operation.
//
wire local_bb1_var__u42_stall_local;
wire [7:0] local_bb1_var__u42;
assign local_bb1_var__u42 = (local_bb1__499 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_9_2_stall_local;
wire local_bb1_cmp19_9_2;
assign local_bb1_cmp19_9_2 = (local_bb1_var__u42 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__500_demorgan_stall_local;
wire local_bb1__500_demorgan;
assign local_bb1__500_demorgan = (rnode_169to170_bb1_cmp16_9_2_0_NO_SHIFT_REG | local_bb1_cmp19_9_2);
// This section implements an unregistered operation.
//
wire local_bb1__502_stall_local;
wire local_bb1__502;
assign local_bb1__502 = (local_bb1_cmp19_9_2 & local_bb1_not_cmp16_9_2);
// This section implements an unregistered operation.
//
wire local_bb1__501_stall_local;
wire [7:0] local_bb1__501;
assign local_bb1__501 = (local_bb1__500_demorgan ? 8'h1 : local_bb1__499);
// This section implements an unregistered operation.
//
wire local_bb1__503_stall_local;
wire [7:0] local_bb1__503;
assign local_bb1__503 = (local_bb1__502 ? 8'h0 : local_bb1__501);
// This section implements an unregistered operation.
//
wire local_bb1_var__u43_stall_local;
wire [7:0] local_bb1_var__u43;
assign local_bb1_var__u43 = (local_bb1__503 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_10_2_stall_local;
wire local_bb1_cmp19_10_2;
assign local_bb1_cmp19_10_2 = (local_bb1_var__u43 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__504_demorgan_stall_local;
wire local_bb1__504_demorgan;
assign local_bb1__504_demorgan = (rnode_169to170_bb1_cmp16_10_2_0_NO_SHIFT_REG | local_bb1_cmp19_10_2);
// This section implements an unregistered operation.
//
wire local_bb1__506_stall_local;
wire local_bb1__506;
assign local_bb1__506 = (local_bb1_cmp19_10_2 & local_bb1_not_cmp16_10_2);
// This section implements an unregistered operation.
//
wire local_bb1__505_stall_local;
wire [7:0] local_bb1__505;
assign local_bb1__505 = (local_bb1__504_demorgan ? 8'h1 : local_bb1__503);
// This section implements an unregistered operation.
//
wire local_bb1__507_stall_local;
wire [7:0] local_bb1__507;
assign local_bb1__507 = (local_bb1__506 ? 8'h0 : local_bb1__505);
// This section implements an unregistered operation.
//
wire local_bb1_var__u44_stall_local;
wire [7:0] local_bb1_var__u44;
assign local_bb1_var__u44 = (local_bb1__507 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1__507_op_stall_local;
wire [7:0] local_bb1__507_op;
assign local_bb1__507_op = (local_bb1__507 & 8'h1);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_11_2_stall_local;
wire local_bb1_cmp19_11_2;
assign local_bb1_cmp19_11_2 = (local_bb1_var__u44 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__508_demorgan_stall_local;
wire local_bb1__508_demorgan;
assign local_bb1__508_demorgan = (rnode_169to170_bb1_cmp16_11_2_0_NO_SHIFT_REG | local_bb1_cmp19_11_2);
// This section implements an unregistered operation.
//
wire local_bb1__510_stall_local;
wire local_bb1__510;
assign local_bb1__510 = (local_bb1_cmp19_11_2 & local_bb1_not_cmp16_11_2);
// This section implements an unregistered operation.
//
wire local_bb1__509_op_stall_local;
wire [7:0] local_bb1__509_op;
assign local_bb1__509_op = (local_bb1__508_demorgan ? 8'h1 : local_bb1__507_op);
// This section implements an unregistered operation.
//
wire local_bb1_var__u45_stall_local;
wire [7:0] local_bb1_var__u45;
assign local_bb1_var__u45 = (local_bb1__510 ? 8'h0 : local_bb1__509_op);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_12_2_stall_local;
wire local_bb1_cmp19_12_2;
assign local_bb1_cmp19_12_2 = (local_bb1_var__u45 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__512_demorgan_stall_local;
wire local_bb1__512_demorgan;
assign local_bb1__512_demorgan = (rnode_169to170_bb1_cmp16_12_2_0_NO_SHIFT_REG | local_bb1_cmp19_12_2);
// This section implements an unregistered operation.
//
wire local_bb1__514_stall_local;
wire local_bb1__514;
assign local_bb1__514 = (local_bb1_cmp19_12_2 & local_bb1_not_cmp16_12_2);
// This section implements an unregistered operation.
//
wire local_bb1__513_op_stall_local;
wire [7:0] local_bb1__513_op;
assign local_bb1__513_op = (local_bb1__512_demorgan ? 8'h1 : local_bb1_var__u45);
// This section implements an unregistered operation.
//
wire local_bb1_var__u46_stall_local;
wire [7:0] local_bb1_var__u46;
assign local_bb1_var__u46 = (local_bb1__514 ? 8'h0 : local_bb1__513_op);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_13_2_stall_local;
wire local_bb1_cmp19_13_2;
assign local_bb1_cmp19_13_2 = (local_bb1_var__u46 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__516_demorgan_stall_local;
wire local_bb1__516_demorgan;
assign local_bb1__516_demorgan = (local_bb1_cmp16_13_2 | local_bb1_cmp19_13_2);
// This section implements an unregistered operation.
//
wire local_bb1__518_stall_local;
wire local_bb1__518;
assign local_bb1__518 = (local_bb1_cmp19_13_2 & local_bb1_not_cmp16_13_2);
// This section implements an unregistered operation.
//
wire local_bb1__517_op_stall_local;
wire [7:0] local_bb1__517_op;
assign local_bb1__517_op = (local_bb1__516_demorgan ? 8'h1 : local_bb1_var__u46);
// This section implements an unregistered operation.
//
wire local_bb1_var__u47_valid_out;
wire local_bb1_var__u47_stall_in;
wire local_bb1_var__u47_inputs_ready;
wire local_bb1_var__u47_stall_local;
wire [7:0] local_bb1_var__u47;
assign local_bb1_var__u47_inputs_ready = (rnode_169to170_bb1__pop48__0_valid_out_1_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_11_2_0_valid_out_0_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_11_2_0_valid_out_1_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_12_2_0_valid_out_0_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_12_2_0_valid_out_1_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_7_2_0_valid_out_0_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_7_2_0_valid_out_1_NO_SHIFT_REG & rnode_169to170_bb1__490_0_valid_out_NO_SHIFT_REG & rnode_169to170_bb1__489_0_valid_out_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_8_2_0_valid_out_0_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_8_2_0_valid_out_1_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_9_2_0_valid_out_0_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_9_2_0_valid_out_1_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_10_2_0_valid_out_0_NO_SHIFT_REG & rnode_169to170_bb1_cmp16_10_2_0_valid_out_1_NO_SHIFT_REG);
assign local_bb1_var__u47 = (local_bb1__518 ? 8'h0 : local_bb1__517_op);
assign local_bb1_var__u47_valid_out = 1'b1;
assign rnode_169to170_bb1__pop48__0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_11_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_11_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_12_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_12_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_7_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_7_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1__490_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1__489_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_8_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_8_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_9_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_9_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_10_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_169to170_bb1_cmp16_10_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
// Register node:
// * latency = 1
// * capacity = 1
logic rnode_170to171_bb1_var__u47_0_valid_out_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_stall_in_0_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_var__u47_0_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_valid_out_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_stall_in_1_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_var__u47_1_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_reg_171_inputs_ready_NO_SHIFT_REG;
logic [7:0] rnode_170to171_bb1_var__u47_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_valid_out_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_stall_in_0_reg_171_NO_SHIFT_REG;
logic rnode_170to171_bb1_var__u47_0_stall_out_reg_171_NO_SHIFT_REG;
acl_data_fifo rnode_170to171_bb1_var__u47_0_reg_171_fifo (
.clock(clock),
.resetn(resetn),
.valid_in(rnode_170to171_bb1_var__u47_0_reg_171_inputs_ready_NO_SHIFT_REG),
.stall_in(rnode_170to171_bb1_var__u47_0_stall_in_0_reg_171_NO_SHIFT_REG),
.valid_out(rnode_170to171_bb1_var__u47_0_valid_out_0_reg_171_NO_SHIFT_REG),
.stall_out(rnode_170to171_bb1_var__u47_0_stall_out_reg_171_NO_SHIFT_REG),
.data_in(local_bb1_var__u47),
.data_out(rnode_170to171_bb1_var__u47_0_reg_171_NO_SHIFT_REG)
);
defparam rnode_170to171_bb1_var__u47_0_reg_171_fifo.DEPTH = 1;
defparam rnode_170to171_bb1_var__u47_0_reg_171_fifo.DATA_WIDTH = 8;
defparam rnode_170to171_bb1_var__u47_0_reg_171_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_170to171_bb1_var__u47_0_reg_171_fifo.IMPL = "shift_reg";
assign rnode_170to171_bb1_var__u47_0_reg_171_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_var__u47_stall_in = 1'b0;
assign rnode_170to171_bb1_var__u47_0_stall_in_0_reg_171_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_var__u47_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_var__u47_0_NO_SHIFT_REG = rnode_170to171_bb1_var__u47_0_reg_171_NO_SHIFT_REG;
assign rnode_170to171_bb1_var__u47_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_170to171_bb1_var__u47_1_NO_SHIFT_REG = rnode_170to171_bb1_var__u47_0_reg_171_NO_SHIFT_REG;
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_14_2_stall_local;
wire local_bb1_cmp19_14_2;
assign local_bb1_cmp19_14_2 = (rnode_170to171_bb1_var__u47_0_NO_SHIFT_REG == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__520_demorgan_stall_local;
wire local_bb1__520_demorgan;
assign local_bb1__520_demorgan = (rnode_170to171_bb1_cmp16_14_2_0_NO_SHIFT_REG | local_bb1_cmp19_14_2);
// This section implements an unregistered operation.
//
wire local_bb1__522_stall_local;
wire local_bb1__522;
assign local_bb1__522 = (local_bb1_cmp19_14_2 & local_bb1_not_cmp16_14_2);
// This section implements an unregistered operation.
//
wire local_bb1__521_op_stall_local;
wire [7:0] local_bb1__521_op;
assign local_bb1__521_op = (local_bb1__520_demorgan ? 8'h1 : rnode_170to171_bb1_var__u47_1_NO_SHIFT_REG);
// This section implements an unregistered operation.
//
wire local_bb1_var__u48_stall_local;
wire [7:0] local_bb1_var__u48;
assign local_bb1_var__u48 = (local_bb1__522 ? 8'h0 : local_bb1__521_op);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_15_2_stall_local;
wire local_bb1_cmp19_15_2;
assign local_bb1_cmp19_15_2 = (local_bb1_var__u48 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__524_demorgan_stall_local;
wire local_bb1__524_demorgan;
assign local_bb1__524_demorgan = (rnode_170to171_bb1_cmp16_15_2_0_NO_SHIFT_REG | local_bb1_cmp19_15_2);
// This section implements an unregistered operation.
//
wire local_bb1__526_stall_local;
wire local_bb1__526;
assign local_bb1__526 = (local_bb1_cmp19_15_2 & local_bb1_not_cmp16_15_2);
// This section implements an unregistered operation.
//
wire local_bb1__525_op_stall_local;
wire [7:0] local_bb1__525_op;
assign local_bb1__525_op = (local_bb1__524_demorgan ? 8'h1 : local_bb1_var__u48);
// This section implements an unregistered operation.
//
wire local_bb1_var__u49_stall_local;
wire [7:0] local_bb1_var__u49;
assign local_bb1_var__u49 = (local_bb1__526 ? 8'h0 : local_bb1__525_op);
// This section implements an unregistered operation.
//
wire local_bb1_cmp19_16_2_stall_local;
wire local_bb1_cmp19_16_2;
assign local_bb1_cmp19_16_2 = (local_bb1_var__u49 == 8'h0);
// This section implements an unregistered operation.
//
wire local_bb1__527_op_op_stall_local;
wire [7:0] local_bb1__527_op_op;
assign local_bb1__527_op_op = (local_bb1_var__u49 + 8'hFF);
// This section implements an unregistered operation.
//
wire local_bb1__528_demorgan_stall_local;
wire local_bb1__528_demorgan;
assign local_bb1__528_demorgan = (rnode_170to171_bb1_cmp16_16_2_0_NO_SHIFT_REG | local_bb1_cmp19_16_2);
// This section implements an unregistered operation.
//
wire local_bb1__530_stall_local;
wire local_bb1__530;
assign local_bb1__530 = (local_bb1_cmp19_16_2 & local_bb1_not_cmp16_16_2);
// This section implements an unregistered operation.
//
wire local_bb1__529_op_op_stall_local;
wire [7:0] local_bb1__529_op_op;
assign local_bb1__529_op_op = (local_bb1__528_demorgan ? 8'h0 : local_bb1__527_op_op);
// This section implements an unregistered operation.
//
wire local_bb1_sext_stall_local;
wire [7:0] local_bb1_sext;
assign local_bb1_sext = (local_bb1__530 ? 8'hFF : local_bb1__529_op_op);
// This section implements an unregistered operation.
//
wire local_bb1_c0_exi1_valid_out;
wire local_bb1_c0_exi1_stall_in;
wire local_bb1_c0_exi1_inputs_ready;
wire local_bb1_c0_exi1_stall_local;
wire [15:0] local_bb1_c0_exi1;
assign local_bb1_c0_exi1_inputs_ready = (rnode_170to171_bb1_cmp16_14_2_0_valid_out_0_NO_SHIFT_REG & rnode_170to171_bb1_var__u47_0_valid_out_1_NO_SHIFT_REG & rnode_170to171_bb1_cmp16_14_2_0_valid_out_1_NO_SHIFT_REG & rnode_170to171_bb1_cmp16_15_2_0_valid_out_0_NO_SHIFT_REG & rnode_170to171_bb1_cmp16_15_2_0_valid_out_1_NO_SHIFT_REG & rnode_170to171_bb1_var__u47_0_valid_out_0_NO_SHIFT_REG & rnode_170to171_bb1_cmp16_16_2_0_valid_out_0_NO_SHIFT_REG & rnode_170to171_bb1_cmp16_16_2_0_valid_out_1_NO_SHIFT_REG);
assign local_bb1_c0_exi1[7:0] = 8'bxxxxxxxx;
assign local_bb1_c0_exi1[15:8] = local_bb1_sext;
assign local_bb1_c0_exi1_valid_out = 1'b1;
assign rnode_170to171_bb1_cmp16_14_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_var__u47_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_14_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_15_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_15_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_var__u47_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_16_2_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_cmp16_16_2_0_stall_in_1_NO_SHIFT_REG = 1'b0;
// This section implements a registered operation.
//
wire local_bb1_c0_exit_c0_exi1_inputs_ready;
reg local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG;
wire local_bb1_c0_exit_c0_exi1_stall_in;
reg [15:0] local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG;
wire [15:0] local_bb1_c0_exit_c0_exi1_in;
wire local_bb1_c0_exit_c0_exi1_valid;
wire local_bb1_c0_exit_c0_exi1_causedstall;
acl_stall_free_sink local_bb1_c0_exit_c0_exi1_instance (
.clock(clock),
.resetn(resetn),
.data_in(local_bb1_c0_exi1),
.data_out(local_bb1_c0_exit_c0_exi1_in),
.input_accepted(local_bb1_c0_enter_c0_eni3_input_accepted),
.valid_out(local_bb1_c0_exit_c0_exi1_valid),
.stall_in(~(local_bb1_c0_exit_c0_exi1_output_regs_ready)),
.stall_entry(local_bb1_c0_exit_c0_exi1_entry_stall),
.valids(local_bb1_c0_exit_c0_exi1_valid_bits),
.IIphases(local_bb1_c0_exit_c0_exi1_phases),
.inc_pipelined_thread(local_bb1_c0_enter_c0_eni3_inc_pipelined_thread),
.dec_pipelined_thread(local_bb1_c0_enter_c0_eni3_dec_pipelined_thread)
);
defparam local_bb1_c0_exit_c0_exi1_instance.DATA_WIDTH = 16;
defparam local_bb1_c0_exit_c0_exi1_instance.PIPELINE_DEPTH = 14;
defparam local_bb1_c0_exit_c0_exi1_instance.SHARINGII = 1;
defparam local_bb1_c0_exit_c0_exi1_instance.SCHEDULEII = 1;
assign local_bb1_c0_exit_c0_exi1_inputs_ready = 1'b1;
assign local_bb1_c0_exit_c0_exi1_output_regs_ready = (&(~(local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG) | ~(local_bb1_c0_exit_c0_exi1_stall_in)));
assign local_bb1_c0_exi1_stall_in = 1'b0;
assign local_bb1__push51__pop50_stall_in = 1'b0;
assign local_bb1__push50__pop49_stall_in = 1'b0;
assign local_bb1__push49__pop48_stall_in = 1'b0;
assign rnode_170to171_bb1__push48__pop47_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push47__pop46_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push46__pop45_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push45__pop44_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push44__pop43_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push43__pop42_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push42__pop41_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push41__pop40_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push40__pop39_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push39__pop38_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push38__pop37_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1__push37__pop36_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1_rows_1933_0_push6_rows_1932_0_pop7_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1_rows_1934_0_push5_rows_1933_0_pop6_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1_rows_1935_0_push4_rows_1934_0_pop5_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__push36__coalesced_pop2_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_169to171_bb1__coalesced_push2_rows_1935_0_pop4_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1_0_push34_rows_0_0_pop35_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_2_0_push33_rows_1_0_pop34_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_3_0_push32_rows_2_0_pop33_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_4_0_push31_rows_3_0_pop32_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_5_0_push30_rows_4_0_pop31_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_0_0_push35_c0_ene3_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_7_0_push28_rows_6_0_pop29_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_15_0_push20_rows_14_0_pop21_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_8_0_push27_rows_7_0_pop28_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_14_0_push21_rows_13_0_pop22_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_9_0_push26_rows_8_0_pop27_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_10_0_push25_rows_9_0_pop26_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_11_0_push24_rows_10_0_pop25_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_13_0_push22_rows_12_0_pop23_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_6_0_push29_rows_5_0_pop30_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_coalesce_counter_push54_next_coalesce_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1920_0_push19_rows_1919_0_coalesced_pop3_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1919_0_coalesced_push3_rows_15_0_pop20_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1926_0_push13_rows_1925_0_pop14_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1925_0_push14_rows_1924_0_pop15_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1924_0_push15_rows_1923_0_pop16_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1923_0_push16_rows_1922_0_pop17_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_12_0_push23_rows_11_0_pop24_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1922_0_push17_rows_1921_0_pop18_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1921_0_push18_rows_1920_0_pop19_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1927_0_push12_rows_1926_0_pop13_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1928_0_push11_rows_1927_0_pop12_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1929_0_push10_rows_1928_0_pop11_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1930_0_push9_rows_1929_0_pop10_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1931_0_push8_rows_1930_0_pop9_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_170to171_bb1_rows_1932_0_push7_rows_1931_0_pop8_0_stall_in_NO_SHIFT_REG = 1'b0;
assign local_bb1_c0_exit_c0_exi1_causedstall = (1'b1 && (1'b0 && !(~(local_bb1_c0_exit_c0_exi1_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG <= 'x;
local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_c0_exit_c0_exi1_output_regs_ready)
begin
local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG <= local_bb1_c0_exit_c0_exi1_in;
local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG <= local_bb1_c0_exit_c0_exi1_valid;
end
else
begin
if (~(local_bb1_c0_exit_c0_exi1_stall_in))
begin
local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements an unregistered operation.
//
wire local_bb1_c0_exe1_valid_out;
wire local_bb1_c0_exe1_stall_in;
wire local_bb1_c0_exe1_inputs_ready;
wire local_bb1_c0_exe1_stall_local;
wire [7:0] local_bb1_c0_exe1;
assign local_bb1_c0_exe1_inputs_ready = local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG;
assign local_bb1_c0_exe1 = local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[15:8];
assign local_bb1_c0_exe1_valid_out = local_bb1_c0_exe1_inputs_ready;
assign local_bb1_c0_exe1_stall_local = local_bb1_c0_exe1_stall_in;
assign local_bb1_c0_exit_c0_exi1_stall_in = (|local_bb1_c0_exe1_stall_local);
// This section implements a registered operation.
//
wire local_bb1_st_c0_exe1_inputs_ready;
reg local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG;
wire local_bb1_st_c0_exe1_stall_in;
wire local_bb1_st_c0_exe1_output_regs_ready;
wire local_bb1_st_c0_exe1_fu_stall_out;
wire local_bb1_st_c0_exe1_fu_valid_out;
wire local_bb1_st_c0_exe1_causedstall;
lsu_top lsu_local_bb1_st_c0_exe1 (
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.flush(start),
.stream_base_addr(),
.stream_size(),
.stream_reset(),
.o_stall(local_bb1_st_c0_exe1_fu_stall_out),
.i_valid(local_bb1_st_c0_exe1_inputs_ready),
.i_address(rnode_175to176_bb1_arrayidx34_0_NO_SHIFT_REG),
.i_writedata(local_bb1_c0_exe1),
.i_cmpdata(),
.i_predicate(rnode_175to176_bb1_first_cleanup_xor_or_0_NO_SHIFT_REG),
.i_bitwiseor(64'h0),
.i_byteenable(),
.i_stall(~(local_bb1_st_c0_exe1_output_regs_ready)),
.o_valid(local_bb1_st_c0_exe1_fu_valid_out),
.o_readdata(),
.o_input_fifo_depth(),
.o_writeack(),
.i_atomic_op(3'h0),
.o_active(local_bb1_st_c0_exe1_active),
.avm_address(avm_local_bb1_st_c0_exe1_address),
.avm_read(avm_local_bb1_st_c0_exe1_read),
.avm_readdata(avm_local_bb1_st_c0_exe1_readdata),
.avm_write(avm_local_bb1_st_c0_exe1_write),
.avm_writeack(avm_local_bb1_st_c0_exe1_writeack),
.avm_burstcount(avm_local_bb1_st_c0_exe1_burstcount),
.avm_writedata(avm_local_bb1_st_c0_exe1_writedata),
.avm_byteenable(avm_local_bb1_st_c0_exe1_byteenable),
.avm_waitrequest(avm_local_bb1_st_c0_exe1_waitrequest),
.avm_readdatavalid(avm_local_bb1_st_c0_exe1_readdatavalid),
.profile_bw(),
.profile_bw_incr(),
.profile_total_ivalid(),
.profile_total_req(),
.profile_i_stall_count(),
.profile_o_stall_count(),
.profile_avm_readwrite_count(),
.profile_avm_burstcount_total(),
.profile_avm_burstcount_total_incr(),
.profile_req_cache_hit_count(),
.profile_extra_unaligned_reqs(),
.profile_avm_stall()
);
defparam lsu_local_bb1_st_c0_exe1.AWIDTH = 30;
defparam lsu_local_bb1_st_c0_exe1.WIDTH_BYTES = 1;
defparam lsu_local_bb1_st_c0_exe1.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_st_c0_exe1.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_st_c0_exe1.ALIGNMENT_BYTES = 1;
defparam lsu_local_bb1_st_c0_exe1.READ = 0;
defparam lsu_local_bb1_st_c0_exe1.ATOMIC = 0;
defparam lsu_local_bb1_st_c0_exe1.WIDTH = 8;
defparam lsu_local_bb1_st_c0_exe1.MWIDTH = 256;
defparam lsu_local_bb1_st_c0_exe1.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_st_c0_exe1.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_st_c0_exe1.KERNEL_SIDE_MEM_LATENCY = 4;
defparam lsu_local_bb1_st_c0_exe1.MEMORY_SIDE_MEM_LATENCY = 8;
defparam lsu_local_bb1_st_c0_exe1.USE_WRITE_ACK = 0;
defparam lsu_local_bb1_st_c0_exe1.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_st_c0_exe1.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_st_c0_exe1.NUMBER_BANKS = 1;
defparam lsu_local_bb1_st_c0_exe1.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_st_c0_exe1.USEINPUTFIFO = 0;
defparam lsu_local_bb1_st_c0_exe1.USECACHING = 0;
defparam lsu_local_bb1_st_c0_exe1.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_st_c0_exe1.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_st_c0_exe1.HIGH_FMAX = 1;
defparam lsu_local_bb1_st_c0_exe1.ADDRSPACE = 1;
defparam lsu_local_bb1_st_c0_exe1.STYLE = "BURST-COALESCED";
defparam lsu_local_bb1_st_c0_exe1.USE_BYTE_EN = 0;
assign local_bb1_st_c0_exe1_inputs_ready = (local_bb1_c0_exe1_valid_out & rnode_175to176_bb1_arrayidx34_0_valid_out_NO_SHIFT_REG & rnode_175to176_bb1_first_cleanup_xor_or_0_valid_out_NO_SHIFT_REG);
assign local_bb1_st_c0_exe1_output_regs_ready = (&(~(local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG) | ~(local_bb1_st_c0_exe1_stall_in)));
assign local_bb1_c0_exe1_stall_in = (local_bb1_st_c0_exe1_fu_stall_out | ~(local_bb1_st_c0_exe1_inputs_ready));
assign rnode_175to176_bb1_arrayidx34_0_stall_in_NO_SHIFT_REG = (local_bb1_st_c0_exe1_fu_stall_out | ~(local_bb1_st_c0_exe1_inputs_ready));
assign rnode_175to176_bb1_first_cleanup_xor_or_0_stall_in_NO_SHIFT_REG = (local_bb1_st_c0_exe1_fu_stall_out | ~(local_bb1_st_c0_exe1_inputs_ready));
assign local_bb1_st_c0_exe1_causedstall = (local_bb1_st_c0_exe1_inputs_ready && (local_bb1_st_c0_exe1_fu_stall_out && !(~(local_bb1_st_c0_exe1_output_regs_ready))));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (local_bb1_st_c0_exe1_output_regs_ready)
begin
local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG <= local_bb1_st_c0_exe1_fu_valid_out;
end
else
begin
if (~(local_bb1_st_c0_exe1_stall_in))
begin
local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
// This section implements a staging register.
//
wire rstag_180to180_bb1_st_c0_exe1_valid_out;
wire rstag_180to180_bb1_st_c0_exe1_stall_in;
wire rstag_180to180_bb1_st_c0_exe1_inputs_ready;
wire rstag_180to180_bb1_st_c0_exe1_stall_local;
reg rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG;
wire rstag_180to180_bb1_st_c0_exe1_combined_valid;
assign rstag_180to180_bb1_st_c0_exe1_inputs_ready = local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG;
assign rstag_180to180_bb1_st_c0_exe1_combined_valid = (rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG | rstag_180to180_bb1_st_c0_exe1_inputs_ready);
assign rstag_180to180_bb1_st_c0_exe1_valid_out = rstag_180to180_bb1_st_c0_exe1_combined_valid;
assign rstag_180to180_bb1_st_c0_exe1_stall_local = rstag_180to180_bb1_st_c0_exe1_stall_in;
assign local_bb1_st_c0_exe1_stall_in = (|rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (rstag_180to180_bb1_st_c0_exe1_stall_local)
begin
if (~(rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG))
begin
rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG <= rstag_180to180_bb1_st_c0_exe1_inputs_ready;
end
end
else
begin
rstag_180to180_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG <= 1'b0;
end
end
end
// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
reg branch_node_valid_out_0_NO_SHIFT_REG;
reg branch_compare_result_NO_SHIFT_REG;
wire branch_var__output_regs_ready;
wire combined_branch_stall_in_signal;
assign branch_var__inputs_ready = (rnode_179to180_bb1_initerations_push53_next_initerations_0_valid_out_NO_SHIFT_REG & rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_valid_out_NO_SHIFT_REG & rnode_179to180_bb1_lastiniteration_last_initeration_0_valid_out_NO_SHIFT_REG & rnode_179to180_bb1_cleanups_push55_next_cleanups_0_valid_out_NO_SHIFT_REG & rnode_179to180_bb1_masked_0_valid_out_NO_SHIFT_REG & rnode_179to180_bb1_notexitcond_notexit_0_valid_out_NO_SHIFT_REG & rstag_180to180_bb1_st_c0_exe1_valid_out);
assign branch_var__output_regs_ready = (~(branch_node_valid_out_0_NO_SHIFT_REG) | (((branch_compare_result_NO_SHIFT_REG != 1'b1) & ~(stall_in_1)) | (~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & ~(stall_in_0))));
assign rnode_179to180_bb1_initerations_push53_next_initerations_0_stall_in_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rnode_179to180_bb1_indvars_iv16_push52_indvars_iv_next17_0_stall_in_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rnode_179to180_bb1_lastiniteration_last_initeration_0_stall_in_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rnode_179to180_bb1_cleanups_push55_next_cleanups_0_stall_in_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rnode_179to180_bb1_masked_0_stall_in_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rnode_179to180_bb1_notexitcond_notexit_0_stall_in_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rstag_180to180_bb1_st_c0_exe1_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign valid_out_0 = (~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & branch_node_valid_out_0_NO_SHIFT_REG);
assign valid_out_1 = ((branch_compare_result_NO_SHIFT_REG != 1'b1) & branch_node_valid_out_0_NO_SHIFT_REG);
assign combined_branch_stall_in_signal = ((((branch_compare_result_NO_SHIFT_REG != 1'b1) & branch_node_valid_out_0_NO_SHIFT_REG) & stall_in_1) | ((~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & branch_node_valid_out_0_NO_SHIFT_REG) & stall_in_0));
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
branch_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
branch_compare_result_NO_SHIFT_REG <= 'x;
end
else
begin
if (branch_var__output_regs_ready)
begin
branch_node_valid_out_0_NO_SHIFT_REG <= branch_var__inputs_ready;
branch_compare_result_NO_SHIFT_REG <= rnode_179to180_bb1_masked_0_NO_SHIFT_REG;
end
else
begin
if (~(combined_branch_stall_in_signal))
begin
branch_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
end
end
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module erosion_basic_block_2
(
input clock,
input resetn,
input valid_in,
output stall_out,
output valid_out,
input stall_in,
input [31:0] workgroup_size,
input start
);
// Values used for debugging. These are swept away by synthesis.
wire _entry;
wire _exit;
reg [31:0] _num_entry_NO_SHIFT_REG;
reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;
assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
_num_entry_NO_SHIFT_REG <= 32'h0;
_num_exit_NO_SHIFT_REG <= 32'h0;
end
else
begin
if (_entry)
begin
_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
end
if (_exit)
begin
_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
end
end
end
// This section defines the behaviour of the MERGE node
wire merge_node_stall_in;
reg merge_node_valid_out_NO_SHIFT_REG;
wire merge_stalled_by_successors;
reg merge_block_selector_NO_SHIFT_REG;
reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
reg invariant_valid_NO_SHIFT_REG;
assign merge_stalled_by_successors = (|(merge_node_stall_in & merge_node_valid_out_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;
always @(*)
begin
if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
end
else
begin
merge_block_selector_NO_SHIFT_REG = 1'b0;
is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
begin
if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
end
end
else
begin
merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
end
else
begin
if (~(merge_stalled_by_successors))
begin
merge_node_valid_out_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
end
else
begin
if (~(merge_node_stall_in))
begin
merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
end
end
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
invariant_valid_NO_SHIFT_REG <= 1'b0;
end
else
begin
invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
end
end
// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
wire branch_var__output_regs_ready;
assign branch_var__inputs_ready = merge_node_valid_out_NO_SHIFT_REG;
assign branch_var__output_regs_ready = ~(stall_in);
assign merge_node_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign valid_out = branch_var__inputs_ready;
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module erosion_function
(
input clock,
input resetn,
output stall_out,
input valid_in,
output valid_out,
input stall_in,
input [255:0] avm_local_bb1_ld__readdata,
input avm_local_bb1_ld__readdatavalid,
input avm_local_bb1_ld__waitrequest,
output [29:0] avm_local_bb1_ld__address,
output avm_local_bb1_ld__read,
output avm_local_bb1_ld__write,
input avm_local_bb1_ld__writeack,
output [255:0] avm_local_bb1_ld__writedata,
output [31:0] avm_local_bb1_ld__byteenable,
output [4:0] avm_local_bb1_ld__burstcount,
input [255:0] avm_local_bb1_st_c0_exe1_readdata,
input avm_local_bb1_st_c0_exe1_readdatavalid,
input avm_local_bb1_st_c0_exe1_waitrequest,
output [29:0] avm_local_bb1_st_c0_exe1_address,
output avm_local_bb1_st_c0_exe1_read,
output avm_local_bb1_st_c0_exe1_write,
input avm_local_bb1_st_c0_exe1_writeack,
output [255:0] avm_local_bb1_st_c0_exe1_writedata,
output [31:0] avm_local_bb1_st_c0_exe1_byteenable,
output [4:0] avm_local_bb1_st_c0_exe1_burstcount,
input start,
input [31:0] input_iterations,
input clock2x,
input [63:0] input_img_in,
input [63:0] input_img_out,
output reg has_a_write_pending,
output reg has_a_lsu_active
);
wire [31:0] workgroup_size;
wire [31:0] cur_cycle;
wire bb_0_stall_out;
wire bb_0_valid_out;
wire bb_0_lvb_bb0_cmp6;
wire bb_1_stall_out_0;
wire bb_1_stall_out_1;
wire bb_1_valid_out_0;
wire bb_1_valid_out_1;
wire bb_1_feedback_stall_out_55;
wire bb_1_feedback_stall_out_0;
wire bb_1_feedback_stall_out_1;
wire bb_1_acl_pipelined_valid;
wire bb_1_acl_pipelined_exiting_valid;
wire bb_1_acl_pipelined_exiting_stall;
wire bb_1_feedback_stall_out_53;
wire bb_1_feedback_stall_out_52;
wire bb_1_feedback_valid_out_53;
wire [3:0] bb_1_feedback_data_out_53;
wire bb_1_feedback_valid_out_0;
wire bb_1_feedback_data_out_0;
wire bb_1_feedback_valid_out_52;
wire [63:0] bb_1_feedback_data_out_52;
wire bb_1_feedback_valid_out_55;
wire [3:0] bb_1_feedback_data_out_55;
wire bb_1_local_bb1_ld__active;
wire bb_1_feedback_valid_out_1;
wire bb_1_feedback_data_out_1;
wire bb_1_feedback_stall_out_34;
wire bb_1_feedback_stall_out_35;
wire bb_1_feedback_stall_out_33;
wire bb_1_feedback_stall_out_32;
wire bb_1_feedback_stall_out_31;
wire bb_1_feedback_stall_out_30;
wire bb_1_feedback_stall_out_28;
wire bb_1_feedback_stall_out_27;
wire bb_1_feedback_stall_out_26;
wire bb_1_feedback_stall_out_20;
wire bb_1_feedback_stall_out_19;
wire bb_1_feedback_stall_out_21;
wire bb_1_feedback_stall_out_22;
wire bb_1_feedback_stall_out_23;
wire bb_1_feedback_stall_out_24;
wire bb_1_feedback_stall_out_54;
wire bb_1_feedback_stall_out_25;
wire bb_1_feedback_stall_out_29;
wire bb_1_feedback_valid_out_35;
wire [7:0] bb_1_feedback_data_out_35;
wire bb_1_feedback_valid_out_31;
wire [7:0] bb_1_feedback_data_out_31;
wire bb_1_feedback_valid_out_30;
wire [7:0] bb_1_feedback_data_out_30;
wire bb_1_feedback_valid_out_29;
wire [7:0] bb_1_feedback_data_out_29;
wire bb_1_feedback_stall_out_13;
wire bb_1_feedback_stall_out_14;
wire bb_1_feedback_stall_out_15;
wire bb_1_feedback_stall_out_16;
wire bb_1_feedback_stall_out_17;
wire bb_1_feedback_stall_out_18;
wire bb_1_feedback_valid_out_3;
wire [7:0] bb_1_feedback_data_out_3;
wire bb_1_feedback_valid_out_18;
wire [7:0] bb_1_feedback_data_out_18;
wire bb_1_feedback_valid_out_20;
wire [7:0] bb_1_feedback_data_out_20;
wire bb_1_feedback_valid_out_21;
wire [7:0] bb_1_feedback_data_out_21;
wire bb_1_feedback_valid_out_22;
wire [7:0] bb_1_feedback_data_out_22;
wire bb_1_feedback_stall_out_3;
wire bb_1_feedback_stall_out_10;
wire bb_1_feedback_stall_out_8;
wire bb_1_feedback_stall_out_7;
wire bb_1_feedback_stall_out_9;
wire bb_1_feedback_stall_out_12;
wire bb_1_feedback_stall_out_11;
wire bb_1_feedback_valid_out_23;
wire [7:0] bb_1_feedback_data_out_23;
wire bb_1_feedback_valid_out_12;
wire [7:0] bb_1_feedback_data_out_12;
wire bb_1_feedback_valid_out_13;
wire [7:0] bb_1_feedback_data_out_13;
wire bb_1_feedback_valid_out_14;
wire [7:0] bb_1_feedback_data_out_14;
wire bb_1_feedback_valid_out_15;
wire [7:0] bb_1_feedback_data_out_15;
wire bb_1_feedback_valid_out_16;
wire [7:0] bb_1_feedback_data_out_16;
wire bb_1_feedback_valid_out_17;
wire [7:0] bb_1_feedback_data_out_17;
wire bb_1_feedback_stall_out_40;
wire bb_1_feedback_stall_out_41;
wire bb_1_feedback_stall_out_42;
wire bb_1_feedback_stall_out_36;
wire bb_1_feedback_stall_out_37;
wire bb_1_feedback_stall_out_38;
wire bb_1_feedback_stall_out_39;
wire bb_1_feedback_stall_out_6;
wire bb_1_feedback_stall_out_5;
wire bb_1_feedback_stall_out_4;
wire bb_1_feedback_valid_out_54;
wire [11:0] bb_1_feedback_data_out_54;
wire bb_1_feedback_valid_out_19;
wire [7:0] bb_1_feedback_data_out_19;
wire bb_1_feedback_valid_out_9;
wire [7:0] bb_1_feedback_data_out_9;
wire bb_1_feedback_valid_out_7;
wire [7:0] bb_1_feedback_data_out_7;
wire bb_1_feedback_valid_out_6;
wire [7:0] bb_1_feedback_data_out_6;
wire bb_1_feedback_valid_out_8;
wire [7:0] bb_1_feedback_data_out_8;
wire bb_1_feedback_valid_out_10;
wire [7:0] bb_1_feedback_data_out_10;
wire bb_1_feedback_stall_out_48;
wire bb_1_feedback_stall_out_43;
wire bb_1_feedback_stall_out_44;
wire bb_1_feedback_stall_out_46;
wire bb_1_feedback_stall_out_47;
wire bb_1_feedback_stall_out_45;
wire bb_1_feedback_valid_out_41;
wire [7:0] bb_1_feedback_data_out_41;
wire bb_1_feedback_valid_out_42;
wire [7:0] bb_1_feedback_data_out_42;
wire bb_1_feedback_valid_out_43;
wire [7:0] bb_1_feedback_data_out_43;
wire bb_1_feedback_valid_out_37;
wire [7:0] bb_1_feedback_data_out_37;
wire bb_1_feedback_valid_out_38;
wire [7:0] bb_1_feedback_data_out_38;
wire bb_1_feedback_valid_out_39;
wire [7:0] bb_1_feedback_data_out_39;
wire bb_1_feedback_valid_out_40;
wire [7:0] bb_1_feedback_data_out_40;
wire bb_1_feedback_stall_out_49;
wire bb_1_feedback_stall_out_50;
wire bb_1_feedback_stall_out_51;
wire bb_1_feedback_valid_out_49;
wire [7:0] bb_1_feedback_data_out_49;
wire bb_1_feedback_valid_out_44;
wire [7:0] bb_1_feedback_data_out_44;
wire bb_1_feedback_valid_out_45;
wire [7:0] bb_1_feedback_data_out_45;
wire bb_1_feedback_valid_out_47;
wire [7:0] bb_1_feedback_data_out_47;
wire bb_1_feedback_valid_out_48;
wire [7:0] bb_1_feedback_data_out_48;
wire bb_1_feedback_valid_out_46;
wire [7:0] bb_1_feedback_data_out_46;
wire bb_1_feedback_stall_out_2;
wire bb_1_feedback_valid_out_50;
wire [7:0] bb_1_feedback_data_out_50;
wire bb_1_feedback_valid_out_51;
wire [7:0] bb_1_feedback_data_out_51;
wire bb_1_feedback_valid_out_36;
wire [7:0] bb_1_feedback_data_out_36;
wire bb_1_feedback_valid_out_33;
wire [7:0] bb_1_feedback_data_out_33;
wire bb_1_feedback_valid_out_34;
wire [7:0] bb_1_feedback_data_out_34;
wire bb_1_feedback_valid_out_32;
wire [7:0] bb_1_feedback_data_out_32;
wire bb_1_feedback_valid_out_27;
wire [7:0] bb_1_feedback_data_out_27;
wire bb_1_feedback_valid_out_26;
wire [7:0] bb_1_feedback_data_out_26;
wire bb_1_feedback_valid_out_25;
wire [7:0] bb_1_feedback_data_out_25;
wire bb_1_feedback_valid_out_28;
wire [7:0] bb_1_feedback_data_out_28;
wire bb_1_feedback_valid_out_24;
wire [7:0] bb_1_feedback_data_out_24;
wire bb_1_feedback_valid_out_11;
wire [7:0] bb_1_feedback_data_out_11;
wire bb_1_feedback_valid_out_5;
wire [7:0] bb_1_feedback_data_out_5;
wire bb_1_feedback_valid_out_4;
wire [7:0] bb_1_feedback_data_out_4;
wire bb_1_feedback_valid_out_2;
wire [7:0] bb_1_feedback_data_out_2;
wire bb_1_local_bb1_st_c0_exe1_active;
wire bb_2_stall_out;
wire bb_2_valid_out;
wire feedback_stall_53;
wire feedback_valid_53;
wire [3:0] feedback_data_53;
wire feedback_stall_52;
wire feedback_valid_52;
wire [63:0] feedback_data_52;
wire feedback_stall_0;
wire feedback_valid_0;
wire feedback_data_0;
wire feedback_stall_51;
wire feedback_valid_51;
wire [7:0] feedback_data_51;
wire feedback_stall_50;
wire feedback_valid_50;
wire [7:0] feedback_data_50;
wire feedback_stall_49;
wire feedback_valid_49;
wire [7:0] feedback_data_49;
wire feedback_stall_48;
wire feedback_valid_48;
wire [7:0] feedback_data_48;
wire feedback_stall_47;
wire feedback_valid_47;
wire [7:0] feedback_data_47;
wire feedback_stall_46;
wire feedback_valid_46;
wire [7:0] feedback_data_46;
wire feedback_stall_45;
wire feedback_valid_45;
wire [7:0] feedback_data_45;
wire feedback_stall_44;
wire feedback_valid_44;
wire [7:0] feedback_data_44;
wire feedback_stall_43;
wire feedback_valid_43;
wire [7:0] feedback_data_43;
wire feedback_stall_42;
wire feedback_valid_42;
wire [7:0] feedback_data_42;
wire feedback_stall_41;
wire feedback_valid_41;
wire [7:0] feedback_data_41;
wire feedback_stall_40;
wire feedback_valid_40;
wire [7:0] feedback_data_40;
wire feedback_stall_39;
wire feedback_valid_39;
wire [7:0] feedback_data_39;
wire feedback_stall_38;
wire feedback_valid_38;
wire [7:0] feedback_data_38;
wire feedback_stall_37;
wire feedback_valid_37;
wire [7:0] feedback_data_37;
wire feedback_stall_34;
wire feedback_valid_34;
wire [7:0] feedback_data_34;
wire feedback_stall_33;
wire feedback_valid_33;
wire [7:0] feedback_data_33;
wire feedback_stall_32;
wire feedback_valid_32;
wire [7:0] feedback_data_32;
wire feedback_stall_31;
wire feedback_valid_31;
wire [7:0] feedback_data_31;
wire feedback_stall_30;
wire feedback_valid_30;
wire [7:0] feedback_data_30;
wire feedback_stall_29;
wire feedback_valid_29;
wire [7:0] feedback_data_29;
wire feedback_stall_28;
wire feedback_valid_28;
wire [7:0] feedback_data_28;
wire feedback_stall_27;
wire feedback_valid_27;
wire [7:0] feedback_data_27;
wire feedback_stall_26;
wire feedback_valid_26;
wire [7:0] feedback_data_26;
wire feedback_stall_25;
wire feedback_valid_25;
wire [7:0] feedback_data_25;
wire feedback_stall_24;
wire feedback_valid_24;
wire [7:0] feedback_data_24;
wire feedback_stall_23;
wire feedback_valid_23;
wire [7:0] feedback_data_23;
wire feedback_stall_22;
wire feedback_valid_22;
wire [7:0] feedback_data_22;
wire feedback_stall_21;
wire feedback_valid_21;
wire [7:0] feedback_data_21;
wire feedback_stall_20;
wire feedback_valid_20;
wire [7:0] feedback_data_20;
wire feedback_stall_18;
wire feedback_valid_18;
wire [7:0] feedback_data_18;
wire feedback_stall_17;
wire feedback_valid_17;
wire [7:0] feedback_data_17;
wire feedback_stall_16;
wire feedback_valid_16;
wire [7:0] feedback_data_16;
wire feedback_stall_15;
wire feedback_valid_15;
wire [7:0] feedback_data_15;
wire feedback_stall_14;
wire feedback_valid_14;
wire [7:0] feedback_data_14;
wire feedback_stall_13;
wire feedback_valid_13;
wire [7:0] feedback_data_13;
wire feedback_stall_12;
wire feedback_valid_12;
wire [7:0] feedback_data_12;
wire feedback_stall_11;
wire feedback_valid_11;
wire [7:0] feedback_data_11;
wire feedback_stall_10;
wire feedback_valid_10;
wire [7:0] feedback_data_10;
wire feedback_stall_9;
wire feedback_valid_9;
wire [7:0] feedback_data_9;
wire feedback_stall_8;
wire feedback_valid_8;
wire [7:0] feedback_data_8;
wire feedback_stall_7;
wire feedback_valid_7;
wire [7:0] feedback_data_7;
wire feedback_stall_6;
wire feedback_valid_6;
wire [7:0] feedback_data_6;
wire feedback_stall_5;
wire feedback_valid_5;
wire [7:0] feedback_data_5;
wire feedback_stall_4;
wire feedback_valid_4;
wire [7:0] feedback_data_4;
wire feedback_stall_54;
wire feedback_valid_54;
wire [11:0] feedback_data_54;
wire feedback_stall_19;
wire feedback_valid_19;
wire [7:0] feedback_data_19;
wire feedback_stall_3;
wire feedback_valid_3;
wire [7:0] feedback_data_3;
wire feedback_stall_36;
wire feedback_valid_36;
wire [7:0] feedback_data_36;
wire feedback_stall_2;
wire feedback_valid_2;
wire [7:0] feedback_data_2;
wire feedback_stall_35;
wire feedback_valid_35;
wire [7:0] feedback_data_35;
wire feedback_stall_1;
wire feedback_valid_1;
wire feedback_data_1;
wire feedback_stall_55;
wire feedback_valid_55;
wire [3:0] feedback_data_55;
wire loop_limiter_0_stall_out;
wire loop_limiter_0_valid_out;
wire writes_pending;
wire [1:0] lsus_active;
erosion_basic_block_0 erosion_basic_block_0 (
.clock(clock),
.resetn(resetn),
.start(start),
.input_iterations(input_iterations),
.valid_in(valid_in),
.stall_out(bb_0_stall_out),
.valid_out(bb_0_valid_out),
.stall_in(loop_limiter_0_stall_out),
.lvb_bb0_cmp6(bb_0_lvb_bb0_cmp6),
.workgroup_size(workgroup_size)
);
erosion_basic_block_1 erosion_basic_block_1 (
.clock(clock),
.resetn(resetn),
.input_img_in(input_img_in),
.input_img_out(input_img_out),
.input_iterations(input_iterations),
.input_wii_cmp6(bb_0_lvb_bb0_cmp6),
.valid_in_0(bb_1_acl_pipelined_valid),
.stall_out_0(bb_1_stall_out_0),
.input_forked_0(1'b0),
.valid_in_1(loop_limiter_0_valid_out),
.stall_out_1(bb_1_stall_out_1),
.input_forked_1(1'b1),
.valid_out_0(bb_1_valid_out_0),
.stall_in_0(bb_2_stall_out),
.valid_out_1(bb_1_valid_out_1),
.stall_in_1(1'b0),
.workgroup_size(workgroup_size),
.start(start),
.feedback_valid_in_55(feedback_valid_55),
.feedback_stall_out_55(feedback_stall_55),
.feedback_data_in_55(feedback_data_55),
.feedback_valid_in_0(feedback_valid_0),
.feedback_stall_out_0(feedback_stall_0),
.feedback_data_in_0(feedback_data_0),
.feedback_valid_in_1(feedback_valid_1),
.feedback_stall_out_1(feedback_stall_1),
.feedback_data_in_1(feedback_data_1),
.acl_pipelined_valid(bb_1_acl_pipelined_valid),
.acl_pipelined_stall(bb_1_stall_out_0),
.acl_pipelined_exiting_valid(bb_1_acl_pipelined_exiting_valid),
.acl_pipelined_exiting_stall(bb_1_acl_pipelined_exiting_stall),
.feedback_valid_in_53(feedback_valid_53),
.feedback_stall_out_53(feedback_stall_53),
.feedback_data_in_53(feedback_data_53),
.feedback_valid_in_52(feedback_valid_52),
.feedback_stall_out_52(feedback_stall_52),
.feedback_data_in_52(feedback_data_52),
.feedback_valid_out_53(feedback_valid_53),
.feedback_stall_in_53(feedback_stall_53),
.feedback_data_out_53(feedback_data_53),
.feedback_valid_out_0(feedback_valid_0),
.feedback_stall_in_0(feedback_stall_0),
.feedback_data_out_0(feedback_data_0),
.feedback_valid_out_52(feedback_valid_52),
.feedback_stall_in_52(feedback_stall_52),
.feedback_data_out_52(feedback_data_52),
.feedback_valid_out_55(feedback_valid_55),
.feedback_stall_in_55(feedback_stall_55),
.feedback_data_out_55(feedback_data_55),
.avm_local_bb1_ld__readdata(avm_local_bb1_ld__readdata),
.avm_local_bb1_ld__readdatavalid(avm_local_bb1_ld__readdatavalid),
.avm_local_bb1_ld__waitrequest(avm_local_bb1_ld__waitrequest),
.avm_local_bb1_ld__address(avm_local_bb1_ld__address),
.avm_local_bb1_ld__read(avm_local_bb1_ld__read),
.avm_local_bb1_ld__write(avm_local_bb1_ld__write),
.avm_local_bb1_ld__writeack(avm_local_bb1_ld__writeack),
.avm_local_bb1_ld__writedata(avm_local_bb1_ld__writedata),
.avm_local_bb1_ld__byteenable(avm_local_bb1_ld__byteenable),
.avm_local_bb1_ld__burstcount(avm_local_bb1_ld__burstcount),
.local_bb1_ld__active(bb_1_local_bb1_ld__active),
.clock2x(clock2x),
.feedback_valid_out_1(feedback_valid_1),
.feedback_stall_in_1(feedback_stall_1),
.feedback_data_out_1(feedback_data_1),
.feedback_valid_in_34(feedback_valid_34),
.feedback_stall_out_34(feedback_stall_34),
.feedback_data_in_34(feedback_data_34),
.feedback_valid_in_35(feedback_valid_35),
.feedback_stall_out_35(feedback_stall_35),
.feedback_data_in_35(feedback_data_35),
.feedback_valid_in_33(feedback_valid_33),
.feedback_stall_out_33(feedback_stall_33),
.feedback_data_in_33(feedback_data_33),
.feedback_valid_in_32(feedback_valid_32),
.feedback_stall_out_32(feedback_stall_32),
.feedback_data_in_32(feedback_data_32),
.feedback_valid_in_31(feedback_valid_31),
.feedback_stall_out_31(feedback_stall_31),
.feedback_data_in_31(feedback_data_31),
.feedback_valid_in_30(feedback_valid_30),
.feedback_stall_out_30(feedback_stall_30),
.feedback_data_in_30(feedback_data_30),
.feedback_valid_in_28(feedback_valid_28),
.feedback_stall_out_28(feedback_stall_28),
.feedback_data_in_28(feedback_data_28),
.feedback_valid_in_27(feedback_valid_27),
.feedback_stall_out_27(feedback_stall_27),
.feedback_data_in_27(feedback_data_27),
.feedback_valid_in_26(feedback_valid_26),
.feedback_stall_out_26(feedback_stall_26),
.feedback_data_in_26(feedback_data_26),
.feedback_valid_in_20(feedback_valid_20),
.feedback_stall_out_20(feedback_stall_20),
.feedback_data_in_20(feedback_data_20),
.feedback_valid_in_19(feedback_valid_19),
.feedback_stall_out_19(feedback_stall_19),
.feedback_data_in_19(feedback_data_19),
.feedback_valid_in_21(feedback_valid_21),
.feedback_stall_out_21(feedback_stall_21),
.feedback_data_in_21(feedback_data_21),
.feedback_valid_in_22(feedback_valid_22),
.feedback_stall_out_22(feedback_stall_22),
.feedback_data_in_22(feedback_data_22),
.feedback_valid_in_23(feedback_valid_23),
.feedback_stall_out_23(feedback_stall_23),
.feedback_data_in_23(feedback_data_23),
.feedback_valid_in_24(feedback_valid_24),
.feedback_stall_out_24(feedback_stall_24),
.feedback_data_in_24(feedback_data_24),
.feedback_valid_in_54(feedback_valid_54),
.feedback_stall_out_54(feedback_stall_54),
.feedback_data_in_54(feedback_data_54),
.feedback_valid_in_25(feedback_valid_25),
.feedback_stall_out_25(feedback_stall_25),
.feedback_data_in_25(feedback_data_25),
.feedback_valid_in_29(feedback_valid_29),
.feedback_stall_out_29(feedback_stall_29),
.feedback_data_in_29(feedback_data_29),
.feedback_valid_out_35(feedback_valid_35),
.feedback_stall_in_35(feedback_stall_35),
.feedback_data_out_35(feedback_data_35),
.feedback_valid_out_31(feedback_valid_31),
.feedback_stall_in_31(feedback_stall_31),
.feedback_data_out_31(feedback_data_31),
.feedback_valid_out_30(feedback_valid_30),
.feedback_stall_in_30(feedback_stall_30),
.feedback_data_out_30(feedback_data_30),
.feedback_valid_out_29(feedback_valid_29),
.feedback_stall_in_29(feedback_stall_29),
.feedback_data_out_29(feedback_data_29),
.feedback_valid_in_13(feedback_valid_13),
.feedback_stall_out_13(feedback_stall_13),
.feedback_data_in_13(feedback_data_13),
.feedback_valid_in_14(feedback_valid_14),
.feedback_stall_out_14(feedback_stall_14),
.feedback_data_in_14(feedback_data_14),
.feedback_valid_in_15(feedback_valid_15),
.feedback_stall_out_15(feedback_stall_15),
.feedback_data_in_15(feedback_data_15),
.feedback_valid_in_16(feedback_valid_16),
.feedback_stall_out_16(feedback_stall_16),
.feedback_data_in_16(feedback_data_16),
.feedback_valid_in_17(feedback_valid_17),
.feedback_stall_out_17(feedback_stall_17),
.feedback_data_in_17(feedback_data_17),
.feedback_valid_in_18(feedback_valid_18),
.feedback_stall_out_18(feedback_stall_18),
.feedback_data_in_18(feedback_data_18),
.feedback_valid_out_3(feedback_valid_3),
.feedback_stall_in_3(feedback_stall_3),
.feedback_data_out_3(feedback_data_3),
.feedback_valid_out_18(feedback_valid_18),
.feedback_stall_in_18(feedback_stall_18),
.feedback_data_out_18(feedback_data_18),
.feedback_valid_out_20(feedback_valid_20),
.feedback_stall_in_20(feedback_stall_20),
.feedback_data_out_20(feedback_data_20),
.feedback_valid_out_21(feedback_valid_21),
.feedback_stall_in_21(feedback_stall_21),
.feedback_data_out_21(feedback_data_21),
.feedback_valid_out_22(feedback_valid_22),
.feedback_stall_in_22(feedback_stall_22),
.feedback_data_out_22(feedback_data_22),
.feedback_valid_in_3(feedback_valid_3),
.feedback_stall_out_3(feedback_stall_3),
.feedback_data_in_3(feedback_data_3),
.feedback_valid_in_10(feedback_valid_10),
.feedback_stall_out_10(feedback_stall_10),
.feedback_data_in_10(feedback_data_10),
.feedback_valid_in_8(feedback_valid_8),
.feedback_stall_out_8(feedback_stall_8),
.feedback_data_in_8(feedback_data_8),
.feedback_valid_in_7(feedback_valid_7),
.feedback_stall_out_7(feedback_stall_7),
.feedback_data_in_7(feedback_data_7),
.feedback_valid_in_9(feedback_valid_9),
.feedback_stall_out_9(feedback_stall_9),
.feedback_data_in_9(feedback_data_9),
.feedback_valid_in_12(feedback_valid_12),
.feedback_stall_out_12(feedback_stall_12),
.feedback_data_in_12(feedback_data_12),
.feedback_valid_in_11(feedback_valid_11),
.feedback_stall_out_11(feedback_stall_11),
.feedback_data_in_11(feedback_data_11),
.feedback_valid_out_23(feedback_valid_23),
.feedback_stall_in_23(feedback_stall_23),
.feedback_data_out_23(feedback_data_23),
.feedback_valid_out_12(feedback_valid_12),
.feedback_stall_in_12(feedback_stall_12),
.feedback_data_out_12(feedback_data_12),
.feedback_valid_out_13(feedback_valid_13),
.feedback_stall_in_13(feedback_stall_13),
.feedback_data_out_13(feedback_data_13),
.feedback_valid_out_14(feedback_valid_14),
.feedback_stall_in_14(feedback_stall_14),
.feedback_data_out_14(feedback_data_14),
.feedback_valid_out_15(feedback_valid_15),
.feedback_stall_in_15(feedback_stall_15),
.feedback_data_out_15(feedback_data_15),
.feedback_valid_out_16(feedback_valid_16),
.feedback_stall_in_16(feedback_stall_16),
.feedback_data_out_16(feedback_data_16),
.feedback_valid_out_17(feedback_valid_17),
.feedback_stall_in_17(feedback_stall_17),
.feedback_data_out_17(feedback_data_17),
.feedback_valid_in_40(feedback_valid_40),
.feedback_stall_out_40(feedback_stall_40),
.feedback_data_in_40(feedback_data_40),
.feedback_valid_in_41(feedback_valid_41),
.feedback_stall_out_41(feedback_stall_41),
.feedback_data_in_41(feedback_data_41),
.feedback_valid_in_42(feedback_valid_42),
.feedback_stall_out_42(feedback_stall_42),
.feedback_data_in_42(feedback_data_42),
.feedback_valid_in_36(feedback_valid_36),
.feedback_stall_out_36(feedback_stall_36),
.feedback_data_in_36(feedback_data_36),
.feedback_valid_in_37(feedback_valid_37),
.feedback_stall_out_37(feedback_stall_37),
.feedback_data_in_37(feedback_data_37),
.feedback_valid_in_38(feedback_valid_38),
.feedback_stall_out_38(feedback_stall_38),
.feedback_data_in_38(feedback_data_38),
.feedback_valid_in_39(feedback_valid_39),
.feedback_stall_out_39(feedback_stall_39),
.feedback_data_in_39(feedback_data_39),
.feedback_valid_in_6(feedback_valid_6),
.feedback_stall_out_6(feedback_stall_6),
.feedback_data_in_6(feedback_data_6),
.feedback_valid_in_5(feedback_valid_5),
.feedback_stall_out_5(feedback_stall_5),
.feedback_data_in_5(feedback_data_5),
.feedback_valid_in_4(feedback_valid_4),
.feedback_stall_out_4(feedback_stall_4),
.feedback_data_in_4(feedback_data_4),
.feedback_valid_out_54(feedback_valid_54),
.feedback_stall_in_54(feedback_stall_54),
.feedback_data_out_54(feedback_data_54),
.feedback_valid_out_19(feedback_valid_19),
.feedback_stall_in_19(feedback_stall_19),
.feedback_data_out_19(feedback_data_19),
.feedback_valid_out_9(feedback_valid_9),
.feedback_stall_in_9(feedback_stall_9),
.feedback_data_out_9(feedback_data_9),
.feedback_valid_out_7(feedback_valid_7),
.feedback_stall_in_7(feedback_stall_7),
.feedback_data_out_7(feedback_data_7),
.feedback_valid_out_6(feedback_valid_6),
.feedback_stall_in_6(feedback_stall_6),
.feedback_data_out_6(feedback_data_6),
.feedback_valid_out_8(feedback_valid_8),
.feedback_stall_in_8(feedback_stall_8),
.feedback_data_out_8(feedback_data_8),
.feedback_valid_out_10(feedback_valid_10),
.feedback_stall_in_10(feedback_stall_10),
.feedback_data_out_10(feedback_data_10),
.feedback_valid_in_48(feedback_valid_48),
.feedback_stall_out_48(feedback_stall_48),
.feedback_data_in_48(feedback_data_48),
.feedback_valid_in_43(feedback_valid_43),
.feedback_stall_out_43(feedback_stall_43),
.feedback_data_in_43(feedback_data_43),
.feedback_valid_in_44(feedback_valid_44),
.feedback_stall_out_44(feedback_stall_44),
.feedback_data_in_44(feedback_data_44),
.feedback_valid_in_46(feedback_valid_46),
.feedback_stall_out_46(feedback_stall_46),
.feedback_data_in_46(feedback_data_46),
.feedback_valid_in_47(feedback_valid_47),
.feedback_stall_out_47(feedback_stall_47),
.feedback_data_in_47(feedback_data_47),
.feedback_valid_in_45(feedback_valid_45),
.feedback_stall_out_45(feedback_stall_45),
.feedback_data_in_45(feedback_data_45),
.feedback_valid_out_41(feedback_valid_41),
.feedback_stall_in_41(feedback_stall_41),
.feedback_data_out_41(feedback_data_41),
.feedback_valid_out_42(feedback_valid_42),
.feedback_stall_in_42(feedback_stall_42),
.feedback_data_out_42(feedback_data_42),
.feedback_valid_out_43(feedback_valid_43),
.feedback_stall_in_43(feedback_stall_43),
.feedback_data_out_43(feedback_data_43),
.feedback_valid_out_37(feedback_valid_37),
.feedback_stall_in_37(feedback_stall_37),
.feedback_data_out_37(feedback_data_37),
.feedback_valid_out_38(feedback_valid_38),
.feedback_stall_in_38(feedback_stall_38),
.feedback_data_out_38(feedback_data_38),
.feedback_valid_out_39(feedback_valid_39),
.feedback_stall_in_39(feedback_stall_39),
.feedback_data_out_39(feedback_data_39),
.feedback_valid_out_40(feedback_valid_40),
.feedback_stall_in_40(feedback_stall_40),
.feedback_data_out_40(feedback_data_40),
.feedback_valid_in_49(feedback_valid_49),
.feedback_stall_out_49(feedback_stall_49),
.feedback_data_in_49(feedback_data_49),
.feedback_valid_in_50(feedback_valid_50),
.feedback_stall_out_50(feedback_stall_50),
.feedback_data_in_50(feedback_data_50),
.feedback_valid_in_51(feedback_valid_51),
.feedback_stall_out_51(feedback_stall_51),
.feedback_data_in_51(feedback_data_51),
.feedback_valid_out_49(feedback_valid_49),
.feedback_stall_in_49(feedback_stall_49),
.feedback_data_out_49(feedback_data_49),
.feedback_valid_out_44(feedback_valid_44),
.feedback_stall_in_44(feedback_stall_44),
.feedback_data_out_44(feedback_data_44),
.feedback_valid_out_45(feedback_valid_45),
.feedback_stall_in_45(feedback_stall_45),
.feedback_data_out_45(feedback_data_45),
.feedback_valid_out_47(feedback_valid_47),
.feedback_stall_in_47(feedback_stall_47),
.feedback_data_out_47(feedback_data_47),
.feedback_valid_out_48(feedback_valid_48),
.feedback_stall_in_48(feedback_stall_48),
.feedback_data_out_48(feedback_data_48),
.feedback_valid_out_46(feedback_valid_46),
.feedback_stall_in_46(feedback_stall_46),
.feedback_data_out_46(feedback_data_46),
.feedback_valid_in_2(feedback_valid_2),
.feedback_stall_out_2(feedback_stall_2),
.feedback_data_in_2(feedback_data_2),
.feedback_valid_out_50(feedback_valid_50),
.feedback_stall_in_50(feedback_stall_50),
.feedback_data_out_50(feedback_data_50),
.feedback_valid_out_51(feedback_valid_51),
.feedback_stall_in_51(feedback_stall_51),
.feedback_data_out_51(feedback_data_51),
.feedback_valid_out_36(feedback_valid_36),
.feedback_stall_in_36(feedback_stall_36),
.feedback_data_out_36(feedback_data_36),
.feedback_valid_out_33(feedback_valid_33),
.feedback_stall_in_33(feedback_stall_33),
.feedback_data_out_33(feedback_data_33),
.feedback_valid_out_34(feedback_valid_34),
.feedback_stall_in_34(feedback_stall_34),
.feedback_data_out_34(feedback_data_34),
.feedback_valid_out_32(feedback_valid_32),
.feedback_stall_in_32(feedback_stall_32),
.feedback_data_out_32(feedback_data_32),
.feedback_valid_out_27(feedback_valid_27),
.feedback_stall_in_27(feedback_stall_27),
.feedback_data_out_27(feedback_data_27),
.feedback_valid_out_26(feedback_valid_26),
.feedback_stall_in_26(feedback_stall_26),
.feedback_data_out_26(feedback_data_26),
.feedback_valid_out_25(feedback_valid_25),
.feedback_stall_in_25(feedback_stall_25),
.feedback_data_out_25(feedback_data_25),
.feedback_valid_out_28(feedback_valid_28),
.feedback_stall_in_28(feedback_stall_28),
.feedback_data_out_28(feedback_data_28),
.feedback_valid_out_24(feedback_valid_24),
.feedback_stall_in_24(feedback_stall_24),
.feedback_data_out_24(feedback_data_24),
.feedback_valid_out_11(feedback_valid_11),
.feedback_stall_in_11(feedback_stall_11),
.feedback_data_out_11(feedback_data_11),
.feedback_valid_out_5(feedback_valid_5),
.feedback_stall_in_5(feedback_stall_5),
.feedback_data_out_5(feedback_data_5),
.feedback_valid_out_4(feedback_valid_4),
.feedback_stall_in_4(feedback_stall_4),
.feedback_data_out_4(feedback_data_4),
.feedback_valid_out_2(feedback_valid_2),
.feedback_stall_in_2(feedback_stall_2),
.feedback_data_out_2(feedback_data_2),
.avm_local_bb1_st_c0_exe1_readdata(avm_local_bb1_st_c0_exe1_readdata),
.avm_local_bb1_st_c0_exe1_readdatavalid(avm_local_bb1_st_c0_exe1_readdatavalid),
.avm_local_bb1_st_c0_exe1_waitrequest(avm_local_bb1_st_c0_exe1_waitrequest),
.avm_local_bb1_st_c0_exe1_address(avm_local_bb1_st_c0_exe1_address),
.avm_local_bb1_st_c0_exe1_read(avm_local_bb1_st_c0_exe1_read),
.avm_local_bb1_st_c0_exe1_write(avm_local_bb1_st_c0_exe1_write),
.avm_local_bb1_st_c0_exe1_writeack(avm_local_bb1_st_c0_exe1_writeack),
.avm_local_bb1_st_c0_exe1_writedata(avm_local_bb1_st_c0_exe1_writedata),
.avm_local_bb1_st_c0_exe1_byteenable(avm_local_bb1_st_c0_exe1_byteenable),
.avm_local_bb1_st_c0_exe1_burstcount(avm_local_bb1_st_c0_exe1_burstcount),
.local_bb1_st_c0_exe1_active(bb_1_local_bb1_st_c0_exe1_active)
);
erosion_basic_block_2 erosion_basic_block_2 (
.clock(clock),
.resetn(resetn),
.valid_in(bb_1_valid_out_0),
.stall_out(bb_2_stall_out),
.valid_out(bb_2_valid_out),
.stall_in(stall_in),
.workgroup_size(workgroup_size),
.start(start)
);
acl_loop_limiter loop_limiter_0 (
.clock(clock),
.resetn(resetn),
.i_valid(bb_0_valid_out),
.i_stall(bb_1_stall_out_1),
.i_valid_exit(bb_1_acl_pipelined_exiting_valid),
.i_stall_exit(bb_1_acl_pipelined_exiting_stall),
.o_valid(loop_limiter_0_valid_out),
.o_stall(loop_limiter_0_stall_out)
);
defparam loop_limiter_0.ENTRY_WIDTH = 1;
defparam loop_limiter_0.EXIT_WIDTH = 1;
defparam loop_limiter_0.THRESHOLD = 1;
erosion_sys_cycle_time system_cycle_time_module (
.clock(clock),
.resetn(resetn),
.cur_cycle(cur_cycle)
);
assign workgroup_size = 32'h1;
assign valid_out = bb_2_valid_out;
assign stall_out = bb_0_stall_out;
assign writes_pending = bb_1_local_bb1_st_c0_exe1_active;
assign lsus_active[0] = bb_1_local_bb1_ld__active;
assign lsus_active[1] = bb_1_local_bb1_st_c0_exe1_active;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
has_a_write_pending <= 1'b0;
has_a_lsu_active <= 1'b0;
end
else
begin
has_a_write_pending <= (|writes_pending);
has_a_lsu_active <= (|lsus_active);
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module erosion_function_wrapper
(
input clock,
input resetn,
input clock2x,
input local_router_hang,
input avs_cra_read,
input avs_cra_write,
input [3:0] avs_cra_address,
input [63:0] avs_cra_writedata,
input [7:0] avs_cra_byteenable,
output avs_cra_waitrequest,
output reg [63:0] avs_cra_readdata,
output reg avs_cra_readdatavalid,
output cra_irq,
input [255:0] avm_local_bb1_ld__inst0_readdata,
input avm_local_bb1_ld__inst0_readdatavalid,
input avm_local_bb1_ld__inst0_waitrequest,
output [29:0] avm_local_bb1_ld__inst0_address,
output avm_local_bb1_ld__inst0_read,
output avm_local_bb1_ld__inst0_write,
input avm_local_bb1_ld__inst0_writeack,
output [255:0] avm_local_bb1_ld__inst0_writedata,
output [31:0] avm_local_bb1_ld__inst0_byteenable,
output [4:0] avm_local_bb1_ld__inst0_burstcount,
input [255:0] avm_local_bb1_st_c0_exe1_inst0_readdata,
input avm_local_bb1_st_c0_exe1_inst0_readdatavalid,
input avm_local_bb1_st_c0_exe1_inst0_waitrequest,
output [29:0] avm_local_bb1_st_c0_exe1_inst0_address,
output avm_local_bb1_st_c0_exe1_inst0_read,
output avm_local_bb1_st_c0_exe1_inst0_write,
input avm_local_bb1_st_c0_exe1_inst0_writeack,
output [255:0] avm_local_bb1_st_c0_exe1_inst0_writedata,
output [31:0] avm_local_bb1_st_c0_exe1_inst0_byteenable,
output [4:0] avm_local_bb1_st_c0_exe1_inst0_burstcount
);
// Responsible for interfacing a kernel with the outside world. It comprises a
// slave interface to specify the kernel arguments and retain kernel status.
// This section of the wrapper implements the slave interface.
// twoXclock_consumer uses clock2x, even if nobody inside the kernel does. Keeps interface to acl_iface consistent for all kernels.
reg start_NO_SHIFT_REG;
reg started_NO_SHIFT_REG;
wire finish;
reg [31:0] status_NO_SHIFT_REG;
wire has_a_write_pending;
wire has_a_lsu_active;
reg [159:0] kernel_arguments_NO_SHIFT_REG;
reg twoXclock_consumer_NO_SHIFT_REG /* synthesis preserve noprune */;
reg [31:0] workgroup_size_NO_SHIFT_REG;
reg [31:0] global_size_NO_SHIFT_REG[2:0];
reg [31:0] num_groups_NO_SHIFT_REG[2:0];
reg [31:0] local_size_NO_SHIFT_REG[2:0];
reg [31:0] work_dim_NO_SHIFT_REG;
reg [31:0] global_offset_NO_SHIFT_REG[2:0];
reg [63:0] profile_data_NO_SHIFT_REG;
reg [31:0] profile_ctrl_NO_SHIFT_REG;
reg [63:0] profile_start_cycle_NO_SHIFT_REG;
reg [63:0] profile_stop_cycle_NO_SHIFT_REG;
wire dispatched_all_groups;
wire [31:0] group_id_tmp[2:0];
wire [31:0] global_id_base_out[2:0];
wire start_out;
wire [31:0] local_id[0:0][2:0];
wire [31:0] global_id[0:0][2:0];
wire [31:0] group_id[0:0][2:0];
wire iter_valid_in;
wire iter_stall_out;
wire stall_in;
wire stall_out;
wire valid_in;
wire valid_out;
always @(posedge clock2x or negedge resetn)
begin
if (~(resetn))
begin
twoXclock_consumer_NO_SHIFT_REG <= 1'b0;
end
else
begin
twoXclock_consumer_NO_SHIFT_REG <= 1'b1;
end
end
// Work group dispatcher is responsible for issuing work-groups to id iterator(s)
acl_work_group_dispatcher group_dispatcher (
.clock(clock),
.resetn(resetn),
.start(start_NO_SHIFT_REG),
.num_groups(num_groups_NO_SHIFT_REG),
.local_size(local_size_NO_SHIFT_REG),
.stall_in(iter_stall_out),
.valid_out(iter_valid_in),
.group_id_out(group_id_tmp),
.global_id_base_out(global_id_base_out),
.start_out(start_out),
.dispatched_all_groups(dispatched_all_groups)
);
defparam group_dispatcher.NUM_COPIES = 1;
defparam group_dispatcher.RUN_FOREVER = 0;
// This section of the wrapper implements an Avalon Slave Interface used to configure a kernel invocation.
// The few words words contain the status and the workgroup size registers.
// The remaining addressable space is reserved for kernel arguments.
wire [63:0] bitenable;
assign bitenable[7:0] = (avs_cra_byteenable[0] ? 8'hFF : 8'h0);
assign bitenable[15:8] = (avs_cra_byteenable[1] ? 8'hFF : 8'h0);
assign bitenable[23:16] = (avs_cra_byteenable[2] ? 8'hFF : 8'h0);
assign bitenable[31:24] = (avs_cra_byteenable[3] ? 8'hFF : 8'h0);
assign bitenable[39:32] = (avs_cra_byteenable[4] ? 8'hFF : 8'h0);
assign bitenable[47:40] = (avs_cra_byteenable[5] ? 8'hFF : 8'h0);
assign bitenable[55:48] = (avs_cra_byteenable[6] ? 8'hFF : 8'h0);
assign bitenable[63:56] = (avs_cra_byteenable[7] ? 8'hFF : 8'h0);
assign avs_cra_waitrequest = 1'b0;
assign cra_irq = (status_NO_SHIFT_REG[1] | status_NO_SHIFT_REG[3]);
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
start_NO_SHIFT_REG <= 1'b0;
started_NO_SHIFT_REG <= 1'b0;
kernel_arguments_NO_SHIFT_REG <= 160'h0;
status_NO_SHIFT_REG <= 32'h30000;
profile_ctrl_NO_SHIFT_REG <= 32'h4;
profile_start_cycle_NO_SHIFT_REG <= 64'h0;
profile_stop_cycle_NO_SHIFT_REG <= 64'hFFFFFFFFFFFFFFFF;
work_dim_NO_SHIFT_REG <= 32'h0;
workgroup_size_NO_SHIFT_REG <= 32'h0;
global_size_NO_SHIFT_REG[0] <= 32'h0;
global_size_NO_SHIFT_REG[1] <= 32'h0;
global_size_NO_SHIFT_REG[2] <= 32'h0;
num_groups_NO_SHIFT_REG[0] <= 32'h0;
num_groups_NO_SHIFT_REG[1] <= 32'h0;
num_groups_NO_SHIFT_REG[2] <= 32'h0;
local_size_NO_SHIFT_REG[0] <= 32'h0;
local_size_NO_SHIFT_REG[1] <= 32'h0;
local_size_NO_SHIFT_REG[2] <= 32'h0;
global_offset_NO_SHIFT_REG[0] <= 32'h0;
global_offset_NO_SHIFT_REG[1] <= 32'h0;
global_offset_NO_SHIFT_REG[2] <= 32'h0;
end
else
begin
if (avs_cra_write)
begin
case (avs_cra_address)
4'h0:
begin
status_NO_SHIFT_REG[31:16] <= 16'h3;
status_NO_SHIFT_REG[15:0] <= ((status_NO_SHIFT_REG[15:0] & ~(bitenable[15:0])) | (avs_cra_writedata[15:0] & bitenable[15:0]));
end
4'h1:
begin
profile_ctrl_NO_SHIFT_REG <= ((profile_ctrl_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h3:
begin
profile_start_cycle_NO_SHIFT_REG[31:0] <= ((profile_start_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
profile_start_cycle_NO_SHIFT_REG[63:32] <= ((profile_start_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h4:
begin
profile_stop_cycle_NO_SHIFT_REG[31:0] <= ((profile_stop_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
profile_stop_cycle_NO_SHIFT_REG[63:32] <= ((profile_stop_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h5:
begin
work_dim_NO_SHIFT_REG <= ((work_dim_NO_SHIFT_REG & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
workgroup_size_NO_SHIFT_REG <= ((workgroup_size_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h6:
begin
global_size_NO_SHIFT_REG[0] <= ((global_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
global_size_NO_SHIFT_REG[1] <= ((global_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h7:
begin
global_size_NO_SHIFT_REG[2] <= ((global_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
num_groups_NO_SHIFT_REG[0] <= ((num_groups_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h8:
begin
num_groups_NO_SHIFT_REG[1] <= ((num_groups_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
num_groups_NO_SHIFT_REG[2] <= ((num_groups_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'h9:
begin
local_size_NO_SHIFT_REG[0] <= ((local_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
local_size_NO_SHIFT_REG[1] <= ((local_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hA:
begin
local_size_NO_SHIFT_REG[2] <= ((local_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
global_offset_NO_SHIFT_REG[0] <= ((global_offset_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hB:
begin
global_offset_NO_SHIFT_REG[1] <= ((global_offset_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
global_offset_NO_SHIFT_REG[2] <= ((global_offset_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hC:
begin
kernel_arguments_NO_SHIFT_REG[31:0] <= ((kernel_arguments_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
kernel_arguments_NO_SHIFT_REG[63:32] <= ((kernel_arguments_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hD:
begin
kernel_arguments_NO_SHIFT_REG[95:64] <= ((kernel_arguments_NO_SHIFT_REG[95:64] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
kernel_arguments_NO_SHIFT_REG[127:96] <= ((kernel_arguments_NO_SHIFT_REG[127:96] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
end
4'hE:
begin
kernel_arguments_NO_SHIFT_REG[159:128] <= ((kernel_arguments_NO_SHIFT_REG[159:128] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
end
default:
begin
end
endcase
end
else
begin
if (status_NO_SHIFT_REG[0])
begin
start_NO_SHIFT_REG <= 1'b1;
end
if (start_NO_SHIFT_REG)
begin
status_NO_SHIFT_REG[0] <= 1'b0;
started_NO_SHIFT_REG <= 1'b1;
end
if (started_NO_SHIFT_REG)
begin
start_NO_SHIFT_REG <= 1'b0;
end
if (finish)
begin
status_NO_SHIFT_REG[1] <= 1'b1;
started_NO_SHIFT_REG <= 1'b0;
end
end
status_NO_SHIFT_REG[11] <= local_router_hang;
status_NO_SHIFT_REG[12] <= (|has_a_lsu_active);
status_NO_SHIFT_REG[13] <= (|has_a_write_pending);
status_NO_SHIFT_REG[14] <= (|valid_in);
status_NO_SHIFT_REG[15] <= started_NO_SHIFT_REG;
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
avs_cra_readdata <= 64'h0;
end
else
begin
case (avs_cra_address)
4'h0:
begin
avs_cra_readdata[31:0] <= status_NO_SHIFT_REG;
avs_cra_readdata[63:32] <= 32'h0;
end
4'h1:
begin
avs_cra_readdata[31:0] <= 'x;
avs_cra_readdata[63:32] <= 32'h0;
end
4'h2:
begin
avs_cra_readdata[63:0] <= 64'h0;
end
4'h3:
begin
avs_cra_readdata[63:0] <= 64'h0;
end
4'h4:
begin
avs_cra_readdata[63:0] <= 64'h0;
end
4'h5:
begin
avs_cra_readdata[31:0] <= work_dim_NO_SHIFT_REG;
avs_cra_readdata[63:32] <= workgroup_size_NO_SHIFT_REG;
end
4'h6:
begin
avs_cra_readdata[31:0] <= global_size_NO_SHIFT_REG[0];
avs_cra_readdata[63:32] <= global_size_NO_SHIFT_REG[1];
end
4'h7:
begin
avs_cra_readdata[31:0] <= global_size_NO_SHIFT_REG[2];
avs_cra_readdata[63:32] <= num_groups_NO_SHIFT_REG[0];
end
4'h8:
begin
avs_cra_readdata[31:0] <= num_groups_NO_SHIFT_REG[1];
avs_cra_readdata[63:32] <= num_groups_NO_SHIFT_REG[2];
end
4'h9:
begin
avs_cra_readdata[31:0] <= local_size_NO_SHIFT_REG[0];
avs_cra_readdata[63:32] <= local_size_NO_SHIFT_REG[1];
end
4'hA:
begin
avs_cra_readdata[31:0] <= local_size_NO_SHIFT_REG[2];
avs_cra_readdata[63:32] <= global_offset_NO_SHIFT_REG[0];
end
4'hB:
begin
avs_cra_readdata[31:0] <= global_offset_NO_SHIFT_REG[1];
avs_cra_readdata[63:32] <= global_offset_NO_SHIFT_REG[2];
end
4'hC:
begin
avs_cra_readdata[31:0] <= kernel_arguments_NO_SHIFT_REG[31:0];
avs_cra_readdata[63:32] <= kernel_arguments_NO_SHIFT_REG[63:32];
end
4'hD:
begin
avs_cra_readdata[31:0] <= kernel_arguments_NO_SHIFT_REG[95:64];
avs_cra_readdata[63:32] <= kernel_arguments_NO_SHIFT_REG[127:96];
end
4'hE:
begin
avs_cra_readdata[31:0] <= kernel_arguments_NO_SHIFT_REG[159:128];
avs_cra_readdata[63:32] <= 32'h0;
end
default:
begin
avs_cra_readdata <= status_NO_SHIFT_REG;
end
endcase
end
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
avs_cra_readdatavalid <= 1'b0;
end
else
begin
avs_cra_readdatavalid <= (avs_cra_read & ~(avs_cra_waitrequest));
end
end
// Handshaking signals used to control data through the pipeline
// Determine when the kernel is finished.
acl_kernel_finish_detector kernel_finish_detector (
.clock(clock),
.resetn(resetn),
.start(start_NO_SHIFT_REG),
.wg_size(workgroup_size_NO_SHIFT_REG),
.wg_dispatch_valid_out(iter_valid_in),
.wg_dispatch_stall_in(iter_stall_out),
.dispatched_all_groups(dispatched_all_groups),
.kernel_copy_valid_out(valid_out),
.kernel_copy_stall_in(stall_in),
.pending_writes(has_a_write_pending),
.finish(finish)
);
defparam kernel_finish_detector.NUM_COPIES = 1;
defparam kernel_finish_detector.WG_SIZE_W = 32;
assign stall_in = 1'b0;
// Creating ID iterator and kernel instance for every requested kernel copy
// ID iterator is responsible for iterating over all local ids for given work-groups
acl_id_iterator id_iter_inst0 (
.clock(clock),
.resetn(resetn),
.start(start_out),
.valid_in(iter_valid_in),
.stall_out(iter_stall_out),
.stall_in(stall_out),
.valid_out(valid_in),
.group_id_in(group_id_tmp),
.global_id_base_in(global_id_base_out),
.local_size(local_size_NO_SHIFT_REG),
.global_size(global_size_NO_SHIFT_REG),
.local_id(local_id[0]),
.global_id(global_id[0]),
.group_id(group_id[0])
);
// This section instantiates a kernel function block
erosion_function erosion_function_inst0 (
.clock(clock),
.resetn(resetn),
.stall_out(stall_out),
.valid_in(valid_in),
.valid_out(valid_out),
.stall_in(stall_in),
.avm_local_bb1_ld__readdata(avm_local_bb1_ld__inst0_readdata),
.avm_local_bb1_ld__readdatavalid(avm_local_bb1_ld__inst0_readdatavalid),
.avm_local_bb1_ld__waitrequest(avm_local_bb1_ld__inst0_waitrequest),
.avm_local_bb1_ld__address(avm_local_bb1_ld__inst0_address),
.avm_local_bb1_ld__read(avm_local_bb1_ld__inst0_read),
.avm_local_bb1_ld__write(avm_local_bb1_ld__inst0_write),
.avm_local_bb1_ld__writeack(avm_local_bb1_ld__inst0_writeack),
.avm_local_bb1_ld__writedata(avm_local_bb1_ld__inst0_writedata),
.avm_local_bb1_ld__byteenable(avm_local_bb1_ld__inst0_byteenable),
.avm_local_bb1_ld__burstcount(avm_local_bb1_ld__inst0_burstcount),
.avm_local_bb1_st_c0_exe1_readdata(avm_local_bb1_st_c0_exe1_inst0_readdata),
.avm_local_bb1_st_c0_exe1_readdatavalid(avm_local_bb1_st_c0_exe1_inst0_readdatavalid),
.avm_local_bb1_st_c0_exe1_waitrequest(avm_local_bb1_st_c0_exe1_inst0_waitrequest),
.avm_local_bb1_st_c0_exe1_address(avm_local_bb1_st_c0_exe1_inst0_address),
.avm_local_bb1_st_c0_exe1_read(avm_local_bb1_st_c0_exe1_inst0_read),
.avm_local_bb1_st_c0_exe1_write(avm_local_bb1_st_c0_exe1_inst0_write),
.avm_local_bb1_st_c0_exe1_writeack(avm_local_bb1_st_c0_exe1_inst0_writeack),
.avm_local_bb1_st_c0_exe1_writedata(avm_local_bb1_st_c0_exe1_inst0_writedata),
.avm_local_bb1_st_c0_exe1_byteenable(avm_local_bb1_st_c0_exe1_inst0_byteenable),
.avm_local_bb1_st_c0_exe1_burstcount(avm_local_bb1_st_c0_exe1_inst0_burstcount),
.start(start_out),
.input_iterations(kernel_arguments_NO_SHIFT_REG[159:128]),
.clock2x(clock2x),
.input_img_in(kernel_arguments_NO_SHIFT_REG[63:0]),
.input_img_out(kernel_arguments_NO_SHIFT_REG[127:64]),
.has_a_write_pending(has_a_write_pending),
.has_a_lsu_active(has_a_lsu_active)
);
endmodule
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module erosion_sys_cycle_time
(
input clock,
input resetn,
output [31:0] cur_cycle
);
reg [31:0] cur_count_NO_SHIFT_REG;
assign cur_cycle = cur_count_NO_SHIFT_REG;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
cur_count_NO_SHIFT_REG <= 32'h0;
end
else
begin
cur_count_NO_SHIFT_REG <= (cur_count_NO_SHIFT_REG + 32'h1);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_TB_V
`define SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_TB_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 SET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 SET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 SET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_TB_V
|
// STD 10-30-16
//
// Synchronous 1-port ram with byte masking
// Only one read or one write may be done per cycle.
//
`define bsg_mem_1rw_sync_mask_write_byte_macro(bits,words) \
if (els_p == words && data_width_p == bits) \
begin: macro \
saed90_``bits``x``words``_1P_BM mem \
(.CE1 (clk_lo) \
,.WEB1 (~w_i) \
,.OEB1 (1'b0) \
,.CSB1 (~v_i) \
,.A1 (addr_i) \
,.I1 (data_i) \
,.O1 (data_o) \
,.WBM1 (write_mask_i) \
); \
end
module bsg_mem_1rw_sync_mask_write_byte #(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
,parameter enable_clock_gating_p=1'b0
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( v_i )
,.bypass_i( ~enable_clock_gating_p )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
// TODO: ADD ANY NEW RAM CONFIGURATIONS HERE
`bsg_mem_1rw_sync_mask_write_byte_macro (64, 512) else
// no hardened version found
begin: notmacro
// Instantiate a synthesizale 1rw sync mask write byte
bsg_mem_1rw_sync_mask_write_byte_synth #(.els_p(els_p), .data_width_p(data_width_p)) synth
(.clk_i(clk_lo)
,.reset_i
,.v_i
,.w_i
,.addr_i
,.data_i
,.write_mask_i
,.data_o
);
end // block: notmacro
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// nios_dut_mm_interconnect_0_avalon_st_adapter_012.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_012 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_4_V
`define SKY130_FD_SC_HD__DLRTN_4_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_4_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_get_offset (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
indices_req_din,
indices_req_full_n,
indices_req_write,
indices_rsp_empty_n,
indices_rsp_read,
indices_address,
indices_datain,
indices_dataout,
indices_size,
ap_ce,
i_index,
i_sample,
sample_buffer_size,
sample_length,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b0;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_30 = 32'b110000;
parameter ap_const_lv32_37 = 32'b110111;
parameter ap_const_lv56_0 = 56'b00000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output indices_req_din;
input indices_req_full_n;
output indices_req_write;
input indices_rsp_empty_n;
output indices_rsp_read;
output [31:0] indices_address;
input [55:0] indices_datain;
output [55:0] indices_dataout;
output [31:0] indices_size;
input ap_ce;
input [15:0] i_index;
input [15:0] i_sample;
input [31:0] sample_buffer_size;
input [15:0] sample_length;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_req_write;
reg indices_rsp_read;
reg [0:0] ap_CS_fsm = 1'b0;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg [15:0] i_sample_read_reg_127;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_127_pp0_it1;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_127_pp0_it2;
wire [31:0] tmp_9_fu_92_p1;
reg [31:0] tmp_9_reg_138;
reg [7:0] indices_stride_load_new_reg_143;
wire [63:0] tmp_fu_81_p1;
wire [15:0] tmp_6_fu_112_p0;
wire [7:0] tmp_6_fu_112_p1;
wire [23:0] tmp_6_fu_112_p2;
wire [31:0] tmp_6_cast_fu_118_p1;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
wire [23:0] tmp_6_fu_112_p00;
wire [23:0] tmp_6_fu_112_p10;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_reg_ppstg_i_sample_read_reg_127_pp0_it1 <= i_sample_read_reg_127;
ap_reg_ppstg_i_sample_read_reg_127_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_127_pp0_it1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
i_sample_read_reg_127 <= i_sample;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_load_new_reg_143 <= {{indices_datain[ap_const_lv32_37 : ap_const_lv32_30]}};
tmp_9_reg_138 <= tmp_9_fu_92_p1;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or indices_rsp_empty_n or ap_ce)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// indices_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_req_write = ap_const_logic_1;
end else begin
indices_req_write = ap_const_logic_0;
end
end
/// indices_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_rsp_read = ap_const_logic_1;
end else begin
indices_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return = (tmp_6_cast_fu_118_p1 + tmp_9_reg_138);
assign indices_address = tmp_fu_81_p1;
assign indices_dataout = ap_const_lv56_0;
assign indices_req_din = ap_const_logic_0;
assign indices_size = ap_const_lv32_1;
assign tmp_6_cast_fu_118_p1 = $unsigned(tmp_6_fu_112_p2);
assign tmp_6_fu_112_p0 = tmp_6_fu_112_p00;
assign tmp_6_fu_112_p00 = $unsigned(ap_reg_ppstg_i_sample_read_reg_127_pp0_it2);
assign tmp_6_fu_112_p1 = tmp_6_fu_112_p10;
assign tmp_6_fu_112_p10 = $unsigned(indices_stride_load_new_reg_143);
assign tmp_6_fu_112_p2 = ($signed({{1'b0}, {tmp_6_fu_112_p0}}) * $signed({{1'b0}, {tmp_6_fu_112_p1}}));
assign tmp_9_fu_92_p1 = indices_datain[31:0];
assign tmp_fu_81_p1 = $unsigned(i_index);
endmodule //sample_iterator_get_offset
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_PP_BLACKBOX_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module addsub16 (
add_sub,
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
input aclr;
input clken;
output [15:0] result;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module main_pll(CLKIN_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK2X_OUT,
LOCKED_OUT);
input CLKIN_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK2X_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK2X_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
.O(CLK2X_OUT));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(CLK2X_BUF),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_cols_V_channel1_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_cols_V_channel1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_cols_V_channel1_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_cols_V_channel1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : HPIO_VREF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HPIO_VREF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter VREF_CNTR = "OFF"
)(
output VREF,
input [6:0] FABRIC_VREF_TUNE
);
// define constants
localparam MODULE_NAME = "HPIO_VREF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam VREF_CNTR_FABRIC_RANGE1 = 1;
localparam VREF_CNTR_FABRIC_RANGE2 = 2;
localparam VREF_CNTR_OFF = 0;
localparam [104:1] VREF_CNTR_REG = VREF_CNTR;
wire [1:0] VREF_CNTR_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire VREF_out = 1'b1;
wire VREF_delay;
wire [6:0] FABRIC_VREF_TUNE_in;
wire [6:0] FABRIC_VREF_TUNE_delay;
assign #(out_delay) VREF = VREF_delay;
// inputs with no timing checks
assign #(in_delay) FABRIC_VREF_TUNE_delay = FABRIC_VREF_TUNE;
assign VREF_delay = VREF_out;
assign FABRIC_VREF_TUNE_in = FABRIC_VREF_TUNE_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((VREF_CNTR_REG != "OFF") &&
(VREF_CNTR_REG != "FABRIC_RANGE1") &&
(VREF_CNTR_REG != "FABRIC_RANGE2"))) begin
$display("Error: [Unisim %s-101] VREF_CNTR attribute is set to %s. Legal values for this attribute are OFF, FABRIC_RANGE1 or FABRIC_RANGE2. Instance: %m", MODULE_NAME, VREF_CNTR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign VREF_CNTR_BIN =
(VREF_CNTR_REG == "OFF") ? VREF_CNTR_OFF :
(VREF_CNTR_REG == "FABRIC_RANGE1") ? VREF_CNTR_FABRIC_RANGE1 :
(VREF_CNTR_REG == "FABRIC_RANGE2") ? VREF_CNTR_FABRIC_RANGE2 :
VREF_CNTR_OFF;
always @ (FABRIC_VREF_TUNE_in) begin
$display("Info: [Unisim %s-1] Fabric Tune Value changed to %b. Instance: %m",MODULE_NAME, FABRIC_VREF_TUNE_in);
end
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
`define zednkw 200
module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
input zfghtn;
input [4:0] cjtmau;
input vipmpg;
input [7:0] knquim;
input [7:0] kqxkkr;
reg covfok;
reg [15:0] xwieqw;
reg [2:0] ofnjjt;
reg [37:0] hdsejo[1:0];
reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
reg vrqrih, ryyjxy;
reg fgzsox;
wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr;
wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10];
wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10];
wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr;
wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr;
wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1);
wire smxixw = vrqrih | (ryyjxy & ktsveg);
wire [7:0] grvsrs, kyxrft, uxhkka;
wire [7:0] eianuv = 8'h01 << ofnjjt;
wire [7:0] jvpnxn = {8{qnpfus}} & eianuv;
wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv;
wire [7:0] nahzat = {8{iytyol}} & eianuv;
genvar i;
generate
for (i=0;i<8;i=i+1)
begin : dnlpyw
DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i],
knquim[3:0], covfok, grvsrs[i]);
DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i],
knquim[7:4], covfok, kyxrft[i]);
DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i],
kqxkkr[3:0], covfok, uxhkka[i]);
end
endgenerate
endmodule
module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh);
input clk, fgzsox, fckiyr, covfok;
input [3:0] uezcjy;
output juvlsh;
task Xinit;
begin
`ifdef TEST_HARNESS
khgawe = 1'b0;
`endif
end
endtask
function X;
input vrdejo;
begin
`ifdef TEST_HARNESS
if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1;
`endif
X = vrdejo;
end
endfunction
task Xcheck;
input vzpwwy;
begin
end
endtask
reg [3:0] udbvtl;
assign juvlsh = |udbvtl;
wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1));
wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox;
always @(posedge clk)
begin
Xinit;
if (X(qqibou))
udbvtl <= #`zednkw mppedc;
Xcheck(fgzsox);
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="axi_stream_gpio,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=0.000000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=1,HLS_SYN_LUT=0}" *)
module axi_stream_gpio (
ap_clk,
ap_rst_n,
ap_start,
ap_done,
ap_idle,
ap_ready,
inputData_V,
inputData_V_ap_vld,
outputData_TDATA,
outputData_TVALID,
outputData_TREADY,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst_n;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [0:0] inputData_V;
input inputData_V_ap_vld;
input [31:0] outputData_TDATA;
input outputData_TVALID;
output outputData_TREADY;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg ap_rst_n_inv;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_19;
reg [0:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_19)
begin
if (ap_sig_bdd_19) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_return = ap_const_lv32_0;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
/// ap_sig_bdd_19 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_19 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
assign outputData_TREADY = ap_const_logic_0;
endmodule //axi_stream_gpio
|
`timescale 1ns / 1ps
module tb_inverter();
`include "bch.vh"
localparam M = 8;
reg clk = 0;
reg start = 1;
reg in = 0;
wire [M-1:0] out;
reg [M-1:0] out2 = 0;
wire [M-1:0] out_dual;
reg [M-1:0] v = 0;
integer i;
reg [M-1:0] a;
reg [M-1:0] b;
berlekamp_inverter #(M) inv(
.clk(clk),
.start(start),
.standard_in(in),
.standard_out(out)
);
fermat_inverter #(M) inv2(
.clk(clk),
.start(start),
.standard_in(a),
.dual_out(out_dual)
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0);
a = lpow(M, 0);
#1;
for (i = 0; i < `BCH_M2N(M); i = i + 1) begin
b = brute_inverse(M, a);
v = a << 1;
in = a[M-1];
start = 1;
#4;
clk = 1;
#1;
repeat (M) begin
in = v[M-1];
v = v << 1;
start = 0;
#4;
clk = 0;
#5;
clk = 1;
#1;
end
out2 = dual_to_standard(M, out_dual);
repeat (M - 2) begin
in = 0;
#4;
clk = 0;
#5;
clk = 1;
#1;
end
#4;
clk = 0;
#1;
$display("%d 1/%b = %b, %b%s %b%s", i, a, b,
out, b == out ? "" : "*",
out2, b == out2 ? "" : "*");
a = `BCH_MUL1(M, a);
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/********
* This module captures the relative frequency with which each bit in 'value'
* toggles. This can be useful for detecting address patterns for example.
*
* Eg. (in hex)
* Linear: 1ff ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Linear predicated: 1ff ff 80 40 00 00 00 20 10 8 4 2 1 0 0 0 ...
* Strided: 00 00 ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Random: ff ff ff ff ff ff ff ff ff ...
*
* The counters that track the toggle rates automatically get divided by 2 once
* any of their values comes close to overflowing. Hence the toggle rates are
* relative, and comparable only within a single module instance.
*
* The last counter (count[WIDTH]) is a saturating counter storing the number of
* times a scaledown was performed. If you assume the relative rates don't
* change between scaledowns, this can be used to approximate absolute toggle
* rates (which can be compared against rates from another instance).
*****************/
module acl_toggle_detect
#(
parameter WIDTH=13, // Width of input signal in bits
parameter COUNTERWIDTH=10 // in bits, MUST be greater than 3
)
(
input logic clk,
input logic resetn,
input logic valid,
input logic [WIDTH-1:0] value,
output logic [COUNTERWIDTH-1:0] count[WIDTH+1]
);
/******************
* LOCAL PARAMETERS
*******************/
/******************
* SIGNALS
*******************/
logic [WIDTH-1:0] last_value;
logic [WIDTH-1:0] bits_toggled;
logic scaledown;
/******************
* ARCHITECTURE
*******************/
always@(posedge clk or negedge resetn)
if (!resetn)
last_value<={WIDTH{1'b0}};
else if (valid)
last_value<=value;
// Compute which bits toggled via XOR
always@(posedge clk or negedge resetn)
if (!resetn)
bits_toggled<={WIDTH{1'b0}};
else if (valid)
bits_toggled<=value^last_value;
else
bits_toggled<={WIDTH{1'b0}};
// Create one counter for each bit in value. Increment the respective
// counter if that bit toggled.
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin:counters
always@(posedge clk or negedge resetn)
if (!resetn)
count[i] <= {COUNTERWIDTH{1'b0}};
else if (bits_toggled[i] && scaledown)
count[i] <= (count[i] + 2'b1) >> 1;
else if (bits_toggled[i])
count[i] <= count[i] + 2'b1;
else if (scaledown)
count[i] <= count[i] >> 1;
end
endgenerate
// Count total number of times scaled down - saturating counter
// This can be used to approximate absolute toggle rates
always@(posedge clk or negedge resetn)
if (!resetn)
count[WIDTH] <= 1'b0;
else if (scaledown && count[WIDTH]!={COUNTERWIDTH{1'b1}})
count[WIDTH] <= count[WIDTH] + 2'b1;
// If any counter value's top 3 bits are 1s, scale down all counter values
integer j;
always@(posedge clk or negedge resetn)
if (!resetn)
scaledown <= 1'b0;
else if (scaledown)
scaledown <= 1'b0;
else
for (j = 0; j < WIDTH; j = j + 1)
if (&count[j][COUNTERWIDTH-1:COUNTERWIDTH-3])
scaledown <= 1'b1;
endmodule
|
module issue_flow_control
(/*AUTOARG*/
// Outputs
wave_valid_entries,
// Inputs
clk, rst, tracemon_barrier_retire_en, valid_entry_out,
tracemon_barrier_retire_wf_bitmap, f_decode_wfid,
f_salu_branch_wfid, alu_wfid, f_decode_valid, f_decode_waitcnt,
f_salu_branch_en, alu_valid, alu_branch
);
input clk,rst;
input tracemon_barrier_retire_en;
input [`WF_PER_CU-1:0] valid_entry_out;
input [`WF_PER_CU-1:0] tracemon_barrier_retire_wf_bitmap;
input [`WF_ID_LENGTH-1:0] f_decode_wfid, f_salu_branch_wfid,
alu_wfid;
input f_decode_valid, f_decode_waitcnt,
f_salu_branch_en,
alu_valid, alu_branch;
wire [`WF_PER_CU-1:0] flopped_valid_entry_out;
wire [`WF_PER_CU-1:0] valid_barrier_retire_wf_bitmap;
wire [`WF_PER_CU-1:0] decoded_decode_waitcnt, decoded_branch_retired;
wire [`WF_PER_CU-1:0] decoded_branch_issued, flopped_decoded_branch_issued;
output [`WF_PER_CU-1:0] wave_valid_entries;
decoder_6b_40b_en branch_issue
(
.addr_in(alu_wfid),
.out(decoded_branch_issued),
.en(alu_valid & alu_branch)
);
decoder_6b_40b_en branch_retire
(
.addr_in(f_salu_branch_wfid),
.out(decoded_branch_retired),
.en(f_salu_branch_en)
);
decoder_6b_40b_en wait_cnt_decoder
(
.addr_in(f_decode_wfid),
.out(decoded_decode_waitcnt),
.en(f_decode_valid & f_decode_waitcnt)
);
dff valid_entry_out_flop[`WF_PER_CU-1:0]
(
.q(flopped_valid_entry_out),
.d(valid_entry_out),
.clk(clk),
.rst(rst)
);
dff branch_issued_flop[`WF_PER_CU-1:0]
(
.q(flopped_decoded_branch_issued),
.d(decoded_branch_issued),
.clk(clk),
.rst(rst)
);
assign valid_barrier_retire_wf_bitmap
= ( tracemon_barrier_retire_en )? tracemon_barrier_retire_wf_bitmap :
{`WF_PER_CU{1'b0}};
// Ask for new instructions when valid goes down (instruction is issued) or when
// a barrier or a branch of a waitcnt retire.
// Do not ask for new instructions when a branch was issued last cycle
assign wave_valid_entries
= ( ( (valid_entry_out ^ flopped_valid_entry_out) & flopped_valid_entry_out ) |
valid_barrier_retire_wf_bitmap | decoded_decode_waitcnt | decoded_branch_retired ) &
~flopped_decoded_branch_issued;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of DTLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.4 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Data TLB
//
module or1200_dmmu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_DMMU_PS] ppn;
output uwe;
output ure;
output swe;
output sre;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_DTLB_TAG] vpn;
wire v;
wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_mr_so;
wire mbist_tr_so;
wire mbist_mr_si = mbist_si_i;
wire mbist_tr_si = mbist_mr_so;
assign mbist_so_o = mbist_tr_so;
`endif
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-19 v 0
// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_DTLB_INDXW{v}}, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
spr_dat_i[`OR1200_DTLBTR_URE_BITS],
spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
//
// Instantiation of DTLB Match Registers
//
or1200_spram_64x14 dtlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_mr_si),
.mbist_so_o(mbist_mr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of DTLB Translate Registers
//
or1200_spram_64x24 dtlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tr_si),
.mbist_so_o(mbist_tr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_xcvr (
// common reset
rst,
// receive interface
rx_clk,
rx_rstn,
rx_ext_sysref,
rx_sysref,
rx_ip_sync,
rx_sync,
rx_status,
// transmit interface
tx_clk,
tx_rstn,
tx_ext_sysref,
tx_sysref,
tx_sync,
tx_ip_sync,
tx_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00060162;
parameter ID = 0;
parameter DEVICE_TYPE = 0;
// common reset
output rst;
// receive interface
input rx_clk;
output rx_rstn;
input rx_ext_sysref;
output rx_sysref;
input rx_ip_sync;
output rx_sync;
input [ 7:0] rx_status;
// transmit interface
input tx_clk;
output tx_rstn;
input tx_ext_sysref;
output tx_sysref;
input tx_sync;
output tx_ip_sync;
input [ 7:0] tx_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_reset = 'd1;
reg up_rx_reset = 'd1;
reg up_tx_reset = 'd1;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_rx_sysref_sel = 'd0;
reg up_rx_sysref = 'd0;
reg up_rx_sync = 'd0;
reg up_rx_resetn = 'd0;
reg up_tx_sysref_sel = 'd0;
reg up_tx_sysref = 'd0;
reg up_tx_sync = 'd0;
reg up_tx_resetn = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg rx_rstn = 'd0;
reg rx_sysref_sel_m1 = 'd0;
reg rx_sysref_sel = 'd0;
reg rx_up_sysref_m1 = 'd0;
reg rx_up_sysref = 'd0;
reg rx_sysref = 'd0;
reg rx_up_sync_m1 = 'd0;
reg rx_up_sync = 'd0;
reg rx_sync = 'd0;
reg tx_rstn = 'd0;
reg tx_sysref_sel_m1 = 'd0;
reg tx_sysref_sel = 'd0;
reg tx_up_sysref_m1 = 'd0;
reg tx_up_sysref = 'd0;
reg tx_sysref = 'd0;
reg tx_up_sync_m1 = 'd0;
reg tx_up_sync = 'd0;
reg tx_ip_sync = 'd0;
reg [ 8:0] up_rx_status_m1 = 'd0;
reg [ 8:0] up_rx_status = 'd0;
reg [ 8:0] up_tx_status_m1 = 'd0;
reg [ 8:0] up_tx_status = 'd0;
// internal signals
wire rx_rst;
wire tx_rst;
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_reset <= 1'b1;
up_rx_reset <= 1'b1;
up_tx_reset <= 1'b1;
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_rx_sysref_sel <= 'd0;
up_rx_sysref <= 'd0;
up_rx_sync <= 'd0;
up_rx_resetn <= 'd0;
up_tx_sysref_sel <= 'd0;
up_tx_sysref <= 'd0;
up_tx_sync <= 'd0;
up_tx_resetn <= 'd0;
end else begin
up_reset <= ~up_resetn;
up_rx_reset <= ~(up_resetn & up_rx_resetn);
up_tx_reset <= ~(up_resetn & up_tx_resetn);
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h03)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_rx_sysref_sel <= up_wdata[1];
up_rx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_rx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_rx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tx_sysref_sel <= up_wdata[1];
up_tx_sysref <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tx_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tx_resetn <= up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h03: up_rdata <= {31'd0, up_resetn};
8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
8'h11: up_rdata <= {31'd0, up_rx_sync};
8'h12: up_rdata <= {23'd0, up_rx_status};
8'h13: up_rdata <= {31'd0, up_rx_resetn};
8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h21: up_rdata <= {31'd0, up_tx_sync};
8'h22: up_rdata <= {23'd0, up_tx_status};
8'h23: up_rdata <= {31'd0, up_tx_resetn};
8'h30: up_rdata <= DEVICE_TYPE;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
assign rst = up_reset;
ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst));
// rx sysref & sync
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst == 1'b1) begin
rx_rstn <= 'd0;
rx_sysref_sel_m1 <= 'd0;
rx_sysref_sel <= 'd0;
rx_up_sysref_m1 <= 'd0;
rx_up_sysref <= 'd0;
rx_sysref <= 'd0;
rx_up_sync_m1 <= 'd0;
rx_up_sync <= 'd0;
rx_sync <= 'd0;
end else begin
rx_rstn <= 1'd1;
rx_sysref_sel_m1 <= up_rx_sysref_sel;
rx_sysref_sel <= rx_sysref_sel_m1;
rx_up_sysref_m1 <= up_rx_sysref;
rx_up_sysref <= rx_up_sysref_m1;
if (rx_sysref_sel == 1'b1) begin
rx_sysref <= rx_ext_sysref;
end else begin
rx_sysref <= rx_up_sysref;
end
rx_up_sync_m1 <= up_rx_sync;
rx_up_sync <= rx_up_sync_m1;
rx_sync <= rx_up_sync & rx_ip_sync;
end
end
// tx sysref & sync
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst == 1'b1) begin
tx_rstn <= 'd0;
tx_sysref_sel_m1 <= 'd0;
tx_sysref_sel <= 'd0;
tx_up_sysref_m1 <= 'd0;
tx_up_sysref <= 'd0;
tx_sysref <= 'd0;
tx_up_sync_m1 <= 'd0;
tx_up_sync <= 'd0;
tx_ip_sync <= 'd0;
end else begin
tx_rstn <= 1'd1;
tx_sysref_sel_m1 <= up_tx_sysref_sel;
tx_sysref_sel <= tx_sysref_sel_m1;
tx_up_sysref_m1 <= up_tx_sysref;
tx_up_sysref <= tx_up_sysref_m1;
if (tx_sysref_sel == 1'b1) begin
tx_sysref <= tx_ext_sysref;
end else begin
tx_sysref <= tx_up_sysref;
end
tx_up_sync_m1 <= up_tx_sync;
tx_up_sync <= tx_up_sync_m1;
tx_ip_sync <= tx_up_sync & tx_sync;
end
end
// status
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rx_status_m1 <= 'd0;
up_rx_status <= 'd0;
up_tx_status_m1 <= 'd0;
up_tx_status <= 'd0;
end else begin
up_rx_status_m1 <= {rx_sync, rx_status};
up_rx_status <= up_rx_status_m1;
up_tx_status_m1 <= {tx_ip_sync, tx_status};
up_tx_status <= up_tx_status_m1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Butterworth low pass IIR filter
// input: 8bit ADC signal, 1MS/s
// output: 8bit value, Fc=20khz
//
// coef: (using http://www-users.cs.york.ac.uk/~fisher/mkfilter/trad.html)
// Recurrence relation:
// y[n] = ( 1 * x[n- 2])
// + ( 2 * x[n- 1])
// + ( 1 * x[n- 0])
// + ( -0.8371816513 * y[n- 2])
// + ( 1.8226949252 * y[n- 1])
//
// therefore:
// a = [1,2,1]
// b = [-0.8371816513, 1.8226949252]
// b is approximated to b = [-0xd6/0x100, 0x1d3 / 0x100] (for optimization)
// gain = 2.761139367e2
//
// See details about its design see
// https://fail0verflow.com/blog/2014/proxmark3-fpga-iir-filter.html
module lp20khz_1MSa_iir_filter(input clk, input [7:0] adc_d, output rdy, output [7:0] out);
// clk is 24Mhz, the IIR filter is designed for 1MS/s
// hence we need to divide it by 24
// using a shift register takes less area than a counter
reg [23:0] cnt = 1;
assign rdy = cnt[0];
always @(posedge clk)
cnt <= {cnt[22:0], cnt[23]};
reg [7:0] x0 = 0;
reg [7:0] x1 = 0;
reg [16:0] y0 = 0;
reg [16:0] y1 = 0;
always @(posedge clk)
begin
if (rdy)
begin
x0 <= x1;
x1 <= adc_d;
y0 <= y1;
y1 <=
// center the signal:
// input range is [0; 255]
// We want "128" to be at the center of the 17bit register
// (128+z)*gain = 17bit center
// z = (1<<16)/gain - 128 = 109
// We could use 9bit x registers for that, but that would be
// a waste, let's just add the constant during the computation
// (x0+109) + 2*(x1+109) + (x2+109) = x0 + 2*x1 + x2 + 436
x0 + {x1, 1'b0} + adc_d + 436
// we want "- y0 * 0xd6 / 0x100" using only shift and add
// 0xd6 == 0b11010110
// so *0xd6/0x100 is equivalent to
// ((x << 1) + (x << 2) + (x << 4) + (x << 6) + (x << 7)) >> 8
// which is also equivalent to
// (x >> 7) + (x >> 6) + (x >> 4) + (x >> 2) + (x >> 1)
- ((y0 >> 7) + (y0 >> 6) + (y0 >> 4) + (y0 >> 2) + (y0 >> 1)) // - y0 * 0xd6 / 0x100
// we want "+ y1 * 0x1d3 / 0x100"
// 0x1d3 == 0b111010011
// so this is equivalent to
// ((x << 0) + (x << 1) + (x << 4) + (x << 6) + (x << 7) + (x << 8)) >> 8
// which is also equivalent to
// (x >> 8) + (x >> 7) + (x >> 4) + (x >> 2) + (x >> 1) + (x >> 0)
+ ((y1 >> 8) + (y1 >> 7) + (y1 >> 4) + (y1 >> 2) + (y1 >> 1) + y1);
end
end
// output: reduce to 8bit
assign out = y1[16:9];
endmodule
|
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a / b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR: mismatch in div for %d and %d", a , b);
$display("VHDL = %d, Verilog = %d", c, int_AB);
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 1;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
if (B === 23'b0) B = 1;
end
#1 A = 1;
B = 1;
#1 A = 23'h7fffff;
#1 B = 23'h7fffff;
#1 B = 1;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = $random % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = $random % MAX;
if (B === 23'b0) B = 1;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input signed [22:0] value);
integer i, temp;
begin
temp = $random;
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
sdiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_if/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_ARUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 32,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
// write request
wire write_ready;
wire write_valid;
wire [31:0] write_address;
wire [31:0] write_length;
wire [C_USER_DATA_WIDTH-1:0] write_data;
// read request
wire read_ready;
wire read_valid;
wire [31:0] read_address;
wire [31:0] read_length;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_begin_request_preprocessor
nfa_accept_samples_generic_hw_indices_begin_request_preprocessor #(
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) request_preprocessor (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.USER_dataout ( USER_dataout ),
.USER_address ( USER_address ),
.USER_size ( USER_size ),
.USER_req_din ( USER_req_din ),
.USER_req_full_n ( USER_req_full_n ),
.USER_req_write ( USER_req_write ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length )
);
// nfa_accept_samples_generic_hw_indices_begin_write
nfa_accept_samples_generic_hw_indices_begin_write #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_AWUSER_WIDTH ( C_AWUSER_WIDTH ),
.C_WUSER_WIDTH ( C_WUSER_WIDTH ),
.C_BUSER_WIDTH ( C_BUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_write (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.AWID ( AWID ),
.AWADDR ( AWADDR ),
.AWLEN ( AWLEN ),
.AWSIZE ( AWSIZE ),
.AWBURST ( AWBURST ),
.AWLOCK ( AWLOCK ),
.AWCACHE ( AWCACHE ),
.AWPROT ( AWPROT ),
.AWQOS ( AWQOS ),
.AWUSER ( AWUSER ),
.AWVALID ( AWVALID ),
.AWREADY ( AWREADY ),
.WDATA ( WDATA ),
.WSTRB ( WSTRB ),
.WLAST ( WLAST ),
.WUSER ( WUSER ),
.WVALID ( WVALID ),
.WREADY ( WREADY ),
.BID ( BID ),
.BRESP ( BRESP ),
.BUSER ( BUSER ),
.BVALID ( BVALID ),
.BREADY ( BREADY ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data )
);
// nfa_accept_samples_generic_hw_indices_begin_read
nfa_accept_samples_generic_hw_indices_begin_read #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_ARUSER_WIDTH ( C_ARUSER_WIDTH ),
.C_RUSER_WIDTH ( C_RUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_read (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.ARID ( ARID ),
.ARADDR ( ARADDR ),
.ARLEN ( ARLEN ),
.ARSIZE ( ARSIZE ),
.ARBURST ( ARBURST ),
.ARLOCK ( ARLOCK ),
.ARCACHE ( ARCACHE ),
.ARPROT ( ARPROT ),
.ARQOS ( ARQOS ),
.ARUSER ( ARUSER ),
.ARVALID ( ARVALID ),
.ARREADY ( ARREADY ),
.RID ( RID ),
.RDATA ( RDATA ),
.RRESP ( RRESP ),
.RLAST ( RLAST ),
.RUSER ( RUSER ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length ),
.USER_datain ( USER_datain ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.USER_rsp_read ( USER_rsp_read )
);
//------------------------Body---------------------------
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_request_preprocessor/*{{{*/
#(parameter
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// user ports
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
// write request
input wire write_ready,
output wire write_valid,
output wire [31:0] write_address,
output wire [31:0] write_length,
output wire [C_USER_DATA_WIDTH-1:0] write_data,
// read request
input wire read_ready,
output wire read_valid,
output wire [31:0] read_address,
output wire [31:0] read_length
);
//------------------------Parameter----------------------
localparam
REQUEST_WIDTH = 1 + 32 + 32 + C_USER_DATA_WIDTH,
MAX_REQUEST = 32;
//------------------------Local signal-------------------
// request fifo
wire req_empty_n;
wire req_full_n;
wire req_rdreq;
wire req_wrreq;
wire [REQUEST_WIDTH-1:0] req_data;
wire [REQUEST_WIDTH-1:0] req_q;
wire [31:0] tmp_size;
wire tmp_type; // 0 - read, 1 - write
wire [31:0] tmp_address; // start address of read/write request
wire [31:0] tmp_length; // length of read/write request
wire [C_USER_DATA_WIDTH-1:0] tmp_data; // data of write request
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_begin_fifo
nfa_accept_samples_generic_hw_indices_begin_fifo #(
.DATA_BITS ( REQUEST_WIDTH ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) req_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( req_empty_n ),
.full_n ( req_full_n ),
.rdreq ( req_rdreq ),
.wrreq ( req_wrreq ),
.q ( req_q ),
.data ( req_data )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++user ports+++++++++++++++++++++
assign USER_req_full_n = req_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
assign write_valid = req_empty_n & tmp_type;
assign write_address = tmp_address;
assign write_length = tmp_length;
assign write_data = tmp_data;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_valid = req_empty_n & ~tmp_type;
assign read_address = tmp_address;
assign read_length = tmp_length;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++request fifo+++++++++++++++++++
assign req_rdreq = (read_valid & read_ready) | (write_valid & write_ready);
assign req_wrreq = USER_req_write;
assign req_data = {USER_req_din, USER_address, tmp_size, USER_dataout};
assign tmp_size = (USER_size==1'b0)? 1'b1 : USER_size;
assign tmp_type = req_q[REQUEST_WIDTH-1];
assign tmp_address = req_q[C_USER_DATA_WIDTH+63:C_USER_DATA_WIDTH+32];
assign tmp_length = req_q[C_USER_DATA_WIDTH+31:C_USER_DATA_WIDTH];
assign tmp_data = req_q[C_USER_DATA_WIDTH-1:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_write/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// write request
output wire write_ready,
input wire write_valid,
input wire [31:0] write_address,
input wire [31:0] write_length,
input wire [C_USER_DATA_WIDTH-1:0] write_data
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_BYTES = USER_DATA_BYTES > BUS_DATA_BYTES?
USER_DATA_BYTES : BUS_DATA_BYTES,
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
DATA = 4'd3,
LOOP = 4'd4;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg enough_data;
reg [DATA_BUF_BYTES*8-1:0] data_buf;
reg [DATA_BUF_BYTES-1:0] data_valid;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
reg [BUS_ADDR_ALIGN-1:0] tmp_bytes;
reg [BUS_ADDR_ALIGN-1:0] head_bytes;
reg [BUS_ADDR_ALIGN-1:0] tail_bytes;
reg add_head;
reg add_tail;
reg first_beat;
reg last_beat;
// axi4 bus
wire [BUS_DATA_BYTES-1:0] wstrb0;
wire [BUS_DATA_BYTES-1:0] wstrb1;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (write_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (AWREADY)
next = DATA;
else
next = ADDR;
DATA:
if (WVALID && WREADY && loop_beats==1'b1)
next = LOOP;
else
next = DATA;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (write_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && AWREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
len_buf <= write_length - 1'b1;
else if (write_ready && write_valid)
len_buf <= len_buf - 1'b1;
end
// enough_data
always @(posedge ACLK) begin
if (state==IDLE && write_valid) begin
if (write_length == 1'b1)
enough_data <= 1'b1;
else
enough_data <= 1'b0;
end
else if (write_ready && write_valid && len_buf==1'b1)
enough_data <= 1'b1;
end
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : wide_to_narrow
assign wstrb0 = {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= write_data;
else if (WREADY & WVALID)
data_buf <= data_buf >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (write_ready & write_valid)
data_valid <= {DATA_BUF_BYTES{1'b1}};
else if (WREADY & WVALID)
data_valid <= data_valid >> BUS_DATA_BYTES;
end
// tmp_bytes, head_bytes, tail_bytes, add_head, add_tail
// first_beat, last_beat
always @(*) begin
// these signals are useless if user data width is
// greater than bus data width
tmp_bytes = 1'b0;
head_bytes = 1'b0;
tail_bytes = 1'b0;
add_head = 1'b0;
add_tail = 1'b0;
first_beat = 1'b0;
last_beat = 1'b0;
end
end
else begin : narrow_to_wide
assign wstrb0 = first_beat? {BUS_DATA_BYTES{1'b1}} << head_bytes : {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = last_beat? {BUS_DATA_BYTES{1'b1}} >> tail_bytes : {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= {write_data, data_buf} >> USER_DATA_WIDTH;
else if (state==DATA && add_tail)
data_buf <= data_buf >> (tail_bytes * 8);
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (WREADY & WVALID)
data_valid <= {USER_DATA_BYTES{write_ready & write_valid}} << (DATA_BUF_BYTES-USER_DATA_BYTES);
else if (write_ready & write_valid)
data_valid <= {{USER_DATA_BYTES{1'b1}}, data_valid} >> USER_DATA_BYTES;
else if (add_head)
data_valid <= (data_valid >> head_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> head_bytes);
else if (state==DATA && add_tail)
data_valid <= (data_valid >> tail_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> tail_bytes);
end
// tmp_bytes
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
tmp_bytes <= write_length[BUS_ADDR_ALIGN-1:0] << USER_ADDR_ALIGN;
end
// head_bytes
always @(posedge ACLK) begin
if (state==PREP)
head_bytes <= addr_buf[BUS_ADDR_ALIGN-1:0];
end
// tail_bytes
always @(posedge ACLK) begin
if (state==PREP)
tail_bytes <= BUS_DATA_BYTES - addr_buf[BUS_ADDR_ALIGN-1:0] - tmp_bytes;
end
// add_head
always @(posedge ACLK) begin
if (state==PREP)
add_head <= 1'b1;
else
add_head <= 1'b0;
end
// add_tail
always @(posedge ACLK) begin
if (write_ready && write_valid && (write_length== 1'b1 || len_buf==1'b1))
add_tail <= 1'b1;
else if (state==DATA)
add_tail <= 1'b0;
end
// first_beat
always @(posedge ACLK) begin
if (state==PREP)
first_beat <= 1'b1;
else if (WREADY & WVALID)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if ((state==PREP || state==LOOP) && total_beats==1'b1)
last_beat <= 1'b1;
else if (WREADY & WVALID) begin
if (total_beats==1'b0 && loop_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end
endgenerate
// total_beats
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
total_beats <= ((write_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && AWREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
else if (WVALID & WREADY)
loop_beats <= loop_beats - 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi4 bus+++++++++++++++++++++++
// write address channel
assign AWID = 1'b0;
assign AWADDR = addr_buf;
assign AWLEN = loop_beats - 1'b1;
assign AWSIZE = BUS_ADDR_ALIGN[2:0];
assign AWBURST = 2'b01;
assign AWLOCK = 2'b00;
assign AWCACHE = C_CACHE_VALUE;
assign AWPROT = C_PROT_VALUE;
assign AWQOS = 4'b0000;
assign AWUSER = C_USER_VALUE;
assign AWVALID = (state==ADDR);
// write data channel
assign WDATA = data_buf[BUS_DATA_WIDTH-1:0];
assign WSTRB = wstrb0 & wstrb1;
assign WLAST = WVALID & (loop_beats==1'b1);
assign WUSER = C_USER_VALUE;
assign WVALID = (state==DATA) & data_valid[0];
// write response channel
assign BREADY = 1'b1; // we don't handle write response
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
generate
if (USER_DATA_BYTES <= BUS_DATA_BYTES) begin : gen_write_ready_0
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(~data_valid[0] | WREADY));
end
else begin : gen_write_ready_1
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(data_valid[DATA_BUF_BYTES-1:BUS_DATA_BYTES]==1'b0) &
(~data_valid[0] | WREADY));
end
endgenerate
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_read/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_ARUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// read request
output wire read_ready,
input wire read_valid,
input wire [31:0] read_address,
input wire [31:0] read_length,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
LOOP = 4'd3;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
// data align
wire align_ready;
wire align_valid;
wire [31:0] align_beats;
wire [31:0] align_address;
wire [31:0] align_length;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_begin_read_data_align
nfa_accept_samples_generic_hw_indices_begin_read_data_align #(
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) data_align (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.RDATA ( RDATA ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.USER_datain ( USER_datain ),
.USER_rsp_read ( USER_rsp_read ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.align_ready ( align_ready ),
.align_valid ( align_valid ),
.align_beats ( align_beats ),
.align_address ( align_address ),
.align_length ( align_length )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (align_ready & read_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (ARREADY)
next = LOOP;
else
next = ADDR;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (read_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && ARREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
len_buf <= read_length;
end
// total_beats
always @(posedge ACLK) begin
if (read_ready & read_valid)
total_beats <= ((read_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && ARREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read address channel+++++++++++
assign ARID = 1'b0;
assign ARADDR = addr_buf;
assign ARLEN = loop_beats - 1'b1;
assign ARSIZE = BUS_ADDR_ALIGN[2:0];
assign ARBURST = 2'b01;
assign ARLOCK = 2'b00;
assign ARCACHE = C_CACHE_VALUE;
assign ARPROT = C_PROT_VALUE;
assign ARQOS = 4'b0000;
assign ARUSER = C_USER_VALUE;
assign ARVALID = (state==ADDR);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++data align+++++++++++++++++++++
assign align_valid = (state==PREP);
assign align_beats = total_beats;
assign align_address = addr_buf;
assign align_length = len_buf;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_ready = (state==IDLE) & align_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_read_data_align/*{{{*/
#(parameter
C_DATA_WIDTH = 32,
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read data channel
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read,
// data align
output wire align_ready,
input wire align_valid,
input wire [31:0] align_beats,
input wire [31:0] align_address,
input wire [31:0] align_length
);
//------------------------Parameter----------------------
localparam
DATA_FIFO_DEPTH = 32,
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_WIDTH = USER_DATA_WIDTH > BUS_DATA_WIDTH?
USER_DATA_WIDTH : BUS_DATA_WIDTH,
DATA_VALID_BITS = USER_DATA_BYTES > BUS_DATA_BYTES ?
USER_DATA_BYTES / BUS_DATA_BYTES :
BUS_DATA_BYTES / USER_DATA_BYTES;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Local signal-------------------
reg [DATA_BUF_WIDTH-1:0] data_buf;
reg [DATA_VALID_BITS-1:0] data_valid;
reg [31:0] total_beats;
reg ready_buf;
wire [BUS_DATA_WIDTH-1:0] rs0_data;
wire rs0_valid;
wire rs0_ready;
wire fifo_empty_n;
wire fifo_full_n;
wire fifo_rdreq;
wire fifo_wrreq;
wire [C_USER_DATA_WIDTH-1:0] fifo_q;
wire [C_USER_DATA_WIDTH-1:0] fifo_data;
wire fifo_push;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_begin_reg_slice
nfa_accept_samples_generic_hw_indices_begin_reg_slice #(
.N ( BUS_DATA_WIDTH )
) rs0 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( RDATA ),
.s_valid ( RVALID ),
.s_ready ( RREADY ),
.m_data ( rs0_data ),
.m_valid ( rs0_valid ),
.m_ready ( rs0_ready )
);
// nfa_accept_samples_generic_hw_indices_begin_fifo
nfa_accept_samples_generic_hw_indices_begin_fifo #(
.DATA_BITS ( C_USER_DATA_WIDTH ),
.DEPTH ( DATA_FIFO_DEPTH ),
.DEPTH_BITS ( log2(DATA_FIFO_DEPTH) )
) data_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( fifo_empty_n ),
.full_n ( fifo_full_n ),
.rdreq ( fifo_rdreq ),
.wrreq ( fifo_wrreq ),
.q ( fifo_q ),
.data ( fifo_data )
);
// nfa_accept_samples_generic_hw_indices_begin_reg_slice
nfa_accept_samples_generic_hw_indices_begin_reg_slice #(
.N ( C_USER_DATA_WIDTH )
) rs1 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( fifo_q ),
.s_valid ( fifo_empty_n ),
.s_ready ( fifo_rdreq ),
.m_data ( USER_datain ),
.m_valid ( USER_rsp_empty_n ),
.m_ready ( USER_rsp_read )
);
//------------------------Body---------------------------
assign fifo_data = data_buf[C_USER_DATA_WIDTH-1:0];
assign fifo_wrreq = data_valid[0];
assign fifo_push = fifo_full_n & fifo_wrreq;
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : narrow_to_wide
/*
* user data width is greater than or equal to bus data width
* so all bytes of bus data are valid
*/
assign align_ready = 1'b1;
assign rs0_ready = ~align_valid & ready_buf & (~data_valid[0] | fifo_push);
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= {rs0_data, data_buf} >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (fifo_push)
data_valid <= (rs0_ready & rs0_valid) << (DATA_VALID_BITS-1);
else if (rs0_ready & rs0_valid)
data_valid <= {1'b1, data_valid} >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (~ARESETN)
total_beats <= 1'b0;
else if (align_valid)
total_beats <= total_beats + align_beats; // may overflow
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (align_valid)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
end // end of narrow_to_wide
else begin : wide_to_narrow
/*
* user data width is less than bus data width
* so we have to remove the padding bytes
*/
localparam
PADDING_BITS = log2(DATA_VALID_BITS),
MAX_REQUEST = 32,
DATA_BITS = PADDING_BITS * 2 + 32;
wire [31:0] end_address;
wire [PADDING_BITS-1:0] head_tmp;
wire [PADDING_BITS-1:0] tail_tmp;
reg [PADDING_BITS-1:0] head_padding;
reg [PADDING_BITS-1:0] tail_padding;
reg first_beat;
reg last_beat;
wire request_fifo_empty_n;
wire request_fifo_full_n;
wire request_fifo_rdreq;
wire request_fifo_wrreq;
wire [DATA_BITS-1:0] request_fifo_q;
wire [DATA_BITS-1:0] request_fifo_data;
// nfa_accept_samples_generic_hw_indices_begin_fifo
nfa_accept_samples_generic_hw_indices_begin_fifo #(
.DATA_BITS ( DATA_BITS ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) request_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( request_fifo_empty_n ),
.full_n ( request_fifo_full_n ),
.rdreq ( request_fifo_rdreq ),
.wrreq ( request_fifo_wrreq ),
.q ( request_fifo_q ),
.data ( request_fifo_data )
);
assign align_ready = request_fifo_full_n;
assign rs0_ready = ready_buf & (data_valid==1'b0 || (data_valid==1'b1 && fifo_push));
assign end_address = align_address + align_length * USER_DATA_BYTES;
assign head_tmp = align_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN];
assign tail_tmp = ~end_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN] + 1'b1;
assign request_fifo_rdreq = request_fifo_empty_n & ~ready_buf;
assign request_fifo_wrreq = align_valid;
assign request_fifo_data = {head_tmp, tail_tmp, align_beats};
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= rs0_data >> (first_beat? head_padding * USER_DATA_WIDTH : 0);
else if (fifo_push)
data_buf <= data_buf >> USER_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (rs0_ready & rs0_valid)
data_valid <= ({DATA_VALID_BITS{1'b1}} >> (last_beat? tail_padding : 0))
>> (first_beat? head_padding : 0);
else if (fifo_push)
data_valid <= data_valid >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (request_fifo_rdreq)
total_beats <= request_fifo_q[31:0];
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (request_fifo_rdreq)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
// head_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
head_padding <= request_fifo_q[31+PADDING_BITS*2:32+PADDING_BITS];
end
// tail_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
tail_padding <= request_fifo_q[31+PADDING_BITS:32];
end
// first_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq)
first_beat <= 1'b1;
else if (rs0_ready & rs0_valid)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq && request_fifo_q[31:0]==1'b1)
last_beat <= 1'b1;
else if (rs0_ready & rs0_valid) begin
if (total_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end // end of wide_to_narrow
endgenerate
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_fifo/*{{{*/
#(parameter
DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
)(
input wire sclk,
input wire reset_n,
output reg empty_n,
output reg full_n,
input wire rdreq,
input wire wrreq,
output wire [DATA_BITS-1:0] q,
input wire [DATA_BITS-1:0] data
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
wire push;
wire pop;
reg [DEPTH_BITS-1:0] pout;
reg [DATA_BITS-1:0] mem[0:DEPTH-1];
//------------------------Body---------------------------
assign push = full_n & wrreq;
assign pop = empty_n & rdreq;
assign q = mem[pout];
// empty_n
always @(posedge sclk) begin
if (~reset_n)
empty_n <= 1'b0;
else if (push)
empty_n <= 1'b1;
else if (~push && pop && pout == 1'b0)
empty_n <= 1'b0;
end
// full_n
always @(posedge sclk) begin
if (~reset_n)
full_n <= 1'b1;
else if (rdreq)
full_n <= 1'b1;
else if (push && ~pop && pout == DEPTH - 2)
full_n <= 1'b0;
end
// pout
always @(posedge sclk) begin
if (~reset_n)
pout <= 1'b0;
else if (push & ~pop & empty_n)
pout <= pout + 1'b1;
else if (~push && pop && pout != 1'b0)
pout <= pout - 1'b1;
end
integer i;
always @(posedge sclk) begin
if (push) begin
for (i = 0; i < DEPTH - 1; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= data;
end
end
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_begin_reg_slice/*{{{*/
#(parameter
N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset_n,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [1:0] state;
reg [1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge sclk) begin
if (load_p1) begin
if (load_p1_from_p2)
data_p1 <= data_p2;
else
data_p1 <= s_data;
end
end
// data_p2
always @(posedge sclk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge sclk) begin
if (~reset_n)
s_ready_t <= 1'b0;
else if (state == ZERO)
s_ready_t <= 1'b1;
else if (state == ONE && next == TWO)
s_ready_t <= 1'b0;
else if (state == TWO && next == ONE)
s_ready_t <= 1'b1;
end
// state
always @(posedge sclk) begin
if (~reset_n)
state <= ZERO;
else
state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready)
next = ONE;
else
next = ZERO;
ONE:
if (~s_valid & m_ready)
next = ZERO;
else if (s_valid & ~m_ready)
next = TWO;
else
next = ONE;
TWO:
if (m_ready)
next = ONE;
else
next = TWO;
default:
next = ZERO;
endcase
end
endmodule/*}}}*/
// vim:ts=4 sw=4 et fdm=marker:
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